СПОСОБ ПРОИЗВОДСТВА ПОДЛОЖКИ НА ОСНОВЕ КАРБИДА КРЕМНИЯ И ПОДЛОЖКА КАРБИДА КРЕМНИЯ

Изобретение относится к технологии получения подложки из поликристаллического карбида кремния. Способ состоит из этапов предоставления покрывающих слоев 1b, каждый из которых содержит оксид кремния, нитрид кремния, карбонитрид кремния или силицид металла, выбранного из группы, состоящей из никеля, кобальта, молибдена и вольфрама, или покрывающих слоев, каждый из которых изготовлен из фосфоросиликатного стекла (PSG) или борофосфоросиликатного стекла (BPSG), имеющего свойства текучести допированного P2O5или B2O3и P2O5,на обеих поверхностях основной подложки 1a, изготовленной из углерода, кремния или карбида кремния для подготовки поддерживающей подложки 1, имеющей покрывающие слои, каждый из которых имеет гладкую поверхность; формирования пленок 10 поликристаллического карбида кремния на обеих поверхностях поддерживающей подложки 1 осаждением из газовой фазы или выращиванием из жидкой фазы; и химического удаления, по меньшей мере, покрывающих слоев 1b в поддерживающей подложке для отделения ...

PN-Übergangsdiode aus Diamant und Methode zu deren Herstellung

Verfahren zur Herstellung eines Trench-MOSFET

Bei einem Verfahren zur Herstellung eines Trench-MOSFET werden Gräben in einer monokristallinen Halbleiterschicht erzeugt und die Oberfläche dann zunächst ganzflächig mit einer Streuoxid-Schicht und anschließend mit einer Polysiliziumschicht bedeckt, so dass die Gräben zumindest teilweise mit dem Polysilizium aufgefüllt sind. Die Polysiliziumschicht wird dann bis auf Oberflächen der Halbleiterschicht in den Bereichen zwischen den Gräben planarisiert. Durch eine thermische Oxidation von freiliegenden Oberflächen des Polysiliziums in den Gräben wird eine dicke SiO2-Schicht über dem Polysilizium erzeugt, die als Implantationsmaske für nachfolgende Implantationsschritte dient. Anschließend erfolgen die Ionenimplantationsschritte zur Erzeugung der Source- und Wannen-Gebiete sowie die weiteren Schritte zur Fertigstellung des MOSFET. Das Verfahren ermöglicht die Herstellung von Trench-MOSFETs in SiC ohne das Erfordernis einer Lithographieanlage für die Erzeugung der Source- und Wannen-Gebiete ...

Siliziumcarbid-Halbleitervorrichtung und Verfahren zu deren Fertigung

Eine SiC-Halbleitervorrichtung weist auf: ein Halbleiterschaltelement mit: einem Substrat (1), einer Driftschicht (2) und einem Basisbereich (3), die in dieser Reihenfolge übereinander geschichtet sind; einem Source-Bereich (4) und einem Kontaktbereich (5) im Basisbereich (3); einem Graben (6), der sich von einer Oberfläche des Source-Bereichs (4) erstreckt, um den Basisbereich (3) zu durchdringen; einer Gate-Elektrode (9) auf einem Gate-Isolierfilm (8) im Graben (6); einer Source-Elektrode (11), die elektrisch mit dem Source-Bereich (4) und dem Basisbereich (3) verbunden ist; einer Drain-Elektrode (13) auf einer Rückseite des Substrats (1); und mehreren tiefen Schichten (10) in einem oberen Abschnitt der Driftschicht (2), die tiefer als der Graben (6) reichen. Jede tiefe Schicht (10) weist einen oberen und einen unteren Abschnitt (10b, 10a) auf. Eine Breite des oberen Abschnitts (10b) ist geringer als eine Breite des unteren Abschnitts (10a).

BIPOLARER HETEROUEBERGANGSTRANSISTOR MIT EINEM BASISBEREICH AUS GERMANIUM.

Heterojunction transistor comprises: a GaAs collector region (3) of first type; a Ge base layer (11) of second type; and an SiGe mixed crystal (I) emitter layer (12) of first type. Si content of (I) is pref. 10-40 mol. %; The Si content may be uniform, or graded from zero at the Ge layer interface. GaAs layer is formed on a high impurity concn. GaAs layer of first type (2) to which a collector electrode is contacted; a base electrode (a) contacts the Ge layer; and a high impurity concn. Ge layer of first type (13) is formed on the mixed crystal layer and an emitter contact attached.

Verfahren und Anordnung zum Abschwächen von Kurzkanaleffekten in Siliciumcarbid-MOSFET-Vorrichtungen

Es werden eine Leistungstransistoranordnung und ein Verfahren zum Abschwächen von Kurzkanaleffekten in einer Leistungstransistoranordnung bereitgestellt. Die Leistungstransistoranordnung enthält eine erste Schicht aus Halbleitermaterial, die aus einem Material eines ersten Leitfähigkeitstyps gebildet ist, und eine Hartmaskenschicht, die mindestens einen Abschnitt der ersten Schicht bedeckt und durch die ein Fenster verläuft, das eine Oberfläche der ersten Schicht freilegt. Die Leistungstransistoranordnung schließt auch eine erste Region, die in der ersten Schicht aus Halbleitermaterial eines zweiten Leitfähigkeitstyps gebildet und an dem Fenster ausgerichtet ist, eine oder mehrere Source-Regionen, die aus Material des ersten Leitfähigkeitstyps innerhalb der ersten Region gebildet und durch einen Abschnitt der ersten Region getrennt sind, und eine Verlängerung der ersten Region, die sich seitlich durch die Oberfläche der ersten Schicht erstreckt, ein ...

Power solid state switch of semiconductor switch type

The resistance in the current path of the solid state switch is adjustable by a control voltage at at least one control electrode. To achieve an isolating switch or free switch a material is inserted with an intrinsic conductivity corresponding to a band gap that is greater than 2.5 eV, and which has a breakdown strength of more than 1 kV per 18 micrometres. The material assumes the isolation state for a drive voltage of O V. In one embodiment the material inserted is silicon carbide.

VERFAHREN ZUR GEZIELTEN HERSTELLUNG VON N-LEITENDEN BEREICHEN IN DIAMANTSCHICHTEN MITTELS IONENIMPLANTATION

Mikroelektronisches Bauelement

Nanosheet-Feldeffekttransistor mit einem zweidimensionalen halbleitenden Material

Strukturen für einen Feldeffekttransistor und Verfahren zum Bilden von Strukturen für einen Feldeffekttransistor. In einem Schichtstapel ist eine Mehrzahl von Kanalschichten angeordnet und ein Source/Drain-Bereich ist mit der Vielzahl von Kanalschichten verbunden. Eine Gatestruktur umfasst eine Mehrzahl von Abschnitten, die jeweils die Mehrzahl von Kanalschichten umgeben. Die Mehrzahl von Kanalschichten umfasst ein zweidimensionales halbleitendes Material.

Vertical diamond field effect transistor and method for making same

Thin film conductor

The invention relates to a thin film conductor which has a composition containing silicon and germanium as major components and has a structure in which both amorphous and microcrystalline phases are present, and a method of manufacturing the same by a CVD method. The resultant thin film conductor has characteristics, such as a high dark conductivity, a large gauge factor, a small temperature coefficient of the dark conductivity, a large thermoelectric power, and the like, and is used as a material for microelectronic devices having a sensor function.

Diamond heterojunction diode

A PROCESS FOR THE PRODUCTION OF A MULTI-COMPONENT AMORPHOUS SILICON FILM FOR USE IN SOLAR CELLS

Growing epitaxial 3C-SiC on single-crystal silicon

A method of growing epitaxial 3C-SiC on single-crystal silicon comprising providing a single-crystal silicon substrate 2 in a cold-wall chemical vapour deposition reactor 7, heating the single-crystal silicon substrate to a temperature equal to or greater than 700 °C and equal to or less than 1200 °C, introducing a gas mixture 41 into the cold-wall chemical vapour reactor while the single-crystal silicon substrate is at the temperature, the gas mixture comprising a silicon source precursor 16, a carbon source precursor 18 and a carrier gas 24 so as to deposit an epitaxial layer 4 (see Figure 1) of 3C-SiC on the single-crystal silicon. The carbon source precursor may be an organosilicon compound such as trimethylsilane. The silicon source precursor may comprise a chloride containing silane. The carrier gas may be hydrogen. The single crystal silicon may have a 001 surface orientation. The layer of epitaxial 3C-SiC may be at least 500nm thick.

Method of horizontally growing carbon nanotubes and field effect transistor using the carbon nanotubes grown by the method

Method for manufacturing a graphene thin-film transistor

METHOD FOR FORMING N-TYPE SEMICONDUCTING DIAMOND FILMS BY VAPOR PHASE TECHNIQUES

Porous semiconductor material

Preparation method for graphene thin film transistor

Provided is a preparation method for a graphene thin film transistor, comprising:depositing a graphene layer (22) on the surface of a copper foil (21);depositing a metal layer (23) on the surface of the graphene layer (22);attaching a supporting layer (24) on the surface of the metal layer (23) to form a graphene film sheet;placing the graphene film sheet into a corrosive solution until the copper foil (21) is fully dissolved, transferring the graphene film sheet to a target substrate, and removing the supporting layer (24); anddefining source and drain electrode patterns on the surface of the metal layer (23), preparing the source electrode and the drain electrode, and preparing a gate electrode on the target substrate.

Semiconductor device

Semiconductor device comprising a semiconductor chip containing silicon carbide (main component), incorporating a reference voltage generating circuit (bandgap reference) which includes a diode, Q1-Q3, and a diffusion resistance (resistor) element R2,R1 formed by introducing an acceptor (e.g aluminium, forming p-type resistor) . The diode may comprise an npn bipolar transistor and include n-type (donor e.g Nitrogen) collector and p-type (acceptor e.g Aluminum) base both shorted together 200. The resistance of resistor R2, R1 preferably has a negative temperature coefficient and the activation energy ratio of the acceptor is smaller than that of the donor. The activation ratio temperature dependence of the acceptor may be larger than that of the donor. The device load current at temperature 500 degree C is preferably not less than 20 times that at room temperature. The cathode and anode of the diode may connect with a ground GL, and power-line VL respectively. Further embodiments disclose ...

An electrical conductor

An electrical conductor

An electrical conductor

An electrical conductor

DIAMOND TRANSISTOR AND PROCEDURE FOR ITS PRODUCTION.

CONTROL OF THE BAND GAP IN AMORPHOUS SEMICONDUCTORS.

SEMICONDUCTOR HETEROSTRUCTURE.

A semiconductor device

SURFACE MOUNTABLE OPTOCOUPLER PACKAGE

A method of providing a layer including a metal or silicon or germanium and oxygen on a surface

Graphene-based infrared bolometer

An infrared bolometer. In one embodiment a waveguide configured to transmit infrared radiation is arranged to be adjacent a graphene sheet and configured so that evanescent waves from the waveguide overlap the graphene sheet. The graphene sheet has two contacts connected to an amplifier, and a power detector connected to the amplifier. Infrared electromagnetic power in the evanescent waves is absorbed in the graphene sheet, heating the graphene sheet. The power of Johnson noise generated at the contacts is proportional to the temperature of the graphene sheet. The Johnson noise is amplified and the power in the Johnson noise is used as a measure of the temperature of the graphene sheet, and of the amount of infrared power propagating in the waveguide.

Microelectrodes made from structured diamond for neural interfacing applications

A microelectrode (2) for neural interfacing applications comprises a first substrate layer (4), a second attachment layer (6), and a third layer (8) forming the active part of the electrode (2) of which the material consists of synthetic diamond made electrically conductive by doping with atoms chosen from boron, nitrogen and phosphorus atoms. The material of the third layer (8) is a textured material that comprises a compact assembly, in the form of a brush, of tubes (26) each comprising, in the form of at least one peripheral outer layer, polycrystalline diamond made electrically conductive by doping. The tubes (26) are separated from each other at the first fixed ends (28) of same and project the free ends (30) of same away from the first and second layers (4, 6) in a direction that is substantially vertical relative to the extension plane (20) of the second layer (6). A method for producing said microelectrode is also described.

LARGE SCALE NANOFIBER EXTRUDER

... 1. Large Scale Nanofiber extruder. This device can be used to produce (novel - weakness of current technologies, the fibers they produce are too short) long nanofibers. Among other nanofibers produced we could produce, nano - (metals by melting) copper wires, aluminium, titanium, fiber glass, teflon/resin/rubber/polymer/nanotube/nanoparticles/strategically spread out carbon nanofibers and other such composite. As long as the material is reducible into fluid (or will fit through the extruder hole - ideally even consistency) whether by heat - molten metal or solvent/enzymes/catalysts. You could shred the input material and melt gas torch or plasma torch to a melting temperature of metals and then extrude via a piston or hydraulic press. We can have different sized pistons/hydraulic chambers and different sized extruder heads depending on desired length and diameter of nanofibers/wires and different shaped extruder heads. The extruder (perhaps multiple maybe lined up horizontally - producing ...

METHOD FOR OPTIMIZING PHOTORESPONSIVE AMORPHOUS ALLOYS AND DEVICES

The production of improved photoresponsive amorphous alloys (118, 146, 168, 180, 194, 206, 208, 210, 214, 216, 218, 220) and devices (142, 168, 178, 192, 198, 212), such as photovoltaic, photoreceptive devices and the like; having improved wavelength threshold characteristics is made possible by adding one or more band gap adjusting elements to the alloys (118, 146, 168, 180, 194, 206, 208, 210, 214, 216, 218, 220) and devices (142, 168, 178, 192, 198, 212). The adjusting element or elements are added at least to the active photoresponsive regions (150, 170, 172, 180, 186, 194, 208, 216) of amorphous devices (142, 168, 178, 192, 198, 212) containing silicon and fluorine, and preferably hydrogen. One adjusting element is germanium which narrows the band gap from that of the materials without the adjusting element incorporated therein. Other adjusting elements can be used such as tin. The silicon and adjusting elements are concurrently combined and deposited as amorphous alloys (118, 146, ...

METHOD FOR OPTIMIZING PHOTORESPONSIVE AMORPHOUS ALLOYS AND DEVICES

METHOD FOR GRADING THE BAND GAPS OF AMORPHOUS ALLOYS AND DEVICES

METHOD FOR MAKING PHOTORESPONSIVE AMORPHOUS GERMANIUM ALLOYS AND DEVICES

AN APPARATUS COMPRISING A SENSOR ARRANGEMENT AND ASSOCIATED FABRICATION METHODS

An apparatus comprising: a plurality of sensors (501) arranged in an array (500), each sensor having a source electrode (504), a drain electrode (503), a gate electrode (505) and a channel, wherein the source electrode and drain electrode are elongate and the channel has a channel width defined by the longitudinal extent of the source and/or drain electrode and a channel length defined by the separation between the source and drain electrodes; a common conductive or semiconductive layer (506), which may be made of graphene, comprising the channels of the sensors (501) and arranged to extend over the plurality of sensors of the array and configured to be in electrical contact with at least the source electrode and the drain electrode of each sensor; and wherein the source electrode or drain electrode of each sensor forms a substantially continuous sensor perimeter at least along the channel width, which substantially encloses the other electrode of each sensor to inhibit the flow of charge ...

NITRIDE SEMICONDUCTOR DEVICE HAVING SUPPORT SUBSTRATE AND ITS MANUFACTURING METHOD

The present invention relates to an opposed terminal structure having a supporting substrate having conductivity. A nitride semiconductor having a light-emitting layer is also provided along with a first terminal formed on one face of the nitride semiconductor and a second terminal formed on another face of the nitride semiconductor. The first terminal is formed in a pattern of one of a rectangular shape, a plurality of lines, a square shape, a grid pattern, a plurality of dots, a rhombus, a parallelogram, a mesh shape, a striped shape, and a ramose shape branching from one into a plurality of branches. The thermal expansion coefficient of the supporting substrate is approximately the same as the thermal expansion coefficient of the nitride semiconductor. The supporting substrate is formed of nitride semiconductor.

P-N-P DIAMOND TRANSISTOR

The present invention provides a P-N-P diamond transistor and a method of manufacture thereof. The transistor comprises a diamond substrate having two p-type semiconducting regions separated by an insulating region with an n-type semiconducting layer established by chemical vapour deposition. Preferably the p-type regions are obtained by doping with boron and controlling the concentration of nitrogen impurities by the use of nitrogen getters. The n-type layer preferably contains phosphorus.

POROUS SEMICONDUCTOR MATERIAL

Porous semiconductor material in the form of crystalline silicon (12) is produced with a porosity in exccess of 90 %, and voids, crazing and peeling of the material are substantially by scanning electron microscopy at a magnification of 7,000. The material (12) is prepared by anodization of a silicon wafer (10) to produce porous silicon, followed by etching of the porous silicon to produce pore overlap defining silicon quantum wires. After etching, the porous silicon is dried by supercritical drying. The resulting material has good properties together with good morphology and crystallinity.

ENGINEERED SUBSTRATE STRUCTURE FOR POWER AND RF APPLICATIONS

Manufacturing method of two-dimensional material structure and two-dimensional material device

Field effect transistor of MOS silicon carbide (SiC)

Semiconductor device

Method and device, for manufacturing thin film transistor (TFT)

Novel digital door integrated circuit structure

Microelectronic structure and forming method thereof

Apparatus and method for sensing analytes using graphene channels, quantum dots and electromagnetic radiation

Semiconductor device and method for producing same

Method of fabricating a heterojunction bipolar transistor

Preparation method of self-organizing silicon terminal diamond conductor and device

The invention discloses a preparation method of a self-organizing silicon terminal diamond conductor and device, which comprises the following steps: polishing and cleaning the surface of a diamond single crystal to obtain a treated diamond single crystal; depositing a diamond single crystal by using PECVD to obtain a SiO2 layer; carrying out photoetching on the SiO2 layer through a mask plate; etching the SiO2 layer after photoetching by using RIE (Reactive Ion Etching) to obtain a patterned substrate; mPCVD is adopted to grow a diamond single crystal epitaxial layer, in the cooling process, stress nonuniformity occurs on the epitaxial layer to achieve self-stripping, and a silicon terminal area and a non-silicon terminal area are formed on the stripped epitaxial layer; preparing a source electrode and a drain electrode on two sides in the silicon terminal area; siO2 is deposited in the middle of the silicon terminal area to form a gate medium, a gate electrode is prepared in the middle ...

PHOTOSENSITIVE AMORPHOUS DEVICE HAS MULTIPLE CELLS

PROCESS AND DEVICE TO INCREASE the INTERVAL OF BANDS Of AMORPHOUS ALLOYS PHOTOSENSITIVE AND ALLOYS OBTAINED

Semiconductors, such as bipolar transistors - with amorphous layers locally crystallised by e.g. laser to reduce number of mfg. operations

Semiconductor e.g. silicon, structure fabricating method for e.g. micro electro mechanical systems, involves carrying out thermal treatment of layer to modify crystallinity of layer, and planarizing layer having homogeneous surface

L'invention concerne un procédé de réalisation d'une structure semi-conductrice, comportant une couche superficielle (20'), au moins une couche enterrée (36, 46), et un support (30), ce procédé comportant : - une étape de formation, sur un premier support, de motifs (23) en un premier matériau, - une étape de formation d'une couche semi-conductrice, entre et sur lesdits motifs, - une étape d'assemblage de cette couche semi-conductrice avec un deuxième support (30).

DEVICE HAS SEMICONDUCTOR USING SILICON CARBIDE

L'invention concerne une structure de dispositif à semiconducteur qui possède une couche épitaxiale (12), formé de silicium par exemple, qui est disposé sur une matière à bande interdite élevée (11), par exemple du carbure de silicium, qui est elle-même disposée sur un substrat semiconducteur (10), par exemple du silicium. La matière à bande interdite élevée acquiert une concentration de charge beaucoup plus élevée qu'une matière semiconductrice classique, pour une même tension de claquage.

광원 장치의 제조 방법

... 제 1 기판 상에 2차원 결정 구조를 갖는 전도성 물질을 포함하는 제 1 전극을 형성하는 것, 상기 제 1 전극을 표면 처리하는 것, 상기 제 1 전극 상에 표시 소자층을 형성하는 것, 및 상기 표시 소자층 상에 제 2 전극을 형성하는 것을 포함하는 광원 장치의 제조 방법을 제공하되, 상기 제 1 전극의 표면 처리는 상기 제 1 기판과 상기 제 1 전극 사이의 간극에 유체를 공급하는 것, 및 상기 간극 내의 유체를 증발시켜 상기 제 1 기판과 상기 제 1 전극을 합착하는 것을 포함할 수 있다.

SILICON CARBIDE PRODUCT, METHOD FOR PRODUCING SAME, AND METHOD FOR CLEANING SILICON CARBIDE PRODUCT

마찰전기 자가발전소자 및 그 제조 방법

... 본 발명은 절연층, 전극 및 대전층을 포함하는 간단한 적층 형태의 구조를 이용하여 대전층 및 접촉 물질 간 마찰에 의해 계면에서 전기음성도 차이로부터 발생하는 마찰전하 이동에 따른 전위차를 이용하여 전기 에너지를 발생시키는 인체접합형 마찰전기 자가발전소자 및 그 제조 방법에 관한 것으로서, 낮은 영률과 낮은 질량을 갖는 물질을 이용해 초박막 형태로 제작하여 피부의 굴곡에 맞게 마찰전기 자가발전소자를 변형시킬 수 있다.

반도체 소자 및 그 제조 방법

... 본 발명의 일 실시예에 따른 반도체 소자는 n+형 탄화 규소 기판의 제1면에 위치하는 n-형층, 상기 n-형층에 위치하며 서로 이격되어 있는 제1 트렌치 및 제2 트렌치, 상기 제1 트렌치의 측면 및 상기 제2 트렌치의 측면 사이에 위치하며, 상기 n-형층 위에 위치하는 n+형 영역, 상기 제1 트렌치의 내부에 위치하는 게이트 절연막, 상기 제2 트렌치의 내부에 위치하는 소스 절연막, 상기 게이트 절연막 위에 위치하는 게이트 전극, 상기 게이트 전극 위에 위치하는 산화막, 상기 산화막, 상기 n+형 영역, 및 상기 소스 절연막 위에 위치하는 소스 전극, 그리고 상기 n+형 탄화 규소 기판의 제2면에 위치하는 드레인 전극을 포함한다.

MANUFACTURING METHOD OF TWO-DIMENSIONAL SEMICONDUCTOR

The present invention relates to a manufacturing method of a two-dimensional semiconductor. More specifically, an alkali metal atom is absorbed onto a phosphorene surface by attending to a structural feature of phosphorene to cause a strong electric field effect so as to broadly adjust a phosphorene bandgap by a stark effect. Therefore, a super small electronic component using a two-dimensional semiconductor material can be manufactured wherein the two-dimensional semiconductor material is thin, whose thickness corresponds to only several atoms. COPYRIGHT KIPO 2016 ...

박막, 그 제조 방법, 및 그 제조 장치

... 박막의 제조 장치가 제공된다. 상기 박막의 제조 장치는, 일단 및 타단을 포함하는 튜브(tube), 상기 튜브의 상기 일단에 인접한 제1 영역으로 열을 공급하는 제1 히터(heater), 상기 튜브의 상기 타단에 인접한 제2 영역으로 열을 공급하고, 상기 튜브를 따라 상기 제1 히터와 나란히 배치된 제2 히터, 상기 튜브의 상기 일단으로 소스 가스(source gas)가 공급되는 가스 주입구, 및 상기 튜브의 상기 타단으로부터 상기 소스 가스가 배출되는 가스 배출구를 포함한다.

Manufacturing method of, array substrate and display panel and display panel

Silicene electronic device

그래핀의 하나 이상의 굽힘변형, 위치이동, 중 하나이상 선택되는 것을 구비하여 일 함수를 하나 이상 조절하는 트랜지스터

... 본 발명은 그래핀의 하나 이상의 굽힘변형, 위치이동, 중 하나 이상 선택되는 것을 구비하여 하나 이상의 일 함수를 하나 이상 조절하는 트랜지스터에 관한 것으로, 그래핀의 하나 이상의 굽힘변형, 위치이동, 중 하나 이상 선택되는 것을 구비하여, 하나 이상의 쇼키장벽(Schottky Barrier)의 높이를 하나 이상 조절, Fermi level(페르미레벨)의 높이를 하나 이상 조절, 중 하나 이상 선택되는 것을 하나 이상의 Piezo(피에조) 물질, 자성입자, 전하를 갖는입자 또는 전하를 띠는 입자, 중 하나 이상 선택되는 것을 그래핀의 하단부에 하나 이상 구비하여 교차되는 장벽조정회로의 정전기적 준위로 인하여 하나 이상의 Piezo(피에조) 물질, 자성입자, 전하를갖는입자 또는 전하를 띠는 입자, 중 하나 이상 선택되는 것이 그래핀을 하나 이상 굽힘변형, 위치이동 중 하나 이상 선택되는 것으로 Work function(일함수)을 하나 이상 조절하는 트랜지스터를 제공한다. 또한, 본 발명은 그래핀의 하나 이상의 굽힘변형, 위치이동, 중 하나 이상 선택되는 것을 구비하여 하나 이상의 일 함수를 하나 이상 조절하는 트랜지스터에 관한 것으로, 그래핀의 하나 이상의 굽힘변형, 위치이동, 중 하나 이상 선택되는 것을 구비하여, 하나 이상의 쇼키장벽(Schottky Barrier)의 높이를 하나 이상 조절, Fermi level(페르미레벨)의 높이를 하나 이상 조절, 중 하나 이상 선택되는 것을 교차되는 장벽조정회로의 정전기적 준위로 인하여 그래핀을 하나 이상 굽힘변형, 위치이동 중 하나 이상 선택되는 것으로 Work function(일함수)을 하나 이상 조절하는 트랜지스터를 제공한다.

SEMICONDUCTOR DEVICE INCLUDING TWO-DIMENSIONAL MATERIAL AND MANUFACTURING METHOD THEREOF

According to the present invention, disclosed are a semiconductor device including a two-dimensional (2D) material and a manufacturing method thereof, to provide a semiconductor device having a controlled energy band structure. The semiconductor device is a photoelectric device including at least one doped 2D material. The photoelectric device includes a semiconductor layer between a first electrode and a second electrode, and At least one of the first and second electrodes includes doped graphene. The semiconductor layer has internal potential of about 0.1 eV or more, or about 0.3 eV or less. One of the first and second electrodes includes p-doped graphene. The other electrode includes n-doped graphene. Otherwise, one of the first and second electrodes includes p-doped or n-doped graphene. The other electrode includes a metallic material. COPYRIGHT KIPO 2016 ...

SIC MOSFET DEVICE FOR DECREASING ELECTRIC FIELD OF BOTTOM OXIDE LAYER AND METHOD FOR MANUFACTURING SAME

The present invention relates to a silicon carbide (SiC) MOSFET device for decreasing an electric field of a bottom oxide layer and a method for manufacturing the same. The SiC MOSFET device includes a first conductive SiC substrate, a first conductive epitaxial layer grown on the first conductive SiC substrate, a second conductive body layer deposited on the first conductive epitaxial substrate, a first trench structure passing through the second conductive body layer, and formed through partial etching to the first conductive epitaxial layer, a trench bottom layer formed on a bottom surface of the first trench structure, a gate electrode deposited to surround an internal side of the first trench structure including the trench bottom layer, a source electrode deposited on an upper end of the second conductive body layer except the first trench structure; and a drain electrode deposited on a lower end of the first conductive SiC substrate. The trench bottom layer is made of a high K material ...

FABRICATING A GALLIUM NITRIDE LAYER WITH DIAMOND LAYERS

METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE

THERMOCONDUCTIVE ELECTROMAGNETIC WAVE SHIELDING PAINT FOR SEMICONDUCTORS CONSISTING OF COPPER, NICKEL, CNT, AND GRAPHENE

The present invention relates to thermoconductive electromagnetic wave shielding paint for semiconductors, consisting of copper, nickel, carbon nanotube (CNT), and graphene. The thermoconductive electromagnetic wave shielding paint for semiconductors consists of: nickel coated on a surface of copper powder; CNT grown on the surface of nickel; and graphene synthesized on the CNT-grown copper powder. When the coating paint produced thereby is coated on a radiant body of semiconductors, effective heat emission taking place in semiconductor devices is possible, electromagnetic interference (EMI) is reduced, and shields off electromagnetic wave, thereby extending lifespan of electronic devices. COPYRIGHT KIPO 2017 ...

POLYMER THIN FILM FOR MANUFACTURING FREE-STANDING NANO-THIN FILM AND METHOD FOR MANUFACTURING NANO-THIN FILM USING SAME

The present invention relates to a polymer thin film for manufacturing a free-standing nano-thin film and a method for manufacturing the nano-thin film using the same. More particularly, the present invention relates to a polymer thin film for manufacturing a free-standing EUV pellicle obtained by forming a polymer thin film by plasma polymerization using monomers containing benzene as a basic structure and being separated in a solvent phase, and a method for manufacturing an EUV pellicle using the same. Therefore, the polymer thin film for manufacturing the free-standing EUV pellicle of the present invention can easily produce an atomically uniform thin film having a thin thickness, so that an EUV pellicle having a high transmittance can be manufactured and can be mass-produced industrially. COPYRIGHT KIPO 2018 ...

강화 박막 필름 장치

... 본 발명은 강화 박막 장치(100, 200, 500)에 관한 것으로, 에피레이어(Epilayer)를 지지하기 위한 상부 표면을 가지는 기판(101); 상기 기판(101) 상에 배치되어 니들 패드(Needle Pad)를 형성하는 복수의 나노 사이즈의 캐비티(Cavity)로 패턴화되어 있는 마스크 레이어(103); 상기 마스크 레이어(103) 상에 배치된 격자 부정합 반도체(Lattice-mismatched Semiconductor)의 박막(105) - 상기 박막(105)은 이에 내장된 상기 격자 부정합 반도체의 복수의 병렬 이격된 반도체 니들을 포함하고, 상기 복수의 반도체 니들은 상기 마스크 레이어(103)의 상기 복수의 나노 사이즈의 캐비티 내에 상기 기판(101)을 향해 축 방향으로 실질적으로 수직으로 배치됨 -; 및 자신에 의해 지지되는 상기 박막 상에 제공되는 격자 부정합 반도체 에피레이어(106)를 포함한다.

Vertical sic mosfet

SETT ATT FRAMSTELLA EN FOTOKENSLIG AMORF LEGERING, LEGERING TILLVERKAD ENLIGT SETTET SAMT FOTKENSLIGT DON

METHOD OF PREPARING A POWER ELECTRONIC DEVICE

A method of forming an electronic device, such as a power electronic device comprising a silicon carbide lamina, is disclosed. Various embodiments of this method are specifically described, leading to the preparation of electronic device precursor and fabrication of electronic devices.

FIELD-EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREFOR

Provided are a field effect transistor and a manufacturing method therefor. The method comprising: depositing a first insulation layer on a substrate (S11); forming a source electrode and a drain electrode on the first insulation layer (S12); forming a carbon quantum dot active layer covering the source electrode and the drain electrode (S13); and successively forming a second insulation layer and a gate electrode on the carbon quantum dot active layer (S14). By means of the method, a carbon quantum dot material is used to manufacture an active layer in a field-effect transistor, such that the manufacturing material for the field-effect transistor is enriched, the environmental pollution created when a metal point film layer is used to manufacture the active layer in the art is reduced, and the dependency on metal elements is reduced at the same time.

TRANSISTOR FOR ADJUSTING AT LEAST ONE OF AT LEAST ONE WORK FUNCTION USING AT LEAST ONE SELECTED FROM AMONG POSITION MOVEMENT AND BENDING DEFORMATION OF GRAPHENE

SEMICONDUCTOR ARRANGEMENT WITH A PIN DIODE

A semiconductor arrangement with a PIN diode is proposed, comprising a heavily n-doped layer (1), a lightly n-doped layer (2) arranged on the heavily n-doped layer (1) and a p-doped layer (3) arranged on the lightly n-doped layer (2), wherein the p-doped layer (3) forms an ohmic contact with a first metallization (5) and the heavily n-doped layer (1) forms an ohmic contact with a second metallization (7). During operation in the forward direction, a high injection takes place, in which the lightly n-doped layer (2) is flooded with charge carriers. At least two trench structures (4) are incorporated in the lightly n-doped layer (2), wherein the trench structures (4) have a dielectric layer (6) on a surface that is in contact with the n-doped surface. The surface (10) of the lightly n-doped layer (2) that is in contact with the dielectric layer (6) has an increased surface recombination velocity for charge carriers.

BURIED GRID WITH SHIELD IN A WIDE BAND GAP MATERIAL

There is disclosed a structure in a wide band gap material such as silicon carbide wherein there is a buried grid and shields covering at least one middle point between two adjacent parts of the buried grid, when viewed from above. Advantages of the invention include easy manufacture without extra lithographic steps compared with standard manufacturing process, an improved trade-off between the current conduction and voltage blocking characteristics of a JBSD comprising the structure.

SELF ALIGNED CARBIDE SOURCE/DRAIN FET

A field effect transistor includes a metal carbide source portion, a metal carbide drain portion, an insulating carbon portion separating the metal carbide source portion from the metal carbide drain portion, a nanostructure formed over the insulating carbon portion and connecting the metal carbide source portion to the metal carbide drain portion, and a gate stack formed over at least a portion of the insulating carbon portion and at least a portion of the nanostructure.

CONNECTION COMPONENT FOR A BRANCH FOR INDIVIDUAL ELECTRON MOTION

The invention relates to an electronic component (10) which is formed by a semiconductor component or a semiconductor-like structure with gate electrode arrangements (16, 18, 20) for the transport of a quantum dot (52). The electronic component (10) contains a substrate (12) comprising a two-dimensional electron gas or electron hole gas. Electrical contacts connect the gate electrode arrangements (16, 18, 20) to voltage sources. A first gate electrode arrangement (16) having gate electrodes (22, 24) is provided on a surface (14) of the electronic component in order to create a potential well (50) in the substrate (12). The gate electrode arrangement (16) has parallel electrode fingers (32, 34), said electrode fingers (32, 34) being alternately connected together at intervals which causes almost continuous transport of the potential well (50) through the substrate (12), a quantum dot (52) being translated together with this potential well (50) in one direction.

SEMI-METAL RECTIFYING JUNCTION

A rectifying junction (15) is formed in a conduction path provided in a material (1). A size of the material (1) is smaller than a threshold size in a first dimension, the threshold size being the size required for the material (1) to exhibit sufficient quantum confinement such that it forms a semiconductor. A surface of a first region (17) of the material (1) is arranged to decrease the bandgap of the material such that the first region is conducting. A surface of a second region (19) of the material (1) is arranged to preserve a bandgap such that the second region is semiconducting. The second region (19) is contiguous to the first region (17), such that a rectifying junction (15) is formed at a boundary (21) between the first region and the second region.

INTEGRATED ASSEMBLIES HAVING POLYCRYSTALLINE FIRST SEMICONDUCTOR MATERIAL ADJACENT CONDUCTIVELY-DOPED SECOND SEMICONDUCTOR MATERIAL

Some embodiments include an integrated assembly having a polycrystalline first semiconductor material, and having a second semiconductor material directly adjacent to the polycrystalline first semiconductor material. The second semiconductor material is of a different composition than the polycrystalline first semiconductor material. A conductivity-enhancing dopant is within the second semiconductor material. The conductivity-enhancing dopant is a neutral-type dopant relative to the polycrystalline first semiconductor material. An electrical gate is adjacent to a region of the polycrystalline first semiconductor material and is configured to induce an electric field within said region of the polycrystalline first semiconductor material. The gate is not adjacent to the second semiconductor material.

VERTICAL POWER TRANSISTOR WITH HETEROJUNCTIONS

A vertical power transistor (100) having a semiconductor substrate (101), on which are arranged at least a first layer (102) and a second layer (108), wherein the second layer (108) is arranged on the first layer (102) and the first layer (102) has a first semiconductor material, and having a multiplicity of trenches (103), which extend into the first layer (102) from an upper side of the second layer (108), each trench base therefore being enclosed by the first layer (102), characterized in that the first layer (102) has a first doping and each trench has a first region (112), which extends from the respective trench base up to a first height, wherein each first region (112) is filled with a second semiconductor material (113), which has a second doping, wherein the first semiconductor material and the second semiconductor material (113) are different, wherein each first region (112) is connected electrically to the second layer (108) and the second doping is higher than the first doping ...

A METHOD FOR FORMING APPARATUS COMPRISING TWO DIMENSIONAL MATERIAL

A method and apparatus, the method comprising: forming at least two electrodes (23) on a release layer wherein the at least two electrodes are configured to enable a layer of two dimensional material (25) to be provided between the at least two electrodes; providing mouldable polymer (27) overlaying the at least two electrodes; wherein the at least two electrodes and the mouldable polymer form at least part of a planar surface (29).

PROCESS FOR PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

A process for producing a semiconductor device includes: forming an SiC epitaxial layer on an SiC substrate; implanting the epitaxial layer with ions; forming a gettering layer having a higher defect density than a defect density of the SiC substrate; and carrying out a heat treatment on the epitaxial layer. The semiconductor device includes an SiC substrate, an SiC epitaxial layer formed on the SiC substrate, and a gettering layer having a higher defect density than a defect density of the SiC substrate.

SIC BIPOLAR JUNCTION TRANSISTOR WITH REDUCED CARRIER LIFETIME IN COLLECTOR AND A DEFECT TERMINATION LAYER

A method of manufacturing a silicon carbide (SiC) bipolar junction transistor (BJT) and a SiC BJT (100) are provided. The SiC BJT comprises an emitter region (150), a base region (140) and a collector region (120). The collector region is arranged on a substrate (110) having an off-axis orientation of about 8 degrees or lower. A defect termination layer (DTL, 130) for terminating dislocations originating from the substrate is arranged between the substrate and the collector region. The collector region includes a zone (125) in which the life time of the minority charge carriers is shorter than in the base region. The present invention is advantageous in terms of improved stability of the SiC BJTs.

METHOD FOR MANUFACTURING META-STRUCTURE HAVING SLOT

One embodiment of the present invention provides a method for manufacturing a meta-structure having a slot, the method being capable of manufacturing a precise slot, wherein the method for manufacturing a meta-structure having a slot sequentially provides, on the upper surface of a flexible base substrate, a plate-shaped structure layer having a first critical strain and a brittle layer having a second critical strain that is less than the first critical strain, applies tensile force to the base substrate so that a strain less than the first critical strain and greater than the second critical strain is generated, thereby generating a crack in the brittle layer and the plate-shaped structure layer, etches the upper part of the base substrate in the crack so as to produce a recessed slot on the base substrate, attaches an adhesive film onto the upper surface of the brittle layer, moves the adhesive film so as to peel the plate-shaped structure layer off from the base substrate, and provides ...

SIC DEVICES WITH HIGH BLOCKING VOLTAGE TERMINATED BY A NEGATIVE BEVEL

A negative bevel edge termination for a Silicon Carbide (SiC) semiconductor device is disclosed. In one embodiment, the negative bevel edge termination includes multiple steps that approximate a smooth negative bevel edge termination at a desired slope. More specifically, in one embodiment, the negative bevel edge termination includes at least five steps, at least ten steps, or at least 15 steps. The desired slope is, in one embodiment, less than or equal to fifteen degrees. In one embodiment, the negative bevel edge termination results in a blocking voltage for the semiconductor device of at least 10 kilovolts (kV) or at least 12 kV. The semiconductor device is preferably, but not necessarily, a thyristor such as a power thyristor, a Bipolar Junction Transistor (BJT), an Insulated Gate Bipolar Transistor (IGBT), a U-channel Metal-Oxide-Semiconductor Field Effect Transistor (UMOSFET), or a PIN diode.

SILICON CARBIDE PRODUCT, METHOD FOR PRODUCING SAME, AND METHOD FOR CLEANING SILICON CARBIDE PRODUCT

A silicon carbide product is disclosed which is characterized by having a surface with a metal impurity concentration of not more than 1 × 1011 (atoms/cm2). Also disclosed are a method for producing such a silicon carbide product and a method for cleaning a silicon carbide product. A silicon carbide having such a highly cleaned surface can be obtained by cleaning it with a hydrofluoric acid, a hydrochloric acid, or an aqueous solution containing a sulfuric acid and a hydrogen peroxide solution. The present invention provides a highly cleaned silicon carbide, and thus enables to produce a semiconductor device which is free from consideration on deterioration in characteristics caused by impurities. Further, when the silicon carbide is used in a unit for semiconductor production or the like, there is such an advantage that an object processed in the unit can be prevented from suffering an adverse affect of flying impurities.

VERTICAL SIC SEMICONDUCTOR DEVICE WITH IMPROVED RUGGEDNESS

A vertical semiconductor device includes one or more of a substrate, a buffer layer over the substrate, one or more drift layers over the buffer layer, and a spreading layer over the one or more drift layers.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device may be provided. The semiconductor device may include a sub-channel layer located over a conductive layer. The semiconductor device may include a hole source layer interposed between the conductive layer and the sub-channel layer. The semiconductor device may include source select lines located over the sub-channel layer. The semiconductor device may include source channel layers contacting the sub-channel layer by penetrating the source select lines.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

According to one embodiment, a semiconductor device includes a first, a second, a third, a fourth, and a fifth semiconductor region, an insulating film, a control electrode, and a first and a second electrode. The first, the second, the third, the fourth and the fifth semiconductor region include silicon carbide. The first semiconductor region has a first impurity concentration, and has a first portion. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on the second semiconductor region. The fourth semiconductor region is provided between the first portion and the second semiconductor region. The fourth semiconductor region is provided between the first portion and the third semiconductor region. The fifth semiconductor region includes a first region provided between the first portion and the second semiconductor region, and has a second impurity concentration higher than the first impurity concentration.

Transistor with asymmetric silicon germanium source region

The present invention is directed to a transistor with an asymmetric silicon germanium source region, and various methods of making same. In one illustrative embodiment, the transistor includes a gate electrode formed above a semiconducting substrate comprised of silicon, a doped source region comprising a region of epitaxially grown silicon that is doped with germanium formed in the semiconducting substrate and a doped drain region formed in the semiconducting substrate.

FinFET with novel body contact for multiple Vt applications

FinFET devices are formed with body contact structures enabling the fabrication of such devices having different gate threshold voltages (Vt). A body contact layer is formed to contact the gate electrode (contact) enabling a forward body bias and a reduction in Vt. Two example methods of fabrication (and resulting structures) are provided. In one method, the gate electrode (silicon-based) and body contact layer (silicon) are connected by growing epitaxy which merges the two structures forming electrical contact. In another method, a via is formed that intersects with the gate electrode (suitable conductive material) and body contact layer and is filled with conductive material to electrically connect the two structures. As a result, various FinFETs with different Vt can be fabricated for different applications.

Semiconductor device with side-junction and method for fabricating the same

A method for fabricating a semiconductor device includes forming a plurality of bodies that are each isolated from another by a trench and each include a diffusion barrier region with a sidewall exposed to the trench, forming a doped layer gap-filling the trench, forming a sidewall junction at the exposed sidewall of the diffusion barrier region by annealing the doped layer, and forming a conductive line coupled with the sidewall junction to fill the trench.

Semiconductor wafer, semiconductor device and method of fabricating the same

A semiconductor substrate according to an embodiment includes: a first semiconductor wafer having a first crystal; and a second semiconductor wafer formed of a second crystal substantially same as the first crystal on the first semiconductor wafer, a crystal-axis direction of unit cell thereof being twisted at a predetermined angle around a direction vertical to a principal surface of the second semiconductor wafer from that of the first semiconductor wafer.

Method for manufacturing silicon carbide semiconductor device

In a silicon carbide MOSFET, interface state generated at an interface between a silicon carbide layer and a gate insulating film cannot be reduced sufficiently, and mobility of a carrier is decreased. To solve this problem, a silicon carbide semiconductor device according to this invention includes a substrate introduction step of introducing a substrate, which includes a silicon carbide layer on which a gate insulating film is formed, in a furnace, and a heating step of heating the furnace having the substrate introduced therein while introducing nitrogen monoxide and nitrogen therein, wherein, in the heating step, nitrogen is reacted to nitride an interface between the gate insulating film and the silicon carbide layer.

Methods of manufacturing semiconductor devices

A semiconductor device and a method of manufacturing a semiconductor device are provided. In a method of manufacturing a semiconductor device, a gate structure is formed on a substrate. An epitaxial layer is formed on a top surface of the substrate adjacent to the gate structure. An elevated source/drain (ESD) layer and an impurity region are formed by implanting impurities and carbon in the epitaxial layer and an upper portion of the substrate using the gate structure as an ion implantation mask. A metal silicide layer is formed on the ESD layer.

INTEGRATED METHOD FOR FORMING METAL GATE FinFET DEVICES

Provided is a high-k metal gate structure formed over a semiconductor fin. A nitride layer is formed over the gate structure and the semiconductor fin, using two separate deposition operations, the first forming a very thin nitride film. Implantation operations may be carried out in between the two nitride film deposition operations. The first nitride film may be SiN x or SiCN x and the second nitride film is SiCN x . The nitride films may be combined to form low wet etch rate spacers enabling further processing operations to be carried out without damaging underlying structures and without requiring the formation of further dummy spacers. Further processing operations include epitaxial silicon/SiGe processing sequences and source/drain implanting operations carried out with the low etch rate spacers intact.

Finfet semiconductor device

The present disclosure provides a FinFET element. The FinFET element includes a germanium-FinFET element (e.g., a multi-gate device including a Ge-fin). In one embodiment, device includes a fin having a first portion including Ge and a second portion, underlying the first portion and including an insulating material (e.g., silicon dioxide). A gate structure may be formed on the fin.

Strain Engineering in Three-Dimensional Transistors Based on a Strained Channel Semiconductor Material

In three-dimensional transistor configurations, such as finFETs, at least one surface of the semiconductor fin may be provided with a strained semiconductor material, which may thus have a pronounced uniaxial strain component along the current flow direction. The strained semiconductor material may be provided at any appropriate manufacturing stage, for instance, prior to actually patterning the semiconductor fins and/or after the patterning the semiconductor fins, thereby providing superior performance and flexibility in adjusting the overall characteristics of three-dimensional transistors.

Apparatus and methods for improving parallel conduction in a quantum well device

Embodiments of an apparatus and methods of providing a quantum well device for improved parallel conduction are generally described herein. Other embodiments may be described and claimed.

Graded high germanium compound films for strained semiconductor devices

Embodiments of an apparatus and methods for providing a graded high germanium compound region are generally described herein. Other embodiments may be described and claimed.

Metal semiconductor alloy structure for low contact resistance

Contact via holes are etched in a dielectric material layer overlying a semiconductor layer to expose the topmost surface of the semiconductor layer. The contact via holes are extended into the semiconductor material layer by continuing to etch the semiconductor layer so that a trench having semiconductor sidewalls is formed in the semiconductor material layer. A metal layer is deposited over the dielectric material layer and the sidewalls and bottom surface of the trench. Upon an anneal at an elevated temperature, a metal semiconductor alloy region is formed, which includes a top metal semiconductor alloy portion that includes a cavity therein and a bottom metal semiconductor alloy portion that underlies the cavity and including a horizontal portion. A metal contact via is formed within the cavity so that the top metal semiconductor alloy portion laterally surrounds a bottom portion of a bottom portion of the metal contact via.

Shallow pn junction formed by in situ doping during selective growth of an embedded semiconductor alloy by a cyclic growth/etch deposition process

A silicon/carbon alloy may be formed in drain and source regions, wherein another portion may be provided as an in situ doped material with a reduced offset with respect to the gate electrode material. For this purpose, in one illustrative embodiment, a cyclic epitaxial growth process including a plurality of growth/etch cycles may be used at low temperatures in an ultra-high vacuum ambient, thereby obtaining a substantially bottom to top fill behavior.

Semiconductor device and semiconductor device manufacturing method

The invention provides an ultra-low-on-resistance, excellent-reliability semiconductor device that can finely be processed using SiC and a semiconductor device producing method. A semiconductor device includes: a silicon carbide substrate; a first-conductive-type first silicon carbide layer provided on a first principal surface of the silicon carbide substrate; a second-conductive-type first silicon carbide region formed at a surface of the first silicon carbide layer; a first-conductive-type second silicon carbide region formed at a surface of the first silicon carbide region; a second-conductive-type third silicon carbide region formed below the second silicon carbide region; a trench piercing through the second silicon carbide region to reach the third silicon carbide region; a gate insulating film; a gate electrode; an interlayer insulating film with which the gate electrode is covered; a first electrode that is formed on the second silicon carbide region and the interlayer insulating film in a side surface of the trench while containing a metallic element selected from a group consisting of Ni, Ti, Ta, Mo, and W; a second electrode that is formed on the third silicon carbide region in a bottom portion of the trench and the first electrode while containing Al; a first main electrode formed on the second electrode; and a second main electrode formed on a second principal surface of the silicon carbide substrate.

Sea-of-fins structure on a semiconductor substrate and method of fabrication

A semiconductor device and a method of fabricating a semiconductor device, wherein the method comprises forming, on a substrate, a plurality of planarized fin bodies to be used for customized fin field effect transistor (FinFET) device formation; forming a nitride spacer around each of the plurality of fin bodies; forming an isolation region in between each of the fin bodies; and coating the plurality of fin bodies, the nitride spacers, and the isolation regions with a protective film. The fabricated semiconductor device is used in customized applications as a customized semiconductor device.

Methods of forming memory cells, memory cells, and semiconductor devices

A memory device and method of making the memory device. Memory device may include a storage transistor at a surface of a substrate. The storage transistor comprises a body portion between first and second source/drain regions, wherein the source/drain regions are regions of a first conductivity type. The storage transistor also comprises a gate structure that wraps at least partially around the body portion in at least two spatial planes. A bit line is connected to the first source/drain region and a word line is connected to the gate structure.

Method and structure for forming high-k/metal gate extremely thin semiconductor on insulator device

A semiconductor device is provided that includes a gate structure present on a substrate. The gate structure includes a gate conductor with an undercut region in sidewalls of a first portion of the gate conductor, wherein a second portion of the gate conductor is present over the first portion of the gate conductor and includes a protruding portion over the undercut region. A spacer is adjacent to sidewalls of the gate structure, wherein the spacer includes an extending portion filling the undercut region. A raised source region and a raised drain region is present adjacent to the spacers. The raised source region and the raised drain region are separated from the gate conductor by the extending portion of the spacers.

Ultra-thin body transistor and method for manufcturing the same

An ultra-thin body transistor and a method for manufacturing an ultra-thin body transistor are disclosed. The ultra-thin body transistor comprises: a semiconductor substrate; a gate structure on the semiconductor substrate; and a source region and a drain region in the semiconductor substrate and on either side of the gate structure; in which the gate structure comprises a gate dielectric layer, a gate embedded in the gate dielectric layer, and a spacer on both sides of the gate; the ultra-thin body transistor further comprises: a body region and a buried insulated region located sequentially under the gate structure and in a well region; two ends of the body region and the buried insulated region are connected with the source region and the drain region respectively; and the body region is isolated from other regions in the well region by the buried insulated region under the body region. The ultra-thin body transistor has a thinner body region, which decreases the short channel effect. In the method for manufacturing an ultra-thin body transistor together with the replacement-gate process, the forming of the buried insulated region is self-aligned with the gate, which reduces the parasitic resistance under the spacer.

Method for Forming a Semiconductor Device, and a Semiconductor with an Integrated Poly-Diode

A method for forming a field effect power semiconductor is provided. The method includes providing a semiconductor body, a conductive region arranged next to a main surface of the semiconductor body, and an insulating layer arranged on the main horizontal surface. A narrow trench is etched through the insulating layer to expose the conductive region. A polycrystalline semiconductor layer is deposited and a vertical poly-diode structure is formed. The polycrystalline semiconductor layer has a minimum vertical thickness of at least half of the maximum horizontal extension of the narrow trench. A polycrystalline region which forms at least a part of a vertical poly-diode structure is formed in the narrow trench by maskless back-etching of the polycrystalline semiconductor layer. Further, a semiconductor device with a trench poly-diode is provided.

Integrated electronic device and method for manufacturing thereof

An embodiment of an integrated electronic device formed in a body of semiconductor material, which includes: a substrate of a first semiconductor material, the first semiconductor material having a first bandgap; a first epitaxial region of a second semiconductor material and having a first type of conductivity, which overlies the substrate and defines a first surface, the second semiconductor material having a second bandgap wider than the first bandgap; and a second epitaxial region of the first semiconductor material, which overlies, and is in direct contact with, the first epitaxial region. The first epitaxial region includes a first buffer layer, which overlies the substrate, and a drift layer, which overlies the first buffer layer and defines the first surface, the first buffer layer and the drift layer having different doping levels.

Semiconductor device

A JFET, which is a semiconductor device allowing for reduced manufacturing cost, includes: a silicon carbide substrate; an active layer made of single-crystal silicon carbide and disposed on one main surface of the silicon carbide substrate; a source electrode disposed on the active layer; and a drain electrode formed on the active layer and separated from the source electrode. The silicon carbide substrate includes: a base layer made of single-crystal silicon carbide, and a SiC layer made of single-crystal silicon carbide and disposed on the base layer. The SiC layer has a defect density smaller than that of the base layer.

Transistor devices and methods of making

In an embodiment, a method of fabricating a transistor device comprises: providing a semiconductor topography comprising a gate conductor disposed above a semiconductor substrate between a pair of dielectric spacers; anisotropically etching exposed regions of the semiconductor substrate on opposite sides of the dielectric spacers to form recessed regions in the substrate; oxidizing exposed surfaces of the substrate in the recessed regions to form an oxide thereon; removing the oxide from bottoms of the recessed regions while retaining the oxide upon sidewalls of the recessed regions; and isotropically etching the substrate such that the recessed regions undercut the pair of dielectric spacers.

Lateral Uniformity in Silicon Recess Etch

A method of etching recesses into silicon prior to formation of embedded silicon alloy source/drain regions. The recess etch includes a plasma etch component, using an etch chemistry of a primary fluorine-based or chlorine-based etchant, in combination with a similar concentration of hydrogen bromide. The concentration of both the primary etchant and the hydrogen bromide is relatively low; a diluent of an inert gas or oxygen is added to the reactive species. Loading effects on the undercut of the recess etch are greatly reduced, resulting in reduced transistor performance variation.

Structure and method for increasing strain in a device

A method and structure are disclosed for increasing strain in a device, specifically an n-type field effect transistor (NFET) complementary metal-oxide-semiconductor (CMOS) device. Embodiments of this invention include growing an epitaxial layer, performing a cold carbon or cluster carbon pre-amorphization implantation to implant substitutional carbon into the epitaxial layer, forming a tensile cap over the epitaxial layer, and then annealing to recrystallize the amorphous layer to create a stress memorization technique (SMT) effect. The epitaxial layer will therefore include substitutional carbon and have a memorized tensile stress induced by the SMT. Embodiments of this invention can also include a lower epitaxial layer under the epitaxial layer, the lower epitaxial layer comprising for example, a silicon carbon phosphorous (SiCP) layer.

Semiconductor Device

A method for fabricating a semiconductor device comprises forming a partial-insulated substrate comprising an insulating region located below both a channel region of a cell transistor and one of a storage node contact region and a bit line contact region, and forming a cell transistor comprising a fin region on the partial-insulated substrate.

Silicon carbide substrate, epitaxial wafer and manufacturing method of silicon carbide substrate

An SiC substrate includes the steps of preparing a base substrate having a main surface and made of SiC, washing the main surface using a first alkaline solution, and washing the main surface using a second alkaline solution after the step of washing with the first alkaline solution. The SiC substrate has the main surface, and an average of residues on the main surface are equal to or larger than 0.2 and smaller than 200 in number.

Semiconductor device and method of forming the same

A semiconductor device includes a semiconductor substrate, a gate electrode, a dummy gate electrode, and a first impurity diffusion region. The semiconductor substrate has first and second grooves. The gate electrode is in the first groove. The dummy gate electrode is in the second groove. The dummy gate electrode has a first top surface. The first impurity diffusion region in the semiconductor substrate is positioned between the first and second grooves. The first top surface is positioned at a lower level than a bottom of the first impurity diffusion region.

Fet structures with trench implantation to improve back channel leakage and body resistance

An FET structure on a semiconductor substrate which includes forming recesses for a source and a drain of the gate structure on a semiconductor substrate, halo implanting regions through the bottom of the source and drain recesses, the halo implanted regions being underneath the gate stack, implanting junction butting at the bottom of the source and drain recesses, and filling the source and drain recesses with a doped epitaxial material. In exemplary embodiments, the semiconductor substrate is a semiconductor on insulator substrate including a semiconductor layer on a buried oxide layer. In exemplary embodiments, the junction butting and halo implanted regions are in contact with the buried oxide layer. In other exemplary embodiments, there is no junction butting. In exemplary embodiments, halo implants implanted to a lower part of the FET body underneath the gate structure provide higher doping level in lower part of the FET body to reduce body resistance, without interfering with FET threshold voltage.

Strained structure of a p-type field effect transistor

In a p-type field effect transistor, a pair of spacers are formed over the top surface of a substrate. A channel recess cavity includes an indentation in the substrate top surface between the pair of spacers. A gate stack has a bottom portion in the channel recess cavity and a top portion extending outside the channel recess cavity. A source/drain (S/D) recess cavity has a bottom surface and sidewalls below the substrate top surface. The S/D recess cavity has a portion extending below the gate stack. A strained material is filled the S/D recess cavity

Method for fabricating mos transistors

A method for fabricating a MOS transistor is disclosed. First, a semiconductor substrate having a gate thereon is provided. A spacer is then formed on the sidewall of the gate, and two recesses are formed adjacent to the spacer and within the semiconductor substrate. Next, the spacer is thinned, and epitaxial layer is grown in each of the two recesses. By thinning the spacer before the epitaxial layer is formed, the present invention could stop the epitaxial layer to grow against the sidewall of the spacer, thereby preventing problem such as Ion degradation.

Semiconductor integrated circuit device and a method of fabricating the same

A method of fabricating a semiconductor integrated circuit includes forming a first dielectric layer on a semiconductor substrate, patterning the first dielectric layer to form a first patterned dielectric layer, forming a non-single crystal seed layer on the first patterned dielectric layer, removing a portion of the seed layer to form a patterned seed layer, forming a second dielectric layer on the first patterned dielectric layer and the patterned seed layer, removing portions of the second dielectric layer to form a second patterned dielectric layer, irradiating the patterned seed layer to single-crystallize the patterned seed layer, removing portions of the first patterned dielectric layer and the second patterned dielectric layer such that the single-crystallized seed layer protrudes in the vertical direction with respect to the first and/or the second patterned dielectric layer, and forming a gate electrode in contact with the single-crystal active pattern.

Semiconductor device and a method for manufacturing a semiconductor device

A semiconductor device of the present invention has a (110)-plane-orientation silicon substrate and a p channel type field effect transistor formed in a pMIS region. The p channel type field effect transistor includes a gate electrode disposed via a gate insulation film, and source/drain regions disposed inside a trench disposed in the silicon substrate on the opposite sides of the gate electrode, and including SiGe larger in lattice constant than Si. The trench has a (100)-plane-orientation first inclined surface, and a (100)-plane-orientation second inclined surface crossing the first inclined surface at a sidewall part situated on the gate electrode side. With the configuration, the angle formed between the surface (110) plane and the (100) plane of the substrate is 45°, so that the first inclined surface is formed at a relatively acute angle. This can effectively apply a compressive strain to a channel region of the p channel type MISFET.

Reacted Conductive Gate Electrodes and Methods of Making the Same

A semiconductor device and a method for fabricating a semiconductor device involve a semiconductor layer that includes a first material and a second material. The first and second materials can be silicon and germanium. A contact of the device has a portion proximal to the semiconductor layer and a portion distal to the semiconductor layer. The distal portion includes the first material and the second material. A metal layer formed adjacent to the relaxed semiconductor layer and adjacent to the distal portion of the contact is simultaneously reacted with the relaxed semiconductor layer and with the distal portion of the contact to provide metallic contact material.

Simultaneous formation of finfet and mugfet

A method and structure comprise a field effect transistor structure that includes a first rectangular fin structure position on a substrate. The first rectangular fin structure has a bottom contacting the substrate, a top opposite the bottom, and sides between the top and the bottom. The structure additionally includes a second rectangular fin structure position on the substrate. Similarly, the second rectangular fin structure also has a bottom contacting the substrate, a top opposite the bottom, and sides between the top and the bottom. The sides of the second rectangular fin structure are parallel to the sides of the first rectangular fin structure. Further, a trench insulator is positioned on the substrate and is positioned between a side of the first rectangular fin structure and a side of the second rectangular fin structure. Additionally, a gate conductor is positioned on the trench insulator, positioned over the sides and the top of the first rectangular fin structure, and positioned over the sides and the top of the second rectangular fin structure. The gate conductor runs perpendicular to the sides of the first rectangular fin structure and the sides of the second rectangular fin structure. Also, a gate insulator is positioned between the gate conductor and the first rectangular fin structure and between the gate conductor and the second rectangular fin structure. The structure further includes a first cap on the top of the first rectangular fin structure. The first cap separates the gate conductor from the first rectangular fin structure.

Method of fabricating semiconductor device

A method of fabricating a semiconductor device includes sequentially forming a first gate insulating layer and a second gate insulating layer on a substrate, implanting impurity ions into the substrate and performing a first thermal process for activating the impurity ions to form a source and drain region, and forming a third gate insulating layer on the substrate after the first thermal process has been completed.

Bipolar junction transistor guard ring structures and method of fabricating thereof

Semiconductor devices with multiple floating guard ring edge termination structures and methods of fabricating same are disclosed. A method for fabricating guard rings in a semiconductor device that includes forming a mesa structure on a semiconductor layer stack, the semiconductor stack including two or more layers of semiconductor materials including a first layer and a second layer, said second layer being on top of said first layer, forming trenches for guard rings in the first layer outside a periphery of said mesa, and forming guard rings in the trenches. The top surfaces of said guard rings have a lower elevation than a top surface of said first layer.

Field effect transistors (fets) and methods of manufacture

An improved field effect transistors (FETs) and methods of manufacturing the field effect transistors (FETs) are provided. The method of manufacturing a zero capacitance random access memory cell (ZRAM) includes comprises forming a finFET on a substrate and enhancing a storage capacitance of the finFET. The enhancement can be by either adding a storage capacity to the finFET or altering a portion of the finFET after formation of a fin body of the finFET.

Method of manufacturing a semiconductor device

A method of manufacturing a semiconductor device which includes forming a gate insulating film and a gate electrode over a semiconductor substrate, forming a first recess in the first semiconductor substrate on both sides of the gate electrode by dry etching, forming a second recess by removing a bottom and sidewalls of the first recess by wet etching, and forming a semiconductor layer in the second recess.

Semiconductor Device Comprising Transistor Structures and Methods for Forming Same

A method for forming an opening within a semiconductor material comprises forming a neck portion, a rounded portion below the neck portion and, in some embodiments, a protruding portion below the rounded portion. This opening may be filled with a conductor, a dielectric, or both. Embodiments to form a transistor gate, shallow trench isolation, and an isolation material separating a transistor source and drain are disclosed. Device structures formed by the method are also described.

Replacement Gate Having Work Function at Valence Band Edge

Replacement gate stacks are provided, which increase the work function of the gate electrode of a p-type field effect transistor (PFET). In one embodiment, the work function metal stack includes a titanium-oxide-nitride layer located between a lower titanium nitride layer and an upper titanium nitride layer. The stack of the lower titanium nitride layer, the titanium-oxide-nitride layer, and the upper titanium nitride layer produces the unexpected result of increasing the work function of the work function metal stack significantly. In another embodiment, the work function metal stack includes an aluminum layer deposited at a temperature not greater than 420° C. The aluminum layer deposited at a temperature not greater than 420° C. produces the unexpected result of increasing the work function of the work function metal stack significantly.

Source tip optimization for high voltage transistor devices

The present disclosure provides a method for fabricating a high-voltage semiconductor device. The method includes designating first, second, and third regions in a substrate. The first and second regions are regions where a source and a drain of the semiconductor device will be formed, respectively. The third region separates the first and second regions. The method further includes forming a slotted implant mask layer at least partially over the third region. The method also includes implanting dopants into the first, second, and third regions. The slotted implant mask layer protects portions of the third region therebelow during the implanting. The method further includes annealing the substrate in a manner to cause diffusion of the dopants in the third region.

Semiconductor device and method of fabricating the same

There is provided a high quality liquid crystal panel having a thickness with high accuracy, which is designed, without using a particulate spacer, within a free range in accordance with characteristics of a used liquid crystal and a driving method, and is also provided a method of fabricating the same. The shape of a spacer for keeping a substrate interval constant is made such that it is a columnar shape, a radius R of curvature is 2 μm or less, a height H is 0.5 μm to 10 μm, a diameter is 20 μm or less, and an angle α is 65° to 115°. By doing so, it is possible to prevent the lowering of an opening rate and the lowering to of light leakage due to orientation disturbance.

Semiconductor device and method of manufacturing the same

Aimed at providing a highly reliable semiconductor device appropriately increased in stress at the channel region so as to improve carrier injection rate, thereby dramatically improved in transistor characteristics, and made adaptable also to recent narrower channel width, and a method of manufacturing the same, and a method of manufacturing the same, a first sidewall composed of a stress film having expandability is formed on the side faces of a gate electrode, a second sidewall composed of a film having smaller stress is formed on the first sidewall, and a semiconductor, which is a SiC layer for example, is formed as being positioned apart from the first sidewall while placing the second sidewall in between.

Structure and method for mobility enhanced mosfets with unalloyed silicide

While embedded silicon germanium alloy and silicon carbon alloy provide many useful applications, especially for enhancing the mobility of MOSFETs through stress engineering, formation of alloyed silicide on these surfaces degrades device performance. The present invention provides structures and methods for providing unalloyed silicide on such silicon alloy surfaces placed on semiconductor substrates. This enables the formation of low resistance contacts for both mobility enhanced PFETs with embedded SiGe and mobility enhanced NFETs with embedded Si:C on the same semiconductor substrate. Furthermore, this invention provides methods for thick epitaxial silicon alloy, especially thick epitaxial Si:C alloy, above the level of the gate dielectric to increase the stress on the channel on the transistor devices.

Semiconductor element and method for manufacturing same

A semiconductor device 100 includes: a silicon carbide layer 102 ; a source region 104 of a first conductivity type disposed in the silicon carbide layer; a body region 103 of a second conductivity type disposed at a position in contact with the source region 104 in the silicon carbide layer; a contact region 105 of the second conductivity type formed in the body region; a drift region 102 d of the first conductivity type disposed in the silicon carbide layer; and a source electrode 109 in ohmic contact with the source region 104 and the contact region 105 , wherein: a side wall of the source electrode 109 is in contact with the source region 104 ; a lower surface of the source electrode 109 is in contact with the contact region 105 and is not in contact with the source region 104 ; and at least a portion of the source region 104 overlaps the contact region 105 as viewed from a direction perpendicular to a principle surface of a substrate 101.

Method for manufacturing a strained channel mos transistor

A method for manufacturing a strained channel MOS transistor including the steps of: forming, at the surface of a semiconductor substrate, a MOS transistor comprising source and drain regions and an insulated sacrificial gate which partly extends over insulation areas surrounding the transistor; forming a layer of a dielectric material having its upper surface level with the upper surface of the sacrificial gate; removing the sacrificial gate; etching at least an upper portion of the exposed insulation areas to form trenches therein; filling the trenches with a material capable of applying a strain to the substrate; and forming, in the space left free by the sacrificial gate, an insulated MOS transistor gate.

Transistor and method for forming the same

The invention discloses a semiconductor device which comprises an NMOS transistor and a PMOS transistor formed on a substrate; and grid electrodes, source cathode doped areas, drain doped areas, and side walls formed on two sides of the grid electrodes are arranged on the NMOS transistor and the PMOS transistor respectively. The device is characterized in that the side walls on the two sides of the grid electrode of the NMOS transistor possess tensile stress, and the side walls on the two sides of the grid electrode of the PMOS transistor possess compressive stress. The stress gives the side walls a greater role in adjusting the stress applied to channels and the source/drain areas, with the carrier mobility further enhanced and the performance of the device improved.

Semiconductor device

A MOSFET includes: a silicon carbide substrate having a main surface having an off angle of not less than 50° and not more than 65° relative to a {0001} plane; an active layer; a gate oxide film; a p type body region having p type conductivity and formed to include a region of the active layer, the region being in contact with the gate oxide film; an n + region having n type conductivity and formed in the p type body region to include a main surface of the active layer opposite to the silicon carbide substrate; and a source contact electrode formed on the active layer in contact with the n + region, the p type body region having a p type impurity density of 5×10 17 cm −3 or greater, the source contact electrode and the p type body region being in direct contact with each other.

Semiconductor device

A source region and a drain region are disposed in a substrate. A gate insulating film is disposed on the substrate. A gate electrode is disposed on the gate insulating film. The gate electrode may include a first gate portion adjacent to the source region and a second gate portion adjacent to the drain region. The first and second gate portions have different work functions from each other.

Semiconductor structures and methods of manufacturing the same

A semiconductor structure has embedded stressor material for enhanced transistor performance. The method of forming the semiconductor structure includes etching an undercut in a substrate material under one or more gate structures while protecting an implant with a liner material. The method further includes removing the liner material on a side of the implant and depositing stressor material in the undercut under the one or more gate structures.

Semiconductor device and method for driving same

The present invention is directed to an MIS type semiconductor device, including a channel layer between a semiconductor body region and a gate insulating film, the channel layer having an opposite semiconductor polarity to that of the semiconductor body region. Since Vfb of the semiconductor device is equivalent to or less than a gate rated voltage Vgcc − of the semiconductor device with respect to an OFF-polarity, density of carrier charge that is induced near the surface of the semiconductor body region is kept at a predetermined amount or less with a guaranteed range of operation of the semiconductor device.

Stressed channel fet with source/drain buffers

A method for forming a stressed channel field effect transistor (FET) with source/drain buffers includes etching cavities in a substrate on either side of a gate stack located on the substrate; depositing source/drain buffer material in the cavities; etching the source/drain buffer material to form vertical source/drain buffers adjacent to a channel region of the FET; and depositing source/drain stressor material in the cavities adjacent to and over the vertical source/drain buffers.

Non-volatile finfet memory array and manufacturing method thereof

An electronic device includes a substrate with a semiconducting surface having a plurality of fin-type projections coextending in a first direction through a memory cell region and select gate regions. The electronic device further includes a dielectric isolation material disposed in spaces between the projections. In the electronic device, the dielectric isolation material in the memory cell regions have a height less than a height of the projections in the memory cell regions, and the dielectric isolation material in the select gate regions have a height greater than or equal to than a height of the projections in the select gate regions. The electronic device further includes gate features disposed on the substrate within the memory cell region and the select gate regions over the projections and the dielectric isolation material, where the gate features coextend in a second direction transverse to the first direction.

Method for manufacturing silicon carbide semiconductor device

A method for manufacturing a silicon carbide semiconductor device includes the step of forming a mask pattern of a silicon oxide film by removing a portion of the silicon oxide film by means of etching employing a gas containing oxygen gas and at least one fluorine compound gas selected from a group consisting of CF 4 , C 2 F 6 , C 3 F 8 , and SF 6 .

Method of manufacturing silicon carbide semiconductor device

A silicon carbide substrate having a substrate surface is prepared. An insulating film is formed to cover a part of the substrate surface. A contact electrode is formed on the substrate surface, so as to be in contact with the insulating film. The contact electrode contains Al, Ti, and Si atoms. The contact electrode includes an alloy film made of an alloy containing Al atoms and at least any of Si atoms and Ti atoms. The contact electrode is annealed such that the silicon carbide substrate and the contact electrode establish ohmic connection with each other. Thus, in a case where a contact electrode having Al atoms is employed, insulation reliability of the insulating film can be improved.

Fabrication of a vertical heterojunction tunnel-fet

Exemplary embodiments include a method for fabricating a heterojunction tunnel field-effect-transistor (FET), the method including forming a gate region on a silicon layer of a silicon-on-insulator (SOI) substrate, forming a drain region on the silicon layer adjacent the gate region and forming a vertical heterojunction source region adjacent the gate region, wherein the vertical heterojunction source region generates a tunnel path inline with a gate field associated with the gate region.

FinFET STRUCTURE HAVING FULLY SILICIDED FIN

A semiconductor device which includes fins of a semiconductor material formed on a semiconductor substrate and then a gate electrode formed over and in contact with the fins. An insulator layer is deposited over the gate electrode and the fins. A trench opening is then etched in the insulator layer. The trench opening exposes the fins and extends between the fins. The fins are then silicided through the trench opening. Then, the trench opening is filled with a metal in contact with the silicided fins to form a local interconnect connecting the fins.

Devices and methods to optimize materials and properties for replacement metal gate structures

Devices and methods for device fabrication include forming a gate structure with a sacrificial material. Silicided regions are formed on source/drain regions adjacent to the gate structure or formed at the bottom of trench contacts within source/drain areas. The source/drain regions or the silicided regions are processed to build resistance to subsequent thermal processing and adjust Schottky barrier height and thus reduce contact resistance. Metal contacts are formed in contact with the silicided regions. The sacrificial material is removed and replaced with a replacement conductor.

Semiconductor device and manufacturing method of the same

A semiconductor device of an embodiment at least includes: a SiC substrate; and a gate insulating film formed on the SiC substrate, wherein at an interface between the SiC substrate and the gate insulating film, some of elements of both of or one of Si and C in an outermost surface of the SiC substrate are replaced with at least one type of element selected from nitrogen, phosphorus, and arsenic.

Finfet structures and methods for fabricating the same

A method for fabricating a FinFET structure includes fabricating a plurality of parallel fins overlying a semiconductor substrate, each of the plurality of parallel fins having sidewalls and forming an electrode over the semiconductor substrate and between the parallel fins. The electrode is configured to direct an electrical field into the fins, thereby affecting the threshold voltage of the FinFET structure.

System and Method for Source/Drain Contact Processing

System and method for reducing contact resistance and prevent variations due to misalignment of contacts is disclosed. A preferred embodiment comprises a non-planar transistor with source/drain regions located within a fin. An inter-layer dielectric overlies the non-planar transistor, and contacts are formed to the source/drain region through the inter-layer dielectric. The contacts preferably come into contact with multiple surfaces of the fin so as to increase the contact area between the contacts and the fin.

Method and apparatus of fabricating silicon carbide semiconductor device

A method of fabricating a SiC semiconductor device includes the steps of preparing a silicon carbide semiconductor including a first surface having impurities implanted at least partially, forming a second surface by dry etching the first surface of the silicon carbide semiconductor using gas including hydrogen gas, and forming an oxide film constituting the silicon carbide semiconductor device on the second surface.

Gated Bipolar Junction Transistors, Memory Arrays, and Methods of Forming Gated Bipolar Junction Transistors

Some embodiments include gated bipolar junction transistors. The transistors may include a base region between a collector region and an emitter region; with a B-C junction being at an interface of the base region and the collector region, and with a B-E junction being at an interface of the base region and the emitter region. The transistors may include material having a bandgap of at least 1.2 eV within one or more of the base, emitter and collector regions. The gated transistors may include a gate along the base region and spaced from the base region by dielectric material, with the gate not overlapping either the B-C junction or the B-E junction. Some embodiments include memory arrays containing gated bipolar junction transistors. Some embodiments include methods of forming gated bipolar junction transistors.

Semiconductor device

A semiconductor device according to an embodiment includes: a semiconductor region on a semiconductor substrate, an upper face and side faces of the semiconductor region forming a saddle-like shape, convex portions being formed at both ends of a region including a saddle point in the upper face; a gate insulating film on the upper face of the semiconductor region except upper faces of the convex portions, and on side faces of the convex portions on a side of the region including the saddle point in the upper face; a gate electrode on the gate insulating film and including: a main body part located immediately above the region including the saddle point in the upper face; and leg portions leading to the main body portion and covering the side faces of the semiconductor region, a length of the leg portions being greater than a length of the main body portion.

Semiconductor device and method of manufacturing the same

A semiconductor device of an embodiment includes: a silicon carbide substrate including first and second principal surfaces; a first conductive-type first silicon carbide layer provided on the first principal surface of the silicon carbide substrate; a second conductive-type first silicon carbide region formed on a surface of the first silicon carbide layer; a first conductive-type second silicon carbide region formed on a surface of the first silicon carbide region; a second conductive-type third silicon carbide region formed on the surface of the first silicon carbide region; a gate insulating film continuously formed on the surfaces of the first silicon carbide layer, the first silicon carbide region, and the second silicon carbide region; a first electrode formed of silicon carbide formed on the gate insulating film; a second electrode formed on the first electrode; an interlayer insulating film for covering the first and second electrodes; a third electrode electrically connected to the second silicon carbide region and the third silicon carbide region; and a fourth electrode formed on the second principal surface of the silicon carbide substrate.

Semiconductor device based on the cubic silicon carbide single crystal thin film

A semiconductor apparatus includes a cubic silicon carbide single crystal thin film of a multilayer structure including an Al x Ga 1-x As (0.6>x≧ 0 ) layer and a cubic silicon carbide single crystal layer. The apparatus also includes a substrate on which a metal layer is formed. The multilayer structure is bonded to a surface of the metal layer with the Al x Ga 1-x As (0.6>x≧ 0 ) in direct contact with the metal layer.

Semiconductor devices and methods of fabricating the same

A method of fabricating one or more semiconductor devices includes forming a trench in a semiconductor substrate, performing a cycling process to remove contaminants from the trench, and forming an epitaxial layer on the trench. The cycling process includes sequentially supplying a first reaction gas containing germane, hydrogen chloride and hydrogen and a second reaction gas containing hydrogen chloride and hydrogen onto the semiconductor substrate.

Methods of fabricating semiconductor devices

A substrate including an NMOS transistor region and a PMOS transistor region is prepared. A silicon-germanium layer is formed on the PMOS transistor region. Nitrogen atoms are injected in an upper portion of the silicon-germanium layer. A first gate dielectric layer is formed on the NMOS transistor region and the PMOS transistor region. The nitrogen atoms are injected into the upper portion of the silicon-germanium layer before forming the first gate dielectric layer.

Methods for fabricating semiconductor devices

A method of fabricating a semiconductor device includes providing a semiconductor substrate including a channel region, forming a gate electrode structure on the channel region of the semiconductor substrate, forming a first trench in the semiconductor substrate, and forming a second trench in the semiconductor device. The first trench may include a first tip that protrudes toward the channel. The second trench may be an enlargement of the first trench and may include a second tip that also protrudes toward the channel region. In some examples, the second tip may protrude further towards the channel region than the first tip.

Silicon carbide semiconductor device

A silicon carbide layer is epitaxially formed on a main surface of a substrate. The silicon carbide layer is provided with a trench having a side wall inclined relative to the main surface. The side wall has an off angle of not less than 50° and not more than 65° relative to a {0001} plane. A gate insulating film is provided on the side wall of the silicon carbide layer. The silicon carbide layer includes: a body region having a first conductivity type and facing a gate electrode with the gate insulating film being interposed therebetween; and a pair of regions separated from each other by the body region and having a second conductivity type. The body region has an impurity density of 5×10 16 cm −3 or greater. This allows for an increased degree of freedom in setting a threshold voltage while suppressing decrease of channel mobility.

Backside bevel protection

The disclosure provides methods and structures for preventing exposing polysilicon layer and silicon substrate on the substrate backside to polysilicon etching chemistry during removal of the dummy polysilicon layer in replacement gate structures. A thermal deposition process or processes are used to deposit a dielectric layer for offset spacers and/or a contact etch stop layer (CESL) to cover the polysilicon layer on the substrate backside. Such mechanisms reduce or eliminate particles originated at bevel of substrate backside, due to complete removal of the polysilicon layer at the backside bevel and the resultant etching of silicon substrate.

Semiconductor device and fabrication method

A semiconductor device includes a semiconductor substrate including a well having a first conductivity type defined by a device isolation region, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film and including a first side surface and a second side surface facing the first side surface, and a first side wall insulating film formed on the first side surface and a second side wall insulating film formed on the second side surface.

Method of gate work function adjustment and metal gate transistor

A method of gate work function adjustment includes the steps as follow. First, a substrate is provided, wherein a metal gate is disposed on the substrate, a source doping region and a drain doping region are disposed in the substrate at opposite sites of the metal gate, wherein the metal gate is divided into a source side adjacent to the source doping region, and a drain side adjacent to the drain doping region. Later, a mask layer is formed to cover the source doping region and the drain doping region. After that, an implantation process is performed to implant nitrogen into the metal gate so as to make a first nitrogen concentration of the source side higher than a second nitrogen concentration of the drain side. Finally, the mask layer is removed.

Semiconductor device and method for manufacturing the same

A semiconductor device comprising: a semiconductor substrate; an STI embedded into the semiconductor substrate and having at least a semiconductor opening region; a channel region in the semiconductor opening region; a gate stack comprising a gate dielectric layer and a gate conductive layer and located above the channel region; and source/drain regions located on both sides of the channel region, and comprising first seed layers on opposite sides of the gate stack adjacent to the STI, wherein the upper surface of the STI is higher than or sufficiently closed to the upper surface of the gate dielectric layer. The semiconductor device and the method for manufacturing the same can enhance the stress of the channel region so as to improve device performance.

Cavity-free interface between extension regions and embedded silicon-carbon alloy source/drain regions

A gate stack is formed on a silicon substrate, and source/drain extension regions are formed around the gate stack. A dielectric spacer is formed around the gate stack. A pair of trenches is formed around the gate stack and the dielectric spacer by an etch so that sidewalls of the source/drain extension regions are exposed. Within each trench, an n-doped silicon liner is deposited on the sidewalls of the trenches by a first selective epitaxy process so that the interface between the dielectric spacer and the source/drain extension region is covered. Within each trench, an n-doped single crystalline silicon-carbon alloy is subsequently deposited to fill the trench by a second selective epitaxy process. A combination of an n-doped single crystalline silicon liner and an n-doped single crystalline silicon-carbon alloy functions as embedded source/drain regions of an n-type field effect transistor (NFET), which applies a tensile stress to the channel of the transistor.

Trench mos structure and method for forming the same

A trench MOS structure is disclosed. The trench MOS structure includes a substrate, an epitaxial layer, a doping well, a doping region and a trench gate. The substrate has a first conductivity type, a first side and a second side opposite to the first side. The epitaxial layer has the first conductivity type and is disposed on the first side. The doping well has a second conductivity type and is disposed on the epitaxial layer. The doping region has the first conductivity type and is disposed on the doping well. The trench gate is partially disposed in the doping region. The trench gate has a bottle shaped profile with a top section smaller than a bottom section, both are partially disposed in the doping well. The bottom section of two adjacent trench gates results in a higher electrical field around the trench MOS structures.

SOI SiGe-BASE LATERAL BIPOLAR JUNCTION TRANSISTOR

A lateral heterojunction bipolar transistor (HBT) is formed on a semiconductor-on-insulator substrate. The HBT includes a base including a doped silicon-germanium alloy base region, an emitter including doped silicon and laterally contacting the base, and a collector including doped silicon and laterally contacting the base. Because the collector current is channeled through the doped silicon-germanium base region, the HBT can accommodate a greater current density than a comparable bipolar transistor employing a silicon channel. The base may also include an upper silicon base region and/or a lower silicon base region. In this case, the collector current is concentrated in the doped silicon-germanium base region, thereby minimizing noise introduced to carrier scattering at the periphery of the base. Further, parasitic capacitance is minimized because the emitter-base junction area is the same as the collector-base junction area.

Semiconductor device and method for fabricating the same

A semiconductor device comprising a silicon substrate, a gate structure and a heteroatom-containing epitaxial structure is provided. The gate structure is disposed on a surface of the silicon substrate. The heteroatom-containing epitaxial structure is disposed adjacent to the gate structure and has a major portion and an extension portion, wherein the major portion virtual vertically extends downwards into the silicon substrate from the surface; and the extension portion further extends downwards into the silicon substrate with a tapered cross-section continuing with the major portion.

Finfet transistor structure and method for making the same

A FINFET transistor structure includes a substrate, a fin structure, an insulating layer and a gate structure. The fin structure is disposed on the substrate and directly connected to the substrate. Besides, the fin structure includes a fin conductive layer and a bottle neck. The insulating layer covers the substrate and has a protruding side which is formed by partially surrounding the bottle neck of the fin structure, and a bottom side in direct contact with the substrate so that the protruding side extend to and under the fin structure. The gate structure partially surrounds the fin structure.

PMOS Threshold Voltage Control by Germanium Implantation

Disclosed herein is a method of forming a semiconductor device. In one example, the method comprises forming a P-active region in a silicon containing semiconducting substrate, performing an ion implantation process to implant germanium into the P-active region to form an implanted silicon-germanium region in the P-active region, and forming a gate electrode structure for a PMOS transistor above the implanted silicon-germanium region.

Well region formation method and semiconductor base

A well region formation method and a semiconductor base in the field of semiconductor technology are provided. A method comprises: forming isolation regions in a semiconductor substrate to isolate active regions; selecting at least one of the active regions, and forming a first well region in the selected active region; forming a mask to cover the selected active region, and etching the rest of the active regions, so as to form grooves; and growing a semiconductor material by epitaxy to till the grooves. Another method comprises: forming isolation regions in a semiconductor substrate for isolating active regions; forming well regions in the active regions; etching the active regions to form grooves, such that the grooves have a depth less than or equal to a depth of the well regions; and growing a semiconductor material by epitaxy to till the grooves.

Method of fabricating semiconductor devices

A method of fabricating a semiconductor device is provided. The method includes forming a gate having a first material on a substrate and a layer of a second material overlaying the gate. Sidewall spacers are formed on opposite sides of the gate. A characteristic of a portion of the substrate between adjacent sidewall spacers is changed using the layer of second material and the sidewall spacers as a mask. An isotropic wet etch process is performed to remove the substrate portion with a changed characteristic to form a recess in the substrate. An orientation selective wet etching process is performed on the recess to shape the inner walls of the recess into sigma-shape. Changing a substrate characteristic in conjunction with isotropic wet etching prevents the substrate from being damaged, and therefore can obtain defect free epitaxial SiGe growth performance.

Method for fabricating semiconductor device

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a dummy gate on the substrate; forming a contact etch stop layer on the dummy gate and the substrate; performing a planarizing process to partially remove the contact etch stop layer; partially removing the dummy gate; and performing a thermal treatment on the contact etch stop layer.

Semiconductor device with increased channel mobility and dry chemistry processes for fabrication thereof

Embodiments of a semiconductor device having increased channel mobility and methods of manufacturing thereof are disclosed. In one embodiment, the semiconductor device includes a substrate including a channel region and a gate stack on the substrate over the channel region. The gate stack includes an alkaline earth metal. In one embodiment, the alkaline earth metal is Barium (Ba). In another embodiment, the alkaline earth metal is Strontium (Sr). The alkaline earth metal results in a substantial improvement of the channel mobility of the semiconductor device.

Devices and methods to optimize materials and properties for replacement metal gate structures

Devices and methods for device fabrication include forming a gate structure with a sacrificial material. Silicided regions are formed on source/drain regions adjacent to the gate structure or formed at the bottom of trench contacts within source/drain areas. The source/drain regions or the silicided regions are processed to build resistance to subsequent thermal processing and adjust Schottky barrier height and thus reduce contact resistance. Metal contacts are formed in contact with the silicided regions. The sacrificial material is removed and replaced with a replacement conductor.

Method to modify the shape of a cavity using angled implantation

A method of modifying a shape of a cavity in a substrate. The method includes forming one or more cavities on a surface of the substrate between adjacent relief structures. The method also includes directing ions toward the substrate at a non-normal angle of incidence, wherein the ions strike an upper portion of a cavity sidewall, and wherein the ions do not strike a lower portion of the cavity sidewall. The method further includes etching the one or more cavities wherein the upper portion of a cavity sidewall etches more slowly than the lower portion of the sidewall cavity.

Fabricating method of mos transistor, fin field-effect transistor and fabrication method thereof

A fabricating method of a MOS transistor includes the following steps. A substrate is provided. A gate dielectric layer is formed on the substrate. A nitridation process containing nitrogen plasma and helium gas is performed to nitride the gate dielectric layer. A fin field-effect transistor and fabrication method thereof are also provided.

System and Method for Packaging of High-Voltage Semiconductor Devices

A method and an electronic device structure comprising at least one access lead to adapted to be connected to an electrical circuit; at least one substrate region; at least one semiconductor die positioned on the substrate; the at least one semiconductor die being operatively connected to the at least one access lead; a dielectric region extending below the at least one semiconductor die; the dielectric region being formed by creating a cavity in the at least one substrate region; whereby the dielectric region operates to reduce electric field stresses produced by the at least one semiconductor die to thereby reduce the possibility of material failure and voltage breakdown. The method of making an electronic device structure comprises providing at least one substrate region; providing at least one semiconductor die located on the at least one substrate region; removing a portion of the at least one substrate region to provide a dielectric region within the substrate extending below the at least one semiconductor die; whereby the dielectric region within the at least one substrate region operates to reduce electric field stresses produced by the at least one semiconductor die to thereby reduce the possibility of material failure and voltage breakdown.

Integrated circuit having a stressor and method of forming the same

An embodiment of the disclosure includes a method of forming a semiconductor structure. A substrate has a region adjacent to a shallow trench isolation (STI) structure in the substrate. A patterned mask layer is formed over the substrate. The patterned mask layer covers the STI structure and a portion of the region, and leaves a remaining portion of the region exposed. A distance between an edge of the remaining portion and an edge of the STI structure is substantially longer than 1 nm. The remaining portion of the region is etched thereby forms a recess in the substrate. A stressor is epitaxially grown in the recess. A conductive plug contacting the stressor is formed.

Recessed contact for multi-gate fet optimizing series resistance

A method to fabricate a transistor including forming at least one electrically conductive channel structure over a substrate, the channel having a length, a width and a first height (h 1 ); forming a gate structure over the substrate, the gate structure having a length, a width and a height, the gate structure being perpendicular to the channel structure and being formed over the channel structure such that the channel structure passes through the width of the gate structure, where the height of the gate structure is greater than h 1 ; reducing the height of the channel structure external to the gate structure so as to have a second height (h 2 ); and depositing a silicide layer at least partially over the at least one channel structure external to the gate structure.

Silicon carbide substrate manufacturing method and silicon carbide substrate

Silicon carbide single crystal is prepared. Using the silicon carbide single crystal as a material, a silicon carbide substrate having a first face and a second face located at a side opposite to the first face is formed. In the formation of the silicon carbide substrate, a first processed damage layer and a second processed damage layer are formed at the first face and second face, respectively. The first face is polished such that at least a portion of the first processed damage layer is removed and the surface roughness of the first face becomes less than or equal to 5 nm. At least a portion of the second processed damage layer is removed while maintaining the surface roughness of the second plane greater than or equal to 10 nm.

Replacement source/drain finfet fabrication

A finFET is formed having a fin with a source region, a drain region, and a channel region between the source and drain regions. The fin is etched on a semiconductor wafer. A gate stack is formed having an insulating layer in direct contact with the channel region and a conductive gate material in direct contact with the insulating layer. The source and drain regions are etched leaving the channel region of the fin. Epitaxial semiconductor is grown on the sides of the channel region that were adjacent the source and drain regions to form a source epitaxy region and a drain epitaxy region. The source and drain epitaxy regions are doped in-situ while growing the epitaxial semiconductor.

Silicon carbide semiconductor device

A first layer has a first conductivity type. A second layer is provided on the first layer such that a part of the first layer is exposed, and it has a second conductivity type. First to third impurity regions penetrate the second layer and reach the first layer. Each of the first and second impurity regions has the first conductivity type. The third impurity region is arranged between the first and second impurity regions and it has the second conductivity type. First to third electrodes are provided on the first to third impurity regions, respectively. A Schottky electrode is provided on the part of the first layer and electrically connected to the first electrode.

Semiconductor device

In one embodiment, a semiconductor device includes a semiconductor substrate, a gate electrode provided on the semiconductor substrate via an insulating layer, and a gate insulator provided on a side surface of the gate electrode. The device includes a stacked layer including a lower main terminal layer of a first conductivity type, an intermediate layer, and an upper main terminal layer of a second conductivity type which are successively stacked on the semiconductor substrate, the stacked layer being provided on the side surface of the gate electrode via the gate insulator. The upper or lower main terminal layer is provided on the side surface of the gate electrode via the gate insulator and the semiconductor layer.

Mechanisms for forming ultra shallow junction

The embodiments of methods and structures are for doping fin structures by plasma doping processes to enable formation of shallow lightly doped source and drain (LDD) regions. The methods involve a two-step plasma doping process. The first step plasma process uses a heavy carrier gas, such as a carrier gas with an atomic weight equal to or greater than about 20 amu, to make the surfaces of fin structures amorphous and to reduce the dependence of doping rate on crystalline orientation. The second step plasma process uses a lighter carrier gas, which is lighter than the carrier gas for the first step plasma process, to drive the dopants deeper into the fin structures. The two-step plasma doping process produces uniform dopant profile beneath the outer surfaces of the fin structures.

Semiconductor device and method of manufacturing the same

According to one embodiment, there is provided a method of manufacturing a semiconductor device. In the method, a substrate portion and a fin portion on the substrate portion are formed. A first silicon oxide film is formed on each side surface of the fin portion. A polysilazane film having an upper surface lower than the upper surface of the first silicon oxide film is formed on each side surface of the first silicon oxide film. The polysilazane film is converted into a silicon oxynitride film. The first silicon oxide film is etched to make the upper surface of the first silicon oxide film not higher than the upper surface of the silicon oxynitride film. A heavily doped semiconductor layer is formed in the fin portion.

Semiconductor device and manufacturing method of semiconductor device

According to one embodiment, a semiconductor device includes a fin-type semiconductor, a gate electrode that is formed on a side surface of the fin-type semiconductor with a gate dielectric film therebetween in a state where both end portions of the fin-type semiconductor are exposed, source/drain formed in both end portions of the fin-type semiconductor, an offset spacer and a sidewall spacer that are formed on a side surface of the source/drain and a side surface of the gate electrode in a state where a surface of an upper portion of the fin-type semiconductor is exposed, and a silicide layer that is formed on a surface of the source/drain in the upper portion of the fin-type semiconductor.

Method to enable compressively strained pfet channel in a finfet structure by implant and thermal diffusion

A method of making a semiconductor device patterns a first fin in a pFET region, and patterns a second fin in an nFET region. A plurality of conformal microlayers containing a straining material are deposited on the first and second fins. A protective cap material is formed on the first fin, and the conformal layers are selectively removed from the second fin. The straining material is then thermally diffused into the first fin. The protective cap material is removed from the first fin after the thermal annealing and after the conformal micro layers are selectively removed from the second fin.

Circuit simulation method and semiconductor integrated circuit

A simulation method of a circuit in which a transistor is formed of a material (e.g., SiGe, etc.) having a lattice constant different from that of a semiconductor substrate, on source and drain regions, an adjacent active region is formed near the transistor, and a gate electrode is formed in the active region, where a region not overlapping with the gate electrode in the adjacent active region is formed of a material such as SiGe, includes a step of calculating an electrical characteristic (e.g., flowing current, threshold voltage, etc.) of the transistor based on a distance between an edge closer to the transistor, of both edges of the adjacent active region disposed near the transistor, and the gate electrode formed in the adjacent active region. Thus, circuit simulation can be performed with high accuracy with respect to an electrical characteristic of the transistor.

Method of isolating nanowires from a substrate

A method is provided. The method includes forming a plurality of nanowires on a top surface of a substrate and forming an oxide layer adjacent to a bottom surface of each of the plurality of nanowires, wherein the oxide layer is to isolate each of the plurality of nanowires from the substrate.