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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 4499. Отображено 100.
05-01-2012 дата публикации

Digital Background Calibration System and Method for Successive Approximation (SAR) Analogue to Digital Converter

Номер: US20120001781A1
Автор: Anthony Gerard Scanlan
Принадлежит: University of Limerick

The invention provides a digital background calibration system and method for a successive approximation analog-to-digital converter comprising a digital to analog converter (DAC) having a plurality of weighted capacitors to be calibrated; means for splitting each of said weighted capacitors into a plurality of sub-capacitors and at least one redundant capacitor; means for multiplying the voltage level of at least one of the sub-capacitors with a PN sequence; and means for calibrating the weighted capacitor from the multiplied sub-capacitor and the redundant capacitor.

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Номер записи: 1
05-04-2012 дата публикации

Complex analog to digital converter (cadc) system on chip double rate architecture

Номер: US20120081246A1
Автор: Byron W. Tietjen, J. Claude Caci, Kevin H. Wilson
Принадлежит: Lockheed Martin Corp

A Complex Analog to Digital Converter System on Chip (CADC SoC) implemented into a microcircuit system is provided. A series of stagger clock signals can be fixed on either a rising or falling edge of the system clock and a plurality of A/D converters can be grouped by sets (i.e. odd and even) and assigned to odd or even stager clocks. A complex I&Q data manager is provided for controlling the system. A clock management system is responsive to an external signal to select from a set of stagger clock settings, thereby improving anti-alias performance.

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Номер записи: 2
19-04-2012 дата публикации

Analog to digital converter

Номер: US20120092202A1
Автор: John Kikidis, Michael Birbas, Nikolaos Petrellis
Принадлежит: ANALOGIES SA

An analog to digital converter for converting an initial analog signal into a digital signal comprising at least one electronic module with an input, a first output, and a second output, which module generates from an analog input signal: a first output signal, which first output signal in terms of multiples of a predetermined amount of current or voltage, such as 1 uA or 1 mV, is substantially equal to the integer quotient of division of the input signal by a number or comprises a plurality of signals which if combined are substantially equal to the integer quotient of division of the input signal in terms of multiples of a predetermined amount of current or voltage, and a second output signal which in terms of multiples of a predetermined amount of current or voltage, such as 1 uA or 1 mV, is substantially equal to the remainder of the division, the analog to digital converter also comprising a further analog to digital converter for converting the second output signal into a digital signal, wherein the further analog to digital converter is connected the at least one module and the module is configured so that in use when the analog input signal connects through the input the first output signal connects through the first output, and the second output signal connects through the second output into the further analog to digital converter.

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Номер записи: 3
26-04-2012 дата публикации

Analog-to-digital converter and image sensor including the same

Номер: US20120098990A1
Автор: Chi-Ho Hwang, Dong-Hun Lee, Kwi-sung Yoo, Min-Ho Kwon, Seung-Hyun Lim, Wun-ki Jung
Принадлежит: SAMSUNG ELECTRONICS CO LTD

An analog-to-digital converter includes a comparison signal generation unit and a control unit. The comparison signal generation unit determines a logic level of a comparison signal by comparing an input signal with a selected reference signal based on a switch control signal in a first comparison mode, and by comparing a difference voltage with a ramp signal based on the switch control signal in a second comparison mode. The difference voltage is generated based on the input signal and the selected reference signal such that a level of the difference voltage is lower than a fine voltage level corresponding to a voltage level of the selected reference signal in the second comparison mode. The control unit generates the switch control signal based on the comparison signal and a mode selection signal.

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Номер записи: 4
12-07-2012 дата публикации

Calibration Circuit and Method for Calibrating Capacitive Compensation in Digital-to-Analog Converters

Номер: US20120176258A1
Автор: Franz Kuttner
Принадлежит: INFINEON TECHNOLOGIES AG

A digital-to-analog converter converts a digital input signal into an analog output signal. The digital-to-analog converter includes an input selector configured to input the digital input signal and an output terminal configured to output the analog signal. An array of current source cells is provided. Each current source cell includes a current source transistor having a gate terminal and a source terminal, a current source switch for coupling the source terminal to the output terminal based on the digital input signal, and a compensation capacitor configured to compensate a capacitive feedback between the gate terminal and the source terminal when the source terminal is coupled to the output terminal. At least one of the current source cells further includes a calibration circuit configured to detect a voltage variation at the gate terminal and provide a compensation voltage for the compensation capacitor.

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Номер записи: 5
16-08-2012 дата публикации

Minimum differential non-linearity trim DAC

Номер: US20120206283A1
Автор: Hans Martin Von Staudt
Принадлежит: Dialog Semiconductor GmbH

A trim DAC wherein the digital input bits to the trim DAC are controlled by a state machine to produce an analog output that is within a least significant bit of the digital input bits. An undersize factor between digital input bits is used to assist in finding a trim solution for major transitions of the digital input bits. Trim solutions are stored in a nonvolatile memory associated with the state machine to be used in creating an accurate analog output.

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Номер записи: 6
23-08-2012 дата публикации

Photonic assisted analog-to-digital conversion using phase detection

Номер: US20120212360A1
Автор: Daniel Reilly, Gregory S. Kanter
Принадлежит: Nucrypt LLC

A method of digitizing an analog electrical signal combines optical and electronic techniques in order to improve the resolution, sampling rate, input frequency range, or flexibility. It implements an optical interferometric modulator, which modulates an input optical signal by the input electrical signal combined with a calibration signal. A set of two or more photoreceivers receiving the output optical signals from the optical modulator produce output electrical signals, which are digitized and processed in a DSP to produce a digitized version of the electrical input signal, and a digitized calibration signal value is used to optimize the input electrical signal digitization. The method and the device can be used in many fields including instrumentation, communications, and imaging.

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Номер записи: 7
13-09-2012 дата публикации

Analog to digital converter circuit

Номер: US20120229313A1
Автор: Chi-Hang CHAN, Franco Maloberti, He-Gong Wei, Li Ding, Rui Paulo da Silva Martins, Sai-Weng Sin, Seng-Pan U, U-Fat CHIO, Yan Zhu
Принадлежит: UNIVERSITY OF MACAU

The present invention provides an analog-to-digital converter (ADC) circuit comprising two time-interleaved successive approximation register (SAR) ADCs. Each of the two time-interleaved SAR ADCs comprises a first stage SAR sub-ADC, a residue amplifier, a second stage SAR sub-ADC and a digital error correction logic. The residue amplifier is shared between the time-interleaved paths, has a reduced gain and operates in sub-threshold to achieve power effective design

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Номер записи: 8
22-11-2012 дата публикации

Method and apparatus for perfoming data conversion with non-uniform quantization

Номер: US20120293350A1
Автор: Arthur J. Redfern, Patrick Satarzadeh
Принадлежит: Texas Instruments Inc

A method for converting a sampled analog signal into digital is provided. An input signal is sampled at a sampling instant to generate a sample voltage. A first current is then applied to a node to change a voltage on the node, and a first interval to change the voltage on the node to a reference voltage from the sample voltage using the first current is determined. A second current is then applied to the node to change a voltage on the node prior to a subsequent sampling instant, and a determination of a second interval to change the voltage on the node to the reference voltage from the sample voltage using the second current is made.

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Номер записи: 9
06-12-2012 дата публикации

Analog-to-digital conversion apparatus and signal processing system

Номер: US20120306673A1
Автор: Yosuke Ueno
Принадлежит: Sony Corp

An analog-to-digital conversion apparatus includes: a first analog-to-digital converter configured to convert an input analog signal into a digital signal; a second analog-to-digital converter configured to convert an analog signal generated by multiplying the input analog signal by α times with a coefficient α into a digital signal; a first non-linear compensation part configured to compensate a non-linear distortion of a first output signal of the first analog-to-digital converter; a second non-linear compensation part configured to compensate a non-linear distortion of a second output signal of the second analog-to-digital converter; and a non-linear detection part configured to estimate how much the non-linear distortions of the first and second analog-to-digital converters are compensated by the first and second non-linear compensation parts depending on first and second signals by the first and second non-linear compensation parts.

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Номер записи: 10
17-01-2013 дата публикации

Track and hold architecture with tunable bandwidth

Номер: US20130015990A1
Автор: Marco Corsi, Robert F. Payne
Принадлежит: Texas Instruments Inc

To date, bandwidth mismatch within time-interleaved (TI) analog-to-digital converters (ADCs) has been largely ignored because compensation for bandwidth mismatch is performed by digital post-processing, namely finite impulse response filters. However, the lag from digital post-processing is prohibitive in high speed systems, indicating a need for blind mismatch compensation. Even with blind bandwidth mismatch estimation, though, adjustment of the filter characteristics of track-and-hold (T/H) circuits within the TI ADCs can be difficult. Here, a T/H circuit architecture is provided that uses variations of the gate voltage of a sampling switch (which varies the “on” resistance of the sampling switch) to change the bandwidth of the T/H circuits so as to precisely match the bandwidths.

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Номер записи: 11
24-01-2013 дата публикации

Multiplexed amplifier with reduced glitching

Номер: US20130021188A1
Автор: Robert F. Payne
Принадлежит: Texas Instruments Inc

In many applications, which use amplifiers that operate at less than 50% duty cycle, it would be advantageous to reduce the number amplifiers to reduce power consumption. Here, an amplifier is provided which is time multiplexed to accommodate multiple data paths. Additionally, reset circuitry or a reset mechanism is provided at the output terminals of this amplifier to briefly short the output terminals to generally prevent glitching that may result from switching between data paths.

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Номер записи: 12
31-01-2013 дата публикации

Modified Dynamic Element Matching For Reduced Latency In A Pipeline Analog To Digital Converter

Номер: US20130027231A1
Автор: Andrea Panigada, Daniel MEACHAM, Jorge GRILO
Принадлежит: Microchip Technology Inc

A circuit in an analog-to-digital converter (ADC) includes an amplifier configured to receive an output of a backend DAC; a harmonic distortion correction circuit (HDC) coupled to the amplifier and configured to correct distortion components due to the residue amplifier present in a digital signal from the backend ADC, the HDC circuit providing an output to an adder, the adder receiving a coarse digital output from a coarse ADC; and a DAC noise cancellation circuit (DNC) configured to provide an output to the adder, wherein the DNC circuit is configured to correct distortion components due to the DAC present in the digital signal from the backend ADC; wherein the output of the adder is an ADC digital output and wherein the ADC digital output forms an input to the HDC and the DNC.

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Номер записи: 13
14-02-2013 дата публикации

Analog-to-digital converters and pipeline analog-to-digital converters

Номер: US20130038483A1
Автор: Cong Liu, Yu-Kai Chou
Принадлежит: Mediatek Singapore Pte Ltd

An analog-to-digital converter is provided. The analog-to-digital converter includes a sampling-voltage providing circuit, a first comparison circuit, a second comparison circuit, and an encoder circuit. The sampling-voltage providing circuit provides a group of first comparison voltages and a group of second comparison voltages. The first comparison circuit performs a first comparison operation to an analog-signal input quantity according to the group of first comparison voltages to generate a first comparison digital quantity. The second comparison circuit selects second comparison voltages among the group of second comparison voltages according to the first comparison digital quantity and performs a second comparison operation to the analog-signal input quantity according to the selected second comparison voltages to generate a second comparison digital quantity. The encoder circuit encodes the first comparison digital quantity and the second comparison digital quantity and generates a digital quantity corresponding to the analog-signal input quantity.

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Номер записи: 14
28-03-2013 дата публикации

Time error estimating device, error correction device and a/d converter

Номер: US20130076545A1
Автор: Junya Matsuno, Masanori Furuta, Takafumi Yamaji, Tomohiko Sugimoto
Принадлежит: Toshiba Corp

A time error estimating device for estimating a sampling time error of each of a plurality of sampling circuits when the sampling circuits generates a plurality of sampling output signals by performing sampling at timings shifted from one another has correlators each configured to obtain a correlation value representing a similarity between the sampling output signals, and a weight adder configured to estimate the sampling time error of the sampling circuits, based on a result obtained by adjusting a weight on the correlation value.

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Номер записи: 15
25-04-2013 дата публикации

SAMPLING

Номер: US20130099948A1
Автор: Allen Gavin Lambertus, DEDIC Ian Juso
Принадлежит: FUJITSU SEMICONDUCTOR LIMITED

There is disclosed current-mode time-interleaved sampling circuitry configured to be driven by substantially sinusoidal clock signals. Such circuitry may be incorporated in ADC circuitry, for example as integrated circuitry on an IC chip. The disclosed circuitry is capable of calibrating itself without being taken off-line. 115-. (canceled)16. Current-mode circuitry comprising:a first node where a flowing current changes in response to an input signal;a plurality of switches each of first terminals of which couples to the first node;a plurality of second nodes each of which couples to a second terminal of a corresponding switch of the plurality of switches,wherein the plurality of switches is configured to be sequentially selected during two selection periods which occur in succession, and the two selection periods are partially overlapped.17. The current-mode circuitry of claim 16 ,wherein selection periods which occur in non-succession are non-overlapped.18. The current-mode circuitry of claim 16 , comprising:a current source coupled between the first node and a reference node; anda third node which receives the input signal and is coupled to the first node, the input being a current signal.19. The current-mode circuitry of claim 18 ,wherein the current source flows a constant current from a coupling node between the first node and the third node to the reference node.20. The current-mode circuitry of claim 16 , comprising:a calibration circuit which samples currents flowing through each of the plurality of second nodes over time, and calibrates characteristics of the plurality of switches on the basis of the sample values.21. Analogue-to-digital conversion circuitry claim 16 , comprising circuitry according to .22. Integrated circuitry claim 16 , comprising circuitry according to .23. An IC chip claim 16 , comprising circuitry according to .24. A sampling method comprising:sequentially distributing a current to a plurality current paths during two distribution ...

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Номер записи: 16
25-04-2013 дата публикации

Analog-Digital Conversion System Comprising a Double Automatic Gain Control Loop

Номер: US20130099952A1
Автор: David DEPRAZ, Jean-Michel Perre, Nicolas Martin
Принадлежит: Thales SA

An analog-digital conversion system comprising at least one variable gain amplifier amplifying an input signal e, an analog-digital converter CAN digitizing said signal e, an interference-suppressing digital processing module, processing the digitized signal, also comprises a first automatic gain control AGC loop, called the analog AGC loop, that compares an estimate of the output power of the CAN converter with a control setpoint g 1 called the control setpoint of the analog AGC loop, a gain ga used to control the variable gain amplifier being deduced from this comparison. The system also comprises a second automatic gain control AGC loop called the digital loop, said digital loop comparing an estimate of the power after the interference-suppressing digital processing with a predetermined control setpoint gn, the analog AGC loop being controlled by a control setpoint deduced from this comparison.

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Номер записи: 17
02-05-2013 дата публикации

Calibration of interleaved adc

Номер: US20130106632A1
Автор: Fabien Reaute, Hugo Gicquel, Roger Petigny
Принадлежит: STMicroelectronics Grenoble 2 SAS

The disclosure is directed to an interleaved analog-to-digital converter having: first, second and third sub-converters; a control block configured to control the first sub-converter to sample a test signal and the second sub-converter to sample an input signal during a first sampling period, and to control the second sub-converter to sample the test signal and the third sub-converter to sample the input signal during a second sampling period.

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Номер записи: 18
23-05-2013 дата публикации

SAMPLING

Номер: US20130127649A1
Автор: Allen Gavin Lambertus, DEDIC Ian Juso
Принадлежит: FUJITSU SEMICONDUCTOR LIMITED

There is disclosed current-mode time-interleaved sampling circuitry configured to be driven by substantially sinusoidal clock signals. Such circuitry may be incorporated in ADC circuitry, for example as integrated circuitry on an IC chip. The disclosed circuitry is capable of calibrating itself without being taken off-line. 115-. (canceled)16. Current-mode circuitry for sampling a current signal , the circuitry comprising:a root node configured to receive the current signal;a plurality of first-tier nodes, each of the plurality of first-tier nodes being conductively connectable directly to the root node;a plurality of subsequent-tier nodes that are provided for each of the first-tier nodes, each of the plurality of subsequent-tier nodes being conductively connectable indirectly to the root node along a respective path via the corresponding first-tier node; anda steering circuit configured to control connections between the root node and the subsequent-tier nodes so that different packets of charge making up the current signal are steered along different ones of the paths over time.17. The current-mode circuitry of claim 16 , wherein:the steering circuit is configured to employ sinusoidal control signals to control connections between the root node and the first-tier nodes, and to employ switched-logic control signals to control connections between the first-tier nodes and the subsequent-tier nodes.18. The current-mode circuitry of claim 17 ,wherein the control signals for controlling the connections between the first-tier nodes and the subsequent-tier nodes have larger peak-to-peak voltages than the peak-to-peak voltages of the control signals for controlling connections between the root node and the first-tier nodes, or longer on-times than the on-times of the control signals for controlling the connections between the root node and the first-tier nodes.19. The current-mode circuitry of claim 16 , comprising:a generating circuit configured to generate a sample ...

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Номер записи: 19
06-06-2013 дата публикации

Time-interleaved analog-to-digital converter bandwidth matching

Номер: US20130141261A1
Автор: Ryan James Kier, Tracy Johancsik, Yusuf Haque
Принадлежит: Crest Semiconductors Inc

A time-interleaved Analog-to-Digital Converter (ADC) includes a set of sub-ADC circuits. Each sub-ADC circuit comprises a sample-and-hold circuit. Each sample-and-hold circuit includes a bootstrap circuit for maintaining a constant voltage level between an input terminal of a switch and a gate terminal of the switch, the switch for switching between a sample mode and a hold mode. Each sample and hold circuit also includes a capacitor bank associated with the bootstrap circuit such that a setting of the capacitor bank affects an ON state intrinsic resistance of the switch by affecting the voltage level.

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Номер записи: 20
27-06-2013 дата публикации

Methods and Systems for Compressed Sensing Analog to Digital Conversion

Номер: US20130162457A1
Автор: Allstot David, Gangopadhyay Daibashish
Принадлежит: University of Washington through its Center for Communications

Disclosed herein are example methods, systems, and devices for compressed sensing analog to digital conversion. In an example embodiment, a multiplication circuit is configured to multiply an input signal with a measurement signal to produce a multiplied signal, where the measurement signal includes data from a column of a measurement matrix. The measurement matrix may be generated by a linear feedback shift register (LFSR)-based measurement-matrix generator. An integration circuit may be coupled to the multiplication circuit and configured to integrate the multiplied signal for a predefined amount of time to produce an integrated signal. An analog to digital converter (ADC) circuit may be coupled to the integration circuit and configured to (i) sample the integrated signal and (ii) produce an output signal comprising at least one sample of the integrated signal. Among other benefits of the disclosure herein, a column-wise multiplication of the input signal with the measurement signal enables an efficient compressed-sensing analog-to-digital conversion architecture. 1. A circuit comprising:a multiplication circuit configured to multiply an input signal with a measurement signal to produce a multiplied signal, wherein the measurement signal comprises data from a column of a measurement matrix;an integration circuit coupled to the multiplication circuit and configured to integrate the multiplied signal for a predefined amount of time to produce an integrated signal; andan analog to digital converter (ADC) circuit coupled to the integration circuit and configured to (i) sample the integrated signal and (ii) produce an output signal comprising at least one sample of the integrated signal.2. The circuit of claim 1 , wherein the measurement matrix comprises a plurality of entries claim 1 , the circuit further comprising:a measurement-matrix generator coupled to the multiplication circuit and configured to generate a random coefficient for each entry in the measurement ...

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Номер записи: 21
04-07-2013 дата публикации

SUCCESSIVE APPROXIMATION ANALOG TO DIGITAL CONVERTER AND CONVERSION METHOD THEREOF

Номер: US20130169465A1
Автор: Lee Chao-Cheng
Принадлежит: REALTEK SEMICONDUCTOR CORPORATION

A successive approximation analog to digital converter and a conversion method thereof are provided. The successive approximation analog to digital converter includes a sample circuit, a conversion circuit, and a filtering control circuit. The sample circuit is configured to sample an analog voltage from an analog signal. The conversion circuit is configured to convert the analog voltage into a digital voltage. The filtering control circuit is configured to transmit a filtering control signal to the sample circuit according to the digital voltage. The sample circuit further samples a next analog voltage from the analog signal and adjusts the next analog voltage into an adjusted analog voltage according to the filtering control signal. The conversion circuit further converts the adjusted analog voltage into a next digital voltage, wherein the next digital voltage is a filtered digital voltage. 1. A successive approximation analog to digital (A/D) converter , comprising:a sample circuit, for sampling an analog voltage from an analog signal;a conversion circuit, coupled to the sample circuit, for converting the analog voltage into a digital voltage; anda filtering control circuit, coupled to the sample circuit and the conversion circuit, for transmitting a filtering control signal to the sample circuit according to the digital voltage;wherein the sample circuit further samples a next analog voltage from the analog signal and adjusts the next analog voltage into an adjusted analog voltage according to the filtering control signal, the conversion circuit further converts the adjusted analog voltage into a next digital voltage, and the next digital voltage is a filtered digital voltage.2. The successive approximation analog to digital converter as claimed in claim 1 , wherein the sample circuit is an M-bit sample circuit claim 1 , where M is a positive integer.3. The successive approximation analog to digital converter as claimed in claim 2 , wherein the M-bit sample ...

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Номер записи: 22
11-07-2013 дата публикации

Off-line gain calibration in a time-interleaved analog-to-digital converter

Номер: US20130176154A1
Автор: Anthony R. Bonaccio, Benjamin T. VOEGLI, Frank R. Keyser, III, Martin L. Schmatz
Принадлежит: International Business Machines Corp

A time-interleaved analog-to-digital converter (ADC) includes a plurality of ADC blocks each including: at least one ADC unit configured to convert an analog input to a digital output; and a digital gain controller configured to adjust a reference voltage of the at least one ADC unit based on a comparison of an actual output of the at least one ADC unit to an expected output of the at least one ADC unit.

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Номер записи: 23
01-08-2013 дата публикации

Analog-to-digital conversion device and method thereof

Номер: US20130194119A1
Автор: Chien-Yi Wu, Yen-Chien Cheng, Yung-Chi Yang
Принадлежит: Sunplus Technology Co Ltd

An analog-to-digital conversion device and a method thereof are provided. The analog-to-digital conversion device includes a first level adjustment unit, an analog-to-digital converter (ADC), and a linear range detection unit. The ADC converts a test signal or a first input signal to generate a test data stream or a first output data stream. In an adjustment mode, the linear range detection unit obtains a conversion curve of the ADC by using the test data stream and determines whether to adjust offset control information according to a linear range of the conversion curve. In an operation mode, the linear range detection unit continues outputting the offset control information. Additionally, before transmitting the first input signal, the first level adjustment unit adjusts a direct-current level of the first input signal according to the offset control information to allow the first input signal to be within the linear range of the conversion curve.

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Номер записи: 24
01-08-2013 дата публикации

Method and Apparatus for Clockless Conversion of Voltage Value to Digital Word

Номер: US20130194123A1
Автор: Dariusz Koscielnik, Marek Miskowicz
Принадлежит: Dariusz Koscielnik, Marek Miskowicz

Method and apparatus for mapping the converted voltage value by electric charge value proportional to the converted voltage value and in accumulation of charge in the sampling capacitor until the voltage on this capacitor is equal to the converted voltage. Furthermore, realization of the process of that electric charge redistribution in the array of redistribution by changes of states of signals from relevant control outputs and in assignment of relevant values to bits in the digital word by means of the control module. As soon as accumulation of electric charge in the sampling capacitor is terminated, electric charge is accumulated in the additional sampling capacitor then the process of that electric charge redistribution is realized and relevant values are assigned to bits of the digital word. When a trigger signal is detected, next cycle begins and electric charge is accumulated in the sampling capacitor.

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Номер записи: 25
22-08-2013 дата публикации

Interleaved analog to digital converter with reduced number of multipliers for digital equalization

Номер: US20130214958A1
Автор: Anatoli B. Stein, Semen P. Volfbeyn, Valeriy Serebryanskiy
Принадлежит: Guzik Technical Enterprises Inc

A digital equalizer with a reduced number of multipliers for correction of the frequency responses of an interleaved ADC is disclosed. An exemplary interleaved analog to digital converter with digital equalization includes a composite ADC including M time interleaved sub-ADC, a demultiplexer, samples repositioning unit, a first PreFIRs transformer, a second PreFIRs transformer, K double buffer FIR filters, a PostFIRs transformer, a samples sequence restoration unit, and a multiplexer, coupled in series and providing an equalized, frequency response-corrected output.

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Номер записи: 26
29-08-2013 дата публикации

DISCRETE TIME ANALOG CIRCUIT AND RECEIVER USING SAME

Номер: US20130222164A1
Автор: Araki Kiyomichi, Kanemaru Masaki, Morishita Yohei, Shiozaki Hiroka
Принадлежит: Panasonic Corporation

The discrete time analog circuit () is provided with: a rotate capacitor circuit (); an amplifier () that is connected to the input line or the output line of the rotate capacitor (), and amplifies the input potential or input charge; a coefficient circuit () that is positioned in series with the amplifier (), and has two history capacitors (--) positioned parallel to each other; a first active capacitor among the two history capacitors (--) that is connected to and charges the amplifier (); and a clock generation circuit () that is connected to the input line or the output line without the involvement of the amplifier (), and that sequentially changes the pairing of the rotate capacitor circuit () a second active capacitor, which shares a charge with the rotate capacitor circuit (). 1. A discrete-time analog circuit comprising:a rotating capacitor circuit; a potential holding section that amplifies input potential or input charge, the potential holding section connected to an input line of the rotating capacitor circuit; and', 'n charge holding sections disposed in series with the potential holding section and in parallel with each other, and, 'at least one coefficient circuit includinga circuit connection switching section that sequentially changes the pairing of a first charge holding section and a second charge holding section among the n charge holding sections, the first charge holding section being connected to the potential holding section and charged thereby, the second charge holding section being connected to the input line not via the potential holding section and sharing charge with the rotating capacitor circuit or being held at the potential at the rotating capacitor circuit.2. The discrete-time analog circuit according to claim 1 ,wherein the circuit connection switching section causes:the first charge holding section at an i-th timing to be the second charge holding section at the i-th timing plus n−1 timings; andthe second charge holding section at ...

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Номер записи: 27
26-09-2013 дата публикации

RECEIVER GAIN ADJUSTMENT TO REDUCING AN INFLUENCE OF A DC OFFSET

Номер: US20130251078A1
Автор: Bachl Rainer, Reinhardt Steffen
Принадлежит: TELEFONAKTIEBOLAGET L.M. ERICSSON (PUBL)

The invention refers to generating a digital signal from an analog signal, wherein the analog signal is amplified according to a gain control value before being converted to a digital value by means of an analog-to-digital converter, wherein a DC offset value of the analog signal is determined, and the gain control value is generated as a function of the dynamic range of the analog-to-digital converter and the DC offset value. The invention further refers to a corresponding circuit and a computer program. 1. A method of generating a digital signal from an analog signal , wherein the analog signal is amplified according to a gain control value before being converted to a digital value by an analog-to-digital converter , the method comprising:determining a DC offset value of the analog signal, andgenerating the gain control value as a function of a dynamic range of the analog-to-digital converter and the DC offset value.2. The method of claim 1 , wherein the gain control value is generated such that a combined distortion power due to signal clipping and to signal quantization is reduced or minimized.3. The method of claim 1 , wherein the DC offset value is determined as a function of an actual parameter or state that affects the DC offset.4. The method of claim 3 , wherein the actual state or parameter is indicative of one of: an upper limit of the absolute DC offset claim 3 , an upper limit of a mean absolute DC offset claim 3 , an absolute DC offset claim 3 , and a mean absolute DC offset.5. The method of claim 1 , wherein the analog signal is a baseband signal being generated by down-mixing a selected one of a plurality of carrier frequencies of a radio signal.6. The method of claim 5 , wherein the down-mixing is performed by pre-amplifying the selected radio frequency according to a pre-gain control value signal and self-mixing a corresponding pre-amplified signal with an oscillator signal at the selected carrier frequency.7. The method of claim 6 , wherein the DC ...

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Номер записи: 28
07-11-2013 дата публикации

Adc, ic including the same, and adc method thereof

Номер: US20130293403A1
Автор: Kun LAN, Yingyi LIU, Yu-Kai Chou
Принадлежит: Mediatek Singapore Pte Ltd

An Analog to Digital Converter (ADC), an analog-to-digital conversion method, and an integrated circuit including the ADC. The ADC includes an input adjustment buffer stage, a sub-ADC, and a sample switch. The sample switch is coupled between the output node of the input adjustment buffer stage and the input node of the sub-ADC. When the sample switch is opened, the input adjustment buffer stage is configured to switch between a first work state and a second work state according to a predetermined rule, and to adjust an input voltage signal of the input adjustment buffer stage based on transitions between the first and second work states. When the sample switch is closed, the input adjustment buffer stage is configured to provide an adjusted voltage signal to the input node of the sub-ADC, and the sub-ADC is configured to perform an analog-to-digital conversion onto the adjusted voltage signal.

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Номер записи: 29
28-11-2013 дата публикации

Signal processing circuit

Номер: US20130314141A1
Автор: Junchao Zhou
Принадлежит: Mediatek Singapore Pte Ltd

The present disclosure relates to a signal processing circuit. The signal processing circuit includes a signal selection module, an offset module, and an amplifier module. The signal selection module is configured to select one from a plurality of input signals for outputting at least one first output signal. The voltage offset module is configured to output an offset voltage. The amplifier module, coupled to the signal selection module and the voltage offset module, is configured to ample the first output signal from the signal selection module, and offset the first output signal according to the offset voltage output from the offset voltage module, and perform an amplification gain control and data buffering processes on the offset signal.

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Номер записи: 30
09-01-2014 дата публикации

Hybrid analog-to-digital converter having multiple adc modes

Номер: US20140008515A1
Автор: Liping Deng, Rui Wang, Tiejun Dai
Принадлежит: Omnivision Technologies Inc

A hybrid ADC having a successive approximation register (SAR) ADC mode for generating a bit of a digital signal and a ramp ADC mode for generating an additional bit of the digital signal is disclosed. When in the SAR ADC mode, a control circuit is configured to disable a ramp signal generator; disable a counter; and enable a register to control an offset stage to set the magnitude of an offset voltage that is provided to an input of a comparator of the ADC. When in the ramp ADC mode, the control circuit is configured to enable the ramp signal generator to provide a ramp signal to the input of the comparator; enable the counter to begin providing the digital count in response to the output of the comparator; and disable the register so that the offset stage is not providing the offset voltage.

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Номер записи: 31
16-01-2014 дата публикации

Mixed mode analog to digital converter and method of operating the same

Номер: US20140015702A1
Автор: Jaewon Nam
Принадлежит: Electronics and Telecommunications Research Institute ETRI

An analog to digital converter in accordance with the inventive concept may include a reference voltage generation circuit outputting first and second reference voltages; a decompression part decompressing amplitude of an analog input signal and the first and second reference voltages; a flash ADC converting the decompressed analog input signal into a first digital signal with reference to the decompressed first and second reference voltages; and a successive approximation ADC converting the analog input signal into a second digital signal according to a successive approximation operation with reference to the first digital signal and the first and second reference voltages.

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Номер записи: 32
06-03-2014 дата публикации

Asynchronous analog-to-digital converter having adapative reference control

Номер: US20140062735A1
Автор: Ganesan THIAGARAJAN, Udayan Dasgupta, Venugopal Gopinathan
Принадлежит: Texas Instruments Inc

A method is provided. An analog signal is received. The analog input signal is compared to first and second reference signals to generate a first comparison result, and the first comparison result and a first time stamp corresponding to the first comparison result are registered. A first portion of a digital signal is generated from the first comparison result. At least one of the first and second reference signals is adjusted. A second comparison result is generated if the analog signal reaches an adjusted one of the first and second reference signals within a predetermined interval, and a second portion of the digital signal is generated from the second comparison result.

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Номер записи: 33
06-03-2014 дата публикации

Sampling circuit, a/d converter, d/a converter, and codec

Номер: US20140062742A1
Автор: Junya Nakanishi, Seiko Nakamoto, Yutaka Nakanishi
Принадлежит: Asahi Kasei Microdevices Corp

An A/D converter comprising: a sampling circuit including a continuous section, a sampling and holding section for intermittently sampling an input signal based on an analog signal input from the continuous section to hold and transfer the sampled signal, and a digital section for outputting a signal transferred from the sampling and holding section as a digital signal; and a control circuit for supplying a clock signal in which jitter is not added to the continuous section and supplying a clock signal in which the jitter is added to the sampling and holding section.

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Номер записи: 34
20-03-2014 дата публикации

METHOD AND SYSTEM FOR BROADBAND ANALOG TO DIGITAL CONVERTER TECHNOLOGY

Номер: US20140077981A1
Автор: Gallagher Timothy, Ling Curtis, Rachid Mansour
Принадлежит: MaxLinear, Inc.

Methods and systems are provided for calibrating nonlinearity correction during analog-to-digital conversions on received analog signals. Correction-parameters may be estimated, such as to reduce, when applied to total spectral content, distortion resulting from the nonlinearity in originally-unoccupied spectral regions. Digital signals generated based on sampling of the received analog signals may then be corrected, to remove nonlinearity related distortion, based on the estimated correction-parameters. The nonlinearity correction calibration may be performed during reception and handling of the analog signals. The correction-parameters may be generated based on signals located in particular spectral regions, such as the originally-unoccupied spectral regions. These signals may be injected within the device, into the particular spectral regions, and the signal may have known characteristics to enable estimating the required correction. 120-. (canceled)21. A method , comprising: determining when nonlinearity is exhibited during analog-to-digital conversion of received analog signals;', 'when nonlinearity is exhibited, generating correction estimation parameters associated with the received analog signals, wherein applying the correction estimation parameters to total spectral content reduces distortion in originally-unoccupied spectral regions, the distortion resulting from the nonlinearity; and', 'correcting based on the correction estimation parameters, digital signals generated based on sampling of the received analog signals., 'in a device that performs analog-to-digital conversion22. The method according to claim 21 , comprising calibrating nonlinearity correction in the device during reception and handling of the analog signals.23. The method according to claim 21 , comprising generating the correction estimation parameters based on signals in particular spectral regions.24. The method according to claim 23 , wherein the particular spectral regions correspond ...

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Номер записи: 35
27-03-2014 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20140085119A1
Автор: MASUDA Takaya
Принадлежит: RENESAS ELECTRONICS CORPORATION

The present invention realizes reliably control so that, at the time of AD converting reference voltage, a low-voltage transistor in a reference voltage generating circuit is not destroyed by voltage held in a sample and hold circuit. In a semiconductor device, when an instruction of detecting a reference voltage value is received, a switch control unit controlling switching of an input signal of an internal AD converter temporarily automatically couples an input node of a sample and hold circuit and a ground node and, after that, couples the input node of the sample and hold circuit and an output node of a reference voltage generating circuit. 1. A semiconductor device comprising:a sample and hold circuit;an AD converter for AD (Analog-to-Digital) converting an output of the sample and hold circuit;a signal terminal for receiving an analog signal from the outside;a reference voltage generating circuit for generating and outputting a reference voltage;a switching unit for coupling an input node of the sample and hold circuit to any of the signal terminal, an output node of the reference voltage generating circuit, and a ground node; anda switch control unit for controlling the switching unit in accordance with a control signal,wherein when a first control signal is activated, the switch control unit temporarily couples the input node of the sample and hold circuit with the ground node by the switching unit and, after that, couples the input node of the sample and hold circuit with the output node of the reference voltage generating circuit.2. The semiconductor device according to claim 1 , wherein when the second control signal is activated claim 1 , the switch control unit couples the input node of the sample and hold circuit with the ground node by the switching unit.3. The semiconductor device according to claim 1 ,wherein when the first control signal is activated in the case where a result of AD conversion of last time by the AD converter is equal to or less ...

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Номер записи: 36
03-04-2014 дата публикации

Data processing device and data processing system

Номер: US20140091956A1
Автор: Iso Yoshimi, Kimura Kakeru, Matsushima Tadashi, SHIMIZU Yuji
Принадлежит: Renesas Electronics Corp

In AD conversion of a voltage, data continuity is ensured between the results of conversion after amplification and of direct conversion without amplification. In AD conversion operation, an analog signal output from a DA converter circuit is directly converted by an AD converter circuit, and the analog signal is converted after amplification with an expected gain of 2′. Based on resultant data, a gain of an amplifier circuit and an offset thereof are calculated. An analog signal to be enhanced in bit precision is amplified by the amplifier circuit and converted by the AD converter circuit, the offset is subtracted from the resultant conversion, and the result is multiplied by a ratio of the expected gain to the calculated gain to cancel gain error. Based on data with gain error canceled, acquisition of bit-extended conversion result data is performed to ensure continuity between data having different degrees of bit precision.

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Номер записи: 37
03-04-2014 дата публикации

METHODS AND ARRANGEMENTS FOR HIGH-SPEED ANALOG-TO-DIGITAL CONVERSION

Номер: US20140091960A1
Автор: Ali Isaac, Cowley Nicholas P., Pinson Keith, Suetinov Viatcheslav I.
Принадлежит:

Logic such as hardware and/or code for high-speed analog-to-digital conversion of a signal. Logic may receive an analog signal as an input to a sampling receiver. The sampling receiver may implement a successive approximation register (SAR), analog-to-digital converter (ADC) to produce the digital output. Logic may re-task a comparator of the SAR ADC during a sampling mode to generate a digital comparator output that represents a comparison of a voltage of the charge on a capacitance of the DAC against a threshold reference voltage. The digital comparator output may be applied to the input of automatic gain control (AGC) logic. The AGC logic may receive the digital comparator signal which is representative of one sample of a multiple sample, sample cycle, allowing the AGC logic to generate a gain control signal that is responsive to both total composite average and peak amplitudes. 1. A method , the method comprising:switching a successive approximation register, analog-to-digital converter from a conversion mode, to couple an input signal of the successive approximation register, analog-to-digital converter with a capacitance of a digital-to-analog converter during a sampling mode to charge the capacitance of the digital-to-analog converter in the sampling mode;coupling, by a selection logic, an input of a comparator to a sampling mode reference voltage for a duration of the sampling mode, wherein the sampling mode reference voltage comprises a threshold voltage for the voltage of a charge on the capacitance of the digital-to-analog converter at the input of the comparator;comparing, during the sampling mode, a voltage of the charge on the capacitance of the digital-to-analog converter with the sampling mode reference voltage to determine whether the voltage of the charge on the capacitance is greater than or less than the threshold voltage; andoutputting, during the sampling mode, a digital comparator signal based upon the comparing the voltage of the charge on ...

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Номер записи: 38
10-04-2014 дата публикации

Method for estimating capacitance weight errors and successive approximation analog to digital converter using the same

Номер: US20140097975A1
Автор: Hao-Chiao Hong, Tsung-Yin HSIEH
Принадлежит: National Chiao Tung University NCTU

A method for estimating capacitance weight errors of a digital-to-analog converter and a successive approximation (SA) analog-to-digital converter (ADC) using the same are disclosed, and the SA ADC includes a comparator, a capacitor set, a switch set and a controller. The capacitor set includes a primary capacitor array including a plurality of binary-weighted capacitors, and a secondary capacitor array including a plurality of binary-weighted capacitors with known capacitance weights. The controller controls the switch set and repeats the steps of pre-charging the primary capacitor array, redistributing electric charges to the primary capacitor array and the secondary capacitor array, and performing a successive approximation binary searching on the primary capacitor array and the secondary capacitor array to calculate the capacitance weight error of each capacitor in the primary capacitor array. The calculated capacitance weight errors are used for calibrating the output of the successive approximation ADC.

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Номер записи: 39
10-04-2014 дата публикации

AD CONVERSION CIRCUIT, SEMICONDUCTOR DEVICE, AND AD CONVERSION METHOD

Номер: US20140097978A1
Автор: KUMAKURA Yoshiaki
Принадлежит: FUJITSU SEMICONDUCTOR LIMITED

A reference voltage generator generates a reference voltage at the time of sampling a received input signal. A sampling time controller detects a change in the reference voltage. When the reference voltage rises to a determined threshold, the sampling time controller determines that sampling is completed, and generates a sampling clock in which sampling time is controlled on the basis of an external clock. 1. An AD conversion circuit comprising:a reference voltage generator which generates a reference voltage at the time of sampling a received input signal; anda sampling time controller which detects a change in the reference voltage, which determines at the time of the reference voltage rising to a determined threshold that sampling is completed, and which generates a sampling clock in which sampling time is controlled on the basis of an external clock.2. The AD conversion circuit according to claim 1 , wherein the determined threshold is smaller than a saturation value of the reference voltage.3. The AD conversion circuit according to claim 1 , wherein the sampling time controller makes a comparison between the reference voltage and the determined threshold every determined timing in a first clock cycle of the external clock claim 1 , holds a number of times the comparison is made until the reference voltage rises to the determined threshold claim 1 , and determines the sampling time in a second or later clock cycle of the external clock on the basis of the held number of times the comparison is made.4. A semiconductor device comprising an AD conversion circuit claim 1 , the AD conversion circuit including:a reference voltage generator which generates a reference voltage at the time of sampling a received input signal; anda sampling time controller which detects a change in the reference voltage, which determines at the time of the reference voltage rising to a determined threshold that sampling is completed, and which generates a sampling clock in which sampling ...

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Номер записи: 40
05-01-2017 дата публикации

LOW POWER ANALOG TO DIGITAL CONVERTER

Номер: US20170005670A1
Автор: Ayers James S., Douglas Jonathan P., Duarte David E., Geannopoulos George L., Hodgson J. Keith, Kornfeld Avner, Oshita Takao
Принадлежит:

Described is an analog to digital converter (ADC) which comprises: a sigma-delta modulator to receive an analog signal, the sigma-delta modulator operable to perform chopping to cancel common-mode noise; and one or more counters coupled to the sigma-delta modulator to generate a digital code representative of the analog signal. 1. An apparatus comprising:a reference generator to provide a reference voltage;a sigma-delta modulator coupled to the reference generator, wherein the sigma-delta modulator is to receive an analog signal; anda finite state machine (FSM) coupled to an output of the sigma-delta modulator, wherein the FSM is to provide a digital code representing the analog signal.2. The apparatus of claim 1 , wherein the sigma-delta modulator comprises an amplifier and a circuit for performing auto zero correction of the amplifier.3. The apparatus of claim 2 , wherein the sigma-delta modulator comprises a chopper which is operable to cancel common-mode noise from the amplifier.4. The apparatus of claim 2 , wherein the amplifier and the circuit are part of an integrator.5. The apparatus of claim 2 , wherein the amplifier comprises an inverter.6. The apparatus of comprises a first multiplexer coupled to the reference generator.7. The apparatus of claim 6 , wherein the first multiplexer is controlled by an input of the FSM.8. The apparatus of claim 6 , wherein the first multiplexer is to selectively provide one of the reference voltage or a digital bit to a first switch.9. The apparatus of claim 8 , comprises a first capacitive device coupled to the first switch and the amplifier.10. The apparatus of claim 9 , comprises a second switch to receive the analog signal claim 9 , wherein the second switch is coupled to the first capacitive device.11. The apparatus of comprises a third switch coupled to an output of the amplifier and the second switch.12. The apparatus of comprises:a fourth switch coupled to the second switch; anda second capacitive device coupled in ...

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Номер записи: 41
07-01-2016 дата публикации

ESTIMATION OF IMPERFECTIONS OF A TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTER

Номер: US20160006447A1
Автор: Sundblad Rolf
Принадлежит: ANACATUM DESIGN AB

A method of operating a time-interleaved analog-to-digital converter for conversion of an analog input signal to a digital output signal having a sample rate R comprises, for each of at least some activations of an array of constituent analog-to-digital converters, defining first and second sets of the constituent analog-to-digital converters, feeding the analog input of each analog-to-digital converter of the first set with a reference value for imperfection measurements and clocking each analog-to-digital converter of the first set with one of the timing signals, feeding the analog input of each of analog-to-digital converter of the second set with the analog input signal for generation of an intermediate constituent digital output signal at the digital output and clocking each analog-to-digital converter of the second set with one of the timing signals, wherein no timing signal is used to clock two or more of analog-to-digital converters of the second set. 1. A method of operating a time-interleaved analog-to-digital converter for conversion of an analog input signal to a digital output signal having a sample rate R , wherein the time-interleaved analog-to-digital converter comprises:a timing circuit for generating a number M of timing signals, wherein each timing signal is a time-shifted copy of a clock signal having a period P; andan array of an integer number N of constituent analog-to-digital converters each having an analog input and a digital output, wherein N is equal to M;the method comprising: defining a first set of an integer number K of the constituent analog-to-digital converters and a second set of an integer number L of the constituent analog-to-digital converters, wherein K+L=N, K is at least one and less than N and the first and second sets are non-overlapping;', 'feeding the analog input of each of the constituent analog-to-digital converters of the first set with a reference value for imperfection measurements;', 'clocking each of the ...

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Номер записи: 42
07-01-2021 дата публикации

SAMPLING CIRCUIT

Номер: US20210006256A1
Автор: Blanc Jean-Pierre, DUPERRAY David, Le Tual Stéphane
Принадлежит:

A sampling circuit includes a metal oxide semiconductor (MOS) transistor that includes a third metallization receiving a reference voltage between a first metallization coupled to a source region of the transistor and a second metallization coupled to a drain region of the transistor. 1. A sampling circuit comprising:a metal oxide semiconductor (MOS) transistor comprising, between a first metallization coupled to a source region of the transistor and a second metallization coupled to a drain region of the transistor, a third metallization receiving a reference voltage.2. The circuit of claim 1 , wherein the third metallization has a length shorter than or equal to the length of a gate stack of the transistor.3. The circuit of claim 1 , wherein the third metallization has the same length as a gate stack of the transistor.4. The circuit of claim 1 , wherein the third metallization has a length equal to half the length of a gate stack of the transistor.5. The circuit of claim 1 , wherein the third metallization has a length equal to approximately 20% of the length of a gate stack of the transistor.6. The circuit of claim 1 , wherein the third metallization comprises at least two non-contiguous portions.7. The circuit of claim 6 , wherein the third metallization comprises two non-contiguous portions.8. The circuit of claim 6 , wherein the portions of the third metallization have a length equal to approximately 20% of the length of a gate stack of the transistor.9. The circuit of claim 1 , wherein the reference voltage is a ground potential.10. An analog to digital converter comprising: a source region,', 'a drain region,', 'a channel region disposed between the source region and the drain region,', 'a gate stack disposed over the channel region;', 'an insulating layer disposed over the gate stack;', 'a first via coupling the source region;', 'a first metal line disposed over the insulating layer and electrically coupled to the first via;', 'a second via coupling the ...

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Номер записи: 43
03-01-2019 дата публикации

ERROR CORRECTING ANALOG-TO-DIGITAL CONVERTERS

Номер: US20190007071A1
Автор: NAGARAJAN Viswanathan, NARU Srinivas Kumar Reddy, RAJAGOPAL Narasimhan
Принадлежит:

A pipeline ADC comprising an ADC segment and a digital backend coupled to the ADC segment. In some examples the ADC is configured to receive an analog signal, generate a first partial digital code representing a first sample of the analog signal, and generate a second partial digital code representing a second sample of the analog signal. In some examples the digital backend is configured to receive the first and second partial digital codes from the ADC segment, generate a combined digital code based at least partially on the first and second partial digital codes, determine a gain error of the ADC segment based at least partially on a first correlation of a PRBS with a difference between the first and second partial digital codes, and apply a first correction to the combined digital code based at least partially on the gain error of the ADC segment. 1. An error correcting analog-to-digital converter (ADC) , comprising:a first ADC segment;a second ADC segment coupled to the first ADC segment; and a digital correction circuit coupled to the first ADC segment and the second ADC segment;', a gain error estimation circuit; and', 'a memory error estimation circuit comprising:, 'an error estimation circuit coupled to the digital correction circuit and comprising], 'a digital backend coupled to the first ADC segment and the second ADC segment and comprising2. The error correcting ADC of claim 1 , wherein the first ADC segment comprises:a flash ADC having an input coupled to an input of the first ADC segment and output coupled to the digital correction circuit;a digital-to-analog converter (DAC) having an input coupled to the output of the flash ADC;a subtractor having a first input coupled to the input of the first ADC segment and a second input coupled to an output of the DAC;an adder having a first input coupled to the digital correction circuit and a second input coupled to an output of the subtractor; andan amplifier having an input coupled to an output of the adder ...

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Номер записи: 44
02-01-2020 дата публикации

ANALOG-TO-DIGITAL CONVERTER, ANALOG-TO-DIGITAL CONVERSION METHOD, AND DISPLACEMENT DETECTING APPARATUS

Номер: US20200007139A1
Автор: Kawai Akio, Mugikura Shun
Принадлежит: MITUTOYO CORPORATION

An analog-to-digital converter includes a cycle processing unit and a control unit. The cycle processing unit converts an analog input signal into a digital signal having a plurality of bits by performing a plurality of cycle processing on the analog input signal to acquire values of each bit in order from a higher-order bit to a lower-order bit. The control unit controls the cycle processing unit such that a period of the cycle processing is shortened according to a cycled number of the cycle processing. 1. An analog-to-digital converter comprising:a cycle processing unit configured to convert an analog input signal into a digital signal having a plurality of bits by performing a plurality of cycle processing on the analog input signal to acquire values of each bit in order from a higher-order bit to a lower-order bit; anda control unit configured to control the cycle processing unit such that a period of the cycle processing is shortened according to a cycled number of the cycle processing.2. The analog-to-digital converter according to claim 1 ,wherein “N” represents an integer of 2 or more, andthe cycle processing unit converts the analog input signal into a digital signal having N bits by performing the cycle processing N times on the analog input signal to acquire a 1-bit value in each of the cycle processing.3. The analog-to-digital converter according to claim 2 ,wherein when “τ” represents a time constant of the analog-to-digital converter, and “i” represents an integer of 1 to N, {'br': None, 'i': Ti', 'N−', 'N−, '>τ{(1)ln 2+ln(1)}.'}, 'a period Ti of the cycle processing between (i+1)-th cycle processing and i-th cycle processing is represented by the following expression4. The analog-to-digital converter according to claim 3 ,wherein an input signal used in first cycle processing is the analog input signal,an input signal used in the (i+1)-th cycle processing is a sample signal that is sampled in the i-th cycle processing,in a case where an i-th bit ...

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Номер записи: 45
08-01-2015 дата публикации

INPUT CONFIGURATION FOR ANALOG TO DIGITAL CONVERTER

Номер: US20150009053A1
Автор: Hernes Bjornar
Принадлежит: Hittite Microwave Corporation

A circuit comprising an input, two or more sampling capacitors, means for connecting each sampling capacitor to said input, means for discharging the sampling capacitors to a given voltage in a reset phase, means to use the voltage across the sampling capacitor for further processing in a hold phase, operating the two sampling capacitors in anti-phase such that the reset phase and sampling phase of one channel are performed in the time period the other channel is in hold phase. 1. A circuit comprising:an input; andat least two sampling capacitors arranged in at least two different channels, each sampling capacitor being coupled to the input when in a sampling phase;the sampling capacitors each having a reset phase to provide a given voltage received by the input during the sampling phase, a hold phase for further processing of the given voltage, and an anti-phase where the reset phase and sampling phase of one channel are performed when the reset phase and sampling phase of the other channel are in a hold phase or idle.2. The circuit according to wherein the circuit comprises a first stage of a pipelined ADC.3. The circuit according to wherein the circuit comprises part of a sample-and-hold amplifier.4. The circuit according to wherein the circuit comprises part of a track-and-hold amplifier.5. The circuit according to wherein the circuit comprises part of an input stage of an ADC.6. The circuit according to further comprising a differential configuration.7. A circuit comprising:an input;at least two sampling capacitors arranged two different channels, the sampling capacitors coupled to the input in a sampling phase, the sampling capacitors also having a reset phase to provide a given voltage obtained in the sampling phase;an amplifier comprising one input stage per sampling capacitor and a common output stage, wherein the sampling capacitors anti-phase with respect to each other such that the reset phase and sampling phase of one channel are performed when the ...

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Номер записи: 46
02-01-2020 дата публикации

PIXEL SENSOR HAVING MULTIPLE PHOTODIODES

Номер: US20200007800A1
Автор: Berkovich Andrew Samuel, CHEN Song, Liu Xinqiao, SCHAUB Michael Patrick, Trail Nicholas Daniel
Принадлежит:

In one example, an apparatus comprises: a plurality of photodiodes, one or more charge sensing units, one or more analog-to-digital converters (ADCs), and a controller. The controller is configured to: enable the each photodiode to generate charge in response to a different component of the incident light; transfer the charge from the plurality of photodiodes to the one or more charge sensing units to convert to voltages; receive a selection of one or more quantization processes of a plurality of quantization processes corresponding to a plurality of intensity ranges; based on the selection, control the one or more ADCs to perform the selected one or more quantization processes to quantize the voltages from the one or more charge sensing units to digital values representing components of a pixel of different wavelength ranges; and generate a pixel value based on the digital values. 1. An apparatus comprising:a plurality of photodiodes, each photodiode being configured to convert a component of incident light of a wavelength range to charge;one or more charge sensing units;one or more analog-to-digital converters (ADCs);a memory; and enable the each photodiode to generate charge in response to a different component of the incident light;', 'transfer the charge from the plurality of photodiodes to the one or more charge sensing units to convert to voltages;', 'receive a selection of one or more quantization processes of a plurality of quantization processes corresponding to a plurality of intensity ranges;', 'based on the selection, control the one or more ADCs to perform the selected one or more quantization processes to quantize the voltages from the one or more charge sensing units to digital values representing components of a pixel of different wavelength ranges;', 'store at least some of the digital values in the memory; and', 'generate a pixel value based on the at least some of the digital values stored in the memory., 'a controller configured to2. The ...

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Номер записи: 47
20-01-2022 дата публикации

Signal converting apparatus and related method

Номер: US20220021396A1
Автор: Chun-Chieh Peng, Ta-Shun Chu, Yu-Jiu Wang
Принадлежит: Tron Future Tech Inc

A signal converting apparatus includes a comparing device, a first digital-slope quantizer, and a second digital-slope quantizer. The comparing device having a first input terminal and a second input terminal for receiving a first received signal and a second received signal, and for generating an output signal at an output port. The first digital-slope quantizer generates a first set of digital signals to monotonically adjust the first received signal and the second received signal at the first input terminal and the second input terminal during a first phase according to a first quantization unit. The second digital-slope quantizer generates a second set of digital signals to monotonically adjust the first received signal and the second received signal at the first input terminal and the second input terminal during a second phase after the first phase according to a second quantization unit.

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Номер записи: 48
14-01-2016 дата публикации

DUAL-COMPARATOR CIRCUIT WITH DYNAMIC VIO SHIFT PROTECTION

Номер: US20160011245A1
Автор: Gerber Johannes, KUHN RUEDIGER, QAIYUM ASIF, RUCK BERNHARD
Принадлежит:

A dual-comparator circuit includes a main comparator providing a first decision output (outmain) including a main MOS differential pair, and an auxiliary comparator including an auxiliary MOS differential pair providing a second decision output (outaux). The auxiliary comparator receives a differential input voltage (Vin), and generates a control signal that is coupled to an enable input of the main comparator. A first operating mode (OM) is implemented when |Vin| Подробнее

Номер записи: 49
27-01-2022 дата публикации

CAPACITOR VOLTAGE STACKING PIPELINE ANALOG-TO-DIGITAL CONVERTER (ADC)

Номер: US20220029632A1
Автор: KURAHASHI PETER, MARSHALL MICHAEL JAMES, ZHOU Dacheng
Принадлежит:

Systems and methods are provided for a pipelined analog-to-digital converter (ADC) circuit. The pipelined ADC circuit comprises a plurality of stages. Each stage comprises a differential input configured to receive a differential signal, a multiplying digital-to-analog converter (MDAC) electrically coupled to the input configured to stack voltages of a set of capacitors; a comparator electrically disposed after the MDAC to compare the differential voltages; and a source follower buffer electrically coupled to the first signal line and the second signal line and electrically disposed after the comparator, wherein the MDAC is configured to amplify an output voltage using passive multiplication; and an alignment circuit communicatively connected to a digital bit output of each stage of the plurality of stages, wherein the alignment circuit is configured to delay a digital bit output of each stage for one or more clock cycles and output a digitized representation of a sampled differential signal. 1. An analog-to-digital converter (ADC) sub-circuit stage comprising:a differential input configured to receive a differential signal comprising a positive voltage signal on a first path and a negative voltage signal on a second path;a multiplying digital-to-analog converter (MDAC) electrically coupled to the differential input configured to stack voltages of a set of capacitors;a comparator electrically coupled to the first path and the second path and electrically disposed after the MDAC, a first input of the comparator connected to the first path and a second input of the comparator connected to the second path; anda source follower buffer electrically coupled to the first path and the second path and electrically disposed after the comparator,wherein the MDAC is configured to amplify an output voltage using passive multiplication.2. The ADC sub-circuit stage of claim 1 , further comprising a set of differential switches claim 1 , a first differential switch connected to the ...

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Номер записи: 50
12-01-2017 дата публикации

ANALOG-TO-DIGITAL CONVERTERS FOR SUCCESSIVE APPROXIMATION INCORPORATING DELTA SIGMA ANALOG-TO-DIGITAL CONVERTERS AND HYBRID DIGITAL-TO-ANALOG CONVERTERS WITH CHARGE-SHARING AND CHARGE REDISTRIBUTION

Номер: US20170012633A1
Автор: Bosi Alessandro, Ghittori Nicola, Nani Claudio, Venca Alessandro
Принадлежит:

An A/D converter including a sample and hold circuit, first and second A/D converters and a combination circuit. The sample and hold circuit samples an analog input signal to generate bits. The first A/D converter generate a first digital signal based on the analog input signal and includes charge-sharing and charge-redistribution D/A converters that convert respectively a most-significant-bit and a first least significant bit. The first digital signal is generated based on outputs of the charge-sharing and charge redistribution D/A converters. The second A/D converter generates a second digital signal based on an output of the first A/D converter and includes a delta sigma D/A converter, which converts a second least significant bit. The second digital signal is generated based on an output of the delta sigma D/A converter. The second A/D converter is a fine conversion A/D converter relative to the first A/D converter. 1. An analog-to-digital converter comprising:a sample and hold circuit configured to sample an analog input signal to generate a plurality of bits; a charge-sharing digital-to-analog converter configured to convert a first most-significant-bit of the plurality of bits, and', 'a charge redistribution digital-to-analog converter configured to convert a first least significant bit of the plurality of bits,', 'wherein the first digital signal is generated based on an output of the charge-sharing digital-to-analog converter and an output of the charge redistribution digital-to-analog converter;, 'a first analog-to-digital converter configured to generate a first digital signal based on the analog input signal, comprising'}a second analog-to-digital converter configured to generate a second digital signal based on an output of the first analog-to-digital converter, wherein the second analog-to-digital converter comprises a delta sigma digital-to-analog converter, wherein the delta sigma digital-to-analog converter is configured to convert a second least ...

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Номер записи: 51
12-01-2017 дата публикации

HYBRID CHARGE-SHARING CHARGE-REDISTRIBUTION DAC FOR SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTERS

Номер: US20170012636A1
Автор: Bosi Alessandro, Ghittori Nicola, Nani Claudio, Venca Alessandro
Принадлежит:

A hybrid D/A converter is provided including first and second D/A converters. The first D/A converter receives a digital signal having an input voltage and converts a first most-significant-bit of the digital signal to be converted to an analog signal. The first D/A converter includes first capacitors, which are charged by the input voltage and reference voltages during a sampling phase of the digital signal. Charges of the first capacitors are shared during successive approximations of first bits of the digital input signal received by the hybrid D/A converter. The second D/A converter converts a first least-significant-bit of the digital input signal. The second D/A converter includes second capacitors, which are charged based on a common mode voltage during the sampling phase. The second D/A converter performs charge redistribution by connecting the second capacitors to receive the reference voltages during successive approximations of second bits of the digital signal. 1. A hybrid digital-to-analog converter comprising:a first digital-to-analog converter configured to (i) receive a digital input signal having an input voltage, and (ii) convert a first most-significant-bit of a plurality of bits of the digital input signal to be converted to an analog signal, wherein the first digital-to-analog converter comprises a first plurality of capacitors, wherein the first plurality of capacitors are charged by the input voltage and reference voltages during a sampling phase of the digital input signal, and wherein charges of the first plurality of capacitors are shared during successive approximations of a first one or more bits of the digital input signal received by the hybrid digital-to-analog converter to provide the analog signal; anda second digital-to-analog converter configured to convert a first least-significant-bit of the plurality of bits of the digital input signal to be converted to the analog signal, wherein the second digital-to-analog converter comprises ...

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Номер записи: 52
14-01-2016 дата публикации

SYSTEMS AND METHODS FOR PROVIDING A PIPELINED ANALOG-TO-DIGITAL CONVERTER

Номер: US20160013803A1
Автор: Kinget Peter, KUPPAMBATTI Jayanth, Shen Junhua
Принадлежит:

Systems comprising: a first MDAC stage comprising: a sub-ADC that outputs a value based on an input signal; at least two reference capacitors that are charged to a Vref; at least two sampling capacitors that are charged to a Vin; and a plurality of switches that couple the at least two reference capacitors so that they are charged during a sampling phase, that couple the at least two sampling capacitors so that they are charged during the sampling phase, that couple at least one of the reference capacitors so that it is parallel to one of the at least two sampling capacitors during a hold phase, and that couple the other of the at least two sampling capacitors so that it couples the at least one of the reference capacitors and the one of the at least two sampling capacitors to a reference capacitor of a second MDAC stage. 1. A system for providing a pipelined Analog-to-Digital Converter , comprising: a sub-Analog-to-Digital Converter (ADC) that outputs a value based on an input signal;', 'at least two reference capacitors that are charged to a reference voltage;', 'at least two sampling capacitors that are charged to a sampling voltage; and', 'a plurality of switches that couple the at least two reference capacitors so that they are charged during a sampling phase, that couple the at least two sampling capacitors so that they are charged during the sampling phase, that couple at least one of the reference capacitors so that it is parallel to one of the at least two sampling capacitors during a hold phase, and that couple the other of the at least two sampling capacitors so that it couples the at least one of the reference capacitors and the one of the at least two sampling capacitors to a reference capacitor of a second MDAC stage., 'a first multiplying Digital-to-Analog Converter (MDAC) stage comprising2. The system of claim 1 , wherein the first MDAC stage further comprises a first current source coupled to a first of the at least two reference capacitors and a ...

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Номер записи: 53
15-01-2015 дата публикации

SYSTEM AND METHOD FOR HIGH SPEED ANALOG TO DIGITAL DATA ACQUISITION

Номер: US20150015428A1
Автор: Snelgrove William Martin
Принадлежит:

An analog to digital conversion system is disclosed which converts an analog signal to a digital representation thereof at a first sampling rate by distributing the analog signal to at least two signal paths, at least one signal path including a limiting mixer to mix the signal with a respective selected square wave and a smoothing (low pass) filter to filter the mixed signal before providing the mixed and filtered signal to a subconverter, the subconverter having a sampling rate less than the first sampling rate, and a digital matrix filter to combine the digital output of each subconverter to form a digital representation of the analog signal as sampled at the first rate. 117-. (canceled)18. A method of converting an input analog signal into a digital signal at a conversion sampling rate , the method comprising:distributing the analog signal into at least two signal paths;mixing the analog signal in at least one of the signal paths with a mixing signal;filtering the mixed analog signal in the at least one signal path using a smoothing filter;converting the analog signal in each signal path into a digital signal using an analog to digital subconverter in each signal path, each subconverter having a respective subconverter sampling rate lower than the conversion sampling rate; andcombining the digital signals from the subconverters in each signal path to produce an overall digital output signal corresponding substantially to the input analog signal sampled at the conversion sampling rate, and compensating the overall digital output signal for aliasing artifacts.19. The method of claim 18 , wherein the mixing signal comprises at least two discrete levels.20. The method of claim 18 , wherein the mixing signal comprises one or more pure sine waves.21. The method of claim 18 , wherein the mixing signal comprises one or more clipped sine waves.22. The method of claim 18 , wherein the mixing comprises using an electrical mixer.23. The method of claim 18 , wherein the ...

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Номер записи: 54
11-01-2018 дата публикации

ANALOG-TO-DIGITAL CONVERSION DEVICE

Номер: US20180013443A1
Автор: Chao Chieh-Yuan, KANG Wen-Juh, Wang Ting-Hao
Принадлежит:

An analog-to-digital conversion device is provided that includes a front SAR ADC and a plurality of rear SAR ADCs. The front SAR ADC is configured to convert an analog input signal into a group of higher bits of a digital output signal in response to different time periods. Each of the rear SAR ADCs is electrically coupled to the front SAR ADC and is configured to receive the analog input signal and the corresponding group of higher bits in response to the different time periods. The rear SAR ADCs convert the analog input signal into a group of lower bits of the digital output signal corresponding to the time period of the group of higher bits. 1. An analog-to-digital conversion device comprising:a clock circuit configured to generate p multi-phase clocks;a front successive-approximation analog-to-digital converter (SAR ADC) electrically coupled to the clock circuit, and configured to convert an analog input signal into p groups of higher bits of a digital output signal in response to different time periods according to the p multi-phase clocks; anda plurality of rear SAR ADCs each electrically coupled to the clock circuit and the front SAR ADC, and configured to receive the analog input signal and one of p groups of higher bits corresponding to each other in response to the different time periods according to the p multi-phase clocks, wherein the number of the plurality of rear SAR ADCs equals the number of phases of the p multi-phase clocks, so that the plurality of rear SAR ADCs convert the analog input signal into p groups of lower bits of the digital output signal corresponding to the time period of the p groups of higher bits; anda combining circuit electrically coupled to the clock circuit, the front SAR ADC and the rear SAR ADCs, and configured to receive the p multi-phase clocks and combine the p groups of higher bits and the p groups of lower bits that correspond to the same time period according to the p multi-phase clocks, so as to generate the digital ...

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Номер записи: 55
14-01-2021 дата публикации

APPARATUS AND METHOD FOR MEASURING FREQUENCY OF SIGNAL

Номер: US20210013897A1
Автор: JEONG Un Seob, Jo Sung Jin, JOO Jeung Min, KIM Jung Hoon, Kim Sang Won, Lee Dong Keun
Принадлежит:

Provided are an apparatus and a method for measuring a frequency of a broadband signal by using low-speed ADCs having sub-Nyquist sampling rates. A plurality of channels each including a low-speed ADC having a sub-Nyquist sampling rate (e.g. sampling frequency from several MHz to hundreds of MHz) are provided, and the frequency of an input signal corresponding to a combination of frequencies calculated through the respective channels is estimated. Therefore, as the number of channels increases, the range of measurable frequencies may be extended. 1. A frequency measuring apparatus comprising:a coupler configured to generate an I component and a Q component from an input signal;a distributor configured to distribute the I component and the Q component to a plurality of channels;the plurality of channels each comprising an analog digital convertor (ADC), which is configured to sample an I component and a Q component input thereto and quantize a sampled I component and a sampled Q component, and a frequency measuring unit configured to calculate a frequency from a quantized I component and a quantized Q component; anda frequency estimator configured to detect a signal frequency corresponding to a combination of frequency values respectively calculated in the plurality of channels based on frequency combination information including different signal frequencies and a combination of frequency values respectively corresponding to the signal frequencies,wherein respective ADCs included in the plurality of channels have different sampling speeds for sampling the I component and the Q component,wherein the frequency measuring unitgenerates trajectories corresponding to frequency values calculated in the plurality of channels according to a change of an input signal in a multi-dimensional space according to the number of channels, andwhen the trajectories overlap at least partially, changes a sampling frequency of each channel to satisfy a pre-set minimum distance between the ...

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Номер записи: 56
09-01-2020 дата публикации

Automatic Gain Control Circuit with Background Calibration

Номер: US20200014353A1
Автор: Chen Kuan-Ming, Chiang Benjamin, Kan Meng-Ping, Wang Tzy-Yun
Принадлежит:

An automatic gain control circuit for controlling an LNA for inputting signals carrying packets, the automatic gain control circuit can perform a background calibration in the non-preamble time region of a first packet for pre-determining a gain adjustment to the LNA before the next preamble of a second packet arrives, so that the gain of the LNA can be adjusted immediately according to the pre-determined gain adjustment when the next preamble of the second packet arrives. 1. An automatic gain control circuit , for controlling a first amplifier for inputting signals carrying packets , each packet comprising a preamble field within a preamble time region and a non-preamble field within a non-preamble time region , wherein a mixer is coupled to the first amplifier to receive outputted signals of the first amplifier , wherein said automatic gain control circuit comprises: a power detector for receiving a first signal outputted from the first amplifier and to output a voltage level representing a power level of the first signal , wherein the power detector is coupled to the first amplifier to receive the first signal via a conductive path that does not include said mixer; and a second amplifier coupled to the power detector to adjust said voltage level outputted from the power detector , wherein a gain of the second amplifier is adjusted while in the current non-preamble time region such that the adjusted voltage level falls in a pre-determined range , so that a gain of the first amplifier is capable of being adjusted while in the next preamble time region immediately following the current non-preamble time region , according to the adjusted gain of the second amplifier.2. The automatic gain control circuit as recited in claim 1 , wherein the first amplifier is an LNA (low-noise amplifier).3. The automatic gain control circuit as recited in claim 2 , wherein the signals inputted to the first amplifier are RF signals.4. The automatic gain control circuit as recited in ...

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Номер записи: 57
09-01-2020 дата публикации

FRONT-END RECEIVING CIRCUIT AND METHOD FOR THE SAME

Номер: US20200014394A1
Автор: Huang Shih-Hsiung, LEI Liang-Huan, Lin Jian-Ru
Принадлежит:

A front-end receiving circuit includes a first input terminal receiving a first signal, a second input terminal receiving a second signal, a comparator, a first sampling switch, a first sampling shifting circuit and a control circuit. The first sampling switch is coupled between the first input terminal and the first comparator input terminal. The first sample shifting circuit includes a first capacitor, a first reference voltage source, and a second reference voltage source. In a sampling mode, the control circuit is configured to control the first sampling switch and the second sampling switch to be turned on, and control the first shifting switch to be turned off. In a shifting mode, the control circuit is configured to control the first sampling switch and the second sampling to be turned off, and control the first shifting switch to be turned on. 1. A front-end receiving circuit connected to a back-end circuit , comprising:a first input terminal configured to receive a first signal;a second input terminal configured to receive a second signal;a comparator having a first comparator input terminal and a second comparator input terminal respectively connected to the first input terminal and the second input terminal;a first sampling switch connected between the first input terminal and the first comparator input terminal; a first capacitor having one end connected between the first sampling switch and the first comparator input terminal;', 'a first reference voltage source connected to another end of the first capacitor through a second sampling switch; and', 'a second reference voltage source connected to the another end of the first capacitor through a first shifting switch; and, 'a first sampling shifting circuit, which includesa control circuit, configured to be electrically and respectively coupled to the first sampling switch, the second sampling switch and a control end of the first shifting switch, to control the first sampling switch, the second sampling ...

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Номер записи: 58
21-01-2016 дата публикации

CONFIGURABLE TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTER

Номер: US20160020777A1
Автор: Hägglund Robert, HOLMBRING Staffan, Sundblad Rolf
Принадлежит: ANACATUM DESIGN AB

A time-interleaved analog-to-digital converter for conversion of L analog input signals to L corresponding digital output signals comprises an array of N (N>L) constituent analog-to-digital converters each having an analog input and a digital output and each adapted to digitize an analog input sample, and a controller adapted to (for each of the L analog input signals indexed by i=1, 2, . . . , L) select a number Nof constituent analog-to-digital converters from the array of N constituent analog-to-digital converters (wherein N and ΣN≦N), and cause each sample of the analog input signal to be digitized in a respective one of the selected Nconstituent analog-to-digital converters. The analog-to-digital converter also comprises a multiplexer adapted to (for each of the L analog input signals) multiplex the digitized samples of each of the selected Ni constituent analog-to-digital converters to produce the digital output signal.

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Номер записи: 59
19-01-2017 дата публикации

MULTIPLYING ANALOG TO DIGITAL CONVERTER AND METHOD

Номер: US20170019121A1
Автор: Verma Naveen, Wang Zhuo, ZHANG Jintao
Принадлежит: THE TRUSTEES OF PRINCETON UNIVERSITY

A multiplying analog to digital converter including an analog to digital converter (ADC) having a sample input and a feedback input and an ADC output configured with a feedback path configured to couple the ADC output to a digital to analog converter. A feedback attenuator is disposed in the feedback path, the feedback attenuator being configured to attenuate a feedback signal coupled to the feedback input, the feedback attenuator being configured to provide analog multiplication observed at the ADC output. A barrel shifter is configured to provide digital multiplication of the ADC output. The feedback attenuator may be configured as a divider network. The feedback attenuator may be configured to provide attenuation using only passive components. The feedback attenuator may be configured as a capacitive divider network. The feedback attenuator may be configured to provide attenuation ranging between 1 and 0.5. 1. A multiplying analog to digital converter comprising:an analog to digital converter (ADC) having a sample input and a feedback input and an ADC output configured with a feedback path configured to couple the ADC output to a digital to analog converter;a feedback attenuator disposed in the feedback path, the feedback attenuator being configured to attenuate a feedback signal coupled to the feedback input, the feedback attenuator being configured to provide analog multiplication observed at the ADC output; anda barrel shifter configured to provide digital multiplication of the ADC output.2. The multiplying analog to digital converter of wherein the feedback attenuator is configured as a divider network.3. The multiplying analog to digital converter of wherein the feedback attenuator is configured to provide attenuation using only passive components.4. The multiplying analog to digital converter of wherein the feedback attenuator is configured as a capacitive divider network.5. The multiplying analog to digital converter of wherein the feedback attenuator is ...

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Номер записи: 60
17-04-2014 дата публикации

Analog-to-Digital Conversion With Multiple Kernels

Номер: US20140104089A1
Автор: Pablo Yelamos Ruiz
Принадлежит: INFINEON TECHNOLOGIES AG

An analog-to-digital conversion system includes at least two analog-to-digital conversion units configured to receive a plurality of analog signals and convert the analog signals to digital signals. The system further includes a delay unit including at least one delay circuit, wherein the analog-to-digital conversion system is configured to convey trigger signals to the analog-to-digital conversion units, and wherein at least one of the trigger signals is delayed via the at least one delay circuit.

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Номер записи: 61
03-02-2022 дата публикации

Time-Interleaved Dynamic-Element Matching Analog-to-Digital Converter

Номер: US20220038112A1
Автор: Kee Scott David, Mohta Setu
Принадлежит: AyDeeKay LLC dba Indie Semiconductor

Analog-to-digital converters (ADCs) with a high sampling rate and larger spurious-free dynamic range (SFDR) in the spectral domain are used in many applications, including, but not limited to, range finders, meteorology, spectroscopy, and/or coherent medical imaging. Circuit techniques for time-interleaving a set of low-sampling-rate sub-ADCs into a higher sampling-rate ADC with a larger SFDR than existing approaches are described. In one embodiment, the circuit techniques add a small number of additional units or sub-ADCs. This change in architecture enables a dynamic-selection procedure to time-interleave the set of sub-ADCs in such a way that mismatch-related non-idealities of the constituent sub-ADCs are spread in the frequency domain into a noise-like spectral shape in order to prevent the creation of spurious tones, which would otherwise deleteriously impact the SFDR. 1. An analog-to-digital converter (ADC) , comprising:an input pad or connector configured to receive an input signal;N+K sub-ADCs, selectively electrically coupled to the input pad or connector, configured to sample and convert the input signal into a digital representation, wherein a given sub-ADC operates at an average sampling rate of 1/(N+K) of a sampling rate of an output of the ADC, and wherein N and K are non-zero integers;a merge circuit, electrically coupled to the N+K sub-ADCs, configured to combine output samples from the N+K sub-ADCs into the output of the ADC; anda control circuit, electrically coupled to the N+K sub-ADCs, configured to provide control signals that select a sequence of the N+K sub-ADCs used to sample and convert the input signal.2. The ADC of claim 1 , wherein the selected sequence converts spectral tones in the output from N-periodic into a more-random spectrum.3. The ADC of claim 1 , wherein the control logic is configured to select the sequence based at least in part on one or more spectral tones in a predefined range of frequencies in the output.4. The ADC of ...

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Номер записи: 62
18-01-2018 дата публикации

COMMON MODE REJECTION IN A RESERVOIR CAPACITOR SAR CONVERTER

Номер: US20180019761A1
Автор: Coln Michael C.W.
Принадлежит:

An analog-to-digital converter (ADC) circuit comprises a first digital-to-analog (DAC) circuit and a second DAC circuit, wherein the first and second DAC circuits include weighted bit capacitors and reservoir capacitors; a sampling circuit configured to sample a differential input voltage onto the weighted bit capacitors and to sample a reference voltage onto the reservoir capacitors; a comparator circuit operatively coupled to outputs of the first and DAC circuits; and logic circuitry configured to: initiate successive bit trials of weighted bit capacitors to convert the input voltage to a digital value by comparing an output of the first DAC circuit and an output of second DAC circuit using the comparator circuit; and apply charge of the reservoir capacitors to the bit capacitors to reduce the comparator differential input voltage and reduce an error between the input common mode offset and the comparator common mode offset. 1. An analog-to-digital converter (ADC) circuit comprising:a first digital-to-analog (DAC) circuit and a second DAC circuit, wherein the first and second DAC circuits include weighted bit capacitors and reservoir capacitors;a sampling circuit configured to sample a differential input voltage onto the weighted bit capacitors, and sample a reference voltage onto the reservoir capacitors with respect to a reference common mode;a first comparator circuit operatively coupled to an output of the first DAC circuit and an output of the second DAC circuit to receive a comparator differential input voltage, wherein the first comparator circuit has a comparator common mode offset and the comparator differential input voltage has an input common mode offset; andlogic circuitry coupled to the first and second DAC circuits, the sampling circuit, and the first comparator circuit, the logic circuitry configured to:initiate successive bit trials to convert the input voltage to a digital value, wherein, in a bit trial, a voltage of one or more of the weighted ...

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Номер записи: 63
21-01-2021 дата публикации

SUB-RANGING ANALOG TO DIGITAL CONVERTER

Номер: US20210021278A1
Автор: BELOSTOTSKI Leo, WU Ge, ZAILER Eugene
Принадлежит:

Systems and methods relating to analog-to-digital converters. A delay block receives an input signal at the same time as a coarse ADC (CADC) block. The CADC block produces a multi-bit output and this output is applied to a signal processing block. The delay block delays the input signal from being applied to the signal processing block until the output of the CADC block has been applied/configures the signal processing block. The signal processing block may be a signal shifter, the output of which is ultimately applied to a fine ADC (FADC) block. In an alternative, the signal processing block may be the FADC block. Regardless of the configuration, the output of the CADC is delayed until the output of the FADC block is available. The outputs of the CADC and the FADC blocks are then simultaneously applied to an encoder that produces the overall system output. 1. A system for assigning a digital value to a current or voltage signal level , the system comprising:a coarse ADC block for receiving an input signal and for performing a coarse analog-to-digital conversion process on said input signal; anda delay block for delaying said input signal prior to passing said input signal to a further processing block that is configured based on an output of said coarse ADC block;wherein said delay block delays said input signal to allow said further processing block to be configured by said output of said coarse ADC block and wherein said coarse analog-to-digital conversion process is applied over a full input signal range.2. The system according to claim 1 , wherein said further processing block is a fine ADC block for receiving said input signal from said delay block claim 1 , said fine ADC block being for performing a fine analog-to-digital conversion process on said input signal claim 1 , said fine analog-to-digital conversion process being focused around a voltage level of said input signal.3. The system according to claim 1 , wherein said further processing block is a signal ...

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Номер записи: 64
28-01-2016 дата публикации

Sample-and-Hold Circuit for an Interleaved Analog-to-Digital Converter

Номер: US20160027528A1
Автор: Craninckx Jan, DEGUCHI Kazuaki, Verbruggen Bob
Принадлежит: IMEC VZW

The present disclosure relates to a sample-and-hold circuit includes a transistor arranged for switching between a sample mode and a hold mode and a bootstrap circuit arranged for maintaining in the sample mode a voltage level between a source terminal and a gate terminal of the transistor independent of the voltage at the source terminal and arranged for switching off the transistor in the hold mode. The bootstrap circuit includes a bootstrap capacitance arranged for being precharged to a given voltage during the hold mode, the bootstrap capacitance being connected between the source terminal and the gate terminal during the sample mode. In one example, the bootstrap circuit comprises a switched capacitor charge pump for generating the given voltage. 1. A sample-and-hold circuit comprisinga transistor arranged for switching between a sample mode and a hold mode;a bootstrap circuit arranged for maintaining in the sample mode a voltage level between a source terminal and a gate terminal of the transistor independent of the voltage at the source terminal and arranged for switching off the transistor in the hold mode, the bootstrap circuit comprising a bootstrap capacitance arranged for being precharged to a given charge voltage during the hold mode, the bootstrap capacitance being connected between the source terminal and the gate terminal during the sample mode, wherein the bootstrap circuit comprises a programmable switched capacitor charge pump for generating the given charge voltage to which the bootstrap capacitance is precharged.2. The sample-and-hold circuit as in claim 1 , wherein the switched capacitor charge pump comprises a first capacitor and a second capacitor.3. The sample-and-hold circuit as in claim 2 , wherein the second capacitor is programmable.4. The sample-and-hold circuit as in claim 2 , wherein the first capacitor is arranged to be charged to a supply voltage and the second capacitor is arranged for being discharged claim 2 , the first and ...

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Номер записи: 65
26-01-2017 дата публикации

METHOD AND DEVICE FOR COMPENSATING BANDWIDTH MISMATCHES OF TIME INTERLEAVED ANALOG TO DIGITAL CONVERTERS

Номер: US20170026052A1
Автор: Le Dortz Nicolas, Lelandais-Perrault Caroline, Parida Rakhel Kumar, Simon Thierry, Urard Pascal
Принадлежит:

A device can be used for compensating bandwith mismatches of time interleaved analog to digital converters. A processor of the device determines, for each original sample stream, an estimated difference between the time constant of a low pass filter representative of the corresponding converter and a reference time constant of a reference low pass filter, and uses this estimated difference and a filtered stream to correct the original stream and deliver a corrected stream of corrected samples. 112-. (canceled)13. A method of direct compensation of bandwidth mismatch , the method comprising:receiving M original trains of M original samples from of M time-interleaved converters, M being greater than two, each converter being considered in the first order as comprising a first order low-pass filter;digitally filtering the M original trains delivering M corresponding filtered trains of filtered samples, the filtering having a transfer function substantially equal to the product of a transfer function of a reference low-pass filter and a transfer function of a derivative filter multiplied by a reference time constant of the reference low-pass filter; and performing an estimation process to deliver an estimated difference between the time constant of the first order low-pass filter associated with the corresponding converter and the reference time constant, the estimation process comprising a first generation of a first item of differentiated power information relative to the original train and a second generation of a second item of information of differentiated power relative to at least one of the M filtered trains, and', 'performing a correction process of the original samples of the original train using the filtered samples of the corresponding filtered train and the corresponding estimated difference, in such a way as to deliver a corrected train of corrected samples., 'for each original train of original samples,'}14. The method according to claim 13 , wherein the ...

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Номер записи: 66
26-01-2017 дата публикации

SEMICONDUCTOR DEVICE INCLUDING INTEGRATOR AND SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER AND DRIVING METHOD OF THE SAME

Номер: US20170026053A1
Автор: Lee Choong-Hoon
Принадлежит:

A semiconductor device includes an integrator, a successive approximation register analog-to-digital converter (SAR ADC) and a residue capacitor. The integrator is configured to receive a signal and generate a first analog signal during a first operation mode using a capacitor module comprising one or more capacitors. The SAR ADC is configured to receive the first analog signal, convert the first analog signal into a first digital signal using the capacitor module, and generate a first residue signal in a second operation mode. The residue capacitor is connected to the capacitor module in parallel, and is configured to receive the first residue signal in the second operation mode and provide the first residue signal to the integrator in the first operation mode. 1. A semiconductor device comprising:an integrator configured to receive a signal and generate a first analog signal responsive to the received signal in a first operation mode using a capacitor module comprising one or more capacitors;a successive approximation register analog-to-digital converter (SAR ADC) configured to receive the first analog signal, convert the first analog signal into a first digital signal using the capacitor module, and generate a first residue signal in a second operation mode; anda residue capacitor connected to the capacitor module in parallel, the residue capacitor configured to receive the first residue signal in the second operation mode and provide the first residue signal to the integrator in the first operation mode.2. The semiconductor device of claim 1 , wherein the integrator is configured to receive the first residue signal generated by the SAR ADC to generate a second analog signal claim 1 , and the SAR ADC is configured to convert the second analog signal into a second digital signal.3. The semiconductor device of claim 2 , further comprising:an output unit configured to combine the first digital signal and the second digital signal to generate an output signal.4. The ...

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Номер записи: 67
28-01-2016 дата публикации

PIPELINED ANALOG-TO-DIGITAL CONVERTER

Номер: US20160028412A1
Автор: Liu Song, WU Ke, YANG Feiqin
Принадлежит:

The invention provides a pipelined analog-digital converter (ADC) and pertains to the technical field of integrated circuit (IC) design. The pipelined ADC at least comprises: a sampling holder, n multiplier digital-analog converters that are connected stage by stage, a clock generator, a reference generator and a digital encoder, wherein at least the sampling holder and n multiplier digital-analog converters are substantially arranged in a loop so as to form an intermediate area in an encircling manner; the clock generator and the reference generator are disposed in the intermediate area so that the clock generator and the reference generator respectively provide corresponding signal inputs to the surrounding n multiplier digital-analog converters in a star connection. The pipelined ADC has an excellent performance and is in particular applicable to high speed/high accuracy application. 1. A pipelined analog-digital converter (ADC) , at least comprising:n multiplier digital-analog converters that are connected stage by stage,a clock generator,a reference generator, anda digital encoder;characterized in that at least n multiplier digital-analog converters are substantially arranged in a loop so as to form an intermediate area in an encircling manner; the clock generator and the reference generator are disposed in the intermediate area so that the clock generator and the reference generator respectively provide corresponding signal inputs to the surrounding n multiplier digital-analog converters in a star connection;wherein n is an integer larger than or equal to 2.2. The pipelined ADC according to claim 1 , characterized in that the pipelined ADC further comprises a power bus for supplying power claim 1 , wherein the power bus is arranged substantially in a loop so as to surround therein the sampling holder and n multiplier digital-analog converters connected stage by stage.3. The pipelined ADC according to claim 2 , characterized in that the power bus is arranged in ...

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Номер записи: 68
24-04-2014 дата публикации

Apparatus, method and system for cancelling an input-referred offset in a pipeline adc

Номер: US20140111361A1
Автор: Kalyan Ghatak
Принадлежит: LSI Corp

An apparatus, method and system for offset compensation in a pipeline analog-to-digital converter. A group of capacitors includes one or more sampling capacitors and one or more feedback capacitors, wherein an input to the pipeline analog-to-digital converter circuit is connected to group of capacitors. An amplifier includes a non-inverting input terminal connected to a ground and an inverting input connected to the group of capacitors. The sampling and feedback capacitors are both partitioned in the same ratio to form partitioned capacitors such that a smaller of the partitioned capacitors is employed for offset compensation with respect to the pipeline analog-to-digital converter.

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Номер записи: 69
10-02-2022 дата публикации

TWO-STAGE AUDIO GAIN CIRCUIT BASED ON ANALOG-TO-DIGITAL CONVERSION AND AUDIO TERMINAL

Номер: US20220045658A1
Автор: ALPMAN Erkan, DUSTER Jon Sweat, FENG Haigang, TAN Yulin, ZHANG Liuan, Zhang Ning
Принадлежит: Radiawave Technologies Co., Ltd.

Disclosed are a two-stage audio gain circuit based on analog-to-digital conversion and an audio terminal. The two-stage audio gain circuit includes a PGA configured to receive an analog audio signal and perform programmable gain amplification processing on the received analog audio signal; an ADC configured to convert the analog audio signal after the programmable gain amplification processing into a digital audio signal and output the digital audio signal; a first AGC gain unit configured to perform a first AGC processing on the digital audio signal and output a first gain adjustment value to the PGA, for the PGA to perform gain adjustment on the received analog audio signal; and a second AGC gain unit configured to perform a second AGC processing on the digital audio signal and output a second gain adjustment value to the PGA, for the PGA to perform gain adjustment on the received analog audio signal. 1. A two-stage audio gain circuit based on analog-to-digital conversion , comprising:a programmable gain amplifier (PGA) configured to receive an analog audio signal and perform programmable gain amplification processing on the received analog audio signal;an analog-to-digital converter configured to convert the analog audio signal after the programmable gain amplification processing into a digital audio signal and output the digital audio signal;a first automatic gain control (AGC) gain unit configured to perform a first AGC processing on the digital audio signal and output a first gain adjustment value to the PGA, for the PGA to perform gain adjustment on the received analog audio signal according to the first gain adjustment value; anda second AGC gain unit configured to perform a second AGC processing on the digital audio signal and output a second gain adjustment value to the PGA, for the PGA to perform gain adjustment on the received analog audio signal according to the second gain adjustment value.2. The two-stage audio gain circuit based on analog-to-digital ...

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Номер записи: 70
10-02-2022 дата публикации

PRE-DRIVE MODULE OF ANALOG-TO-DIGITAL CONVERTER, AND ANALOG-TO-DIGITAL CONVERSION DEVICE

Номер: US20220045688A1
Автор: ALPMAN Erkan, DUSTER Jon Sweat, FENG Haigang, Guo Xiaofeng, TAN Yulin, Zhang Ning
Принадлежит: Radiawave Technologies Co., Ltd.

Disclosed are a pre-drive module of an analog-to-digital converter and an analog-to-digital conversion device. The pre-drive module includes a sampling capacitor; a controller configured to output a reset control signal, a pre-sampling control signal, and a sampling control signal according to a preset timing sequence; a reset module configured to reset the sampling capacitor upon receiving the reset control signal; a first auxiliary drive circuit configured to amplify an input analog signal and output to the sampling capacitor for sampling upon receiving the sample control signal; and a second auxiliary drive circuit. The controller is configured to output the pre-sampling control signal before outputting the sampling control signal, control the second auxiliary drive circuit to amplify the input analog signal, and output to the sampling capacitor for pre-sampling, and when a charging voltage of the sampling capacitor during pre-sampling reaches a preset voltage value, output the sampling control signal. 1. A pre-drive module of an analog-to-digital converter , comprising:a sampling capacitor;a controller configured to output a reset control signal, a pre-sampling control signal, and a sampling control signal according to a preset timing sequence;a reset module configured to reset the sampling capacitor upon receiving the reset control signal;a first auxiliary drive circuit configured to amplify an input analog signal and output the amplified input analog signal to the sampling capacitor for sampling upon receiving the sample control signal; anda second auxiliary drive circuit;wherein the controller is configured to output the pre-sampling control signal before outputting the sampling control signal, control the second auxiliary drive circuit to amplify the input analog signal, and output the amplified input analog signal to the sampling capacitor for pre-sampling, and, the controller is further configured to output the sampling control signal when a charging ...

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Номер записи: 71
02-02-2017 дата публикации

SYMMETRICAL CAPACITOR ARRAYS SUCCESIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTER (ADC)

Номер: US20170033800A1
Автор: Ng Kian Ann, Xu Yong Ping, Yuan Chao
Принадлежит:

Analog-to-digital converter (ADC) circuitry includes a first binary-weighted capacitor array having a total capacitance of 2C. The value of n represents number of bits of a digital signal that represents an analog signal. The ADC circuitry also includes a second binary-weighted capacitor array having a total capacitance of 2C. In addition to that, the ADC circuitry further includes a comparator circuit having first and second terminals. The first terminal is coupled to the first binary-weighted capacitor array, and the second terminal is coupled to the second binary weighted capacitor array. The switching circuit within the second binary-weighted capacitor array may be configurable to couple a largest capacitance capacitor within the second binary-weighted capacitor array from remaining capacitors within the second binary weighted capacitor array. 1. Analog-to-digital converter (ADC) circuitry , comprising:{'sup': 'n-2', 'first and second binary-weighted capacitor arrays, wherein each first and second binary-weighted capacitor array is having a total capacitance of 2C, wherein n represents a number of bits of a digital signal representing an analog signal;'}a comparator circuit having first and second terminals, wherein the first terminal is coupled to the first binary-weighted capacitor array, and the second terminal is coupled to the second binary weighted capacitor array; anda switching circuit within the second binary-weighted capacitor array is configurable to couple a largest capacitance capacitor within the second binary-weighted capacitor array from remaining capacitors within the second binary weighted capacitor array.2. The ADC circuitry of claim 1 , wherein the first binary-weighted capacitor array includes a plurality of capacitors arranged parallel to each other claim 1 , wherein capacitances for the capacitors are based on a sequence that follows 2 claim 1 , where a value of the m decreases from m=n to m=3.3. The ADC circuitry of claim 2 , wherein the ...

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Номер записи: 72
12-02-2015 дата публикации

CONTINUOUS-TIME OVERSAMPLING PIPELINE ANALOG-TO-DIGITAL CONVERTER

Номер: US20150042501A1
Автор: SHIBATA Hajime
Принадлежит: ANALOG DEVICES TECHNOLOGY

A converter may include multiple converter stages connected in series. Each converter stage may receive a clock signal and an analog input signal, and may generate an analog output signal and a digital output signal. Each converter stages may include an encoder generating the digital output signal, a decoder generating a reconstructed signal, a delaying converter generating a delayed signal, and an amplifier generating a residue signal, wherein the delayed signal may be a continuous current signal. 120-. (canceled)21. A pipelined analog-to-digital converter (ADC) , comprising: a delay unit to generate an analog input current signal representing a delayed version of an analog input voltage signal;', 'an encoder circuit including a plurality of encoders to generate a plurality of digital output signals based on the analog input voltage signal and a plurality of interleaved clock signals;', 'a decoder circuit including a plurality of decoders to generate a plurality of analog output current signals based on the digital output signals and the plurality of interleaved clock signals; and', 'a subtraction circuit to generate a residue signal based on the analog input current signal and at least one of the plurality of analog output current signals., 'at least one pipeline stage including22. The pipelined ADC of claim 21 , wherein the analog input current signal is delayed from the analog input voltage signal by a predetermined period of time.23. The pipelined ADC of claim 22 , wherein the predetermined period of time is based on a period of the plurality of interleaved clock signals.24. The pipelined ADC of claim 21 , wherein the analog input current signal is delayed from the analog input voltage signal by 1.5 times a period of the plurality of interleaved clock signals.25. The pipelined ADC of claim 21 , wherein each of the plurality of encoders generates a respective one of the plurality of digital output signals at a different time based on a respective different one ...

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Номер записи: 73
11-02-2016 дата публикации

Method and system for Time Interleaved Analog-To-Digital Converter Timing Mismatch Estimation And Compensation

Номер: US20160043731A1
Автор: Anandakumer Anand, Chen Xuefeng, Gallagher Timothy Leo, Taluja Pawandeep, Ye Sheng, Zhu Mingrui
Принадлежит:

Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may comprise receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is aliased onto a desired signal by a timing offset in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal. A decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients. 120-. (canceled)21. A method for wireless communication , the method comprising:receiving an analog signal on a chip;converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC); andreducing a blocker signal that is aliased onto a desired digital signal by a timing offset in said time interleaved ADC, by estimating complex coupling coefficients between said desired digital signal and said blocker signal.22. The method according to claim 21 , comprising estimating said complex coupling coefficients utilizing a decorrelation algorithm running in timing offset estimation and compensation circuitry.23. The method according to claim 21 , comprising approximating an amplitude of a blocker signal as linear within a desired frequency bandwidth.24. The method according to claim 21 , comprising performing a foreground estimation and timing offset compensation by generating the received analog signal utilizing a calibration tone generator on said chip.25. The method ...

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Номер записи: 74
09-02-2017 дата публикации

CONTINUOUS TRACKING OF MISMATCH CORRECTION IN BOTH ANALOG AND DIGITAL DOMAINS IN AN INTERLEAVED ADC

Номер: US20170041011A1
Автор: BALAKRISHNAN Jaiganesh, Ramakrishnan Sthanunathan, Venkatraman Sashidharan
Принадлежит:

A system. The system includes a first tracking filter configured to track a frequency domain mismatch profile between component analog-to-digital convertors (ADCs) of an interleaved ADC (IADC), and a second tracking filter configured to a track a frequency independent timing delay mismatch and a timing delay mismatch correction error based on frequency domain mismatch profile estimates. An output of the first tracking filter determines a correction of a frequency dependent mismatch profile in an output of the interleaved ADC and an output of the second tracking filter determines a correction of the timing delay mismatch correction error in the output of the interleaved ADC. 1. A. system comprising:a first tracking filter configured to track a frequency domain mismatch profile between component analog-to-digital convertors (ADCs) of an interleaved ADC (IADC); 'an output of the first tracking filter determines a correction of a frequency dependent mismatch profile in an output of the interleaved ADC and an output of the second tracking filter determines a correction of the timing delay mismatch correction error in the output of the interleaved ADC.', 'a second tracking filter configured to a track a frequency independent timing delay mismatch and a timing delay mismatch correction error based on frequency domain mismatch profile estimates; and wherein2. The system of further comprising control logic coupled to the first and second tracking filters claim 1 , and wherein the control logic is configured to:couple the frequency domain mismatch profile estimate to the first and second tracking filters in a first correction phase; andcouple a difference of the frequency domain mismatch profile estimate and an output of the first tracking filter to the second tracking filter in a second correction phase.3. The system of wherein the control logic is further configured to couple the difference of the frequency domain mismatch profile estimate and an output of the first ...

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Номер записи: 75
09-02-2017 дата публикации

AMPLIFIER SHARING TECHNIQUE FOR POWER REDUCTION IN ANALOG-TO-DIGITAL CONVERTER

Номер: US20170041012A1
Автор: Cao Peng, GUPTA Amit Kumar, Kidambi Srinivasan Venkata Krishnan
Принадлежит:

A dual delta-sigma modulator includes a first modulator, a second modulator, and a shared amplifier coupled to the first and second modulators. The first modulator includes an integrator configured to generate a first modulator output signal. The second modulator includes a second integrator configured to generate a second modulator output signal. The shared amplifier is configured to assist the first integrator integrating a difference between a first analog input signal and a first modulator output signal from the first modulator during a first period of time and to assist the second integrator integrate a difference between a second analog input signal and a second modulator output signal from the second modulator during a second period of time. 1. A dual delta-sigma analog-to-digital converter (ADC) , comprising: a first modulator including a first integrator configured to integrate a difference between the analog input signal and a current modulator output signal of the first modulator during a first period of time, hold a first integrator output value by a first low power amplifier during a second period of time, and generate a first modulator output signal;', 'a second modulator including a second integrator configured to hold a second integrator output value during the first period of time, integrate a difference between the analog input signal and a current modulator output signal of the second modulator during the second period of time, and generate a second modulator output signal; and', 'a shared operational amplifier configured to assist the first modulator during the first period of time and to assist the second modulator during the second period of time;, 'a dual delta-sigma modulator configured to receive an analog input signal, the dual delta-sigma modulator includingan interleaver configured to interleave the first modulator output signal and the second modulator output signal to generate an interleaved output signal; anda decimation filter ...

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Номер записи: 76
09-02-2017 дата публикации

DRIVER ARRANGEMENT AND METHOD FOR PROVIDING AN ANALOG OUTPUT SIGNAL

Номер: US20170041017A1
Автор: "DAbramo Paolo", Biagi Edoardo, Fanucci Luca, Piro Luigi Di, Serventi Riccardo
Принадлежит:

A driver arrangement () comprises a digital controller () that is configured to receive a digital input signal (SDI) and a driver () that comprises a driver input () and a driver output () and is configured to provide an analog output signal (SANO) at the driver output (). The driver arrangement () comprises a coupling circuit () that comprises a digital-to-analog converter () and a feedback circuit (). The digital-to-analog converter () comprises a converter input () coupled to the digital controller () and a converter output () coupled to the driver input (). The feedback circuit () is coupled to the driver output () and to a feedback input () of the digital controller (). 1. A driver arrangement , comprising:a digital controller that is configured to receive a digital input signal,a driver that comprises a driver input and a driver output and is configured to provide an analog output signal at the driver output,a coupling circuit that comprises a digital-to-analog converter, a feedback circuit and a change-over switch anda hold circuit that is arranged between the change-over switch and the driver input,wherein the digital-to-analog converter comprises a converter input coupled to the digital controller and a converter output andthe feedback circuit is coupled to the driver output and to a feedback input of the digital controller,wherein in a driving phase, the converter output is coupled to the driver input via the change-over switch and the hold circuit andin a sense phase, the converter output is connected to an input of the feedback circuit via the change-over switch andwherein the driving phase follows the sense phase that in turn follows a previous driving phase,wherein the coupling circuit is designed to convert the analog output signal into a digital feedback signal in the sense phase by a successive approximation register principle by means of the digital-to-analog converter and the feedback circuit and to provide the digital feedback signal to the ...

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Номер записи: 77
08-02-2018 дата публикации

METHOD AND SYSTEM FOR BROADBAND ANALOG TO DIGITAL CONVERTER TECHNOLOGY

Номер: US20180041219A1
Автор: Gallagher Timothy, Ling Curtis, Rachid Mansour
Принадлежит:

Nonlinearity correction in a device that performs analog-to-digital conversion on received analog signals, may be calibrated by generating correction-parameters estimation which when applied to the total spectral content reduces distortion resulting from said nonlinearity in originally-unoccupied spectral regions. Digital signals generated based on sampling of the received analog signals may then be corrected, to remove nonlinearity related distortion, based on the estimated correction-parameters. The nonlinearity calibration may be performed during reception and handling of said analog signals. The correction-parameters may be generated based on signals located in particular spectral regions, such as the originally-unoccupied spectral regions. These signals may be injected within the device, into the particular spectral regions, and the signal may have known characteristics to enable estimating the required correction. 1. A method , comprising:in a device that performs analog-to-digital conversion, calibrating nonlinearity associated with analog-to-digital conversion of received analog signals, said calibrating comprises generating correction estimation parameters, wherein applying said correction estimation parameters to total spectral content reduces distortion in originally-unoccupied spectral regions, said distortion resulting from said nonlinearity; andcorrecting based on said correction estimation parameters, digital signals generated based on sampling of said received analog signals.2. The method according to claim 1 , comprising performing said calibration during reception and handling of said analog signals.3. The method according to claim 1 , comprising generating said correction estimation parameters based on signals in particular spectral regions.4. The method according to claim 3 , wherein said particular spectral regions correspond to said originally-unoccupied spectral regions.5. The method according to claim 3 , comprising injecting specific signals ...

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Номер записи: 78
08-02-2018 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20180041220A1
Автор: Nakano Shunsuke, USUI Masaaki
Принадлежит:

An object of the present invention is to shorten time required for detecting disconnection in an input terminal of an A/D conversion circuit. A semiconductor device includes a first input channel that couples a first input terminal and an A/D conversion unit to each other, a second input channel that couples a second input terminal and the A/D conversion unit to each other, and a control circuit unit that separates the second input channel from the second input terminal and the A/D conversion unit to charge or discharge the second input channel when a signal input into the first input terminal is sampled by the A/D conversion unit. 1. A semiconductor device comprising:a first input terminal configured to receive a first voltage;a second input terminal configured to receive a second input voltage;a signal transmission circuit that selects one of the first and second input terminals;an A/D conversion circuit that couples to the selected input terminal; anda comparison determination circuit that compares an output signal from the A/D conversion circuit with a first voltage and detects a disconnection of the second input terminal,wherein the second input terminal couples to the signal transmission circuit through a channel,wherein the second input voltage has a voltage range between a second voltage and a third voltage lower than the first voltage, the second voltage being lower than the first voltage;wherein when the signal transfer circuit selects the first input terminal, the channel is coupled to the first voltage,wherein when the signal transfer circuit selects the second input terminal after the selection of the first input terminal, the comparison determination circuit detects the disconnection upon a match result of the comparison.2. The semiconductor device according to claim 1 , further comprising a central processing unit (CPU) claim 1 , whereinwhen the comparison determination circuit detects the disconnection, the comparison determination circuit outputs an ...

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Номер записи: 79
08-02-2018 дата публикации

ANALOGUE-DIGITAL CONVERTER OF NON-BINARY CAPACITOR ARRAY WITH REDUNDANT BIT AND ITS CHIP

Номер: US20180041221A1
Автор: Chen Guangbing, Hu Gangyi, Liu Lu, Xu Daiguo, Xu Shiliu
Принадлежит: No. 24 Research Institute of China Electronics Technology Group Corporation

An analog-to-digital converter of non-binary capacitor array with redundancy bits and its chip. The non-binary capacitor array with redundancy bits comprises a common-mode voltage, analog signal input, no less than one redundancy bit capacitor and multiple capacitors; each capacitor of capacitors with redundancy bits and multiple capacitors is connected in parallel between common-mode voltage and analog signal input and marked in a sequence from highest to lowest/lowest to highest bit; the sum of the capacitance of capacitors from the lowest bit capacitor to an random capacitor must be no less than the capacitance of the higher bit capacitor adjacent to the random capacitor. The ratio of the capacitance of each capacitor to the capacitance of unit capacitor is set to be positive. The capacitor array is applied into an analog-to-digital converter or fabricated as a chip. 1. A non-binary capacitor array with redundancy bits for analog sampling , characterized in that , including a common-mode voltage , analog signal input , no less than one capacitor with redundancy bits and multiple capacitors , whereinall capacitors of said no less than one capacitor with redundancy bits and multiple capacitors are connected in parallel between common-mode voltage and analog signal input and marked in a sequence from highest to lowest/lowest to highest bit; the sum of the capacitance of capacitors from the lowest bit capacitor to an random capacitor must be no less than the capacitance of the higher bit capacitor adjacent to the random capacitor. The ratio of the capacitance of each capacitor to the capacitance of unit capacitor is set to be positive.2. The non-binary capacitor array with redundancy bits according to claim 1 , characterized in that claim 1 , the capacitance of each capacitor with redundancy bits is no less than the minimum capacitance among multiple capacitors and no larger than the maximum capacitance among multiple capacitors.3. The non-binary capacitor array with ...

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Номер записи: 80
07-02-2019 дата публикации

DIGITAL-TO-ANALOG CONVERTER (DAC) WITH ENHANCED DYNAMIC ELEMENT MATCHING (DEM) AND CALIBRATION

Номер: US20190044524A1
Автор: Chandra Gaurav, Swaroop Shantha Murthy Prem, Zeng Tao
Принадлежит:

In a digital-to-analog converter (DAC) that includes one or more conversion circuits, with each conversion circuit configured to handle one or more bits in an input signal to the DAC, one or more types of errors that occur during operation of the DAC may be detected, and one or more adjustments may be determined for correcting the one or more types of errors that occur during operation of the DAC and/or for reducing effects resulting from the one or more types of errors. At least one of the one or more adjustments may applied, with the at least one of the one or more adjustments is applied to only a subset of one or more conversion circuits. The DAC may be adaptive switched among a plurality of modes, and adjustments may be applied only in one or more of the modes but not in all of the modes. 1. A system comprising: one or more conversion circuits, wherein each conversion circuit is configured to handle one or more bits in an input to the DAC; and', detect one or more types of errors that occur during operation of the DAC;', 'determine one or more adjustments for correcting the one or more types of errors that occur during operation of the DAC and/or for reducing effects resulting from the one or more types of errors;', 'apply at least one of the one or more adjustments, wherein the one or more control circuits are configured to apply at least one of the one or more adjustments to only a subset of the one or more conversion circuits., 'one or more control circuits configured to apply], 'a digital-to-analog converter (DAC) that is configured to apply digital-to-analog conversions, the DAC comprising2. The system of claim 1 , wherein the DAC is configured to switch among a plurality of modes; andthe one or more control circuits are configured to apply adjustments only in one or more of the plurality of modes but not in all of the plurality of modes.3. The system of claim 2 , wherein the plurality of modes comprises a normal mode and a correction mode; andthe one or ...

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Номер записи: 81
07-02-2019 дата публикации

APPARATUS AND METHOD FOR SINGLE TEMPERATURE SUBTHRESHOLD FACTOR TRIMMING FOR HYBRID THERMAL SENSOR

Номер: US20190044528A1
Автор: LEE Hyung-Jin, Lu Cho-ying
Принадлежит: Intel Corporation

An apparatus is provided which comprises: a thermal sensor comprising one or more n-type devices or p-type devices that suffer from subthreshold factor variation, wherein the thermal sensor is to generate an output digital code representing a temperature; and a calibration circuitry coupled to the thermal sensor, wherein the calibration circuitry is to trim the effects of subthreshold factor variation from the output digital code. 1. An apparatus comprising:a first circuitry to compare a proportional-to-absolute-temperature (PTAT) voltage and a complementary-to-absolute-temperature (CTAT) voltage;an analog-to-digital converter (ADC) coupled to the first circuitry, wherein the ADC is to provide a digital code representing a temperature;a second circuitry to generate temperature independent first and second voltages;a first switch coupled to a node providing the CTAT voltage; anda second switch coupled to the second circuity and to the node providing the CTAT voltage, wherein the second switch is to provide one of the first or second voltages.2. The apparatus of claim 1 , wherein the PTAT voltage is derived from one or more n-type devices or p-type devices in weak inversion.3. The apparatus of claim 1 , wherein the CTAT voltage is generated by a p-n junction diode.4. The apparatus of comprises logic to trim the digital code for subthreshold factor variation claim 1 , wherein the output of the logic is a trimmed digital code.5. The apparatus of comprises a finite state machine claim 1 , wherein the first and second switches are controllable by the finite state machine.6. The apparatus of claim 1 , wherein the ADC is to implement a successive approximation algorithm.7. The apparatus of claim 1 , wherein the first circuity is part of a thermal sensor claim 1 , and wherein the secondary circuitry is part of a built-in-self-test circuitry.8. The apparatus of comprises:a first memory to store the digital code during a first temperature;a second memory to store the digital ...

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Номер записи: 82
18-02-2021 дата публикации

Track and Hold Circuit

Номер: US20210050860A1
Автор: Fukuyama Hiroyuki, Miura Naoki, Nosaka Hideyuki
Принадлежит:

Provided is a track-and-hold circuit capable of reducing the power consumption of a differential amplifier circuit while preserving the broadband nature (without narrowing the bandwidth). In the track-and-hold circuit including a differential amplifier circuit a switch circuit and a hold capacitor C, the differential amplifier circuit includes a first resistor Rhaving one end connected to a collector electrode of a first transistor Qconstituting a differential pair, a second resistor Rhaving one end connected to the collector electrode of a second transistor Qconstituting the differential pair, and a third resistor Rto which the other end of the first resistor Rand the other end of the second resistor Rare connected and which is connected between the other ends and a power supply V. 1. A track-and-hold circuit comprising:a differential amplifier circuit;a switch circuit; anda hold capacitor,wherein the differential amplifier circuit includesa first resistor having one end connected to a collector electrode of a first transistor constituting a differential pair,a second resistor having one end connected to a collector electrode of a second transistor constituting the differential pair, anda third resistor to which the other end of the first resistor and the other end of the second resistor are connected and which is connected between the other ends and a power supply.2. A track-and-hold circuit comprising:a differential amplifier circuit;a switch circuit; anda hold capacitor,wherein the differential amplifier circuit includesa fourth resistor connected between respective collector electrodes of a first transistor and a second transistor constituting a differential pair,a fifth resistor connected between the collector electrode of the first transistor and a power supply, anda sixth resistor connected between the collector electrode of the second transistor and the power supply.3. The track-and-hold circuit according to claim 1 ,wherein the switch circuit includes ...

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Номер записи: 83
18-02-2016 дата публикации

N-Path Interleaving Analog-to-Digital Converter (ADC) with Offset gain and Timing Mismatch Calibration

Номер: US20160049949A1
Автор: Mikko Waltari
Принадлежит: IQ Analog Corp

A system and method are provided for calibrating timing mismatch in an n-path time interleaved analog-to-digital converter (ADC). The method digitizes an analog signal with an n-path interleaved ADC, creating an interleaved ADC signal. In a first process, the phase of the interleaved ADC signal is rotated by 90 degrees, creating a rotated signal. This rotation may be accomplished using a finite impulse response (FIR) filter with taps at {0.5, 0, −0.5}, enabled as a derivative filter, or as a Hilbert transformation. In a parallel second process, the interleaved ADC signal is delayed, creating a delayed signal. The rotated signal is multiplied by the delayed signal to create a timing error signal. Using the timing error signal, timing errors are accumulated for the ADC signal paths, and corrections are applied that minimize timing errors in each of the n ADC signal paths.

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Номер записи: 84
06-02-2020 дата публикации

ANALOG-TO-DIGITAL CONVERTER CIRCUIT AND METHOD FOR ANALOG-TO-DIGITAL CONVERSION

Номер: US20200044660A1
Автор: RUYTHOOREN Koen, Xhakoni Adi
Принадлежит:

In one embodiment an analog-to-digital converter circuit has an input for receiving a first analog signal level and a second analog signal level, a ramp generator adapted to provide a ramp signal, a comparison unit coupled to the input and the ramp generator, a control unit coupled to the comparison unit the control unit having a counter, the control unit being prepared to enable the counter as a function of a comparison of the ramp signal with the first analog signal level and the second analog signal level, and an output for providing an output digital value as a function of a relationship between the first analog signal level and the second analog signal level. Therein the ramp signal has at least one linearly rising and at least one linearly falling portion and an adjustable shift at a reversal point between the rising and the falling portion of the ramp signal, the shift depending on the number of rising and falling portions of the ramp signal. 1. An analog-to-digital converter circuit havingan input for receiving a first analog signal level and a second analog signal level,a ramp generator adapted to provide a ramp signal,a comparison unit coupled to the input and the ramp generator,a control unit coupled to the comparison unit the control unit having a counter, the control unit being prepared to enable the counter as a function of a comparison of the ramp signal with the first analog signal level and the second analog signal level, andan output for providing an output digital value as a function of a relationship between the first analog signal level and the second analog signal level,wherein the ramp signal has at least one linearly rising and at least one linearly falling portion and an adjustable shift at a reversal point between the rising and falling portion of the ramp signal, the shift depending on the number of rising and falling portions of the ramp signal.2. The analog-to-digital converter circuit according to claim 1 , wherein the shift at the ...

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Номер записи: 85
16-02-2017 дата публикации

Reference Voltage Generator for an Analog-Digital Converter and Method for Analog-Digital Conversion

Номер: US20170047940A1
Автор: Cardoso Paulo António Ribeiro, de Figueiredo Pedro Miguel Ferreira
Принадлежит:

Analog-digital converter configured for conversion of an input voltage, represented by a pair of input potentials, into a binary code using successive approximation. The analog-digital converter comprises a reference voltage generator (RVG) supplying a first pair of reference potentials and a second pair of reference potentials. The analog-digital converter further comprises a switched capacitor array (SCA) configured to receive the first and the second pair of reference potentials as well as a control unit (CTRL) coupled to the switched capacitor array (SCA) and configured to switch capacitors of the switched capacitor array (SCA) either to the first pair of reference potentials or to the second pair of reference potentials depending on a progress of the conversion. 1. Reference voltage generator (RVG) for supplying a first pair of reference potentials at a first terminal pair and a second pair of reference potentials at a second terminal pair to a switched capacitor array (SCA) of an analog-digital converter working with successive approximation , wherein{'b': 1', '2, 'the reference voltage generator (RVG) comprises a first input (I) and a second input (I) to be coupled to an external voltage supply (EVS); and'}{'b': 1', '2, 'a first charge reservoir (RESa) with a first and a second terminal coupled between the first terminal pair, the first terminal coupled to the first input (I) via a first switch and the second terminal coupled to the second input (I) via a second switch; and'}{'b': 1', '2, 'the second terminal pair is coupled to the first input (I) and the second input (I).'}2. Reference voltage generator (RVG) according to claim 1 , further comprising:{'b': 1', '1, 'a first charge pump (CP) coupled to the first terminal of the first charge reservoir (RESa) via a first pump switch (PS); and'}{'b': 2', '2, 'a second charge pump (CP) coupled to the second terminal of the first charge reservoir (RESa) via a second pump switch (PS).'}31212. Reference voltage ...

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Номер записи: 86
15-02-2018 дата публикации

SYSTEMS AND METHODS FOR SIMULTANEOUS SAMPLING OF SERIAL DIGITAL DATA STREAMS FROM MULTIPLE ANALOG-TO-DIGITAL CONVERTERS (ADCS), INCLUDING IN DISTRIBUTED ANTENNA SYSTEMS

Номер: US20180049183A1
Автор: Gutman Amit
Принадлежит:

Systems and methods for simultaneous sampling of serial digital data streams from multiple analog-to-digital converters (ADCs), including in distributed antenna systems, are disclosed. In one embodiment, a controller unit samples a plurality of serial digital data streams simultaneously. To allow the controller unit to sample the multiple serial digital data streams simultaneously from a plurality of ADCs, the controller unit is configured to provide a plurality of data input ports. Each of the ADCs is coupled to a common chip select port and clock signal port on the controller unit. The controller unit communicates a chip select signal on the chip select port to activate all of the ADCs simultaneously to cause each of the ADCs to provide its respective digital data stream to the respective data input port of the controller unit simultaneously for sampling. As a result, fewer or lower-cost components may be used to sample multiple ADCs. 1. An apparatus for simultaneous sampling of digital data streams from multiple analog-to-digital converters (ADCs) , comprising:a chip select output port configured to be coupled to a chip select input port of each of a plurality of ADCs;a clock output port configured to be coupled to a clock input port of each of the plurality of ADCs;a plurality of data input ports, each of the plurality of data input ports configured to be coupled to a corresponding data output port among a plurality of data output ports of the plurality of ADCs; and communicate a chip select signal on the chip select output port to receive a serial digital data stream on each of the plurality of data input ports simultaneously; and', 'communicate a clock signal on the clock output port,, 'a processor configured towherein each of the plurality of data input ports is configured to simultaneously receive a digital data stream from two or more of the plurality of ADCs in response to communicating the clock signal from the clock output port to the clock input port of ...

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Номер записи: 87
03-03-2022 дата публикации

ANALOG-TO-DIGITAL CONVERTING DEVICE AND CONTROL SYSTEM

Номер: US20220069832A1
Автор: ENDO Hiroshi
Принадлежит: DENSO WAVE INCORPORATED

An analog-to-digital converting device includes: a main analog-to-digital converter configured to convert an analog signal output from a sensor to a digital signal; and a monitoring unit configured to monitor the digital signal converted by the main analog-to-digital converter. The main analog-to-digital converter is provided by a special purpose IC arranged separately from a microcomputer for controlling the main analog-to-digital converter. The monitoring unit includes multiple sub analog-to-digital converters each of which having a conversion accuracy lower than that of the main analog-to-digital converter and converting the analog signal output from the sensor to a digital signal. The monitoring unit sets a predetermined threshold based on conversion values of the digital signals converted by the multiple sub analog-to-digital converters, and compares a conversion value of the digital signal converted by the main analog-to-digital converter with the predetermined threshold. 1. An analog-to-digital converting device applied to a control system that controls an industrial equipment as a control target , the analog-to-digital converting device comprising:a main analog-to-digital converter configured to convert an analog signal, which is output from a sensor and input to the analog-to-digital converting device, to a digital signal; anda monitoring unit configured to monitor the digital signal converted by the main analog-to-digital converter,whereinthe main analog-to-digital converter is provided by an analog-to-digital conversion purpose integrated circuit arranged separately from a microcomputer that controls the main analog-to-digital converter, and a plurality of sub analog-to-digital converters each of which having a conversion accuracy lower than a conversion accuracy of the main analog-to-digital converter and converting the analog signal, which is output from the sensor and input to the analog-to-digital converting device, to a digital signal;', 'a setting ...

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Номер записи: 88
03-03-2022 дата публикации

MULTIPATH SAMPLING CIRCUITS

Номер: US20220069833A1
Автор: Lee Hae-Seung
Принадлежит:

A multipath sampling circuit includes an input line electrically having an input voltage, a plurality of voltage amplifiers in parallel electrically with one another, each voltage amplifier having a respective input electrically coupled in series with the input line, each voltage amplifier having a different gain and a different saturation voltage; and a plurality of track-and-hold circuits. The track-and-hold circuits have a first state in which a respective input of each track-and-hold circuit is electrically coupled to an output of a respective amplifier. The track-and-hold circuits have a second state in which the respective input of each track-and-hold circuit is electrically decoupled from the output of the respective amplifier. The track-and-hold circuits can be electrically coupled to a summing circuit, a buffer amplifier, or an operational amplifier. 1. A multipath sampling circuit comprising:an input line electrically having an input voltage;a plurality of voltage amplifiers in parallel electrically with one another, each voltage amplifier having a respective input electrically coupled with the input line, each voltage amplifier having a different gain and a different saturation voltage;a plurality of track-and-hold circuits;a shorting line electrically coupled to a respective output of each sample-and-hold circuit;a shorting switch electrically coupled to the shorting line;a buffer amplifier having an input electrically coupled to the shorting line, the multipath sampling circuit has a tracking phase and a hold phase,', the shorting switch is in an open state, and', 'the track-and-hold circuits are in a first state in which a respective input of each track-and-hold circuit is electrically coupled to an output of a respective amplifier, and, 'when the multipath sampling circuit is in the tracking phase, the shorting switch is in a closed state, and', 'the track-and-hold circuits are in a second state in which the respective input of each track-and-hold ...

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Номер записи: 89
03-03-2022 дата публикации

ANALOG-TO-DIGITAL CONVERSION CIRCUIT WITH IMPROVED LINEARITY

Номер: US20220069836A1
Автор: STEENSGAARD-MADSEN Jesper
Принадлежит: ANALOG DEVICES, INC.

Herein disclosed is an example analog-to-digital converter (ADC) and methods that may be performed by the ADC. The ADC may derive a first code that approximates a combination of an analog input value of the ADC and a dither value for the ADC sampled on a capacitor array. The ADC may further derive a second code to represent a residue of the combination with respect to the first code applied to the capacitor array. The ADC may combine the numerical value of the first code and the numerical value of the second code to produce a combined code applied to the capacitor array for deriving a digital output code. Combining the numerical value of the first code and the numerical value of the second code in the digital domain can provide for greater analog-to-digital (A/D) conversion linearity. 1. A method for providing a digital output code to represent an analog input value , the method comprising:acquiring and sampling, using a first segment of a capacitor array and a second segment of the capacitor array, a combined value having an analog input value and a dither value;deriving, by a first successive-approximation-register analog-to-digital converter, a first code representing the sampled combined value;deriving, by a second successive-approximation-register analog-to-digital converter, a second code representing a first residue of the sampled combined value with respect to the first code;deriving, by the second successive-approximation-register analog-to-digital converter, a third code representing a second residue of the sampled combined value with respect to the first code combined with the second code; andderiving a digital output code representing the analog input value by combining the first code, the second code, the third code, and a dither code representing the dither value.2. The method of claim 1 , further comprising:combining the first code and the second code to derive a combined code;applying a first segment of the combined code to the first segment of the ...

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Номер записи: 90
25-02-2016 дата публикации

Enhanced resolution successive-approximation register analog-to-digital converter and method

Номер: US20160056831A1
Автор: Joonsung Park, Krishnaswamy Nagaraj, Mikel Ash
Принадлежит: Texas Instruments Inc

An enhanced resolution successive-approximation register (SAR) analog-to-digital converter (ADC) is provided that includes a digital-to-analog converter (DAC), a comparator and enhanced resolution SAR control logic. The DAC includes analog circuitry that is configured to convert an M-bit digital input to an analog output. The comparator includes a plurality of coupling capacitors. The enhanced resolution SAR control logic is configured to generate an M-bit approximation of an input voltage and to store a residue voltage in at least one of the coupling capacitors. The residue voltage represents a difference between the input voltage and the M-bit approximation of the input voltage. The enhanced resolution SAR control logic is further configured to generate an N-bit approximation of the input voltage based on the stored residue voltage, where N>M.

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Номер записи: 91
22-02-2018 дата публикации

ADC controller With Temporal Separation

Номер: US20180054209A1
Автор: Kris Bryan
Принадлежит: MICROCHIP TECHNOLOGY INCORPORATED

Embodiments of the present disclosure may include an ADC circuit including channel register sets, a conversion request flip-flop, a priority encoder circuit, and a controller circuit. The controller circuit may be configured to receive a conversion request signal, latch the conversion request signal into the conversion request flip-flop, determine by the priority encoder circuit a highest priority pending conversion request, and output an active channel identifier code. The channel identifier code may be configured to select the data channel register sets that are active by identifying received selection bits. The embodiments may include logic to store a converted value from a selected analog input to a data output register based on the channel identifier code. 1. A microcontroller comprising:an analog-to-digital conversion (ADC) circuit including a plurality of channel register sets;a conversion request flip-flop;a priority encoder circuit; receive a conversion request signal;', 'latch the conversion request signal into the conversion request flip-flop;', 'determine by the priority encoder circuit a highest priority pending conversion request; and', 'output an active channel identifier code, wherein the channel identifier code is configured to select which of the plurality of data channel register sets is active by identifying received analog selection bits; and', 'control logic configured to store a converted value from a selected analog input to a data output register based on the channel identifier code., 'a controller circuit configured to2. The microcontroller according to claim 1 , wherein the controller circuit includes a state machine.3. The microcontroller according to claim 1 , wherein the conversion request flip-flop is configured to be cleared as the conversion process is completed.4. The microcontroller according to claim 1 , further comprising a plurality of connection pins claim 1 , a timer claim 1 , and a pulsed-width-modulation (PWM) module claim 1 ...

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Номер записи: 92
22-02-2018 дата публикации

MULTIPLE SAMPLING STAGE RECEIVER AND RELATED METHODS

Номер: US20180054210A1
Автор: Ali Tamer, Awad Ramy
Принадлежит:

A line receiver including an analog-to-digital converter is described. The line receiver may include an input stage, a first sampling stage, an integration stage, and a second sampling stage. The input stage may be configured to receive an input voltage representative of a signal transmitted by a transmitter, and to convert the input voltage to a current. The input stage may include a trans-conductance stage. The current may be sampled using the first sampling stage. The sampled current may be converted to a voltage using the integration stage. The integration stage may include a trans-impedance stage. The voltage obtained using the integration stage may be sampled using the second sampling stage. 1. A line receiver comprising:an input stage configured to receive an input signal and to generate an intermediate signal;a first sampling stage coupled to the input stage and configured to sample the intermediate signal at a first rate;an integration stage coupled to the first sampling stage and configured to integrate the sampled intermediate signal; anda second sampling stage coupled to the integrator stage and configured to sample the integrated sampled intermediate signal at a second rate,wherein the first sampling stage comprises a plurality of switches configured to sample the intermediate signal at different times and wherein the integration stage comprises a plurality of integrators, each of the plurality of integrators being coupled to a respective switch of the plurality of switches.2. The line receiver of claim 1 , wherein the integration stage comprises an amplifier and a capacitor coupled between an input terminal and an output terminal of the amplifier.3. The line receiver of claim 2 , wherein the input terminal of the amplifier is clamped to a fixed potential.4. The line receiver of claim 2 , wherein the amplifier has a gain that is greater than 1.5. The line receiver of claim 2 , wherein the amplifier has a gain that is greater than or equal to 100.6. The ...

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Номер записи: 93
15-05-2014 дата публикации

Analog-to-digital converter arrangement

Номер: US20140132433A1
Автор: Andreas Wiesbauer, Dietmar Straeussnigg
Принадлежит: INFINEON TECHNOLOGIES AG

An analog-to-digital converter arrangement may include an analog amplifier with variable gain; an analog-to-digital converter; a digital reconstruction element including elements to reduce an influence of transients during a change of the variable gain of the analog amplifier.

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Номер записи: 94
23-02-2017 дата публикации

RADIO FREQUENCY FLASH ADC CIRCUITS

Номер: US20170054448A1
Автор: CHANA Jatinder, LYE William Michael, ZORTEA Anthony Eugene
Принадлежит:

A system and method for sampling an RF signal are described. The system comprises a plurality of capacitors, a plurality of resistors, and a sampling circuit. A first port of each capacitor of the plurality of capacitors is coupled to the RF signal. A first port of each resistor of the plurality of resistors is coupled to one of a plurality of reference levels. A second port of each resistor of the plurality of resistors is coupled to a second port of a corresponding capacitor of the plurality of capacitors. The sampling circuit produces a plurality of digital outputs by sampling the second port of each resistor of the plurality of resistors. 1. A system for sampling an RF signal , the system comprising:a plurality of capacitors, a first port of each of the plurality of capacitors being operably coupled to the RF signal;a plurality of resistors, a first port of each of the plurality of resistors being operably coupled to a reference level of a plurality of reference levels, a second port of each of the plurality of resistors being operably coupled to a second port of each of the plurality of capacitors; anda sampling circuit operably coupled to the second port of each of the plurality of resistors, the sampling circuit producing a plurality of digital outputs.2. The system of claim 1 , wherein the system comprises a converter operable to convert the plurality of digital outputs to a binary output.3. The system of claim 1 , wherein the system comprises a series of resistors between a first reference input and a second reference input claim 1 , each reference level of the plurality of reference levels being produced along the series of resistors.4. The system of claim 3 , wherein the system comprises a first switch for selecting the first reference input and a second switch for selecting the second reference input.5. The system of claim 1 , wherein the sampling circuit comprises a plurality of comparators claim 1 , the second port of each of the plurality of resistors ...

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Номер записи: 95
05-03-2015 дата публикации

SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER AND METHOD OF ANALOG-TO-DIGITAL CONVERSION

Номер: US20150061904A1
Автор: Choi Michael, Lee Choong-Hoon
Принадлежит:

An analog-to-digital converter includes a digital-to-analog converting circuit, a comparator, a comparator offset detector, and a signal processing circuit. The digital-to-analog converting circuit generates a reference voltage signal that changes in response to a comparator offset compensation signal, samples and holds an analog input signal, and performs a digital-to-analog conversion on digital output data to generate a hold voltage signal. The comparator compares the hold voltage signal with the reference voltage signal in response to a clock signal to generate a comparison output voltage signal. The comparator offset detector generates the comparator offset compensation signal based on the comparison output voltage signal. The signal processing circuit performs successive approximation based on the comparison output voltage signal to generate the digital output data. 1. An analog-to-digital converter , comprising: generate a reference voltage signal, the reference voltage signal changing in response to a comparator offset compensation signal,', 'sample and hold an analog input signal, and', 'perform a digital-to-analog conversion on digital output data to generate a hold voltage signal;, 'a digital-to-analog converting circuit configured to,'}a comparator configured to compare the hold voltage signal with the reference voltage signal in response to a clock signal to generate a comparison output voltage signal;a comparator offset detector configured to generate the comparator offset compensation signal based on the comparison output voltage signal; anda signal processing circuit configured to perform analog-to-digital conversion using a successive approximation based on the comparison output voltage signal to generate the digital output data.2. The analog-to-digital converter of claim 1 , wherein the analog-to-digital converter is configured to claim 1 ,perform an analog-to-digital conversion on a comparator offset to generate the comparator offset compensation ...

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Номер записи: 96
10-03-2022 дата публикации

ANALOG-TO-DIGITAL CONVERTER, ELECTRONIC DEVICE INCLUDING THE SAME, AND OPERATING METHOD OF ANALOG-TO-DIGITAL CONVERTER

Номер: US20220077869A1
Автор: CHAE Hyungil, OH Younggyun
Принадлежит: KONKUK UNIVERSITY INDUSTRIAL COOPERATION CORP.

Disclosed are an analog-to-digital converter (ADC), an electronic device including the ADC, and an operating method of the ADC. The ADC includes a first stage that includes a plurality of channels, generates a first sampling signal by sequentially sampling a first analog signal based on time interleaving, and generates a first digital signal and a first residual signal corresponding to the first analog signal by performing analog-to-digital conversion based on the first sampling signal, an amplifier that amplifies the first residual signal, and a second stage that includes a plurality of channels, generates a second sampling signal by sequentially sampling the amplified first residual signal based on time interleaving, and generates a second digital signal and a second residual signal corresponding to the first analog signal by performing analog-to-digital conversion based on the second sampling signal. The number of the plurality of channels included in the first stage is odd-numbered. 1. An analog-to-digital converter comprising:a first stage including a plurality of channels, and the first stage which generates a first sampling signal by sequentially sampling a first analog signal based on time interleaving and generates a first digital signal and a first residual signal corresponding to the first analog signal by performing analog-to-digital conversion based on the first sampling signal;an amplifier which amplifies the first residual signal; anda second stage including a plurality of channels, to the second stage which generates a second sampling signal by sequentially sampling the amplified first residual signal based on time interleaving and generates a second digital signal and a second residual signal corresponding to the first analog signal by performing analog-to-digital conversion based on the second sampling signal,wherein the number of the plurality of channels included in the first stage is odd-numbered.2. The analog-to-digital converter of claim 1 , ...

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Номер записи: 97
02-03-2017 дата публикации

FINITE STATE MACHINE-BASED TRIGGER EVENT DETECTION EMPLOYING INTERPOLATION

Номер: US20170060114A1
Автор: Barford Lee A., Lehane Andrew R.
Принадлежит:

Trigger event detection employs a finite state machine (FSM) and interpolation of time-sampled data. A trigger event detector includes an interpolator configured to interpolate time-sampled data and to provide an interpolated sequence of data. The trigger event detector further includes an FSM that has a plurality of predefined states including a trigger event state. The FSM is configured to transition among the predefined states according to an ordered sequence of symbols corresponding to the interpolated sequence of data. A transition of the FSM into the trigger event state represents detection of a trigger event. The trigger event detection provides one or both of a real-time trigger and a post-acquisition trigger. 1. A trigger event detector comprising:an interpolator configured to interpolate time-sampled data and to provide an interpolated sequence of data; anda finite state machine (FSM) having a plurality of predefined states including a trigger event state, the FSM being configured to transition among the predefined states according to an ordered sequence of symbols corresponding to the interpolated sequence of data,wherein a transition of the FSM into the trigger event state represents detection of a trigger event, the trigger event detection providing one or both of a real-time trigger (RTT) and a post-acquisition trigger (PAT).2. The trigger event detector of claim 1 , wherein the interpolator is further configured to receive the time-sampled data from an analog-to-digital converter (ADC) claim 1 , the time-sampled data sequence representing time samples of an analog signal.3. The trigger event detector of claim 1 , wherein the interpolator is further configured to receive the time-sampled data from a memory claim 1 , the memory being configured to store the time-sampled data sequence prior to interpolation by the interpolator.4. The trigger event detector of claim 1 , wherein the interpolator is configured to interpolate the time-sampled data sequence ...

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Номер записи: 98
21-02-2019 дата публикации

ANALOG-TO-DIGITAL CONVERSION CIRCUIT AND METHOD

Номер: US20190058486A1
Автор: FAN Shuo
Принадлежит:

An analog-to-digital conversion circuit and method are provided. At a sampling stage, the first capacitor array connects lower electrode plates of N capacitors to a first input voltage, connect lower electrode plates of the other capacitors to a common-mode voltage, and connect upper electrode plates of all the capacitors to the common-mode voltage to sample the first input voltage; in an iconversion at a conversion stage, the logic circuit controls, the lower electrode plate of an icapacitor to connect to a reference voltage or a ground voltage, a first comparison voltage output by the first capacitor array approximates a second comparison voltage; and the comparator stores a comparison result between the first and the second comparison voltage to an i+1flag bit in the logic circuit, and analog-to-digital conversion is completed when i+1 is equal to the total number of capacitors in the first capacitor array. 1. An analog-to-digital conversion circuit , comprising a first capacitor array , a logic circuit and a comparator; wherein:at a sampling stage, the first capacitor array is configured to connect lower electrode plates of N capacitors in the first capacitor array to a first input voltage, connect lower electrode plates of the other capacitors in the first capacitor array to a common-mode voltage, and connect upper electrode plates of all capacitors in the first capacitor array to the common-mode voltage to sample the first input voltage, wherein N is a positive integer less than a total number of the capacitors in the first capacitor array;{'sup': th', 'th', 'th, 'in an iconversion at a conversion stage, the logic circuit is configured to control, according to an istored flag bit, the lower electrode plate of an icapacitor in the first capacitor array to connect to a reference voltage or a ground voltage, such that a first comparison voltage output by the first capacitor array approximates a second comparison voltage, wherein i is a positive integer less than ...

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Номер записи: 99
03-03-2016 дата публикации

HIGH-SPEED COMPARATOR FOR ANALOG-TO-DIGITAL CONVERTER

Номер: US20160065229A1
Автор: Kull Lukas, Toifl Thomas H.
Принадлежит:

A comparator for an analog-to-digital converter is provided. The comparator includes a differential amplifier unit that receives a sampling signal and provides an output signal, based on a voltage provided by the sampling signal. The differential amplifier unit includes an input stage that receives the sampling signal and integrates a current on the integration nodes based on potentials of the sampling signal. The comparator includes a sense amplifier coupled with the integration nodes that detects a potential difference and amplifies the potential difference to generate the output signal. The comparator includes a charge injection circuit () to inject equal charges into the integration nodes. 1. An analog-to-digital comparator , comprising:a differential amplifier unit wherein the differential amplifier unit receives a sampling signal and provides an output signal based on a voltage provided by the sampling signal, wherein the differential amplifier unit includes:an input stage wherein the input stage receives the sampling signal and integrates a current on integration nodes based on potentials of the sampling signal;a sense amplifier coupled with the integration nodes wherein the sense amplifier detects a potential difference and amplifies the potential difference to generate the output signal; anda charge injection circuit wherein the charge injection circuit injects equal charges into the integration nodes.2. The comparator according to claim 1 , wherein the sense amplifier includes cross-coupled inverters.3. The comparator according to claim 2 , wherein one terminal of each of the cross-coupled inverters is coupled with a respective one of the integration nodes claim 2 , so that the voltage over the cross-coupled inverters depends on the potential on the respective integration node.4. The comparator according to claim 3 , wherein charges are selectively injected into the integration nodes before the voltage over the cross-coupled inverters reaches a value at ...

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Номер записи: 100