СПОСОБ ИЗГОТОВЛЕНИЯ ПЛАТ ГИБРИДНЫХ ИНТЕГРАЛЬНЫХ СХЕМ КРЮЧАТОВА В.И.

Изобретение относится к электротехнике, в частности к технологии изготовления плат гибридных интегральных схем, и может быть использовано в радиоэлектронной промышленности, приборостроении и вычислительной технике. Технический результат - повышение качества и снижение трудоемкости изготовления плат гибридных интегральных схем. Достигается тем, что технологические перемычки образуют из проводящего слоя многослойной структуры с получением на заготовке рисунка проводников, полученного фотолитографической обработкой, и последующим селективным травлением проводящего и резистивного слоев между проводниками и пленочными технологическими перемычками, а после электролитического осаждения дополнительного проводящего и защитного слоя проводника выполняют селективное химическое стравливание пленочных технологических перемычек. На подложку наносят трехслойное покрытие, состоящее из слоя адгезива, на который осаждают проводящий и защитный слой, на последний наносят фоторезист, соответствующий рисунку ...

СПОСОБ ИЗГОТОВЛЕНИЯ МНОГОСЛОЙНОЙ ПЕЧАТНОЙ ПЛАТЫ

Изобретение относится к способу изготовления многослойной печатной платы. Способ, в частности, подходит для изготовления гибких многослойных элементов, содержащих, например, антенны радиочастотной идентификации РЧИ (RFID). Технический результат - предложение более управляемого и эффективного способа изготовления многослойных печатных плат, посредством которого можно получить рисунок, имеющий межлинейные промежутки точно заданных размеров, включая очень тонкие промежутки, даже в тех случаях, когда рисунок предусматривает наличие больших участков, не содержащих проводника, а также избежать проблем, возникающих в процессе изготовления многослойных элементов защищенных изделий из-за остатков клеевого покрытия на непроводящих участках, предложение экономически рентабельного и надежного способа изготовления электрических контуров, размещаемых по обе стороны подложки, допускающего применение лазера при производстве печатных плат, в том числе и плат, содержащих термобумагу, со спиральной антенной ...

ЛИНИЯ ДЛЯ ЖИДКОСТНОЙ ХИМИЧЕСКОЙ ОБРАБОТКИ ПЛОСКИХ ИЗДЕЛИЙ, ПРЕИМУЩЕСТВЕННО ПОЛУПРОВОДНИКОВЫХ ПЛАСТИН

Изобретение может быть использовано, в частности, в электронике для жидкостной химической обработки полупроводниковых пластин (ППП). Цель - повышение качества обработки ППП достигается тем, что в линии поворотные носители выполнены в виде ротора с горизонтально расположенным центральным валом 9 с цапфами 10, лысками для фиксации от поворота и парой торцовых зубчатых дисков (ТЗД) с венцом 12. По периферии ТЗД равномерно по окружности имеются отверстия, в которых установлены обоймы 16. Каждая обойма выполнена с окнами 17 на боковой поверхности для прохода травителя и воды и внутренней продольной полостью со средствами установки и фиксации в ней ППП в виде круглой пластины 18 с вырезами по периферийной части. В описании изобретения даны варианты конструктивного выполнения средств установки ППП в полости обойм 16, а также конструкция выполнения привода обойм 16. Линия высокопроизводительна. 3 з.п.ф-лы, 12 ил.

СПОСОБ ИЗГОТОВЛЕНИЯ ПЕЧАТНОЙ ПЛАТЫ

Изобретение относится к различным областям микроэлектроники и изготовлению печатных плат, в частности к изготовлению многослойных печатных плат. Технический результат - разработка способа изготовления печатной платы, характеризующегося высокой точностью воспроизведения рисунка электрической схемы, обеспечивающего высокую адгезию слоя металлорезиста к подложке, контактным площадкам и к стенкам отверстий перфорации ПП, сохраняющего способность к пайке оловосодержащим сплавом в течение продолжительного времени (порядка 6 месяцев). Достигается тем, что в способе изготовления печатной платы формируют на диэлектрическом основании токопроводящий рисунок электрической схемы последовательно методом фотолитографии с получением слоя металлорезиста, перфорируют диэлектрическое основание с получением сквозных отверстий на заданных участках и наносят металлосодержащее покрытие гальваническим методом. После чего проводят защиту слоя токопроводящего покрытия и удаление покрытия с несанкционированных участков ...

СПОСОБ ИЗГОТОВЛЕНИЯ ГИБКИХ ПЕЧАТНЫХ ПЛАТ

Изобретение относится к радиоэлектронике и может быть использовано при изготовлении гибких печатных плат, применяемых при изготовлении радиоэлектронной техники. Технический результат - получение электропроводящих печатных плат на полимерной основе с хорошо паяющейся электросхемой, устойчивой к окислению при ширине электропроводящих дорожек менее 100 мкм. Достигается тем, что в способе изготовления печатных плат, состоящем из последовательного нанесения на металлическую пластину алюминиевого покрытия, металлорезистивного никелевого (кобальтового) покрытия и получения электропроводящей медной схемы путем формирования защитного рельефа пленочным фоторезистом на никелевом или кобальтовом резистивном покрытии и нанесением меди на незащищенные фоторезистом участки, полученную электропроводящую медную схему покрывают тонким слоем полимера. Затем отделяют полимерную пленку с электропроводящей схемой и металлорезестивным покрытием путем растворения алюминиевого слоя и формируют из защитного никелевого ...

СПОСОБ ИЗГОТОВЛЕНИЯ ГИБРИДНЫХ ИНТЕГРАЛЬНЫХ СХЕМ

Изобретение относится к радиотехнике, в частности к изготовлению гибридных интегральных схем. Сущность изобретения: на поверхности фольгированного алюминием полиимида формируют рисунок контактных площадок, зеркально отражающий рисунок контактных площадок на подложке платы. На контактные площадки наносят припой и соединяют их пайкой. Затем полиимид удаляют. На поверхности подложки образуются монтажные столбики, которые позволяют проводить монтаж навесных элементов сваркой. 7 ил.

СПОСОБ ФОРМИРОВАНИЯ СТРУКТУР В МИКРОЛИТОГРАФИИ

Изобретение относится к области микроэлектроники и может использован при формировании структур методом обратной литографии. Сущность изобретения: на подложку наносят позитивный электронорезист проводят экспонирование рисунка, проявление, наносят дополнительный слой материала и удаляют резист, а после проявления облучают сформированные в резисте элементы пучком электронов с энергией 1-5 КэВ дозой, равной 2-10 чувствительностям резиста, после чего удаление резиста проводят на глубину облученного слоя проявлением.

КАССЕТА ПРЕИМУЩЕСТВЕННО ДЛЯ ЖИДКОСТНОЙ ОБРАБОТКИ ПЕЧАТНЫХ ПЛАТ

Изобретение относится к технологическому оборудованию для обработки узлов на печатных платах в ваннах. Сущность изобретения: изобретение позволяет повысить производительность путем присоединения верхней плиты 1 к центральной стойке (С) 6 и нижней плиты 2 к внутренней втулке (ВВ) 8, которая размещена на С 6 и зафиксирована на ней при помощи шариков 9, утопленных в углублениях 10, и наружной втулки (НВ) 12 с внутренним кольцевым пазом 13. НВ 12 взаимодействует с опорным кольцом 11 и цилиндрической пружиной 16, размещенными на ВВ 8. 2 з. п. ф-лы, 2 ил.

СПОСОБ ИЗГОТОВЛЕНИЯ ПЕЧАТНЫХ ПЛАТ ДЛЯ СВЕТОДИОДОВ

... 1. Способ изготовления печатных плат, основанный на фотохимическом методе, отличающийся тем, что проводят первое сверление технологических базовых отверстий, затем на базовой заготовке формируют токопроводящий рисунок электрической схемы последовательно методом фотолитографии с использованием слоя фоторезиста, затем проявляют рисунок печатной платы, защищают торцы и открытые места алюминий жидким фоторезистом и проводят травление, после чего удаляют щелочно-проявляемый фоторезист и наносят жидкую паяльную маску, затем наносят припой, например, ПОС-63, проводят второе сверление конструктивных отверстий. ! 2. Способ по п.1, отличающийся тем, что в качестве заготовок - базового материала - печатных плат применяют структуру медь-диэлектрик-алюминий, причем медное покрытие предназначено для размещения силовых элементов, например, светодиодов. ! 3. Способ по п.1, отличающийся тем, что травление проводят в составе: медь хлористая двухводная, амлоний хлористый, кислота соляная в количестве 50-135 ...

СПОСОБ ИЗГОТОВЛЕНИЯ ПРОВОДЯЩЕЙ СХЕМЫ НА ПОДЛОЖКЕ, ПРОВОДЯЩАЯ СХЕМА НА ПОДЛОЖКЕ И УСТРОЙСТВО ДЛЯ ИЗГОТОВЛЕНИЯ ГИБКОЙ ПРОВОДЯЩЕЙ СХЕМЫ

Из проводящей схемы можно изготовить плотно упакованные блоки контактов для использования в качестве электрических соединителей или схем. Способ и устройство для изготовления проводящей схемы включает в себя формование листа проводящего материала 22 для образования выступов 24 и желобков 26, из которых один образует проводящую схему, а другой - отходы материала, которые затем механически удаляются. Таким образом проводящая схема поддерживается слоем 12 диэлектрика.

СПОСОБ ТРАВЛЕНИЯ МЕДНОЙ ЗАГОТОВКИ ПЕЧАТНОЙ ПЛАТЫ И УСТРОЙСТВО ДЛЯ ЕГО ОСУЩЕСТВЛЕНИЯ

Изобретение относится к электронике и может быть использовано при изготовлении печатных плат. Целью изобретения является повышение производится травления меди. На заготовку печатной платы из фольгированного медью стеклотекстолита наносят защитное покрытие по рисунку схемы. Затем заготовку помещают в рабочую камеру, где ее перемещают со скоростью, необходимой для полного удаления меди с незащищенных участков заготовки. Удаление меди проводят путем травления. Для этого травильный раствор на основе хлорной меди разбрызгивают на поверхность заготовки во время ее перемещения в рабочей камере. Во время травления в травильный раствор вводят под давлением воздух. Его количество определяется из соотношения 0,01Vтр≅Vвозд≅0,1Vтр, где Vвозд - скорость подачи воздуха в травильной раствор, л/мин, Vтр - скорость подачи травильного раствора на поверхность заготовки, л/мин. Введение в распыляемый травильный раствор определенного количества воздуха увеличивает количество кислорода в слое травильного раствора ...

СПОСОБ ИЗГОТОВЛЕНИЯ ПОЛОСКОВОЙ ПЛАТЫ НА ДИЭЛЕКТРИЧЕСКОЙ ПОДЛОЖКЕ

... 1. Способ изготовления полосковой платы на диэлектрической подложке, включающий нанесение адгезивного подслоя и осаждение слоя меди на поверхность диэлектрической подложки, выполнение на поверхности заготовки фотолитографии рисунка полосковой платы, электролитическое наращивание полосок электропроводников до номинальной толщины, удаление резиста и стравливание слоя металла с пробельных мест, отличающийся тем, что полоски электропроводников в заготовке отделяют от пробельных мест технологическими канавками, рисунок которых дополнительно наносят фотолитографией на поверхность заготовки вдоль периметра полосок, и по рисунку канавок последние образуют селективным химическим стравливанием металла до адгезивного подслоя шириной, достаточной для нанесения на боковые стороны канавки защитного слоя, предохраняющего полоску электропроводника от разрушения при химическом стравливании слоев металла и адгезива с пробельных мест.2. Способ по п.1, отличающийся тем, что на поверхность диэлектрической подложки ...

Устройство для двустороннего травления плоских заготовок

Линия для химической обработки печатных плат

Фотошаблон

Устройство для изготовления печатных схем из фольгированного диэлектрика

Способ изготовления микросхем

Способ изготовления печатных плат

СПОСОБ ИЗГОТОВЛЕНИЯ ПЛЕНОЧНЫХ МИКРОСХЕМ

Способ термического дубления светочувствительного слоя

Способ изготовления трафаретов

Способ изготовления гибких печатных плат и кабелей

Использование: изобретение относится к технике создания электронной аппаратуры , в частности ее коммутирующих элементов . Сущность изобретения: способ изготовления ГПП и ГПК включает нанесение фоторезиста на фольгированный диэлектрик , экспонирование и проявление фоторезиста , травление металла через фоторезистивную маску, приклейку защитной пленки с адгезивом к поверхности со стороны металла, повторное нанесение слоя фоторезиста на поверхность, его экспонирование и травление полиимида. При этом нанесение фоторезиста выполняют после травления металла, затем осуществляют экспонирование повторно нанесенного фоторезиста , травление полиимида, после чего выполняют приклейку защитной пленки с адгезивом. 7 ил.

Способ изготовления фотошаблонов

Раствор для травления печатных плат

Устройство для травления плоскихиздЕлий

Травильный раствор для печатных плат

Способ изготовления трафарета

Умножитель частоты следования импульсов

УМНОЖИТЕЛЬ ЧАСТОТЫ СЛЕДОВАНИЯ ИМПУЛЬСОВ, содержащий последовательно соединенные фильтр, делитель напряжения, компараторы и сумматор , отличающийся тем, что, с целью расширения функциональных возможностей путем получения коэффициента умножения равного N, в него введены последовательно соединенные формирователь импульсов, формирователь пилообразного напряжения : и амплитудный детектор, а делитель напряжения выполнен с (Н-1)-м выходами , каждый из которых соединен с первьш входом соответствующего компаратора , второй вход которого соединен с выходом формирователя пилообразного напряжения, а выход - с соответствующими входами сумматора, дополнительный , вход которого подключён к выходу формирователя импульсов .

Способ изготовления печатных схем

Способ травления хрома

Способ изготовления печатной платы

Устройство для травления плат печатных схем на фольгированном диэлектрике

Фотополимеризующаяся композиция

KLEBEVORRICHTUNG

Verfahren und Vorrichtung zum kontinuierlichen Zuführen von Filmmaterial in eine Vorrichtung zum Aufbringen eines Filmes

Elektrobeschichtungsverfahren

VERFAHREN ZUM PHOTOLITHOGRAPHISCHEN METALLISIEREN ZUMINDEST DER INNENSEITEN VON LÖCHERN DIE IN ZUSAMMENHANG MIT EINEM AUF EINER AUS ELEKTRISCH ISOLIERENDEM MATERIAL BESTEHENDE PLATTE BEFINDLICHEN MUSTER AUFGEBRACHT SIND

Ein Tetrazol enthaltender Verfärbungsinhibitor für photopolymerisierbare Zusammensetzungen

BILDERZEUGUNGSVERFAHREN

Verfahren zur Herstellung einer Halbleitervorrichtung mit einem keramischen Substrat und einem integrierten Schaltungskreis

VERFAHREN UND ANORDNUNG ZUR KONTROLLIERTEN SPRÜHÄTZUNG

VERFAHREN ZUM BESCHICHTEN MIT EINER DUENNEN FOLIE.

METHOD OF MAKING PRINTED CIRCUITS

Rotatable manual device for the engraving and machining of printed electronic circuits

A device for the engraving of one or more printed circuits in a single operation, characterised in that this device has a column (1) which is set up at the ends for the respective accommodation of a crank-like gripping means (10) and an attachment piece (8) which forms a pin which is fitted on a bearing (9) and is centred, two plates (2-6) being provided between the said ends, which plates (2-6) are set up such that they fix between them one or more boards of printed circuits by connecting means and adjusting means. ...

Zweiseitige Siebdruckvorrichtung mit einem Mechanismus zur Hin- und Herbewegung und einer neigbaren Rakel

Leitfähige Muster-Schichtstruktur und Verfahren zur Herstellung der leitfähigen Muster-Schichtstruktur

AUFZEICHNUNGSKOPF FUER ELEKTROSTATISCHE AUFZEICHNUNGSGERAETE UND VERFAHREN ZU SEINER HERSTELLUNG

PHOTOPOLYMERISIERBARE ZUSAMMENSETZUNG

Durch Strahlung polymerisierbares Aufzeichnungsmaterial und Verfahren zur Herstellung von Reliefaufzeichnungen.

Urethanpolymeres, Verfahren zu seiner Herstellung und seine Verwendung

VERFAHREN ZUR HERSTELLUNG EINER LEITERPLATTE MIT KONTAKTKAMM

VERFAHREN UND EINRICHTUNG ZUR HERSTELLUNG VON LEITENDEN MUSTERN AUF EINEM SUBSTRAT.

Verfahren zur Herstellung gedruckter Schaltungen und/oder gedruckter Schaltungselemente

Kupfer-Aetzverfahren mit Hilfe von Haliden

LEITERPLATTENMERKMALE MIT REDUZIERTER PARASITÄRER KAPAZITÄT UND DEREN HERSTELLUNGSVERFAHREN

Verfahren zur Herstellung einer Schaltung unter Verwendung von Prägeverfahren

Process for applying a solderable conductor pattern

A process for applying a conductor pattern to glass is described, in which a heavy metal film is first applied, a copper layer is then applied, a structured photoresist layer is then applied, a further copper layer and, on this layer, a tin layer are then applied by electroplating, the photoresist layer is then removed and the Cu layer not covered with tin and the heavy metal film are removed.

Verfahren zur Herstellung einer gedruckten Schaltung mit Loch

Lichthärtendes elektrostatisches Element mit verbesserten ökologischen Eigenschaften.

Verfahren zum Abtrennen eines durch Bonden angehefteten Films von einer Leiterplatte.

Herstellen von Metallmustern auf einem Substrat

Verfahren zur Herstellung gedruckter Schaltungen

PROCESS FOR INCREASING THE SOLUBILITY RATE RATIO OF A POSITIVE-WORKING RESIST

INDIVIDUALISIERTES MARKIERUNGSVERFAHREN FÜR LEITERPLATTEN

SUBSTRAT FUER EINE GEDRUCKTE SCHALTUNG MIT WIDERSTANDSELEMENTEN

ELEKTRISCHES NETZWERK

VERFAHREN UND SCHICHTMATERIAL ZUR HERSTELLUNG DURCHKONTAKTIERTER ELEKTRISCHER LEITERPLATTEN

Wasch-, Bleich- und Desinfektionsmittel

Verfahren und Vorrichtung zur Herstellung einer Rolle von Antennenelementen und zur Ausgabe derartiger Antennenelemente

VERFAHREN UND EINRICHTUNG ZUM BEHANDELN VON LEITERPLATTEN

Vorrichtung zur Ätzbehandlung von Leiterplatten

Thin film printed circuits

... 1,077,686. Printed circuits. XEROX CORPORATION. No. 17, 1964 [Nov. 20, 1968], No. 46845/64. Heading H1R. In a method of making a thin film circuit component, e.g. a conductor, resistor, dielectric layer, an image of the component is formed, as by xerography; this image (27, Fig. 2, not shown), is located on the adhesive surface of an adhesive tape (30) which is applied to a strippable film (174) of etchant-resist material, formed on a layer (173) of component-forming material on an insulating base (168), e.g. of ceramic or plastics. The tape (30) is then stripped off, taking with it the resist (174) except where the latter is protected from the adhesive by the image (27). The component is then formed by etching, after which the remaining resist is removed. The component material (173) may be an evaporated film of e.g. Al, Ag, Cu, or may be a chemically deposited layer, of which examples are given in the Specification involving the deposition of conductive layers of Cu and Ni, resistive ...

RESIST INK COMPOSITION

AQUEOUS SOLUTION

Staining inhibitor for photopolymerizable compositions

Copper etching

Copper etching process and product particularly suitable for use in the manufacture of printed circuit boards. The copper is etched in a liquid etchant, and the crystal structure of the copper is selected and carefully controlled to provide an anisotropic etch and a relatively high vertical-to-lateral etching ratio. In one disclosed embodiment, the etching solution contains nitric acid, copper nitrate or sulfuric acid, a polymer and a surfactant, and the copper has a top surface crystal structure with predominantly (111) and (200) orientations and relatively little (220) orientation. In another disclosed embodiment, the etching solution contains hydrogen peroxide and sulfuric acid, and the copper foil has a top surface crystal structure with predominantly (311) and (511) orientations. A printed circuit board manufactured in accordance with the invention has a copper foil with a crystal structure selected to provide anisotropic etching and a relatively high vertical-to-lateral etching ratio ...

Method for examining surface of copper layer in circuit board and process for producing circuit board

The surface (3) of a copper layer (2) on a circuit board (4) is irradiated with a light beam, and the degree of progress of oxidation of the surface of the copper layer is determined by taking advantage of the resultant reflected light beam (for example, an intensity or a hue of a reflected beam). Then, the step of coating a resist (4) is carried out only when the thickness of the copper oxide film is not more than about 10 nm. Alternatively, the step of coating a resist may be carried out after removal or reduction of the oxide film or cladding of the oxide film with copper. The present invention enables occurrence of peeling of the resist (4) or dive of plating (5, Fig 1b) to be prevented in the step of effecting selective etching or plating of a copper layer in a circuit board using a resist pattern as a mask. ...

Improvements in the manufacture of printed wiring boards

Method for manufacturing fine pattern and color filter,shading pattern filter and color lcd element formed by using the same

Gating grid and method of making same

A gating grid for deflecting ions includes an insulating substrate (16) a conducting layer (28) adhered to the insulating substrate (16), and interdigitated electrodes (14) patterned in the conducting layer by a photolithographic process. A hole (18) in the insulating substrate beneath the interdigitated electrodes allows ions to pass through the hole in the substrate. A process for making a gating grid for deflecting ions includes adhering a conducting layer (28) to an insulating substrate (16), forming interdigitated electrodes (14) on the conducting layer (28), and then forming a hole (18) in the insulating substrate beneath the interdigitated electrodes.

DISSOLUTION OF METALS UTILIZING A FURAN DERIVATIVE

Process for making a printed circuit board partially coated with solder

A process for making a printed circuit board with partial land areas coated with solder has the steps of coating the printed circuit board with solder, applying print ink or dry film resist onto the land areas 30 for a tape carrier package (TCP), removing solder outside the land areas 30, applying a layer of immersion nickel/gold or anti-oxidant agent on the land areas outside the land areas 30, thus forming a printed circuit board having partial land areas coated with solder. The process overcomes the conventional drawbacks that neither the print ink nor dry film resist effectively covers circuitry and areas defining through-holes.

Manufacture of multi-layer printed circuit boards

A multi-layer printed circuit board is manufactured by forming an alignment target (61) and a first printed circuit on a first dielectric substrate (31), laminating a second dielectric substrate (32) and a conductive layer (33) to the first dielectric substrate (31), covering the conductive layer (33) with a layer of photoresist, providing a first phototool (35) defining an alignment sight (62) and the profiles of via holes to be formed through the conductive layer (33) and the second dielectric substrate (32), exposing the photoresist through the first phototool (35) whilst the alignment sight (62) is accurately aligned with the alignment target (61), processing the exposed photoresist to uncover those portions of the conductive layer (33) which need to be removed to define the via holes, etching the uncovered portions to form via holes, removing the remainder of the exposed photoresist layer, extending the via holes through the second dielectric substrate (32) by ablating those portions ...

Multilayer PCB manufacture with dielectric material matched to photo-resist material

A method for manufacture of multilayer printed circuit boards comprises the steps of: (a) applying a layer of a photoimageable composition onto a copper layer; (b) exposing and developing the photoimageable composition layer to provide a relief image (20) of the composition layer and bared areas of the copper layer; (c) removing bared copper layer areas produced in step (b) to define a copper circuit pattern (26) that is coated with the photoimageable composition relief image (20); and (d) laminating the circuit pattern with coated photoimageable composition with a prepreg dielectric layer (28) to produce a multilayer board. Enhanced adhesion is found between the bonded layers where components of the photoimageable composition are matched to the prepreg material. Thus, for example, enhanced bond strengths are achieved where a photoimageable composition that contains an epoxy resin is bonded to an epoxy based-prepreg material.

DISSOLUTION OF METALS UTILIZING -CAPROLACTAM

Methods and Apparatuses for Detecting Registration Offsets

A method for detecting a registration offset is disclosed. The method includes transferring a first pattern to a metal layer on a first side of a printed circuit board (PCB) substrate. The first pattern has a reference scale. The method further includes transferring a second pattern to a metal layer on a second side opposite to the first side of the PCB substrate. The second pattern has a measurement scale. The second pattern is transferred by aligning an origin of the measurement scale with an origin of the reference scale in an apparatus such that at least a portion of the reference scale is overlapped with the measurement scale. The method includes etching the metal layers of the PCB substrate and measuring an offset in the patterns on the PCB substrate by using the reference scale and the measurement scale. 1. A method for detecting a registration offset , comprising:transferring a first pattern to a metal layer on a first side of a printed circuit board (PCB) substrate, the first pattern having a reference scale;transferring a second pattern to a metal layer on a second side opposite to the first side of the PCB substrate, the second pattern having a measurement scale, wherein the second pattern is transferred by aligning an origin of the measurement scale with an origin of the reference scale in an apparatus such that at least a portion of the reference scale is overlapped with the measurement scale;etching the metal layers of the PCB substrate; andmeasuring an offset in the patterns on the PCB substrate by using the reference scale and the measurement scale.2. The method according to claim 1 , wherein the reference scale and the measurement scale are formed on a corner region of the PCB substrate.3. The method according to claim 2 , wherein the reference scale and the measurement scale are a pair of scales claim 2 , andthe method further comprises forming one or more pairs of scales on one or more corner regions of the PCB substrate.4. The method according to ...

Printed circuit board and the method for manufacturing the same

Provided is a method for manufacturing a printed circuit board. The method for manufacturing a printed circuit board includes preparing an insulation board, irradiating a laser onto a graytone mask to each a surface of the insulation board, thereby forming a circuit pattern groove and a via hole at the same time, and filling the circuit pattern groove and the via hole to form a buried circuit pattern and the via. Thus, the circuit pattern groove and the via hole may be formed using the graytone mask at the same time without performing a separate process for forming the via hole. Therefore, the manufacturing process may be simplified to reduce the manufacturing costs.

PRINTED CIRCUIT BOARD, METHOD OF MANUFACTURING THE SAME AND CONNECTION TERMINAL

A read wiring trace and a write wiring trace are formed on an insulating layer. Connection terminals made of conductor are connected to the read wiring trace and the write wiring trace, respectively. Each connection terminal has at least one corner with a radius of curvature of not larger than 35 μm. 1. A printed circuit board comprising:an insulating layer;a wiring trace formed on said insulating layer; anda connection terminal made of conductor that is electrically connected to said wiring trace, whereinsaid connection terminal has at least one corner with a radius of curvature of not larger than 35 μm.2. The printed circuit board according to claim 1 , whereinsaid conductor includes stainless steel, andthe radius of curvature of said at least one corner of said connection terminal is not larger than 30 μm.3. The printed circuit board according to claim 1 , whereinsaid conductor includes copper, andthe radius of curvature of said at least one corner of said connection terminal is not larger than 10 μm.4. The printed circuit board according to claim 1 , whereinsaid connection terminal has first and second sides parallel to each other, and a third side orthogonal to said first and second sides, andsaid at least one corner includes a first corner that is formed by said first and third sides, and a second corner that is formed by said second and third sides.5. The printed circuit board according to claim 4 , whereinthe width between said first and second sides is not larger than 70 μm.6. The printed circuit board according to claim 1 , whereinsaid connection terminal is configured to be electrically connectable to a magnetic head, and transmittable of an electrical signal between said magnetic head and an electronic circuit through said wiring trace and said connection terminal.7. A method of manufacturing a printed circuit board claim 1 , comprising the steps of:forming a conductor trace that has a side extending in one direction on an insulating layer;forming on ...

TRANSPARENT CONDUCTIVE FILM

A transparent conductive film includes: a substrate film composed of a transparent resin; a high refractive index coat layer formed on a surface of the substrate film and having an optical refractive index higher than that of the substrate film a low refractive index coat layer formed on a surface of the high refractive index coat layer and having an optical refractive index lower than that of the high refractive index coat layer a moisture-proof underlying layer formed on a surface of the low refractive index coat layer and composed of silicon oxide; and a transparent wiring layer patterned on a surface of the underlying layer and composed of crystalline ITO having an optical refractive index higher than the underlying layer The crystallite size of ITO in the transparent wiring layer is 9 nm or less. 1. A transparent conductive film , characterized by:a substrate film composed of a transparent resin;a high refractive index coat layer formed on a surface of the substrate film, and having an optical refractive index higher than that of the substrate film;a low refractive index coat layer formed on a surface of the high refractive index coat layer, and having an optical refractive index lower than that of the high refractive index coat layer;a moisture-proof underlying layer formed on a surface of the low refractive index coat layer and composed of silicon oxide; anda transparent wiring layer patterned on a surface of the underlying layer and composed of crystalline ITO having an optical refractive index higher than that of the underlying layer;wherein crystallite size of ITO in the transparent wiring layer is 9 nm or less.2. A method for producing a transparent conductive film , the method characterized by:forming, on a surface of a multilayer film on the side of a low refractive index coat layer, a moisture-proof underlying layer composed of silicon oxide, the multilayer film being comprised of a high refractive index coat layer formed on a surface of a substrate ...

METHODS OF PATTERNING A CONDUCTOR ON A SUBSTRATE

A method of patterning a conductor on a substrate includes providing an inked elastomeric stamp inked with self-assembled monolayer-forming molecules and having a relief pattern with raised features. Then the raised features of the inked stamp contact a metal-coated visible light transparent substrate. Then the metal is etched to form an electrically conductive micropattern corresponding to the raised features of the inked stamp on the visible light transparent substrate. 1. A method of patterning a conductor on a substrate , comprising: a two-dimensional mesh of raised linear features having an average area density value of raised features between 0.5% to 20%, wherein the raised linear features have a width value between 0.5 to 25 micrometers;', 'a distance value between adjacent raised linear features of less than 1 millimeter;, 'providing an inked elastomeric stamp inked with self-assembled monolayer-forming molecules and having a relief pattern with raised features, the relief pattern having a low density region with a fill factor between 0.5% and 20%, measuring at least 5 square millimeters comprisingthe relief pattern further having a raised feature measuring at least 50 micrometers in width, wherein for a junction formed between the raised linear features and a larger raised feature, the raised linear feature width is widened by tapering before making contact to the larger raised feature;contacting the raised linear features of the inked elastomeric stamp to a metal-coated visible light transparent substrate; andetching the metal to form an electrically conductive micropattern corresponding to the raised features of the inked elastomeric stamp on the visible light transparent substrate.2. A method according to claim 1 , wherein the contacting step has a contact time in a range from 0.1 to 30 seconds.3. A method according to claim 1 , wherein the two-dimensional mesh of raised linear features has an average area density value of raised features between 0.5% to ...

Patterned Substrates With Darkened Conductor Traces

The present disclosure provides an article having (a) a substrate having a first nanostructured surface that is antireflective when exposed to air and an opposing second surface; and (b) a conductor micropattern disposed on the first surface of the substrate, the conductor micropattern formed by a plurality of traces defining a plurality of open area cells. The micropattern has an open area fraction greater than 80% and a uniform distribution of trace orientation. The traces of the conductor micropattern have a specular reflectance in a direction orthogonal to and toward the first surface of the substrate of less than 50%. Each of the traces has a width from 0.5 to 10 micrometer. The articles are useful in devices such as displays, in particular, touch screen displays useful for mobile hand held devices, tablets and computers. They also find use in antennas and for EMI shields 115-. (canceled)16. An article comprising:a substrate having a first nanostructured surface that is antireflective when exposed to air and an opposing second surfaces; anda conductor micropattern disposed on the first surface of the substrate, the conductor micropattern formed by a plurality of traces defining a plurality of open area cells,wherein the micropattern has an open area fraction greater than 80% and a uniform distribution of trace orientation;wherein the traces of the conductor micropattern have a specular reflectance in a direction orthogonal to and toward the first surface of the substrate of less than 50%; andwherein each of the traces has a width from 0.5 to 10 micrometer.17. The article of claim 16 , wherein the nanostructured surface comprises nanofeatures having a height of from 50 to 500 nanometers.18. The article of claim 16 , wherein the nanostructured surface comprises nanofeatures having a height-to-width ration of 2 to 1.19. The article of claim 16 , wherein the nanostructured surface has a reflectance of between 0.05 to 1%.20. The article of claim 16 , wherein the ...

ETCHING LIQUID COMPOSITION FOR MULTILAYER CONTAINING COPPER AND MOLYBDENUM AND PROCESS FOR ETCHING THEREOF

There is provided an etching liquid composition for a multilayer film containing copper and molybdenum. The etching liquid composition comprises: (A) a peroxosulfate ion source; (B) a copper ion source; and (C) at least one nitrogen compound source selected from the group consisting of ammonia, ammonium ions, amines, and alkyl ammonium ions and has pH 3.5 to 9. 1. An etching liquid composition for a multilayer film containing copper and molybdenum , the liquid composition comprising:(A) a peroxosulfate ion source;(B) a copper ion source; and(C) at least one nitrogen compound source selected from the group consisting of ammonia, ammonium ions, amines, and alkyl ammonium ions,the liquid composition having pH 3.5 to 9.2. The liquid composition according to claim 1 , wherein the peroxosulfate ion source (A) is at least one compound selected from the group consisting of ammonium peroxodisulfate claim 1 , potassium peroxodisulfate claim 1 , sodium peroxodisulfate claim 1 , and potassium hydrogen peroxomonosulfate.3. The liquid composition according to claim 1 , wherein the mixing ratio of the peroxosulfate ion source (A) to the copper ion source (B) is 0.01 to 20 on a molar basis.4. The liquid composition according to claim 1 , wherein the copper ion source (B) is at least one compound selected from the group consisting of copper claim 1 , copper sulfate claim 1 , copper nitrate claim 1 , and copper acetate.5. The liquid composition according to claim 1 , wherein the nitrogen compound source (C) is at least one compound selected from the group consisting of ammonia claim 1 , ammonium sulfate claim 1 , ammonium nitrate claim 1 , ammonium acetate claim 1 , ammonium peroxodisulfate claim 1 , and tetramethylammonium hydroxide.6. The liquid composition according to claim 1 , wherein the mixing ratio of the nitrogen compound source (C) to the copper ion source (B) is 4 to 100 on a molar basis.7. The liquid composition according to claim 1 , which further comprises (D) a ...

ETCHANT COMPOSITION, METAL WIRING, AND METHOD OF MANUFACTURING A DISPLAY SUBSTRATE

A wet etching composition usable for etching a copper-based wiring layer includes between about 40% by weight to about 60% by weight of phosphoric acid, between about 1% by weight to about 10% by weight of nitric acid, between about 3% by weight to about 15% by weight of acetic acid, between about 0.01% by weight to about 0.1% by weight of a copper-ion compound, between about 1% by weight to about 10% by weight of a nitric salt, between about 1% by weight to about 10% by weight of an acetic salt, and a remainder of water 1. A combination of patterned metal wire and a substrate having the metal wire formed thereon , the metal wire comprising:an oxide layer including indium and zinc; anda copper-based layer disposed on or under the oxide layer including indium and zinc, wherein a zinc oxide amount of the oxide layer including indium and zinc is equal to or more than 10% by weight and less than about 35% by weight.2. The combination of claim 1 , wherein a thickness of the copper-based layer is between about 1 claim 1 ,000 Å to about 3 μm claim 1 , and a thickness of the oxide layer including indium and zinc is between about 100 Å to about 500 Å.3. The combination of claim 1 , wherein a thickness of the copper-based layer is between about 1 μm to about 3 μm.4. The combination of claim 1 , wherein the oxide layer including indium and zinc is disposed on the copper-based layer.5. The combination of claim 1 , wherein a zinc oxide amount of the oxide layer including indium and zinc is equal to or more than 10% by weight and less than about 35% by weight.6. The combination of claim 1 , wherein the copper-based layer has a substantially trapezoidal cross sectional profile claim 1 , and the base taper angle of the cross sectional profile of the copper-based layer is substantially more than 50°.7. The combination of claim 6 , wherein the base taper angle of the copper-based layer is between about 60° to about 85°.8. The combination of claim 1 , wherein the oxide semiconductor ...

Printed wiring board and method for manufacturing printed wiring board

A method for manufacturing a printed wiring board includes forming metal posts on a conductor circuit formed on a resin insulating layer, forming the outermost resin layer on the resin insulating layer such that the metal posts is embedded in the outermost resin layer, forming a mask at a dam formation site for a dam structure of the outermost resin layer to surround at least part of a pad group including the metal posts on the outermost resin layer, and reducing a thickness of the outermost resin layer exposed from the mask such that end portions of the metal posts are exposed from the outermost resin layer, that the metal posts form the pad group, and that the outermost resin layer has the dam structure forming part of the outermost resin layer and formed to surround at least part of the pad group including the metal posts.

INSULATED CIRCUIT BOARD

An insulated circuit board having a ceramic substrate, a circuit layer on which a circuit pattern is formed and that is bonded to one surface of the ceramic substrate, and a metal layer bonded to the other surface of the ceramic substrate. The circuit layer has a first circuit layer that is bonded to the ceramic substrate and is made of aluminum and a second circuit layer that is bonded to the upper surface of the first circuit layer and is made of copper, the metal layer has a first metal layer that is bonded to the ceramic substrate and is made of aluminum and a second metal layer that is bonded to the upper surface of the first metal layer and is made of copper, and the thicknesses of the first circuit layer and the first metal layer are each 0.2 mm or more and 0.9 mm or less. 1. An insulated circuit board comprising:a ceramic substrate;a circuit layer that is bonded to one surface of the ceramic substrate and on which a circuit pattern is to be formed; anda metal layer bonded to the other surface of the ceramic substrate,wherein the circuit layer has a first circuit layer that is bonded to the ceramic substrate and is made of aluminum or an aluminum alloy, and a second circuit layer that is bonded to an upper surface of the first circuit layer and is made of copper or a copper alloy,the metal layer has a first metal layer that is bonded to the ceramic substrate and is made of aluminum or an aluminum alloy, and a second metal layer that is bonded to an upper surface of the first metal layer and is made of copper or a copper alloy,thicknesses of the first circuit layer and the first metal layer are equal to each other and are 0.2 mm or more and 0.9 mm or less,{'b': '1', 'the second circuit layer has a thickness T of 0.65 mm or more and 2.0 mm or less,'}{'b': 1', '2', '1', '2', '1', '2', '1', '2, 'an area ratio S/S of a bonding area S of the circuit layer to the ceramic substrate to a bonding area S of the metal layer to the ceramic substrate is 0.5 or more and 0.8 ...

METHOD OF MANUFACTURING BRAKE PEDAL COIL PRINTED CIRCUIT BOARD FOR VEHICLE

A method of manufacturing a brake pedal coil printed circuit board for vehicles is provided which is capable of allowing a wireless sensor to quickly sense whether physical energy from a driver is applied to a foot brake pedal to turn on rear brake lights. To solve the above problems, the method of manufacturing a brake pedal coil printed circuit board for vehicles includes preparing a first epoxy layer () having first copper foil () laminated on both surfaces thereof (S), laminating each of second epoxy layers (and ) on the first copper foil (), and laminating second copper foil () on each of the second epoxy layers (and ) (S), forming a through hole (A) passing through upper and lower surfaces, performing electroless copper plating on an inside surface of the through hole (A) and the second copper foil (), and forming an electrolytic copper-plated layer () on each of the electroless copper-plated layer () of the through hole (A) and the electroless copper-plated layer () formed on the second copper foil () (S), forming circuits having a predetermined pattern on the electrolytic copper-plated layer () and the electroless copper-plated layer () and forming a gap between the circuits to have the same size as the circuits (S), applying a PSR ink () onto the electrolytic copper-plated layer () (S), applying a marking ink () onto the PSR ink () (S), forming a nickel (Ni)-plated layer () around the through hole (A) and the hole land (S), and forming an Au-plated layer () on the Ni-plated layer () (S). 1. A method of manufacturing a brake pedal coil printed circuit board for vehicles , comprising:{'b': 100', '110', '100, 'preparing a first epoxy layer () having first copper foil () laminated on both surfaces thereof (S);'}{'b': 200', '200', '110', '210', '200', '200', '200, 'i': a', 'b', 'a', 'b, 'laminating each of second epoxy layer (and ) on the first copper foil (), and laminating second copper foil () on each of the second epoxy layers (and ) (S);'}{'b': 210', '220', ...

METHOD OF MANUFACTURING SUBSTRATE HAVING CAVITY

The method of manufacturing a substrate includes: forming a penetrating hole in a base layer; inserting a metal dummy part in the penetrating hole; forming an insulating portion made of synthetic resin to fill a ring-shaped gap between the penetrating hole and the dummy part; forming lower insulating layers, covering the bottom surface of the dummy part, that are made of synthetic resin on the bottom surface of the base layer to be continuous with the insulating portion; forming upper insulating layers, covering the top surface of the dummy part, that are made of synthetic resin on the top surface of the base layer to be continuous with the insulating portion; forming an exposing hole by routing in the upper insulating layers to expose the top surface of the dummy part; and forming a cavity by removing the dummy part exposed through the exposing hole by etching. 1. A method of manufacturing a substrate having a cavity for installing an electronic part therein , comprising:forming a penetrating hole for inserting a dummy part made of metal, said penetrating hole penetrating through a base layer;inserting the dummy part in the penetrating hole such that a ring-shaped gap is formed between an inner wall of the penetrating hole and an outer wall of the dummy part;filling said ring-shaped gap with an insulating portion made of synthetic resin;forming a lower insulating layer made of synthetic resin onto a bottom surface of the base layer so as to cover a bottom surface of the dummy part and so as to be continuous with the insulating portion;forming an upper insulating layer made of synthetic resin onto a top surface of the base layer so as to cover a top surface of the dummy part and so as to be continuous with the insulating portion;forming, by mechanical cutting, an exposing hole in either the upper insulating layer to expose the top surface of the dummy part or the lower insulating layer to expose the bottom surface of the dummy part; andchemically etching the dummy ...

SOLDER BOND SITE INCLUDING AN OPENING WITH DISCONTINOUS PROFILE

Apparatuses and methods for formation of a bond site including an opening with a discontinuous profile are disclosed herein. An example apparatus may at least include a substrate, a contact on the substrate, and a mask layer formed on the substrate and at least a portion of the contact. The mask layer may also include an opening formed therein, with the opening having a discontinuous profile from a top surface of the mask layer to the contact. 1. An apparatus , comprising:a substrate;a contact on the substrate; anda mask layer formed on the substrate and a portion of the contact, wherein an opening in the mask layer has a discontinuous profile from a top surface of the mask layer to the contact.2. The apparatus of claim 1 , wherein the opening in the mask layer further comprises a first sidewall extending from the top surface of the mask layer to a first edge of a step claim 1 , and a second sidewall that extends from a second edge of the step to the contact.3. The apparatus of claim 2 , wherein an angle of the first sidewall is different than an angle of the second sidewall.4. The apparatus of claim 3 , wherein the angle of the second sidewall is normal to the top surface of the mask layer.5. The apparatus of claim 2 , wherein the opening in the mask layer comprises a first opening and a second opening claim 2 , and wherein the first opening is defined by the first sidewall and the step claim 2 , and wherein the second opening is defined by the second sidewall.6. The apparatus of claim 1 , wherein a first sidewall of the opening is set back from a second sidewall of the opening by a step.7. The apparatus of claim 1 , further comprising first and second metal layers formed on a top side of the contact.8. The apparatus of claim 7 , wherein the first and second metal layers are formed in the opening of the mask layer claim 7 , wherein the opening of the mask layer is defined by first and second openings claim 7 , and wherein the second opening has a smaller diameter ...

Circuit board and method for manufacturing the same

A circuit board element includes a glass substrate, a first dielectric layer, and a first patterned metal layer. The glass substrate has an edge. The first dielectric layer is disposed on the glass substrate and has a central region and an edge region. The edge region is in contact with the edge of the glass substrate, and the thickness of the central region is greater than the thickness of the edge region. The first patterned metal layer is disposed on the glass substrate and in the central region of the first dielectric layer.

METHOD OF MANUFACTURING WIRING BOARD

A manufacturing method includes a step of forming a first plating mask on a base metal layer, a step of forming a main conductor layer on the base metal layer exposed from the first plating mask, a step of forming a second plating mask on them, a step of attaching a metal plating layer to an upper surface of the main conductor layer exposed from the second plating mask, a step of removing the first and second plating masks, a step of etching away a portion of the base metal layer to which the main conductor layer is not attached, and a step of forming a solder resist layer. 1. A method of manufacturing a wiring board comprising:a step of attaching a base metal layer serving as a wiring conductor to an upper surface of an insulating board;a step of forming a first plating mask on the base metal layer to expose the base metal layer into a shape corresponding to the wiring conductor;a step of attaching a main conductor layer serving as the wiring conductor by electrolytic plating, on the base metal layer exposed from the first plating mask;a step of forming a second plating mask on the first plating mask and the main conductor layer, to expose an upper surface of the main conductor layer having a portion corresponding to a semiconductor element connection pad; a step of attaching a metal plating layer by electrolytic plating to the upper surface of the main conductor layer exposed from the first and second plating masks;a step of removing the first and second plating masks;a step of etching away a portion of the base metal layer to which the main conductor layer is not attached, and forming the wiring conductor comprising the base metal layer and the main conductor layer, and having the metal plating layer attached to the upper surface of the semiconductor element connection pad; anda step of forming a solder resist layer having an opening to expose the semiconductor element connection pad, on the insulating board and the wiring conductor.2. The method of manufacturing ...

METHOD FOR FORMING ELECTRODE PATTERN ON SUBSTRATE BY LIGHT ANNEALING

A method for forming electrode patterns on a substrate is disclosed. A layer of conductive materials is formed on the substrate, and a portion of the conductive materials is annealed by an exposing manner. The layer of conductive materials after being exposed includes an annealed first portion and an unannealed second portion. One of the annealed first portion or the unannealed second portion is removed from the substrate to form electrode patterns on the substrate. 1. A method for forming electrode patterns on a substrate , comprising:forming a layer of conductive materials on the substrate;annealing a portion of the layer of conductive materials by exposing the layer of conductive materials, so that the layer of conductive materials comprise an annealed first portion and an unannealed second portion; andremoving one of the annealed first portion or the unannealed second portion to form electrode patterns on the substrate.2. The method according to claim 1 , wherein the layer of conductive materials is exposed using a photomask having a plurality of light shielding portions and a plurality of light transition portions.3. The method according to claim 2 , wherein the annealed first portion is corresponding to the light transition portions claim 2 , and the unannealed second portion is corresponding to the light shielding portions.4. The method according to claim 2 , wherein the photomask is located at a side of the layer of conductive materials opposite to the substrate claim 2 , the photomask and the layer of conductive materials define a space therebetween.5. The method according to claim 4 , wherein the space is less than or equal to 100 micrometers.6. The method according to claim 2 , wherein the photomask is located on and contact with a surface of the layer of conductive materials opposite to the substrate.7. The method according to claim 6 , wherein the photomask is formed by light shielding materials coated on the surface of the layer of conductive materials ...

METHOD FOR PRODUCING PRINTED-WIRING BOARD

The present invention provides a method for producing a printed-wiring board in a semi-additive process, comprising the steps of: providing a chemical copper plating on an insulation layer or forming a copper thin film on the insulation layer using a sputtering method; subjecting the obtained copper surface to a roughening treatment using an etching solution containing 0.1 to 3% by mass of hydrogen peroxide, 0.3 to 5% by mass of sulfuric acid, 0.1 to 3 ppm of halogen ion and 0.003 to 0.3% by mass of tetrazoles; attaching a dry film resist to the copper surface after the roughening treatment to perform exposure and development and providing an electrolytic copper plating to an opening after the exposure; and subjecting the remaining dry film resist to a stripping treatment using a resist stripping liquid containing 0.5 to 20% by mass of monoethanolamine, 0.2 to 10% by mass of quaternary ammonium hydroxide, 0.01 to 10% by mass of ethylene glycols and 0.01 to 0.5% by mass of azoles. 1. A method for producing a printed-wiring board in a semi-additive process , comprising the steps of:providing a chemical copper plating on an insulation layer or forming a copper thin film on the insulation layer using a sputtering method;subjecting the obtained copper surface to a roughening treatment using an etching solution containing 0.1 to 3% by mass of hydrogen peroxide, 0.3 to 5% by mass of sulfuric acid, 0.1 to 3 ppm of halogen ion and 0.003 to 0.3% by mass of tetrazoles;attaching a dry film resist to the copper surface after the roughening treatment to perform exposure and development and providing an electrolytic copper plating to an opening after the exposure; andsubjecting the remaining dry film resist to a stripping treatment using a resist stripping liquid containing 0.5 to 20% by mass of monoethanolamine, 0.2 to 10% by mass of quaternary ammonium hydroxide, 0.01 to 10% by mass of ethylene glycols and 0.01 to 0.5% by mass of azoles.2. The method for producing a printed- ...

METHOD FOR MANUFACTURING CIRCUIT BOARD AND CIRCUIT BOARD

The present invention relates to a method for manufacturing a circuit board including the steps of preparing a substrate containing silicon at least at a surface, applying a paste containing aluminum particles onto the substrate, forming a conductor layer on the substrate by firing the substrate to which the paste has been applied, forming a resist film having a specific pattern on the conductor layer, and removing with an etchant, the conductor layer in a portion where the resist film has not been formed, the etchant containing fluoride ions and metal ions of a metal M of which standard electrode potential is higher in value than a standard electrode potential of aluminum, and to a circuit board which can be manufactured with such a method. 1. A method for manufacturing a circuit board , comprising the steps of:preparing a substrate containing silicon at least at a surface;applying a paste containing aluminum particles onto the substrate;forming a conductor layer on the substrate by firing the substrate to which the paste has been applied;forming a resist film having a specific pattern on the conductor layer; andremoving with an etchant, the conductor layer in a portion where the resist film has not been formed,the etchant containing fluoride ions and metal ions of a metal M of which standard electrode potential is higher in value than a standard electrode potential of aluminum.2. The method for manufacturing a circuit board according to claim 1 , whereinthe metal ions of the metal M are iron ions or copper ions, and the fluoride ions are derived from at least one compound selected from the group consisting of hydrogen fluoride, tetrafluorosilicon, hexafluorosilicic acid, hexafluorosilicate, boron trifluoride, fluoroboric acid, fluoroborate, phosphorus fluoride, ammonium fluoride, silver fluoride, aluminum fluoride, cesium fluoride, potassium fluoride, sodium fluoride, and lithium fluoride.3. The method for manufacturing a circuit board according to claim 1 , ...

CONDUCTIVE FILM SUBSTRATE, TRANSPARENT CONDUCTIVE FILM, AND METHOD FOR PRODUCING TRANSPARENT CONDUCTIVE FILM

Provided is a transparent conductive film including a transparent electrode layer composed of a patterned thin metal wire on at least one surface of a transparent film substrate. The line width of the wire is 5 μm or less. The wire includes a first metal layer and a second metal layer that is in contact with the first metal layer, in this order from a transparent film substrate side. Both of the first and second metal layers contain copper in an amount of 90% by weight or more. The total film thickness of the first and second metal layers is 150 to 1000 nm. The diffraction angle 2θ of the (111) plane of the second metal layer is less than 43.400° as measured using a CuKα ray as an X-ray source, and the first metal layer has crystal properties different from those of the second metal layer.

TREATMENT OF SHAPED BODIES COMPRISING COPPER WITH A MIXTURE COMPRISING CHLORINE-FREE ACIDS AND OXIDIZING AGENT

A process for treatment of shaped bodies comprising copper, wherein an aqueous mixture (M) comprising (a.) chlorine-free acids without carboxyl groups, (b.) oxidizing agents, (c.) aqueous solvent and optionally additional additives is contacted with the shaped body. Another characteristic feature of the process is that the aqueous mixture (M) after the etching or pickling additionally comprises (e.) dissolved copper and is separated from the solid. Also encompassed is a process for workup of the aqueous mixture (M) which has been separated and additionally comprises dissolved copper by electrolysis. Further provided are mixtures (MI) comprising (a.) from 10 to 40% by weight of methanesulfonic acid, (b.) from 10 to 20% by weight of hydrogen peroxide and (c.) from 40 to 80% by weight of water, and the use thereof for etching or pickling of shaped bodies comprising copper. 1. A process for treating a shaped body , the process comprising: contacting an aqueous mixture with the shaped body ,wherein:the shaped body comprises copper, andthe aqueous mixture comprises(a) a chlorine-free acid without carboxyl groups,(b) an oxidizing agent, and(c) an aqueous solvent.2. The process according to claim 1 , wherein the aqueous mixture further comprises(d) an additional additive.3. The process according to claim 1 , wherein the aqueous mixture comprisesfrom 10 to 40% by weight of the chlorine-free acid without carboxyl groups (a),from 1 to 50% by weight of the oxidizing agent (b),from 10 to 89% by weight of the aqueous solvent (c), andfrom 0 to 10% by weight of an additional additives (d),based on a total amount of components (a), (b), (c), and (d).4. The process according to claim 1 , wherein the aqueous mixture has a pH of from −0.5 to 5.5. The process according to claim 1 , wherein the copper is present at least partly on at least one surface of the shaped body and is contacted with the aqueous mixture.6. The process according to claim 1 , wherein the shaped body is a printed ...

THIN FLEXIBLE CIRCUITS

An approach for making thin flexible circuits. A layer of dielectric may have one or two surfaces coated with metal. The dielectric and the metal may each have a sub-mil thickness. The dielectric may be held in a fixture for fabrication like that of integrated circuits. The metal may be patterned and have components attached. More layers of dielectric and patterned metal may be added to the flexible circuit. Also bond pads and connecting vias may be fabricated in the flexible circuit. The flexible circuit may be cut into a plurality of smaller flexible circuits. 1. A method for fabricating a flexible circuit , comprising:providing a first dielectric layer having a first metal layer formed on a first side of the first dielectric layer;forming a first dielectric layer;forming a first metal layer on a first side of the first dielectric layer;situating a mask having a pattern on the first metal layer;processing the pattern into the first metal layer;removing the mask;forming a second dielectric layer on the first metal layer;forming a lift-off resist layer on the second dielectric layer;forming a photosensitive resist layer having a pattern of at least one opening on the lift-off resist layer;etching at least one opening through the lift-off resist layer and the second dielectric layer forming an opening through the lift-off resist layer and second dielectric layer to the first metal layer; anddepositing a metal towards the at least one opening to form at least one bond pad on the first metal layer.2. The method of claim 1 , further comprising:removing the lift-off resist layer;forming a second metal layer on a second side of the first dielectric layer; andrepeating the steps from situating a mask with a pattern on the first metal layer through removing the lift-off resist layer for the second metal layer in lieu of the first metal layer, and a third dielectric layer in lieu of the second dielectric layer.3. The method of claim 2 , wherein the first dielectric layer ...

HOT MELT COMPOSITIONS WITH IMPROVED ETCH RESISTANCE

Hot melt compositions include non-aromatic cyclic (alkyl)acrylates and low acid number waxes. Upon application of actinic radiation, the hot melt compositions cure to form resists. They may be stripped from substrates with high alkaline strippers. The hot melt compositions may be used in the manufacture of printed circuit boards and photovoltaic devices. 1. A hot melt composition comprising one or more non-aromatic cyclic (alkyl)acrylates , one or more waxes comprising an acid number of 0 to 30 mg KOH/g and one or more radical initiators.2. The hot melt composition of claim 1 , further comprising one or more waxes comprising an acid number of 100 mg KOH/g or greater wherein a weight ratio of the one or more waxes comprising an acid number of 0 to 30 mg KOH/g to the one or more waxes comprising an acid number of 100 mg KOH/g is 1:1 to 5:1.3. The hot melt composition of claim 2 , wherein the weight ratio is 1:1 to 2:1.4. The hot melt composition of claim 1 , further comprising one or more non-cyclic (alkyl)acrylates free of acid groups.5. The hot melt composition of claim 1 , wherein the one or more waxes comprising an acid number of 0 to 30 mg KOH/g are chosen from candelilla waxes claim 1 , paraffin waxes claim 1 , esterified montan waxes claim 1 , ozokerite waxes claim 1 , ceresin waxes claim 1 , synthesized hydrocarbon waxes and hydrogenated waxes.6. A method comprising:a. providing a hot melt composition comprising one or more non-aromatic cyclic (alkyl)acrylates, one or more waxes comprising and acid number of 0 to 30 mg KOH/g and one or more radical initiators;b. selectively depositing the hot melt composition on a substrate;c. applying actinic radiation to the hot melts composition to cure the composition;d. etching sections of the substrate not covered with the cured hot melt composition; ande. removing the cured hot melt composition from the substrate with a base comprising a pH of 11 or greater to form a patterned article.7. The method of claim 6 , wherein ...

METHOD OF SELECTIVELY ETCHING A METAL LAYER FROM A MICROSTRUCTURE

The invention relates to a method of etching a portion of a metal layer of a microstructure comprised of the metal layer disposed on a transparent conducting oxide (TCO) layer, and in particular, to selectively etching the portion of the metal layer and not the TCO layer. 1. A method of selectively etching a portion of a metal layer of a microstructure , wherein the microstructure is comprised of the metal layer disposed on a transparent conducting oxide (TCO) layer , the method comprising contacting the microstructure with an etchant formulation comprising a mixture of cupric halide and a solution of an amine and/or ammonium compound.2. The method of claim 1 , wherein the ammonium compound is at least one of an ammonium halide and ammonium hydroxide.3. The method of claim 2 , wherein the ammonium compound is ammonium chloride and ammonium hydroxide.4. The method of claim 1 , wherein the amine compound has a boiling point higher than 100° C.5. The method of claim 1 , wherein the amine compound is at least one of an alkyl amine and an alkoxy amine.6. The method of claim 5 , wherein the amine compound is an alkoxy amine.7. The method of claim 6 , wherein the amine compound is monoethanol amine.8. The method of claim 1 , wherein the amine compound is a monodentate ligand.9. The method of claim 1 , wherein the amine compound is a bidentate ligand.10. The method of claim 1 , wherein the etchant formulation has a pH above 7.11. The method of claim 10 , wherein the pH of the etchant formulation is between about 8.5 and 9.12. The method of claim 1 , wherein a mole ratio of cupric halide to the ammonium compound is about 1:4.13. The method of claim 1 , wherein the etchant formulation is heated to between about 50° C. and about 100° C. prior to contacting the microstructure.14. The method of claim 1 , wherein the etchant formulation is contacted with the microstructure of a period of between about 30 seconds and about 1 claim 1 ,200 seconds.15. The method of claim 1 , wherein ...

PRINT ELEMENT SUBSTRATE, METHOD OF MANUFACTURING THE SAME, PRINTHEAD AND PRINTING APPARATUS

A method of manufacturing a print element substrate, comprising preparing a substrate, including a first region and a second region, in which a printing portion is formed on the first region, and a wiring pattern connected to the printing portion is formed on the first region and the second region, forming an insulating film covering the printing portion and the wiring pattern, and forming a conductive cavitation-resistant film on the insulating film, wherein in the forming the insulating film, the insulating film is formed such that a side surface of a portion of the insulating film, which is formed on the second region, includes an inclined face. 1. A method of manufacturing a print element substrate , comprising steps of:preparing a substrate including a first region, a second region different from the first region, a printing portion configured to print by supplying thermal energy to a liquid and formed on the first region, and a wiring pattern electrically connected to the printing portion and formed on the first region and on the second region;forming an insulating film covering the printing portion and the wiring pattern, the insulating film being formed on the first region and on the second region; andforming a conductive cavitation-resistant film on the insulating film by forming a conductive member on the insulating film, and removing at least a portion of the conductive member, the portion of the conductive member being formed on the second region,wherein in the step of forming the insulating film, the insulating film is formed such that a side surface of a portion of the insulating film, portion of the insulating film being formed on the second region, includes an inclined face.2. The method according to claim 1 , further comprising a step of forming the wiring pattern claim 1 ,wherein the step of forming the wiring pattern includes:a first step of forming a metal pattern on the first region and the second region by a patterning method; anda second step ...

METHOD OF MANUFACTURING A MULTI-LAYER PRINTED CIRCUIT BOARD

A method of manufacturing a multi-layer printed circuit board by bonding together a plurality of circuit board layers, each of which includes a substrate and a conductive circuit pattern on at least one surface of the substrate, includes the steps of: coating the surface of the substrate with a continuous layer of conductive material, masking the layer with a resist, etching away a part of the conductive material so as to obtain the circuit pattern with conductive parts separated by gaps, and filling the gaps with an electrically insulating adhesive material to a level that is at least equal to the thickness of the layer of conductive material. The resist is left on the conductive parts and the adhesive material is selected to be chemically compatible with the resist. 1. A method of manufacturing a multi-layer printed circuit board by bonding together a plurality of circuit board layers , each of the plurality of circuit board layers including a substrate and a conductive circuit pattern on at least one surface of the substrate , the method comprising the steps of:coating the surface of the substrate with a continuous layer of conductive material;masking the layer with a resist;etching away a part of the conductive material so as to obtain the circuit pattern with conductive parts separated by gaps; andfilling the gaps with an electrically insulating adhesive material to a level that is at least equal to a thickness of the layer of conductive material,wherein the resist is left on the conductive parts and the adhesive material is selected to be chemically compatible with the resist.2. The method according to claim 1 , wherein the adhesive material is identical with the material of the resist.3. The method according to claim 1 , wherein claim 1 , in the step of filling the adhesive material into the gaps claim 1 , the same adhesive material is also applied onto the conductive parts and/or onto the resist that has been left thereon.4. The method according to claim 1 , ...

CIRCUIT BOARD AND METHOD FOR MANUFACTURING THE SAME

A circuit board element includes a glass substrate, a first dielectric layer, and a first patterned metal layer. The glass substrate has an edge. The first dielectric layer is disposed on the glass substrate and has a central region and an edge region. The edge region is in contact with the edge of the glass substrate, and the thickness of the central region is greater than the thickness of the edge region. The first patterned metal layer is disposed on the glass substrate and in the central region of the first dielectric layer. 1. A method for manufacturing a circuit board , comprising:forming a first sacrificial metal layer on a carrier, wherein the first sacrificial metal layer has a plurality of first openings;forming a first etching stop layer on the carrier, wherein the first etching stop layer covers the first sacrificial metal layer;forming a patterned resist on the first etching stop layer, wherein the patterned resist has a plurality of second openings and a intaglioed pattern, the second openings respectively correspond to the first openings to expose a part of the first sacrificial metal layer, and the intaglioed pattern exposes a part of the first etching stop layer;forming a plurality of metal bump in the first openings and the second openings and forming a first circuit layer in the intaglioed pattern;removing the patterned resist;forming a build-up structure on the first etching stop layer, wherein the build-up structure includes a dielectric layer, a plurality of conductive vias, and at least one second circuit layer, the dielectric layer covers the metal bumps and the first circuit layer, the conductive vias is formed in the dielectric layer, the second circuit layer is formed on the dielectric layer, the conductive vias connects the first circuit layer and the second circuit layer;a second etching stop layer is formed on the dielectric layer, wherein the second etching stop layer covers the second circuit layer;separating the carrier and the first ...

MANUFACTURING METHOD OF COMPOSITE SUBSTRATE

A manufacturing method of a composite substrate is provided. A first conductive layer is formed on a first liquid crystal polymer layer. The first conductive layer is patterned to form a patterned first conductive layer. A second liquid crystal polymer layer including a soluble liquid crystal polymer is formed to cover the patterned first conductive layer. The second liquid crystal polymer layer which is on the patterned first conductive layer is removed. 1. A manufacturing method of a composite substrate , comprising:forming a first conductive layer on a first liquid crystal polymer layer;patterning the first conductive layer to form a patterned first conductive layer;forming a second liquid crystal polymer layer comprising a soluble liquid crystal polymer to cover the patterned first conductive layer; andremoving the second liquid crystal polymer layer which is on the patterned first conductive layer.2. The manufacturing method of claim 1 , wherein forming the second liquid crystal polymer layer to cover the patterned first conductive layer comprises:coating a mixture comprising the soluble liquid crystal polymer and a solvent on the first liquid crystal polymer layer; andremoving the solvent to form the second liquid crystal polymer layer.3. The manufacturing method of claim 1 , wherein the soluble liquid crystal polymer comprises a repeating unit represented by a formula shown below:{'br': None, '\ue8a0Y—Ar—X—Ar—Z\ue8a0,'}wherein Ar is 1,4-phenylene, 1,3-phenylene, 2,6-naphthalene, or 4,4′-biphenylene; Y is —O— or —NH—; Z is —C═O—; and X is amino group, carboxamido group, imido/imino group, amidino group, aminocarbonylamino group, aminothiocarbonyl group, aminocarbonyloxy group, aminosulfonyl group, aminosulfonyloxy group, aminosulfonylamino group, carboxyl ester group, (carboxyl ester)amino group, (alkoxycarbonyl)oxy group, alkoxycarbonyl group, hydroxyamino group, alkoxyamino group, cyanato group, isocyanato group, or a combination thereof.4. The manufacturing ...

CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF

A circuit board and a manufacturing method thereof are provided. A dielectric layer is formed on a substrate, wherein an internal circuit layer is formed on the substrate and the dielectric layer covers the internal circuit layer. A first trench, a second trench and an opening are formed in the dielectric layer. The opening is located below the first trench and connected with the first trench, and a portion of the internal circuit layer is exposed by the opening. A patterned conductive layer is formed on the dielectric layer. The patterned conductive layer covers a portion of the dielectric layer and fills the first trench, the second trench and the opening so as to form a first circuit layer, a second circuit layer and a conductive through via, respectively, wherein the conductive through via is electrically connected with the first circuit layer and the internal circuit layer. 1. A manufacturing method of a circuit board comprising:forming a dielectric layer on a substrate, wherein the substrate has an internal circuit layer formed thereon, and the dielectric layer covers the internal circuit layer;forming a first trench, a second trench, and an opening in the dielectric layer, wherein the opening is located below the first trench and is connected with the first trench, and the opening exposes a portion of the internal circuit layer;forming a patterned conductive layer on the dielectric layer, the patterned conductive layer covering a portion of the dielectric layer and filling the first trench, the second trench and the opening, so as to form a first circuit layer, a second circuit layer and a conductive through via, wherein the conductive through via is electrically connected with the first circuit layer and the internal circuit layer.2. The manufacturing method of a circuit board according to claim 1 , wherein the first circuit layer comprises a first embedded circuit layer and a first surface circuit layer claim 1 , the first embedded circuit layer being ...

PRINTED CIRCUIT BOARD AND METHOD FOR MANUFACTURING THE SAME

There is provided a method for manufacturing a printed circuit board including: preparing a substrate having a conductive layer formed on at least a portion thereof; forming an insulating layer formed with an opening through which a portion of the conductive layer is exposed on the substrate; forming a plating seed layer on the insulating layer and the exposed conductive layer; forming an electroplating layer on the plating seed layer by overplating the plating seed layer; and etching the overplated portion in a lump to form a circuit layer in the opening. 1. A method for manufacturing a printed circuit board , the method comprising:preparing a substrate having a conductive layer formed on at least a portion thereof;forming an insulating layer formed with an opening through which a portion of the conductive layer is exposed on the substrate;forming a plating seed layer on the insulating layer and the exposed conductive layer;forming an electroplating layer on the plating seed layer by overplating the plating seed layer; andetching the overplated portion in a lump to form a circuit layer in the opening.2. The method of claim 1 , wherein the forming of the electroplating layer includes overplating the plating seed layer until an exposed surface of the electroplating layer is planarized.3. The method of claim 1 , wherein the etching of the overplated portion in a lump includes etching the overplated portion in a lump until the insulating layer is exposed.4. The method of claim 1 , wherein the etching of the overplated portion in a lump includes etching the overplated portion in a lump so that the electroplating layer and the plating seed layer of 1 μm or less remains outside the insulating layer and the electroplating layer and the plating seed layer of 1 μm or less which are formed outside the insulating layer serve as the plating seed layer for forming additional circuit layer.5. The method of claim 1 , wherein the forming of the plating seed layer includes forming ...

PRINTED WIRING BOARD WITH METAL POST AND METHOD FOR MANUFACTURING THE SAME

A printed wiring board includes a resin insulating layer, a conductor layer formed on the resin insulating layer and including conductor pads, a solder resist layer formed on the resin insulating layer such that the solder resist layer is covering the conductor layer and has opening portions exposing the conductor pads, respectively, and metal posts formed on the conductor pads such that each of the metal posts is protruding from the solder resist layer and has a side surface forming an angle with respect to a surface of the solder resist layer. 1. A printed wiring board , comprising:a resin insulating layer;a conductor layer formed on the resin insulating layer and comprising a plurality of conductor pads;a solder resist layer formed on the resin insulating layer such that the solder resist layer is covering the conductor layer and has a plurality of opening portions exposing the plurality of conductor pads, respectively; anda plurality of metal posts formed on the plurality of conductor pads such that each of the metal posts is protruding from the solder resist layer and has a side surface forming an angle with respect to a surface of the solder resist layer.2. A printed wiring board according to claim 1 , wherein each of the metal posts has the side surface such that a portion of the side surface protruding from the solder resist layer forms the angle in a range of 45 degrees to 90 degrees with respect to the surface of the solder resist layer.3. A printed wiring board according to claim 1 , wherein the plurality of metal posts comprises electroless nickel plating.4. A printed wiring board according to claim 3 , wherein the plurality of metal posts comprises the electroless nickel plating having a phosphorus content in a range of 5% to 12%.5. A printed wiring board according to claim 1 , further comprising:an intermediate metal layer formed on the plurality of metal posts such that the intermediate metal layer is formed only on an upper surface of each of the ...

CIRCUIT BOARD AND METHOD FOR MANUFACTURING THE SAME

A circuit board element includes a glass substrate, a first dielectric layer, and a first patterned metal layer. The glass substrate has an edge. The first dielectric layer is disposed on the glass substrate and has a central region and an edge region. The edge region is in contact with the edge of the glass substrate, and the thickness of the central region is greater than the thickness of the edge region. The first patterned metal layer is disposed on the glass substrate and in the central region of the first dielectric layer. 1. A method for manufacturing a circuit board , comprising:forming a first sacrificial metal layer on a carrier, wherein the first sacrificial metal layer has a plurality of first openings;forming a first etching stop layer on the carrier, wherein the first etching stop layer covers the first sacrificial metal layer;forming a patterned resist on the first etching stop layer, wherein the patterned resist has a plurality of second openings and an intaglioed pattern, the second openings respectively correspond to the first openings to expose a part of the first sacrificial metal layer, and the intaglioed pattern exposes a part of the first etching stop layer;forming a plurality of metal bump in the first openings and the second openings and forming a first circuit layer in the intaglioed pattern;removing the patterned resist;forming a build-up structure on the first etching stop layer, wherein the build-up structure includes a dielectric layer, a plurality of conductive vias, and at least one second circuit layer, the dielectric layer covers the metal bumps and the first circuit layer, the conductive vias is formed in the dielectric layer, the second circuit layer is formed on the dielectric layer, the conductive vias connects the first circuit layer and the second circuit layer;a second etching stop layer is formed on the dielectric layer, wherein the second etching stop layer covers the second circuit layer;separating the carrier and the ...

ULTRA-THIN COPPER FOIL, ULTRA-THIN COPPER FOIL WITH CARRIER, AND METHOD FOR MANUFACTURING PRINTED WIRING BOARD

An extremely thin copper foil is provided that enables formation of highly fine different wiring patterns with a line/space (L/S) of 10 μm or less/10 μm or less on two sides of the copper foil and is thus usable as an inexpensive and readily processable substitution for silicon and glass interposers. The extremely thin copper foil includes, in sequence, a first extremely thin copper layer, an etching stopper layer, and the second extremely thin copper layer. Two sides of the extremely thin copper foil each have an arithmetic average roughness Ra of 20 nm or less. 1. An extremely thin copper foil comprising , in sequence:a first extremely thin copper layer;an etching stopper layer; anda second extremely thin copper layer,wherein two sides of the extremely thin copper foil each have an arithmetic average roughness Ra of 20 nm or less.2. The extremely thin copper foil according to claim 1 , wherein the etching stopper layer is composed of at least one metal selected from the group consisting of Al claim 1 , Nb claim 1 , Zr claim 1 , Cr claim 1 , W claim 1 , Ta claim 1 , Co claim 1 , Ti claim 1 , Ag claim 1 , Ni claim 1 , and Mo.3. The extremely thin copper foil according to claim 1 , wherein the first extremely thin copper layer and the second extremely thin copper layer each have a thickness of 0.05 to 1.0 μm and the etching stopper layer has a thickness of 0.05 to 1.0 μm.4. The extremely thin copper foil according to claim 1 , wherein the extremely thin copper foil has a thickness of 0.15 to 3.0 μm.5. The extremely thin copper foil according to claim 1 , wherein the two sides of the extremely thin copper foil each have an arithmetic average roughness Ra of 0.1 to 20 nm.6. The extremely thin copper foil according to claim 1 , wherein the first extremely thin copper layer claim 1 , the etching stopper layer claim 1 , and the second extremely thin copper layer are sputtered films.7. An extremely thin copper foil with a carrier claim 1 , comprising:a carrier composed of ...

PRINTED WIRING BOARD AND METHOD FOR MANUFACTURING PRINTED WIRING BOARD

A printed wiring board includes a resin insulating layer, a conductor circuit formed on the resin insulating layer, an outermost resin layer formed on the resin insulating layer such that the outermost resin layer covers the conductor circuit, and multiple metal posts formed on the conductor circuit such that the metal posts have end portions exposed from the outermost resin layer and that the metal posts form a pad group. The outermost resin layer has a dam structure forming part of the outermost resin layer such that the dam structure is formed to surround at least part of the pad group including the metal posts. 1. A printed wiring board , comprising:a resin insulating layer;a conductor circuit formed on the resin insulating layer;an outermost resin layer formed on the resin insulating layer such that the outermost resin layer covers the conductor circuit; anda plurality of metal posts formed on the conductor circuit such that the metal posts have end portions exposed from the outermost resin layer and that the plurality of metal posts forms a pad group,wherein the outermost resin layer has a dam structure forming part of the outermost resin layer such that the dam structure is formed to surround at least part of the pad group comprising the plurality of metal posts.2. The printed wiring board according to claim 1 , wherein the resin insulating layer and the outermost resin layer are formed of same resin material.3. The printed wiring board according to claim 1 , wherein the dam structure has a trapezoidal cross-sectional shape.4. The printed wiring board according to claim 1 , wherein the dam structure has a metal pattern forming a mask for forming the dam structure such that the metal pattern is formed on the dam structure.5. The printed wiring board according to claim 3 , wherein the dam structure is formed such that a lower base of the trapezoidal cross-sectional shape has a length in a range of 50 to 250 μm claim 3 , and a height in a range of 10 to 30 μm.6. ...

CIRCUIT BOARD MATERIAL

A circuit board material includes an electrical resistance material layer having a preselected resistivity adhered to the support layer, and a barrier layer adhered to the electrical resistive layer, and a conductive layer adhered to the barrier layer, wherein the barrier layer is plated on the conductive material such that the resistance of the subsequently applied resistive layer does not vary substantially during exposure to printed circuit board processing chemistries. The process for making the material is directed to adjusting the electro deposition of the barrier layer by using the time for etching the resistive layer of the circuit board material in a standard etching bath. 1. A circuit board material comprising an electrical resistance material layer having a preselected resistivity adhered to the support layer , a barrier layer adhered to the electrical resistive layer , and a conductive layer adhered to the barrier layer , wherein the barrier layer is plated on the conductive material such that the resistance of the subsequently applied resistive layer does not vary substantially during exposure to printed circuit board processing chemistries.2. The circuit board material according to wherein the application of the barrier layer is controlled by etch time in a 1 molar copper sulfate solution with an etch time ranging from 10 to 18 minutes.3. The circuit board material according to wherein the application of the barrier layer is controlled by etch time in a 1 molar copper sulfate solution with an etch time ranging from 11 to 17 minutes.4. The circuit board material according to wherein the application of the barrier layer is controlled by etch time in a 1 molar copper sulfate solution with an etch time ranging from 13 to 15 minutes.5. The circuit board material according to wherein the application of the barrier layer is controlled by etch time in a 1 molar copper sulfate solution with an etch time of about 14 minutes.6. The circuit board material ...

Dummy core plus plating resist restrict resin process and structure

A printed circuit board (PCB) has multiple layers, where select portions of inner layer circuitry, referred to as inner core circuitry, are exposed from the remaining layers. The PCB having an exposed inner core circuitry is formed using a dummy core plus plating resist process. The select inner core circuitry is part of an inner core. The inner core corresponding to the exposed inner core circuitry forms a semi-flexible PCB portion. The semi-flexible PCB portion is an extension of the remaining adjacent multiple layer PCB. The remaining portion of the multiple layer PCB is rigid. The inner core is common to both the semi-flexible PCB portion and the remaining rigid PCB portion.

RIGID-BEND PRINTED CIRCUIT BOARD FABRICATION

A printed circuit board (PCB) has multiple layers, where select portions of one or more conductive layers, referred to as core circuitry, form a semi-flexible PCB portion that is protected by an exposed prepreg layer. The semi-flexible PCB portion having an exposed prepreg layer is formed using a dummy core process that leaves the exposed prepreg layer smooth and undamaged. The core circuitry is part of a core structure. The semi-flexible PCB portion is an extension of the remaining adjacent multiple layer PCB. The remaining portion of the multiple layer PCB is rigid. The core structure is common to both the semi-flexible PCB portion and the remaining rigid PCB portion. 1. A printed circuit board comprising:a. a rigid printed circuit board portion comprising a laminated stack of a plurality of non-conducting layers and a plurality of conductive layers, wherein the laminated stack further comprises a first portion of a core structure; andb. a semi-flexible printed circuit board portion comprising a second portion of the core structure, wherein the core structure is a continuous structure that extends through both the rigid printed circuit board portion and the semi-flexible printed circuit board portion, further wherein the second portion of the core structure comprises core circuitry and the semi-flexible printed circuit board portion further comprises an exposed non-conductive layer covering the core circuitry, wherein the exposed non-conductive layer has an exposed surface that is smooth.2. The printed circuit board of wherein each of the conductive layers is pattern etched.3. The printed circuit board of further comprising one or more plated through hole vias in the rigid printed circuit board portion.4. The printed circuit board of wherein the rigid printed circuit board portion comprises a first rigid printed circuit board portion claim 1 , further wherein the printed circuit board further comprises a second rigid printed circuit board portion comprising a ...

Printed circuit board and manufacturing method thereof

Disclosed herein are a printed circuit board and a manufacturing method thereof capable of improving poor inter-layer conduction by increasing inter-layer insulating property and rigidity. The manufacturing method of a printed circuit board includes: laminating a copper foil layer on upper and lower surfaces of an insulating layer; coating an insulating material on a surface of the copper foil layer; forming a circuit layer by etching the copper foil layer; laminating an insulator on the copper foil layer so as to enclose the insulating material and the circuit layer; forming a via in the insulator so as to be communicated with the circuit layer; and forming a circuit pattern on the insulator.

WIRING SUBSTRATE

A wiring substrate includes a first insulation layer covering a first wiring layer, a wiring pattern formed on an upper surface of the first insulation layer, and a via formed in a via hole of the first insulation layer to electrically connect the wiring pattern and the first wiring layer. The via includes a via seed layer and a filled portion filling the via hole. The wiring pattern includes a wiring seed layer formed on the upper surface of the first insulation layer and a pattern layer formed on the wiring seed layer. The via seed layer is formed from a metal acting to adsorb a plating enhancement agent, which enhances formation of the filled portion and the pattern layer in an electrolytic plating solution. The wiring seed layer is formed from a metal not acting to adsorb the plating enhancement agent as compared to the via seed layer. 1. A wiring substrate comprising:a first wiring layer;a first insulation layer covering the first wiring layer and including a via hole that exposes a portion of an upper surface of the first wiring layer; anda second wiring layer including a wiring pattern and a via, wherein the wiring pattern is formed on an upper surface of the first insulation layer, and the via is formed in the via hole to electrically connect the wiring pattern and the first wiring layer, wherein a via seed layer formed on a wall surface of the first insulation layer that defines the via hole, and', 'a filled portion formed in the via hole in which the via seed layer is formed, wherein the via hole is filled with the filled portion,, 'the via includes'} a wiring seed layer formed on the upper surface of the first insulation layer, and', 'a pattern layer formed on the wiring seed layer,, 'the wiring pattern includes'}the via seed layer is formed from a metal material that acts to adsorb a plating enhancement agent which enhances formation of the filled portion and the pattern layer in an electrolytic plating solution, andthe wiring seed layer is formed from a ...

Process For The Production Of A Layered Body And Layered Bodies Without Masking Obtainable Therefrom

A process for the production of a layered body S2 (), comprising the process steps: i) provision of a layered body S1 () comprising a substrate () and an electrically conductive layer () which is applied to the substrate () and comprises an electrically conductive polymer P1; ii) bringing of at least a first region D() of the electrically conductive layer () into contact with a composition Z1 for reduction of the electrical conductivity of this first region D(), wherein the electrically conductive layer () has a temperature in a range of from more than 40 to 100° C. during the bringing into contact. 1. A process for the production of a layered body S2 , comprising the process steps:i) provision of a layered body S1 comprising a substrate and an electrically conductive layer which is applied to the substrate and comprises an electrically conductive polymer P1;{'sub': u', 'u, 'ii) bringing of at least a first region Dof the electrically conductive layer into contact with a composition Z1 for reduction of the electrical conductivity of this first region D,'} 'the electrically conductive layer has a temperature in a range of from more than 40 to 100° C. during the bringing into contact.', 'wherein'}2. The process according to claim 1 , wherein the composition Z1 is released by means of a release area.3. The process according to claim 2 , wherein the release area has a pattern.4. The process according to claim 2 , wherein the release area comprises an absorbent material.5. The process according to claim 2 , wherein the release area is constructed from a material chosen from the group consisting of a porous body claim 2 , a gel and a fibre material or a combination of at least two of these.6. The process according to claim 5 , wherein the porous body is at least in part formed from a paper claim 5 , a nonwoven claim 5 , a sponge and a porous ceramic or a combination of at least two of these.7. The process according to claim 1 , wherein the release area is a recess or ...

STRETCHABLE MEMBER WITH METAL FOIL

Disclosed is a stretchable member with a metal foil including a stretchable resin base material, and a conductive metal foil provided on the stretchable resin base material. A surface of the metal foil on the stretchable resin base material side is a roughened surface having surface roughness Ra of 0.1 μm to 3 μm. 1. A stretchable member with a metal foil , comprising:a stretchable resin base material; anda conductive metal foil provided on the stretchable resin base material,wherein a surface of the metal foil on the stretchable resin base material side is a roughened surface having surface roughness Ra of 0.1 μm to 3 μm.2. The stretchable member with a metal foil according to claim 1 ,wherein a recovery rate after the stretchable resin base material is subjected to tensile deformation up to strain of 20% is greater than or equal to 80%.3. The stretchable member with a metal foil according to claim 1 ,wherein the metal foil is a copper foil.4. The stretchable member with a metal foil according to claim 1 ,wherein the stretchable resin base material contains (A) a rubber component, andthe rubber component includes at least one kind selected from the group consisting of acrylic rubber, isoprene rubber, butyl rubber, styrene butadiene rubber, butadiene rubber, acrylonitrile butadiene rubber, silicone rubber, urethane rubber, chloroprene rubber, ethylene propylene rubber, fluorine rubber, sulfurized rubber, epichlorohydrin rubber, and chlorinated butyl rubber.5. The stretchable member with a metal foil according to claim 4 ,wherein a content of the rubber component is 30 mass % to 100 mass % with respect to a mass of the stretchable resin base material.6. The stretchable member with a metal foil according to claim 4 ,wherein the stretchable resin base material further contains a cross-linking polymer of (B) a cross-linking component.7. The stretchable member with a metal foil according to claim 6 ,wherein the cross-linking component is a compound having a reactive ...

HEAT DISSIPATION PRINTED CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF

A heat dissipation printed circuit board includes a metal core, lower and upper insulating layers, first lower and first upper circuit patterns, and second lower and second upper circuit patterns. The lower and upper insulating layers are disposed at a lower side and an upper side of the metal core, respectively. The first lower and first upper circuit patterns are disposed at a lower side of the lower insulating layer and at an upper side of the upper insulating layer, respectively. The second lower and second upper circuit patterns are disposed at a lower side of the first lower circuit pattern and at an upper side of the first upper circuit pattern, respectively. An etching portion in the first lower circuit pattern is filled with the lower insulating layer and an etching portion in the first upper circuit pattern is filled with the upper insulating layer. 1. A heat dissipation printed circuit board , comprising:a metal core;a lower insulating layer disposed at a lower side of the metal core and an upper insulating layer disposed at an upper side of the metal core;a first lower circuit pattern disposed at a lower side of the lower insulating layer and a first upper circuit pattern disposed at an upper side of the upper insulating layer; anda second lower circuit pattern disposed at a lower side of the first lower circuit pattern and a second upper circuit pattern disposed at an upper side of the first upper circuit pattern,wherein an etching portion in the first lower circuit pattern is filled with the lower insulating layer and an etching portion in the first upper circuit pattern is filled with the upper insulating layer.2. The heat dissipation printed circuit board of claim 1 , wherein:the second lower circuit pattern and the first lower circuit pattern have the same pattern as each other, andthe second upper circuit pattern and the first upper circuit pattern have the same pattern as each other.3. The heat dissipation printed circuit board of claim 1 , ...

METHODS OF FORMING SEGMENTED VIAS FOR PRINTED CIRCUIT BOARDS

Novel methods for forming a printed circuit board (PCB) having one or more segmented vias are provided, including improved methods of removing the catalyst after the plating process when forming a segmented via in the PCB. After the electroless plating, excess catalyst on the surface of the plating resist is removed using a catalyst remover, such as an acidic solution that includes at least nitrite or nitrite ion and halogen ion, or the catalyst remover may be an etchant for plating resist, such as alkaline permanganate compound solution or plasma gas comprising at least one of oxygen, nitrogen, argon and tetrafluoromethane, or a mixture of at least two of these gasses. After removal of the excess catalyst, electrolytic plating is then applied to the through holes and the outer layer circuit or signal traces are formed. That is, the etching of paths on the conductive foils/layers of the core structure. 1. A method for making a printed circuit board having a segmented plated through hole , comprising:forming a core or sub-composite structure;selectively depositing at least one plating resist on a dielectric layer within the core or sub-composite structure or external to the core or sub-composite structure;forming one or more through holes through the core or sub-composite structure and the plating resist; andapplying a catalyzing material to an interior surface of the one or more through holes, the interior surface having a laminate portion and a plating resist portion where only the laminate portion is coated with a conductive material;applying electroless plating to the one or more through holes;removing the catalyzing material from the plating resist portion using a catalyst remover;applying electrolytic plating to the one or more through holes; andforming an outer layer circuit on the external conductive layers.2. The method of claim 1 , wherein the catalyzing material is palladium or a palladium derivative.3. The method of claim 1 , wherein the catalyst remover ...

Microcircuit forming method and etching fluid composition

The disclosure relates to a microcircuit forming method. The microcircuit forming method according to the disclosure comprises: a seed-layer forming step for forming a high-reflectivity seed layer on a substrate material by using a conductive material; a pattern-layer forming step for forming a pattern layer on the seed layer, the pattern layer having a pattern hole arranged thereon to allow the seed layer to be selectively exposed therethrough; a plating step for filling the pattern hole with a conductive material; a pattern-layer removing step for removing the pattern layer; and a seed-layer patterning step for removing a part of the seed layer which does not overlap the conductive material in the plating step, wherein the high-reflectivity seed layer has a specular reflection property.

ELECTRONIC DEVICE, THIN FILM TRANSISTOR, ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF

Disclosed are an electronic device and the manufacturing method thereof, a manufacturing method of a thin film transistor, and an array substrate and manufacturing method thereof. The manufacturing method of an electronic device includes: forming a metallic structure on a base substrate; forming an oxygen-free insulating layer on the metallic structure and the base substrate; and forming an insulating protective layer on the oxygen-free insulating layer. The manufacturing method of the electronic device protects a metallic structure by forming an oxygen-free insulating layer, not containing oxygen elements, on the metallic structure, and hence prevents the metallic structure from being oxidized. 1. A manufacturing method of an electronic device , comprising:forming a metallic structure on a base substrate;forming an oxygen-free insulating layer on the metallic structure and the base substrate; andforming an insulating protective layer on the oxygen-free insulating layer.2. The manufacturing method of the electronic device according to claim 1 , wherein the oxygen-free insulating layer is made from silane; and the manufacturing method of the electronic device further comprises:forming a semiconductor layer below the metallic structure; andchanging a part of the semiconductor layer making contact with the oxygen-free insulating layer into conductor by hydrogen released from the silane in the process of forming the oxygen-free insulating layer.3. The manufacturing method of the electronic device according to claim 1 , further comprising:forming a conductive structure on the insulating protective layer, wherein the conductive structure and the metallic structure have an overlapped part; and the dielectric constant of the oxygen-free insulating layer is less than or equal to 6.4. The manufacturing method of the electronic device according to claim 1 , further comprising:forming through holes in the oxygen-free insulating layer and the insulating protective layer, wherein ...

Method of Manufacturing Substrate for Chip Packages and Method of Manufacturing Chip Package

Provided are a method of manufacturing a substrate for chip packages and a method of manufacturing a chip package, the method of manufacturing the substrate including: forming a lower adhesive layer in a lower part of an insulation film; forming an upper adhesive layer in an upper part of the insulation film to form a base material; forming via holes in the base material; and forming a circuit pattern layer on the upper adhesive layer, so it is effective to improve adhesion power between the molding resin and the insulation film at the time of manufacturing a chip package later. 1. A method of manufacturing a substrate for chip packages , comprising:forming a lower adhesive layer for implementing surface roughness in a lower part of an insulation film;forming an upper adhesive layer in an upper part of the insulation film to form a base material;forming via holes in the base material; andforming a circuit pattern layer on the upper adhesive layer.2. The method of claim 1 , wherein the forming of the lower adhesive layer includes: forming a prepreg in the lower part of the insulation film; and implementing surface roughness on a surface of the prepreg.3. The method of claim 2 , wherein the implementing of the surface roughness is performed by transferring the surface roughness to the prepreg by laminating a copper layer having surface roughness on a lower part of the prepreg.4. The method of claim 3 , comprising removing the copper foil layer after transferring the surface roughness to the prepreg.5. The method of claim 3 , wherein an Rz value of the surface roughness is formed in a range of 3 to 10 μm.6. The method of claim 1 , wherein the insulation film is formed of polyimide claim 1 , polyethylene naphthalate claim 1 , or polyethyleneterephthalate.7. The method of claim 1 , wherein the adhesive layer is composed of an adhesive or a bonding sheet.8. The method of claim 1 , wherein the forming of the via holes is performed by a punching process or a laser drill ...

Component Carrier With Different Surface Finishes and Method for Manufacturing the Same

A component carrier and a method for manufacturing the same are disclosed. The component carrier includes an electrically conductive layer structure and an overhanging end. A first surface finish is formed on a first surface portion of the electrically conductive layer structure. Furthermore, the component carrier further includes a second surface finish on a second surface portion of the electrically conductive layer structure connected to the first surface finish and extending under the overhanging end. 1. A component carrier , comprising:an electrically conductive layer structure;a first surface finish formed on a first surface portion of the electrically conductive layer structure and having an overhanging end; anda second surface finish on a second surface portion of the electrically conductive layer structure connecting to the first surface finish and extending under the overhanging end.2. The component carrier according to wherein the second surface finish connects to a roughened surface of the first surface finish.3. The component carrier according to claim 1 , wherein the first surface finish comprises:a first layer structure arranged above the electrically conductive layer structure; anda second layer structure arranged above the first layer structure.4. The component carrier according to claim 3 , wherein the first layer structure and/or the second layer structure comprise at least one from the group consisting of nickel claim 3 , palladium claim 3 , platinum claim 3 , gold claim 3 , copper.5. The component carrier according to claim 4 , wherein a chemical composition of the first layer structure and a chemical composition of the second layer structure differ from each other.6. The component carrier according to claim 4 , wherein the first layer structure comprises nickel and the second layer structure comprises palladium.7. The component carrier according to claim 1 , wherein the second surface finish comprises at least one from the group consisting of ...

MINIATURIZED CIRCUIT AND METHOD OF MAKING THE SAME

A method for making a miniaturized circuit includes: depositing a bottom metal layer including a first metal on a substrate; forming a patterned photoresist layer on the bottom metal layer to expose a first portion of the bottom metal layer and to cover a second portion thereof; plating a middle circuit pattern including a second metal on the bottom metal layer to cover the first portion of the bottom metal layer; plating a top circuit pattern including a third metal different from the first metal onto the middle circuit pattern to cover the middle circuit pattern; removing the patterned photoresist layer; and etching the second portion of the bottom metal layer with an etchant, so as to pattern the bottom metal layer into a bottom circuit pattern. 1. A method for making a miniaturized circuit , comprising the steps of:depositing a bottom metal layer on a surface of a substrate, the bottom metal layer including a first metal;forming a patterned photoresist layer on the bottom metal layer such that a first portion of the bottom metal layer is exposed from the patterned photoresist layer and a second portion of the bottom metal layer is covered by the patterned photoresist layer;plating a middle circuit pattern on the bottom metal layer so that the first portion of the bottom metal layer is covered by the middle circuit pattern, the middle circuit pattern including a second metal;plating a top circuit pattern onto the middle circuit pattern so as to cover a portion of the middle circuit pattern that is not in contact with the bottom metal layer and the patterned photoresist layer, the top circuit pattern including a third metal different from the first metal;removing the patterned photoresist layer to expose the second portion of the bottom metal layer; andetching the second portion of the bottom metal layer with an etchant, so as to pattern the bottom metal layer into a bottom circuit pattern, the bottom circuit pattern being disposed underneath the middle circuit ...

Conductive Transparent Substrate Manufacturing Method, and Conductive Transparent Substrate

Provided herein is a method for manufacturing a conductive transparent substrate, the method including forming a plurality of main electrodes on the substrate such that the main electrodes are distanced from one another; and forming a connecting electrode that electrically connects two or more main electrodes such that the plurality of main electrodes are grouped into a plurality of group electrodes that are electrically disconnected from one another, thereby producing a conductive transparent substrate with excellent transmittance in a process of high yield. 1. A method for manufacturing a conductive transparent substrate ,comprising:a main electrode step of manufacturing a plurality of main electrodes arranged on a substrate in such a manner that the plurality of main electrodes are spaced apart from each other; anda connection electrode step of manufacturing a connection electrode electrically connecting at least two main electrodes in such a manner that the plurality of main electrodes are grouped as a plurality of group electrodes and the plurality of group electrodes are electrically isolated from each other.219-. (canceled)20. The method according to claim 1 ,wherein at the forming of a connecting electrode, a connecting electrode pattern is printed, or a connecting electrode layer is formed and then a portion of the connecting electrode layer is removed or insulated thereby forming a connecting electrode, such that the main electrodes that are distanced and electrically disconnected from one another are electrically connected but that two or more of the main electrodes are grouped and the grouped main electrodes are disconnected from one another.21. The method according to claim 1 ,wherein the forming of a connecting electrode comprises:depositing a conductive layer having electrical conductivity on the substrate; andpatterning the conductive layer such that the connecting electrode is formed.22. The method according to claim 1 ,wherein the forming of a ...

METHOD FOR PRODUCING CERAMIC CIRCUIT BOARD

A method for producing a ceramic circuit board comprising the steps of bonding a metal sheet to a ceramic substrate via a brazing material containing Ag to form a bonded body; etching the bonded metal sheet to form a circuit pattern; and removing an unnecessary brazing material from the substrate provided with the circuit pattern, by etching with an acidic solution comprising carboxylic acid and/or carboxylate and hydrogen peroxide. 113-. (canceled)14. A method for producing a ceramic circuit board comprising the steps ofbonding a metal sheet to a ceramic substrate via a brazing material containing Ag to form a bonded body;etching said bonded metal sheet to form a circuit pattern; andremoving an unnecessary brazing material from said substrate provided with the circuit pattern, by etching with a first acidic solution comprising (i) at least one of carboxylic acid and carboxylate and (ii) hydrogen peroxide; andremoving a residual brazing material from said substrate having an unnecessary brazing material removed, by etching with a second acidic solution comprising ammonium fluoride and hydrogen peroxide.15. The method for producing a ceramic circuit board according to claim 14 , wherein said first acidic solution is an aqueous solution comprising (i) 0.083-1.7 mol/L of at least one of carboxylic acid and carboxylate claim 14 , and (ii) 2.9-8.9 mol/L of hydrogen peroxide claim 14 , and having pH of 6 or less.16. The method for producing a ceramic circuit board according to claim 14 , wherein said first acidic solution further comprises at least one of sulfuric acid claim 14 , urea claim 14 , and phosphoric acid.17. The method for producing a ceramic circuit board according to claim 14 , wherein said second acidic solution is an aqueous solution comprising 0.7-2.1 mol/L of ammonium fluoride claim 14 , and 2.9-8.9 mol/L of hydrogen peroxide claim 14 , and having pH of 5 or less.18. The method for producing a ceramic circuit board according to claim 14 , wherein said ...

CORE SUBSTRATE AND METHOD FOR FABRICATING CIRCUIT BOARD

A core substrate includes a dielectric layer, at least one releasing layer, at least one first copper foil layer and at least one nickel layer. The releasing layer is disposed on the dielectric layer and directly covers the dielectric layer. The first copper foil layer is disposed on the releasing layer and directly covers the releasing layer. The nickel layer is disposed on the first copper foil layer and directly covers the first copper foil layer. 1. A core substrate comprising:a dielectric layer;at least one releasing layer disposed on the dielectric layer and directly covering the dielectric layer;at least one first copper foil layer disposed on the releasing layer and directly covering the releasing layer; andat least one nickel layer disposed on the first copper foil layer and directly covering the first copper foil layer.2. The core substrate as claimed in claim 1 , wherein a thickness of the first copper foil layer ranges from 12 μm to 35 μm.3. The core substrate as claimed in claim 1 , further comprising:a second copper foil layer disposed on the nickel layer and directly covering the nickel layer.4. The core substrate as claimed in claim 3 , wherein a thickness of the second copper foil layer ranges from 5 μm to 70 μm.5. A method for fabricating a circuit board claim 3 , comprising: a dielectric layer;', 'at least one releasing layer disposed on the dielectric layer and directly covering the dielectric layer;', 'at least one first copper foil layer disposed on the releasing layer and directly covering the releasing layer; and', 'at least one nickel layer disposed on the first copper foil layer and directly covering the first copper foil layer;, 'providing a core substrate, the core substrate comprisingforming at least one patterned circuit layer on the nickel layer, wherein the patterned circuit layer exposes a portion of the nickel layer;forming at least one insulating layer on the patterned circuit layer, wherein the insulating layer covers the ...

METHOD OF FABRICATING TOUCH SCREEN PANEL

A method of manufacturing a touch screen panel, including forming first and second conductive layers and an organic insulating layer on a substrate; forming a first organic insulating pattern having a first thickness and a second organic insulating pattern having a second thickness, the second thickness being larger than the first thickness; forming first and second conductive patterns; exposing a part of the second conductive pattern to form a third organic insulating pattern having a thickness smaller than the second thickness; removing the exposed second conductive pattern; forming an organic insulating capping layer surrounding the first and second conductive patterns positioned under the third organic insulating pattern; and forming a third conductive layer on the first conductive pattern and the organic insulating capping layer, the first conductive pattern being exposed, and then forming a connection pattern electrically connected with the exposed first conductive pattern using a second mask. 1. A method of manufacturing a touch screen panel , comprising:forming a first conductive layer, a second conductive layer, and an organic insulating layer on a substrate;forming a first organic insulating pattern having a first thickness and a second organic insulating pattern having a second thickness by disposing a first mask on the organic insulating layer, the second thickness being larger than the first thickness;forming first and second conductive patterns by etching the first and second conductive layers at exposed portions using the first and second organic insulating patterns as masks;exposing a part of the second conductive pattern by ashing the first organic insulating pattern and ashing the second organic insulating pattern to form a third organic insulating pattern having a thickness smaller than the second thickness;removing the exposed part of the second conductive pattern by etching and exposing the first conductive pattern positioned under the second ...

METHODS OF ETCHING CONDUCTIVE FEATURES, AND RELATED DEVICES AND SYSTEMS

A method of making a device patterned with one or more electrically conductive features includes depositing a conductive material layer over an electrically insulating surface of a substrate, depositing an anti-corrosive material layer over the conductive material layer, and depositing an etch-resist material layer over the anti-corrosive material layer. The etch-resist material layer may be deposited over the anti-corrosive material layer, and the anti-corrosive material layer forming a bi-component etch mask in a pattern resulting in covered portions of the conductive material layer and exposed portions of the conductive material layer, the covered portions being positioned at locations corresponding to one or more conductive features of the device. A wet-etch process is performed to remove the exposed portions of the conductive material layer from the electrically insulating substrate, and the bi-component etch mask is removed to expose the remaining conductive material. Systems and devices relate to devices with patterned features. 1. A method of making a device patterned with one or more electrically conductive features , the method comprising:depositing a conductive material layer over an electrically insulating surface of a substrate;depositing an anti-corrosive material layer over the conductive material layer;depositing an etch-resist material layer over the anti-corrosive material layer, the etch-resist material layer and the anti-corrosive material layer forming a bi-component etch mask in a pattern resulting in covered portions of the conductive material layer and exposed portions of the conductive material layer, the covered portions being positioned at locations corresponding to one or more conductive features of the device;performing a wet-etch process to remove the exposed portions of the conductive material layer from the electrically insulating substrate; andremoving the bi-component etch mask to expose the remaining conductive material of the ...

PRINTED WIRING BOARD AND METHOD FOR MANUFACTURING PRINTED WIRING BOARD

A printed wiring board includes a resin insulating layer, a projecting conductor layer formed on a surface of the resin insulating layer such that the projecting conductor layer is projecting from the surface of the resin insulating layer, and an integral conductor structure formed in the resin insulating layer and including a via conductor portion and an embedded conductor layer portion such that the embedded conductor layer portion is embedded in the resin insulating layer on the opposite side of the resin insulating layer with respect to the projecting conductor layer and has an exposed surface exposed from the resin insulating layer and the via conductor portion is formed through the resin insulating layer and is connecting the embedded conductor layer portion and projecting conductor layer. The projecting conductor layer and integral conductor structure are formed such that the projecting conductor layer and integral conductor structure are individual conductor structures. 1. A printed wiring board , comprising:a resin insulating layer;a projecting conductor layer formed on a surface of the resin insulating layer such that the projecting conductor layer is projecting from the surface of the resin insulating layer; andan integral conductor structure formed in the resin insulating layer and comprising a via conductor portion and an embedded conductor layer portion such that the embedded conductor layer portion is embedded in the resin insulating layer on an opposite side of the resin insulating layer with respect to the projecting conductor layer and has an exposed surface exposed from the resin insulating layer and that the via conductor portion is formed through the resin insulating layer and is connecting the embedded conductor layer portion and the projecting conductor layer,wherein the projecting conductor layer and the integral conductor structure are formed such that the projecting conductor layer and the integral conductor structure are individual ...

Method Of Manufacturing A Patterned Transparent Conductor

Method of manufacturing patterned conductor is provided, comprising: providing a conductivised substrate, wherein the conductivised substrate comprises a substrate and an electrically conductive layer; providing an electrically conductive layer etchant; providing a spinning material; providing a masking fiber solvent; forming a plurality of masking fibers and depositing the plurality of masking fibers onto the electrically conductive layer; exposing the electrically conductive layer to the electrically conductive layer etchant, wherein the electrically conductive layer that is uncovered by the plurality of masking fibers is removed from the substrate, leaving an interconnected conductive network on the substrate covered by the plurality of masking fibers; and, exposing the plurality of masking fibers to the masking fiber solvent, wherein the plurality of masking fibers are removed to uncover the interconnected conductive network on the substrate. 1. A method of manufacturing a patterned conductor , comprising:providing a conductivised substrate, wherein the conductivised substrate comprises a substrate and an electrically conductive layer;providing an electrically conductive layer etchant;providing a spinning material;providing a masking fiber solvent;forming a plurality of masking fibers and depositing the plurality of masking fibers onto the electrically conductive layer;optionally, compressing the plurality of masking fibers on the electrically conductive layer;exposing the electrically conductive layer to the electrically conductive layer etchant, wherein the electrically conductive layer that is uncovered by the plurality of masking fibers is removed from the substrate, leaving an interconnected conductive network on the substrate covered by the plurality of masking fibers; and,exposing the plurality of masking fibers to the masking fiber solvent, wherein the plurality of masking fibers are removed to uncover the interconnected conductive network on the ...

STRUCTURE OF VIA HOLE OF ELECTRICAL CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF

A structure of via hole of electrical circuit board includes an adhesive layer and a conductor layer that are formed after wiring is formed on a carrier board. At least one through hole extends in a vertical direction through the carrier board, the wiring, the adhesive layer, and the conductor layer and forms a hole wall surface. The conductor layer shows a height difference with respect to an exposed zone of the circuit trace in the vertical direction. A conductive cover section covers the conductor layer and the hole wall surface of the through hole. The carrier board is a single-sided board, a double-sided board, a multi-layered board, or a combination thereof, and the single-sided board, the double-sided board, and multi-layered board can be flexible boards, rigid boards, or composite boards combining flexible and rigid boards. 1. An electrical circuit board , comprising:a carrier board, which is a flexible circuit board, the carrier board comprising a first substrate, which has a substrate upper surface and a substrate lower surface, the substrate upper surface comprising at least one upper circuit trace;an upper adhesive layer, which is formed on at least a partial area of the upper circuit trace, a portion of the upper circuit trace that is not covered by the upper adhesive layer forming an upper circuit trace exposed zone, the upper adhesive layer comprising an upper adhesive layer opening zone corresponding to the upper circuit trace exposed zone;an etching resisting layer, which is filled in the upper adhesive layer opening zone;an upper conductor layer, which is formed on the upper adhesive layer and the etching resisting layer, the upper conductor layer showing a first height difference with respect to the upper circuit trace exposed zone in a vertical direction;a lower adhesive layer, which is formed on at least a partial area of the lower circuit trace, a portion of the lower circuit trace that is not covered by the lower adhesive layer forming a lower ...

CERAMIC CIRCUIT BOARD AND PROCESS FOR PRODUCING SAME

According to one embodiment, a ceramic circuit board includes a ceramic substrate, a copper circuit plate and a brazing material protrudent part. The copper circuit plate is bonded to at least one surface of the ceramic substrate through a brazing material layer including Ag, Cu, and Ti. The brazing material protrudent part includes a Ti phase and a TiN phase by 3% by mass or more in total, which is different from the total amount of a Ti phase and a TiN phase in the brazing material layer that is interposed between the ceramic substrate and the copper circuit plate. The number of voids each having an area of 200 μmor less in the brazing material protrudent part is one or less (including zero). 1. A method for the production of a ceramic circuit board , comprising:providing a first masking on a part other than an area to be a copper circuit pattern and a brazing material protrudent part on a ceramic substrate;forming a brazing material layer comprising Ag, Cu and Ti on an area other than the first masking on the ceramic substrate;mounting a copper plate on the brazing material layer and bonding the ceramic substrate and the copper plate by heating;providing a second masking on an area to be a copper circuit pattern on the copper plate; andforming a copper circuit pattern by etching.2. The method for the production of a ceramic circuit board according to claim 1 ,wherein an etchant of ferric chloride or cupric chloride is used in the etching.3. The method for the production of a ceramic circuit board according to claim 1 ,wherein markings for position alignment are provided to the ceramic substrate and the copper plate.4. The method for the production of a ceramic circuit board according to claim 1 ,wherein a material for the first masking and second masking is a printable organic ink resist. This is a divisional patent application of U.S. application Ser. No. 13/418,813 filed Mar. 13, 2012, which is a Continuation Application of PCT Application No. PCT/JP2010/065914 ...

CARRYING DEVICE, WET ETCHING APPARATUS AND USAGE METHOD THEREOF

The present invention discloses a carrying device, a wet etching apparatus and a usage method thereof. The carrying device comprises a carrying body and a heating unit both disposed under a to-be-processed substrate, the carrying body is used for carrying the to-be-processed substrate such that the to-be-processed substrate is placed inclined; the heating unit is used for heating the to-be-processed substrate, such that temperature of the to-be-processed substrate rises gradually from a top portion to a bottom portion thereof. In the technical solution of the present invention, by disposing the heating unit under the to-be-processed substrate, the temperature of the to-be-processed substrate rises gradually from the top portion to the bottom portion thereof, thus etch rate of the etchant on the bottom portion of the to-be-processed substrate can be increased, and uniformity of etch rate in the inclined wet etching process is improved. 110-. (canceled)11. A carrying device , used for carrying a to-be-processed substrate in a wet etching process , the carrying device comprising:a carrying body, disposed under the to-be-processed substrate and used for carrying the to-be-processed substrate such that the to-be-processed substrate is placed inclined;a heating unit, disposed under the to-be-processed substrate and used for heating the to-be-processed substrate, such that temperature of the to-be-processed substrate rises gradually along an inclined direction from a top portion to a bottom portion thereof.12. The carrying device of claim 11 , wherein the heating unit includes a plurality of thermal light sources claim 11 , and light generated by the thermal light sources is emitted to a back face of the to-be-processed substrate.13. The carrying device of claim 12 , wherein distances of the thermal light sources to the to-be-processed substrate are equal claim 12 , the thermal light sources have equal output powers claim 12 , the top portion of the to-be-processed ...

PRINTED WIRING BOARD AND METHOD FOR MANUFACTURING PRINTED WIRING BOARD

A printed wiring board includes a conductor layer including a conductor circuit, a resin insulating layer formed on the conductor layer and having a via opening reaching to the conductor circuit of the conductor layer, and a via conductor formed in the via opening of the resin insulating layer such that the via conductor is connecting to the conductor circuit of the conductor layer. The conductor circuit of the conductor layer has a first conductor portion and a second conductor portion integrally formed such that the first conductor portion is connected to the via opening of the resin insulating layer, that the second conductor portion is surrounding the first conductor portion and that the first conductor portion has a thickness which is greater than a thickness of the second conductor portion. 1. A printed wiring board , comprising:a conductor layer including a conductor circuit;a resin insulating layer formed on the conductor layer and having a via opening reaching to the conductor circuit of the conductor layer; anda via conductor formed in the via opening of the resin insulating layer such that the via conductor is connecting to the conductor circuit of the conductor layer,wherein the conductor circuit of the conductor layer comprises a first conductor portion and a second conductor portion integrally formed such that the first conductor portion is connected to the via opening of the resin insulating layer, that the second conductor portion is surrounding the first conductor portion and that the first conductor portion has a thickness which is greater than a thickness of the second conductor portion.2. A printed wiring board according to claim 1 , further comprising:a first conductor layer;a first resin insulating layer formed on the first conductor layer such that the conductor layer is a second conductor layer formed on the first resin insulating layer and that the resin insulating layer is a second resin insulating layer; anda first via conductor formed ...

COMPOSITION OF AN AQUEOUS ETCHANT CONTAINING A PRECURSOR OF OXIDANT AND PATTERNING METHOD FOR CONDUCTIVE CIRCUIT

The present invention is primarily related to the composition of an aqueous etchant containing a precursor of oxidant and patterning methods for conductive circuits, in which the chemical structure of the precursor contains chlorine and can produce oxidants through various reactions. And, the patterned conductive circuits can be used for electronic devices, including printed electronics, sensors, displays, organic light emitting diodes (OLED), touch panels, electronic circuit boards, electrodes, electroluminescent (EL) films, antennas, and solar cells. 1. A aqueous etchant contains a precursor of oxidant for patterning conductive circuit , wherein the chemical structure of the precursor contains chlorine , and the precursor produces at least one of the following oxidants: Cl , ClO , HClO , ClO , ClO , ClO , HClOand HClO.2. A manufacturing method using an aqueous etchant containing a precursor of oxidant for patterning conductive circuit on a conductive layer , comprising steps of:a) covering the surface of a substrate with conjugated transparent conductive polymer;{'sup': −', '−', '−, 'sub': 2', '2', '2', '2', '3', '3', '4, 'b) covering the areas of the conductive layer predetermined for oxidation treatment on the conductive substrate with an aqueous etchant containing a precursor of oxidant, wherein the chemical structure of the precursor contains chlorine, and the precursor produces at least one of the following oxidants: Cl, ClO, HClO, ClO, ClO, ClO, HClOand HClO; and'}c) using one or more than one of the following methods: drying, heating, radiation, to cause the precursor to produce the a oxidant, whereby etching is carried out on areas of the conductive layer predetermined not require conductivity to form non-conductive areas, and the rest of the conductive layer excluding the non-conductive areas thereby forming the conductive circuit; wherein electrical resistivity of the non-conductive areas is 100 times greater than the electrical resistivity of the ...

CIRCUIT BOARD AND METHOD FOR PRODUCTION THEREOF

A circuit board (″) includes at last one insulating substrate layer (SL, SL, SL, SL, SL) and a plurality of electrically conductive copper coats (C, C, C) arranged on the at least one insulating substrate layer (SL, SL, SL, SL, SL), wherein at least one of the electrically conductive copper coats (C, C, C) is coated at least on both sides with a layer (HSI, HS, HS) made of a material for inhibiting electromigration, wherein on a layer (HS, HS) made of a material for inhibiting electromigration a further metal layer (M, M, M, M′) is provided, which is in turn coated with a further layer (HS, HS′) made of a material for inhibiting electromigration. 1. A circuit board , comprising:at least one insulating substrate layer and a multiplicity of electrically conductive copper layers arranged on the at least one insulating substrate layer; andat least one of the electrically conductive copper layers is coated at least on both sides with a layer of a material for inhibiting electromigration, a further metal layer being provided on a layer of a material for inhibiting electromigration, which further metal layer is in turn coated with a further layer of a material for inhibiting electromigration.2. The circuit board as claimed in claim 1 , wherein at least one bore is provided claim 1 , which connects at least two copper layers and on the inner wall of which a layer of a material for inhibiting electromigration is applied.3. The circuit board as claimed in claim 2 , wherein the bore is a through-contact claim 2 , a buried bore or a blind hole.4. The circuit board as claimed in claim 1 , wherein the material for inhibiting electromigration is zinc claim 1 , brass claim 1 , a layer sequence comprising nickel or a nickel compound.5. The circuit board as claimed in claim 1 , which has a solder resist covering claim 1 , a layer of a material for inhibiting electromigration being provided between an uppermost copper layer and the solder resist covering.6. The circuit board as ...

METHOD FOR FORMING CIRCUITS USING SEED LAYER AND ETCHANT COMPOSITION FOR SELECTIVE ETCHING OF SEED LAYER

The present invention relates to a method for forming a circuit using a seed layer. The method for forming a circuit using a seed layer according to the present invention, may realize a fine pitch, increase the adhesion of the circuit, and prevent the migration phenomenon. 1. A method of forming a circuit using a seed layer , comprising:preparing a seed layer of a first conductive material;forming a pattern layer with a pattern groove, through which the seed layer is selectively exposed, on the seed layer;plating the pattern groove by filling a second conductive material into the pattern groove using a plating process;forming a resin layer on the pattern layer; andremoving the seed layer,the first conductive material and the second conductive material being in different in material from each other.2. The method according to claim 1 , wherein the removing the seed layer comprises using an etching solution capable of selectively removing the seed layer to remove the seed layer.3. The method according to claim 2 , wherein the first conductive material comprises silver (Ag) claim 2 , and the second conductive material comprises copper (Cu).4. The method according to claim 2 , whereinthe seed layer is provided on a release film,the forming the pattern layer comprises forming a pattern groove by applying a lithography process to the pattern layer provided as a photosensitive film,the method further comprises removing the pattern layer between the plating and the forming the resin layer, andthe removing the seed layer comprises separating the release film as the seed layer is removed.5. The method according to claim 2 , whereinthe seed layer is provided on a release film,the forming the pattern layer comprises forming a pattern groove in the pattern layer provided as a photosensitive film, andthe removing the seed layer comprises separating the release film as the seed layer is removed.6. A method of forming a circuit using a seed layer claim 2 , comprising:forming a seed ...

ETCHING METHOD AND ETCHING LIQUID USED THEREIN

An etching method having the step of: applying an etching liquid to a substrate, the etching liquid containing: a fluorine ion, a nitrogen-containing compound having at least 2 of nitrogen-containing structural units, and water, the etching liquid having a pH of being adjusted to 5 or less; and etching a titanium compound in the substrate. 1. An etching method comprising the steps of:applying an etching liquid to a substrate, the etching liquid comprising: a fluorine ion, a nitrogen-containing compound having two or more nitrogen-containing structural units, and water, the etching liquid having a pH of being adjusted to 5 or less; andetching a titanium compound in the substrate.2. The etching method according to claim 1 , wherein the nitrogen-containing compound has a molecular weight from 300 to 20 claim 1 ,000.4. The etching method according to claim 1 , wherein the nitrogen-containing compound is a compound represented by the following formula (b):{'br': None, 'sup': c', 'd', 'c', 'd', 'c, 'sub': 2', 'm', '2, 'RN-[L-N(R)]-L-NR\u2003\u2003(b)'}{'sup': d', 'c', 'c', 'd', 'c, 'wherein Lrepresents an alkylene group, a carbonyl group, an amino group, an arylene group, a heteroarylene group, or a combination thereof; Rrepresents a hydrogen atom, or an alkyl group; m represents an integer of 1 or more; respective Rs and Ls may be the same as or different from each other; and respective Rs may bind to each other to form a ring.'}5. The etching method according to claim 1 , wherein the nitrogen-containing compound is a polyethyleneimine claim 1 , a polyallylamine claim 1 , a polyvinylamine claim 1 , a polydiallylamine claim 1 , a polymethyldiallylamine claim 1 , or a polydimethyldiallylammonium salt.6. The etching method according to claim 1 , wherein a conjugate acid of the nitrogen-containing compound has a pKa of 5 or more.7. The etching method according to claim 1 , wherein a ground substance that acts as a supply source of the fluorine ion is one selected from the ...

Anisotropic Etching Using Highly Branched Polymers

An etching composition for etching an electrically conductive layer structure for forming a conductor track is provided. The etching composition includes an etchant, a highly branched compound and optionally a solvent. In addition, a method of etching an electrically conductive layer structure, a conductor track, an arrangement of at least two conductor tracks, and a component carrier are provided. 1. An etching composition for etching an electrically conductive layer structure for forming a conductor track , the etching composition comprising:an etchant;a highly branched compound; andoptionally a solvent.2. The etching composition according to claim 1 , wherein the etchant comprises at least one of cupric chloride (CuCl) and ferric chloride (FeCl).3. The etching composition according to claim 1 , wherein the highly branched compound is selected from the group consisting of hyperbranched polymers claim 1 , dendrons claim 1 , dendrimers and multifunctional polyethylene glycols.4. The etching composition according to claim 1 , wherein the highly branched compound comprises at least one of an amine functional group and/or a thiol functional group.5. The etching composition according to claim 1 , wherein the highly branched compound is permeable for the etchant.6. The etching composition according to claim 1 , further comprising:an etching inhibitor having a larger sizer than a size of the etchant and/or a larger size than a space between neighboring branches of the highly branched compound.7. The etching composition according to claim 1 , further comprising:a wetting additive.8. The etching composition according to claim 1 , further comprising:a rheological additive.9. The etching composition according to claim 8 , wherein the rheological additive is selected from the group consisting of silica claim 8 , hydroxyethyl cellulose claim 8 , phyllosilicates and urea.10. A method of etching an electrically conductive layer structure of a component carrier for forming a ...

PRINTED CIRCUIT BOARD AND MANUFACTURING METHOD THEREFOR

A printed circuit board according to one embodiment of the present invention comprises an insulation board and a plurality of metal electrodes disposed on the insulation board, wherein: the plurality of metal electrodes include a first electrode and a second electrode; the first electrode includes a first surface parallel to an upper surface of the insulation board, a second surface facing the first surface, a first side surface disposed between the first surface and the second surface, and a second side surface facing the first side surface; a part of the first side surface and a part of the second side surface protrude toward the outside of the first electrode in the direction parallel to the upper surface of the insulation board; the first side surface protrudes farther in an area adjacent to the first surface than in an area adjacent to the second surface; and the second side surface protrudes farther in the area adjacent to the second surface than in the area adjacent to the first surface. 1. A printed circuit board comprising:an insulation board; anda plurality of metal electrodes disposed on the insulation board,wherein the plurality of metal electrodes include a first electrode and a second electrode,the first electrode includes a first surface parallel to an upper surface of the insulation board, a second surface opposite to the first surface, a first side surface disposed between the first surface and the second surface, and a second side surface opposite to the first side surface,a part of the first side surface and a part of the second side surface protrude toward the outside of the first electrode in a direction parallel to the upper surface of the insulation board,the first side surface protrudes further in an area adjacent to the first surface than in an area adjacent to the second surface, andthe second side surface protrudes further in the area adjacent to the second surface than in the area adjacent to the first surface.2. The printed circuit board ...

Printed circuit board and method for manufacturing same

Provided is a printed circuit board which includes: a first dielectric layer including a first principal surface and a second principal surface on a side opposite to the first principal surface; a first adhesive layer formed on the first principal surface; a first metal foil pattern formed on the first adhesive layer and forming a signal line; and a second metal foil pattern formed on the second principal surface and forming a ground layer, in which the first metal foil pattern has a higher specific conductivity than a specific conductivity of the second metal foil pattern.

A RESISTIVE RANDOM-ACCESS MEMORY IN PRINTED CIRCUIT BOARD

Provided in one example is an article. The article including: a first electrode; a switching layer disposed over at least a portion of the first electrode, the switching layer including a metal oxide; and a second electrode disposed over at least a portion of the switching layer. The first electrode, the switching layer, and the second electrode are parts of a resistive random-access memory, and one or both of the first electrode and the second electrode is a part of a layer of a printed circuit board. 1. An article , including:a first electrode;a switching layer disposed over at least a portion of the first electrode, the switching layer including a metal oxide; anda second electrode disposed over at least a portion of the switching layer; the first electrode, the switching layer, and the second electrode are parts of a resistive random-access memory; and', 'one or both of the first electrode and the second electrode is a part of a layer of a printed circuit board., 'wherein'}2. The article of claim 1 , wherein one or both of the first electrode and the second electrode is selected from the group consisting of platinum claim 1 , copper claim 1 , aluminium claim 1 , titanium claim 1 , tantalum claim 1 , cobalt claim 1 , nickel claim 1 , molybdenum claim 1 , tungsten claim 1 , chromium claim 1 , niobium claim 1 , hafnium claim 1 , zirconium claim 1 , ruthenium claim 1 , and iridium claim 1 , or an alloy claim 1 , or a nitride claim 1 , or an oxide thereof.3. The article of claim 1 , further including any of the following:(i) a first electrode interface layer, including one or both of a nitride and an oxide of a metal selected from the group consisting of copper, aluminium, titanium, tantalum, cobalt, zinc, nickel, iron, yttrium, silicon, gallium, molybdenum, tungsten, chromium, niobium, hafnium, zirconium, ruthenium, platinum, iridium, and combinations thereof; and(ii) a second electrode interface layer, including one or both of a nitride and an oxide of a metal ...

Method and Device of Manufacturing Printed Circuit Board

Provided is a method of manufacturing a printed circuit board, the method including: preparing an insulating substrate including a resin material in which a solid component is impregnated; forming a circuit pattern groove on the resin material by etching an upper surface of the insulating substrate; forming a plated layer in which the circuit pattern groove is buried; and forming a buried circuit pattern by removing the plated layer until the insulating layer is exposed, wherein the solid component has a diameter of less than 5% to a width of the buried circuit pattern. Thus, as a filler of a predetermined size or less is applied into the insulating layer for forming the circuit pattern, the occurrence of a void due to separation of the filler from a boundary part with the circuit pattern can be reduced, and reliability can be also secured. 1. A method of manufacturing a printed circuit board , comprising:preparing an insulating substrate including a resin material in which a solid component is impregnated;forming a circuit pattern groove on the resin material by etching an upper surface of the insulating substrate;forming a plated layer in which the circuit pattern groove is buried; andforming a buried circuit pattern by removing the plated layer until the insulating layer is exposed,wherein the solid component has a diameter of less than 5% to a width of the buried circuit pattern.2. The method of claim 1 , wherein the forming of the circuit pattern groove is performed by forming the circuit pattern groove using a laser.3. The method of claim 1 , wherein the removing of the plated layer is performed by removing the plated layer using a slurry at an alkali atmosphere of more less pH 9.4. The method of claim 3 , wherein the alkali atmosphere is formed by mixing the slurry with ammonia and hydrogen peroxide.5. The method of claim 1 , wherein the forming of the buried circuit pattern comprises: plating a surface of the circuit pattern groove with a first metal layer ...

SUBTRACTIVE ETCH RESOLUTION IMPLEMENTING A FUNCTIONAL THIN METAL RESIST

Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a substrate and a conductive feature over the substrate. In an embodiment, a metallic mask is positioned over the conductive feature. In an embodiment, the metallic mask extends beyond a first edge of the conductive feature and a second edge of the conductive feature. 1. An electronic package , comprising:a substrate;a conductive feature over the substrate; anda metallic mask over the conductive feature, wherein the metallic mask extends beyond a first edge of the conductive feature and a second edge of the conductive feature.2. The electronic package of claim 1 , wherein the metallic mask extends beyond the first edge of the conductive feature a first distance claim 1 , and the metallic mask extends beyond the second edge of the conductive feature a second distance claim 1 , wherein the first distance is substantially equal to the second distance.3. The electronic package of claim 2 , wherein the first distance is 1 micron or less.4. The electronic package of claim 1 , wherein sidewall surfaces of the conductive feature are non-vertical.5. The electronic package of claim 4 , wherein the sidewall surfaces provide an hour-glass shaped cross-section to the conductive feature.6. The electronic package of claim 1 , wherein a thickness of the metallic mask is approximately 5 microns or less.7. The electronic package of claim 1 , wherein sidewall surfaces of the metallic mask are non-vertical.8. The electronic package of claim 1 , further comprising:a barrier layer between the conductive feature and the metallic mask.9. The electronic package of claim 8 , wherein sidewalls of the barrier layer are substantially coplanar with sidewalls of the metallic mask.10. The electronic package of claim 8 , wherein the barrier layer comprises one or more of tin claim 8 , gold claim 8 , and a conductive polymer.11. The electronic package of ...

BUILD-UP HIGH-ASPECT RATIO OPENING

Embodiments herein relate to creating a high-aspect ratio opening in a package. Embodiments may include applying a first laminate layer on a side of a substrate, applying a seed layer to at least part of the laminate layer, building up one or more copper pads on the seed layer, etching the seed layer to expose a portion of the first laminate layer, applying a second laminate layer to fill in around the sides of one or more copper pads, and removing part of the buildup copper pads. Other embodiments may be described and/or claimed. 19-. (canceled)10. A method for creating a package , comprising:applying a first laminate layer on a side of a substrate;applying a seed layer to at least part of the first laminate layer;building up one or more copper pads on the seed layer;etching at least a portion of the seed layer to expose a portion of the first laminate layer;applying a second laminate layer to the side of the substrate, the second laminate layer to fill in around sides of at least one of the one or more copper pads and to couple with at least a portion of the exposed first laminate layer; andremoving at least part of the built-up one or more copper pads to create at least one opening in the second laminate layer wherein the at least one opening is a high-aspect ratio opening, wherein the high-aspect ratio opening has an aspect ratio greater than 1:1 for opening depths greater than 20 micrometers (μm).11. The method of claim 10 , wherein the aspect ratio is approximately 2:1 or the aspect ratio is approximately 5:1.12. The method of claim 10 , wherein building up one or more copper pads on the seed layer includes:applying a dry film resist (DFR) layer or a liquid photo resist (LPR) layer to the seed layer;forming one or more copper pads onto the seed layer or onto an existing one or more copper pads, wherein one of the formed one or more copper pads includes an etch stop layer on a surface of the one of the formed one or more copper pads; andremoving the one or more ...

METHOD OF MANUFACTURING PRINTED WIRING BOARD

A printed wiring board includes a copper foil pattern on a base material, a solder resist uniformly provided on the copper foil pattern so as to cover the copper foil pattern, and an outline character forming layer provided in a part where characters are not formed so that outline characters are formed on the solder resist. A method of manufacturing the printed wiring board includes a step of forming the copper foil pattern on the base material, a step of uniformly forming the solder resist on the copper foil pattern so as to cover the copper foil pattern, and a step of forming the outline character forming layer on the solder resist. The solder resist is formed by applying it by a spray method. 1. (canceled)2. (canceled)3. (canceled)4. A method of manufacturing a printed wiring board , comprising:forming a copper foil pattern on a base material;forming a solder resist on the copper foil pattern so as to cover the copper foil pattern;forming an outline character forming layer on the solder resist; andremoving the solder resist on the portion to be soldered, whereinthe solder resist is formed so as not to expose the copper foil pattern.5. The method of manufacturing a printed wiring board claim 4 , according to claim 4 , whereinthe solder resist is formed by using a white ink, and the outline character forming layer is formed by using a green ink.6. The method of manufacturing a printed wiring board claim 4 , according to claim 4 , whereinthe solder resist and the outline character forming layer are formed by using a thermosetting ink,the method further comprising:heating processing for curing the solder resist and the outline character forming layer.7. The method of manufacturing a printed wiring board claim 5 , according to claim 5 , whereinthe solder resist and the outline character forming layer are formed by using a thermosetting ink,the method further comprising:heating processing for curing the solder resist and the outline character forming layer. This ...

BASE MATERIAL FOR PRINTED CIRCUIT BOARD AND PRINTED CIRCUIT BOARD

A base material for a printed circuit board includes: an insulating base film; a sintered layer that is layered on at least one side surface of the base film and that is formed of a plurality of sintered metal particles; an electroless plating layer that is layered on a surface of the sintered layer that is opposite to the base film; and an electroplating layer that is layered on a surface of the electroless plating layer that is opposite to the sintered layer, wherein an arithmetic mean height Sa of the surface of the electroless plating layer opposite to the sintered layer is greater than or equal to 0.001 μm and less than or equal to 0.5 μm. 1. A base material for a printed circuit board comprising:an insulating base film;a sintered layer that is layered on at least one side surface of the base film and that is formed of a plurality of sintered metal particles;an electroless plating layer that is layered on a surface of the sintered layer that is opposite to the base film; andan electroplating layer that is layered on a surface of the electroless plating layer that is opposite to the sintered layer,wherein an arithmetic mean height Sa of the surface of the electroless plating layer opposite to the sintered layer is greater than or equal to 0.001 μm and less than or equal to 0.5 μm.2. The base material for a printed circuit board according to claim 1 , wherein an average particle size of the metal particles is greater than or equal to 1 nm and less than or equal to 500 nm.3. The base material for a printed circuit board according to claim 1 , wherein a main component of the sintered layer claim 1 , the electroless plating layer claim 1 , and the electroplating layer is copper.4. A printed circuit board comprising:an insulating base film;a sintered layer that is layered on at least one side surface of the base film and that is found of a plurality of sintered metal particles;an electroless plating layer that is layered on a surface of the sintered layer that is ...

METHOD FOR MAKING A CIRCUIT BOARD

A method for making a circuit board comprising: providing a silver clad laminate comprising a substrate and two silver foils; forming at least one through hole on the silver clad laminate, the through hole comprises an annular middle wall and two annular edge walls connected to two sides of the annular middle wall; forming an organic conductive film on the annular middle wall; forming a dry film pattern layer on the second area; plating copper to form a copper circuit layer on the first area, and to form a via hole in the through hole; removing the dry film pattern layer; and etching the second area of the silver foil away. The first area changes to a silver circuit layer. The copper circuit layer and the silver circuit layer define a conductive circuit layer. A circuit board made by the method is also provided. 1. A method for making a circuit board comprising:providing a silver clad laminate, the silver clad laminate comprising a substrate and two silver foils attached to two opposite surfaces of the substrate, each of the two silver foils comprising a first area and a second area;forming at least one through hole on the silver clad laminate, the through hole comprising an annular side wall, the annular side wall comprising an annular middle wall and two annular edge walls connected to two sides of the annular middle wall, the annular middle wall being a surface of the substrate, each of the two annular edge walls being a surface of a silver foil;forming an organic conductive film on the annular middle wall;forming a dry film pattern layer on a surface of the second area away from the substrate to obtain an intermediate product;plating copper on the intermediate product to form a copper circuit layer on a surface of the first area away from the substrate and to form a via hole in the through hole;removing the dry film pattern layer from the second area of the silver foil to expose the surface of the second area away from the substrate;etching the second area of ...

CERAMIC SUBSTRATE AND MANUFACTURING METHOD THEREFOR

A ceramic substrate is provided in which an inclined protrusion is formed on boundary surface of a metal layer bonded to a ceramic base so as to increase bonding strength; and a manufacturing method therefor. The inclined protrusion may include: a tapered protrusion and a multi-stepped protrusion formed on the boundary surface of the metal layer according to an interval between the metal layer bonded to the ceramic base and a neighboring metal layer, wherein a multi-stepped protrusion having an inclination angle within a predetermined angle range with respect to the ceramic base may be formed on the boundary surface of the metal layer where stress is concentrated, such as the short edge, apex, corner, and the like, and a tapered protrusion may be formed on a remaining portion of the boundary surface of the metal layer. 1. A ceramic substrate , comprising:a ceramic base and;a metal layer bonded to at least one surface of the ceramic base,wherein the metal layer has an inclined protrusion formed on a boundary surface thereof.2. The ceramic substrate of claim 1 , wherein the metal layer is bonded to the surface of the ceramic base through brazing.3. The ceramic substrate of claim 1 , further comprising:a bonding layer interposed between the ceramic base and the metal layer to bond the ceramic base and the metal layer to each other.4. The ceramic substrate of claim 1 , wherein the inclined protrusion inclinedly extends from an upper edge of the metal layer to protrude toward an outside end of the ceramic base through a virtual line which is perpendicular to the ceramic substrate.5. The ceramic substrate of claim 1 , wherein the inclined protrusion increases in protruding length toward the ceramic base.6. The ceramic substrate of claim 1 , wherein the inclined protrusion is formed in a shape concaved toward the ceramic base.7. The ceramic substrate of claim 1 , wherein the inclined protrusion is formed to have a protruding length toward the ceramic base claim 1 , the ...

METHOD FOR FABRICATING A FLEXIBLE ELECTRONIC STRUCTURE AND A FLEXIBLE ELECTRONIC STRUCTURE

Flexible electronic structure and methods for fabricating flexible electronic structures are provided. An example method includes applying a first layer to a substrate, creating a plurality of vias through the first layer to the substrate, and applying a second polymer layer to the first layer such that the second polymer forms anchors contacting at least a portion of the substrate. At least one electronic device layer is disposed on a portion of the second polymer layer. At least one trench is formed through the second polymer layer to expose at least a portion of the first layer. At least a portion of the first layer is removed by exposing the structure to a selective etchant to providing a flexible electronic structure that is in contact with the substrate. The electronic structure can be released from the substrate. 1. A method for fabricating a flexible electronic structure , said method comprising:applying a first layer to a portion of a substrate;removing selected portions of the first layer to provide a plurality of vias, wherein a portion of the vias extend substantially to a surface of the substrate;disposing a second polymer layer, such that portions of the second polymer layer conform to a dimension of at least one of the plurality of vias and forms a plurality of anchors that contact at least a portion of the substrate, wherein the second polymer layer is more resistant to a selective etchant than the first layer;disposing at least one electronic device layer above a portion of the first layer and/or the second polymer layer;forming at least one trench through the second polymer layer and the at least one electronic device layer to expose at least a portion of the first layer;exposing at least a portion of the first layer to the selective etchant through the at least one trench; andremoving, by the selective etchant, portions of the first layer, thereby providing the flexible electronic structure, wherein at least one anchor of the plurality of anchors ...

METHOD FOR PRODUCING WIRING BOARD

A method for producing a wiring board includes the steps of forming an upper insulating layer on a lower insulating layer having a lower wiring conductor on its upper surface; forming a via-hole in the upper insulating layer; depositing a first base metal layer in the via-hole and on an upper surface of the upper insulating layer; forming a first plating resist layer on the first base metal layer; depositing a first electrolytically plated layer to completely fill at least the via-hole; forming a via conductor, and depositing a second base metal layer; forming a second plating resist layer on the second base metal layer; depositing a second electrolytically plated layer; and forming a wiring pattern. 1. A method for producing a wiring board comprising the steps of:forming an upper insulating layer on a lower insulating layer in such a manner as to cover a lower wiring conductor formed on an upper surface of the lower insulating layer;forming a via-hole in the upper insulating layer in such a manner that its bottom surface reaches the lower wiring conductor;depositing a first base metal layer in the via-hole and on an upper surface of the upper insulating layer;forming a first plating resist layer on the first base metal layer having a first opening pattern to expose the via-hole and a periphery of the via-hole;depositing a first electrolytically plated layer in the first opening pattern to completely fill at least the via-hole;forming a via conductor including the first base metal layer and the first electrolytically plated layer by removing the first plating resist layer, and recessing a surface of the first electrolytically plated layer from the surface of the upper insulating layer by 0 μm to 15 μm;depositing a second base metal layer on a surface of the via conductor and an exposed surface of the upper insulating layer;forming a second plating resist layer on the second base metal layer having a second opening pattern passing on the via-hole and having a width ...

METHODS OF ETCHING CONDUCTIVE FEATURES, AND RELATED DEVICES AND SYSTEMS

A method of making a device patterned with one or more electrically conductive features includes depositing a conductive material layer over an electrically insulating surface of a substrate, depositing an anti-corrosive material layer over the conductive material layer, and depositing an etch-resist material layer over the anti-corrosive material layer. The etch-resist material layer may be deposited over the anti-corrosive material layer, and the anti-corrosive material layer forming a bi-component etch mask in a pattern resulting in covered portions of the conductive material layer and exposed portions of the conductive material layer, the covered portions being positioned at locations corresponding to one or more conductive features of the device. A wet-etch process is performed to remove the exposed portions of the conductive material layer from the electrically insulating substrate, and the bi-component etch mask is removed to expose the remaining conductive material. Systems and devices relate to devices with patterned features.

STRETCHABLE CIRCUIT BOARD AND METHOD OF MANUFACTURING THE SAME

A stretchable circuit board has stretchability as well as flexibility of the flexible substrate and retains mechanical and electrical properties even under larger deformation such as bending, twisting, etc. The liquid metal pattern can exhibit stretchability almost to same to that of the polymer substrate due to that the liquid metal is fully wetted on the substrate with metal patterns based on the wetting behavior of the liquid metal. Therefore, the stretchable circuit board can achieve both mechanical and electrical properties even under physical deformation such as bending, stretching and twisting. It is demonstrated that the stretchable circuit board can be effectively applied to wearable tactile interfaces, stretchable solar cell arrays, stretchable displays, and wearable electronic devices. 1. A method of manufacturing a stretchable circuit board , comprising steps of:(a) forming a first polymer layer on a surface of a wafer;(b) forming a pattern by coating a surface of the first polymer layer with a metal film;(c) plating a reduced liquid metal on the pattern; and(d) removing the wafer,wherein the step (c), plating a reduced liquid metal on the pattern is performed based on the wettability of the liquid metal, which varies depending on the surface of the material which is in contact with the reduced liquid metal.2. The method of claim 1 , wherein the step (a) is performed by coating polydimethylsiloxane (PDMS) on the surface of the wafer.3. The method of claim 1 , wherein the step (b) is performed by depositing metal on the first polymer layer formed in the step (a) claim 1 , wherein the metal is selected from the group including gold (Au) claim 1 , chromium (Cr) claim 1 , silver (Ag) claim 1 , aluminum (Al) claim 1 , copper (Cu) claim 1 , platinum (Pt) claim 1 , zinc (Zn) claim 1 , nickel (Ni) claim 1 , tin (Sn) claim 1 , iron (Fe) claim 1 , and so on.4. The method of claim 1 , wherein the step (c) is performed by plating liquid metal (comprising gallium ...

CONDUCTIVE STRUCTURE BODY AND METHOD FOR MANUFACTURING THE SAME

The present specification relates to a conductive structure body and a method for manufacturing the same. 1. A conductive structure body comprising:a substrate;a conductive pattern layer provided on the substrate; anda darkening pattern layer provided on at least one surface of the conductive pattern layer,{'sub': a', 'b', 'c', 'd, 'wherein the darkening pattern layer includes a copper-manganese-based material represented by CuMnON,'}in the copper-manganese-based material,b is a mass ratio of Mn to the copper-manganese-based material and 0.01 or more and 0.5 or less,c is a mass ratio of O to the copper-manganese-based material and 0.05 or more and 0.6 or less,d is a mass ratio of N to the copper-manganese-based material and 0 or more and 0.15 or less, anda is a mass ratio of Cu to the copper-manganese-based material and a remainder value to a sum of the mass ratios of components other than Cu.2. The conductive structure body of claim 1 , wherein in the copper-manganese-based material claim 1 , d is 0 claim 1 , and c is 0.25 or more and 0.6 or less.3. The conductive structure body of claim 1 , wherein in the copper-manganese-based material claim 1 , d is more than 0 and 0.15 or less claim 1 , and c+d is 0.15 or more and 0.6 or less.4. The conductive structure body of claim 1 , wherein total reflectance of the conductive structure body is 25% or less.56-. (canceled)7. The conductive structure body of claim 2 , wherein the conductive pattern layer is provided between the substrate and the darkening pattern layer claim 2 , and the total reflectance is measured on a surface of the substrate claim 2 , on which the conductive pattern is provided.8. The conductive structure body of claim 2 , wherein the darkening pattern layer is provided between the substrate and the conductive pattern layer claim 2 , and the total reflectance is measured on an opposite surface of the surface of the substrate claim 2 , on which the conductive pattern is provided.9. The conductive structure ...

PRINTED CIRCUIT BOARD AND METHOD OF MANUFACTURING THE SAME

A printed circuit board includes: an insulating layer including a cavity formed therein, the cavity being recessed into the insulating layer from a top surface of the insulating layer; a first circuit layer formed inside the insulating layer such that a portion of the first circuit layer is disposed within the cavity; a second circuit layer disposed above the insulating layer; a first surface-treated layer disposed above the portion of the first circuit layer disposed within the cavity; and a second surface-treated layer disposed above the second circuit layer. 1. A printed circuit board comprising:an insulating layer comprising a cavity formed therein, the cavity being recessed into the insulating layer from a top surface of the insulating layer;a first circuit layer formed inside the insulating layer such that a portion of the first circuit layer is disposed within the cavity;a second circuit layer disposed above the insulating layer;a first surface-treated layer disposed above the portion of the first circuit layer disposed within the cavity; anda second surface-treated layer disposed above the second circuit layer.2. The printed circuit board of claim 1 , wherein the first surface-treated layer is constructed of a material that does not react with an etchant that reacts with the second circuit layer.3. The printed circuit board of claim 1 , further comprising a first protective layer disposed above the insulating layer within the cavity and surrounding and protecting the first circuit layer claim 1 , wherein the first protective layer is formed to expose an upper surface of the first surface-treated layer to an outside environment.4. The printed circuit board of claim 1 , further comprising a first protective layer disposed above the insulating layer within the cavity and between a lateral surface of the second insulating layer and a lateral surface of the first circuit layer.5. The printed circuit board of claim 1 , further comprising a second protective layer ...

PRINTED CIRCUIT BOARD AND METHOD OF MANUFACTURING THE SAME

A printed circuit board and a method of manufacturing a printed circuit board are provided. The printed circuit board includes an insulating layer, a circuit layer embedded in the insulating layer, a solder resist layer disposed on one surface of the insulating layer, the solder resist layer having a cavity of a through-hole shape to expose a part of the circuit layer from the insulating layer, and a metal post embedded in the solder resist layer and exposed to outside via an opening of the solder resist layer, and the metal post includes a first post metal layer, a post barrier layer, and a second post metal layer disposed in that order. 1. A printed circuit board comprising:an insulating layer;a circuit layer embedded in the insulating layer;a solder resist layer disposed on one surface of the insulating layer, the solder resist layer having a cavity of a through-hole shape to expose a part of the circuit layer from the insulating layer; anda metal post embedded in the solder resist layer and exposed to outside via an opening of the solder resist layer,wherein the metal post comprises a first post metal layer, a post barrier layer, and a second post metal layer disposed in that order.2. The printed circuit board of claim 1 , wherein the post barrier layer is formed of a material that is different from that of the first post metal layer and the second post metal layer.3. The printed circuit board of claim 2 , wherein the post barrier layer comprises a material that has a different reactivity to an etchant reactive to the first post metal layer and second post metal layer.4. The printed circuit board of claim 1 , wherein the circuit layer has a 2-layered structure comprising a circuit metal layer and a circuit barrier layer claim 1 , the circuit barrier layer disposed on the circuit metal layer.5. The printed circuit board of claim 4 , wherein a portion of the circuit layer that is exposed to the outside through the cavity is formed in a single-layered structure ...

SILVER-BASED TRANSPARENT CONDUCTIVE LAYERS INTERFACED WITH COPPER TRACES AND METHODS FOR FORMING THE STRUCTURES

A method is described for method for patterning a metal layer interfaced with a transparent conductive film, in which the method comprises contacting a structure through a patterned mask with an etching solution comprising Feions, wherein the structure comprises the metal layer comprising copper, nickel, aluminum or alloys thereof covering at least partially a transparent conductive film with conductive elements comprising silver, to expose a portion of the transparent conductive film. Etching solutions and the etched structures are also described. 1. A method for patterning a metal layer interfaced with a transparent conductive film , the method comprising:{'sup': '+3', 'contacting a structure through a patterned mask with an etching solution comprising Feions, wherein the the structure comprises the metal layer comprising copper, nickel, aluminum or alloys thereof covering at least partially a transparent conductive film with conductive elements comprising silver, to expose a portion of the transparent conductive film.'}2. The method of wherein the etching solution comprises water and from about 0.001M to about 0.25M Fe.3. The method of wherein the etching solution further comprises a strong acid at a concentration from about 0.0001M to about 0.1M.4. The method of wherein the etching solution further comprises from 0.001 to about 0.5 wt % non-ionic surfactant.5. The method of wherein the etching solution further comprises from 0.001M to about 0.25M Fe.6. The method of wherein the etching solution has from about 0.005M to about 0.05M Fe claim 1 , from about 0.0025 wt % to about 0.1 wt % non-ionic surfactant claim 1 , and the strong acid at a concentration from about 0.00025M to about 0.03M claim 1 , wherein the strong acid is nitric acid and the anions balancing the iron cations are nitrate anions.7. The method of wherein the transparent conductive film comprises a fused metal nanostructured network with a polymer overcoat having an average thickness from about 25 ...

SYSTEMS AND METHODS FOR ETCHING OF METALS

A method of fabricating a multilayer superconducting printed circuit board comprises first, forming a bimetal foil to overlie a substrate, the bimetal foil comprising a first layer of a first metal, a layer of a second metal, and a second layer of the first metal, and then etching the second layer of the first metal. Forming a bimetal foil to overlie a substrate may include forming a bimetal foil comprising a first layer of a normal metal, a layer of a superconducting metal, and a second layer of the normal metal. Etching the second layer of the first metal may include preparing a patterned image in the second layer of the first metal for etching, processing the patterned image through a cleaner, rinsing the patterned image, and then, immersing the patterned image in a microetch. 1. A method of fabricating a multilayer superconducting printed circuit board , the method comprising:first, forming a bimetal foil to overlie a substrate, the bimetal foil comprising a first layer of a first metal, a layer of a second metal, and a second layer of the first metal; andthen etching the second layer of the first metal.2. The method of claim 1 , wherein the etching the second layer of the first metal includes:preparing a patterned image in the second layer of the first metal for etching;processing the patterned image through a cleaner;rinsing the patterned image; andthen, immersing the patterned image in a microetch.3. The method of claim 2 , wherein the processing the patterned image through a cleaner includes processing the patterned image through the cleaner claim 2 , the cleaner comprising a surfactant.4. The method of claim 3 , wherein the processing the patterned image through the cleaner includes processing the patterned image through the cleaner claim 3 , the cleaner which further includes de-ionized water and sulfuric acid.5. The method of claim 2 , wherein the immersing the patterned image in a microetch includes immersing the patterned image in the microetch claim 2 ...

一种闪蚀药水及其制备方法和应用

本发明提供了一种闪蚀药水及其制备方法和应用，所述闪蚀药水包括溶解在去离子水中的如下组分：硫酸50‑100g/L；过氧化氢10‑50g/L；铜离子5‑45g/L；混合醇10‑35g/L；余量为去离子水；其中，所述混合醇为任意两种醇的组合。本发明提供的闪蚀药水可以有效地去除底铜并减少侧蚀，同时有效地保护了线路的棱角，维持线路截面的矩形形状，可适用于MSAP工艺；同时，本发明提供的闪蚀药水具有较好的储存稳定性。

Nickel etching process and solution

Process and solution for etching nickel and nickel alloys, particularly suitable for use in the manufacture of printed circuit boards. The nickel or alloy is contacted with an aqueous solution of nitric acid, nickel nitrate, a halogen additive and a surfactant. In some embodiments, a small amount of an amino acid is included in the solution to enhance the smoothness of the edges of the etched patterns.

一种闪蚀药水及其制备方法和应用

本发明提供了一种闪蚀药水及其制备方法和应用，所述闪蚀药水包括溶解在去离子水中的如下组分：硫酸50‑100g/L；过氧化氢10‑50g/L；铜离子5‑45g/L；混合醇10‑35g/L；余量为去离子水；其中，所述混合醇为任意两种醇的组合。本发明提供的闪蚀药水可以有效地去除底铜并减少侧蚀，同时有效地保护了线路的棱角，维持线路截面的矩形形状，可适用于MSAP工艺；同时，本发明提供的闪蚀药水具有较好的储存稳定性。

Method of producing fine-line circuit boards using chemical polishing

A printed circuit board is produced by patterning a resist layer according to a circuit mask that defines desired circuit paths. The resist pattern layer is formed by removing the resist from the board in the desired circuit paths and a conductive material is plated onto the board in the resist voids defined by the circuit mask so that the height of the conductive material relative to the substrate equals or exceeds the height of the resist layer relative to the substrate. A low-reactive solution is applied over the conductive material and removes a surface portion of the conductive material. As the solution removes the conductive layer, it forms a film barrier and the solution composition changes, both of which substantially inhibits any further removal of the conductive material. Next, the film barrier is removed from the board allowing another film barrier to form stimulating the removal of further conductive material. The removal step is repeated until the conductive material is at a desired height relative to the height of the resist layer. The board is then finished using conventional circuit board fabrication techniques.

Method for manufacturing printed wiring board

Copper-clad laminate with copper-plated circuit layer and method for producing printed wiring board using copper-clad laminate with copper-plated circuit layer

Multi-layer printed circuit boards and their manufacture

High-current transfer methods utilizing the printed circuit board

본 발명은 다층 인쇄회로기판에 형성된 비아 홀의 충전 구조 및 방법에 관한 것으로, 보다 구체적으로는 일반 다층 인쇄회로기판 제조 공정 시 형성된 비아 홀을 Cu, Au 도금으로 1차 충전하고, 나머지 빈 공간을 솔더크림으로 완전히 메움으로써 도체량을 증가시켜 좁은 공간에서도 고전류 전송이 가능하도록 하는 다층 인쇄회로기판에 형성된 비아 홀의 충전구조 및 방법에 관한 것이다. The present invention relates to a filling structure and method of via holes formed in a multilayer printed circuit board. More specifically, the via holes formed during a general multilayer printed circuit board manufacturing process are primarily filled with Cu or Au plating, and the remaining empty space is soldered. The present invention relates to a filling structure and method for via holes formed in a multilayer printed circuit board to increase the amount of conductors by completely filling the cream to enable high current transmission even in a narrow space.

エツチングレジストインキ

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Method for making metallic patterns

Method of manufacturing multilayer wiring boards

하층의 배선층 위에 주형 금속체을 형성하는 단계를 가지며, 또한 주형 금속체에 전기적으로 연결된 일부 상층의 배선층을 형성한 후, 하층의 배선층에 도금 단계의 일부 주형체와 일부 주형 금속체로 구성된 금속이 에칭 되는 경우 도전층 주형 금속체로 구성되는 금속 도금층의 형성, 도전층을 포함하는 표면의 개구, 주형 금속체로부터 도금층의 외면의 개구 상에 마스크 층, 및 도금층의 에칭을 하는 특징이 있는 다층 배선기판의 제조방법이고, 이 방법은 간이하고 저렴하며, 또한 짧은 시간에 일정하게 높은 주형 금속체을 형성하는 능력이 있다. Forming a mold metal body on the lower wiring layer, and forming a part of the upper wiring layer electrically connected to the mold metal body, and then etching the metal composed of some of the mold body and some mold metal body of the plating step on the lower wiring layer. Manufacture of a multilayer wiring board characterized by forming a metal plating layer composed of a conductive layer mold metal body, an opening on a surface including the conductive layer, a mask layer on the opening of the outer surface of the plating layer from the mold metal body, and etching of the plating layer. It is a method, which is simple and inexpensive, and also has the ability to form a constantly high mold metal body in a short time.

필름 박리, 탈검 및 코퍼링을 위한 쓰리 인 원 방법

필름 박리, 탈검 및 코퍼링을 위한 쓰리 인 원 방법으로서, (a) 구리 층을 갖는 인쇄 회로 기판을 제공하는 단계 ― 구리 층의 표면은 조면화되어 필름을 형성하며, 인쇄 회로 기판은 적어도 홀 및 접착 잔류물을 생성하도록 레이저 드릴링 됨 ―; 및 (b) 필름 박리 공정, 탈검 공정 및 코퍼링 공정을 통합하는 단계 ― 필름 박리 공정은 필름의 제1 마이크로 에칭 및 박리를 동시에 수행하기 위한 필름 박리제를 갖는 마이크로 에칭 용액을 제공하며, 그 후에 접착 잔류물을 제거하도록 탈검 공정을 수행하며, 그 후에 홀 상에 화학적 구리의 얇은 층을 증착하도록 코퍼링 공정을 수행함 ―;를 포함한다.

Copper plated circuit layer-carring copper clad laminated sheet and method of producing printed wiring board using the copper plated circuit layer-carring copper clad laminated sheet

화인피치회로를 구비한 프린트배선판에 가공한 경우에 회로형상의 어스팩트비를, 종래보다 우수한 형상으로 하는 것이 가능한 동도금 회로층이 부착된 동 클래드적층판 및 프린트배선판의 제조방법을 제공하는 것을 목적으로 한다. It is an object of the present invention to provide a method for producing a copper clad laminated board and a printed wiring board with a copper plating circuit layer capable of making the aspect ratio of the circuit shape superior to that in the past when processed to a printed wiring board having a fine pitch circuit. do. 세미 어디티브법으로 프린트배선판을 제조하기 위한 동도금 회로층(6)을 구비한 동도금 회로층이 부착된 동 클래드적층판에 있어서, 특정의 애칭액을 사용하는 경우에, 상기 동도금 회로층(6)을 구성하는 적출동의 용해속도(Vsp)와, 바깥층 동박층(3)을 구성하는 동의 용해속도(Vsc)와의 비인 Rv 값 = (Vsc / Vsp)가 1.0 이상으로 되는 관계를 만족하는 동도금 회로층(6)과 바깥층 동박층(3)을 포함하는 것을 특징으로 하는 동도금 회로층이 부착된 동 클래드적층판을 이용하여, 프린트배선판의 제조를 행한다. In the copper clad laminated board with the copper plating circuit layer provided with the copper plating circuit layer 6 for manufacturing a printed wiring board by the semiadditive process, when the specific nickname is used, the copper plating circuit layer 6 is used. Copper plating circuit layer 6 which satisfies the relationship that Rv value = (Vsc / Vsp) which is ratio of melting | dissolution rate (Vsp) of the extraction copper to constitute and copper melting rate (Vsc) which comprises the outer layer copper foil layer 3 becomes 1.0 or more. And a copper clad laminated board with a copper plating circuit layer characterized by including an outer layer copper foil layer 3, and a printed wiring board is manufactured.

陶瓷基板及其制造方法

本发明的一实施例提供在接合到陶瓷基材的金属层的外周形成倾斜突出部以增加接合强度的陶瓷基板及其制造方法。针对倾斜突出部，也可根据接合到陶瓷基材的金属层与相邻的其他金属层之间的间隔而在金属层的外周形成锥形突出部及多级突出部，并且可以在金属层的外周中如短边、顶点、角部的压力集中的外周形成与陶瓷基材具有设定角度范围以内的倾斜度的多级突出部，在剩余外周形成锥形突出部。该陶瓷基板及其制造方法具有如下的效果：与现有的微凹型陶瓷AMB基板相比能够增加金属层的面积并提高导电率、热电阻等电气特性的同时，维持与现有的微凹型陶瓷AMB基板同等或相对高的水平的耐龟裂型、耐分离性及接合强度，因此能够延长使用寿命的同时确保可靠性，并且也可以应用到微细图案中。

Curcuit board and method of manufacturing the same

도전막을 용이하게 식각할 수 있도록, 본 발명은 절연성 기판상에 금속으로 패드부 및 상기 패드부와 연결되는 리드 라인부를 형성하는 단계, 상기 패드부 및 리드 라인부상에 니켈을 함유하는 제1 도전층 및 상기 제1 도전층상에 형성되고 금을 함유하는 제2 도전층을 구비하는 도전층을 형성하는 단계, 상기 도전층의 영역 중 상기 리드 라인부에 대응되는 영역을 노출하도록 상기 도전층상에 식각 마스크를 형성하는 단계, 상기 식각 마스크에 의하여 노출된 상기 리드 라인부의 영역과 상기 리드 라인부에 대응되는 상기 도전층의 영역을 산을 포함하는 식각 용액으로 식각하는 단계 및 상기 식각 마스크를 제거하는 단계를 포함하는 회로 기판 제조 방법을 제공한다. According to an embodiment of the present invention, a pad portion and a lead line portion connected to the pad portion are formed on an insulating substrate so that the conductive layer can be easily etched. The first conductive layer containing nickel is formed on the pad portion and the lead line portion. And forming a conductive layer formed on the first conductive layer and having a second conductive layer containing gold, wherein the etching mask is formed on the conductive layer to expose a region corresponding to the lead line portion among the regions of the conductive layer. Forming an etching solution; and etching the region of the lead line portion exposed by the etching mask and the region of the conductive layer corresponding to the lead line portion with an etching solution including an acid and removing the etching mask. It provides a circuit board manufacturing method comprising.

회로기판용 에칭장치

본 발명은 회로기판용 에칭장치를 개시한다. 본 발명의 회로기판용 에칭장치는 에칭 처리조 내에 설치되어 에칭액을 회로기판의 표면으로 토출하는 에칭 노즐과, 상기 에칭 노즐에 에칭액을 공급하며 염산 탱크와 과산화수소 탱크로부터 용액을 공급받아 이를 혼합하는 혼합 탱크와, 상기 혼합 탱크내의 에칭액이 와류 흐름을 갖도록 배관되는 와류수단과, 상기 혼합 탱크내의 에칭액 농도를 유지하는 신액을 보관하는 신액 탱크 및 이 신액 탱크내의 신액을 혼합 탱크 내부로 분무하는 분무수단을 포함하여 구성된다. 상기와 같이 구성되는 본 발명에 따른 회로기판용 에칭장치는, 신액의 지속적인 공급과 안정된 액 순환을 유도하여 혼합 탱크내의 에칭액의 농도 균일화를 안정되게 보장하므로 에칭 공정에서의 불량률 감소에 따른 생산성 및 수율 향상을 기대할 수 있는 효과가 있다. 회로기판, 에칭, 에칭기, 농도

附有镀铜电路层的覆铜层压板及使用该附有镀铜电路层的覆铜层压板制造印刷电路板的方法

本发明的目的是提供一种附有镀铜电路层的覆铜层压板及印刷电路板的制造方法。使用该覆铜层压板制造含有微细电路的印刷电路板时，其电路形状的纵横比可比迄今为止的形状更优良。一种附有镀铜电路层的覆铜层压板，它具有用于通过半添加法制造印刷电路板的镀铜电路层(6)，其特征在于，它具有满足下述条件镀铜电路层(6)和外层铜箔层(3)，在使用特定的浸蚀液的情况下，上述构成镀铜电路层(6)的析出铜的溶解速度(Vsp)与上述构成外层铜箔层(3)的铜的溶解速度(Vsc)之比Rv值＝(Vsc/Vsp)为1.0以上，使用具有该特征的附有镀铜电路层的覆铜层压板制造印刷电路板。

Printed circuit board using carrier substrate and method of manufacturing the same

캐리어 기판을 이용한 초미세 피치 인쇄회로기판 및 그 제조 방법에 대하여 개시한다. 본 발명에 따른 초미세 피치 인쇄회로기판은 제1 면과 제2 면을 포함하는 절연층; 상기 절연층의 제1 면에 형성되며 서로 이격된 복수의 회로를 포함하는 제1 회로부; 상기 절연층의 제2 면에 형성된 외부 연결용 제2 회로부; 상기 제1 회로부를 보호하도록 형성된 제1 솔더 레지스트; 상기 제2 회로부를 보호하도록 형성된 제2 솔더 레지스트; 및 상기 제1 회로부 및 제2 회로부를 연결하도록 상기 절연층을 관통하여 형성된 비아 회로부;를 포함하고, 상기 제1 회로부는 상기 절연층의 제1 면으로부터 내측 방향으로 매립된 형태로 서로 이격 형성된 복수의 매립형 회로와, 상기 절연층의 제1 면 상에 형성된 절연 필름과, 상기 절연 필름 상에 서로 이격 형성된 복수의 돌출형 회로를 포함하는 것을 특징으로 한다. An ultrafine pitch printed circuit board using a carrier substrate and a manufacturing method thereof are disclosed. An ultrafine pitch printed circuit board according to the present invention includes: an insulating layer including a first side and a second side; A first circuit comprising a plurality of circuits formed on a first surface of the insulating layer and spaced apart from each other; A second circuit part for external connection formed on a second surface of the insulating layer; A first solder resist formed to protect the first circuit portion; A second solder resist formed to protect the second circuit portion; And a via circuit portion formed through the insulating layer to connect the first circuit portion and the second circuit portion, wherein the first circuit portion includes a plurality of spaced-apart An insulating film formed on the first surface of the insulating layer, and a plurality of protruding circuits spaced apart from each other on the insulating film.