МОЩНАЯ ГИБРИДНАЯ ИНТЕГРАЛЬНАЯ СХЕМА СВЧ-ДИАПАЗОНА

Использование: полупроводниковая микроэлектроника. Сущность изобретения: в мощной гибридной интегральной схеме СВЧ-диапазона глубина углублений в металлическом основании выбрана такой, что лицевая поверхность кристаллов и металлическое основание расположены в одной плоскости, диэлектрическая плата имеет экранную заземляющую металлизацию на обратной стороне в местах, прилегающих к металлическому основанию, металлическое основание герметично и электрически соединено с экранной заземляющей металлизацией платы, а соединяющие отверстия платы заполнены электропроводящим материалом, причем расстояние от боковых поверхностей кристаллов до боковых поверхностей углублений в основании составляет 0,001 - 0,2 мм. Техническим результатом изобретения является улучшение электрических и теплорассеивающих характеристик схемы. 2 з.п.ф-лы, 2 ил.

ВЕРТИКАЛЬНЫЕ ЭЛЕКТРИЧЕСКИЕ СОЕДИНЕНИЯ В СТОПЕ СЛОЕВ

... 1. Устройство памяти и/или обработки данных, содержащее, по меньшей мере, два слоя (L), образующие стопу (1), представляющую собой отдельную структуру или расположенную на подложке (2) и содержащую, по меньшей мере, одну структуру, сдвинутую, по меньшей мере, в одном направлении, в результате чего в сдвинутой структуре сформированы ступени, образованные открытыми частями отдельных слоев (L) в стопе (1), причем высота (h) ступени определяется толщиной соответствующего слоя, отличающееся тем, что на каждой ступени сдвинутой структуры образованы одна или более контактных площадок (4), электрически соединенных с контурами памяти и/или обработки данных в соответствующем слое (L); поверх ступени в каждом слое (L) сформированы одно или более краевых соединений (3) в виде электропроводных структур, нанесенных над указанной ступенью и за ее кромкой между ступенями в каждом слое (L) на поверхности этого слоя, причем электрические краевые соединения (3) находятся в контакте с одной или более контактными ...

Halbleiterbauelement

Laterales Leistungs-MOSFET mit einer Metallschicht zur Verminderung des verteilten Widerstandes und Verfahren zur Herstellung

Halbleiteranordnung mit Metallplatte

Einkapselungsverfahren

Verfahren zum Einkapseln eines Halbleiterbauelements, mit den folgenden Schritten: Bereitstellen eines Systemträgers (12), der eine erste Chippadzone und eine zweite Chippadzone aufweist, wobei jede Chippadzone eine erste Seite (60, 62) und eine zweite Seite (70, 72) aufweist, wobei die erste Chippadzone relativ zu der zweiten Chippadzone in der Höhe versetzt ist und wobei die erste Chippadzone und die zweite Chippadzone zusammenhängend sind; Befestigen eines ersten Chips (16) an der ersten Seite (62) der ersten Chippadzone; Befestigen eines zweiten Chips (14) an der ersten Seite (60) der zweiten Chippadzone; Drahtbonden von Drähten an den ersten und zweiten Chip (16, 14); Anordnen eines Gussrahmens gegenüber dem Systemträger (12), um eine Lücke zwischen den zweiten Seiten (72, 70) der ersten und der zweiten Chippadzonen und einer Oberfläche des Gussrahmens zu bilden; und Einkapseln mit einem den ersten Chip (16) und den zweiten Chip (14) überdeckenden Einkapselungsmaterial, das in die ...

ELEKTRONIKGEHÄUSE MIT LEITERRAHMEN MIT VERBESSERTER ADHAESION

Gestapelte Mehrchip-Module und Verfahren zur Herstellung

Verfahren zur Anordnung von Bauelementen mittels Kleber

KLEBSTOFFPASTE WELCHE EIN POLYMERES HARZ ENTHÄLT

Packung für elektronische Schaltung

Verfahren zum Herstellen einer harzumhüllte Halbleiteranordnung

Leiterplatte für Plastikhalbleitergehäuse

Methode zur Verminderung der gegenseitigen Induktanz zwischen Verbindungsdrähten einer Hochfrequenzverstärkerschaltung

Herstellungsverfahren von einer Mehrschichtleiterbahn-Struktur über einer Halbleiteranordung

In ein Gehaeuse eingebauter Hochleistungsgleichrichter

Haft-Klebemittel-Zusammensetzung für Halbleiter.

LOTTRAEGER, VERFAHREN ZU DESSEN HERSTELLUNG UND VERFAHREN ZUR MONTAGE VON HALBLEITERANORDNUNGEN UNTER DESSEN VERWENDUNG

Bauelement mit einem Halbleiterchip und Verfahren zur Herstellung eines Moduls mit gestapelten Bauelementen

Bauelement (300), umfassend: einen Träger (30), ein auf dem Träger (30) abgeschiedenes erstes Material (31), wobei das erste Material (31) einen Elastizitätsmodul von unter 100 MPa aufweist, einen über dem ersten Material (31) platzierten Halbleiterchip (11), ein auf dem Träger (30) und dem Halbleiterchip (11) abgeschiedenes zweites Material (12), wobei das zweite Material (12) einen Elastizitätsmodul von unter 100 MPa aufweist, eine Metallschicht (10) umfassend eine erste Fläche (13) und eine der ersten Fläche (13) gegenüberliegende zweite Fläche (14), wobei die Metallschicht (10) über dem zweiten Material (12) platziert ist und ihre erste Fläche (13) dem zweiten Material (12) zugewandt ist, und mindestens ein Durchgangsloch (38, 39), das von der ersten Fläche (13) der Metallschicht (10) durch das zweite Material (12) und den Träger (30) verläuft.

Verfahren zur Herstellung einer Halbleiter-anordnung

HALBLEITERANORDNUNG UND VERFAHREN ZU IHRER HERSTELLUNG

Halbleitervorrichtung, Substrat zum Herstellen einer Halbleitervorrichtung und Verfahren zum Herstellen derselben

Halbleitervorrichtung, umfassend: eine Chipkontaktstelle; ein Halbleiterelement, das auf die Chipkontaktstelle geladen ist, das Elektroden aufweist; eine Mehrzahl von elektrisch leitfähigen bzw. leitenden Abschnitten, die um die Chipkontaktstelle angeordnet sind; Drähte zum Verbinden der Elektroden des Halbleiterelements und der elektrisch leitfähigen Abschnitte; und ein Dichtharz zum Dichten von wenigstens dem Halbleiterelement, den elektrisch leitfähigen Abschnitten und Drähten; wobei jeder der elektrisch leitfähigen Abschnitte eine Metallfolie enthält, wobei den elektrisch leitfähigen Abschnitt plattierende Schichten bzw. Lagen sowohl am oberen als auch unteren Ende der Metallfolie zur Verfügung gestellt sind; wobei die Chipkontaktstelle eine Chipkontaktstellen-Plattierschicht beinhaltet, die in derselben Ebene wie untere, den elektrisch leitfähigen Abschnitt plattierende Schichten der elektrisch leitfähigen Abschnitte vorgesehen ist; und wobei die unteren, den elektrisch leitfähigen ...

Anschlussrahmen für Harz-Halbleiterverpackungen

Verfahren zur Befestigung einer metallischen Kontakt-Elektrode an dem Koerper aus halbleitendem Material einer Halbleiteranordnung

MIKROWELLEN-/MILLIMETERWELLEN-SCHALTUNGSSTRUKTUR MIT EINZELN MONTIERTEN ELEMENTEN VOM FLIPCHIPTYP UND HERSTELLUNGSVERFAHREN DAFÜR

Elektrischer Schaltungsapparat

Compensating circular lamination for power semiconductor modules

Use is made in power semiconductor modules of compensating circular laminations which absorb thermal stresses due to unequal coefficients of expansion of silicon semiconductor chips and metal parts connected thereto, e.g. copper connecting parts or copper/ceramic substrates. The compensating circular laminations are intended, moreover, to exhibit good electrical and thermal conductivity. The object of the invention is to specify a compensating circular lamination which by comparison with known compensating circular laminations leads to a reduction in the thermal stresses occurring during operation. This object is achieved by means of a compensating circular lamination in which a powdery mixture of different materials, e.g. molybdenum and copper, is sintered to produce a moulded part, the concentration of the powder components used varying by location. The circular lamination exhibits a high molybdenum concentration, e.g. on the side facing a silicon chip, and a high copper fraction on the ...

System und Verfahren zur Verstärkung einer Anschlussfläche

Verpackungsstruktur für elektronische Bauteile und Methode zu deren Herstellung

Verfahren zum Herstellen einer Halbleiteranordnung.

Wiring substrate for pressure sensors, acceleration sensors and ultrasonic sensors, comprises electrode cushion pad, which is arranged in opening, formed in protection insulation film

The wiring substrate has a wiring layer (15) formed on the surface of a silicon substrate (11), another wiring layer (16) formed on the surface of the former wiring layer. A protection insulation film (14) is so formed that it covers the latter wiring layer. An opening (14a) is formed in the protection insulation film, and an electrode cushion pad is arranged in the opening. The opening in the protection insulation film and the former wiring layer are formed at such positions that they do not overlap each other toward the card thickness of the substrate.

Vorrichtung und Verfahren zum Verbinden von Komponenten

Vorrichtung zum Verbinden von mindestens zwei Komponenten, wobei die Vorrichtung ein Ober- (96) und ein Unterwerkzeug (95) aufweist, wobei das Unterwerkzeug (95) die mindestens zwei Komponenten (3, 2, 21, 22, 23, 1, 11, 12, 13) umfasst, wobei eine erste Komponente (3) die mindestens eine zweite Komponente (2, 21, 22, 23, 1, 11, 12, 13) mit einem zumindest teilweisen Überlapp relativ zur ersten Komponente (3) trägt; das Unterwerkzeug (95) und das Oberwerkzeug (96) relativ zueinander bewegt werden können; das Oberwerkzeug (96) mindestens zwei heizbare Stempel (7, 8, 15, 16, 71, 72, 81, 82, 83) umfasst, die so verbunden sind, dass sie sich relativ zueinander über ein abgedichtetes Druckkissen (5) bewegen können; wobei die Stempel (7, 8, 15, 16, 71, 72, 81, 82, 83) und das Druckkissen (5) zwischen sich eine erste flexible Schicht (6) aufweisen; dadurch gekennzeichnet, dass zwischen dem Oberwerkzeug (96) und dem Unterwerkzeug...

Insulating material metal composite substrate, particularly ceramic metal composite substrate, has insulating layer, metal conductive paths, and power elements

The insulating material metal composite substrate has an insulating layer, metal conductive paths, and power elements, where the power element is arranged on a side of the insulating material metal composite substrate. The electrically conductive connecting elements are provided with two ends (30,31). The insulating material metal composite substrate has a metal plate, at which one end of the electrically conductive connecting elements is arranged. The metal plate is an aluminum plate (2).

Electronic component used as a semiconductor wafer comprises a semiconductor chip having contact surfaces of an integrated circuit on its active surface, and a bimetallic strip arranged on the contact surfaces

Electronic component comprises: a semiconductor chip (2) having contact surfaces (4) of an integrated circuit on its active surface (3); and a bimetallic strip (5) arranged on the contact surfaces and having a fixed end (6) connected to the contact surface and a flexible free end (7) protruding from the active surface of the chip. Preferred Features: An angled bimetallic strip is arranged on the contact surfaces. The free end of the bimetallic strip has a coating made from gold or a gold alloy, or silver alloy. The bimetallic strip is made from a copper alloy and an aluminum alloy.

Halbleitervorrichtung mit Wärmeabstrahlplatte und Anheftteil

Eine Halbleitervorrichtung mit: einem Wärmeerzeugungselement (10), das durch einen IGBT bereitgestellt wird; einem Anheftteil (50); ersten und zweiten Wärmeabstrahlplatten (20, 30), welche auf ersten und zweiten Seiten (12, 13) des Wärmeerzeugungselementes (10) entsprechend über das Anheftteil (50) angeordnet sind; einem Wärmeabstrahlblock (40), der zwischen der ersten Wärmeabstrahlplatte (30) und dem Wärmeerzeugungselement (10) über das Anheftteil (50) angeordnet ist; und einem Kunstharzverguss (60), der praktisch die gesamte Vorrichtung eingießt, wobei die ersten und zweiten Wärmeabstrahlplatten (20, 30) in der Lage sind, von dem Wärmeerzeugungselement (10) erzeugte Wärme abzustrahlen; das Wärmeerzeugungselement (10) elektrisch und thermisch mit der ersten Wärmeabstrahlplatte (30) über das Anheftteil (50) und den Wärmeabstrahlblock (40) verbunden ist; das Wärmeerzeugungselement (10) elektrisch und thermisch mit der zweiten Wärmeabstrahlplatte (20) über das Anheftteil (50) verbunden ist ...

Verfahren zum Herstellen von Leitungsverbindungen an elektronischen schaltelementen

Connection between sensor terminal and conductor path applied to glass plate uses conductive connection element ultrasonically welded to conductor path

Connection is provided by electrically conductive connection element (11), e.g. bonding wire, which is ultrasonically welded to conductor path (5) applied to surface of glass plate (1) and which is coupled to sensor terminal (13) mounted on glass plate. Surface (3) of glass plate is ridged at point of connection between conductor path and connection element, ultrasonic welding position lying in furrow between 2 ridges (4). An Independent claim for an application of a sensor terminal connection for a ceramic glass cooking hob surface is also included.

Halbleiterbauelement mit einer verstärkten Substruktur einer Kontaktstelle und zugehöriges Herstellungsverfahren

Halbleiterbauelement mit einer verstärkten Substruktur einer Kontaktstelle, mit - einem Halbleitersubstrat (200), - einer auf dem Halbleitersubstrat ausgebildeten Substruktur (205), - einer dielektrischen Zwischenebenenschicht (208) auf der Substruktur, wobei die dielektrische Zwischenebenenschicht eine darin ausgebildete Kontaktöffnung (210) beinhaltet, und - einem Kontaktstift (214), der in der Kontaktöffnung ausgebildet ist, dadurch gekennzeichnet, dass - die Kontaktöffnung (210) aus einer Mehrzahl von separaten Punkten gebildet ist, die miteinander verbunden werden.

Elektronisches Bauelement und Verfahren zur Herstellung eines elektronischen Bauelements

Es handelt sich um ein elektronisches Bauelement (100a, 100b, 200), insbesondere ein optoelektronisches Bauelement. Das elektronische Bauelement weist ein Substrat (124, 224) mit mindestens einer Halbleiterchip-Kontaktschicht (110a, 110b, 210) auf. Auf der Halbleiterchip-Kontaktschicht (110a, 110b, 210) ist ein Halbleiterchip (102, 202) angeordnet. Zwischen der Halbleiterchip-Kontaktschicht (110a, 110b, 210) und einer dem Substrat (124, 224) zugewandten Kontaktfläche (104, 204) des Halbleiterchips (102, 202) ist eine Poren aufweisende Verbindungsschicht (106, 206) angeordnet.

Druckkontakt-Halbleiterbauelement mit Blindsegment

Jedes der äußersten Segmente (OMSG) und der innersten Segmente (IMSG) wird als Blindsegment verwendet. Eine obere Oberfläche eines vorstehenden Teils (OMPP, IMPP) jedes der äußersten Segmente (OMSG) und der innersten Segmente (IMSG) ist mit einer Isolierschicht (1S + 1P) bedeckt, und zwischen einer oberen Oberfläche der Isolierschicht (1S + 1P) und einer unteren Oberfläche (2BS) einer Katodenentlastungsplatte ist ein Abstand (CL) vorhanden. Alle anderen Segmente (SG), mit Ausnahme der äußersten und der innersten, besitzen einen vorstehenden Teil, auf dem eine Katodenelektrode (1K-AL) ausgebildet ist. Die Dicke (T1) der Katodenelektrode (1K-AL) ist so bemessen, dass eine obere Oberfläche der Katodenelektrode (1K-AL) mit der unteren Oberfläche (2BS) der Katodenentlastungsplatte in Kontakt kommen kann.

Sinterwerkstoff, Sinterverbindung sowie Verfahren zum Herstellen eines Sinterverbindung

Die Erfindung betrifft einen Sinterwerkstoff mit metallischen, mit einer organischen Beschichtung versehenen Strukturpartikeln. Erfindungsgemäß ist vorgesehen, dass nicht-organisch beschichtete, metallische und/oder keramische, beim Sinterprozess nicht ausgasende Hilfspartikel (7) vorgesehen sind. Ferner betrifft die Erfindung eine Sinterverbindung (1) sowie ein Verfahren zum Herstellen einer Sinterverbindung (1).

Direkt auf ungehäusten Bauelementen erzeugte freitragende Kontaktierstrukturen

Direkt auf einem ungehäusten Bauelement wird eine freitragende Kontaktierstruktur erzeugt, indem eine Schicht aus isolierendem Material und eine Schicht aus elektrisch leitendem Material auf das Bauelement sowie einen Träger aufgebracht und vom Träger wieder abgelöst werden.

Elektronisches Bauteil mit Halbleiterchip und Halbleiterwafer mit Kontaktflecken, sowie Verfahren zur Herstellung derselben

Die Erfindung betrifft ein elektronisches Bauteil mit Halbleiterchips (1) und einen Halbleiterwafer mit Kontaktflecken (2) sowie Verfahren zur Herstellung derselben. Dazu weisen die Kontaktflecken (2) auf dem Halbleiterchip (1) Mesastrukturen (6) auf, die derart dimensioniert sind, dass sie an die Größen von Kompressionsköpfen (7) von Bondverbindungen (4) angepasst sind und eine druckverteilende Wirkung auf die Oberseite (10) der Kontaktflecken (2) ausüben.

Halbleiterpackung und -modul, Herstellungsverfahren und elektronisches Bauelement

Die Erfindung bezieht sich auf eine Halbleiterpackung mit gestapelten Halbleiterchips, auf ein Halbleitermodul mit einer derartigen Packung, auf ein Verfahren zur Herstellung der Halbleiterpackung sowie auf ein elektronisches Bauelement, das ein derartiges Modul beinhaltet. Eine Halbleiterpackung gemäß der Erfindung beinhaltet ein Packungssubstrat (200) mit einem Durchkontakt (220s), wenigstens einen Halbleiterchip (100, 120), der auf dem Packungssubstrat gestapelt ist, einen thermischen Grenzflächenfilm (132), der auf dem Halbleiterchip gestapelt ist, eine Packungsabdeckung (300), die in Kontakt mit dem thermischen Grenzflächenfilm und über dem Halbleiterchip positioniert ist, und eine Packungshaftstruktur (310) zwischen dem Durchkontakt und einem Teil der Packungsabdeckung. Verwendung in der Halbleiterbauelementtechnologie.

Vorrichtung zum Anschweissen von duennen Draehten an Halbleiterbauteile mit Hilfe der Pressschweissung (Kalt- und Warmschweissung), mit einer Zufuhr fuer den Draht an einem den Pressdruck auf den Draht uebertragenden Schweisskopf

VERFAHREN ZUR HERSTELLUNG UND ZUM TRANSFERIEREN METALLISCHER TROPFEN

Verfahren und Vorrichtung zur "Flip-Chip" Montage eines elektronischen Bauteils

Verfahren zur Kontaktierung und Verbindung von Halbleiterelementen

Anschlusskoerper fuer Halbleiterbauelemente

HERSTELLUNGSVERFAHREN EINES VERTIKAL INTEGRIERTEN HALBLEITERBAUELEMENTS

Power semiconductor module

The module has a housing and a metal base carrying electrically and thermally insulating substrates with conducting tracks and six adjacent controllable power semiconductor switches (1-6), each attached to one track and electrically connected to it. Load current connections are connected to the housing wall. Bonding areas (35-43) on the underside of the substrate are connected to the switches via bonding wires. At least one additional conducting track (30-32) is provided for each two adjacent switches. Each additional track is connected via bonding wires to one of the bonding surfaces and/or to at least one of the adjacent switches and/or to the additional track of the adjacent two switches. There are at least six load current connections with six bonding surfaces. The conducting tracks of two adjacent switches can be directly connected via bonding wires.

TESTSYSTEM VON INTEGRIERTEN SCHALTUNGEN

Assembly structure of electronic parts prevents the formation of cracks in adhesive substrate

The assembly structure has the electronic part (11), which has first and second electrodes (13), a substrate on which the part is mounted, first and second solder eyes (15) on the substrate and a conducting adhesive (16) between the first electrode and first solder eye and between the second electrode and second solder eye to electrically connect them. Part of the conducting adhesive spreads out from one of the electrodes and solder eyes. An Independent claim is also included for a method of assembling electronic parts.

Cooling for power thyristor - has copper base insert and internal coil spring

Thepower thyristors in flat based metal encapsulation usually have a central integral bolt for mounting and require a critically flat metal surface for efficient cooling. A novel method of keeping thermal resistance to a minimum, yet with reduced overall dimension, is to employ a copper base insert and a internal spring to cause the base to bulge slightly so as to make close contact with the surface on which it is mounted eventually. The flat base (12) of the thyristor consists of thin steel in the form of an equilateral triangle with a hole in its centre in which a copper disc (120) about 3mm thick is soldered. On the disc is mounted the semiconductor assembly. Between this assembly and the cover is the flat coil spring (17) which exerts strong downward pressure.

LICHTEMITTIERENDE HALBLEITERVORRICHTUNG UND VERFAHREN ZU IHRER HERSTELLUNG

Halbleiterelement mit Leistungsverdrahtungsstruktur

Herstellungsverfahren von Öffnungen in einer Passivierungsschicht einer Halbleiterschaltung

ANORDNUNG EINES ELEKTRISCHEN BAUELEMENTS UND EINER ZWEI-PHASEN-KÜHLVORRICHTUNG UND VERFAHREN ZUM HERSTELLEN DER ANORDNUNG

Halbleiteranordnung

Verfahren zur Herstellung eines Halbleiterbauteils mit Durchkontakten zwischen Oberseite und Rückseite

Die Erfindung betrifft ein Verfahren zur Herstellung eines Halbleiterbauteils (1) mit Durchkontakten (2) zwischen Oberseite (3) und Unterseite (4), wobei die Durchkontakte (2) in mindestens einem Randbereich (5) des Halbleiterbauteils (1) angeordnet sind. Die Durchkontakte (2) verbinden elektrisch miteinander Außenkontaktflächen (7, 8) des Halbleiterbauteils (1) auf der Oberseite (3) und Unterseite (4). Eine Kunststoffgehäusemasse (10) umgibt mindestens einen Halbleiterchip (9) mit Kontaktflächen (11) auf der aktiven Oberseite (12) des Halbleiterchips (9). Die Kontaktflächen (11) stehen mit den Durchkontakten (2) über eine Verdrahtungsstruktur (14) elektrisch in Verbindung, wobei die Durchkontakte (2) in mindestens einer vorgefertigten Durchkontaktleiste (15) angeordnet sind, die in dem Randbereich (5) des Halbleiterbauteils (1) positioniert ist.

Spannungsreduzierte Ni-P/Pd-Stapel für Waferoberfläche

GEHAEUSETEIL FUER HALBLEITERBAUELEMENTE

VERFAHREN ZUM HERSTELLEN EINER INTEGRIERTEN HALBLEITERSCHALTUNG

Appliance and method for detecting machining electrode of metals erosion machine based on impedance change as electrode traverses measurement zone

A metal electrode (1) is threaded through an insulated sleeve (5) filled with a transport fluid. Measurement ring electrodes (7,7') enclose a measurement zone (3) supplied by an ac voltage (9), a current sensor being included in the circuit. As the metal electrode traverse the measurement zone the impedance changes and, with the aid of an evaluating circuit (13), it's measurement provides an indication of the position of the electrode tip (15).

HALBLEITERBAUELEMENT

Verfahren zum Verbinden einer Edelmetalloberfläche mit einem Polymer

Verfahren zum Verbinden einer Edelmetalloberfläche eines Halbleitermaterials oder eines Schaltungsträgers mit einem Polymer mit den Schritten:Abscheiden einer Schicht (3) aus 20% bis 40% Gold und 80% bis 60% Silber auf einen Träger,selektives Entfernen des Silbers zur Erzielung einer nanoporösen schwammartigen Goldschicht (4),Auftragen eines flüssigen Polymers, wobei das flüssige Polymer in die nanoporöse schwammartige Goldschicht (4) eindringt und eine dreidimensionale Grenzfläche mit mechanischer Verzahnung zwischen der nanoporösen schwammartigen Goldschicht (4) und dem flüssigen Polymer gebildet wird,Aushärten des flüssigen Polymers zur Erzeugung einer Polymerschicht (5).

HALTER FUER EIN DRUCKKONTAKTIERTES HALBLEITERBAUELEMENT

Electrical assembly comprises cooler structure and electrical component on metal-ceramic substrate having electrical module, where electrical module comprises two metal-ceramic substrates

Electrical assembly comprises cooler structure and an electrical component (6) on a metal-ceramic substrate (4,5) having electrical module. The electrical module comprises two metal-ceramic substrates, where each substrate includes a ceramic layer (7,10), which are provided with partially structured metal plating (9,12). An active cooler (2,3) and an electrical component are also provided between two metal-ceramic substrates, which are thermally connected.

Multilayer contact system comprises a contact metallization deposited on a semiconductor substrate, a barrier layer deposited on the metallization, a bond metallization, and a protective metallization made from composite material

Multilayer contact system comprises a contact metallization deposited on a semiconductor substrate; a barrier layer deposited on the metallization to prevent interdiffusion processes; a bond metallization with a bond pad deposited on the barrier layer; and a protective metallization made from composite material of chromium and precious metal or a chromium-precious metal alloy. Preferred Features: The bond pad is laterally displaced against the vertical contact structure. The region is protected with a passivation outside of the bond pads. The contact metallization is deposited in a contact structure etched into a SiO2 layer.

Halbleitervorrichtung mit Abstrahlungsbauteilen

Semi-conductor device

... 943,860. Semi-conductor devices. SIEMENS-SCHUCKERTWERKE A.G. June 21, 1961 [June 21, 1960], No. 22537/61. Drawings to Specification. Heading H1K. A semi-conductor device 3 is mounted on a carrier plate 2 by a sintered plate 1 whose composition varies from the semi-conductor to the carrier so as to match the coefficients of expansion both of the semi-conductor device and of the carrier plate. When the semi-conductor device is a silicon rectifier the plate may vary from molybdenum/nickel in the ratio 99: 1, through molybdenum/copper 50: 50 to all copper. In other arrangements tungsten nickel and copper may be used or tungsten nickel and silver.

IMPROVEMENTS IN OR RELATING TO METHODS OF MOUNTING ELECTRONIC COMPONENTS ON SHEET-LIKE SUPPORTS

... 1,216,827. Moulding plastic substances. HONEYWELL Inc. 25 April, 1969 [6 May, 1968], No. 21150/69. Heading B5A. [Also in Division H1] An electronic component is mounted on a sheet-like support by forming a perforation in the support, placing one face of the support against a surface composed of a "mould-release" material, inserting the component in the perforation so that its terminals lie against the mould-release surface, filling the remainder of the perforation with a hard-cure plastics material to secure the component and removing the support from the mould release surface when the plastics material has cured. As shown, Fig. 3, a ceramic circuit board 1 is placed on a plate 5 the upper surface 7 of which is coated with a mould-release material such as P.T.F.E., an integrated circuit chip 2 is arranged in a perforation in the circuit board and is retained by a positioning device 6 while the perforation is filled with epoxy resin 3 which is cold or hot cured. The assembly is then removed ...

ATTACHMENT OF CONDUCTORS TO SEMICONDUCTOR PELLETS

SEMICONDUCTOR DEVICE ARRANGEMENTS

... 1403371 Semi-conductor devices MULLARD Ltd 15 Nov 1972 [12 Jan 1972 5 May 1972] 1390/72 and 21029/72 Heading H1K The invention relates to a wiring arrangement, e.g. for a motor vehicle, in which semi-conductor devices are mounted on a flexible service strip 1 (Fig. 1) comprising a plurality of conductors 2, 3 on a flexible insulating strip 4 so that the device terminals are connected to the conductors 2, 3. Each device comprises a semi-conductor element, such as a thyristor or a switching transistor 11 (Fig. 6) including an integrated emitterbase resistor, mounted on a metal carrier 10 which constitutes one terminal, electrodes 15, 16 on the upper surface of the element 11 being contacted by metal foil conductors 21, 22 isolated from the carrier 10 by an insulating backing 23. Various modifications of the foil structure 12 including conductors 21, 22 and and backing 23 are described. Flat contact areas 25, 26 of the conductors 21, 22, and in some cases also of the metal carrier 10, are ...

Coil isolators

Improvements in or relating to electrical couplings to semiconductor elements

... 753,488. Semiconductor devices. STANDARD TELEPHONES & CABLES, Ltd. July 2, 1954 [July 10, 1953], No. 19173/53. Class 37. [Also in Group XXII] A conductor wire 11 is electrically connected to a wafer 1 of semiconductor material such as germanium, by forming the wire in a double coiled spring, inserting the wafer between the two turns and soldering. Fig. 7 shows the arrangement used for the base electrode 13 of a junction transistor which is sealed in a glass envelope 14. The wire may be of phosphor bronze or beryllium copper. Stannous chloride may be used as a flux and pure tin as the solder. The envelope 14 may be filled with resin. Soldering may be affected with a minimum amount of heat by arranging for the solder to fill the coil on the germanium and may be carried out after the process for forming PN junctions in the device.

Semiconductor devices

... 1,104,515. Semi-conductor devices. SIEMENS-SCHUCKERTWERKE A.G. 9 Aug., 1965 [8 Aug., 1964], No. 34085/65. Heading H1K. A semi-conductor body is clamped between pressure members via members the expansion coefficient of which matches that of the body. The members are bonded to the body and a synthetic resin covering extends around the periphery of the member-body assembly on to opposite end faces of the members. In an embodiment the semi-conductor body is of lightlydoped P-type silicon with heavily doped P and N type surface zones. The members are mushroom-shaped and after their attachment, by alloying or soldering, to the surface zones the silicon body is peripherally etched and the resulting recess between the heads of the members filled with alizarin in a synthetic resin. The resin covering, e.g. of epoxy, polyester or silicone which is then applied to form a U-section ring about the device may be keyed to the outer faces of the mushroom heads with the aid of grooves, elevations or depressions ...

Electrical contacts with semiconductor bodies comprising silicon

... 1,106,260. Semi-conductor devices. SIEMENS A.G. 12 Dec., 1966 [11 Dec., 1965], No. 55640/66. Heading H1K. A contact member 8 fixed to a body 4 formed in a semi-conductor material which includes silicon, is made of a material comprising titanium and silicon; e.g. titanium disilicide or a variant thereof of higher silicon content; and has a coating 11 comprising a mixture of silicon and titanium oxides covering the parts of its surface not actually in contact with the body 4. As shown a thermoelectric generator 1 includes two bodies 4, 5, e.g. of a germanium/silicon alloy, respectively doped with boron, gallium or indium, and phosphorus, arsenic or antimony to produce P and N type limbs. The contact member 8 forms a bridge at the hot end of the device, which is heated by a gas, while similar contact members 6, 7 at the liquid-cooled cold end provide external contacts to the device. Foils or grids 12-15 of tungsten or molybdenum may be interposed between the germanium/silicon bodies and the ...

SEALING ELECTRICAL FEEDTHROUGH

Semiconductor Devices and methods of making them

... 1,160,086. Semi-conductor devices. WESTERN ELECTRIC CO., Inc. 30 Sept., 1966 [1 Oct., 1965], No.43728/66. Heading H1K. A device is made by providing a multiapertured insulating layer on a semi-conductor substrate, treating the material exposed through the apertures to provide localized PN junctions, or other rectifying elements and connecting to one of the elements with a wire inserted into the associated aperture. In a typical case the substrate 22 (Fig. 2) is monocrystalline silicon formed in part by epitaxial growth and provided with an oxide layer 23 by oxidation or evaporation. Apertures are formed in the layer by photo-resist techniques, the opposite face of the substrate masked and gold barrier type electrodes 24 electroplated on the silicon within the apertures. The substrate is attached to header 22 in an insulating tube 29 and the gold wire 25 pressed onto the oxide layer, where it finds its way into one of the apertures. In alternative devices the gold electrode is replaced by ...

METHOD FOR BONDING A WIRE TO A METAL LAYER

... 1294770 Soldering HITACHI Ltd 22 Dec 1970 [29 Dec 1969] 60892/70 Heading B3R [Also in Division H1] In connecting a wire to a metal layer on a substrate the wire is guided through the passage of a capillary tube and a portion of the wire extending from the tube is pressed against the layer by the tube, the tube is heated to a temperature not lower than the melting point of the layer but lower than the melting point of the wire whereby the portion of the wire is pressed into the metal layer while metal of the layer is melted and the layer is then cooled to bond the wire to the layer, the tool being then moved away. An electrode 2, Fig. la, printed on a ceramic substrate 1 of a semi-conductor device carries a lead-tin solder layer 3 and a silver wire 5 is guided through the passage of a capillary tube 4. A head 6 is formed on the wire by burning in a hydrogen flame. The tube 4 is heated by resistance means to a temperature not lower than the melting point of the solder 3, e.g. to 300‹ C. and ...

ELECTRICAL PRINTED CIRCUIT BOARD ASSEMBLY AND METHOD OF MANUFACTURE THEREOF

... 1383487 Printed circuits NORTHROP CORP 30 March 1973 [10 April 1972] 15375/73 Heading H1R A printed circuit board assembly comprises an electrically and thermally conducting layer 12, e.g. vacuum deposited on insulant substrate board 11, and photoetched out at 13 to leave insulated electrically conductive lands 14, 15, 16 providing grounds and heat sinks for respective components, and alignment members 18 (Fig. 1). Several layers of polymeric material are laminated on to surface 12 and photoetched to leave cavities 20 to 24 for components and also alignment marker holes to form an alignment plate 25 (Fig. 2). Components 35 (which may be integrated circuit chips) are placed in the cavities in positional alignment with the markers and are bonded to the layer 12 so as to protrude above the alignment plate, and selected components, e.g. those in cavities 22, 23 have distinct ground and heat sink connections 15, 16 (Fig. 5). A conventional etched printed circuit board 40 (Fig. 7), with photoetched ...

Substrate for integrated circuit devices including multi-layer glass core and methods of making the same

Copper wire for bonding a semiconductor device

The present invention eliminates the problems associated with the use of oxygen-free copper and other high-purity copper materials as bonding wires. At least one rare earth element, or at least one element selected from the group consisting of Mg, Ca, Ti, Zr, Hf, Li, Na, K, Rb and Cs, or the combination of at least one rare earth element and at least one elemented selected from the above-specified group is incorporated in high-purity copper as a refining component in an amount of 0.1-100 ppm on a weight basis, and the high-purity copper is subsequently refined by zone melting. The very fine wire drawn from the so refined high-purity copper has the advantage that it can be employed in high-speed ball bonding of a semiconductor chip with a minimum chance of damaging the bonding pad on the chip by the ball forming at the tip of the wire.

Method for manufacturing semiconductor device

An amorphous Ni-P layer (10) which cancels crystallinity of a base metal layer is formed on the base metal layer, such as an FET electrode, by electroless gilding and then an electrolytic Au gilding layer (9) is formed on the amorphous Ni-P layer. Thus, luster nonuniformity of the electrolytic Au gilding layer formed on the base metal layer, such as the FET electrode, is avoided so that a position of an electrode pad can be mechanically detected in an easy manner, during auto- bonding, and its appearance is improved. Processing of MMICs is thus improved. ...

Semiconductor fabrication with contact processing for wrap-around flange interface

A method and apparatus for forming an under bump metallization structure

Methods and apparatuses are disclosed in which a refractory layer is formed during rapid thermal processing wherein ambient hydrogen is used in the thermal processing chamber. Rapid thermal processing may occur at a temperature approximately in the range of 350 {C to approximately 550 {C.

An electronic component package with posts on the active surface

A method and apparatus for an electronic component package using wafer level processing is provided. Posts (1935) are formed on the active side of the substrate (1910) of an electronic component. A conductive layer (1945) leads the contact areas of the electronic component to the tops of the posts (1935). The conductive layer (1945) on the top of the posts (1935) acting as leads, attaching to traces on a printed circuit board.

Active energy ray-curable pressure-sensitive adhesive for re-release and dicing die-bonding film

Provided is an active energy ray-curable pressure-sensitive adhesive for re-release, which has a small influence on an environment or a human body, can be easily handled, can largely change its pressure-sensitive adhesiveness before and after irradiation with an active energy ray, and can express high pressure-sensitive adhesiveness before the irradiation with the active energy ray and express high releasability after the irradiation with the active energy ray. The active energy ray-curable pressure-sensitive adhesive for re-release includes an active energy ray-curable polymer (P), in which the polymer (P) includes one of a polymer obtained by causing a carboxyl group-containing polymer (P3) and an oxazoline group-containing monomer (m3) to react with each other, and a polymer obtained by causing an oxazoline group-containing polymer (P4) and a carboxyl group-containing monomer (m2) to react with each other.

Method for manufacture of integrated circuit package system with protected conductive layers for pads

A method for manufacture of an integrated circuit package system includes: providing an integrated circuit die having a contact pad; forming a protection cover over the contact pad; forming a passivation layer having a first opening over the protection cover with the first opening exposing the protection cover; developing a conductive layer over the passivation layer; forming a pad opening in the protection cover for exposing the contact pad having the conductive layer partially removed; and an interconnect directly on the contact pad and only adjacent to the protection cover and the passivation layer.

Method for Reducing Chip Warpage

A method of forming an integrated circuit structure including providing a wafer comprising a front surface and a back surface, wherein the wafer comprises a chip; forming an opening extending from the back surface into the chip; filling an organic material in the opening, wherein substantially no portion of the organic material is outside of the opening and on the back surface of the wafer; and baking the organic material to cause a contraction of the organic material.

Microelectronic packages with dual or multiple-etched flip-chip connectors

A packaged microelectronic element includes a microelectronic element having a front surface and a plurality of first solid metal posts extending away from the front surface. A substrate has a major surface and a plurality of conductive elements exposed at the major surface and joined to the first solid metal posts. In particular examples, the conductive elements can be bond pads or can be second posts having top surfaces and edge surfaces extending at substantial angles away therefrom. Each first solid metal post includes a base region adjacent the microelectronic element and a tip region remote from the microelectronic element, the base region and tip region having respective concave circumferential surfaces. Each first solid metal post has a horizontal dimension which is a first function of vertical location in the base region and which is a second function of vertical location in the tip region.

Power semiconductor module and fabrication method

A power semiconductor module includes: an interconnect layer including an electrical conductor patterned on a dielectric layer, the electrical conductor including a power coupling portion having a thickness sufficient to carry power currents and a control coupling portion having a thickness thinner than that of the power coupling portion; and a semiconductor power device physically coupled to the interconnect layer and electrically coupled to the power coupling portion of the electrical conductor.

Interconnections for flip-chip using lead-free solders and having reaction barrier layers

An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting composition including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components. With a two-layer ball-limiting composition comprising an adhesion/reaction barrier layer, wherein the adhesion/reaction barrier layer serves both as an adhesion layer and a reaction barrier layer, the adhesion/reaction barrier layer can be comprised of a material selected from the group consisting of Zr and ZrN

Stacked microelectronic packages having at least two stacked microelectronic elements adjacent one another

A microelectronic assembly includes first and second microelectronic elements. Each of the microelectronic elements has oppositely-facing first and second surfaces and edges bounding the surfaces. The first microelectronic element is disposed on the second microelectronic element with the second surface of the first microelectronic element facing toward the first surface of the second microelectronic element. The first microelectronic element preferably extends beyond at least one edge of the second microelectronic element and the second microelectronic element preferably extends beyond at least one edge of the first microelectronic element. A first edge of the first microelectronic element has a length that is smaller than a first edge of the second microelectronic element. A second edge of the first microelectronic element has a length that is greater than the second edge of the second microelectronic element.

Film for flip chip type semiconductor back surface, dicing tape-integrated film for semiconductor back surface, process for producing semiconductor device, and flip chip type semiconductor device

The present invention relates to a film for flip chip type semiconductor back surface to be formed on a back surface of a semiconductor element flip chip-connected onto an adherend, in which the film for flip chip type semiconductor back surface before thermal curing has, at the thermal curing thereof, a volume contraction ratio within a range of 23° C. to 165° C. of 100 ppm/° C. to 400 ppm/° C.

Semiconductor device and method of manufacturing the same

A preferred aim of the invention is to provide technique for improving reliability of semiconductor devices when using a low-dielectric-constant film having a lower dielectric constant than a silicon oxide film to a part of an interlayer insulating film. More specifically, to achieve the preferred aim, an interlayer insulating film IL 1 forming a first fine layer is formed of a middle-Young's-modulus film, and thus it is possible to separate an integrated high-Young's-modulus layer (a semiconductor substrate 1 S and a contact interlayer insulating film CIL) and an interlayer insulating film (a low-Young's-modulus film; a low-dielectric-constant film) IL 2 forming a second fine layer not to let them directly contact with each other, and stress can be diverged. As a result, film exfoliation of the interlayer insulating film IL 2 formed of a low-Young's-modulus film can be prevented and thus reliability of semiconductor devices can be improved.

Semiconductor device

There is provided a semiconductor device with which stress can be prevented from locally concentrating on an external connecting terminal on a post and thus damages of the external connecting terminal can be prevented. The semiconductor device includes a semiconductor chip, a sealing resin layer stacked on a surface of the semiconductor chip, and the post which penetrates the sealing resin layer in a stacking direction of the semiconductor chip and the sealing resin layer, protrudes from the sealing resin layer, and has a periphery of the protruding portion opposedly in contact with a surface of the sealing resin layer in the stacking direction.

Stitch bump stacking design for overall package size reduction for multiple stack

A method for die stacking is disclosed. In one embodiment a first die is formed overlying a substrate. A first wire is bonded to the first die and to a bond finger of the substrate, wherein the first wire is bonded to the bond finger with a first bond. A first stitch bump is formed overlying the first stitch bond, wherein the first stitch bump is formed from a molten ball of conductive material. A second die is formed overlying the first die. A second wire is bonded to the second die and to the first stitch bump, wherein the second wire is bonded to the first stitch bump with a second bond.

Conductive connection structure with stress reduction arrangement for a semiconductor device, and related fabrication method

A semiconductor device disclosed herein includes a conductive connection structure having a stepped profile that serves as a stress relief feature. The conductive connection structure includes a stress buffer arrangement for a contact pad. The stress buffer arrangement has a stepped via that terminates at the contact pad, and the stepped via has a plurality of inwardly sloped and concentric sections in a stacked orientation. The connection structure also includes underbump metallization overlying at least a portion of the contact pad and lining the stepped via, and a conductive connection element coupled to the underbump metallization. The conductive connection element fills the lined recess.

Control device of semiconductor device

A control device of a semiconductor device is provided. The control device of a semiconductor device is capable of reducing both ON resistance and feedback capacitance in a hollow-gate type planar MOSFET to which a second gate electrode is provided or a trench MOSFET to which a second gate electrode is provided. In the control device controlling driving of a hollow-gate type planar MOSFET to which a second gate electrode is provided or a trench MOSFET to which a second gate electrode is provided, a signal of tuning ON or OFF is outputted to a gate electrode in a state of outputting a signal of turning OFF to the second gate electrode.

Semiconductor device and manufacturing method of the same

A semiconductor chip is mounted on a heat sink disposed inside a through-hole of a wiring board, electrodes of the semiconductor chip and connecting terminals of the wiring board are connected by bonding wires, a sealing resin is formed to cover the semiconductor chip and the bonding wires, and solder balls are formed on the lower surface of the wiring board, thereby constituting the semiconductor device. The heat sink is thicker than the wiring board. The heat sink has a protruded portion protruding to outside from the side surface of the heat sink, the protruded portion is located on the upper surface of the wiring board outside the through-hole, and the lower surface of the protruded portion contacts to the upper surface of the wiring board. When the semiconductor device is manufactured, the heat sink is inserted from the upper surface side of the wiring board.

Semiconductor chip with redundant thru-silicon-vias

A semiconductor chip with conductive vias and a method of manufacturing the same are disclosed. The method includes forming a first plurality of conductive vias in a layer of a first semiconductor chip. The first plurality of conductive vias includes first ends and second ends. A first conductor pad is formed in ohmic contact with the first ends of the first plurality of conductive vias.

Semiconductor device having pad structure with stress buffer layer

A semiconductor device has a pad structure with a ring-shaped stress buffer layer between a metal pad and an under-bump metallization (UBM) layer. The stress buffer layer is formed of a dielectric layer with a dielectric constant less than 3.5, a polymer layer, or an aluminum layer. The stress buffer layer is a circular ring, a square ring, an octagonal ring, or any other geometric ring.

Multi-function and shielded 3d interconnects

A microelectronic unit includes a semiconductor element consisting essentially of semiconductor material and having a front surface, a rear surface, a plurality of active semiconductor devices adjacent the front surface, a plurality of conductive pads exposed at the front surface, and an opening extending through the semiconductor element. At least one of the conductive pads can at least partially overlie the opening and can be electrically connected with at least one of the active semiconductor devices. The microelectronic unit can also include a first conductive element exposed at the rear surface for connection with an external component, the first conductive element extending through the opening and electrically connected with the at least one conductive pad, and a second conductive element extending through the opening and insulated from the first conductive element. The at least one conductive pad can overlie a peripheral edge of the second conductive element.

Microsprings Partially Embedded In A Laminate Structure And Methods For Producing Same

At least one microspring has applied thereover a laminate structure to provide: mechanical protection during handling and wafer processing, a spring spacer layer, strengthening of the anchor between spring and substrate, provision of a gap stop during spring deflection, and moisture and contaminant protection. A fully-formed laminate structure may be applied over the microspring structure or a partly-formed laminate structure may be applied over the microspring structure then cured or hardened. The tip portion of the microspring may protrude through the laminate structure and be exposed for contact or may be buried within the contact structure. The laminate structure may remain in place in the final microspring structure or be removed in whole or in part. The laminate structure may be photolithographically patternable material, patterned and etched to remove some or all of the structure, forming for example additional structural elements such as a gap stop for the microspring.

Method of making a light emitting device having a molded encapsulant

Disclosed herein is a method of making a light emitting device having an LED die and a molded encapsulant made by polymerizing at least two polymerizable compositions. The method includes: (a) providing an LED package having an LED die disposed in a reflecting cup, the reflecting cup filled with a first polymerizable composition such that the LED die is encapsulated; (b) providing a mold having a cavity filled with a second polymerizable composition; (c) contacting the first and second polymerizable compositions; (d) polymerizing the first and second polymerizable compositions to form first and second polymerized compositions, respectively, wherein the first and second polymerized compositions are bonded together; and (e) optionally separating the mold from the second polymerized composition. Light emitting devices prepared according to the method are also described.

Semiconductor structure and method for making same

One or more embodiments relate to a method for making a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece; forming a separation layer over the barrier layer; forming a conductive layer over the separation layer; and wet etching the conductive layer.

Semiconductor assembly and semiconductor package including a solder channel

Semiconductor packages connecting a semiconductor chip to an external device by bumps are provided. The semiconductor packages may include a connection pad on a semiconductor chip, a connecting bump on and configured to be electrically connected to the connection pad and a supporting bump on the semiconductor chip and configured to be electrically isolated from the connection pad. The connection bump may include a first pillar and a first solder ball and the supporting bump may include a second pillar and a second solder ball. The semiconductor packages may further include a solder channel in the second pillar configured to allow a portion of the second solder ball to extend into the solder channel along a predetermined direction.

Microelectronic assemblies having compliancy and methods therefor

A microelectronic assembly is disclosed that includes a semiconductor wafer with contacts, compliant bumps of dielectric material overlying the first surface of the semiconductor wafer, and a dielectric layer overlying the first surface of the semiconductor wafer and edges of the compliant bumps. The compliant bumps have planar top surfaces which are accessible through the dielectric layer. Conductive traces may be electrically connected with contacts and extend therefrom to overlie the planar top surfaces of the compliant bumps. Conductive elements may overlie the planar top surfaces in contact with the conductive traces.

Composite alloy bonding wire and manufacturing method thereof

A manufacturing method for a composite alloy bonding wire and products thereof. A primary material of Ag is melted in a vacuum melting furnace, and then a secondary metal material of Pd is added into the vacuum melting furnace and is co-melted with the primary material to obtain an Ag—Pd alloy solution. The obtained Ag—Pd alloy solution is drawn to obtain an Ag—Pd alloy wire. The Ag—Pd alloy wire is then drawn to obtain an Ag—Pd alloy bonding wire with a predetermined diameter.

Bond pad for wafer and package for cmos imager

An electronic packaging having at least one bond pad positioned on a chip for effectuating through-wafer connections to an integrated circuit. The electronic package is equipped with an edge seal between the bond pad region and an active circuit region, and includes a crack stop, which is adapted to protect the arrangement from the entry of deleterious moisture and combination into the active regions of the chip containing the bond pads.

Semiconductor package device with a heat dissipation structure and the packaging method thereof

The present invention provide a heat dissipation structure on the active surface of the die to increase the performance of the heat conduction in longitude direction of the semiconductor package device, so that the heat dissipating performance can be improved when the semiconductor package device is associated with the exterior heat dissipation mechanism.

Laser ashing of polyimide for semiconductor manufacturing

A method for laser ashing of polyimide for a semiconductor manufacturing process using a structure, the structure comprising a supporting material attached to a semiconductor chip by a polyimide glue, includes releasing the supporting material from the polyimide glue, such that the polyimide glue remains on the semiconductor chip; and ashing the polyimide glue on the semiconductor chip using an ablating laser.

Contact pad

The present disclosure relates to forming multi-layered contact pads for a semiconductor device, wherein the various layers of the contact pad are formed using one or more thin-film deposition processes, such as an evaporation process. Each contact pad includes an adhesion layer, which is formed over the device structure for the semiconductor device; a titanium nitride (TiN) barrier layer, which is formed over the adhesion layer; and an overlay layer, which is formed over the barrier layer. At least the titanium nitride (TiN) barrier layer is formed using an evaporation process.

Method for manufacturing a semiconductor device having a refractory metal containing film

A semiconductor device and a method for manufacturing the same of the present invention in which the semiconductor device is provided with a fuse structure or an electrode pad structure, suppress the copper blowing-out from a copper containing metal film. The semiconductor device comprises a silicon substrate, SiO 2 film provided on the silicon substrate, copper films embedded in the SiO 2 film, TiN films covering an upper face of a boundary region between an upper face of copper films and the copper films, and the SiO 2 film, and SiON films covering an upper face of the TiN films.

Connecting and Bonding Adjacent Layers with Nanostructures

An apparatus, comprising two conductive surfaces or layers and a nanostructure assembly bonded to the two conductive surfaces or layers to create electrical or thermal connections between the two conductive surfaces or layers, and a method of making same.

Package carrier

A package carrier including a substrate, at least an under bump metallurgic (UBM) layer and at least a conductive bump is provided. The substrate has a conductive structure and at least a pad connected with the conductive structure. A region of the pad connected with the conductive structure is a signal source region. The UBM layer is disposed on the pad and includes a first conductive pattern and a second conductive pattern. A side wall of the second conductive pattern is directly connected to a side wall of the first conductive pattern, and the second conductive pattern is disposed close to the signal source region. The conductivity of the second conductive pattern is smaller than the conductivity of the first conductive pattern. The conductive bump is disposed on the UBM layer.

Structures and methods for improving solder bump connections in semiconductor devices

Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The structure includes a trench formed in a dielectric layer which has at least a portion thereof devoid of a fluorine boundary layer. The structure further includes a copper wire in the trench having at least a bottom portion thereof in contact with the non-fluoride boundary layer of the trench. A lead free solder bump is in electrical contact with the copper wire.

Mechanisms for resistivity measurement of bump structures

The embodiments described above provide mechanisms for bump resistivity measurement. By using designated bumps on one or more corners of dies, the resistivity of bumps may be measured without damaging devices and without a customized probing card. In addition, bump resistivity may be collected across the entire wafer. The collected resistivity data may be used to monitor the stability and/or health of processes used to form bumps and their underlying layers.

Semiconductor component, semiconductor wafer component, manufacturing method of semiconductor component, and manufacturing method of joining structure

A semiconductor component of the present invention includes a semiconductor element and a joining layer formed on one surface of the semiconductor element and consisting of a joining material containing Bi as an essential ingredient, and projecting sections are formed on a surface of the joining layer on a side opposite to a surface in contact with the semiconductor element. By joining the semiconductor component to an electrode arranged so as to face the joining layer, the generation of a void can be suppressed.

Chip Pad Resistant to Antenna Effect and Method

A chip pad structure of an integrated circuit (IC) and the method of forming are disclosed. The chip pad comprises a main pad portion and a ring pad portion. During a charging process involved in forming the chip pad structure, electrical connections from the gate electrodes of MOS transistors in the IC substrate generally are made only to the ring pad portion that has an antenna-to-gate area ratio substantially below a predetermined antenna design rule ratio, and thus is resistant or immune to antenna effect. The main pad portion and the ring pad portion are coupled together through metal bridges formed in an upper interconnect metal layer or in the top conductive pad layer. The chip pad may be used as probe pads on a parametric testline or bonding pads on an IC.

Semiconductor Device and Method of Forming Integrated Passive Device Over Semiconductor Die with Conductive Bridge and Fan-Out Redistribution Layer

A semiconductor device has a first semiconductor die. A first inductor is formed over the first semiconductor die. A second inductor is formed over the first inductor and aligned with the first inductor. An insulating layer is formed over the first semiconductor die and the first and second inductors. A conductive bridge is formed over the insulating layer and electrically connected between the second inductor and the first semiconductor die. In one embodiment, the semiconductor device has a second semiconductor die and a conductive layer is formed between the first and second semiconductor die. In another embodiment, a capacitor is formed over the first semiconductor die. In another embodiment, the insulating layer has a first thickness over a footprint of the first semiconductor die and a second thickness less than the first thickness outside the footprint of the first semiconductor die.

Increasing Dielectric Strength by Optimizing Dummy Metal Distribution

A method includes providing a wafer representation including a metal layer and a plurality of bump pads over the metal layer, wherein the metal layer includes directly-under-bump-pad regions. A solid metal pattern is inserted into the metal layer, wherein the solid metal pattern includes first parts in the directly-under-bump-pad regions and second parts outside the directly-under-bump-pad regions. Portions of the second parts of the solid metal pattern are removed, wherein substantially no portions of the first parts of the solid metal pattern are removed. The remaining portions of the solid metal pattern not removed during the step of removing form dummy metal patterns. The dummy metal patterns and the plurality of bump pads are implemented in a semiconductor wafer.

Semiconductor Package with Embedded Die

A semiconductor package having an embedded die and solid vertical interconnections, such as stud bump interconnections, for increased integration in the direction of the z-axis (i.e., in a direction normal to the circuit side of the die). The semiconductor package can include a die mounted in a face-up configuration (similar to a wire bond package) or in a face-down or flip chip configuration.

MEMS and Protection Structure Thereof

A protection structure of a pad is provided. The pad is disposed in a dielectric layer on a semiconductor substrate and the pad includes a connection region and a peripheral region which encompasses the connection region. The protection structure includes at least a barrier, an insulation layer and a mask layer. The barrier is disposed in the dielectric layer in the peripheral region. The insulation layer is disposed on the dielectric layer. The mask layer is disposed on the dielectric layer and covers the insulation layer and the mask layer includes an opening to expose the connection region of the pad.

Semiconductor Device and Method of Forming Narrow Interconnect Sites on Substrate with Elongated Mask Openings

A semiconductor device has a semiconductor die with a plurality of bumps formed over a surface of the semiconductor die. A plurality of conductive traces is formed over a surface of the substrate with interconnect sites. A masking layer is formed over the surface of the substrate. The masking layer has a plurality of parallel elongated openings each exposing at least two of the conductive traces and permitting a flow of bump material along a length of the plurality of conductive traces within the plurality of elongated openings while preventing the flow of bump material past a boundary of the plurality of elongated openings. One of the conductive traces passes beneath at least two of the elongated openings. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surface of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate.

Device mounting board and method of manufacturing the same, semiconductor module, and mobile device

A device mounting board includes: an insulating resin layer; a wiring layer formed on one of the principal surfaces of the insulating resin layer; a protection layer covering the insulating resin layer and the wiring layer; a protruding electrode electrically connected to the wiring layer, the protruding electrode protruding from the wiring layer toward the insulating resin layer and penetrating through the insulating resin layer; a wiring-layer-side convex portion protruding from the wiring layer toward the insulating resin layer and having the top end thereof located inside the insulating resin layer; and a resin-layer-side convex portion protruding from the protection layer toward the insulating resin layer and having the top end thereof located inside the insulating resin layer.

Semiconductor device and method for manufacturing semiconductor device

A semiconductor device includes: a support base material, and a semiconductor element bonded to the support base material with a binder, the binder including: a porous metal material that contacts the support base material and the semiconductor element, and a solder that is filled in at least one part of pores of the porous metal material.

Heat radiation material, electronic device and method of manufacturing electronic device

The electronic device includes a heat generator 54, a heat radiator 58, and a heat radiation material 56 disposed between the heat generator 54 and the heat radiator 58 and including a plurality of linear structures 12 of carbon atoms and a filling layer 14 formed of a thermoplastic resin and disposed between the plurality of linear structures 12.

Formation of liner and barrier for tungsten as gate electrode and as contact plug to reduce resistance and enhance device performance

The invention provides a method of forming a film stack on a substrate, comprising performing a silicon containing gas soak process to form a silicon containing layer over the substrate, reacting with the silicon containing layer to form a tungsten silicide layer on the substrate, depositing a tungsten nitride layer on the substrate, subjecting the substrate to a nitridation treatment using active nitrogen species from a remote plasma, and depositing a conductive bulk layer directly on the tungsten nitride layer.

Protection of reactive metal surfaces of semiconductor devices during shipping by providing an additional protection layer

When forming complex metallization systems on the basis of copper, the very last metallization layer may receive contact regions on the basis of copper, the surface of which may be passivated on the basis of a dedicated protection layer, which may thus allow the patterning of the passivation layer stack prior to shipping the device to a remote manufacturing site. Hence, the protected contact surface may be efficiently re-exposed in the remote manufacturing site on the basis of an efficient non-masked wet chemical etch process.

Contact Metal for Hybridization and Related Methods

A contact structure for interconnecting a first substrate to an indium interconnect structure on a second substrate. The contact structure comprises a diffusive layer and a non-oxidizing layer, with a thickness of less than approximately 150 nm, positioned on the diffusive layer for alignment with the indium interconnect.

Circuit module and manufacturing method for the same

A circuit module and a manufacturing method for the same, reduce a possibility that a defect area where an electrically conductive resin is not coated may occur in a shield layer. A mother board is prepared. A plurality of electronic components are mounted on a principal surface of the mother board. An insulator layer is arranged so as to cover the principal surface of the mother board and the electronic components. The insulator layer is cut such that grooves and projections are formed in and on the principal surface of the insulator layer and the insulator layer has a predetermined thickness H. An electrically conductive resin is coated on the principal surface of the insulator layer to form a shield layer. The mother board including the insulator layer and the shield layer both formed thereon is divided to obtain a plurality of circuit modules.

Light-Emitting Element and Light-Emitting Device

Provided are a light-emitting element capable of reducing power consumption by increasing its light extraction efficiency and a light-emitting device using the light-emitting element. A light-emitting element includes a composite material, which contains an organic compound having a high hole-transport property and an electron acceptor and in which the spin density measured by an electron spin resonance (ESR) method is less than or equal to 1×10 19 spins/cm 3 , the spin density is less than or equal to 3×10 19 spins/cm 3 when the molar ratio of the electron acceptor to the organic compound is greater than or equal to 1, or the spin density is less than or equal to 5×10 19 spins/cm 3 when the molar ratio is greater than or equal to 2.

Methods and structures for forming integrated semiconductor structures

The invention provides methods and structures for fabricating a semiconductor structure and particularly for forming a semiconductor structure with improved planarity for achieving a bonded semiconductor structure comprising a processed semiconductor structure and a number of bonded semiconductor layers. Methods for forming semiconductor structures include forming a dielectric layer over a non-planar surface of a processed semiconductor structure, planarizing a surface of the dielectric layer on a side thereof opposite the processed semiconductor structure, and attaching a semiconductor structure to the planarized surface of the dielectric layer. Semiconductor structures include a dielectric layer overlaying a non-planar surface of a processed semiconductor structure, and a masking layer overlaying the dielectric layer on a side thereof opposite the processed semiconductor structure. The masking layer includes a plurality of mask openings over conductive regions of the non-planar surface of the processed semiconductor structure.

Method for Producing a Metal Layer on a Substrate and Device

A method produces a metal layer on a semiconductor substrate. A metal layer is produced on the semiconductor substrate by depositing metal particles. The metal particles include cores made of a first metal material and shells surrounding the cores. The shells are made of a second metal material that is resistant to oxidation.

Apparatus for restricting moisture ingress

Apparatus and methods to protect circuitry from moisture ingress, e.g., using a metallic structure as part of a moisture ingress barrier.

Method for producing reconstituted wafers and method for producing semiconductor devices

In order to provide a method for producing semiconductor devices that can use the highly productive W to W method, and achieve a high yield, a method for producing semiconductor devices comprises a step (S 401 ) in which a reconstituted wafer is prepared by replacing defective chips with non-defective chips, a step (S 403 ) in which the reconstituted wafer and the base wafer are connected to one another by laminating, a step (S 406 ) in which through-electrodes are formed in the reconstituted wafer, and a step (S 409 ) in which a separate reconstituted wafer is laminated onto and connected to the reconstituted wafer having through-electrodes.

Through wafer vias and method of making same

A method of forming and structure for through wafer vias and signal transmission lines formed of through wafer vias. The method of forming through wafer vias includes forming an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via through a semiconductor substrate having a top surface and an opposite bottom surface, each through wafer via of the array of through wafer vias extending from the top surface of the substrate to the bottom surface of the substrate.

Semiconductor device and method for manufacturing same

A semiconductor device includes an interlayer insulating film, a wiring formed on the interlayer insulating film so as to protrude therefrom and made of a material having copper as a main component, and a passivation film formed so as to cover the wiring. The passivation film is made of a laminated film in which a first nitride film, an intermediate film, and a second nitride film are laminated in that order from the wiring side. The intermediate film is made of an insulating material (for example, an oxide) differing from those of the first and second nitride films.

Semiconductor Constructions

Some embodiments include semiconductor processing methods in which a copper barrier is formed to be laterally offset from a copper component, and in which nickel is formed to extend across both the barrier and the component. The barrier may extend around an entire lateral periphery of the component, and may be spaced from the component by an intervening ring of electrically insulative material. The copper component may be a bond pad or an interconnect between two levels of metal layers. Some embodiments include semiconductor constructions in which nickel extends across a copper component, a copper barrier is laterally offset from the copper component, and an insulative material is between the copper barrier and the copper component.

Semiconductor element-embedded substrate, and method of manufacturing the substrate

A semiconductor element-embedded substrate includes a semiconductor element; a chip component; a peripheral insulating layer covering at least the outer circumferential side surfaces thereof; an upper surface-side wiring line provided on the upper surface side of the substrate; and a lower surface-side wiring line provided on the lower surface side of the substrate. The built-in semiconductor element includes a terminal on the upper surface side thereof, and this terminal is electrically connected to the upper surface-side wiring line. The built-in chip component includes an upper surface-side terminal electrically connected to the upper surface-side wiring line; a lower surface-side terminal electrically connected to the lower surface-side wiring line; and a through-chip via penetrating through the chip component to connect the upper surface-side terminal and the lower surface-side terminal.

Thermal enhanced package

A method of manufacturing an integrated circuit package. The method includes attaching a first surface of a semiconductor die to a thermally and/or electrically conductive substrate, forming a plurality of die connectors on a second surface of the semiconductor die, and encapsulating the semiconductor die and the plurality of die connectors in an encapsulant material. The method also includes removing a portion of the encapsulant material to expose one or more of the plurality of die connectors, thereby forming a routing surface. The method further includes forming a plurality of conductive traces on the routing surface. Each of the plurality of conductive traces is characterized by a first portion in electrical communication with one of the plurality of die connectors and a second portion in electrical communication with a package connector.

Semiconductor Device with Solder Bump Formed on High Topography Plated Cu Pads

A semiconductor device has a first conductive layer formed over a substrate. A first insulating layer is formed over the substrate and first conductive layer. A second conductive layer is formed over the first conductive layer and first insulating layer. A second insulating layer is formed over the first insulating layer and second conductive layer. The second insulating layer has a sidewall between a surface of the second insulating material and surface of the second conductive layer. A protective layer is formed over the second insulating layer and surface of the second conductive layer. The protective layer follows a contour of the surface and sidewall of the second insulating layer and second conductive layer. A bump is formed over the surface of the second conductive layer and a portion of the protective layer adjacent to the second insulating layer. The protective layer protects the second insulating layer.

Solder Bump with Inner Core Pillar in Semiconductor Package

A flip chip semiconductor package has a substrate with a plurality of active devices. A contact pad is formed on the substrate in electrical contact with the plurality of active devices. A passivation layer, second barrier layer, and adhesion layer are formed between the substrate and an intermediate conductive layer. The intermediate conductive layer is in electrical contact with the contact pad. A copper inner core pillar is formed by plating over the intermediate conductive layer. The inner core pillar has a rectangular, cylindrical, toroidal, or hollow cylinder form factor. A solder bump is formed around the inner core pillar by plating solder material and reflowing the solder material to form the solder bump. A first barrier layer and wetting layer are formed between the inner core pillar and solder bump. The solder bump is in electrical contact with the intermediate conductive layer.

Three dimensional semiconductor assembly board with bump/flange supporting board, coreless build-up circuitry and built-in electronic device

A semiconductor assembly board includes a supporting board, a coreless build-up circuitry and a built-in electronic device. The supporting board includes a bump, a flange and a via hole in the bump. The built-in electronic device extends into the via hole and is electrically connected to the build-up circuitry. The build-up circuitry extends from the flange and the built-in electronic device and provides signal routing for the built-in electronic device. The supporting board provides mechanical support, ground/power plane and heat sink for the coreless build-up circuitry.

Electronic component and method for producing same

This electronic component is provided with an inorganic substrate, a conductor film formed on a surface of the substrate, and bonding wires bonded to a part of said conductor film, and wire bonding sections are formed on at least a part of the electronic component. The part of the conductor film at least forming the aforementioned wire bonding sections contains an Ag-based metal formed of Ag or an alloy having Ag as the main constituent and a metal oxide which coats said Ag-based metal and which has, as a constituent element, any of the elements selected from the group consisting of Al, Zr, Ti, Y, Ca, Mg, and Zn. The coating quantity of the metal oxide is a quantity corresponding to 0.02 to 0.1 parts by mass relative to 100 parts by mass of the aforementioned Ag-based metal.

Semiconductor Device and Method of Forming Interposer Frame Electrically Connected to Embedded Semiconductor Die

A semiconductor device has an interposer frame mounted over a carrier. A semiconductor die has an active surface and bumps formed over the active surface. The semiconductor die can be mounted within a die opening of the interposer frame or over the interposer frame. Stacked semiconductor die can also be mounted within the die opening of the interposer frame or over the interposer frame. Bond wires or bumps are formed between the semiconductor die and interposer frame. An encapsulant is deposited over the interposer frame and semiconductor die. An interconnect structure is formed over the encapsulant and bumps of the first semiconductor die. An electronic component, such as a discrete passive device, semiconductor die, or stacked semiconductor die, is mounted over the semiconductor die and interposer frame. The electronic component has an I/O count less than an I/O count of the semiconductor die.

Method to form solder deposits and non-melting bump structures on substrates

Described is a method of forming a metal or metal alloy layer onto a substrate comprising the following steps i) provide a substrate including a permanent resin layer on top of at least one contact area and a temporary resin layer on top of the permanent resin layer, ii) contact the entire substrate area including the at least one contact area with a solution suitable to provide a conductive layer on the substrate surface and i) electroplate a metal or metal alloy layer onto the conductive layer.

Semiconductor Device and Method of Forming Interposer Frame Over Semiconductor Die to Provide Vertical Interconnect

A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame. The interposer is mounted over the carrier and first die with the conductive pillars disposed around the die. A cavity can be formed in the interposer frame to contain a portion of the first die. An encapsulant is deposited through the opening in the interposer frame over the carrier and first die. Alternatively, the encapsulant is deposited over the carrier and first die and the interposer frame is pressed against the encapsulant. Excess encapsulant exits through the opening in the interposer frame. The carrier is removed. An interconnect structure is formed over the encapsulant and first die. A second semiconductor die can be mounted over the first die or over the interposer frame.

Connecting material, method for manufacturing connecting material and semiconductor device

In a connecting material of the present invention, a Zn series alloy layer is formed on an outermost surface of an Al series alloy layer. In particular, in the connecting material, an Al content of the Al series alloy layer is 99 to 100 wt.% or a Zn content of the Zn series alloy layer is 90 to 100 wt.%. By using this connecting material, the formation of an Al oxide film on the surface of the connecting material at the time of the connection can be suppressed, and preferable wetness that cannot be obtained with the Zn—Al alloy can be obtained. Further, a high connection reliability can be achieved when an Al series alloy layer is left after the connection, since the soft Al thereof functions as a stress buffer material.

Electronic Device and a Method for Fabricating an Electronic Device

The electronic device includes a carrier, a semiconductor substrate attached to the carrier, and a layer system disposed between the semiconductor substrate and the carrier. The layer system includes an electrical contact layer disposed on the semiconductor substrate. A functional layer is disposed on the electrical contact layer. An adhesion layer is disposed on the functional layer. A solder layer is disposed between the adhesion layer and the carrier.

Semiconductor device and method for production of semiconductor device

A semiconductor device with a connection pad in a substrate, the connection pad having an exposed surface made of a metallic material that diffuses less readily into a dielectric layer than does a metal of a wiring layer connected thereto.

Semiconductor device

The reliability of a semiconductor device is improved. A package of a semiconductor device internally includes a first semiconductor chip and a second semiconductor chip in which power MOS•FETs are formed and a third semiconductor chip in which a control circuit controlling the first and second semiconductor chips is formed. The first to third semiconductor chips are mounted on die pads respectively. Source electrode bonding pads of the first semiconductor chip on a high side are electrically connected with a first die pad of the die pads via a metal plate. On a top surface of the die pad 7 D 2 , a plated layer formed in a region where the second semiconductor chip is mounted, and another plated layer formed in a region where the metal plate is joined are provided and the plated layers are separated each other with a region where no plated layer is formed in between.

Anti-reflection structures for cmos image sensors

Optical structures having an array of protuberances between two layers having different refractive indices are provided. The array of protuberances has vertical and lateral dimensions less than the wavelength range of lights detectable by a photodiode of a CMOS image sensor. The array of protuberances provides high transmission of light with little reflection. The array of protuberances may be provided over a photodiode, in a back-end-of-line interconnect structure, over a lens for a photodiode, on a backside of a photodiode, or on a window of a chip package.

Semiconductor Packaging Structure and Method

A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections.

Semiconductor device and method of manufacturing the same

A semiconductor device includes a first bump that is located over a surface of a semiconductor element, and is formed on a first bump formation face distanced from a back surface of the semiconductor element at a first distance, and a second bump that is located over the surface of the semiconductor element, and is formed on a second bump formation face distanced from the back surface of the semiconductor element at a second distance being longer than the first distance, the second bump having a diameter larger than a diameter of the first bump.

Design system for semiconductor device, method for manufacturing semiconductor device, semiconductor device and method for bonding substrates

The terminals that oppose each other when substrates are bonded are designed to be reliably joined. Comprised in a semiconductor device design system are a numerical value acquiring part, which acquires the respective numerical values of a plurality of calculation parameters, a junction estimating part, which, in the case in which a plurality of substrates has been pressed at a prescribed pressure so that the bump front end faces come into contact, estimates whether or not the respective mutually opposing bumps will be joined based on the respective numerical values of the calculation parameters acquired by the numerical value acquiring part, and a change processing part, which, in the case in which it has been estimated by the junction estimating part that any of the bumps will not be joined, gives a warning or performs processing so as to change the numerical value of at least one calculation parameter among the plurality of calculation parameters.

Package-in-Package Using Through-Hole Via Die on Saw Streets

A semiconductor device includes a first die having top, bottom, and peripheral surfaces. A bond pad is formed over the top surface. An organic material is connected to the first die and disposed around the peripheral surface. A via hole is formed in the organic material. A metal trace connects the via hole to the bond pad. A conductive material is deposited in the via hole. A redistribution layer (RDL) has an interconnection pad disposed over the top surface of the first die.

Starting material for a sintered bond and process for producing the sintered bond

The invention relates to a starter material for a sintering compound, said starter material comprising first particles of at least one metal having a first coating which is applied to the first particles and consists of an organic material, and second particles which contain an organic metal compound and/or a precious metal oxide, the organic metal compound and/or the precious metal oxide being converted during heat treatment of the starter material into the fundamental elemental metal and/or precious metal. The invention is characterized in that the second particles have a core of at least one metal and a second coating which is applied to the core and contains the organic metal compound and/or precious metal oxide. Furthermore, the first coating contains a reducing agent by means of which the organic metal compound and/or the precious metal oxide is/are reduced to the elemental metal and/or precious metal at a temperature below the sintering temperature of the elemental metal and/or precious metal.

Semiconductor device bonding with stress relief connection pads

An inventive semiconductor device includes: a semiconductor chip; an internal pad provided on a surface of the semiconductor chip for electrical connection; a surface protective film covering the surface of the semiconductor chip and having a pad opening from which the internal pad is exposed; a stress relief layer provided on the surface protective film and having an opening portion through which the internal pad exposed from the pad opening is exposed; a connection pad including an anchor buried in the pad opening and the opening portion and connected to the internal pad, and a projection provided integrally with the anchor as projecting on the stress relief layer, the projection having a width greater than an opening width of the opening portion; and a metal ball provided for external electrical connection as covering the projection of the connection pad.

Bonded processed semiconductor structures and carriers

Methods of fabricating semiconductor structures include implanting atom species into a carrier die or wafer to form a weakened region within the carrier die or wafer, and bonding the carrier die or wafer to a semiconductor structure. The semiconductor structure may be processed while using the carrier die or wafer to handle the semiconductor structure. The semiconductor structure may be bonded to another semiconductor structure, and the carrier die or wafer may be divided along the weakened region therein. Bonded semiconductor structures are fabricated using such methods.

Semiconductor Package and Method of Manufacturing the Same

A method of forming a semiconductor package having a large capacity and a reduced or minimized volume includes: attaching a semiconductor substrate on a support substrate using an adhesive layer, wherein the semiconductor substrate includes a plurality of first semiconductor chips and a chip cutting region, wherein first and second ones of the plurality of first semiconductor chips are separated each other by the chip cutting region, and the semiconductor substrate includes a first surface on which an active area is formed and a second surface opposite to the first surface; forming a first cutting groove having a first kerf width, between the first and second ones of the plurality of first semiconductor chips, so that the semiconductor substrate is separated into a plurality of first semiconductor chips; attaching a plurality of second semiconductor chips corresponding to the first semiconductor chips, respectively, to the plurality of first semiconductor chips; forming a molding layer so as to fill the first cutting groove; and forming a second cutting groove having a second kerf width that is less than the first kerf width, in the molding layer, so as to separate the molding layer into individual molding layers covering one of the plurality of first semiconductor chips and corresponding one of the plurality of second semiconductor chips.

Method to realize flux free indium bumping

A method to realize flux free indium bumping process includes several steps including substrate metallization, contact holes opening, underbump metallization (UBM) layer thickening, indium bump preparation and Ag layer coating. The method can be used in the occasion for some special application, e.g., the packaging of the photoelectric chip (with optical lens), MEMS and biological detection chip, where the usage of flux is prohibited.

Starting material for a sintered bond and process for producing the sintered bond

The invention relates to a starter material for a sintering compound, said starter material comprising particles which at least proportionally contain an organic metal compound and/or a precious metal oxide, the organic metal compound and/or the precious metal oxide being converted during heat treatment of the starter material into the elemental metal and/or precious metal. The invention is characterized in that the particles have a coating containing a reducing agent by means of which the organic metal compound and/or precious metal oxide is reduced to the elemental metal and/or precious metal at a temperature below the sintering temperature of the elemental metal and/or precious metal.

Semiconductor integrated circuit device

In semiconductor integrated circuit devices for vehicle use, an aluminum pad on a semiconductor chip and an external device are coupled to each other by wire bonding using a gold wire for the convenience of mounting. Such a semiconductor integrated circuit device, however, causes a connection failure due to the interaction between aluminum and gold in use for a long time at a relatively high temperature (about 150 degrees C.). A semiconductor integrated circuit device can include a semiconductor chip as a part of the device, an electrolytic gold plated surface film (gold-based metal plated film) provided over an aluminum-based bonding pad on a semiconductor chip via a barrier metal film, and a gold bonding wire (gold-based bonding wire) for interconnection between the plated surface film and an external lead provided over a wiring board (wiring substrate).

Low-temperature flip chip die attach

A mechanism for electrically coupling a semiconductor device die to a semiconductor device package substrate that avoids introduction of excessive temperature induced stresses to the semiconductor device die interconnect is provided. In one embodiment, the semiconductor device die is mechanically attached to the package substrate (or another semiconductor device die) at room temperature through the use of a plug-in socket or wedge connection having corresponding mating features formed on the die and substrate. The mechanical interconnect features can be formed on the die and substrate interconnects using an electroplating process. The surfaces of the semiconductor device die and package substrate can then be coupled using an underfill material. A low-temperature solid state bonding process can then be used to diffuse the materials forming the plug and socket features in order to form the electrical connection.

Semiconductor package with single sided substrate design and manufacturing methods thereof

A multilayer substrate includes a first outer conductive patterned layer, a first insulating layer exposing a portion of the first outer conductive patterned layer to define a first set of pads, a second outer conductive patterned layer, and a second insulating layer exposing a portion of the second outer conductive patterned layer to define a second set of pads. The multilayer substrate further includes inner layers each with an inner conductive patterned layer, multiple inner conductive posts formed adjacent to the inner conductive patterned layer, and an inner dielectric layer, where the inner conductive patterned layer and the inner conductive posts are embedded in the inner dielectric layer, and a top surface of each of the inner conductive posts is exposed from the inner dielectric layer.

Method for fabricating a through wire interconnect (twi) on a semiconductor substrate having a bonded connection and an encapsulating polymer layer

A method for fabricating a through wire interconnect for a semiconductor substrate having a substrate contact includes the steps of: forming a via through the semiconductor substrate from a first side to a second side thereof; placing a wire in the via having a first end with a bonded connection to the substrate contact and a second end proximate to the second side; forming a first contact on the wire proximate to the first side; forming a second contact on the second end of the wire; and forming a polymer layer on the first side at least partially encapsulating the wire while leaving the first contact exposed.

Semiconductor Device and Method of Dual-Molding Die Formed on Opposite Sides of Build-Up Interconnect Structure

A semiconductor device has a first interconnect structure. A first semiconductor die has an active surface oriented towards and mounted to a first surface of the first interconnect structure. A first encapsulant is deposited over the first interconnect structure and first semiconductor die. A second semiconductor die has an active surface oriented towards and mounted to a second surface of the first interconnect structure opposite the first surface. A plurality of first conductive pillars is formed over the second surface of the first interconnect structure and around the second semiconductor die. A second encapsulant is deposited over the second semiconductor die and around the plurality of first conductive pillars. A second interconnect structure including a conductive layer and bumps are formed over the second encapsulant and electrically connect to the plurality of first conductive pillars and the first and second semiconductor die.

Semiconductor device including bottom surface wiring and manufacturing method of the semiconductor device

Disclosed herein is a semiconductor device including a semiconductor substrate, a wiring layer formed above the semiconductor substrate, a through-hole electrode extending from the bottom surface of the semiconductor substrate to the wiring layer, a bottom surface wiring provided, at the bottom surface of the semiconductor substrate such that the bottom surface wiring is connected to the through-hole electrode, and an external terminal connected to the bottom surface wiring. The bottom surface wiring has a greater film thickness than a film thickness of the through-hole electrode at least a portion of the bottom surface wiring including a connection part between the bottom surface wiring and the external terminal.

Solder interconnect with non-wettable sidewall pillars and methods of manufacture

A solder interconnect structure is provided with non-wettable sidewalls and methods of manufacturing the same. The method includes forming a nickel or nickel alloy pillar on an underlying surface. The method further includes modifying the sidewall of the nickel or nickel alloy pillar to prevent solder wetting on the sidewall.

Package process and package structure

A package process is provided. An adhesive layer is disposed on a carrier board and then plural first semiconductor devices are disposed on the adhesive layer. A first molding compound formed on the carrier board covers the sidewalls of the first semiconductor devices and fills the gaps between the first semiconductor devices so as to form a chip array board constructed by the first semiconductor devices and the first molding compound. Next, plural second semiconductor devices are flip-chip bonded to the first semiconductor devices respectively. Then, a second molding compound formed on the chip array board at least covers the sidewalls of the second semiconductor devices and fills the gaps between the second semiconductor devices. Subsequently, the chip array board is separated from the adhesive layer. Then, the first and the second molding compound are cut along the gaps between the second semiconductor devices.

Compliant interconnects in wafers

A microelectronic assembly includes a substrate and an electrically conductive element. The substrate can have a CTE less than 10 ppm/° C., a major surface having a recess not extending through the substrate, and a material having a modulus of elasticity less than 10 GPa disposed within the recess. The electrically conductive element can include a joining portion overlying the recess and extending from an anchor portion supported by the substrate. The joining portion can be at least partially exposed at the major surface for connection to a component external to the microelectronic unit.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME

In a semiconductor device in which a plurality of semiconductor chips are stacked, performance is enhanced without deteriorating productivity. The semiconductor device has a plurality of elements, an interlayer insulating film, a pad, and a bump electrode electrically connected with the pad sequentially formed on a main surface of a silicon substrate and has a back-surface electrode formed on a back surface of the silicon substrate and electrically connected with the bump electrode. The bump electrode has a protruding portion penetrating through the pad and protruding toward the silicon substrate side. The back-surface electrode is formed so as to reach the protruding portion of the bump electrode from the back surface side of the silicon substrate toward the main surface side and to cover the inside of a back-surface electrode hole portion which does not reach the pad, so that the back-surface electrode is electrically connected with the bump electrode. 1. A semiconductor device comprising:a semiconductor substrate having a main surface and a back surface positioned on an opposite side to the main surface;a first insulating film formed on the main surface of the semiconductor substrate;a first hole formed in the first insulating film;a second hole formed in the back surface of the semiconductor substrate;an electrode having a first portion which is formed at least in and entirely fills the first hole and a protruding portion which extends from the semiconductor substrate; anda conductive film conformally formed in the second hole and electrically connected to a bottom surface of the electrode.2. The semiconductor device according to claim 1 , wherein a protective insulating film is formed at a boundary portion between the electrode and the semiconductor substrate so that the electrode and the semiconductor substrate are electrically insulated from each other.3. The semiconductor device according to claim 1 , further comprising a second insulating film formed at a ...

CHIP PACKAGE

An embedded die package comprising a die having die contract pads in a passivation layer, the die contact pads being coupled to a first side of a feature layer by an adhesive layer, a layer of pillars extending from a second side of the feature layer, the die, feature layer and the layer of pillars being encapsulated by a dielectric material. 1. An embedded die package comprising a die having die contract pads in a passivation layer , the die contact pads being coupled to a first side of a feature layer by an adhesion/barrier layer , and a layer of pillars extending from a second side of the feature layer , the die , feature layer and the layer of pillars being encapsulated by a dielectric material.2. The embedded die package of wherein the die contact pads comprise aluminum.3. The embedded die package of wherein the passivation layer comprises either PI or SiN.4. The embedded die package of wherein the adhesion/barrier layer is selected from the group consisting of Ti/Cu claim 1 , Ti/W/Cu claim 1 , Ti/Ta/Cu claim 1 , Cr/Cu and Ni/Cr.5. The embedded die package of wherein the adhesion/barrier layer has a thickness in the range of from 0.05 microns to 1 microns.6. The embedded die package of wherein the feature layer comprises copper.7. The embedded die package of wherein the feature layer has a thickness in the range of from 1 micron to 25 micron.8. The embedded die package of wherein the layer of pillars has a height in the range of 15 microns to 50 microns.9. The embedded die package of wherein the feature layer has a fan-out form.10. The embedded die package of wherein the feature layer has a fan-in form.11. The embedded die package of wherein said chip and said layer of pillars are embedded in different polymer dielectric materials.12. The embedded die package of wherein said layer of pillars comprises a grid array of pads that serve as contacts for coupling the die to a substrate.13. The embedded die package of wherein the substrate is a PCB.14. The embedded ...

CHIP PACKAGE

An embedded die package and method of manufacture, the die package comprising a die having I/O contact pads in a passivation layer wherein the die contact pads are coupled to a first side of a feature layer by an adhesion/barrier layer, and a layer of pillars extends from a second side of the feature layer, the die, feature layer and the layer of pillars being encapsulated by a dielectric material and wherein the feature layer comprises routing lines that are individually drawn by laser exposure of photoresist under guidance of an optical imaging system for good alignment with both the I/O contact pads of the die and with the subsequently to be deposited pillars that are positioned with respect to the package edges. 1. An embedded die package comprising a die having I/O contact pads in a passivation layer , the die contact pads being coupled to a first side of a feature layer by an adhesion/barrier layer , and a layer of pillars extending from a second side of the feature layer , the die , feature layer and the layer of pillars being encapsulated by a dielectric material wherein the feature layer comprises routing lines that are individually drawn for good alignment with the I/O contact pads of the die and with pillars.2. The embedded die package of wherein the die is misaligned with sides and edges of the package by more than acceptable tolerances for subsequent reliable deposition of routing lines by stencil exposure of a photoresist.3. The embedded die package of wherein sides of the die are angled to sides of the package by an angle of several degrees.4. The embedded die package of wherein one pair of sides of the die are displaced by 3 to 8 microns from a symmetrical position with regards to one pair of parallel sides of the package.5. The embedded die package of wherein each of two pairs of sides of the die are displaced by 3 to 8 microns from a symmetrical position with regards to each of two pairs pair of parallel sides of the package.6. The embedded die ...

PROCESSING TECHNIQUES FOR SILICON-BASED TRANSIENT DEVICES

Provided are methods of making a transient electronic device by fabricating one or more inorganic semiconductor components, one or more metallic conductor components or one or more inorganic semiconductor components and one or more metallic conductor components supported by a mother substrate. The components may independently comprise a selectively transformable material and, optionally, further have a preselected transience profile. The components are transfer printed, thereby decoupling the component fabrication step from additional processing to provide desired device functionality and transient properties. A substrate layer is provided on top of the components and used to facilitate handling, processing, and/or device functionality. 1. A method of making a transient electronic device comprising the steps of:fabricating one or more inorganic semiconductor components, one or more metallic conductor components or one or more inorganic semiconductor components and one or more metallic conductor components supported by a mother substrate; wherein the one or more inorganic semiconductor components or one or more metallic conductor components independently comprise a selectively transformable material and have a preselected transience profile;providing a handle substrate having a receiving surface; wherein the receiving surface supports a release layer;transfer printing the one or more inorganic semiconductor components, one or more metallic conductor components or one or more inorganic semiconductor components and one or more metallic conductor components from the mother substrate to the release layer supported by the handle substrate;removing the release layer on said handle substrate;providing a substrate layer on top of the one or more inorganic semiconductor components, one or more metallic conductor components or one or more inorganic semiconductor components and one or more metallic conductor components;releasing the substrate layer and the one or more inorganic ...

PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME

A package structure and method for forming the same are provided. The package structure includes a substrate and a package layer formed over the substrate. The package structure further includes an alignment structure formed over the package layer, and the alignment structure includes a first alignment mark formed in a trench, and the trench has a step-shaped structure. 1. A package structure , comprising:a substrate;a package layer formed over the substrate; andan alignment structure formed over the package layer, wherein the alignment structure comprises a first alignment mark formed in a trench, and the trench has a step-shaped structure.2. The package structure as claimed in claim 1 , further comprising:a plurality of semiconductor dies formed over the substrate; anda package layer adjacent to the semiconductor dies.3. The package structure as claimed in claim 1 , further comprising:a scribe line between adjacent semiconductor dies, wherein the alignment structure is formed over the scribe line.4. The package structure as claimed in claim 1 , wherein each of the semiconductor dies comprises a plurality of sub-dies with a gap region between the sub-dies claim 1 , and the alignment structure is formed over the gap region.5. The package structure as claimed in claim 1 , wherein the trench has an ellipse-shaped or circle-shaped top-view profile.6. The package structure as claimed in claim 1 , further comprising:a first dielectric layer formed over the package layer, wherein the first dielectric layer comprises a first opening with an ellipse-shaped or circle-shaped top-view profile.7. The package structure as claimed in claim 1 , wherein the alignment structure comprises a second alignment mark formed over the package layer claim 1 , and the first alignment mark and the second alignment mark are in the same level.8. The package structure as claimed in claim 1 , further comprising:a first dielectric layer formed over the package layer, wherein the second alignment ...

SEMICONDUCTOR DEVICE

A semiconductor device according to the present invention includes a semiconductor chip, an electrode pad made of a metal material containing aluminum and formed on a top surface of the semiconductor chip, an electrode lead disposed at a periphery of the semiconductor chip, a bonding wire having a linearly-extending main body portion and having a pad bond portion and a lead bond portion formed at respective ends of the main body portion and respectively bonded to the electrode pad and the electrode lead, and a resin package sealing the semiconductor chip, the electrode lead, and the bonding wire, the bonding wire is made of copper, and the entire electrode pad and the entire pad bond portion are integrally covered by a water-impermeable film. 1. A semiconductor device comprising:an interlayer insulating film formed on a semiconductor substrate;an uppermost layer wiring made of copper and formed on the interlayer insulating film;a passivation film formed on the uppermost layer wiring and selectively exposing a top surface of the uppermost layer wiring as an electrode pad; anda bonding wire made of copper and bonded directly to the electrode pad.2. The semiconductor device according to claim 1 , wherein the bonding wire is stitch bonded directly to the electrode pad.3. The semiconductor device according to claim 1 , wherein the bonding wire is bonded to the electrode pad by a stud bump.4. The semiconductor device according to claim 1 , wherein a thickness of the electrode pad is no less than 10 μm.5. The semiconductor device according to claim 1 , wherein a thickness of the electrode pad is 10 μm to 15 μm.6. The semiconductor device according to claim 1 , further comprising a lower layer wiring covered with the interlayer insulating film claim 1 , whereinthe uppermost layer wiring includes a protrusion extending inside the interlayer insulating film,the lower layer wiring is electrically connected to the electrode pad via a pathway including the protrusion.7. The ...

3D BONDED SEMICONDUCTOR STRUCTURE WITH AN EMBEDDED CAPACITOR

A first semiconductor structure including a first bonding oxide layer having a first metallic structure embedded therein and a second semiconductor structure including a second bonding oxide layer having second metallic structure embedded therein are provided. A high-k dielectric material is formed on a surface of the first metallic structure. A nitride surface treatment process is performed to provide a nitrided surface layer to each structure. The nitrided surface layer includes nitridized oxide regions located in an upper portion of the bonding oxide layers and either a nitridized high-k dielectric material located in at least an upper portion of the high k dielectric material or a nitridized metallic region located in an upper portion of the second metallic structure. The nitrogen within the nitridized metallic region is then selectively removed to restore the upper portion of the second metallic structure to its original composition. Bonding is then performed. 1. A method of forming a three-dimensional (3D) bonded semiconductor structure , said method comprising:providing a first semiconductor structure including a first wafer, a first interconnect structure, and a first bonding oxide layer containing at least one first metallic structure embedded therein, and a second semiconductor structure including a second wafer, a second interconnect structure, and a second bonding oxide layer containing at least one second metallic structure embedded therein;forming a high-k dielectric material on a surface of said at least one first metallic structure;performing a nitridation process to provide a first nitrided surface layer comprising first nitridized oxide regions in an upper portion of said first bonding oxide layer and a nitridized high-k dielectric material in at least an upper portion of said high-k dielectric material, and to provide a second nitrided surface layer comprising second nitridized oxide regions in an upper portion of said second bonding oxide layer ...

Method for Producing Electronic Device With Multi-Layer Contact

A method for producing an electric device with a multi-layer contact is disclosed. In an embodiment, a method includes providing a carrier, the carrier having a metallic layer disposed on its surface, providing a semiconductor substrate, forming a layer stack on the semiconductor substrate and attaching the layer stack of the semiconductor substrate to the metallic layer of the carrier so that an intermetallic phase is formed between the metallic layer and the solder layer. 1. A method for fabricating an electronic device , the method comprising:providing a carrier, the carrier having a metallic layer disposed on its surface, wherein the metallic layer comprises Ni or NiNiP;providing a semiconductor substrate; directly depositing an electrical contact layer on the semiconductor substrate, the electrical contact layer being a single elemental Al layer;', 'directly depositing a functional layer on the electrical contact layer, the functional layer comprising Ti or an alloy containing Ti;', 'directly depositing an adhesion layer on the functional layer, the adhesion layer comprising Ni or NiV;', 'directly depositing a solder layer on the adhesion layer, the solder layer being a single element Sn layer or a noble metal free alloy layer containing Sn; and', 'directly depositing a protective layer on the solder layer, the protection layer being an Ag layer; and, 'forming a layer stack on the semiconductor substrate bybonding the layer stack of the semiconductor substrate to the metallic layer of the carrier so that an intermetallic phase is formed between the metallic layer and the solder layer, the intermetallic phase comprising a binary alloy of Ni/Sn.2. The method according to claim 1 , wherein the electrical contact layer has a thickness in a range from 100 nm to 1 μm.3.The method according to claim 2 , wherein the functional layer has a thickness in a range from 50 nm to 200 nm.4382. The method according to claim claim 2 , wherein the solder layer has a thickness in ...

Fan-Out Stacked System in Package (SIP) and the Methods of Making the Same

An embodiment package includes a first fan-out tier having a first device die, a molding compound extending along sidewalls of the first device die, and a through intervia (TIV) extending through the molding compound. One or more first fan-out redistribution layers (RDLs) are disposed over the first fan-out tier and bonded to the first device die. A second fan-out tier having a second device die is disposed over the one or more first fan-out RDLs. The one or more first fan-out RDLs electrically connects the first and second device dies. The TIV electrically connects the one or more first fan-out RDLs to one or more second fan-out RDLs. The package further includes a plurality of external connectors at least partially disposed in the one or more second fan-out RDLs. The plurality of external connectors are further disposed on conductive features in the one or more second fan-out RDLs. 1. A package comprising: a first device die;', 'a first molding compound extending along sidewalls of the first device die; and', 'a first through intervia (TIV) extending through the first molding compound;, 'a first fan-out tier comprisingone or more first fan-out redistribution layers (RDLs) over the first fan-out tier and bonded to the first device die;a second fan-out tier over the one or more first fan-out RDLs, wherein the second fan-out tier comprises a second device die bonded to the one or more first fan-out RDLs, wherein the one or more first fan-out RDLs electrically connects the first device die to the second device die;one or more second fan-out RDLs on an opposing side of the first fan-out tier from the one or more first fan-out RDLs, wherein the first TIV electrically connects the one or more first fan-out RDLs to the one or more second fan-out RDLs; anda plurality of external connectors at least partially disposed in the one or more second fan-out RDLs, wherein the plurality of external connectors are further disposed on conductive features in the one or more second fan ...

THERMAL PADS BETWEEN STACKED SEMICONDUCTOR DIES AND ASSOCIATED SYSTEMS AND METHODS

Systems and methods are described for improved heat dissipation of the stacked semiconductor dies by including metallic thermal pads between the dies in the stack. In one embodiment, the thermal pads may be in direct contact with the semiconductor dies. Heat dissipation of the semiconductor die stack can be improved by a relatively high thermal conductivity of the thermal pads that directly contact the adjacent silicon dies in the stack without the intervening layers of the low thermal conductivity materials (e.g., passivation materials). In some embodiments, the manufacturing yield of the stack can be improved by having generally coplanar top surfaces of the thermal pads and under-bump metallization (UBM) structures. 1. A semiconductor die , comprising:a semiconductor substrate having a first surface and a second surface angled relative to the first surface, wherein the second surface at least partially defines an opening in the first surface;an interconnect extending at least partially through the semiconductor substrate, wherein the interconnect includes an end portion projecting from the opening, and wherein the end portion has a sidewall exposed from the semiconductor substrate in the opening;a metallization structure extending at least partially around the sidewall of the end portion of the interconnect, wherein the metallization structure is laterally spaced apart from the second surface of the semiconductor substrate; anda thermal pad on the first surface of the semiconductor substrate, wherein the thermal pad and the metallization structure project to generally the same vertical height above the first surface of the semiconductor substrate.2. The semiconductor die of claim 1 , further comprising a passivation material at least partially on the first surface of the semiconductor substrate.3. The semiconductor die of claim 1 , further comprising a passivation material in the opening between the metallization structure and the semiconductor substrate.4. The ...

Package Systems Having Interposers

A package system includes a first integrated circuit disposed over an interposer. The interposer includes at least one molding compound layer including a plurality of electrical connection structures through the at least one molding compound layer. A first interconnect structure is disposed over a first surface of the at least one molding compound layer and electrically coupled with the plurality of electrical connection structures. The first integrated circuit is electrically coupled with the first interconnect structure. 1. A method comprising:providing a first substrate;forming a first interconnect layer on the first substrate;attaching the first interconnect layer to a second substrate;removing the first substrate;forming electrical connections on the first interconnect layer;forming a molding compound over the first interconnect layer, the molding compound encircling each of the electrical connections;forming a second interconnect layer on the molding compound; andremoving the second substrate.2. The method of claim 1 , wherein the forming the electrical connections on the first interconnect layer comprises:forming a patterned layer over the first interconnect layer, the patterned layer having openings;forming a conductive material in the openings; andremoving the patterned layer.3. The method of claim 2 , further comprising forming a conductive seed layer over the first interconnect layer prior to the forming the patterned layer claim 2 , and further comprising removing exposed portions of the conductive seed layer after the removing the patterned layer.4. The method of claim 1 , further comprising attaching a semiconductor substrate between adjacent ones of the electrical connections prior to the forming the molding compound.5. The method of claim 4 , wherein the molding compound extends over the semiconductor substrate.6. The method of claim 1 , further comprising forming external electrical connectors on the first interconnect layer prior to attaching to ...

CONDUCTIVE STRUCTURE AND METHOD FOR FORMING THE SAME

A conductive structure for a semiconductor chip and a method for forming the conductive structure are provided. The semiconductor chip comprises a semiconductor substrate, a pad, a passivation layer and a patterned insulating layer. The patterned insulating layer is disposed on the passivation layer and partially and directly covers the first opening of the pad to expose a second opening. The conductive structure comprises an under bump metal (UBM) layer and a conductive bump. The UBM layer is disposed in the second opening defined by the patterned insulating layer and is electrically connected to the pad. The conductive bump is disposed on the UBM layer and is electrically connected to the UBM layer. The upper surface of the conductive bump is greater than the upper surface of the patterned insulating layer, while the portion of the conductive bump disposed in the second opening is covered by the UBM layer. 1. A method for forming a conductive structure comprising:forming a patterned insulating layer on a passivation layer of a semiconductor chip, the patterned insulating layer partially and directly covering a first opening of a pad to expose a second opening, and the first opening being larger than the second opening, wherein the semiconductor chip comprises a semiconductor substrate, a pad and a passivation layer, the pad is disposed on the semiconductor substrate, the passivation layer is disposed on the semiconductor substrate and the pad to expose the first opening;forming an under bump metal (UBM) layer covering the patterned insulating layer and the second opening to electrically connect to the pad; andforming a conductive bump disposed in the second opening to electrically connect to the under bump metal layer, wherein the under bump metal layer covers a periphery of the conductive bump; andremoving the under bump metal layer disposed in an external region layer outside the second opening, wherein an upper surface of the conductive bump is higher than an ...

SEMICONDUCTOR DEVICES HAVING METAL BUMPS WITH FLANGE

A semiconductor device having a terminal site () including a flat pad () of a first metal covered by a layer () of dielectric material, the layer over the pad parallel to the pad and having a window of a first diameter () exposing the surface of the underlying pad. The terminal site further has a patch-shaped film () of a second metal covering the surface of the exposed first metal and the surface of an annulus of the dielectric layer framing the window, the film patch having a second diameter () greater than the first diameter; and a bump () of a third metal adhering to the film, the bump having a third diameter () smaller than the second diameter, whereby the film protrudes like a flange from the bump. 18-. (canceled)9. A method for fabricating a semiconductor chip comprising:providing a semiconductor wafer having a plurality of devices, each device having a plurality of terminal sites;forming a bond pad over each of the plurality of terminal sites, the bond pad being flat and made of a first metal adhering to semiconductor wafer;depositing a layer of dielectric material across the semiconductor wafer covering the bond pads of all terminal sites;patterning the layer of dielectric material over each bond pad to open a window of a first diameter to each bond pad, the window exposing the surface of the underlying bond pad; sputtering a metallic seed layer of a refractory metal over the semiconductor wafer;', 'subsequently patterning the metallic seed layer to form patches of the refractory metal over the window and the surface of the bond pad at each terminal site, the patches having a second diameter greater than the first diameter; and', 'using the patches as a seed material, plating to form the flange on the bond pad at each terminal site, the flange being a film of a second metal adhering to the first metal as well as to the layer of dielectric material; and, 'forming a flange for bumps on each bond pad; comprisingforming a bump of a third metal on each flange, ...