SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
In the embodiment below the semiconductor device relates to, in particular connecting plurality of circuit pattern including a via (Via) relates to a semiconductor device. Probe card a nitride layer for character-istics that are illuminated from the light illumination section one is terminals of the tape carrier package. These probes card can be, and meter reading pad of a device communication between the reading part, same of which carries a substrate portion (or support), electrical connected a PCB part (or connection) and wheel brake unit by pneumatic pressure from includes reinforcement reinforcement for a. The meter reading configurations of probe card 2 dimensional (2D) and 3 dimensional (3D) method in number may be small. 2D (Tip) is lying in the case of tip is capable of to have a predetermined thickness, space converter (Space Transformer) adheres to sanitary condition while ensuring the tip used for massaging a when is adhesion. 3D the probe using process in the case of space while direction is adhered transducer. In the embodiment the, semiconductor device including probe card in the worst condition, and number are associated with to method bath. Semiconductor device in the embodiment according to the circuit pattern a via pad connecting upper and lower each of outputs a relay driving signal. projecting shape. Wherein, via pad and sensor is mounted on the support substrate a via hole, via including pad can be mixture by the addition of an initiator. At this time, at least two stacked vias pad or more vias can be structure (Stacked Via). At this time, via pad shape projecting top of a via pad material formed at upper portion of a thickness of the insulation layer can be by. At this time, a curved surface operable shape projecting top of pad via the first to third locking States, upper projecting shape can be different shape projecting lower edge. In the embodiment according to the via holes or stack semiconductor device using via structure in which all of the semiconductor device is applicable to any type of items, in one example using ceramic substrate can be applied to the probe card. According to such in the embodiment, upper projecting shape projecting lower edge shape via of chip for using the plurality of circuit patterns by deficiency, a ripeness of kimchi, such a circuit pattern are formed in different layers between the second lines adjacent to each other connectivity, stacked vias by the use of, increase the area of wiring of each layer can be enhance an integration degree. Figure 1 shows a semiconductor device in the embodiment according to one also concerns a cross-sectional to.. 1 also also shown in Figure 2 shows a via pad account an end surface due concerns a.. 1 door has 3f also to 3a also shown in semiconductor device number bath process. concerns a cross-sectional drawing. Figure 4 shows a 1 also also projecting top of pad via shown in for the shape. concerns a examples of a plane. In the embodiment according to Figure 5 one probe card. indicating a the configuration. Hereinafter, in the embodiment below to with an rapidly and to reduce a memory reference to drawing.. However in the embodiment below number by one or limited not. In addition, each drawing number to the same references the same it became at the time of exhibits and member. According to semiconductor device has is provided at the top in the embodiment are having the shape protruded and and has a shape having a positioned on a via of chip for using the plurality of thin film product is formed in layers a plurality of circuit patterns by deficiency, a ripeness of kimchi, such a circuit pattern are formed in different layers the sensor is mounted to the connectivity between a separation and eccentricity.. Wherein, at least two or more vias pads are provided to interconnect the stacked vias by the use of, increase the area of wiring of each layer can be enhance an integration degree. Probe card of a device communication between the reading part can be, and meter reading pad, a support is supplying, electrical connected a connection and reinforcement reinforcement for a wheel brake unit by pneumatic pressure from may comprise an. Wherein, the for inspecting probe card of semiconductor device pad pitch (pad pitch) is becoming to the outside are a filed oxidation layer thickness of tip 2D fastening thereby. must have respect for the continuously. In addition, meter reading the substrate the PCB for number pad for bonding directly upon ceramic substrate as well as for controlling single - or multi-layer insulating layer for example, polyimide (PI; polyimide) layer electrical wiring goes on, most to the entire surface of the wafer which is allowed to proceed for a small number pad for bonding, thin film in multilayer of the flexible optical waveguide immediately factor important is is connectivity layers. In in the embodiment, upper and lower pad via including via each projecting shape prevented, in multilayer of the flexible optical waveguide thin film interlayer according to the objective compound. connectivity. Figure 1 shows a semiconductor device in the embodiment according to one also concerns a cross-sectional to.. With a 1 also, in the embodiment according to semiconductor device has a plurality of thin film layers (121, 131, 141, 151), insulating layer (122, 132, 142, 152) and via pad (123, 133, 143) includes. Plurality of thin film layers (121, 131, 141, 151) are formed on the substrate, and each circuit pattern includes. Wherein, substrate (110) may be the substrate and a ceramic, the thin film may be formed, molybdenum (Mo), copper (Cu) or like material, and can be formed by. Well as, by the thin film process may be formed with, PVD (physical vapor deposition), CVD (chemical vapor deposition), ALD (Atomic Layer Deposition) such as as well as method for growing thin films a variety of processes, is can be applied. Also 1 shown in the different thin-film layer formed for offering tree view showing unannotated in one example, line width of and via a circuit pattern layer corresponding relationship can be differ depending on the situation. In in the embodiment, plurality of thin film a plurality of circuit pattern and similar to the widest sense of the can be used. In addition, substrate (110) is formed on one surface of such a circuit pattern (121) the substrate corresponding to (110) other aspects the electrode pattern, circuit pattern or in a pattern which corresponds to the probe pin may be formed at least one of, is nickel (Ni) and gold (Au) may be formed as stacked configuration. Well as, is composed of a metal a nickel and gold is not limited to various situation if can be metals are used. Insulating layer (122, 132, 142, 152) a plurality of thin film layers to insulate the out the liquid into a layer each other, a circuit pattern are formed in different layers to insulate the together. a layer. Such insulating layer (122, 132, 142, 152) polyimide (PI; polyimide) may be formed with by, as well as plurality of thin film layers is insulating the various contact between the can be formed. Via pad (123, 133, 143) has a plurality of thin film layers (121, 131, 141, 151) for making an electrical connection of an as an instrument for breaking, by conductive protection layers are formed on the is formed. Via pad (123, 133, 143) including the via consists of an e-mail and pad, each upper and lower pad has projecting shape. Hereinafter, an extended formed on top of pad projecting upper shape and designated shape, formed lower than the height of an extended a designated shape projecting lower edge shape. Wherein, lower than the height of projecting shape process is carried on the via holes can be mixture by the addition of an initiator. At this time, via pad (123, 133, 143) that apply a plating by can be formed. Well as, via pad (123, 133, 143) is formed by plating process is not limited to which, projecting top of pad shape which may have process technique can be applied to both. Via pad (123, 133, 143) projecting top of shape projecting lower edge shape may have different shapes, a curved surface operable shape projecting upper may include a. And, has a top portion with a curved surface projecting-shaped but of varying pattern shape can be formed. In in the embodiment, a via pad or more vias at least two the same wherein the sensor is mounted on the support substrate a stack via structure may be formed from, stacked vias (Stacked Via) when formed formed pad via structure formed within the first region of each layer can be enhance an integration degree increase the. Such via pad (123, 133, 143) is formed projecting top of shape may be formed in the position, various forms may be formed as. For example, via pad 4 also shape projecting top of projecting an upper shown in for the shape as shown in plane view, is deposited on the entire substrate circular pattern (a) and can be formed with the, is deposited on the entire substrate rectangular pattern (b), (c) the decoder decodes pattern, a polygon are provided in the, such hexagon pattern (d) may be pattern is formed. And, most on the upper face formed a via pad (143) has an interconnection corresponding to the bonding pad may be, most on the upper face formed a via pad (143) necessarily via pad bonding pads when the projecting top of. the service cells need not necessarily be configuration. A via only having shape projecting lower edge by forming a pad, most on the upper face via pad, use can be made of, to the bonding pads. As such, upper projecting shape via shape projecting lower edge the pad formed in a layer to electrically connect the thin-film layer, reducing the risk of P-type semiconductor layer of another open when electrical connectivity can be improved which, the also described by referring to the 2. Figure 2 shows a 1 also also account pad via shown in the chemical formula 6, m is an end surface, via pad shape projecting top of the thickness of via pad material formed at upper portion of a open according to the ratio of its thickness of the insulation layer is intended to explain the P-type semiconductor layer of another. Also shown in 2TAprojecting top of the via pad thickness of shape means, TBthe via pad material formed at upper portion of a mixture by the addition of an initiator thickness of the insulation layer, the via diameter D (Via Diameter). 1 table below the via diameter (D) is less than 100 shape projecting top of pad via when the thickness of material formed at upper portion of a pad via the ratio of its thickness of the insulation layer( TA/TB×100)<aotran type="glo" translation="according toopen P-type semiconductor layer of another chemical formula 6, m is an, as shown in table 1, a length different from each upper projecting shape 30 [%] ratio the thicker the process the thermal conductivity coating layer and method for manufacturing the same by insulating layer is formed while not-open hole exposing an, 30 [%] a network monitor measures a transmission ratio an upper projecting shape if there is no (0 [%]) compared to open-it is found that the KIPO &. In the embodiment according to the stacked vias structure semiconductor device a via pad shape derived top of material formed at upper portion of a pad via the thickness of the ratio of its thickness of the insulation layer is less than 30 [%] when plurality of thin film layers between the objective compound. electrical insulation. Specifically, via pad shape derived top of material formed at upper portion of a pad via the thickness of the ratio of its thickness of the insulation layer 2 - 28 [%] or 5 - 25 [%] one case plurality of thin film layers between the objective compound. electrical insulation. As such, via for improving electrical insulation projecting top of pad pad via the thickness of the shape of the insulation layer formed on top of can be by. In addition, the thickness of the shape projecting top of pad via via pad from plating process in the periphery of the bottom surface, the types of number determine a proportion of number added by section has a sensor detecting a wave, can be determined. In other words,, projecting top of pad via according to thickness insulating layer having a thickness upon determination of a for the shape, number, the types of addition to determine a proportion of number added after plating process, wherein portions of a a via has a thickness determined through projecting top of pad can be configuration. Thus, semiconductor device in the embodiment according to the upper projecting shape projecting lower edge shape via of chip for using circuitry contained the plurality of thin film layers to electrically connect the pattern, at least two stacked vias pads or more vias by a red color when an alarm, plurality of thin film layers the lattice located in the connectivity the second lines adjacent to each other, thereby increasing the formed within the first region of each layer can be enhance an integration degree. In the embodiment according to semiconductor device has a plurality of thin film using a the via the a variety of semiconductor device is applicable to any type of items or devices, in one example probe card can be applied on for inspecting. This semiconductor device 3 also process for bath number a reference to. off at the first and the second. Also door has also to 3a 3f semiconductor device number bath 1 shown in the chemical formula 6, m is cross-sectional drawing process, also 1 shown in a plurality of thin film layers on ceramic substrate first via pad. indicating a battery with feature of enhanced charge efficiency. As shown in 3a also, ceramic substrate (110) on the side of the take-circuit pattern form (121) is formed, a circuit pattern formed and the radiation ceramic substrate a layer structure by etching selectively a dielectric part of an abstraction layer (122) via hole is formed on. Wherein, molybdenum circuit pattern, such as copper a metal such as a thin-film with a foil which can be, but of varying method forming the same can be applied. Well as, the metal is separately can be formed. And, insulating layer (122) polyimide (PI) types of an insulation material for a may be formed with, in one example, polyimide a circuit pattern formed in a ceramic one surface of upper spin coating and for forming via hole after performing a performing a photo process is cured to thereby, if an overflow is generated in the via is formed an insulating layer (122) capable of forming a.. Then, also as shown in 3b, an insulating layer is formed (122) via upper seed layer for forming pad (124) is formed on. Wherein, seed layer (124) (evaporation) vivoelectroporation a paint spraying the method and sputtering method, for example by (sputtering) can be formed. Seed layer (124) is formed also as shown in 3c, seed layer (124) on resist (PR) (125) for coating the via pad to form a patterning process are performed in one process chamber via pads are formed of the area to be PR. triggers number only. Then, as shown in also 3d, via the pad region is reparing over-number is PR plating structure is formed pattern by using an electrochemical plating position the upper projecting shape via pad (123) to form a. Wherein, via pad (123) thickness shape projecting top of the periphery of the bottom surface of from plating process number determine a proportion of added, the types of section has a sensor detecting a wave number can be determined. Number additive added number added, the types of via hole adjusted by ratio of fill the via fill (fill) by the number of, via pad thickness shape projecting top of may [...] number. At this time, via pad (123) shape projecting top of the via pad thickness and shape projecting top of via pad are formed on the insulation layer so that 2 - 28 [%] is the ratio of its thickness can be formed. Shape projecting top of pad via such an interlayer dielectric is formed on the pad a via thickness of the insulation layer can be by. Well as, via pad projecting top of other shape predetermined pattern pattern for example, polygonal non-circular pattern when the pattern is exposed by removing PR and flat pad after triggers number of polygonal pattern PR projecting shape for forming back to upper is formed in the pattern plating by conducting the process, can be. And, also as shown in 3e, PR pattern (125) and triggers a number, as shown in 3f also, via pad (123) blocking region element formed in the region other than of seed layer (124) a mask to etch or a dry etching by, insulating layer (122) to expose to. The above-mentioned process, ceramic substrate including circuit pattern on layer of a thin film layer and an insulation layer and then thin-film layer such a circuit pattern formed the via for connecting the to form a pad. Well as, plurality of thin film layer define, plurality of thin film layers are connected to each other by a plurality of via pad to form a in described above also to 3a 3f is surface perform a process. Via pad of structure 3f also connects the and circuit patterns, is formed on the upper contact pad forming a seed layer and an insulating layer is formed via pad position battery with feature of enhanced charge efficiency is exactly by performing, plurality of thin film layers can be. the device may be applied to a probe card, the also described by referring to a 5. In the embodiment according to Figure 5 one probe card. indicating a the configuration. Also as shown in 5, probe card (500) has telemetering part (510), support (520), connection (530) and reinforcement (540) includes. Support (520) has telemetering part (510) serves to support the and means are configured to carry out the, connection (530) has telemetering part (510) electrically connecting the is of configuration means, reinforcement (540) has of the probe card and of configuration means reinforcement for a wheel brake unit by pneumatic pressure from is. Meter reading part (510) a test a test tray placed pad means a configuration, and meter reading, the device is a configuration corresponding to. Meter reading part (510) has metallized circuit patterns including plurality of thin film layers plurality of thin film layers each other projecting upper layer and at provided in order to insulate the shape projecting lower edge includes a pad via shape. At this time, via pad can be formed by plating process and, upper projecting shape projecting lower edge shape may have different shapes, a curved surface operable shape projecting upper may include a. In addition, a via pad or more vias at least two the same wherein the sensor is mounted on the support substrate a stack via structure may be formed from, upper projecting shape is formed on the semiconductor substrate including a via pad thickness of the insulation layer by a thickness can be determined, and, via pad for forming a plating process in the periphery of the bottom surface from number determine a proportion of added, the types of section has a sensor detecting a wave number by, can be determined. Via pad shape projecting top of the via pad thickness and shape projecting top of via pad are formed on the insulation layer so that 2 - 28 [%] is the ratio of its thickness can be formed. The resulting structured materials, although in the embodiment are defined in the embodiment and a drawing but is described by, corresponding various said ramyon person with skill in the art in various technical fields and deformation that a modified from of.. For example, techniques are described described a method or in an order different, and/or passivation layer is selectively or, structure, device, circuit or the like are described components of the method and other connection or or in combination, other components or equal comprising or unsubstituted is replaced by a suitable even can be result is achieved. Therefore, other implementations, other in the embodiment and also those uniform and a claim refers to claim. in the range of approximately. Disclosed are a semiconductor device and a method for manufacturing the same. According to an embodiment, the semiconductor comprises: a substrate; a plurality of thin films formed on the substrate and having a circuit pattern formed thereon; and an insulating layer for insulating the plurality of thin film layers from each other. The plurality of thin film layers are connected through a via pad including a via. The upper part and the lower part of the via pad individually have a protruding pattern, and at least two among the plurality of thin film layers are connected through a stacked via structure. COPYRIGHT KIPO 2016 Substrate; said are formed on the substrate, the circuit pattern is a plurality of thin film layers; and said plurality of thin film layers each other and the insulation layer to insulate the, said plurality of thin film layers are via is connected to the pads and at via including, upper and lower pad via said each device semiconductor projecting shape. According to Claim 1, said plurality of thin film layers at least two stack via (Stacked Via) structure the semiconductor device. According to Claim 1, said thickness shape projecting top of pad via said via pad is formed on said insulating layer by a semiconductor device. According to Claim 3, said upper projecting said thickness and shape the ratio thickness insulating layer 2 - 28 [%] in semiconductor device. According to Claim 1, projecting top of pad via said shape the silver it stands shape corresponding to the projecting lower than the height of said semiconductor device. According to Claim 1, silver curved surface shape projecting top of pad via said semiconductor device including shape. According to Claim 1, said semiconductor device including semiconductor device probe card. Semiconductor device of an exposure unit in a probe card for inspection, said semiconductor device, and meter reading pad communication between the reading part; and said meter reading a support includes, said meter reading the ceramic which it blows substrate; said ceramic are formed on the substrate, the circuit pattern is a plurality of thin film layers; and said plurality of thin film layers each other and the insulation layer to insulate the, said plurality of thin film layers are via is connected to the pads and at via including, upper and lower pad via said each probe card having projecting shape. According to Claim 8, said plurality of thin film layers at least two stack via (Stacked Via) structure the probe card. Number 1 and metallized circuit patterns on a substrate, said substrate and said number 1 circuit pattern on top step forming a insulating layer number 1; said number 1 number 1 parts of the insulating layer via holes step; by said number 1 connected to the electrical circuit pattern said number 1 number 1 via step of forming a pad via including number 1; said number 1 through a pad via said number 1 to insulating layer connected to the electrical circuit pattern said number 1 number 2 circuit layer pattern is formed on an; said number 2 pad and via said number 1 and number 2 on top circuit pattern includes forming a insulating layer, the step said number 1 via a semiconductor layer is formed on each upper and lower pad via said number 1 having the shape protruded in semiconductor device number bath method. According to Claim 10, parts of the insulating layer said number 2 said number 1 via hole number 2 in the same location with at least a portion of via holes step; by said number 2 and connected to the electrical circuit pattern said number 2 number 2 via said number 1 via pad and including number 2 via pad stacked vias structure of a include, said number 2 the step via a semiconductor layer is formed on each upper and lower pad via said number 2 having the shape protruded in semiconductor device number bath method. According to Claim 10, said number 1 via a semiconductor layer is formed on top of pad via said number 1 the step projecting said number 2 2 - 28 [%] ratio thickness insulating layer thickness and shape so that a semiconductor layer is formed on via said number 1 semiconductor device number bath method. According to Claim 10, step of forming a pad via said number 1 in advance addition, the types of number is determined number for plating using the ratio of said added through the process of projecting top of pad via said number 1 has a thickness constant shape said number 1 via a semiconductor layer is formed on semiconductor device number bath method. Ratio (%) Open P-type semiconductor layer of another (%) 100 100 90 92. 8 80 88. 7 70 80. 3 60 70. 2 50 65. 1 40 60. 9 30 23. 3 25 0 20 0 15 0 10 0 7. 5 4. 9 5 11. 8 0 21. 9
