SEMICONDUCTOR ELEMENT

Advantages and features of the present invention, achieve the appended drawing method and an electronic component connected to the reference surface with specifically carry activitycopyright will in the embodiment. In the embodiment in the present invention refers to hereinafter however limited to various different rather than the disclosure are embodied in the form of percussion, in the embodiment of the present invention are only the technical idea of and can be utilized for a complete disclosure, the present invention is provided to a target area of the invention completely for alerting the person with skill in the art in categories to which ball number, defined by category of the present invention refers to claim only disclosed. In drawing and regions size and relative size exaggerated colors for intelligibility descriptions may be disclosed. Throughout the specification the same references refer to the same components.

In the embodiment of the present invention are discussed specification the ideal that excels in regards cross-sectional drawing, plane view and block also refer to be described are disclosed. The, number bath techniques and/or tolerances of form can be modified by example degrees. Thus, the specific number of the present invention in the embodiment shown are but one type of change including process for preparing produced in accordance number are disclosed. The, drawing attribute has exemplified regions are coarse, drawing the shape for the region exemplified areas in form and for example, categories for valve timing of the number of the invention are not correct.

Substrate in drawing, exaggerated for clarity and the virtualization of thickness regions are disclosed. In addition, referred to as "on" another layer or substrate layer determines when it formed directly on the other layer or substrate or may be interposed therebetween a layer number 3 may be filled. The same reference number throughout the specification indicated by parts may be on big components.

Top, bottom, top, the, or upper, lower in terms of relative position used for distinguishing different components are disclosed. For example, drawing upward [...] on upper, lower downwards when drawing on referred to, chamber outside of the range of the present invention in upper unit has a number can be designated without rights, can be termed upper lower.

In addition, "upper", "intermediate" and "lower" relative position between components such as term used by distinguishing different, these terms are not correct is restricted by technical idea of the present invention. Thus, these "upper", "lower" and other terms such as "intermediate" term, e.g. "number 1", "number 2" and terms such as "number 3" replaced components of the specification be used account for disapproval.

"Number 1", "number 2" describes terms such as various components can be used but, said components are defined by said terms are not correct. Components are mounted to one of said terms are used only distinguished from other components of the object. For example, outside of the range of the present invention rights without "number 1 component" is "number 2 component" can be referred to.

The term used in application specific embodiment is only used to account for example, technical idea of the present invention intending to be define is endured.

It is apparent that a single representation of the differently in order not providing language translators, comprising plurality of representation. In the application, the term "comprising" or "having disclosed" specification of articles feature, number, step, operation, component, piece or specify a combination not present included, another aspect of one or more moveable number, step, operation, component, piece or a combination of pre-times the number should not understood to presence or additional possibility.

Not differently defined, all technical or scientific terms so that the present invention is thus the technical idea in the art terms is provided by the same person with skill in the art will generally of reconciliation is disclosed. Generally defined dictionary used for providing language translators such as terms of reconciliation is consistent semantics and having associated technology must be interprets, the application will not become manifest in defining, or overly formal sense interpreted not ideal.

In the embodiment of the present invention are according to the schematic diagram of the block diagram of Figure 1 shows a semi-structure for preventing generation of technical idea also are disclosed.

The reference also 1, according to the semiconductor device of the present invention in the embodiment (10) memory cell array (20), driving circuit (30), read/write (read/write) circuit (40) and the circuit number (50) can be a.

Said memory cell array (20) comprises a plurality of memory cells can be, arranged along a plurality of memory cells includes a plurality of row with columns can be. Said memory cell array (20) contained in the plurality of memory cells, word line (Word Line, WL), common source line (Common Source Line, CSL), string selection line (String Select Line, SSL), ground select lines (Ground Select Line, GSL) by a reduction in said driving circuit (30) can be connected to, read/write circuit through bit line (Bit Line, BL) (40) can be connected.

In an exemplary in the embodiment, arranged along the same row have identical memory cell connected to the word line (WL), arranged along the same column as the memory cell have identical bit line (BL) can be connected.

Said memory cell array (20) contained in the plurality of memory cells are partitioned into a plurality of memory blocks can be. Each memory block includes a plurality of word lines (WL), a plurality of string selection lines (SSL), plurality of ground select line (GSL), common source line (CSL) comprising a plurality of bit lines (BL) and at least one can.

Said driving circuit (30) on said read/write circuit (40) said number has circuitry (50) can be operated by.

To one in the embodiment, said driving circuit (30) address (address) is also receives information (ADDR), receiving address information (ADDR) (WL) decodes the memory cell array connected to said word line, said common source line (CSL), said string selection line (SSL) and said ground select line (GSL) can be at least one selected part. Said driving circuit (30) includes said word line (WL), said string selection line (SSL), said common source line (CSL) can be a driver for each circuit.

Said read/write circuit (40) said number is the circuit (50) according to instructions received from said memory cell array (20) connected to said bit line (BL) can be at least one selected part. Said read/write circuit (40) writes the selected at least some of the bit line (BL) connected to or stored in the output buffer, at least some of the selected bit line (BL) for writing data into a memory cell can be connected. Said read/write circuit (40) is such as to perform said operation, page buffer, input/output buffer, data latch circuit such as can be.

The circuit said number (50) in response to a signal (CTRL) number is also conveyed from said driving circuit (30) and said read/write circuit (40) be operation of [...] number. Said memory cell array (20) on an stored data are read, the circuit said number (50) is inputted to the database containing data word line (WL) for read operation voltage supplied to said driving circuit (30) be operation of [...] number. For read operation voltage supplied to a particular word line (WL), said number the circuit (50) includes said read/write circuit (40) is a read word line voltage is supplied for the operation of a stored in the output buffer number [...] (WL) to be connected.

On the other hand, said memory cell array (20) when write data from, said number circuitry (50) tracks of read or write word line (WL) supplies voltages from the first writing operation to said driving circuit (30) be operation of [...] number. For write operation voltage supplied to a particular word line (WL), said number the circuit (50) includes a word line voltage is supplied for write operation to a memory coupled to said read/write circuit configured to record (WL) cells (40) [...] be a number.

In the embodiment of Figure 2 shows a technical idea of the present invention are also of semiconductor memory cell array according to an exemplary equivalent circuit are disclosed. Also Figure 2 shows a vertical semiconductor element (10) contained in the memory cell array (20a) indicating equivalent circuit of 3 dimensional structure are disclosed.

The reference 2 also, in the embodiment of memory cell array according to the technical idea of the present invention (20a) is, connected in series with one another n connected memory cell element (MC1 provided MCn), memory cell element (MC1 provided MCn) connected in series with a ground selection transistor (GST) to both ends of a plurality of memory cells including transistors (SST) can be strings.

N connected memory cell element is connected in series with one another (MC1 provided MCn) for selecting at least some of said memory cell element (MC1 provided MCn) (WL1 provided WLn) can be each coupled to a word line.

The gate terminals of said ground select line (GSL) (GST) said ground selection transistor is coupled to the, common source line (CSL) can be connected to said source terminal. On the other hand, said string selection transistor connected to the gate terminals of said string selection line (SSL) (SST), source terminal can be connected to the drain terminals of said memory cell element (MCn). In Figure 2 are each connected in series with a ground selection transistor to said n connected memory cell element (MC1 provided MCn) (GST) (SST) on said string selection transistor connected structure is shown but one, alternatively a plurality of ground select transistors (GST) or a plurality of string selection transistors (SST) connected disapproval.

(SST) string selection transistor connected to the drain terminals of said bit line (BL1 provided BLm) can be. Said operation of said string selection line (SSL) string selection transistor (SST) through signal is applied, said bit line (BL1 provided BLm) it is applied through n connected in series connected memory cell element (MC1 provided MCn) can be transmitted to the data read or write operation is executed. In addition, common source line (CSL) said source terminal is connected to said operation of said gate select line (GSL) gate selection transistor (GST) by applying a signal through, n connected memory cell element (MC1 provided MCn) (erase) action is both a stand-alone number charge stored can be erased.

Also in the embodiment according to one example of semiconductor device of the present invention with reference to the technical idea of 3 and 4 also produced in less than 1000. Figure 3 shows a plane view of a portion of the technical idea of the present invention also in the embodiment according to semiconductor and indicating, Figure 4 shows a I a-I ' cross-section of Figure 3 taken along a line indicating an area are disclosed.

The reference also 3 and 4 also, substrate (103) on said substrate (103) (Z) direction perpendicular to the surface of interlayer insulating layers alternately stacked (109) and horizontal conductive patterns (167) can be disposed. Said substrate (103) is formed of a semiconductor material such as silicon can be a semiconductor substrate.

Said interlayer insulating layers (109) may be the number 1 (X) direction extending line shape, a pair of mutually opposed side number 1 (S1) and (S2) may have a side number 2. Said interlayer insulating layers (109) said number 1 and number 2 (S1, S2) number 1 regions adjacent the sides (A1) (A2) (A1) comprising said number 1 and number 2 region can be between regions.

Said interlayer insulating layers (109) is said horizontal conductive patterns (167) may have a greater width than. Said interlayer insulating layers (109) of said number 1 and number 2 sides (S1, S2) may be cross-shaped, said horizontal conductive patterns (167) is concave shaped sides may have.

Said horizontal conductive patterns (167) during, the lowest horizontal conductive pattern (167g) said ground select line (GSL) is described in Figure 2 may be, top horizontal conductive pattern (167s) is described in Figure 2 may be said string selection line (SSL), said least significant horizontal conductive pattern (167g) and said top horizontal conductive pattern (167s) between a plurality of horizontal conductive patterns (167w) is said word lines (WL1 provided WLn) implementation being described in Figure 2.

Said top horizontal conductive pattern (167s) onto a lower interlayer dielectric layer (115) can be disposed. Said dielectric layer (115) is said interlayer insulating layers (109) can be formed to the same.

Said dielectric layer (115), said horizontal conductive patterns (167) and said interlayer insulating layers (109) through vertical structures (133) can be disposed.

Said vertical structures (133) is said interlayer insulating layers (109) of said number 2 region (A2) can be through. Said vertical structures (133) is said interlayer insulating layers (109) (S1, S2) of said number 1 and number 2 sides near outer vertical structures (133a) and said outer vertical structures (133a) than said number 1 and number 2 sides remote from (S1, S2) inner vertical structures (133b) can be comprising.

Said vertical structures (133) each of the pattern of the core (139), said pattern of the core (139) covering the bottom surface and side surfaces of the semiconductor layer (136), said pattern of the core (139) pad pattern on (142) can be comprising.

In one example, said pattern of the core (139) such as an insulating material can be formed of silicon. Said semiconductor layer (136) is can be formed of a semiconductor material such as silicon.

In one example, said pad pattern (142) shaped conductive material such as polysilicon doming can be. E.g., said pad pattern (142) formed at the N can be formed. Said pad pattern (142) is described in Figure 2 be a drain terminals of said string selection transistor (SST).

Said vertical structures (133) and said horizontal conductive patterns (167) including information storage layer is disposed between the gate dielectric structure (gate dielectric structure) can be.

In one example, said gate dielectric structure is a dielectric structure number 1 (121) and a dielectric structure number 2 (160) can be a. Said number 1 and number 2 dielectric structures (121, 160) can be one of either said information storage layer.

In one example, a dielectric structure said number 1 (121) is a dielectric structure said number 2 (160) on said vertical structures (133) interposed between said interlayer insulating layers while (109) and said vertical structures (133) can be extending between. A dielectric structure said number 2 (160) said number 1 is a dielectric structure (121) on said horizontal conductive patterns (167w) interposed between said horizontal conductive patterns while (167w) and said interlayer insulating layers (109) can be extending between.

Said vertical structures (133) and said dielectric layer (115) covering the upper insulating layer (145) can be disposed.

Said substrate (3) each other spaced apart isolation patterns (181) can be disposed. Said separation patterns (181) is said upper insulating layer (145), said dielectric layer (115), said interlayer insulating layers (109), and said horizontal conductive patterns (167) can be through. Said separation patterns (181) is, in a plane, extending line shape be a number 1 (X) direction. Said interlayer insulating layers (109) and said horizontal conductive patterns (167) is said separation patterns (181) can be disposed between.

In one example, said separation patterns (181) can be conductive material. E.g., said separation patterns (181) metal nitride (e.g., TiN, TaN or the like) and/or metal materials (for example, Ti, W or the like) can be comprising.

Said separation patterns (181) on sides of an insulating spacers (175) can be disposed. Said insulating spacers (175) such as an insulating material can be formed of silicon. Said insulating spacers (175) is said separation patterns (181) and said horizontal conductive patterns (167w) interposed between said separation patterns (181) and said interlayer insulating layers (109) can be interposed between.

Said separation patterns (181) underlying said substrate (103) in the source impurity regions (178) can be disposed. Said source impurity regions (178) N may be the second conductive type, said source impurity regions (178) adjacent to said substrate (103) P be a portion of the second conductive type. Said source impurity regions (178) is a common source line (CSL) said implementation being described in Figure 2.

Said interlayer insulating layers (109) made of silicon oxide or a silicon can be formed. Said high-(C) can be made of a silicon oxide including a silicon oxide.

Said interlayer insulating layers (109) impurity concentration can each of the different regions. E.g., said interlayer insulating layers (109) said number 2 area (A2) of the interlayer insulating layers (109) of said number 1 regions (A1) can be impurity concentration than low portion.

Said interlayer insulating layers (109) said impurity is in said interlayer insulating layers (109) can be be a dry etching of an atom. E.g., said interlayer insulating layers (109) along sides of said of said interlayer insulating layers (109) can be varied when it is etching process.

In one example, said interlayer insulating layers (109) (phosphorous) of said impurity is phosphorus or boron (boron) can be one of the element. However, technical idea of the present invention is not limited to. E.g., said interlayer insulating layers (109) of said impurity is nitrogen (N), hydrogen (H), chlorine (Cl), comprising flow five starting material (F) or sulfur (S) can be.

In one example, said interlayer insulating layers (109) said regions having different impurity concentration, said high impurity concentration region is said low impurity concentration may have etch selectivity area with the other. E.g., said interlayer insulating layers (109) in, high impurity concentration impurity is deposited etch rate of low VOC region can differ from each other disclosed. Said interlayer insulating layers (109) in, high impurity concentration can be greater than that of etching rate of etching low impurity concentration. For example, said number 1 (A1) (A2) said number 2 regions is formed below the portion of the region having a concentration thereof can etching rate than said number 1 regions (A1).

In one example, said interlayer insulating layers (109) said regions having different impurity concentration, low impurity concentration than the high impurity concentration region thereof can thin. (A1) (A2) said number 1 regions having a concentration region is formed below the number 2 (A1) may have thickness which is thicker than the part of the number 1 regions.

In one example, said horizontal conductive patterns (167) contiguous with said dielectric layer (115) is said interlayer insulating layers (109) can be formed to have the same material and the same impurity concentration. E.g., said dielectric layer (115) is said interlayer insulating layers (109) as well as high impurity concentration low impurity concentration region can be regions, have a thick region thickness can be thin regions.

In one example, said interlayer insulating layers (109) of said number 1 regions (A1) interposed between said horizontal conductive patterns (167) the area of the number 1 regions (A1) has said number 1 (A1) is formed below the interlayer insulating layers having a thickness thicker than said regions (109) of said number 2 region (A2) interposed between portions of said horizontal conductive patterns (167) can be formed thickness greater than the areas.

Said interlayer insulating layers (109) said number 2 area (A2) of the outer vertical structures (133a) number 1 (P1) and positioned between the portions (P1) (P2) between portions portion comprising said number 1 number 2 can be. Said inner vertical structures (133b) is said interlayer insulating layers (109) through said number 2 (P2) can be part of.

In one example, said inner vertical structures (133b) contiguous with said interlayer insulating layers (109) the concentration of impurities in said interlayer insulating layers (109) (S1, S2) of said number 1 and number 2 sides adjacent said interlayer insulating layers (109) be less than the concentration of impurities in.

As described, said interlayer insulating layers (109) and concentration of impurities can include different regions, having different thicknesses can be regions. And, said horizontal conductive patterns (167) having a thickness regions can be different.

The concentration of impurities including said interlayer insulating layers different regions (109) and the upper using the process for forming a semiconductor device can be reduced, such reduction leads to reject yield and productivity can be increased.

Process serves to prevent a predetermined function can be. In addition, said separation patterns (181) increased thickness at a portion adjacent to said horizontal conductive patterns (167) of a single can be improved. The, method for electrical characteristics can be improved.

This said interlayer insulating layers (109) and said horizontal conductive patterns (167) for examples of used or produced in a hole of 5a to 10b also also. Wherein, descriptions for convenience and easy understanding said interlayer insulating layers (109) adjacent to each other apart from number 1 and number 2 and an interlayer dielectric layer of an interlayer dielectric layer, said horizontal conductive patterns (167) in, said number 1 and number 2 interlayer insulators positioned between the conductive pattern and higher horizontal number 1 through a browser, said reference 3 and also through a browser such as interlayer insulating layers also 4 (109) of said regions (A1, A2, P1, P2), said vertical structures (133) and said number 1 and number 2 dielectrics (121, 160) details description for dispensed the on-sensors other.

Also 5a, 6a also, also 7a, 8a also, also each of the interlayer insulating layers also 9a and 10a (109) adjacent to each other apart from said number 1 and number 2 during interlayer insulating layers, said number 1 and number 2 interlayer insulating layers between said number 1 to account for a cross-sectional drawing one example of conductive pattern are disclosed.

Also 5a of said interlayer insulating layers is also 5b (109) exemplary concentration of impurities and to explain the coarse drawing, 6a of said interlayer insulating layers also is also 6b (109) to explain the coarse drawing and impurity concentration in an exemplary, said interlayer insulating layers also 7a 7b is also of (109) exemplary concentration of impurities and to explain the coarse drawing, interlayer insulating layers of said 8b also is also 8a (109) exemplary concentration of impurities and to explain the coarse drawing, 9a 9b is interlayer insulating layers of said hole are also (109) to explain the coarse drawing and impurity concentration in an exemplary, said interlayer insulating layers also 10a 10b is also of (109) to explain the coarse drawing an exemplary concentration of impurities are disclosed.

Also 5a, 6a also, also 7a, also 8a, 9a and 10a also in also, said interlayer insulating layers (109) is said vertical structures (133) and by but appear like that has, said interlayer insulating layers (109) said number 1 and number 2 sides (S1, S2) plane of Figure 3 is studied in the field of view between one another at the nanometer range. The, also 5b, also 6b, 7b also, also 8b, 9b and 10b also includes the interlayer insulating layers also interconnected said (109) indicating impurity concentration of are disclosed.

First, with reference to the 5a and 5b also with 3 and 4 also may also, said interlayer insulating layers (109) and said horizontal conductive patterns (167) is described one example of the device for each other.

Also with 3 and 4 also, the 5a and 5b also also reference, said interlayer insulating layers (109) are adjacent to each other apart from interlayer dielectric layer number 1 (109a _ 1) number 2 and an interlayer dielectric layer (109a _ 2) and include, said horizontal conductive patterns (167) one of horizontal conductive pattern (167a) said number 1 and number 2 the interlayer insulating layers (109a _ 1, 109a _ 2) can be disposed between.

Said number 1 and number 2 interlayer insulating layers (109a _ 1, 109a _ 2) in, said number 1 and number 2 sides (S1, S2) from said number 1 (P1) (A2) said number 2 region in impurity concentration gradually to the portions can be reduced. Said number 1 and number 2 interlayer insulating layers (109a _ 1, 109a _ 2) said number 1 and number 2 (S1, S2) from the area (A2) said number 2 sides portions are gradually increased in thickness to said number 1 (P1) can be.

Said number 1 and number 2 interlayer insulating layers (109a _ 1, 109a _ 2) in, said number 2 region of said number 2 (P2) (A1) (A2) impurity concentration lower than that of the portion the number 1 regions thereof can. Said number 1 and number 2 interlayer insulating layers (109a _ 1, 109a _ 2) in, high impurity concentration regions (A1) (A2) said number 1 said number 2 (P2) of the thickness of the low impurity concentration region thickness less than that of said number 2 portion thereof can.

Said horizontal conductive pattern (167a) said number 1 and number 2 the interlayer insulating layers (109a _ 1, 109a _ 2) said number 1 and number 2 from overlapping portions of said number 1 regions (A1) interlayer insulating layers (109a _ 1, 109a _ 2) said number 2 area (A2) of said number 1 (P1) portions of decreasing thickness can be placed overlapping portions.

Said number 1 horizontal conductive pattern (167w _ 1) in, said number 1 and number 2 interlayer insulating layers (109a _ 1, 109a _ 2) said number 1 and number 2 (S1, S2) said number 1 and number 2 the thickness of the sides of the free portion and closer interlayer insulating layers (109a _ 1, 109a _ 2) (A2) and (P2) over a portion of said number 2 of area can be greater than the thickness of said number 2.

Next, with reference to the 3 and 4 also with 6a and 6b also may also, said interlayer insulating layers (109) and said horizontal conductive patterns (167) is described variants of to less than 1000.

Also with 3 and 4 also, the 6a and 6b may also reference, said interlayer insulating layers (109) are adjacent to each other apart from interlayer dielectric layer number 1 (109b _ 1) number 2 and an interlayer dielectric layer (109b _ 2) and include, said horizontal conductive patterns (167) one of horizontal conductive pattern (167b) said number 1 and number 2 the interlayer insulating layers (109b _ 1, 109b _ 2) can be disposed between.

Said number 1 and number 2 interlayer insulating layers (109b _ 1, 109b _ 2) in, said number 1 (A1) (A2) the concentration of impurities in the regions of said number 2 (P2) area than that of said number 2 portion thereof can reach.

Said number 1 and number 2 interlayer insulating layers (109b _ 1, 109b _ 2) in, the concentration of impurities in said number 1 regions (A1) can be substantially uniform, said number 2 area (A2) of said number 2 portion (P2) can be substantially uniform impurity concentration. Said number 1 and number 2 interlayer insulating layers (109b _ 1, 109b _ 2) said number 1 and number 2 substantial impurity concentration change in interlayer insulating layers (109b _ 1, 109b _ 2) portions of said number 1 (P1) of said number 2 region (A2) can be generated.

Said number 1 and number 2 interlayer insulating layers (109b _ 1, 109b _ 2) in, said number 2 (P2) (A1) (A2) of said number 2 region portion the number 1 regions have an impurity concentration lower than may be thicker disclosed. Said number 1 and number 2 interlayer insulating layers (109b _ 1, 109b _ 2) step (A2) of said number 1 (P1) due to the thickness of said number 2 region can be generated in portions.

Said horizontal conductive pattern (167b) said number 1 and number 2 the interlayer insulating layers (109b _ 1, 109b _ 2) (A1) and said number 1 and number 2 of said number 1 regions over a thickness in interlayer insulating layers (109b _ 1, 109b _ 2) area (A2) of said number 2 (P2) over a portion of said number 2 and profile may be thicker than disclosed. Said horizontal conductive pattern (167b) variation in the thickness of the interlayer insulating layers in said number 1 and number 2 including signal lines (109b _ 1, 109b _ 2) portions of said number 1 (P1) and (A2) over a region of said number 2 can be generated.

Next, with reference to the 7a and 7b also with 3 and 4 also may also, said interlayer insulating layers (109) and said horizontal conductive patterns (167) of another version is described the on-sensors other.

Also with 3 and 4 also, the 7a and 7b may also reference, said interlayer insulating layers (109) are adjacent to each other apart from interlayer dielectric layer number 1 (109c _ 1) number 2 and an interlayer dielectric layer (109c _ 2) and include, said horizontal conductive patterns (167) one of horizontal conductive pattern (167c) said number 1 and number 2 the interlayer insulating layers (109c _ 1, 109c _ 2) can be disposed between.

Said number 1 and number 2 interlayer insulating layers (109a _ 1, 109a _ 2) regions (A1) of said number 1 in, said number 1 and number 2 edge sides (S1, S2) can be concentration of impurities is reduced gradually. Said number 1 and number 2 interlayer insulating layers (109c _ 1, 109c _ 2) regions (A1) of said number 1 in, said number 1 and number 2 sides (S1, S2) edge gradually reduced thickness can.

Said number 1 and number 2 interlayer insulating layers (109c _ 1, 109c _ 2) in, said number 1 and number 2 (S1, S2) said number 2 region (A2) (A1) said number 1 regions adjacent the sides thereof can low impurity concentration than. Said number 1 and number 2 interlayer insulating layers (109c _ 1, 109c _ 2) in, said number 2 (A2) said number 1 and number 2 sides (S1, S2) the region adjacent said number 1 regions (A1) can be a greater thickness than the.

Said horizontal conductive pattern (167c) said number 1 and number 2 the interlayer insulating layers (109c _ 1, 109c _ 2) overlap with those portions of said number 1 regions (A1), said number 1 and number 2 interlayer insulating layers (109c _ 1, 109c _ 2) (S1, S2) of said number 1 and number 2 sides edge gradually reduced thickness can.

Said horizontal conductive pattern (167c) in, said number 1 and number 2 interlayer insulating layers (109c _ 1, 109c _ 2) overlapping said number 2 area (A2) of said horizontal conductive pattern (167c) said number 1 and number 2 substantially uniform thickness of the portion of interlayer insulating layers (109c _ 1, 109c _ 2) (S1, S2) of said number 1 and number 2 sides near said horizontal conductive pattern (167c) thinner than thereof can.

Next, with reference to the 3 and 4 also with 8a and 8b also may also, said interlayer insulating layers (109) and said horizontal conductive patterns (167) for a hole of another aspect of a variation in mammals are also described.

Also with 3 and 4 also, the 8a and 8b may also reference, said interlayer insulating layers (109) are adjacent to each other apart from interlayer dielectric layer number 1 (109d _ 1) number 2 and an interlayer dielectric layer (109d _ 2) and include, said horizontal conductive patterns (167) one of horizontal conductive pattern (167d) said number 1 and number 2 the interlayer insulating layers (109d _ 1, 109d _ 2) can be disposed between.

Said number 1 and number 2 interlayer insulating layers (109d _ 1, 109d _ 2) (A1) of the upper part of said number 1 regions can be high density portion and a low portion. Said number 1 and number 2 interlayer insulating layers (109d _ 1, 109d _ 2) in regions of said number 1 (A1), said number 1 and number 2 (S1, S2) and the upper part of sides a portion adjacent higher concentration, said number 1 and number 2 sides (S1, S2) and remote portion thereof can low impurity concentration.

Said number 1 and number 2 interlayer insulating layers (109d _ 1, 109d _ 2) in regions of said number 1 (A1), said high impurity concentration may be thin portion, said low portion is formed on the impurity concentration thereof can. Said number 1 and number 2 interlayer insulating layers (109d _ 1, 109d _ 2) in regions of said number 1 (A1), the photoresist pattern having the can be said.

Said horizontal conductive pattern (167d) said number 1 and number 2 the interlayer insulating layers (109d _ 1, 109d _ 2) overlap with those portions of said number 1 regions (A1), the thin portion of the conductor layer thickness can be due to the photoresist pattern. Said number 1 and number 2 interlayer insulating layers (109d _ 1, 109d _ 2) overlapping said number 2 area (A2) of said horizontal conductive pattern (167d) said number 1 and number 2 substantially uniform thickness of the portion of interlayer insulating layers (109d _ 1, 109d _ 2) (S1, S2) of said number 1 and number 2 sides near said horizontal conductive pattern (167d) thinner than thereof can.

Next, with reference to the 9a and 9b also with 3 and 4 also may also, said interlayer insulating layers (109) and said horizontal conductive patterns (167) for a hole of another aspect of a variation in mammals are also described.

Also with 3 and 4 also, the 9a and 9b may also reference, said interlayer insulating layers (109) are adjacent to each other apart from interlayer dielectric layer number 1 (109e _ 1) number 2 and an interlayer dielectric layer (109e _ 2) and include, said horizontal conductive patterns (167) one of horizontal conductive pattern (167e) said number 1 and number 2 the interlayer insulating layers (109e _ 1, 109e _ 2) can be disposed between.

Said number 1 and number 2 interlayer insulating layers (109e _ 1, 109e _ 2) in, said number 1 and number 2 edge sides (S1, S2) impurity concentration gradually can be significantly reduced.

In one example, said number 1 and number 2 interlayer insulating layers (109e _ 1, 109e _ 2) said number 1 and number 2 sides from said number 1 and number 2 (S1, S2) impurity concentration in the interlayer insulating layers (109e _ 1, 109e _ 2) gradually to the appearance of the can be significantly reduced.

Said number 1 and number 2 interlayer insulating layers (109e _ 1, 109e _ 2) said number 1 and number 2 (S1, S2) from said number 1 and number 2 sides the interlayer insulating layers (109e _ 1, 109e _ 2) until the appearance of the thickness can be gradually increased.

Said horizontal conductive pattern (167e) said number 1 and number 2 the interlayer insulating layers (109e _ 1, 109e _ 2) (S1, S2) of said number 1 and number 2 sides edge gradually reduced thickness can.

Next, with reference to the 10a and 10b also with 3 and 4 also may also, said interlayer insulating layers (109) and said horizontal conductive patterns (167) for a hole of another aspect of a variation in mammals are also described.

Also with 3 and 4 also, the 10a and 10b also also reference, said interlayer insulating layers (109) are adjacent to each other apart from interlayer dielectric layer number 1 (109f _ 1) number 2 and an interlayer dielectric layer (109f _ 2) and include, said horizontal conductive patterns (167) one of horizontal conductive pattern (167f) said number 1 and number 2 the interlayer insulating layers (109f _ 1, 109f _ 2) can be disposed between.

Said number 1 and number 2 interlayer insulating layers (109f _ 1, 109f _ 2) in, said number 1 (A1) and (A2) said number 1 (P1) regions of said number 2 region portions can be substantially uniform concentration of impurities in, said number 2 area (A2) at a portion of said number 2 (P2) layer is as irrational.

Said number 1 and number 2 interlayer insulating layers (109f _ 1, 109f _ 2) said number 2 area (A2) of said number 2 (P2) can be a variation in the thickness of the photoresist pattern due in part. Said number 1 and number 2 interlayer insulating layers (109f _ 1, 109f _ 2) area (A2) of said number 2 (P2) of said number 2 portion is thicker at thickened portion is said number 1 region (A1) and (A2) said number 1 (P1) portions of said number 2 region can be substantially equal thickness and is. Said number 1 and number 2 interlayer insulating layers (109f _ 1, 109f _ 2) (A2) (P2) of said number 2 region of said number 2 area (A2) of said number 2 portion is thicker at thickened portion is adjacent said number 1 (P1) portions can be.

Said horizontal conductive pattern (167f) said number 1 and number 2 the interlayer insulating layers (109f _ 1, 109f _ 2) said number 2 area (A2) of said number 2 (P2) in the thin portion of the overlapping portion of gap between a conductor layer and may have.

Examples include embodiment, said number 1 and number 2 dielectric structures (121, 160) can be one of either the information storage layer. The number 1 and number 2 dielectric structures (121, 160) including examples of a gate dielectric for a 11a and 11b also each also through a browser-sensors other. Number 1 and number 2 is also 11a and 11b also dielectric structures (121, 160) including a cross-sectional drawing to explain the examples of a gate dielectric are disclosed.

First, also with 3 and 4 also, the reference also 11a, a dielectric structure said number 1 (121) is information storage layer (127) can be comprising. For example, a dielectric structure said number 1 (121) is tunnel dielectric (130), information storage layer (127) and barrier dielectric (124) can be a.

Said information storage layer (127) is said tunnel dielectric (130) on said barrier dielectric (124) can be interposed between. Said tunnel dielectric (130) is said vertical structures (133) of said semiconductor layer (136) can be adjacent, said barrier dielectric (124) said number 2 is a dielectric structure (160) can be adjacent.

Said tunnel dielectric (130) comprising silicon oxide and/or nitrogen doped silicon oxide (nitriogen doped silicon oxide) can be.

Said information storage layer (127) for storing information in non-volatile memory device such as a flash memory device can be layers. E.g., said information storage layer (127) trapped charge (charge) (trap) the charge trap layer (charge trap layer) stores information on the implementation being.

Said information storage layer (127) according to the operation of the memory element, said semiconductor layer (136) from said tunnel dielectric (130) trapping electrons injected through retention (retention) or, or said information storage layer (127) can be be erased electrons trapped in the material. E.g., said information storage layer (127) can be formed from silicon nitride. Said barrier dielectric (124) the characteristic whole energy band gap energy band gap greater than dielectric, e.g. silicon oxide can be formed.

A dielectric structure said number 2 (160) includes a blocking dielectric can be formed. For example, a dielectric structure said number 2 (160) is hafnium oxide and/or aluminum oxide dielectric such as can be formed.

Next, also with 3 and 4 also, the reference also 11b, a dielectric structure said number 1 (121) can be tunnel dielectric, a dielectric structure said number 2 (160) includes information storage layer (159a) and blocking dielectric (159b) can be a. Said information storage layer (159a) is said blocking dielectric (159b) said number 1 on a dielectric structure (121) can be interposed between. Said information storage layer (159a) can be the charge trap layer.

In the embodiment according to the technical idea of the present invention of variants of semiconductor also 12, 13a and 13b also describe also refers to less than 1000.

In the embodiment according to Figure 12 shows a plane view of a technical idea of the present invention also indicating a part of another example of semiconductor and, 13a is also of Figure 12 II a-II 'indicating the region taken along a line a cross-sectional drawing and, 13b of Figure 12 III a-III is also' cross-section taken along a line indicating an area are disclosed.

Also 12, 13a and 13b may also reference the, substrate (203) stacked alternately on the interlayer insulating layers (209) and horizontal conductive patterns (267) can be disposed.

Said interlayer insulating layers (209) and said horizontal conductive patterns (267) of said lowermost interlayer insulating layers is (209) the lowest layer can be disposed of. Said horizontal conductive patterns (267) on top of said pattern of interlayer insulating layers (209) of deposited on an interlayer dielectric layer (209) can be disposed. Said horizontal conductive patterns (267) top pattern during (267s) includes an insulating string cut pattern (214) can be separated by, said string selection line (SSL) implementation being described in Figure 2. Said horizontal conductive patterns (267) lowest pattern (267g) said ground select line (GSL) the implementation being described in Figure 2. Said horizontal conductive patterns (267) in, said top pattern (267s) and said lowest pattern (267g) between patterns (267w) said word lines (WL) the implementation being described in Figure 2.

Said interlayer insulating layers (209) is also 5a, 6a also, also 7a, also 8a, 9a and 10a also said interlayer insulating layers also of (109) with any one of a can be substantially the same.

Said interlayer insulating layers (109) top of the interlayer dielectric layer (109) onto a lower interlayer dielectric layer (215) can be disposed. Said dielectric layer (215) and said interlayer insulating layers (109) through vertical structures (233) can be disposed. Said vertical structures (233) between the dummy structures (232) can be arranged. Said dummy structures (232) is said string cut pattern (214) can be through.

In one example, said vertical structures (233) and said dummy structures (232) can be mutually the same structure.

In one example, said vertical structures (233) and said dummy structures (232) is also described with reference to said vertical structures such as 3 (133) can be the same structure. E.g., said vertical structures (233) and said dummy structures (232) the pattern of the core (139), said pattern of the core (139) covering the bottom surface and side surfaces of the semiconductor layer (136), said pattern of the core (139) pad pattern on (142) can be comprising.

Said interlayer insulating layers (209) in, said dummy structures (232) portion of the adjacent said impurity concentration to interlayer insulating layers (209) side surface of the impurity concentration thereof can lower than adjacent regions. Wherein, said interlayer insulating layers (209) in said interlayer insulating layers 3 and 4 also said impurity is also described with reference to (109) of said impurities can be the same.

In addition, said interlayer insulating layers (209) in said impurity concentration, said interlayer insulating layers (209) thickness, and said horizontal conductive patterns (267) is described with reference to the interlayer insulating layers also also 5a to 10b (109) in said impurity concentration, said interlayer insulating layers (109) thickness of, and said horizontal conductive patterns (167) can be the same.

Said vertical structures (233), said dummy structures (232) and said dielectric layer (215) an interlayer dielectric layer covering (245) can be disposed.

Said substrate (203) each other spaced apart isolation patterns (281) can be disposed. Said separation patterns (281) is said interlayer dielectric layer (245), said dielectric layer (215), said interlayer insulating layers (209), and said horizontal conductive patterns (267) can be through. Said separation patterns (281) is, in a plane, extending line shape be a number 1 (X) direction. Said interlayer insulating layers (209) and said horizontal conductive patterns (267) is said separation patterns (281) can be disposed between.

In one example, said separation patterns (281) conductive material, e.g., metal nitride (e.g., TiN, TaN or the like) and/or metal materials (for example, Ti, W or the like) can be comprising.

Said separation patterns (281) breakdown of insulating spacers (275) can be disposed. Said separation patterns (281) underlying said substrate (203) in the source impurity regions (278) can be disposed. Said source impurity regions (278) said common source line (CSL) the implementation being described in Figure 2.

With reference to fig. 14, in the embodiment according to technical idea of the present invention produced in variants of semiconductor of less than 1000. Figure 14 shows a cross-section of technical idea of the present invention also in the embodiment according to method for indicating variants are disclosed.

The reference also 14, such as described in Figure 4 and also 3 said substrate (103) and said substrate (103) on semiconductor substrate elements (303) can be disposed on. Said lower semiconductor substrate (303) on individual elements such as transistor including integrated circuit (TR) and can be positioned, such integrated circuit (TR) is said lower semiconductor substrate (303) and said substrate (103) that is located between the lower interlayer insulating layer (ILD) can be covered by.

Next, also with 3 and 4 also, in the embodiment according to technical idea of the present invention with reference to the method for forming a semiconductor device of 15 to 22 are also produced in one example of less than 1000.

Figure 22 shows a semiconductor device in the embodiment according to one example of method of technical idea of the present invention to also 15 also to account for cross section are disclosed. 15 Also to Figure 22 shows a I a-I ' indicating the region taken along a line a cross-sectional drawing of Figure 3 are disclosed.

The reference also 3 and also 15, substrate (103) stacked alternately on the interlayer insulating layers (109) and a sacrificial layers (112) can be formed. Said substrate (103) is formed of a semiconductor material such as silicon can be a semiconductor substrate. Said interlayer insulating layers (109) and said sacrificial layers (112) is laminated structure (106) can be constituting.

In one example, said interlayer insulating layers (109) can be formed of silicon.

In one example, said interlayer insulating layers (109) an insulating oxide series can be formed. E.g., said interlayer insulating layers (109) (C) including a high-silicon oxide can be formed.

Said sacrificial layers (112) is said interlayer insulating layers (109) with a material layer having an etch selectivity, e.g. made of a nitride can be formed. E.g., said sacrificial layers (112) can be formed from silicon nitride.

Said laminated structure (106) onto a lower interlayer dielectric layer (115) can be formed. Said dielectric layer (115) is said interlayer insulating layers (109) can be formed to the same.

The reference also 3 and also 16, said dielectric layer (115) and said laminated structure (106) through holes (118) can be formed. Said holes (118) number 1 on sidewalls of dielectric structures (121) can be formed. Said holes (118) vertical structures (133) can be formed.

Said vertical structures (133) the dielectric structures forming said number 1 (121) having said substrate (103) semiconductor layer overlying (136) and a trench crossing the active region, said semiconductor layer (136) on said holes (118) core patterns partially fills (139) is formed, said core patterns (139) having said substrate (103) are formed on pad material, said pad material layer planarized to pad patterns (142) comprising forming can be. Said core patterns (139) blended with an insulating material can be formed of silicon. Said semiconductor layer (136) is formed on a semiconductor properties can be. Said pad patterns (142) N doped is formed on the can.

17 Also and also 3 reference surface, said vertical structures (133) and said upper insulating layer (145) on capping layer (146) can be formed. Said capping layer (146) is said interlayer insulating layers (109) can be made of material harder than. E.g., said capping layer (146) silicon nitride such as silicon oxide can be formed compared to a harder material.

Said capping layer (146), said upper insulating layer (145) and said laminated structure (106) penetrate said substrate (103) exposing openings (148) can be formed. Said openings (148) by said laminated structure (106) of said interlayer insulating layers (109) of side surfaces can be exposed.

The reference 3 and also 18 also, in one example, said impurities interlayer insulating layers (109) and said dielectric layer (115) into the diffusion process (151) regions in said interlayer insulating layers (109) and an upper interlayer dielectric layer (115) for diffusing impurities within the be.

In one example, said sacrificial layers (112) and said capping layer (146) is said interlayer insulating layers (109) and said dielectric layer (115) can be formed to be more rigidly. The, said diffusion process (151) during, said interlayer insulating layers (109) and said dielectric layer (115) the diffusion velocity of said impurities in said sacrificial layers (112) and said capping layer (146) in the diffusion velocity of said impurities can be faster. Said capping layer (146) said substrate is said impurities (103) in a direction vertical to said dielectric layer (115) serves to diffuse into can be prevent.

In one example, said impurity is said interlayer insulating layers (109) and said dielectric layer (115) while said diffused into the interlayer insulating layers (109) and said sacrificial layers (112) and said interface between the sacrificial layers (112) of said sacrificial layer between top of dielectric layer (115) on the interface between the partially to an accumulated can be. The, said impurity is said interlayer insulating layers (109) and said dielectric layer (115) in said than interlayer insulating layers (109) and said sacrificial layers (112) and said interface between the sacrificial layers (112) of said sacrificial layer between top of dielectric layer (115) can be increased concentration at the interface between the.

Said impurity is said interlayer insulating layers (109) and said dielectric layer (115) of the periodic table of elements (etch rate) etch rate can be a varying element. For example, elements such as said impurity is boron or the like but may be, of the present invention is not limited to technical idea. For example, e.g., said interlayer insulating layers (109) of said impurity is nitrogen (N), hydrogen (H), chlorine (Cl), comprising flow five starting material (F) or sulfur (S) can be.

In one example, said interlayer insulating layers (109) and said dielectric layer (115) such as also taught 5b in said diffusion thereof can. However, technical idea of the present invention is not limited to. E.g., said interlayer insulating layers (109) and said dielectric layer (115) said diffusion process in said diffusion (151) of process conditions (e.g., temperature, process time or process source gas amount and the like) for varying said interlayer insulating layers (109) and said dielectric layer (115) and an impurity concentration of said impurity in said horizontal diffusion can be varying the depth. E.g., said interlayer insulating layers (109) and said dielectric layer (115) also described in said 6b diffusion such as concentration, also taught 7b such as concentration, concentration such as also taught 8b, such as taught 10b also taught 9b concentration or also can be formed such as concentration. Said diffusion process (151) is performed on the plant or at a high temperature using, or plasma into the space between the plasma doping using can be put.

In one example, said diffusion process (151) is said impurities said interlayer insulating layers (109) and said dielectric layer (115) before or after diffused into, said interlayer insulating layers (109) and said dielectric layer (115) into the additional elements (additional element) can be diffusing. the additional element is said interlayer insulating layers (109) and said dielectric layer (115) can be more rigidly a serves.

In one example, said additional element is said interlayer insulating layers (109) and said dielectric layer (115) areas uniformly dispersed within and to be injected, said interlayer insulating layers (109) and said dielectric layer (115) areas in, said impurity concentration also 6b, 8b or 10b also formed such as concentration can be also described. Said impurity is boron (B) or phosphorous (P) may be elements such as, said additional element is an element such as carbon (C) can be.

In one example, this additional element is in Figure 15 said interlayer insulating layers (e.g., carbon (C)) (109) (in a-situ) while forming said interlayer dielectric layers to in - situ (109) into a disapproval. This additional element is said interlayer insulating layers (109) such as warp or the collapse of a nitride can be prevent.

The reference also 19 and also 3, a stand-alone said sacrificial layers (of Figure 18 112) number empty waiting to spaces (157) can be formed. Said sacrificial layers (of Figure 18 112) include wet etching using the process number can be a stand-alone. For example, the dilution said sacrificial layers (of Figure 18 112) such as phosphate using mold opening number can be a stand-alone.

In one example, a number of the housing while said capping layer (of Figure 18 146) stand-alone said sacrificial layers (of Figure 18 112) number 1308. wetting ability.

Said layer is a sacrificial layers (of Figure 18 112) number industry association, said interlayer insulating layers (109) and said dielectric layer (115) be a portion of the etched. For example, sacrificial layers (of Figure 18 112) said number to said selectively industry association, said interlayer insulating layers (109) and said dielectric layer (115) that the impurities are implanted in said etching said low VOC region is high due to the low etch rate, said regions are implanted into said high impurity concentration of the low etching the sidewall more than said interlayer insulating layers (109) and said dielectric layer (115) reduced than the thickness of the can. The, said interlayer insulating layers (109) and said dielectric layer (115) of said along sides of, said interlayer insulating layers (109) also the thickness of the 5a, 6a also, also 7a, 8a also, 9a or 10a also described also can be formed as shown with.

Said openings (148) adjacent said interlayer insulating layers (109) since the thickness of one or more areas, said openings (148) adjacent to said empty spaces (157) of portals can be relatively large. The, said empty spaces (157) for increasing size without the entrance of a selectively etched, said etching said sacrificial layers (of Figure 18 112) industry a number said empty spaces (157) can be the entrance of may increase its size.

In addition, said empty spaces (157) for increasing the entrance of a size of a photolithography process since there is no need, said number 1 gate dielectric (121) can be minimize or prevent silicon oxide layer is formed. The, improved reliability can be.

Also 20 also 3 and reference surface, said empty spaces (157) having said substrate (103) number 2 on a dielectric structure (160) can be a trench crossing the active region. A dielectric structure said number 2 (160) on said empty spaces (157) horizontal filling conductive layer (166) can be formed. Said horizontal conductive layer (166) is said openings (148) formed along the sidewalls and while said openings (148) for complete filling thereof can not. Said horizontal conductive layer (166) metal nitride layer (e.g., TiN layer) and a metal layer (e.g., W layer) can be formed.

A dielectric structure said number 1 (121) and a dielectric structure said number 2 (160) is also taught said 11a 11b also taught said gate dielectric structure or gate dielectric structure can be formed.

Said empty spaces (157) since the entrance of a size is increased, said empty spaces (157) in said horizontal conductive layer (166) can be formed without a void such as excess.

The reference also 3 and also 21, said horizontal conductive layer (166) is formed by etching the horizontal conductive patterns (167) can be formed. Said horizontal conductive patterns (167) is said interlayer insulating layers (109) a smaller width than can be formed.

The reference also 3 and also 22, said openings (148) on sidewalls of an insulating spacers (175) can be formed. Said insulating spacers (175) such as an insulating material can be formed of silicon.

An ion implantation process is performed, said openings (148) exposed by said substrate (103) in the source impurity regions (178) can be formed. Said source impurity regions (178) N the second conductive type can be formed.

Also with 3, 4 also again reference surface, said source impurity regions (178) on said openings (148) separation patterns filling (181) can be formed. In one example, said separation patterns (181) can be conductive material. E.g., said separation patterns (181) metal silicide (e.g., such as TiSi), metal nitride (e.g., such as TiN) and/or metal (e.g., W or the like) can be formed.

Examples of embodiment according to technical idea of the present invention, said interlayer insulating layers (109) (A1, A2) regions different in concentration of impurities can be formed. The interlayer insulating layers (109) different in concentration of impurities (A1, A2) regions may have different etching rates. The interlayer insulating layers (109) and the upper using the process for forming a semiconductor device can be reduced, such reduction leads to reject yield and productivity can be increased.

Examples of embodiment according to technical idea of the present invention, regions of different concentration of impurities including said interlayer insulating layers (109) which can be used for word line gate electrode or between said horizontal conductive patterns (167) can be formed. Said interlayer insulating layers (109) (A1) may have a higher concentration at a region adjacent to , the interlayer insulating layers having thicknesses greater than said thin (109) areas (A1) interposed between horizontal conductive patterns (167) is relatively thickness thereof can. Thus, the electrical characteristics of semiconductor gate electrode or word line can be so increased.

Or more, for example with reference to the attached drawing of the present invention embodiment described but, in the present invention is provided to the present invention is technical idea or person with skill in the art without changing its essential features can be understand other specific embodiment can form are disclosed. The exemplary embodiment described above are not limited to examples in all of which must not understood to 2000.