NIEDRIG-TEMPERATUR-VERFAHREN ZUR HERSTELLUNG VON GESCHICHTETEN SUPERGITTERMATERIALEN

Isolierschicht-Feldeffekttransistor

Isolierschicht-Feldeffekttransistor (MISFET) mit Drain (104), Source (106) und Gate (102), der dazu eingerichtet ist, bei angesteuertem Gate (102) in einem Kanalgebiet zwischen Drain (104) und Source (106) einen Kanal auszubilden, der einen Stromfluss zwischen Source (106) und Drain (104) ermöglicht, wobei in dem Isolierschicht-Feldeffekttransistor (100) integriert ein spannungsabhängiger Vorwiderstand (108) ausgebildet ist, der zwischen Source (106) und dem Kanalgebiet angeordnet und dazu eingerichtet ist, den Stromfluss zwischen Source (106) und Drain (104) zu beeinflussen.

PROCEDURE FOR THE PRODUCTION OF SCHICHTIGEN SUPERCLATTICE MATERIALS.

USE OF SCHICHTIGEM OVER LATTICE MATERIAL

Method and apparatus for a surface-mountable device for prot ection against electrostatic damage to electronic components

Glasartiges Material mit einem elektrisch leitenden Überzug

Non reversible semiconductor switching element - consists of resistance of polycrystalline silicon with high specific resistance

Composing for electronic circuit

VERFAHREN ZUR HERSTELLUNG DOTIERTER BST-SCHICHTEN UND KONDENSATOREN FÜR INTEGRIERTE SCHALTUNGEN MIT MAGNESIUM DOTIERTEN BST SCHICHTEN

VERFAHREN ZUR HERSTELLUNG VON SCHICHTIGEN SUPERGITTERMATERIALIEN.

LOW TEMPERATURE PROCESS FOR FABRICATING LAYERED SUPERLATTICE MATERIALS AND MAKING ELECTRONIC DEVICES INCLUDING SAME

A liquid precursor containing a metal is applied to a first electrode, RTP backed at a temperature of 700 ~C, and annealed at the same temperature from 3 to 5 hours to form a layered superlattice material. A second electrode is formed to form a capacitor, and a second anneal is performed at a temperature of 700 ~C. If the material is strontium bismuth tantalate, the precursor contains u mole-equivalents of strontium, v mole-equivalents of bismuth, and w mole-equivalents of tantalum, where 0.8 <= u <= 1.0, 2.0 <= v <= 2.3, and 1.9 <= w <= 2.1.

VOLTAGE SENSITIVE RESISTOR (VSR) READ ONLY MEMORY

Disclosed is a voltage sensitive resistor (VSR) write once (WO) read only memory (ROM) device which includes a semiconductor device and a VSR connected, to die semiconductor device. The VSR WO ROM device is a write once read only device. The VSR includes a CVD titanium nitride layer having residual titanium-carbon bonding such that the VSR is resistive as formed and can become less resistive by an order of 10 2 , more preferably 10 3 and most preferably 10 4 when a predetermined voltage and current are applied to the VSR. A plurality of the VSR WO ROM devices may be arranged to form a high density programmable logic circuit in a 3-D stack. Also disclosed are methods to form the VSR WO ROM device.

Electrical circuit components

... 1,079,891. U/V. irradiation apparatus. INTERNATIONAL BUSINESS MACHINES CORPORATION. Jan. 15, 1965 [Jan. 24, 1964], No. 1796/65. Heading H5R. [Also in Division H1] An electrical circuit component consisting of a layer of an ethylenically unsaturated organic polymer sandwiched between two metallic electrodes (see Division H1) is produced by a method in which the organic compound is deposited on one of the electrodes in monomeric form and is then polymerized by exposure to u/v. radiation. The irradiation apparatus comprises an evacuated chamber 36 (see Fig. 3), in which a substrate 45 is mounted on a holder 43 in a first position A, over a source 53 of vaporized metal (Pb, Cu, or Au) in an evacuated chamber. The metal is deposited through a mask on to the substrate to form a first electrode. The holder 43 is then moved to a second position B and an ethylenically unsaturated monomer, e.g. butadiene, styrene, acrylic acid, acrolein or any of a large number of other compounds mentioned in the ...

METHOD AND APPARATUS FOR A SURFACE-MOUNTABLE DEVICE FOR PROTECTION AGAINST ELECTROSTATIC DAMAGE TO ELECTRONIC COMPONENTS

The thin film, circuit device is a subminiature overvoltage protection device in a surface mountable configuration for use in printed circuit board or thick film hybrid circuit technology. The surface mountable device (SMD) is designed to protect against electrostatic discharge (ESD) damage to electronic components. The circuit protection device comprises three material subassemblies. The first subassembly generally includes a substrate carrier, electrodes, and terminal pads for connecting the protection device (60) to a PC board. The second subassembly includes a voltage variable polymer material with non-linear characteristics, and the third subassembly includes a cover coat for protecting other elements of the circuit protection device.

Device with conductivity maintained by a field

Precursors and processes for making metal oxides

Surface-mounted fuse device

A thin film surface-mount fuse having two material subassemblies. The first subassembly includes a fusible link, its supporting substrate and terminal pads. The second subassembly includes a protective layer which overlies the fusible link so as to provide protection from impacts and oxidation. The protective layer is preferably made of a polymeric material. The most preferred polymeric material is a polycarbonate adhesive. In addition, the most preferred supporting substrate is an FR-4 epoxy or a polyimide.

Method of making metal polyoxyalkylated precursor solutions

A liquid precursor solution for use according to a method of manufacturing metal oxide electronic components includes a polyoxyalkylated metal complex dispersed in an alkane solvent. The alkane solvent is preferably n-octane.

Schaltbares Widerstands-Bauelement und Verfahren zu seiner Herstellung

Ein schaltbares Widerstands-Bauelement 10, das einen veränderlichen elektrischen Widerstand aufweist, umfasst eine erste Elektrode 1, die ein erstes elektrisch leitfähiges Elektrodenmaterial umfasst, eine zweite Elektrode 2, die ein zweites elektrisch leitfähiges Elektrodenmaterial umfasst, und eine Barriereschicht 3, die zwischen der ersten Elektrode und der zweiten Elektrode angeordnet ist, wobei das Widerstands-Bauelement eine elektrische Leitfähigkeit aufweist, die durch Anlegen einer elektrischen Spannung zwischen der ersten Elektrode 1 und der zweiten Elektrode 2 veränderlich ist, und wobei das erste Elektrodenmaterial ein Chalkogenid mit metallischer Leitfähigkeit umfasst, das zweite Elektrodenmaterial ein Metall umfasst, und die Barriereschicht 3 eine Schichtzusammensetzung aufweist, die mindestens teilweise das erste Elektrodenmaterial und mindestens teilweise das zweite Elektrodenmaterial enthält. Es werden auch ein Verfahren zur Herstellung und Anwendungen des Widerstands-Bauelements ...

PROCEDURE AND DEVICE FOR AN SMD ELEMENT FOR PROTECTING THE ELECTRICAL COMPONENTS FROM ESD

Surface-mounted fuse device

Electroconducting covering

Non reversible semiconductor switching element - consists of resistance of polycrystalline silicon with high specific resistance

Switching element which is used as a semiconductor memory, can operate from low voltage and low current. It can be manufactured by the conventional LSI process. It is an inert memory operating on low voltage and current. The semiconductor switching element (10) consists of a resistance (11) of polycrystalline silicon with a high specific resistance. There are terminal electrodes (12,13) made from a metal or a semiconductor connected on both sides of the resistance. The switching operation is carried out by making use of the face that the resistance of the silicone resistance varies in one direction only dependent on the size of the operating voltage.

Electroconducting covering

세라믹 전자 부품 및 그 제조 방법

세라믹 소자 표면에만 선택적으로 코팅막을 형성할 수 있는 세라믹 전자 부품 및 그 제조 방법을 제공한다. 배리스터(10)는 세라믹 소자(1)와, 세라믹 소자(1)의 표면에 마련된 코팅막(8) 및 외부전극(6a, 6b)을 포함하고 있다. 코팅막(8)은 황산, 술폰산, 카르복실산, 인산, 포스폰산, 불산 중 적어도 1종의 음이온성 이온을 포함하는 수지 함유 용액을 배리스터(10)에 부여함으로써, 세라믹 소자(1)의 세라믹 표면에 선택적으로 형성되어 있다. 코팅막(8)은 황산, 술폰산, 카르복실산, 인산, 포스폰산, 불산 중 적어도 1종의 음이온성 이온을 포함하는 수지로 형성되어 있다.

CHEMICAL VAPOR DEPOSITION OF THICK DEPOSITS OF ISOTROPIC BORON NITRIDE

VERWENDUNG VON SCHICHTIGEM ÜBERGITTER MATERIAL

Verfahren zum chemischen Niederschlagen von relativ dicken Schichten aus isotropem Bornitrid aus dem Dampf

CHEMICAL VAPOR DEPOSITION OF THICK DEPOSITS OF ISOTROPIC BORON NITRIDE

DISPOSITIF DE PROTECTION INTEGRE CONTRE LES SURTENSIONS D'UN CIRCUIT ELECTRONIQUE, ET CIRCUIT ELECTRONIQUE PROTEGE PAR CE DISPOSITIF

L'INVENTION CONCERNE UN DISPOSITIF DE PROTECTION DES CIRCUITS ET SEMICONDUCTEURS CONTRE LES SURTENSIONS D'ORIGINE STATIQUE OU SURCHARGES DYNAMIQUES EN TENSION. LE DISPOSITIF SELON L'INVENTION CONSISTE A DEPOSER SUR LE SUPPORT 3 ET SUR LES CONNEXIONS 4, 5 D'ACCES EXTERIEUR DU CIRCUIT UNE RESISTANCE NON LINEAIRE OU VARISTANCE 6, DONT LA COMPOSITION ET L'EPAISSEUR DU DEPOT SONT CHOISIES POUR QUE LA TENSION DE SEUIL V DE LA VARISTANCE SOIT INFERIEURE A LA SURTENSION DANGEREUSE POUR LE CIRCUIT. SELON UNE FORME PREFEREE DE L'INVENTION, LA VARISTANCE 6 EST DEPOSEE PAR SERIGRAPHIE EN ANNEAU RECOUVRANT LES CONNEXIONS 4, 5 D'ACCES EXTERIEUR, UNE METALLISATION 7 DEPOSEE SUR LA VARISTANCE 6 ASSURANT LA MISE A LA MASSE EN CAS DE SURTENTION. SELON UNE AUTRE FORME, LA MISE A LA MASSE EST ASSUREE PAR LES CONNEXIONS D'ACCES ELLES-MEMES. APPLICATION AUX CIRCUITS MOS ET AUX FET EN MICROBOITIERS CERAMIQUES OU AUX CIRCUITS HYBRIDES.

SAFETY DEVICE INTEGRATES AGAINST OVERPRESSURES Of an ELECTRONIC CIRCUIT, AND ELECTRONIC CIRCUIT PROTECTS BY THIS DEVICE

The device is intended for the protection of circuits and semiconductors against static overvoltages or dynamic voltage overloads. The device according to the invention comprises the deposition on the support (3) and on the external access connections (4, 5) to the circuit of a non-linear resistance or varistance (6), of which the composition and the thickness of the deposition are selected so that the threshold voltage (Vo) of the varistance is lower than the critical overvoltage for the circuit. According to a preferred embodiment of the invention, the varistance (6) is deposited by serigraphy as a ring covering the external access connections (4, 5), and metallization (7) deposited on the varistance (6) provides for the grounding in case of overvoltage. According to another embodiment, the grounding is provided by the access connections themselves. Application to MOS and FET circuits in ceramic micro-packages or to hybrid circuits.

Method of protecting a surface-mount fuse device

A thin film surface-mount fuse having two material subassemblies. The first subassembly includes a fusible link, its supporting substrate and terminal pads. The second subassembly includes a protective layer which overlies the fusible link so as to provide protection from impacts and oxidation. The protective layer is preferably made of a polymeric material. The most preferred polymeric material is a polycarbonate adhesive. In addition, the most preferred supporting substrate is an FR-4 epoxy or a polyimide.

Microvaristor-based overvoltage protection

The disclosure relates to an overvoltage protection means containing ZnO microvaristor particles for protecting electrical elements and a method to produce the means. Single microvaristor particles are placed in an arrangement having a monolayer thickness and are electrically coupled to the electrical element to protect it against overvoltages. Embodiments, among other things, relate to: 1-dimensional or 2-dimensional arrangements of microvaristor particles; placement of single microvaristors on a carrier; the carrier being planar or string-like, being structured, being a sticky tape, having fixation means for fixing the microvaristors, or having electrical coupling means. The monolayered overvoltage protection means allows very tight integration and high flexibility in shaping and adapting it to the electric or electronic element. Furthermore, reduced capacitance and hence reaction times of overvoltage protection are achieved.

Low temperature process for fabricating layered superlattice materialsand making electronic devices including same

Variable resistor element and its manufacturing method

A variable resistance element comprises a variable resistor of strongly-correlated material sandwiched between two metal electrodes, and the electric resistance between the metal electrodes varies when a voltage pulse is applied between the metal electrodes. Such a switching operation as the ratio of electric resistance between low and high resistance states is high can be attained by designing the metal electrodes and variable resistor appropriately based on a definite switching operation principle. Material and composition of the first electrode and variable resistor are set such that metal insulator transition takes place on the interface of the first electrode in any one of two metal electrodes and the variable resistor by applying a voltage pulse. Two-phase coexisting phase of metal and insulator phases can be formed in the vicinity of the interface between the variable resistor and first electrode by the work function difference between the first electrode and variable resistor.

VORLÄUFER UND VERFAHREN ZUR HERSTELLUNG VON METALLOXIDEN

VERFAHREN UND VORRICHTUNG FÜR EIN SMD-ELEMENT ZUM SCHÜTZEN DER ELEKTRISCHEN KOMPONENTEN GEGEN ESD

Surface-mounted fuse device

PRECURSORS AND PROCESSES FOR MAKING METAL OXIDES

A first metal, an alcohol, and a carboxylic acid are reacted to form a metal alkoxycarboxylate which is then reacted with an alkoxide and/or a carboxylate of a second metal to form a precursor. Alternatively, a metal carboxylate and a metal alkoxide are combined and heated to form a precursor. In either alternative, the precursor includes all or most of the metal-oxygen-metal bonds of a desired metal oxide and a carboxylate ligand. The precursor is applied to a substrate (18, 38, 47, 75), dried and annealed to form the metal oxide (12, 30, 48, 60), such as BST. The metal-oxygen-metal bonds in the precursor permit the desired metal oxide (12, 30, 48, 60) to be formed from the precursor in one step, providing excellent thin films suitable for integrated circuits. The carboxylate ligand provides stability to the precursor allowing it to be stored for periods common in large scale manufacturing.

Method of making integrated circuit capacitors

Layered superlattice material applications

THIN FILM VARISTOR

SAFETY DEVICE INTEGRATES AGAINST OVERPRESSURES Of an ELECTRONIC CIRCUIT, AND ELECTRONIC CIRCUIT PROTECTS BY THIS DEVICE

dispositivo semicondutor nanoestruturado do tipo varistor constituído de polímero condutor e óxido de zinco e metais

VARISTOR-TYPE, NANOSTRUCTURED SEMICONDUCTOR DEVICE MADE OF CONDUCTING POLYMER, ZINC OXIDE AND METALS

The present invention relates to a semiconducting nanodevice comprising a heterojunction made of a conducting polymer (PANI) and zinc oxide (ZnO). Electronic devices having specific electric characteristics can be obtained by controlling the doping properties, the degree of oxidation of the conducting polymer and the physical dimensions of the zinc oxide films. This technology can be used to produce a semiconducting p-n junction having with rectifier diode characteristics, as well as a varistor-type device with controlled breakdown voltages, and having unprecedented features for which protection is sought. The device comprises a metallic film made of either gold or aluminium, a thin polyaniline film of various thicknesses and sizes, a zinc oxide film of various thickness and sizes, and finally metallic contacts made of aluminium or gold as depicted in figure 1. The electric characteristics of these new devices are improved over those of commercially available devices, since they constitute organic hybrid devices which are cheaper and easier to produce. Another important aspect is the possibility to control the breakdown voltage of the device by varying the degree of doping and the thickness of the active components.

Process for fabricating layered superlattice materials and making electronic devices including same

A liquid precursor containing a metal is applied to a substrate, RTP baked, and annealed to form a layered superlattice material. Prebaking the substrate and oxygen in the RTP and anneal is essential, except for high bismuth content precursors. Excess bismuth between 110% and 140% of stoichiometry and RTP temperature of 725° C. is optimum. The film is formed in two layers, the first of which uses a stoichiometric precursor and the second of which uses an excess bismuth precursor. The electronic properties are so regularly dependent on process parameters and material composition, and such a wide variety of materials are possible, that electronic devices can be designed by selecting from a continuous record of the values of one or more electronic properties as a continuous function of the process parameters and material composition, and utilizing the selected process and material composition to make a device.

Electronic circuit device and manufacturing method

Geschichteter Koerper mit durch Bestrahlung anregbarer elektrischer Leitfaehigkeit und Verfahren zu seiner Herstellung

IRREVERSIBLE SEMICONDUCTOR SWITCHING ELEMENT AND SEMICONDUCTOR MEMORY DEVICE UTILIZING THE SAME

Specification Title of the Invention Irreversible Semiconductor Switching Element and Semiconductor Memory Device Utilizing the Same Abstract of the Disclosure The switching element comprised a high resistivity polycrystalline silicon resistor whose resistance irreversi-bly decreases to a small value at a threshold voltage when the voltage across the resistor reaches the threshold voltage. A semiconductor memory devise is constituted by using the switching element as a memory cell, and a semiconductor gate element for controlling the current flowing through the semiconductor switching element. The switching element has simple construction and can operate with low voltage and low current. It is not necessary to blow fuse or destroy diode as in the prior art semiconductor switching element.

Surface-mountable device having a voltage variable polgmeric material for protection against electrostatic damage to electronic components

The thin film, circuit device is an subminiature overvoltage protection device in a surface mountable configuration for use in printed circuit board or thick film hybrid circuit technology. The surface mountable device (SMD) is designed to protect against electrostatic discharge (ESD) damage to electronic components. The circuit protection device includes three material subassemblies. The first subassembly generally includes a substrate carier, electrodes, and terminal pads for connecting the protection device 60 to a PC board. The second subassembly includes a voltage variable polymer material with non-linear characteristics, and the third subassembly includes a cover coat for protecting other elements of the circuit protection device.

Metal polyoxyalkylated precursor solutions in an octane solvent and method of making the same

A liquid precursor solution for use according to a method of manufacturing metal oxide electronic components includes a polyoxyalkylated metal complex dispersed in an alkane solvent. The alkane solvent is preferably n-octane.

Surface-mounted fuse device

A thin film surface-mount fuse having two material subassemblies. The first subassembly includes a fusible link, its supporting substrate and terminal pads. The second subassembly includes a protective layer which overlies the fusible link so as to provide protection from impacts and oxidation. The protective layer is preferably made of a polymeric material. The most preferred polymeric material is a polycarbonate adhesive. In addition, the most preferred supporting substrate is an FR-4 epoxy or a polyimide.

OBERFLÄCHENMONTIERTE SICHERUNGSVORRICHTUNG

ELECTRIC CURRENT CONTROLLING DEVICES

... 1442750 Semiconductor devices GENERAL ELECTRIC CO Ltd 30 Nov 1973 [18 Dec 1972] 58311/72 Heading H1K A threshold switch switchable from a high to a low resistance state by a voltage above a threshold comprises at least two identical switching devices connected in series, each device comprising a switching element and first and second electrodes, the second electrode of each device being connected to the first electrode of the succeeding one. Each device may comprise a first molybdenum electrode 6 on a glass substrate 5, a silica layer 7 having an aperture 8, a switching element 10 of 15 atomic per cent germanium and 85 atomic per cent tellurium and a second electrode of a thin chromium film 11 and a thicker gold layer 12. The material layers of each device may be simultaneously deposited by sputtering or vacuum deposition and shaped by masking or photolithographic techniques. Preferably the molybdenum is sputtered, the remaining materials being vacuum deposited. The gold electrode may be ...

SURFACE-MOUNTED FUSE DEVICE

A thin film surface-mount fuse (58) having two material subassemblies. The first subassembly includes a fusible link (42), its supporting substrate (13) and terminal pads (34, 36). The second subassembly includes a protective layer (56) which overlies the fusible link (42) so as to provide protection from impacts and oxidation. The protective layer (56) is preferably made of a polymeric material. The most preferred polymeric material is a polycarbonate adhesive. In addition, the most preferred supporting substrate (13) is an FR-4 epoxy or a polyimide.

Thin film type varistor and method thereof

THIN-FILM RESISTOR HAVING A LAYER STRUCTURE AND METHOD FOR PRODUCING A THIN-FILM RESISTOR HAVING A LAYER STRUCTURE

The invention describes a thin-film resistor (122) having a layer structure having a Ti layer and a TiN layer, wherein a layer thickness of the Ti layer and a layer thickness of the TiN layer are selected such that a resultant thermal coefficient of the resistor (TCR) is less than 1000 ppm/°C.

VARISTOR-TYPE, NANOSTRUCTURED SEMICONDUCTOR DEVICE MADE OF CONDUCTING POLYMER, ZINC OXIDE AND METALS

The present invention relates to a semiconducting nanodevice comprising a heterojunction made of a conducting polymer (PANI) and zinc oxide (ZnO). Electronic devices having specific electric characteristics can be obtained by controlling the doping properties, the degree of oxidation of the conducting polymer and the physical dimensions of the zinc oxide films. This technology can be used to produce a semiconducting p-n junction having with rectifier diode characteristics, as well as a varistor-type device with controlled breakdown voltages, and having unprecedented features for which protection is sought. The device comprises a metallic film made of either gold or aluminium, a thin polyaniline film of various thicknesses and sizes, a zinc oxide film of various thickness and sizes, and finally metallic contacts made of aluminium or gold as depicted in figure 1. The electric characteristics of these new devices are improved over those of commercially available devices, since they constitute organic hybrid devices which are cheaper and easier to produce. Another important aspect is the possibility to control the breakdown voltage of the device by varying the degree of doping and the thickness of the active components.

METHOD OF MAKING A VOLTAGE ACTUATABLE SWITCH

VORLÄUFER UND VERFAHREN ZUR HERSTELLUNG VON METALLOXIDEN

THIN FILM VARISTOR

THIN FILM VARISTOR ABSTRACT OF THE DISCLOSURE A thin film metal oxide-metal oxide heterojunction nonlinear resistor is described. A non-symmetrical embodiment wherein zino oxide and bismuth oxide are employed provides exemplary nonlinear characteristics for triggering or transient suppression applications. A symmetrical embodiment which includes a sandwich-like structure of one metal oxide between layers of a second metal oxide provides similar characteristics in a symmetrical form.

IRREVERSIBLE SEMICONDUCTOR SWITCHING ELEMENT AND SEMICONDUCTOR MEMORY DEVICE UTILIZING THE SAME

전류 전환 트랜지스터

... 본 발명에 따르면, 전자 장치 및 전자 장치를 제조하는 방법이 개시된다. 전자 장치는 반도체 물질의 몸체, 및 각각의 단자들을 형성하기 위해 적어도 3개의 도전성 접점들을 형성하는 도전성 물질을 포함한다. 반도체 물질과 도전성 접점들은 전자 장치를 형성하기 위해 적어도 부분적으로 오버랩되어, 어느 한 쌍의 단자들 사이의 전자 장치의 전기적 특성들은 배리스터의 전기적 특성들에 대응한다. 반도체 물질의 몸체는 인쇄 또는 코팅에 의해 적층된 층일 수 있다. 각 쌍의 단자들 사이의 배리스터 특성들은, 제 1 단자로의 양 전류가 있을 때, 양 전위가 인가되는 제 2 단자를 통한 미세 전류, 및 제 2 단자에 대하여 음 전위로 유지되는 제 3 단자로부터의 양 전류가 있는 방식으로, 하나의 단자와 나머지 2개의 단자들 사이의 전류의 전환을 가능하게 한다. 제 1 단자의 바깥으로의 음 전류가 있을 때, 제 2 단자로의 양 전류, 및 제 3 단자를 통한 미세 전류가 있다.

Electronic circuit device and manufacturing method

An electronic element having at least a pair of electrodes (4,5) is formed on a substrate (1). A varistor element (10) is formed on the substrate, the varistor element including a pair of electrodes (11, 12) and a varistor insulating film (13). When a surge voltage is applied across the pair of electrodes (11, 12) of the varistor element (10), a surge current flows through the varistor insulating film (13). One electrode (11) of the varistor element is connected to one electrode (4) of the electronic element, and the other electrode (12) of the varistor element is connected to the other electrode (5) of the electronic element. Thus, a countermeasure against electrostatic surges is provided.

DISCONTINUOUS THIN FILM MULTI-STABLE STATE RESISTORS

... 1,211,669. Multi-stable resistors. CORNING GLASS WORKS. 4 July, 1969, No. 33736/69. Heading H1K. [Also in Division C7] A discontinuous thin film multi-stable resistor comprises, on a dielectric substrate 12, a plurality of electrically conductive discontinuous thin films 20, 24 connected in parallel, each film having a pair of distinct resistance states, one being a low resistance and the other a high resistance state, the resistor switching from low to high resistance at a given potential and from high to low resistance at a different given potential. The thin films are made of metal, such as gold, covered with a barrier layer 22, 26 of a material such as barium oxide, silicon dioxide, tantalum pentoxide or titanium dioxide to stabilize the layer characteristics. Each film in a parallel network has a different switching potential and a different open circuit resistance, the film having the highest open circuit resistance not being permitted to switch to its high resistance state to afford ...

Cascade varistor having improved energy handling capabilities

A varistor is provided having a rectangular configuration defining first and second opposing end surfaces offset in a lengthwise direction. The varistor may include a first terminal adjacent the first opposing end surface and a second terminal adjacent the second opposing end surface. The varistor may include an active electrode layer including a first electrode electrically connected with the first terminal and a second electrode electrically connected with the second terminal. The first electrode may be spaced apart from the second electrode in the lengthwise direction to form an active electrode end gap. The varistor may include a floating electrode layer including a floating electrode. The floating electrode layer may be spaced apart from the active electrode layer in a height-wise direction to form a floating electrode gap. A ratio of the active electrode end gap to the floating electrode gap may be greater than about 2.

Embedded transient voltage suppression for light emitting devices (LED)

A transient voltage suppressor is created within a conventional structure of a light emitting device (LED). A varistor compound is applied between the electrodes of the LED on a common surface, then sintered in situ. The compound may be applied between the electrodes on the substrate, within the LED structure, or at other convenient locations. In this manner, the suppressor becomes an integral element of the package, and not a discrete device attached to the package.

VOLTAGE SWITCHABLE DIELECTRIC MATERIAL INCORPORATING MODIFIED HIGH ASPECT RATIO PARTICLES

Embodiments described herein provide for a composition of voltage switchable dielectric (VSD) material that includes a concentration of modified high-aspect ratio (HAR) particles. In an embodiment, at least a portion of the concentration includes HAR particles are surface-modified to provide core-shell HAR particles. As an alternative or addition, a portion of the concentration includes HAR particles that are surface-modified to have activated surfaces.

Varistor type multi-directional input device

A varistor type multi-directional input device, including an upper cover, a base, a rocker assembly, a reset assembly, an electrical component, a switch elastic piece and a terminal assembly. The conductive elastic piece of the electrical component is mounted in a cavity surrounded by the upper cover, the base and the varistor. The rocking bar is operated to swing the eccentric wheel of the upper rocker arm or the lower rocker arm, and the surface pressure of the varistor is different due to the different deformation of elastic piece caused by the change of the height of the eccentric wheel in the axial direction, so that the varistor outputs different resistance values to achieve control of the screen cursor. The present disclosure is provided with a rocker arm seat which is matched with the upper rocker arm and the lower rocker arm.

Silicon MOS inductor

A device made of amorphous silicon which exhibits inductive properties at certain voltage biases and in certain frequency ranges in described. Devices of the type described can be made in integrated circuit form.

OBERFLÄCHENMONTIERTE SICHERUNGSVORRICHTUNG

Field sustained conductivity devices

A memory device exhibiting conductivity which is modified by an incident radiation or electron beam to a valve which is sustained at least temporarily on cessation of the beam unless the applied voltage is removed or reversed consists of an insulating support carrying a cadmium sulphide layer sandwiched between an aluminium electrode and another electrode. A barrier layer between the aluminium and the adjacent sulphide layer has been formed by heating them in a sulphur containing atmosphere. A typical device is made by vapour depositing aluminium to a thickness of 5000 <\>rA on a prepared glass substrate, vapour depositing a 0.5 m thick layer of cadmium sulphide over it and then heating, preferably at 300 DEG C. for 2 hours in a flow of dry hydrogen sulphide or sulphur dioxide. An electrode layer of aluminium, platinum, tin oxide, gold, indium, palladium or rhodium is then deposited on the layer. The resulting device exhibits a rectifying characteristic which varies in accordance with the ...

Surface-mountable device for protection against electrostatic damage to electronic components

ELECTRIC SHOCK PROTECTION DEVICE AND MOBILE ELECTRONIC DEVICE INCLUDING SAME

The purpose of the present invention is to provide an electric shock protection device capable of protecting an internal circuit and/or a user from leakage current by static electricity or external power, and a mobile electronic device including the same. Provided are the electric shock protection device and the mobile electronic device including the same. The electric shock protection device according to an exemplary embodiment of the present invention is an electric shock protection device arranged between a human body touchable conductor of an electronic device and an embedded circuit unit and comprises: two or more varistor material layers in which first and second varistor material layers are alternately layered; a plurality of first internal electrodes separated at regular intervals (L) on the first varistor layer; and a plurality of second internal electrodes separated at regular intervals (L) on the second varistor layer. The electric shock protection device passes the static electricity ...

ZnO THIN-FILM VARISTORS AND METHOD OF MAKING THE SAME

A thin-film zinc oxide varistor (10) for use in integrated circuits and the like is produced by applying a polyoxyalkylated metal complex, such as a metal alkoxycarboxylate, to a substrate (12, 14, and 16) for the formation of a dried non-ohmic layer (18). The method of production includes the steps of providing a substrate and a precursor solution including a polyoxyalkylated zinc complex (P22, P24), coating a portion of the substrate with the precursor solution (P26), drying the coated substrate (P32), and crystallizing the dried thin-film zinc oxide layer (P30). The resultant crystalline zinc oxide varistor layer (18) may be doped with bismuth, yttrium, praseodymium, cobalt, antimony, manganese, silicon, chromium, titanium, potassium, dysprosium, cesium, cerium, and iron to provide a non-ohmic varistor. The varistor layer (10) is annealed at a temperature ranging from about 400 to about 1000 °C to provide a layer having a thickness ranging from about 50 nanometers to about 500 nanometers ...

Surface-mountable device for protection against electrostatic damage to electronic components

The thin film, electrical device is an subminiature overvoltage circuit protection device in a surface mountable configuration for use in printed circuit board or thick film hybrid circuit technology. The surface mountable device (SMD) is designed to protect against electrostatic discharge (ESD) damage to electronic components. The circuit protection device comprises three material subassemblies. The first subassembly generally includes a substrate carrier, electrodes, and terminal pads for connecting the protection device 60 to a PC board. The second subassembly includes a voltage variable polymer material with nonlinear resistance characteristics, and the third subassembly includes a cover coat for protecting other elements of the circuit protection device. The devices of the present invention employ various electrode configurations and profiles to control the electrical field created between the electrodes and increase the active area of the electrodes in contact with the voltage variable ...

Liquid deposition methods of fabricating layered superlattice materials

A precursor liquid comprising several metal 2-ethylhexanoates, such as strontium, tantalum, and bismuth 2-ethylhexanoates, in a xylenes/methyl ethyl ketone solvent is prepared, and deposited on a substrate. In one embodiement the substrate is placed within a vacuum deposition chamber, the precursor liquid is misted, and the mist is flowed into the deposition chamber while maintaining the chamber at ambient temperature to deposit the precursor liquid on the substrate. In another embodiment, the precursor is spin-coated on the substrate. The liquid is dried, baked, and annealed to form a thin film of a layered superlattice material, such as strontium bismuth tantalate, on the substrate.

VOLTAGE SWITCHABLE DIELECTRIC MATERIAL INCORPORATING MODIFIED HIGH ASPECT RATIO PARTICLES

Embodiments described herein provide for a composition of voltage switchable dielectric (VSD) material that includes a concentration of modified high-aspect ratio (HAR) particles. In an embodiment, at least a portion of the concentration includes HAR particles are surface-modified to provide core-shell HAR particles. As an alternative or addition, a portion of the concentration includes HAR particles that are surface-modified to have activated surfaces. COPYRIGHT KIPO & WIPO 2010 ...

CASCADE VARISTOR HAVING IMPROVED ENERGY HANDLING CAPABILITIES

PROCESS FOR FABRICATING LAYERED SUPERLATTICE MATERIALS AND MAKING ELECTRONIC DEVICES INCLUDING SAME

A liquid precursor containing a metal is applied to a substrate, RTP baked, and annealed to form a layered superlattice material. Special polyoxyalkylated precursor solutions are designed to optimize polarizability of the corresponding metal oxide materials by adding dopants including stoichiometric excess amounts of bismuth and tantalum. The RTP baking process is especially beneficial in optimizing the polarizability of the resultant metal oxide.

EMBEDDED TRANSIENT VOLTAGE SUPPRESSION FOR LIGHT EMITTING DEVICES

A transient voltage suppressor (330, 332, 334, 336) is created within aconventional structure of a light emitting device, LED (301). A varistor compound (330, 332, 334, 336) is applied between the electrodes (320-340, 322-340, 324-342, 326-342)of the LED (301)on a common surface, then sintered in situ. The compound may be applied between the electrodes on the substrate, within the LED structure, or at other convenient locations. In this manner, the suppressor becomes an integral element of the package, and not a discrete device attached to the package.

Thin films of ABO.sub.3 with excess B-site modifiers and method of fabricating integrated circuits with same

A SURGE SUPPRESSOR ARRANGED FOR SUPPRESSING SURGES, A DRIVER COMPRISING A SURGE SUPPRESSOR AS WELL AS A METHOD FOR OPERATING THE SURGE SUPPRESSOR

SEMICONDUCTOR MEMORY UNIT

PURPOSE: To enable the information memory of low-current and low voltage by using high resistance multiplex as the memory element. COPYRIGHT: (C)1977,JPO&Japio ...

HERSTELLUNGSVERFAHREN VON SCHICHTIGEN SUPERGITTERMATERALIEN DURCH CHEMISCHE ABSCHEIDUNG AUS DER DAMPFPHASE

Process for fabricating layered superlattice materials

ELECTRONIC COMPONENT

An electronic component in which a metal layer is unlikely to be peeled from a substrate includes an insulating ceramic substrate, a ceramic layer diffusion-bonded to the substrate, a metal layer including a first principal surface and a second principal surface opposed to the first principal surface, with the first principal surface diffusion-bonded to the ceramic layer, and a characteristic layer diffusion-bonded to the second principal surface of the metal layer and prepared from a ceramic material, wherein the characteristic layer varies in resistance value with respect to ambient temperature or applied voltage. 1. An electronic component comprising:a substrate including an insulating ceramic material;a ceramic layer diffusion-bonded to the substrate;a metal layer including a first principal surface and a second principal surface opposed to the first principal surface, with the first principal surface diffusion-bonded to the ceramic layer; anda characteristic layer diffusion-bonded to the second principal surface of the metal layer and including a ceramic material; whereinthe characteristic layer varies in resistance value with respect to at least one of an ambient temperature and an applied voltage.2. The electronic component according to claim 1 , wherein the ceramic layer blocks atom transfer from the substrate to the characteristic layer.3. The electronic component according to claim 1 , wherein the ceramic layer is made of a same ceramic material as the characteristic layer.4. The electronic component according to claim 1 , wherein the substrate is a multilayer substrate including a plurality of insulating ceramic sheets including silicon-based glass.5. The electronic component according to claim 1 , wherein the substrate is made of an insulating ceramic material containing Al.6. The electronic component according to claim 1 , wherein the characteristic layer is a thermistor characteristic layer.7. The electronic component according to claim 6 , wherein the ...

Passive microwave device and method for producing the same

The present invention provides an electrical circuit component, specifically a passive microwave device, and a method for producing the same. In one embodiment, the present invention provides an electrical circuit component, comprising: at least one patterned resistive area on a first surface of a diamond substrate, a first patterned conductive area on the first surface of the diamond substrate, and a second patterned conductive area on a second surface of the diamond substrate. The patterned resistive area may comprise a very thin film of tantalum nitride or a very thin film of tantalum nitride and a thin film of nichrome. The patterned conductive area may comprise a layer of titanium-tungsten, a layer of gold, and optionally a layer of nickel. Alternatively, the patterned conductive area may comprise a layer of chrome, a layer of copper, a layer of gold, and optionally a layer of nickel.

PROCESS FOR FABRICATING LAYERED SUPERLATTICE MATERIALS AND MAKING ELECTRONIC DEVICES INCLUDING SAME

A liquid precursor containing a metal is applied to a substrate, RTP baked, and annealed to form a layered superlattice material. Special polyoxyalkylated precursor solutions are designed to optimize polarizability of the corresponding metal oxide materials by adding dopants including stoichiometric excess amounts of bismuth and tantalum. The RTP baking process is especially beneficial in optimizing the polarizability of the resultant metal oxide.

Low temperature process for fabricating layered superlattice materialsand making electronic devices including same

A liquid precursor containing a metal is applied to a first electrode, RTP baked at a temperature of 700 DEG C., and annealed at the same temperature for from 3 to 5 hours to form a layered superlattice material. A second electrode is formed to form a capacitor, and a second anneal is performed at a temperature of 700 DEG C. If the material is strontium bismuth tantalate, the precursor contains u mole-equivalents of strontium, v mole-equivalents of bismuth, and w mole-equivalents of tantalum, where 0.8 Подробнее

Thin film type varistor and a method of manufacturing the same

A thin film type varistor and a method of manufacturing the same are provided. The method includes: a depositing a first zinc oxide thin film at a low temperature through a sputtering method; and a forming a zinc oxide thin film for a varistor by treating the first zinc oxide thin film with heat at a low temperature in an environment in which an inert gas and oxygen are injected. Accordingly, it is possible to lower a processing temperature and simplify a manufacturing process while maintaining a varistor characteristic so as to be applied to a highly integrated circuit.

VERFAHREN ZUR HERSTELLUNG VON SCHICHTIGEN SUPERGITTERMATERIALIEN.

Resistance element with increased voltage and increased resistance value

Integrated circuit device and fabrication method therefor

In a temperature sensor section of a semiconductor integrated circuit device, wires of the topmost wiring layer of a multi-layer wiring structure are formed. A sheet-like temperature monitor element of vanadium oxide is provided between two of the wires in such a way as to cover the two wires. Accordingly, the temperature monitor element is connected between the two wires of an underlying wiring layer of the multi-layer wiring structure through two vias and the two wires of the topmost wiring layer.

Ferroelectric dielectric memory cell can switch at least giga cycles and has low fatigue - has high dielectric constant and low leakage current

An integrated circuit includes a layered superlattice material having the formula A1w1+a1 A2w2+a2 . . . Ajwj+aj S1x1+s1 S2x2+s2 . . . Skxk+ak B1y1+b1 B2y2+b2 . . . Blyl+bl Qz-2, where A1, A2 . . . Aj represent A-site elements in a perovskite-like structure, S1, S2 . . . Sk represent superlattice generator elements, B1, B2 . . . Bl represent B-site elements in a perovskite-like structure, Q represents an anion, the superscripts indicate the valences of the respective elements, the subscripts indicate the number of atoms of the element in the unit cell, and at least w1 and y1 are non-zero. Some of these materials are extremely low fatigue ferroelectrics and are applied in non-volatile memories. Others are high dielectric constant materials that do not degrade or breakdown over long periods of use and are applied in volatile memories.

Chemical vapor deposition process for fabricating layered superlattice materials

A substrate is prebaked in an oxygen furnace. A thin film of layered superlattice oxide is formed on the substrate by a chemical vapor deposition process. The film is RTP baked to provide grains with a mixed phase of A-axis and C-axis orientation. The film may be treated by ion implantation prior to the RTP bake and oxygen furnace annealed after the RTP bake. An electrode is deposited on the layered superlattice thin film and then the film and electrode are oxygen furnace annealed.

Composite resistors

A composite resistor includes a thin film resistor element having a first temperature coefficient of resistance and a metal resistor element having a second temperature coefficient of resistance. A portion of the metal resistor element overlaps a portion of the thin film resistor element such that the portion of the metal resistor element is in thermal communication with the portion of the thin film resistor element to compensate for a resistance drift arising during operation of the composite resistor.

Low temperature fabrication of lateral thin film varistor

A structure and method for fabricating a laterally configured thin film varistor surge protection device using low temperature sputtering techniques which do not damage IC device components contiguous to the varistor being fabricated. The lateral thin film varistor may include a continuous layer of alternating regions of a first metal oxide layer and a second metal oxide layer formed between two laterally spaced electrodes using a low temperature sputtering process followed by a low temperature annealing process.

Low temperature fabrication of lateral thin film varistor

A structure and method for fabricating a laterally configured thin film varistor surge protection device using low temperature sputtering techniques which do not damage IC device components contiguous to the varistor being fabricated. The lateral thin film varistor may include of a continuous layer of alternating regions of a first metal oxide layer and a second metal oxide layer formed between two laterally spaced electrodes using a low temperature sputtering process followed by a low temperature annealing process.

Cascade Varistor Having Improved Energy Handling Capabilities

A varistor is provided having a rectangular configuration defining first and second opposing end surfaces offset in a lengthwise direction. The varistor may include a first terminal adjacent the first opposing end surface and a second terminal adjacent the second opposing end surface. The varistor may include an active electrode layer including a first electrode electrically connected with the first terminal and a second electrode electrically connected with the second terminal. The first electrode may be spaced apart from the second electrode in the lengthwise direction to form an active electrode end gap. The varistor may include a floating electrode layer including a floating electrode. The floating electrode layer may be spaced apart from the active electrode layer in a height-wise direction to form a floating electrode gap. A ratio of the active electrode end gap to the floating electrode gap may be greater than about 2.

Low Inductance Component

A low inductance component may include a multilayer, monolithic device including a first active termination, a second active termination, at least one ground termination, and a pair of capacitors connected in series between the first active termination and the second active termination. The lead(s) may be coupled with the first active termination, second active termination, and/or the at least one ground termination. The lead(s) may have respective length(s) and maximum width(s). A ratio of the length(s) to the respective maximum width(s) of the lead(s) may be less than about 20.

Integrated Component Including a Capacitor and Discrete Varistor

An integrated component may include a multilayer capacitor include a first active termination, a second active termination, at least one ground termination, and a pair of capacitors connected in series between the first active termination and the second active termination. The integrated component may include a discrete varistor comprising a first external varistor termination connected with the first active termination and a second external varistor termination connected with the second active termination of the multilayer capacitor.

Chemical vapor deposition process for fabricating layered superlattice materials

Cascade varistor with improved energy processing capacity

長さ方向にずれた第１の対向端面および第２の対向端面を画定する矩形構成を有するバリスタが提供される。バリスタは、第１の対向端面に隣接する第１の端子、および、第２の対向端面に隣接する第２の端子を含むことができる。バリスタは、第１の端子と電気的に接続された第１の電極および第２の端子と電気的に接続された第２の電極を含む活性電極層を含むことができる。第１の電極は、活性電極端部間隙を形成するように、長さ方向において第２の電極から離間され得る。バリスタは、浮遊電極を含む浮遊電極層を含むことができる。浮遊電極層は、浮遊電極間隙を形成するように、高さ方向において活性電極層から離間され得る。活性電極端部間隙の浮遊電極間隙に対する比率は、約２よりも大きくてもよい。【選択図】図１Ａ

Process for fabricating layered superlattice materials

Heat sink for integrated circuit devices

A resistor with heat sink is provided. The heat sink includes a conductive path having metal or other thermal conductor having a high thermal conductivity. To avoid shorting the electrical resistor to ground with the thermal conductor, a thin layer of high thermal conductivity electrical insulator is interposed between the thermal conductor and the body of the resistor. Accordingly, a resistor can carry large amounts of current because the high conductivity thermal conductor will conduct heat away from the resistor to a heat sink. Various configurations of thermal conductors and heat sinks are provided offering good thermal conductive properties in addition to reduced parasitic capacitances and other parasitic electrical effects, which would reduce the high frequency response of the electrical resistor.

Thin films of ABO3 with excess A-site and B-site modifiers and method of fabricating integrated circuits with same

A method for fabricating an integrate circuit capacitor having a dielectric layer comprising BST with excess A-site and B-site materials such as barium and titanium added. An organometallic or metallic soap precursor solution is prepared comprising a stock solution of BST of greater than 99.999% purity blended with excess A-site and B-site materials such as barium and titanium such that the barium is in the range of 0.01-100 mol %, and such that the titanium is in the range of 0.01-100 mol %. A xylene exchange is then performed to adjust the viscosity of the solution for spin-on application to a substrate. The precursor solution is spun on a first electrode, dried at 400° C. for 2 to 10 minutes, then annealed at 650° C. to 800° C. for about an hour to form a layer of BST with excess titanium. A second electrode is deposited, patterned, and annealed at between 650° C. to 800° C. for about 30 minutes. The resultant capacitor exhibits an enlarged dielectric constant with little change in leakage current.

Integrated vertical resistor structure with reduced dimensions, for high voltage, and manufacturing process thereof

The high-voltage resistor is of the vertical type, and is formed in a chip which includes a high-voltage region and a low-voltage region superimposed on the high-voltage region, both having a first conductivity type. An isolation region, at least partially buried, extends between the high-voltage region and the low-voltage region, and delimits a vertical resistive region connecting the high-voltage region to the low-voltage region.

Process for fabricating layered superlattice materials and making electronic devices including same

A liquid precursor containing a metal is applied to a substrate, RTP baked, and annealed to form a layered superlattice material. Special polyoxyalkylated precursor solutions are designed to optimize polarizability of the corresponding metal oxide materials by adding dopants including stoichiometric excess amounts of bismuth and tantalum. The RTP baking process is especially beneficial in optimizing the polarizability of the resultant metal oxide.

CASCADE VARISTOR WITH IMPROVED ENERGY MANAGEMENT CAPABILITIES

РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) (13) 2020 129 247 A (51) МПК H01C 7/10 (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ЗАЯВКА НА ИЗОБРЕТЕНИЕ (21)(22) Заявка: 2020129247, 04.03.2019 (71) Заявитель(и): ЭйВиЭкс КОРПОРЭЙШН (US) Приоритет(ы): (30) Конвенционный приоритет: 05.03.2018 US 62/638,369 (85) Дата начала рассмотрения заявки PCT на национальной фазе: 05.10.2020 R U (43) Дата публикации заявки: 06.04.2022 Бюл. № 10 (72) Автор(ы): КИРК, Майкл (US), БЕРОЛИНИ, Марианна (US), РАВИНДРАНАТАН, Паланиаппан (US) (86) Заявка PCT: (87) Публикация заявки PCT: WO 2019/173186 (12.09.2019) A Адрес для переписки: 105064, г. Москва, а/я 88, ООО "Патентные поверенные Квашнин, Сапельников и партнеры", Квашнин Валерий Павлович R U (57) Формула изобретения 1. Варистор прямоугольной конфигурации, задающей первую и вторую противоположные торцевые поверхности, смещенные в продольном направлении, содержащий: первый вывод, примыкающий к первой противоположной торцевой поверхности; второй вывод, примыкающий ко второй противоположной торцевой поверхности; активный электродный слой, содержащий первый электрод, электрически соединенный с первым выводом, и второй электрод, электрически соединенный со вторым выводом, причем первый электрод отстоит от второго электрода в продольном направлении для образования зазора конца активного электрода; и плавающий электродный слой, содержащий плавающий электрод, причем плавающий электродный слой отстоит от активного электродного слоя по высоте для образования зазора плавающего электрода; при этом отношение зазора конца активного электрода к зазору плавающего электрода составляет более чем около 2. 2. Варистор по п. 1, в котором первый электрод перекрывает плавающий электрод в продольном направлении вдоль длины перекрывающегося участка; активный электродный слой имеет длину в продольном направлении между первым выводом и вторым выводом; и коэффициент перекрытия составляет более чем около 5. Стр.: 1 A 2 0 2 0 1 2 9 2 4 7 (54) КАСКАДНЫЙ ...

Electronic device, method of forming an electronic device, and circuit

本公开涉及一种电子器件、一种形成电子器件的方法以及一种电路。在一方面，电路包括漏极端子和源极端子；HEMT，具有漏极和源极，其中漏极耦接到漏极端子；以及可变电阻器，具有第一和第二电极。第一电极可耦接到HEMT的源极，并且第二电极可耦接到源极端子。在另一方面，电子器件包括源极端子；沟道层和阻挡层之间的异质结；HEMT的源极电极，源极电极覆盖在沟道层上面；第一电阻器电极，第一电阻器电极覆盖在沟道层上面并与源极电极间隔开，第一电阻器电极耦接到源极端子；以及可变电阻器，其中从俯视图看，可变电阻器在源极电极和第一电阻器电极之间沿着异质结设置。当切换包括HEMT的电子器件或电路时，可变电阻器可帮助减少在瞬态期间的过压或过流情况。

Cascade varistor having improved energy handling capabilities

Electronic component

电子部件(1)具备素体(2)、以覆盖一对端面(2a、2b)及四个侧面(2c、2d、2e、2f)的方式配置的薄膜层(10)、第一外部电极(3)及第二外部电极(4)、内部导体(5、6)，薄膜层(10)沿着一对端面(2a、2b)及四个侧面(2c、2d、2e、2f)各自的表面形状形成，第一外部电极(3)及第二外部电极(4)分别具有配置于薄膜层(10)上并且与内部导体(5、6)电连接的第一电极层(20、30)和以覆盖第一电极层(20、30)的方式配置的第二电极层(21、31)，第二电极层(21、31)的热传导率比第一电极层(20、30)的热传导率低。

Method for manufacturing ESD protection element

Electronic parts

Electronic component

为了提供金属层不容易从基板上剥离的电子元器件，电子元器件(1a)包括：由绝缘性陶瓷材料所制成的基板(7)；由陶瓷材料所制成且与基板(7)进行扩散接合的陶瓷层(8)；金属层(9)，该金属层(9)具有第一主面(91)和与该第一主面(91)相对的第二主面(92)，该金属层(9)在该第一主面(91)侧与陶瓷层(8)进行扩散接合；以及特性层(10)，该特性层(10)与金属层(9)的第二主面(92)侧进行扩散接合，该特性层(10)由陶瓷材料制成，其电阻值根据周围温度或施加电压而变化。

Vertical switching configuration for ESD protection

Method and apparatus for a surface-mountable device for protection against electrostatic damage to electronic components

Integrated circuit device and manufacturing method thereof

Heat sink, thermal interface, resistor, and method of cooling the resistor

For the construction of the Vertical Handover of ESD protections

公开了用于ESD保护的垂直切换的构造。此处所公开的实施例一般涉及使用电压可切换的介电材料来实现针对ESD及其他过电压事件的垂直和/或双切换保护的结构、方法以及设备。

NON-REVERSIBLE TO BE BRIDGED IN ANOTHER CONDUCTED CONDITION SEMICONDUCTOR SWITCH ELEMENT AND SEMI-CONDUCTOR MEMORY DEVICE WITH AT LEAST SUCH SEMI-CONDUCTOR SWITCH ELEMENT.

Thin films of ABO3 with excess B-site modifiers and method of fabricating integrated circuits with same

A method for fabricating an integrated circuit capacitor having a dielectric layer comprising BST with excess B-site material, such as titanium, added. A polyoxyalkylated metal liquid precursor solution is prepared comprising a stock solution of BST of greater then 99.999% purity blended with excess B-site material such as titanium such that the titanium is in the range of 0-100 mol %. A xylene exchange is then performed to adjust the viscosity of the solution for spin-on application to a substrate. The precursor is spun on a first electrode, dried at 400° C. for 2 minutes, then annealed at 650° C. to 800° C. for about an hour to form a layer of BST with excess titanium. A second electrode is deposited, patterned, and annealed at between 650° C. to 800° C. for about 30 minutes. The resultant capacitor exhibits an enlarged dielectric constant with only a small increase in leakage current.

Current switching transistor

본 발명에 따르면, 전자 장치 및 전자 장치를 제조하는 방법이 개시된다. 전자 장치는 반도체 물질의 몸체, 및 각각의 단자들을 형성하기 위해 적어도 3개의 도전성 접점들을 형성하는 도전성 물질을 포함한다. 반도체 물질과 도전성 접점들은 전자 장치를 형성하기 위해 적어도 부분적으로 오버랩되어, 어느 한 쌍의 단자들 사이의 전자 장치의 전기적 특성들은 배리스터의 전기적 특성들에 대응한다. 반도체 물질의 몸체는 인쇄 또는 코팅에 의해 적층된 층일 수 있다. 각 쌍의 단자들 사이의 배리스터 특성들은, 제 1 단자로의 양 전류가 있을 때, 양 전위가 인가되는 제 2 단자를 통한 미세 전류, 및 제 2 단자에 대하여 음 전위로 유지되는 제 3 단자로부터의 양 전류가 있는 방식으로, 하나의 단자와 나머지 2개의 단자들 사이의 전류의 전환을 가능하게 한다. 제 1 단자의 바깥으로의 음 전류가 있을 때, 제 2 단자로의 양 전류, 및 제 3 단자를 통한 미세 전류가 있다.

Cascaded varistor with improved energy handling capability

提供了一种变阻器，该变阻器具有限定沿长度方向偏移的第一和第二相对端面的矩形构造。变阻器可以包括邻近第一相对端面的第一端子和邻近第二相对端面的第二端子。变阻器可以包括有源电极层，该有源电极层包括与第一端子电连接的第一电极和与第二端子电连接的第二电极。第一电极可以在长度方向上与第二电极间隔开，以形成有源电极端部间隙。变阻器可以包括具有浮动电极的浮动电极层。浮动电极层可以在高度方向上与有源电极层间隔开，以形成浮动电极间隙。有源电极端部间隙与浮动电极间隙的比可以大于约2。

Current switching transistor

An electronic device and a method of fabricating an electronic device are disclosed. The device includes a body of semiconductor material, and a conductive material defining at least three conducting contacts to form respective terminals. The semiconductor material and the conducting contacts overlap at least partially to define the device, so that the electrical characteristics of the device between any pair of terminals correspond to those of a varistor. The body of semiconductor material may be a layer deposited by printing or coating. The varistor characteristics between each pair of terminals enable switching of an electrical current between one terminal and any two other terminals in such a manner that when there is a positive current into a first terminal, there is a negligible current through a second terminal at which a positive potential is applied and a positive current out of a third terminal which is held at a negative potential with respect to the second terminal. When there is a negative current outwards of the first terminal, there is a positive current into the second terminal and a negligible current through the third terminal.

Protection of an integrated circuit with voltage variable materials

A number of integrated circuit dies having on board protection against electrical overstress (EOS) transients are provided. Generally, the devices have an integrated circuit die with an outer periphery and a functional die area. A plurality of conductive input/output pads are formed on the integrated circuit die. Typically, a first conductive guard rail is disposed on the integrated circuit die and forms a gap between each one of the input/output pads. A voltage variable material is disposed in the gaps between the conductive guard rail and the input/output pads. Typically, a plurality of electrical leads are electrically connected to a respective one of the plurality of conductive input/output pads. At normal operating voltages, the voltage variable material is non-conductive. However, in response to an EOS transient, the voltage variable material switches to a low resistance state, providing a conductive path between the conductive guard rail and the input/output pads.

Microvaristor-based overvoltage protection

本发明涉及一种用于保护电气元件(6、6b、6c、6d、6e、8、9、11-13)的包含ZnO微变阻器颗粒(2)的过电压保护装置以及用于生产该装置的方法。根据本发明，将单微变阻器颗粒(2)放置在具有单层厚度(t)的布置(1)中并将其电耦合到电气元件(6、6b、6c、6d、6e、8、9、11-13)，以便保护其耐过电压.在成形中，单层过电压保护装置允许非常紧凑的集成和高的柔性，并使其适合电气或电子元件(6、6b、6c、6d、6e、8、9、11-13).另外，获得了降低的电容及由此降低的过电压保护的反应时间。

Layered superlattice material applications

Un circuit stratifié (36) comprend un matériau de surstructure stratifiée (60, 60', 92) représenté par la formule (1) dans laquelle A1, A2 ... Aj représentent des éléments de site A (84) d'une structure de type pérovskite, S1, S2 ... Sk représentent des éléentts générateurs de surstructure (87), B1, B2 ... Bl représentent des éléments de site B (86) d'une structure de type pérovskite (94), Q représente un anion (88), les exposants indiquent que les valences des éléments respectifs (84, 87, 86, 88), les indices indiquent le nombre d'atomes de l'élément de la cellule unitaire (89) et, au moins w1 et y1 sont non zéro. Quelques uns desdits matériaux sont des ferro-électriques extrêmement résistants et s'utilisent dans des mémoires non volatiles (36). D'autres sont des matériaux à constantes diélectriques élevées ne se détériorant pas pendant des périodes d'utilisation prolongée et s'appliquent à des mémoires volatiles (36). A laminated circuit (36) comprises a laminated substructure material (60, 60 ', 92) represented by the formula (1) in which A1, A2 ... Aj represent site elements A (84) of a structure of perovskite type, S1, S2 ... Sk represent elements generating the superstructure (87), B1, B2 ... Bl represent site elements B (86) of a structure of the perovskite type (94), Q represents a anion (88), the exponents indicate that the valences of the respective elements (84, 87, 86, 88), the indices indicate the number of atoms of the element of the unit cell (89) and, at least w1 and y1 are non zero. Some of said materials are extremely resistant ferroelectrics and are used in non-volatile memories (36). Others are materials with high dielectric constants which do not deteriorate during periods of prolonged use and apply to volatile memories (36).

Voltage switchable dielectric material incorporating modified high aspect ratio particles

Embodiments described herein provide for a composition of voltage switchable dielectric (VSD) material that includes a concentration of modified high-aspect ratio (HAR) particles. In an embodiment, at least a portion of the concentration includes HAR particles are surface-modified to provide core-shell HAR particles. As an alternative or addition, a portion of the concentration includes HAR particles that are surface-modified to have activated surfaces.

Electro-optical device

Cascade varistor having improved energy handling capabilities

A varistor is provided having a rectangular configuration defining first and second opposing end surfaces offset in a lengthwise direction. The varistor may include a first terminal adjacent the first opposing end surface and a second terminal adjacent the second opposing end surface. The varistor may include an active electrode layer including a first electrode electrically connected with the first terminal and a second electrode electrically connected with the second terminal. The first electrode may be spaced apart from the second electrode in the lengthwise direction to form an active electrode end gap. The varistor may include a floating electrode layer including a floating electrode. The floating electrode layer may be spaced apart from the active electrode layer in a height-wise direction to form a floating electrode gap. A ratio of the active electrode end gap to the floating electrode gap may be greater than about 2.

Variable resistance element and manufacturing method thereof

２つの金属電極の間に強相関材料からなる可変抵抗体を設けてなり、金属電極間に電圧パルスを印加することにより金属電極間の電気抵抗が変化する可変抵抗素子において、明確なスイッチング動作原理の裏付けによって、金属電極及び可変抵抗体を適切に設計して、電気抵抗の低抵抗状態と高抵抗状態間の抵抗比の大きなスイッチング動作を可能とする可変抵抗素子を提供する。電圧パルスの印加によって、２つの金属電極１，３の何れか一方の第１電極と可変抵抗体２の界面において金属絶縁体転移が生じるように第１電極と可変抵抗体の材料及び組成を設定する。更に、第１電極と可変抵抗体の仕事関数差が、可変抵抗体の第１電極との界面近傍において金属相と絶縁体相の２相共存相を形成し得る仕事関数差となっている。 A clear switching operation principle in a variable resistance element in which a variable resistor made of a strongly correlated material is provided between two metal electrodes, and the electric resistance between the metal electrodes changes by applying a voltage pulse between the metal electrodes. Thus, a variable resistance element is provided in which a metal electrode and a variable resistor are appropriately designed to enable a switching operation with a large resistance ratio between a low resistance state and a high resistance state of electrical resistance. The material and composition of the first electrode and the variable resistor are set so that the metal-insulator transition occurs at the interface between the first electrode of one of the two metal electrodes 1 and 3 and the variable resistor 2 by applying the voltage pulse. To do. Furthermore, the work function difference between the first electrode and the variable resistor is a work function difference that can form a two-phase coexisting phase of the metal phase and the insulator phase in the vicinity of the interface between the variable resistor and the first electrode.

NON-REVERSIBLE TO BE BRIDGED IN ANOTHER CONDUCTED CONDITION SEMICONDUCTOR SWITCH ELEMENT AND SEMI-CONDUCTOR MEMORY DEVICE WITH AT LEAST SUCH SEMI-CONDUCTOR SWITCH ELEMENT.

Electronic device and circuit including a transistor and a variable resistor

In an aspect, a circuit can include drain and source terminals; a HEMT having a drain and a source, wherein the drain is coupled to the drain terminal; and a variable resistor having a first electrode and a second electrode. The first electrode can be coupled to the source of the HEMT, and the second electrode can be coupled to the source terminal. In another aspect, an electronic device can include a source terminal; a heterojunction between a channel layer and a barrier layer; a source electrode of a HEMT overlying the channel layer; a first resistor electrode overlying the channel layer and spaced apart from the source electrode, wherein the first resistor electrode is coupled to the source terminal; and a variable resistor, wherein from a top view, the variable resistor is disposed along the heterojunction between the source electrode and the first resistor electrode.

Electronic component

电子部件(1)具备素体(2)、以覆盖一对端面(2a、2b)及四个侧面(2c、2d、2e、2f)的方式配置的薄膜层(10)、第一外部电极(3)及第二外部电极(4)、内部导体(5、6)，薄膜层(10)沿着一对端面(2a、2b)及四个侧面(2c、2d、2e、2f)各自的表面形状形成，第一外部电极(3)及第二外部电极(4)分别具有配置于薄膜层(10)上并且与内部导体(5、6)电连接的第一电极层(20、30)和以覆盖第一电极层(20、30)的方式配置的第二电极层(21、31)，第二电极层(21、31)的热传导率比第一电极层(20、30)的热传导率低。

Protection system against electrical overstress (EOS) of junction or switch-on steps of integrated circuit chip uses semiconductor chip with several conductive in-/output terminal pads having first protective conductor

The semiconductor chip has numerous, conductive input/output terminal pads, to which is allocated a first conductive protective conductor in adjacent configuration. There is a gap between the protective conductor and each terminal pad. In the gap is fitted material of variable voltage, forming a path between each terminal pad and the first protective conductor. To the numerous terminal pads are coupled corresponding electric lines. The chip comprises an integrated circuit, operated at a normal voltage, at which the path between the pads and protective conductor is not conductive. An Independent claim is included for the integrated circuit.

SEMICONDUCTOR SWITCHING ELEMENT WITH IRREVERSIBLE BEHAVIOR AND SEMICONDUCTOR STORAGE USING THE SEMICONDUCTOR SWITCHING ELEMENT

低电感组件

一种低电感组件可以包括多层单片设备，该多层单片设备包括第一有源终端、第二有源终端、至少一个接地终端和一对电容器，该对电容器串联连接在第一有源终端与第二有源终端之间。引线可以与第一有源终端、第二有源终端和/或至少一个接地终端耦合。引线可以具有各自的长度和最大宽度。引线的长度与各自的最大宽度之比可小于约20。

低電感元件

本發明揭示一種低電感元件，其可包含一多層單塊裝置，該多層單塊裝置包含一第一作用端接部、一第二作用端接部、至少一個接地端接部及在該第一作用端接部與該第二作用端接部之間串聯連接之一對電容器。引線可與該第一作用端接部、第二作用端接部及/或該至少一個接地端接部耦合。該(等)引線可具有各別長度及最大寬度。該(等)引線之長度與各別最大寬度之一比率可小於約20。

저 인덕턴스 컴포넌트

저 인덕턴스 컴포넌트는 제1 능동 종단, 제2 능동 종단, 적어도 하나의 접지 종단, 및 상기 제1 능동 종단과 제2 능동 종단 사이에 직렬로 연결된 한 쌍의 커패시터를 포함하는 적층, 모놀리식 디바이스를 포함할 수 있다. 리드(들)는 제1 능동 종단, 제2 능동 종단 및/또는 적어도 하나의 접지 종단 중 적어도 하나에 연결될 수 있다. 리드(들)는 각각 길이(들)와 최대 폭(들)을 구비할 수 있다. 리드(들)의 최대 폭(들)에 대한 각각 길이(들)의 비는 약 20 미만일 수 있다.

低インダクタンス構成要素

低インダクタンス構成要素は、第１のアクティブ端子、第２のアクティブ端子、少なくとも１つの接地端子、および、第１のアクティブ端子と第２のアクティブ端子との間に直列に接続された一対のコンデンサを含む多層モノリシックデバイスを含み得る。リードは、第１のアクティブ端子、第２のアクティブ端子、および／または少なくとも１つの接地端子と結合され得る。リードは、それぞれの長さおよび最大幅を有し得る。リードのそれぞれの最大幅に対する長さの比は、約２０未満であり得る。

コンデンサおよびディスクリートバリスタを含む統合構成要素

統合構成要素は、第１のアクティブ端子、第２のアクティブ端子、少なくとも１つの接地端子、および、第１のアクティブ端子と第２のアクティブ端子との間に直列に接続された一対のコンデンサとを含む多層コンデンサを含み得る。統合構成要素は、多層コンデンサの第１のアクティブ端子に接続された第１の外部バリスタ端子と、第２のアクティブ端子に接続された第２の外部バリスタ端子とを備えるディスクリートバリスタを含み得る。

Low temperature fabrication of lateral thin film varistor

A structure and method for fabricating a laterally configured thin film varistor surge protection device using low temperature sputtering techniques which do not damage IC device components contiguous to the varistor being fabricated. The lateral thin film varistor may include a continuous layer of alternating regions of a first metal oxide layer and a second metal oxide layer formed between two laterally spaced electrodes using a low temperature sputtering process followed by a low temperature annealing process.

Low temperature fabrication of lateral thin film varistor

A structure and method for fabricating a laterally configured thin film varistor surge protection device using low temperature sputtering techniques which do not damage IC device components contiguous to the varistor being fabricated. The lateral thin film varistor may consist of a continuous layer of alternating regions of a first metal oxide layer and a second metal oxide layer formed between two laterally spaced electrodes using a low temperature sputtering process followed by a low temperature annealing process.

横向薄膜变阻器及其低温制造方法

本发明涉及横向薄膜变阻器的低温制造。一种使用不损害与被制造的变阻器邻接的IC设备组件的低温溅射技术来制造横向配置的薄膜变阻器电涌防护设备的结构和方法。横向薄膜变阻器可以由使用低温溅射工艺随后通过低温退火工艺而在两个横向隔开的电极之间形成的连续层组成，所述连续层包括第一金属氧化物层和第二金属氧化物层的交替区域。

Composite resistors

A composite resistor includes a thin film resistor element having a first temperature coefficient of resistance and a metal resistor element having a second temperature coefficient of resistance. A portion of the metal resistor element overlaps a portion of the thin film resistor element such that the portion of the metal resistor element is in thermal communication with the portion of the thin film resistor element to compensate for a resistance drift arising during operation of the composite resistor.

에너지 감응형 전자 부품 및 기능 박막이 형성된 집합 기판

본 발명의 일 측면에 따른 에너지 감응형 전자 부품은, 서로 마주한 일면 및 타면, 각각 상기 일면과 타면을 연결하고 서로 마주한 일단면 및 타단면, 및 각각 상기 일단면과 타단면을 연결하고 서로 마주한 일측면 및 타측면을 가지고, Al 2 O 3 단결정 기판인 베이스 기판; 상기 베이스 기판의 타면에 배치되고, Ti가 도핑되어 있는 VO 2 박막인 기능 박막; 상기 베이스 기판의 일단면 및 타단면에 형성된 제1 및 제2 오목부; 및 상기 제1 및 제2 오목부에 배치되고, 상기 기능 박막과 연결된 제1 및 제2 외부 전극; 을 포함하고, 상기 기능 박막은, 25℃에서의 저항을 R1, 80℃에서의 저항을 R2라고 할 때, R1/R2 가 10 4 이상이고, 상기 기능 박막은, 25℃로부터 80℃까지의 승온 과정과 80℃부터 25℃까지의 냉각 과정을 1 싸이클(cycle)이라고 할 때, a) 10 싸이클 동안 히스테리시스 온도 차(△T)의 변화(V △T )가 1℃ 이하, b) 10 싸이클 동안 상전이 온도(T MI )의 변화(V TMI )가 1.5℃ 이하, 및 c) 10 싸이클 동안 R1/R2의 변화율(V R1/R2 )이 5% 이하 중 적어도 하나를 충족할 수 있다.

包括电容器和分立变阻器的集成组件

一种集成组件可包括多层电容器，该多层电容器包括第一有源终端、第二有源终端、至少一个接地终端、以及在第一有源终端与第二有源终端之间串联连接的成对电容器。该集成组件可包括分立变阻器，该分立变阻器包括与多层电容器的第一有源终端连接的第一外部变阻器终端和与多层电容器的第二有源终端连接的第二外部变阻器终端。

Composite resistors

A composite resistor includes a thin film resistor element having a first temperature coefficient of resistance and a metal resistor element having a second temperature coefficient of resistance. A portion of the metal resistor element overlaps a portion of the thin film resistor element such that the portion of the metal resistor element is in thermal communication with the portion of the thin film resistor element to compensate for a resistance drift arising during operation of the composite resistor.

一种压阻式压力传感器压敏电阻的制作方法

一种压阻式压力传感器压敏电阻的制作方法，该方法主要由清洗工艺、光刻工艺、扩散工艺、电感耦合等离子体刻蚀工艺、退火工艺组成。该发明目的在于将扩散工艺和电感耦合等离子刻蚀工艺相结合，提出一种简化的工艺方案，即配合刻蚀工艺，仅进行一次扩散掺杂工艺即可同时制作压阻式压力传感器轻、重掺杂区域的方法，减少MEMS压阻式压力传感器的工艺步骤及工艺成本。该方法可适用于包括但不限于基于硅衬底的压阻式压力传感器的轻掺杂及重掺杂区域制作，对于简化传感器制作的工艺步骤、降低制作成本具有重要的应用价值。

Verwendung von schichtigem übergitter material

Verfahren und vorrichtung für ein smd-element zum schützen der elektrischen komponenten gegen esd

一种改善焊接破裂的直流微电机用环形压敏电阻器

本发明公开了一种改善焊接破裂的直流微电机用环形压敏电阻器，包括具备非线性伏安特性的环形压敏电阻基片和烧结在基片端面上的等距离分布的至少3个独立电极，其中，任意两相邻电极间隙由电极边缘互相平行的直线和基片圆环上内外同心圆弧组成，且与圆环非正交，从现有技术的表面电极、电极间隙的对称性设置改为非对称性设置，不同导热系数的电极材质和基片材质在径向的电极间隙处有了互相间没有接触的交叉，焊接时的热量冲击通过非对称的电极在环形基片上非对称的传导，间接提高了压敏电阻整体导热分布的均匀性，基片焊接破裂的不良率得以下降，且环形压敏变阻器的非线性伏安特性电性能并没有改变，电容得以提高。

Isolierschicht-feldeffekttransistor

Isolierschicht-Feldeffekttransistor (MISFET) mit Drain (104), Source (106) und Gate (102), der dazu eingerichtet ist, bei angesteuertem Gate (102) in einem Kanalgebiet zwischen Drain (104) und Source (106) einen Kanal auszubilden, der einen Stromfluss zwischen Source (106) und Drain (104) ermöglicht, wobei in dem Isolierschicht-Feldeffekttransistor (100) integriert ein spannungsabhängiger Vorwiderstand (108) ausgebildet ist, der zwischen Source (106) und dem Kanalgebiet angeordnet und dazu eingerichtet ist, den Stromfluss zwischen Source (106) und Drain (104) zu beeinflussen.

一种多层片式压敏电阻器及其制备方法

本发明公开了一种多层片式压敏电阻器及其制备方法，其中制备方法包括：准备压敏材料膜片；将铜箔贴合在所述压敏材料膜片上并进行刻蚀，再将所述压敏材料膜片和贴合有所述铜箔的所述压敏材料膜片依次叠压形成坯体；将所述坯体进行压实、切割，形成成型样品；将所述成型样品烧结，形成多层片式压敏电阻瓷体；在所述多层片式压敏电阻瓷体的两个端头涂银电极后热处理，形成多层片式压敏电阻器。多层片式压敏电阻器是由上述制备方法制备得到。本发明提出的多层片式压敏电阻器及其制备方法，在降低压敏电阻器的制备成本的基础上还提高产品使用可靠性。

Passive microwave device and method for producing the same

The present invention provides an electrical circuit component, specifically a passive microwave device, and a method for producing the same. In one embodiment, the present invention provides an electrical circuit component, comprising: at least one patterned resistive area on a first surface of a diamond substrate, a first patterned conductive area on the first surface of the diamond substrate, and a second patterned conductive area on a second surface of the diamond substrate. The patterned resistive area may comprise a very thin film of tantalum nitride or a very thin film of tantalum nitride and a thin film of nichrome. The patterned conductive area may comprise a layer of titanium-tungsten, a layer of gold, and optionally a layer of nickel. Alternatively, the patterned conductive area may comprise a layer of chrome, a layer of copper, a layer of gold, and optionally a layer of nickel.

Oberflächen-montierbare Vorrichtung zum Schutz gegen elektrostatische Beschädigung von elektronischen Komponenten

包括电容器和分立变阻器的集成组件

一种集成组件可包括多层电容器，该多层电容器包括第一有源终端、第二有源终端、至少一个接地终端、以及在第一有源终端与第二有源终端之间串联连接的成对电容器。该集成组件可包括分立变阻器，该分立变阻器包括与多层电容器的第一有源终端连接的第一外部变阻器终端和与多层电容器的第二有源终端连接的第二外部变阻器终端。

低インダクタンス構成要素

【課題】（ＥＭＩ／ＥＳＤ保護機能付きの）低インダクタンスのフィルタ用容量素子を提供する。【解決手段】低インダクタンス構成要素１００は、第１のアクティブ端子１０４、第２のアクティブ端子１０６、第１の接地端子１０８、第２の接地端子１１０及び第１のアクティブ端子と第２のアクティブ端子との間に直列に接続された一対のコンデンサを含む多層モノリシックデバイスを含む。アクティブリード１１２、１１４、１１６、１１８が、第１のアクティブ端子、第２のアクティブ端子、第１の接地端子及び／又は第２の接地端子と結合され、それぞれの長さ１２０及び最大幅１２４を有し、それぞれの最大幅に対する長さの比は、約２０未満である。【選択図】図１Ａ

Low temperature process for fabricating layered superlattice materials and making electronic devices including same

A liquid precursor containing a metal is applied to a first electrode, RTP backed at a temperature of 700 °C, and annealed at the same temperature from 3 to 5 hours to form a layered superlattice material. A second electrode is formed to form a capacitor, and a second anneal is performed at a temperature of 700 °C. If the material is strontium bismuth tantalate, the precursor contains u mole-equivalents of strontium, v mole-equivalents of bismuth, and w mole-equivalents of tantalum, where 0.8 « u « 1.0, 2.0 « v « 2.3, and 1.9 « w « 2.1.

Voltage sensitive resistor (vsr) read only memory

A method to form a voltage sensitive resistor (VSR) read only memory (ROM) device on a semiconductor substrate having a semiconductor device including depositing by chemical vapor deposition (CVD) a titanium nitride layer having residual titanium-carbon bonding such that the VSR is resistive as formed and can become less resistive by at least an order of 10 2 when a predetermined voltage and current are applied to the VSR; and applying a predetermined voltage and current so as to make the CVD titanium nitride less resistive by at least an order of 10 2 .

Structure and material of over-voltage protection device and manufacturing method thereof

The present invention relates to a material and structure of an over-voltage protection device. The material of the over-voltage protection device includes either a P-type semiconductor powder or an N-type semiconductor powder and an adhesive. The structure of the over-voltage protection device includes a first electrode, a second electrode, and a porous matrix connected between the first and second electrodes. The present invention further relates to a method of manufacturing the over-voltage protection device.

산화물 박막

본 기술은 산화물 박막에 관한 것이다. 본 기술의 산화물 박막은 단결정 기판; 및 상기 단결정 기판 상에 적층되고, 이종 금속 원소로 도핑된 주산화물층;을 포함하되, 투과형 전자 현미경(TEM)을 이용한 에너지 분산형 X선 분석법(EDX)에서 상기 이종 금속 원소와 상기 주산화물층을 구성하는 금속 산화물의 금속 원소는 균일하게 분포되어 있을 수 있다. 본 기술은 신뢰성, 민감성, 정확성 및 재현성이 향상된 MIT 특성을 보이는 산화물 박막을 제공할 수 있다.

박막 기판 및 이를 포함하는 에너지 감응형 전자 부품

박막 기판 및 이를 포함하는 에너지 감응형 전자 부품

본 발명의 일 측면에 따른 박막 기판은, Al 2 O 3 단결정 베이스 기판; 및 상기 베이스 기판에 배치되고, Ti가 도핑되어 있는 VO 2 기능 박막 을 포함하고, 상기 기능 박막은, 25℃에서의 저항을 R1, 80℃에서의 저항을 R2라고 할 때, R1/R2 가 10 4 이상이고, 상기 기능 박막은, 25℃로부터 80℃까지의 승온 과정과 80℃부터 25℃까지의 냉각 과정을 1 싸이클이라고 할 때, 10 싸이클 동안 히스테리시스 온도 차(△T)의 변화(V △T )가 1℃ 이하이거나, 10 싸이클 동안 상전이 온도(T MI )의 변화(V TMI )가 1.5℃ 이하이거나, 10 싸이클 동안 R1/R2의 변화율(V R1/R2 )이 5% 이하일 수 있다.

過電圧保護素子の構造と材料、およびその製造方法

【課題】過電圧保護素子の材料と構造を提供する。 【解決手段】この材料は、Ｐ型半導体粉末又はＮ型半導体粉末と、粘着剤とを含む。この過電圧保護素子は、第一の電極と、第二の電極と、この第一の電極とこの第二の電極の間に接続される多孔質マトリクスとを含むように構成される。更にこの過電圧保護素子を製造する方法を提供する。 【選択図】図１

Multi-sided optical waveguide-fed photoconductive switches

A photoconductive switch and optical transconductance varistor having a photoconductive region e.g. a wide bandgap semiconductor material substrate between opposing electrodes. An optical waveguide is arranged to surround the photoconductive region for directing conduction-inducing radiation into the photoconductive region. And an optical diffusion element is arranged to diffuse/disperse the radiation prior to entering the optical waveguide and into the substrate, for uniformly illuminating the substrate for conduction.

Ring varistor for use in dc micromotor

The present invention provides a ring varistor for use in DC micromotor including a ring varistor substrate having nonlinear volt-ampere characteristics and at least three independent electrodes evenly sintered on an end face of the ring varistor substrate. The electrode gap between two adjacent electrodes consists of two straight parallel edges of the two adjacent electrodes, and an inner and an outer concentric arc on the substrate ring, the electrode gap is not orthogonal to the ring. Due to the asymmetry arrangement of the surface electrodes and the electrode gaps, the electrode materials and the substrate materials with different thermal conductivity have no contact cross distribution with each other at the radial electrode gap. During welding, the heat shock is transmitted asymmetrically through the asymmetric electrodes, to improve the uniformity of the heat conduction distribution of the varistor and reduce the defective rate of the substrate welding fracture.

表面実装型ヒューズデバイス

Thin-film substrate and energy-sensitive electronic component including same

Provided herein is a thin-film substrate including an Al 2 O 3 single crystal base substrate, and a VO 2 functional thin film disposed on the base substrate and doped with Ti, wherein, when R1 is a resistance at a temperature of 25° C. and R2 is a resistance at a temperature of 80° C., the functional thin film has an R1/R2 of 10 4 or more, and when a heating process from 25° C. to 80° C. and a cooling process from 80° C. to 25° C. are referred to as one cycle, a variation (VAT) in hysteresis temperature difference (ΔT) of the functional thin film during 10 cycles may be 1° C. or lower, a variation (V TMI ) in phase transition temperature (T MI ) of the functional thin film during 10 cycles may be 1.5° C. or lower, and a variation rate (V R1/R2 ) of R1/R2 of the functional thin film during 10 cycles may be 5% or less.

에너지 감응형 산화물 박막

본 기술은 산화물 박막에 관한 것이다. 본 기술의 산화물 박막은 단결정 기판; 및 상기 단결정 기판 상에 적층되고, 이종 금속 원소로 도핑된 주산화물층;을 포함하되, 투과형 전자 현미경(TEM)을 이용한 에너지 분산형 X선 분석법(EDX)에서 상기 이종 금속 원소와 상기 주산화물층을 구성하는 금속 산화물의 금속 원소는 균일하게 분포되어 있을 수 있다. 본 기술은 신뢰성, 민감성, 정확성 및 재현성이 향상된 MIT 특성을 보이는 산화물 박막을 제공할 수 있다.

산화물 박막

본 기술은 산화물 박막에 관한 것이다. 본 기술의 산화물 박막은 단결정 기판; 및 상기 단결정 기판 상에 적층되고, 이종 금속 원소로 도핑된 주산화물층;을 포함하되, 투과형 전자 현미경(TEM)을 이용한 에너지 분산형 X선 분석법(EDX)에서 상기 이종 금속 원소와 상기 주산화물층을 구성하는 금속 산화물의 금속 원소는 균일하게 분포되어 있을 수 있다. 본 기술은 신뢰성, 민감성, 정확성 및 재현성이 향상된 MIT 특성을 보이는 산화물 박막을 제공할 수 있다.

Voltage sensitive resistor (VSR) read only memory

Voltage sensitive resistor (VSR) read only memory

A method to form a voltage sensitive resistor (VSR) read only memory (ROM) device on a semiconductor substrate having a semiconductor device including depositing by chemical vapor deposition (CVD) a titanium nitride layer having residual titanium-carbon bonding such that the VSR is resistive as formed and can become less resistive by at least an order of 10 2 when a predetermined voltage and current are applied to the VSR; and applying a predetermined voltage and current so as to make the CVD titanium nitride less resistive by at least an order of 10 2 .

Verfahren zur herstellung von schichtigen supergittermaterialien.