СПОСОБ ИЗГОТОВЛЕНИЯ САМОСОВМЕЩЕННЫХ ТРАНЗИСТОРОВ СО СВЕРХКОРОТКОЙ ДЛИНОЙ КАНАЛА, ПОЛУЧАЕМОЙ НЕЛИТОГРАФИЧЕСКИМ МЕТОДОМ

Использование: для изготовления транзисторов со сверхкороткой длиной канала. Сущность изобретения: способ изготовления транзисторов со сверхкороткой длиной канала включает следующие этапы: осаждение электропроводящего материала на подложку из полупроводникового материала, формирование рельефа первых параллельных полосковых электродов с шагом, определяемым соответствующими правилами конструирования, при этом оставляют открытыми области подложки в виде полосок между первыми электродами, осаждение барьерного слоя, покрывающего первые электроды вплоть до подложки, легирование подложки в открытых областях, осаждение электропроводящего материала поверх легированных областей подложки с формированием вторых параллельных полосковых электродов, удаление барьерного слоя, при котором оставляют вертикальные каналы, проходящие вниз до нелегированных областей подложки между первыми и вторыми электродами, легирование подложки в открытых областях нижней части каналов, заполнение каналов барьерным материалом ...

Verfahren zur Herstellung von intergrierten Schaltungen mit Hochspannungs- und Niederspannungs-lateralen-DMOS-Leistungsbauelementen und nichtflüchtigen Speicherzellen

VARIABLE GATE-LÄNGEN FÜR VERTIKALE TRANSISTOREN

Ein Verfahren zu Fertigen einer vertikalen FET-Struktur beinhaltet vor einem Abscheiden eines Gates auf einem ersten vertikalen FET auf einem Halbleitersubstrat ein Abscheiden einer ersten Schicht auf dem ersten vertikalen FET auf dem Halbleitersubstrat. Das Verfahren beinhaltet des Weiteren vor einem Abscheiden eines Gates auf einem zweiten vertikalen FET auf dem Halbleitersubstrat ein Abscheiden einer zweiten Schicht auf dem zweiten vertikalen FET auf dem Halbleitersubstrat. Das Verfahren beinhaltet des Weiteren ein Ätzen der ersten Schicht auf dem ersten vertikalen FET bis zu einer geringeren Höhe als die zweite Schicht auf dem zweiten vertikalen FET. Das Verfahren beinhaltet des Weiteren ein Abscheiden eines Gate-Materials sowohl auf dem ersten vertikalen FET als auch auf dem zweiten vertikalen FET. Das Verfahren beinhaltet des Weiteren ein Ätzen des Gate-Materials sowohl auf dem ersten vertikalen FET als auch auf dem zweiten vertikalen FET bis zu einer koplanaren Höhe.

Verfahren zum Bilden von Halbleitervorrichtungen, bei dem elektrolysierte Schwefelsäure (ESA) verwendet wird

Ein Verfahren zum Bilden einer Halbleitervorrichtung kann ein Bilden einer Metallschicht (51) auf einem Siliziumbereich eines Substrats (10) und Reagieren der Metallschicht (51) mit dem Siliziumbereich zum Bilden eines Metallsilizids (53) aufweisen. Nach einem Reagieren der Metallschicht (51) kann ein nichtreagierter Rest (52) der Metallschicht (51) durch Verwenden einer elektrolysierten Schwefelsäurelösung entfernt werden. Insbesondere kann ein Volumen von Schwefelsäure in der elektrolysierten Schwefelsäurelösung in einem Bereich von ungefähr 70% bis ungefähr 95% des Gesamtvolumens der elektrolysierten Schwefelsäurelösung liegen, eine Konzentration von Oxidationsmittel in der elektrolysierten Schwefelsäurelösung kann in einem Bereich von ungefähr 7 g/L bis ungefähr 25 g/L liegen und eine Temperatur der elektrolysierten Schwefelsäurelösung kann in einem Bereich von ungefähr 130 Grad Celsius bis ungefähr 180 Grad Celsius liegen.

Fin-Feldeffekttransistor (Finfet) - Bauelementstruktur mit unebenem Gate und Verfahren zur Ausbildung derselben

Es wird eine FinFET-Bauelementstruktur geschaffen. Die FinFET-Bauelementstruktur umfasst eine Isolationsstruktur auf, die über einem Substrat ausgebildet ist, und eine Fin-Struktur, die über dem Substrat ausgebildet ist. Die FinFET-Bauelementstruktur umfasst eine erste Gate-Struktur und eine zweite Gate-Struktur, die über der Fin-Struktur ausgebildet sind, und die erste Gate-Struktur weist in einer Richtung parallel zur Fin-Struktur eine erste Breite auf, die zweite Gate-Struktur weist in einer Richtung parallel zur Fin-Struktur eine zweite Breite auf, und die erste Breite ist kleiner als die zweite Breite. Die erste Gate-Struktur umfasst eine erste Austrittsarbeit-Schicht, die eine erste Höhe aufweist. Die zweite Gate-Struktur umfasst eine zweite Austrittsarbeit-Schicht, die eine zweite Höhe aufweist, und eine Lücke zwischen der ersten Höhe und der zweiten Höhe liegt in einem Bereich von circa 1 nm bis zu circa 6 nm.

Nichtflüchtige Speicherbauelementstruktur und Verfahren zur Herstellung derselben

Die Erfindung bezieht sich auf eine nichtflüchtige Speicherbauelementstruktur mit einem Substrat (101), das einen Zellenbereich, einen Bereich für niedrige Spannung und einen Bereich für hohe Spannung beinhaltet, wobei ein Masseauswahltransistor (110), ein Kettenauswahltransistor (111) und ein Zellentransistor (112) in dem Zellenbereich ausgebildet sind und der Transistor (120) für niedrige Spannung in dem Bereich für niedrige Spannung ausgebildet ist und der Transistor (130) für hohe Spannung in dem Bereich für hohe Spannung ausgebildet ist, sowie auf ein Verfahren zur Herstellung einer derartigen Bauelementstruktur. Eine nichtflüchtige Speicherbauelementstruktur der Erfindung beinhaltet einen gemeinsamen Sourcekontakt (151) auf einem Störstellenbereich des Masseauswahltransistors und einen ersten Kontakt (153) für niedrige Spannung auf einem Störstellenbereich des Transistors für niedrige Spannung, wobei sich die Kontakte bis zu einer Höhe einer ersten Zwischenisolationsschicht (140) ...

A self-aligning patterning method

Configurable electronic device and method

HALBLEITERANORDNUNG UND VERFAHREN ZUR HERSTELLUNG DIESER HALBLEITERANORDNUNG.

A semiconductor device and manufacturing method thereof and electronic device

INTEGRATED CIRCUIT WITH A GATE STRUCTURE AND METHOD MAKING THE SAME

반도체 소자

... 반도체 소자가 제공된다. 본 발명의 일 실시예에 따른 반도체 소자는, 소자 분리막에 의해 정의되며, 제1 영역 및 제2 영역을 포함하는 활성 영역; 제1 영역과 제2 영역 사이에서 활성 영역 상을 가로질러 제1 방향으로 연장되며, 활성 영역과 소자 분리막의 경계 상에서 제1 영역을 향하여 제1 방향과 상이한 제2 방향으로 돌출된 제1 게이트 탭을 포함하는 게이트 전극; 제1 영역에 위치하고, 제1 방향으로 제1 폭을 가지는 제1 콘택 플러그; 및 제2 영역에 위치하고, 제1 방향으로 제1 폭보다 큰 제2 폭을 가지는 제2 콘택 플러그를 포함한다.

FABRICATION METHOD OF SEMICONDUCTOR DEVICE

PURPOSE: A fabrication method of semiconductor device is provided to form a device isolation oxidation during fabricating a MOSFET to be simplified. CONSTITUTION: A fabrication method of semiconductor device comprises steps of: sequentially forming and patterning a diffusion film and an insulation film on a substrate to form a stacked structure; etching the substrate exposed besides of the stacked structure; forming insulation film sidewall spacers on sides of the other stacked structure; forming a device isolation insulation film on the exposed substrate; removing the spacers and the insulation film on the diffusion layer to expose the substrate and the diffusion layer; depositing a gate insulation film on the exposed substrate and diffusion layer; forming sidewall spacers used as a gate on the exposed gate insulation film and the sidewalls of the diffusion layer; and forming a diffusion area. COPYRIGHT 2001 KIPO ...

Mos field effect transistor having thick edge gate insulating layer pattern and method of fabricating the same

Semiconductor device comprising p-MOS transistor and method of manufacturing the same

METHOD OF FABRICATING A SEMICONDUCTOR DEVICE HAVING A TRANSISTOR, HAVING A DUAL GATE USING A ION IMPLANT PROCESS TO FORMING A SOURCE/DRAIN

PURPOSE: A method of fabricating a semiconductor device having a transistor is provided to improve the degree of integration of a semiconductor by burying a gate electrode of a high voltage transistor in a gate trench. CONSTITUTION: A first gate trench(115a) is formed in a first active region of a semiconductor substrate(100). A first gate film(120a) partly filling the first gate trench is formed. A first spacer(130a) is formed on the upper sidewall of the first gate trench. A first ion injection process is performed and the first gate film is formed into a first conductive gate electrode(140). A first impurity region(139) same conductive as the first gate electrode is formed within the first active region. COPYRIGHT KIPO 2010 ...

Semiconductor device and method of fabricating the same

A semiconductor device includes a recessed trench in a substrate, a gate insulating layer including a first portion and a second portion, the first portion having a first thickness and covering lower portions of sidewalls of the recessed trench and a bottom surface of the recessed trench, and the second portion having a second thickness and covering upper portions of the sidewalls of the recessed trench, the second thickness being greater than the first thickness, a gate electrode filling the recessed trench, a first impurity region having a first concentration and disposed at opposing sides of the gate electrode, and a second impurity region having a second concentration greater than the first concentration and disposed on the first impurity region to correspond to the second portion of the gate insulating layer.

Method for manufacturing semiconductor integrated circuit device, and semiconductor integrated circuit device

Proposed are a semiconductor integrated circuit device production method and a semiconductor integrated circuit device in which when forming, in a production process, first selection gate electrodes (G2a, G2b) and second selection gate electrodes (G3a, G3b) that can be independently controlled, there is no need to further separately add an extra dedicated photomask step for electrically separating the first selection gate electrodes (G2a, G2b) and the second selection gate electrodes (G3a, G3b) in addition to a conventional dedicated photomask process for processing only a memory circuit area, thereby making it possible to reduce production costs.

Device having multiple transistors and electronic apparatus

Two or more types of fin-based transistors having different gate structures and formed on a single integrated circuit are described. The gate structures for each type of transistor are distinguished at least by the thickness or composition of the gate dielectric layer(s) or the composition of the work function metal layer(s) in the gate electrode. Methods are also provided for fabricating an integrated circuit having at least two different types of fin-based transistors, where the transistor types are distinguished by the thickness and composition of the gate dielectric layer(s) and/or the thickness and composition of the work function metal in the gate electrode.

Integrated circuit device

Examples of an integrated circuit with FinFET devices and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate, a fin extending from the substrate, a gate disposed on a first side of the fin, and a gate spacer disposed alongside the gate. The gate spacer has a first portion extending along the gate that has a first width and a second portion extending above the first gate that has a second width that is greater than the first width. In some such examples, the second portion of the gate spacer includes a gate spacer layer disposed on the gate.

Method of manufacturing semiconductor devices

A method of manufacturing a semiconductor device includes forming first sacrificial cores on a first region of a lower structure and second sacrificial cores on a second region of the lower structure, forming spacers on side walls of the first sacrificial cores and side walls of the second sacrificial cores, forming a protective pattern covering the second sacrificial cores on the second region of the lower structure, removing the first sacrificial cores from the first region, and etching the lower structure using the spacers on the first region, and the second sacrificial cores and the spacers on the second region.

Method for fabricating semiconductor device

A method for fabricating a semiconductor device, which comprises the following steps: (i-a) forming at least one impurity region of a first conductivity type in a semiconductor substrate; (ii-a) forming a gate insulation film and a gate electrode on the impurity region of the first conductivity type followed by the formation of impurity diffusion layers of a second conductivity type in self-alignment with the gate electrode to yield a plurality of transistors; (iii-a) forming low-concentration impurity layers of the second conductivity type in peripheral portions of the impurity diffusion layers of the second conductivity type ; and (iv-a) implanting impurity ions of the first conductivity type into desired regions between the plurality of transistors to form device isolation regions, thus converting at least a part of the low-concentration impurity layers of the second conductivity type to low-concentration impurity layers of the first conductivity type.

A MOS DEVICE ASSEMBLY

A MOS device assembly comprising at least a first transistor (110) and a second transistor (111), each having a gate region. The dimensions of the gate region of the first transistor are different from the dimensions of the gate region of the second transistor and the transconductance of the MOS device assembly is substantially uniform when the gate regions of the first and second transistors are biased using the same voltage.

FINFET TRANSISTORS

A fin FET array includes a number of fins 12 and a switch FET 52 between fins 12. The switch FET 52 acts to divide the transistor array into first 42 and second 44 FINFET regions having first 46 and second 48 gate electrodes controllably connected through the switch FET 52. Suitable voltages applied between the gate of the switch FET and the substrate 10 can allow the fin FET array either to act as a plurality of separate FETs or as a single device. A method of making the fin FET array to reduce the number of additional steps to fabricate the switch FET 52 is also described.

SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR

The gate electrodes (1-1, 2-1, 3-1) of parallel-connected transistors (Tr1, Tr2, Tr3) have different gate widths with different distances between adjacent gate electrodes, and associated gate electrodes in a source region and a drain region have varying lengths along a gate width direction and different areas in different transistors (Tr1, Tr2, Tr3). Therefore, the correlation of characteristics such as a gate length between transistors (Tr1, Tr2, Tr3) in the same transistor group lowers to thereby decrease variations in characteristics between a plurality of transistor groups.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE

Semiconductor devices and methods of manufacturing semiconductor devices with differing threshold voltages are provided. In embodiments the threshold voltages of individual semiconductor devices are tuned through the removal and placement of differing materials within each of the individual gate stacks within a replacement gate process, whereby the removal and placement helps keep the overall process window for a fill material large enough to allow for a complete fill. 1. A method comprising:depositing a gate dielectric over a first region, a second region, and a third region;depositing a first metal material over the first region, the second region, and the third region;depositing a first work function layer over the first region, the second region, and the third region;forming a first capping layer over the first region, the second region, and the third region on the first work function layer, the first capping layer comprising an insulating material;removing the first capping layer from the second region;removing the first capping layer and the first work function layer from the first region; anddepositing a fill material over the first region, the second region, and the third region after the removing the first work function layer from the first region.2. The method of claim 1 , wherein the first work function layer comprises tungsten claim 1 , tungsten oxide claim 1 , tungsten nitride claim 1 , molybdenum claim 1 , or molybdenum nitride.3. The method of claim 1 , wherein the first capping layer comprises silicon oxide or silicon nitride.4. The method of claim 3 , wherein forming the first capping layer comprises performing a silicon-based gas soak to deposit a silicon-based dielectric.5. The method of claim 4 , wherein forming the first capping layer further comprises breaking vacuum in a processing chamber claim 4 , thereby oxidizing a silicon layer formed by the silicon-based gas soak.6. The method of claim 1 , wherein a thickness of the first capping layer ...

Multiple gate length vertical field-effect-transistors

Various embodiments disclose a method for fabricating a semiconductor structure. In one embodiment, the method includes forming a masking layer over at least a first portion of a source contact layer formed on a substrate. At least a second portion of the source contact layer is recessed below the first portion of the source contact layer. The mask layer is removed and a first spacer layer, a replacement gate on the first spacer layer, a second spacer layer on the replacement gate, and an insulating layer on the second spacer layer are formed. First and second trenches are then formed. A first channel layer is epitaxially grown within the first trench. A second channel layer is epitaxially grown within the second trench. A length of the second channel layer is greater than a length of the first channel layer.

Asymmetrical devices for short gate length performance with disposable sidewall

An asymmetrical channel implant from source to drain improves short channel characteristics. The implant provides a relatively high VT net dopant adjacent to the source region and a relatively low VT net dopant in the remainder of the channel region. One way to achieve this arrangement with disposable gate processing is to add disposable sidewalls inside the gate opening (after removing the disposable gate), patterning to selectively remove the source or gate side sidewalls, implant the source and drain regions and remove the remaining sidewall and the proceed. According to a second embodiment, wherein the channel implant can be symmetrical, a relatively low net VT implant is provided in the central region of the channel and a relatively high net VT implant is provided in the channel regions adjacent to the source and drain regions.

System-on-chip (SOC) solutions with multiple devices by multiple poly gate trimming process

A method of forming gate electrode layer portions having differing widths comprising the following steps. A structure having a gate electrode layer and a hard mask layer thereover and including two or more active areas is provided. The hard mask layer is patterned to form two or more respective hard mask layer portions within the two or more active areas. One or more of the two or more respective hard mask layer portions is/are selectively trimmed to reduce its/their width to a second width leaving at least one the respective hard mask layer portions untrimmed. The gate electrode layer is then patterned.

Semiconductor device and its manufacture method

Multiple kinds of transistors exhibiting desired characteristics are manufactured in fewer processes. A semiconductor device includes an isolation region reaching a first depth, first and second wells of first conductivity type, a first transistor formed in the first well and having a gate insulating film of a first thickness, and a second transistor formed in the second well and having a gate insulating film of a second thickness less than the first thickness. The first well has a first impurity concentration distribution having an extremum maximum value only at the depth equal to or greater than the first depth. The second well has a second impurity concentration distribution which is superposition of the first impurity concentration distribution, and another impurity concentration distribution which shows an extremum maximum value at a second depth less than the first depth, the superposition shows also an extremum maximum value at the second depth.

Process for manufacturing integrated circuit with power field effect transistors

A manufacturing process for an integrated circuit which includes at least one vertical-current-flow MOS transistor. The patterned photoresist which screens the body implant is also used to mask the etching of a nitride layer over a pad oxide. After the photoresist is cleared, the nitride pattern is transferred into the oxide, and the resulting oxide/nitride stack is used to mask the source implant. The nitride/oxide stack is then removed, the gate oxide is grown, and the gate layer is then deposited.

Semiconductor device and method for manufacturing the same

A semiconductor device of the invention integrates a plurality of types of MOSFETs formed on its substrate in such a configuration that a gate insulator film 51 of a core-purpose MOSFET is thinner than a gate insulator film 12 of an I/O-purpose MOSFET and also a poly-silicon film 8 which is to act as a gate electrode of the core-purpose MOSFET is thinner in thickness than a poly-silicon 13 which is to act as a gate electrode of the I/O-purpose MOSFET.

SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME

A semiconductor device structure, along with methods of forming such, are described. The structure includes a first and second gate electrode layers, and a dielectric feature disposed between the first and second gate electrode layers. The dielectric feature has a first surface. The structure further includes a first conductive layer disposed on the first gate electrode layer. The first conductive layer has a second surface. The structure further includes a second conductive layer disposed on the second electrode layer. The second conductive layer has a third surface, and the first, second, and third surfaces are coplanar. The structure further includes a third conductive layer disposed over the first conductive layer, a fourth conductive layer disposed over the second conductive layer, and a dielectric layer disposed on the first surface of the dielectric feature. The dielectric layer is disposed between the third conductive layer and the fourth conductive layer. 1. (canceled)2. A semiconductor device structure , comprising:a first gate electrode layer;a second gate electrode layer adjacent the first gate electrode layer;a dielectric feature disposed between the first gate electrode layer and the second gate electrode layer, wherein the dielectric feature has a first surface;a first conductive layer disposed on the first gate electrode layer, wherein the first conductive layer has a second surface;a second conductive layer disposed on the second gate electrode layer, wherein the second conductive layer has a third surface, wherein the first surface, the second surface, and the third surface are coplanar;a third conductive layer disposed over the first conductive layer;a fourth conductive layer disposed over the second conductive layer;a dielectric layer disposed on the first surface of the dielectric feature, wherein the dielectric layer is disposed between the third conductive layer and the fourth conductive layer;a first plurality of semiconductor layers, wherein ...

SEMICONDUCTOR DEVICES

A semiconductor device includes a substrate including first and second active regions extending in a first direction and isolated from direct contact with each other in the first direction; a device isolation layer between the first and second active regions in the substrate; and first and second gate structures extending in a second direction on the substrate while respectively intersecting end portions of the first and second active regions. The first gate structure includes a first gate electrode. The second gate structure includes a second gate electrode. The first gate structure protrudes further toward the device isolation layer, as compared to the second gate structure, in a vertical direction that is perpendicular to the first and second directions, and a lower end of the first gate electrode is located on a lower height level than a lower end of the second gate electrode.

Method for fabricating mask ROM semiconductor device with junction isolation

A method for fabricating a semiconductor device is provided, which includes the steps of: (i-a) forming at least one impurity region of a first conductivity type in a semiconductor substrate; (ii-a) forming a gate insulation film and a gate electrode on the impurity region of the first conductivity type followed by the formation of impurity diffusion layers of a second conductivity type in self-alignment with the gate electrode to yield plurality of transistors; (iii-a) forming low-concentration impurity layers of the second conductivity type in peripheral portions of the impurity diffusion layers of the second conductivity type; and (iv-a) implanting impurity ions of the first conductivity type into desired regions between the plurality of transistors to form device isolation regions, whereby converting at least a part of the low-concentration impurity layers of the second conductivity type to a low-concentration impurity layers of the first conductivity type.

Semiconductor device and method for manufacturing the same

In a semiconductor device including a core transistor and an I/O transistor on the same semiconductor substrate, the core transistor includes a gate insulating film, a gate electrode, sidewalls, extension diffusion layers, and source/drain diffusion layers. The I/O transistor includes a gate insulating film, a gate electrode, sidewalls, and source/drain diffusion layers. In the I/O transistor, the source/drain diffusion region is offset relative to a channel region located beneath the gate insulating film in regions below the sidewalls.

Methods of forming field effect transistors having t-shaped gate electrodes using carbon-based etching masks

Methods of forming field effect transistors include forming a first electrically insulating layer comprising mostly carbon on a surface of a semiconductor substrate and patterning the first electrically insulating layer to define an opening therein. A trench is formed in the substrate by etching the surface of the substrate using the patterned first electrically insulating layer as an etching mask. The trench is filled with a gate electrode. The first electrically insulating layer is patterned in an ambient containing oxygen. This oxygen-containing ambient supports further oxidation of trench-based isolation regions within the substrate when they are exposed by openings within the first electrically insulating layer.

FORMING A COMBINATION OF LONG CHANNEL DEVICES AND VERTICAL TRANSPORT FIN FIELD EFFECT TRANSISTORS ON THE SAME SUBSTRATE

A method of forming a vertical transport fin field effect transistor and a long-channel field effect transistor on the same substrate, including, forming a recessed region in a substrate and a fin region adjacent to the recessed region, forming one or more vertical fins on the fin region, forming a long-channel pillar from the substrate in the recessed region, where the long-channel pillar is at a different elevation than the one or more vertical fins, forming two or more long-channel source/drain plugs on the long-channel pillar, forming a bottom source/drain plug in the fin region, where the bottom source/drain plug is below the one or more vertical fins, forming a gate structure on the long-channel pillar and a gate structure on the one or more vertical fins, and forming a top source/drain on the top surface of the one or more vertical fins.

Semiconductor device and manufacturing method of semiconductor device

A semiconductor device includes a memory transistor including a first side wall insulating film and a second side wall insulating film disposed on the outside; a high-voltage transistor including a third side wall insulating film having the same composition as that of the first side wall insulating film, and a fourth side wall insulating film having the same composition as that of the second side wall insulating film, the fourth side wall insulating film being disposed on the outside; and a low-voltage transistor including a fifth side wall insulating film having the same composition as that of the second and fourth side wall insulating films. The memory transistor, the high-voltage transistor, and the low-voltage transistor are disposed on the same substrate. A total side wall spacer width of the low-voltage transistor is smaller than that of the high-voltage transistor by a thickness corresponding to the third side wall insulating film.

Semiconductor device integrated with converter and package structure thereof

The present invention provides a semiconductor device including a semiconductor substrate having a first conductive type, at least one high-side transistor device and at least one low-side transistor device. The high-side transistor device includes a doped high-side base region having a second conductive type, a doped high-side source region having the first conductive type and a doped drain region having the first conductive type. The doped high-side base region is disposed within the semiconductor substrate, and the doped high-side source region and the doped drain region are disposed within the doped high-side base region. The doped high-side source region is electrically connected to the semiconductor substrate, and the semiconductor substrate is regarded as a drain of the low-side transistor device.

METHOD OF MANUFACTURING NON-VOLATILE MEMORY

A method of manufacturing a non-volatile memory is provided. A substrate includes a memory cell region and a first periphery circuit region. The memory cell region includes a select transistor region. A first gate dielectric layer having a first thickness is formed on the substrate in the first periphery circuit region and the select transistor region. A portion of the first gate dielectric layer on the select transistor region is removed to form a second gate dielectric layer. The second dielectric layer has a second thickness, wherein the second thickness is less than the first thickness.

Semiconductor device and method for fabricating the same

A semiconductor device includes: a semiconductor substrate divided into a first region and a second region; a first MIS transistor formed in the first region of the semiconductor substrate and including a stack of a first gate insulating film and a fully-silicided first gate electrode; and a second MIS transistor formed in the second region of the semiconductor substrate and including a stack of a second gate insulating film and a fully-silicided second gate electrode. The second gate electrode has a gate length larger than that of the first gate electrode. A middle portion in the gate length direction of the second gate electrode has a thickness smaller than the thickness of the first gate electrode.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device includes a first channel region disposed over a substrate, and a first gate structure disposed over the first channel region. The first gate structure includes a gate dielectric layer disposed over the channel region, a lower conductive gate layer disposed over the gate dielectric layer, a ferroelectric material layer disposed over the lower conductive gate layer, and an upper conductive gate layer disposed over the ferroelectric material layer. The ferroelectric material layer is in direct contact with the gate dielectric layer and the lower gate conductive layer, and has a U-shape cross section.

GATE RESISTANCE IMPROVEMENT AND METHOD THEREOF

The present disclosure describes structure and method of a fin field-effect transistor (finFET) device. The finFET device includes: a substrate, a fin over the substrate, and a gate structure over the fin. The gate structure includes a work-function metal (WFM) layer over an inner sidewall of the gate structure. A topmost surface of the WFM layer is lower than a top surface of the gate structure. The gate structure also includes a filler gate metal layer over the topmost surface of the WFM layer. A top surface of the filler gate metal layer is substantially co-planar with the top surface of the gate structure. The gate structure further includes a self-assembled monolayer (SAM) between the filler gate metal layer and the WFM layer.

SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF

A method includes forming a gate layer over a semiconductor fin; forming a patterned mask over the gate layer; performing a first etching process to pattern the gate layer using the patterned mask as an etch mask, the patterned gate layer comprising a first gate extending across the semiconductor fin; depositing, by using an directional ion beam, a protection layer to wrap around a top surface, a first sidewall and a second sidewall of the first gate, the protection layer extending along the first and second sidewalls of the first gate towards a bottom surface of the first gate without extending to the bottom surface of the first gate on the second sidewall of the first gate; and after depositing the protection layer, performing a second etching process to a portion of the second sidewall of the first gate exposed by the protection layer.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device includes plurality of fin structures extending in first direction on semiconductor substrate. Fin structure's lower portion is embedded in first insulating layer. First gate electrode and second gate electrode structures extend in second direction substantially perpendicular to first direction over of fin structures and first insulating layer. The first and second gate electrode structures are spaced apart and extend along line in same direction. First and second insulating sidewall spacers are arranged on opposing sides of first and second gate electrode structures. Each of first and second insulating sidewall spacers contiguously extend along second direction. A second insulating layer is in region between first and second gate electrode structures. The second insulating layer separates first and second gate electrode structures. A third insulating layer is in region between first and second gate electrode structures. The third insulating layer is formed of different ...

METAL GATE STRUCTURE AND MANUFACTURING METHOD THEREOF

A method of manufacturing a semiconductor structure includes receiving a substrate; patterning a first active region, a second active region and an isolation between the first active region and the second active region over the substrate; disposing an inter-level dielectric (ILD) over the substrate; forming a first gate extended over the first active region, the isolation and the second active region; and forming a second gate over the first active region and the second active region, wherein the second gate includes a first section disposed over the first active region and a second section disposed over the second active region, a portion of the ILD is disposed between the first section and the second section.

Series resistor over drain region in high voltage device

Some embodiments relate to a semiconductor device. The semiconductor device includes a drain region and a channel region surrounding the drain region. A source region surrounds the channel region such that the channel region separates the drain region from the source region. A gate electrode is arranged over the channel region and has an inner edge proximate to the drain. A resistor structure, which is made up of a curved or polygonal path of resistive material, is arranged over the drain and is coupled to the drain. The resistor structure is perimeterally bounded by the inner edge of the gate electrode.

INTEGRATING A PLANAR FIELD EFFECT TRANSISTOR (FET) WITH A VERTICAL FET

One embodiment provides a method of integrating a planar field-effect transistor (FET) with a vertical FET. The method comprises masking and etching a semiconductor of the vertical FET to form a fin, and providing additional masking, additional etching, doping and depositions to isolate a bottom source/drain (S/D) region. A dielectric is formed on the bottom S/D region to form a spacer. The method further comprises depositing gate metals, etching a vertical gate for the vertical FET and a planar gate for the planar FET using a shared gate mask, depositing dielectric, etching the dielectric to expose one or more portions of the fin, growing epitaxy on a top S/D region, masking and etching S/D contact openings for the bottom S/D region, forming silicide regions in S/D regions, depositing contact metal in the silicide regions to form contacts, and planarizing the contacts.

Semiconductor memory device

The present invention is a semiconductor memory device having a logic block and a memory block on the same chip. In the memory device, unit memory cells each include at least two transistors, one of which is a write transistor for storing an electric charge into and releasing it from an electric charge storage node, and the other is a read transistor whose conductance in a channel region provided between a source and drain of the read transistor is modulated dependently on the amount of electric charge stored into or released from the electric charge storage node by the write transistor. The read transistor has a gate-insulating film thicker than that of a transistor provided in the logic block, and uses the same diffusion layer structure as that of the logic block.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

In an LCD driver, in a high voltage resistant MISFET, end portions of a gate electrode run onto electric field relaxing insulation regions. Wires to become source wires or drain wires are formed on an interlayer insulation film of the first layer over the high voltage resistant MISFET. At this moment, when a distance from an interface between a semiconductor substrate and a gate insulation film to an upper portion of the gate electrode is defined as a, and a distance from the upper portion of the gate electrode to an upper portion of the interlayer insulation film on which the wires are formed is defined as b, a relation of a>b is established. In such a high voltage resistant MISFET structured in this manner, the wires are arranged so as not to be overlapped planarly with the gate electrode of the high voltage resistant MISFET.

TRANSISTOR WITH DUAL SPACER AND FORMING METHOD THEREOF

A transistor with dual spacers includes a gate, a first dual spacer and a second inner spacer. The gate is disposed on a substrate, wherein the gate includes a gate dielectric layer and a gate electrode, and the gate dielectric layer protrudes from the gate electrode and covers the substrate. The first dual spacer is disposed on the gate dielectric layer beside the gate, wherein the first dual spacer includes a first inner spacer and a first outer spacer. The second inner spacer having an L-shaped profile is disposed on the gate dielectric layer beside the first dual spacer. The present invention also provides a method of forming said transistor with dual spacers.

Replacement gate process for semiconductor devices

Disclosed is a method of forming a semiconductor device. The method includes providing a precursor having a substrate and gate stacks over the substrate, wherein each of the gate stacks includes an electrode layer, a first hard mask (HM) layer over the electrode layer, and a second HM layer over the first HM layer. The method further includes depositing a dielectric layer over the substrate and the gate stacks and filling spaces between the gate stacks; and performing a first chemical mechanical planarization (CMP) process to partially remove the dielectric layer. The method further includes performing an etching process to remove the second HM layer and to partially remove the dielectric layer, thereby exposing the first HM layer. The method further includes performing a second CMP process to at least partially remove the first HM layer.

Method for manufacturing semiconductor device

A method for manufacturing a semiconductor device comprising: providing a substrate, wherein a first gate structure corresponding to a dense area transistor and a second gate structure corresponding to an isolated area transistor are formed on the substrate, and the first gate structure is higher than the second gate structure; forming a buffer layer over the second gate structure, wherein the upper surface of the buffer layer is flush with the upper surface of the first gate structure; and removing the top of the first gate structure, and forming a hard mask filling layer on a top area of the first gate structure.

Improvements in or relating to semiconductor processing

A process flow which can be used to fabricate a high frequency bipolar transistor 147, a power transistor 146, and non-power MOS devices on a single substrate while maintaining superior performance. The process flow forms an initial high-voltage tank 170 in substrate 150. A thin epitaxial layer 156 is formed on the substrate which overlies the initial high voltage tank and Diffusion Under Film, DUF, region 154. The high voltage tank is extended through the epitaxial layer and power transistor 146 is formed in the high voltage tank and high frequency bipolar transistor 147 is formed in the epitaxial layer using the DUF region as a deep collector. Other types of low voltage devices 139 and 140 and mid voltage devices 141-145 and 148-149 are formed unaffected by the presence of epitaxial layer 156. A single chip transmitter 400 and a single chip receiver 410 is fabricated with high frequency transistors and power devices. A single chip disk controller 460 is fabricated with high frequency ...

SEMICONDUCTOR DEVICE AND MEMORY DEVICE INCLUDING A DUMMY ELEMENT

A semiconductor device (200) includes a plurality of semiconductor elements (210), each of the plurality of semiconductor elements (210) including an active region (211) disposed on a substrate (201), and a gate structure (215) intersecting the active region (211) and extending in a first direction that is parallel to an upper surface of the substrate (201); and at least one dummy element (220) disposed between a pair of semiconductor elements adjacent to each other in a second direction, intersecting the first direction, among the plurality of semiconductor elements (210). The dummy element (220) includes a dummy active region (221) and at least one dummy gate structure (225) intersecting the dummy active region (221) and extending in the first direction. A length of the dummy active region (221) in the second direction is less than a length of the active region (211) included in each of the pair of semiconductor elements (210).

INTEGRATED CIRCUIT STRUCTURE HAVING ANTI-FUSE STRUCTURE

Integrated circuit structures having anti-fuse structures, and methods of fabricating integrated circuit structures having anti-fuse structures, are described. For example, an integrated circuit structure (600) includes a first vertical stack of horizontal nanowires (108). A first gate structure (602) is over the first vertical stack of horizontal nanowires, the first gate structure including a first gate dielectric (612) and a first gate electrode (614) completely surrounding a channel region of each nanowire of the first vertical stack of horizontal nanowires. The integrated circuit structure also includes a second vertical stack of horizontal nanowires (108). A second gate structure (604) is over the second vertical stack of horizontal nanowires, the second gate structure including a second gate dielectric (662) and a second gate electrode (664) only partially surrounding a channel region of each nanowire of the second vertical stack of horizontal nanowires.

SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To provide a highly reliable semiconductor device. SOLUTION: A semiconductor device is provided with an element area consisting of semiconductor of one conductivity type in which a semiconductor element is formed, and an element separation area which is formed in contact with the element area and separates electrically the element area from other element areas. The element area has a bent part, and that an angle formed on the above element separation area among angles formed by two sides of the element area is obtuse angle. By adopting this constitution, a semiconductor device with high reliability can be provided. COPYRIGHT: (C)2001,JPO ...

Verfahren zum Herstellen einer Halbleitervorrichtung mit reduzierter Dicke

Verfahren zum Herstellen einer Halbleitervorrichtung mit folgenden Schritten:Vorbereiten eines Halbleitersubstrats (1; 100; 200), das eine erste und eine zweite aktive Region (3a, 3b; 103a, 103b; 203a, 203b) hat;Bilden eines ersten Transistors (CT1, CT2; CT3, CT4; CT5, CT6) in der ersten aktiven Region (3a; 103a; 203a), wobei der erste Transistor (CT1, CT2; CT3, CT4; CT5, CT6) eine erste Gatestruktur (24; 124; 224) und erste Störstellenregionen (18a, 18b; 118a, 118b; 218a, 218b) aufweist;Bilden eines zweiten Transistors (PT1; PT2) in der zweiten aktiven Region (3b; 103b; 203b), wobei der zweite Transistor (PT1; PT2) eine zweite Gatestruktur (40; 140) und zweite Störstellenregionen (48; 148) aufweist; undBilden einer ersten leitfähigen Struktur (39a; 139a) an dem ersten Transistor (CT1, CT2; CT3, CT4; CT5, CT6), wobei mindestens ein Teil der ersten leitfähigen Struktur (39a; 139a) in einer gleichen Entfernung von einer oberen Oberfläche des Halbleitersubstrats (1; 100; 200) wie mindestens ...

Verfahren und Struktur für vertikalen Tunnel-Feldeffekttransistor und planare Vorrichtungen

Die vorliegende Offenbarung sieht eine Ausführungsform eines Verfahrens zum Ausbilden eines Tunnel-Feldeffekttransistors (TFETs) vor. Das Verfahren umfasst das Ausbilden einer Halbleitermesa auf einem Halbleitersubstrat; das Anwenden einer ersten Implantation auf das Halbleitersubstrat und die Halbleitermesa, um einen Drain von einer ersten Art von Leitfähigkeit auszubilden; das Ausbilden einer ersten dielektrischen Schicht auf dem Halbleitersubstrat und Seitenwänden der Halbleitermesa; das Ausbilden eines Gatestapels auf der Seitenwand der Halbleitermesa und der ersten dielektrischen Schicht; das Ausbilden einer zweiten dielektrischen Schicht auf der ersten dielektrischen Schicht und dem Gatestapel; und das Ausbilden einer Source auf der Halbleitermesa, die eine zweite Art von Leitfähigkeit aufweist, die der ersten Art von Leitfähigkeit entgegengesetzt ist. Der Gatestapel umfasst ein Gate-Dielektrikum und eine Gate-Elektrode auf dem Gate-Dielektrikum. Die Source, der Drain und der Gatestapel ...

Verbesserte Füllbedingungen in einem Austauschgateverfahren durch Ausführen eines Polierprozesses auf der Grundlage eines Opferfüllmaterials

In einem Austauschgateverfahren erhält ein oberer Bereich einer Gateöffnung eine verbesserte Querschnittsform nach dem Abscheiden einer austrittsarbeitseinstellenden Sorte auf der Grundlage eines Polierprozesses, wobei ein Opfermaterial die empfindlichen Materialien in der Gateöffnung schützt.

Durchdringendes Implantieren zum Bilden einer Halbleitereinheit

Halbleitereinheit, die aufweist: einen Gatterstapel, der auf einem Substrat angeordnet ist; Spitzenbereiche, welche dotierende Störatome eines ersten Leitfähigkeitstyps aufweisen, die in dem Substrat auf jeder Seite des Gatterstapels angeordnet sind; Halo-Bereiche, die dotierende Störatome eines zweiten Leitfähigkeitstyps, der dem ersten Leitfähigkeitstyp entgegengesetzt ist, aufweisen, die in dem Substrat benachbart den Spitzenbereichen angeordnet sind; und einen Schwellenspannungs-Implantierbereich, der dotierende Störatome des zweiten Leitfähigkeitstyps aufweist, der in dem Substrat direkt unterhalb des Gatterstapels angeordnet ist, wobei die Konzentration der dotierenden Störatome des zweiten Leitfähigkeitstyps in dem Schwellenspannungs-Implantierbereich ungefähr dieselbe ist wie die Konzentration der dotierenden Störatome des zweiten Leitfähigkeitstyps in den Halo-Bereichen.

Configurable electronic device and method

Integration method of a semiconductor device having a recessed gate electrode

Semiconductor device and method of manufacturing the same

The invention discloses a semiconductor device and a method of manufacturing the same. The semiconductor device includes a semiconductor substrate including a first driving transistor region having a first driving transistor disposed therein and a second driving transistor region having a second driving transistor disposed therein, wherein the second driving transistor is driven at a lower voltage than the first driving transistor, a first gate insulating layer formed at edges of the second driving transistor region, and a second gate insulating layer formed at a center of the second driving transistor region, wherein the first gate insulating layer is thicker than the second gate insulating layer.

Semiconductor device

FIELD-EFFECT TRANSISTORS HAS MODE DEPLETION AND HAS JUST MODE ENRICHISSEMENTMONOLITHIQUEMENT AND PROCESS TO MANUFACTURE THEM

SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME HAVING RECESSED CHANNEL ARRAY TRANSISTOR CAPABLE OF IMPROVING RELIABILITY

PURPOSE: A semiconductor device and a method for forming the same are provided to form a silicide layer irrespective of leakage current and reduce contact resistance by increasing a depth of a junction region according to a recess channel. CONSTITUTION: A dummy pattern is formed on a semiconductor substrate(11). A source region(33) and a drain region(34) are formed on the semiconductor substrate corresponding to both sides of the dummy pattern. A first metal silicide layer(41) is formed on the source region and the drain region. A recess region is formed on the semiconductor substrate corresponding to a lower side of the dummy pattern. A gate insulating layer(53) and a gate electrode(55) are formed on the recess region. © KIPO 2007 ...

A SEMICONDUCTOR MEMORY DEVICE WITH TRIPLE WELL STRUCTURE

METHOD FOR FABRICATING SEMICONDUCTOR DEVICE

Manufacturing method of the semiconductor body

SEMICONDUCTOR DEVICE INCLUDING A GATE STRUCTURE WITH LOW RESISTANCE, AND A MANUFACTURING METHOD THEREOF

PURPOSE: A semiconductor device and a manufacturing method thereof are provided to form a gate structure with low resistance in spite of a narrow line width by increasing the thickness of a conductive pattern with low resistance. CONSTITUTION: A first conductive structure(117a) is comprised in a first area of a substrate(100). A first poly silicon pattern, a first conductive pattern(115a), and a first mask pattern are formed on the first conductive structure. A second conductive structure(117b) is comprised in a second area of the substrate. A second poly silicon pattern, a second conductive pattern(115b), and a second mask pattern are formed on the second conductive structure. The second conductive structure has the same thickness as the first conductive structure. COPYRIGHT KIPO 2010 ...

MANUFACTURING METHOD OF A SEMICONDUCTOR DEVICE EQUIPPED WITH THE BURIED GATE, CAPABLE OF PREVENTING THE PROPERTY DETERIORATION OF THE SEMICONDUCTOR

PURPOSE: A manufacturing method of a semiconductor device equipped with the buried gate is provided to prevent the formation of a protrusion on a boundary area between a cell area and a peri area by forming a gate conductive layer on the peri area before forming a plug. CONSTITUTION: A gate conductive film(37A) is selectively formed on the peri area of a substrate(31) having the cell area and the peri area. A sealing film(39) is formed along the structure surface including the gate conductive film. An insulating layer(40A) is formed on the sealing film in order to cover the structure including the gate conductive film. COPYRIGHT KIPO 2011 ...

N/P BOUNDARY EFFECT REDUCTION FOR METAL GATE TRANSISTORS

SEMICONDUCTOR DEVICE WITH REDUCED DISHING AND METHOD OF MANUFACTURING THE SAME

PURPOSE: A semiconductor device and a method of manufacturing the same are provided to reduce dishing of an interlayer dielectric at a periphery of a mark region by using a dishing prevention pattern. CONSTITUTION: The first patterns(3a,3b) are formed on a semiconductor substrate(1) within a device region(A1). The second pattern(3c) is formed on the substrate within an alignment mark region(A2). The second pattern is used as a dishing prevention pattern. An interlayer dielectric(4) for enclosing the first and second patterns is deposited thereon. The interlayer dielectric on the first and second patterns is selectively etched by using a predetermined photoresist pattern. The photoresist pattern is removed therefrom. The first and second patterns are exposed by planarizing the interlayer dielectric using CMP(Chemical Mechanical Polishing). © KIPO 2005 ...

SEMICONDUCTOR DEVICE MANUFACTURING METHOD

Disclosed are a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a semiconductor substrate divided into an active area defined by a device membrane, a gate area including a pair of gate trenches extended in a first direction to intersect the active area and arrange the active area on the floor surface of the gate trenches, a first junction area arranged on the center of the active area, and a second junction area arranged on ends of the active area; a first conductive line including a gate insulating film covering the lower side walls and floor surface of the gate trenches, a gate line embedding the lower part of the gate trenches while having an upper surface lower than the upper surface of the gate insulating film, and a capping line covering the gate line while being arranged on the upper part of the gate line to have an upper surface arranged at the same height with the gate insulating film; and a sealing line which embeds the upper part of ...

Semiconductor devices and fabricating methods thereof

Provided are semiconductor devices and fabricating methods thereof. The semiconductor device includes a field insulating layer formed in a substrate, an interlayer dielectric layer formed on the field insulating layer and including a trench exposing at least a portion of the field insulating layer, a deposition insulating layer formed in the trench to be disposed on the field insulating layer, a gate insulating layer formed in the trench to be disposed on the deposition insulating layer, and a metal gate formed in the trench on the gate insulating layer.

Method for making semiconductor device

This invention provides a method for making a semiconductor device, for easily forming a memory transistor and a high voltage resisting MOS transistor on a same semiconductor substrate without causing the performance characteristics of the memory transistor to vary. The process step for forming a tunnel insulation film of the memory transistor and the process step for forming a gate insulation film are separated from each other. More specifically, after forming an insulation film 9 to be a part of the tunnel insulation film and a silicon nitride film on the entire surface, the silicon nitride film 10 of the MOS transistor forming region is selectively removed using a photo resist layer 11. Thereafter, the MOS transistor forming region is selectively oxidated using the remaining silicon nitride film 10 as an oxidation resisting mask, to form a gate insulation film 12 of a desired thickness of MOS transistor.

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

The present invention relates to the technical field of semiconductor manufacturing. Disclosed is a method for manufacturing a semiconductor device, which solves the problem in the prior art that the silicon on the edge of an oxide layer in an LDMOS drift region is easily exposed and causes breakdown of an LDMOS device. In the technical solution provided by the embodiment of the present invention, a method for manufacturing a semiconductor device is provided, which comprises: providing a semiconductor substrate comprising an LDMOS region and a CMOS region; forming a sacrificial oxide layer on the semiconductor substrate; removing the sacrificial oxide layer; forming a masking layer on the semiconductor substrate after the sacrificial oxidation treatment; using the masking layer as a mask to form an LDMOS drift region, and forming a drift region oxide layer above the drift region; and removing the masking layer. The embodiment of the present invention is applicable to a BCD process and the ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Provided are: a semiconductor device, which has a BLDD structure having an increased withstand voltage, has a drain region that can sufficiently suppress hot carrier deterioration, and achieves high ESD resistance; and a method for manufacturing the semiconductor device. The semiconductor device that is provided with an MOS transistor is formed, said MOS transistor having a source region and a drain region that are formed in a semiconductor substrate, and a channel region formed between the source region and the drain region. The semiconductor device is configured such that the concentration of holes which contribute to electrical conduction by being discharged from a P-type impurity implanted in the channel region is lower on the side close to the drain region than that on the side close to the source region, the drain region includes a drift region having an N-type impurity implanted therein, and that, in the areas other than the area close to the semiconductor substrate surface, the ...

Semiconductor device

A die size is reduced in a semiconductor device having a gate electrode formed on a first gate insulation film and a second gate insulation film, source and drain regions (N− layers and N+ layers) formed adjacent to the gate electrode and a channel region, wherein the gate electrode, the channel region and the source and drain regions are hexagonal. Neighboring transistors are displaced from each other by a predetermined distance.

Stacked vertical devices

A semiconductor structure containing a plurality of stacked vertical field effect transistor (FETs) is provided. After forming a first vertical FET of a first conductivity type at a lower portion of a semiconductor fin, a second vertical FET of a second conductivity type is formed on top of the first vertical FET. The second conductivity type can be opposite to, or the same as, the first conductivity type. A source/drain region of the first vertical FET is electrically connected to a source/drain region of the second vertical FET by a conductive strip structure.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device includes a substrate including a fin-shaped active region that protrudes from the substrate; a gate insulating film covering a top surface and both side walls of the fin-shaped active region; a gate electrode on the top surface and the both side walls of the fin-shaped active region and covering the gate insulating film; one pair of insulating spacers on both side walls of the gate electrode; and a source region and a drain region on the substrate and respectively located on sides of the gate electrode. The source region and the drain region form a source/drain pair. The one pair of insulating spacers include protrusions that protrude from upper portions of the one pair of insulating spacers toward the gate electrode.

Integrated single-gated vertical field effect transistor (VFET) and independent double-gated VFET

A structure and method of making a semiconductor device includes a single-gated vertical field effect transistor (VFET), that has a first fin on a first bottom source/drain region, a gate of a first work force metal (WFM) surrounding the first fin, and a single gate contact connected to the first WFM. Also included is a double-gated VFET, that has a second fin on a second bottom source/drain region, a first gate of the first WFM disposed on a first side of the second fin, a second wider gate of a second WFM disposed on a second side of the second fin, a first gate contact contacting the first narrow gate, and a second gate contact contacting the second wider gate of the second WFM on the second side.

Threshold voltage adjustment for a gate-all-around semiconductor structure

A semiconductor structure includes a plurality of first semiconductor layers interleaved with a plurality of second semiconductor layers. The first and second semiconductor layers have different material compositions. A dummy gate stack is formed over an uppermost first semiconductor layer. A first etching process is performed to remove portions of the second semiconductor layer that are not disposed below the dummy gate stack, thereby forming a plurality of voids. The first etching process has an etching selectivity between the first semiconductor layer and the second semiconductor layer. Thereafter, a second etching process is performed to enlarge the voids.

Semiconductor device and method of manufacturing the same

In an LCD driver, in a high voltage resistant MISFET, end portions of a gate electrode run onto electric field relaxing insulation regions. Wires to become source wires or drain wires are formed on an interlayer insulation film of the first layer over the high voltage resistant MISFET. At this moment, when a distance from an interface between a semiconductor substrate and a gate insulation film to an upper portion of the gate electrode is defined as a, and a distance from the upper portion of the gate electrode to an upper portion of the interlayer insulation film on which the wires are formed is defined as b, a relation of a>b is established. In such a high voltage resistant MISFET structured in this manner, the wires are arranged so as not to be overlapped planarly with the gate electrode of the high voltage resistant MISFET.

Semiconductor device and manufacturing method thereof

A semiconductor device includes: an isolation region formed in a semiconductor substrate; an active region surrounded by the isolation region; and a first gate electrode formed on the isolation region and the active region and including a first region on the isolation region. The first region has a pattern width in a gate length direction larger than a pattern width of the first gate electrode on the active region. The first region includes a part having a film thickness different from a film thickness of the first gate electrode on the active region.

Semiconductor device and method for fabricating the same

A semiconductor device includes a resistor element covered by a silicon oxide film. In the semiconductor device, with respective gate electrodes of MIS transistors and impurity doped layers, i.e., non-silicide regions exposed, thermal treatment for activating an impurity and silicidization are performed. Thus, auto-doping of an impurity is suppressed, so that variations in a resistance value of a resistor are suppressed. Also, the gate electrodes of the MIS transistors and the like are exposed when thermal treatment for activating an impurity, and therefore breakdown of respective gate insulation films of the MIS transistors hardly occurs.

METHOD OF INTEGRATING HIGH VOLTAGE METAL OXIDE SEMICONDUCTOR DEVICES AND SUBMICRON METAL OXIDE SEMICONDUCTOR DEVICES

The present invention provides a method of integrating at least one high voltage metal oxide semiconductor device and at least one Submicron metal oxide semiconductor device on a substrate. The method comprises: providing the substrate, forming a plurality of shallow trenches having different depths on a surface of the substrate, and forming a plurality of silicon oxide layers filling up the shallow trenches, and a top of each of the silicon oxide layers being in the shape of a mushroom.

Semiconductor integrated circuit device having deposited layer for gate insulation

A method for manufacturing a semiconductor integrated circuit device including a first field effect transistor having a gate insulating film formed over a first element forming region of a main surface of a semiconductor substrate; and a second field effect transistor having a gate insulating film formed over a second element forming region of the main surface of the semiconductor substrate and made thinner than the gate insulating film of the first field effect transistor. The method comprises the steps of forming a thermally oxidized film over a first element forming region and a second element forming region of the main surface of the semiconductor substrate; forming a deposited film over the main surface of the semiconductor substrate including said thermally oxidized film; removing the deposited film and said thermally oxidized film from over the second element forming region; and forming a thermally oxidized film over the second element forming region to form a gate insulating film ...

Fin semiconductor device including dummy gate on isolation layer

A semiconductor device and a method of manufacturing a semiconductor device, the device including an active fin protruding from a substrate and extending in a first direction, a first device isolation region disposed at a sidewall of the active fin and extending in a second direction, the second direction crossing the first direction, a normal gate electrode crossing the active fin, a first dummy gate electrode having an undercut portion on the first device isolation region, the first dummy gate electrode extending in the second direction, and a first filler filling the undercut portion on the first device isolation region, wherein the undercut portion is disposed at a lower portion of the first dummy gate electrode.

Integrated Circuitry and Methods of Forming Transistors

Some embodiments include integrated circuits having first and second transistors. The first transistor is wider than the second transistor. The first and second transistors have first and second active regions, respectively. Dielectric features are associated with the first active region and break up the first active region. The second active region is not broken up to the same extent as the first active region. Some embodiments include methods of forming transistors. Active areas of first and second transistors are formed. The active area of the first transistor is wider than the active area of the second transistor. Dielectric features are formed in the active area of the first transistor. The active area of the first transistor is broken up to a different extent than the active area of the second transistor. The active areas of the first and second transistors are simultaneously doped.

Vertical FET with various gate lengths by an oxidation process

Techniques for forming VFETs with differing gate lengths Lg on the same wafer using a gas cluster ion beam (GCIB) process to produce fins of differing heights are provided. In one aspect, a method of forming fins having different heights includes: patterning the fins having a uniform height in a substrate, the fins including at least one first fin and at least one second fin; forming an oxide at a base of the at least one second fin using a low-temperature directional oxidation process (e.g., GCIB oxidation); and removing the oxide from the base of the at least one second fin to reveal the at least one first fin having a height HI and the at least one second fin having a height H2, wherein H2>H1. VFETs and methods for forming VFETs having different fin heights using this process are also provided.

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME

A semiconductor structure and a method for forming the same are provided. The method comprises following steps. A gate material film is formed on a substrate in a first device region and a second device region. The gate material film in the first device region is patterned to form a first patterned gate. A first spacer material film containing a nitride material is formed on the first patterned gate in the first device region and the gate material film in the second device region. The first spacer material film and the gate material film are patterned in the second device region to form a second patterned gate.

Semiconductor device and its production process

A semiconductor device comprising a semiconductor substrate, gate insulators formed on the substrate, and gate electrodes formed on the gate insulators, the gate insulators which are mainly composed of a material selected from titanium oxide, zirconium oxide and hafnium oxide, and in which compressive strain is produced and equipped with MOS transistors, can suppress leakage current flowing through the gate insulators and has high reliability.

Semiconductor device with two types of FET's having different gate lengths and its manufacture method

A gate electrode conductive film is formed on the surface of a semiconductor substrate. First and second gate mask patterns made of a first insulating material are formed on the gate electrode conductive film on first and second sections. Sidewall spacers are formed on the sidewalls of the first and second gate mask patterns, the sidewall spacer being made of a second insulating material having an etching resistance different from the first insulating material. The second section is covered with a mask pattern and the sidewall spacer on the sidewall of the first gate mask pattern is removed. The gate electrode conductive film is etched to leave first and second gate electrodes on the first and second sections.

Epitaxial structure of N-face AlGaN/GaN, active device, and method for fabricating the same with integration and polarity inversion

The present invention provides an epitaxial structure of N-face AlGaN/GaN, its active device, and the method for fabricating the same. The structure comprises a substrate, a C-doped buffer layer on the substrate, a C-doped i-GaN layer on the C-doped buffer layer, a i-AlyGaN buffer layer on the C-doped i-GaN layer, an i-GaN channel layer on the C-doped i-AlyGaN buffer layer, and an i-AlxGaN layer on the i-GaN channel layer, where x=0.1˜0.3 and y=0.05˜0.75. By using the p-GaN inverted trapezoidal gate or anode structure in device design, the 2DEG in the epitaxial structure of N-face AlGaN/GaN below the p-GaN inverted trapezoidal gate structure will be depleted. Then the 2DEG is located at the junction between the i-GaN channel layer and the i-AlyGaN layer, and thus fabricating p-GaN gate enhancement-mode (E-mode) AlGaN/GaN high electron mobility transistors (HEMTs).

FIELD EFFECT TRANSISTOR DEVICES HAVING THICK GATE DIELECTRIC LAYERS AND THIN GATE DIELECTRIC LAYERS

A semiconductor device includes a substrate, a fin arranged on the substrate, a first field effect transistor (FET) comprising a first gate stack disposed over the a portion of the fin, the first gate stack including a polysilicon layer and a silicide material disposed on the polysilicon layer, and an epitaxial material disposed over portions of the fin, the epitaxial material defining source and drain regions of the first FET, and a second effect transistor (FET) comprising a second gate stack disposed over the a portion of the fin, the second gate stack including a metal gate material layer, and an epitaxial material disposed over portions of the fin, the epitaxial material defining source and drain regions of the second FET.

Methods for Forming Gates in Gate-Last Processes and Gate Areas formed by the Same

Methods are provided for forming gates in gate-last processes. The methods may include performing chemical mechanical polishing (CMP) on an interlayer dielectric (ILD) that is on a plurality of dummy gates, each of the plurality of dummy gates including a gate mask in an upper portion thereof, and the CMP exposing the gate mask. The methods may also include removing the gate mask by etching the gate mask. The methods may further include performing CMP on the ILD.

Thick gate oxide for ldmos and demos

A process of forming an integrated circuit, including forming a dummy oxide layer for ion implanting low voltage transistors, replacing the dummy oxide in the low voltage transistor area with a thinner gate dielectric layer, and retaining the dummy oxide for a gate dielectric for a DEMOS or LDMOS transistor. A process of forming an integrated circuit, including forming a dummy oxide layer for ion implanting low voltage and intermediate voltage transistors, replacing the dummy oxide in the low voltage transistors with a thinner gate dielectric layer, replacing the dummy oxide in the intermediate voltage transistor with another gate dielectric layer, and retaining the dummy oxide for a gate dielectric for a DEMOS or LDMOS transistor.

Method for manufacturing a transistor

The invention provides a method for manufacturing a transistor which includes: providing a substrate having a plurality of transistors formed thereon, wherein each transistor includes a gate; forming a stressed layer and a first oxide layer on the transistors and on the substrate successively; forming a sacrificial layer on the first oxide layer; patterning the sacrificial layer to remove a part of the sacrificial layer which covers on the gates of the transistors; forming a second oxide layer on the residual sacrificial layer and on a part of the first oxide layer which is exposed after the part of the sacrificial layer is removed; performing a first planarization process to remove a part of the second oxide layer located on the gates of the transistors; performing a second planarization process to remove the residual second oxide layer; and performing a third planarization process to remove the stressed layer.

Semiconductor devices and methods of fabricating the same

A semiconductor device includes a substrate having first and second regions, a device isolation layer on the substrate defining an active region in each of the first and second regions, a gate pattern on the active region of each of the first and second regions, and a first dopant region and a second dopant region in each of the first and second regions of the substrate, the gate pattern in each of the first and second regions being between respective first and second dopant regions. At least one of upper surfaces of the first and second dopant regions in the second region is lower in level than an upper surface of the substrate under the gate pattern in the second region, the first and second dopant regions in the second region having an asymmetric recessed structure with respect to the gate pattern in the second region.

Localized carrier lifetime reduction

A semiconductor structure includes a substrate, a first power device and a second power device in the substrate, at least one isolation feature between the first and second power device, and a trapping feature adjoining the at least one isolation feature in the substrate.

Process for producing an integrated circuit

A process for producing an integrated circuit on the surface of a substrate, the process including: producing a first layer, including active zones and insulating zones, on the surface of the substrate; producing gate zones on the surface of the first layer, the gate zones each being surrounded by insulating spacers; producing source/drain electrodes; producing a dielectric layer between the insulating spacers, the dielectric layer having an upper surface level with the upper surfaces of the gate zones; partially etching each gate zone so as to lower the upper surface of a first part of each gate zone; and depositing an insulating dielectric layer on the first parts of the gate zones.

Semiconductor chip and fabricating method thereof

The present disclosure provides a fabricating method of a semiconductor chip which includes the following steps. First, a substrate is provided. The substrate defines a memory unit region and a peripheral logic region. Then, a first spacer is formed around a stack structure of the memory unit region. The first space includes a first silicon oxide layer and the first silicon oxide layer directly contacts with the stack structure. After that, a silicon nitride layer is formed on both the first spacer and the peripheral logic region. Finally, the additional silicon nitride layer on the first spacer is removed but portions of the additional silicon nitride layer around gate structures in the peripheral logic region are remained.

Mask free protection of work function material portions in wide replacement gate electrodes

In a replacement gate scheme, after formation of a gate dielectric layer, a work function material layer completely fills a narrow gate trench, while not filling a wide gate trench. A dielectric material layer is deposited and planarized over the work function material layer, and is subsequently recessed to form a dielectric material portion overlying a horizontal portion of the work function material layer within the wide gate trench. The work function material layer is recessed employing the dielectric material portion as a part of an etch mask to form work function material portions. A conductive material is deposited and planarized to form gate conductor portions, and a dielectric material is deposited and planarized to form gate cap dielectrics.

Transistor of semiconductor device and method for manufacturing the same

Provided are a transistor of a semiconductor device and a method for manufacturing the same. A gate induced drain leakage (GIDL) current is reduced by decreasing a work function at an upper portion of a gate electrode, and a threshold voltage of the transistor is maintained by maintaining a work function at a lower portion of the gate electrode at a high level, thereby reducing a leakage current of the transistor and reducing a read time and a write time of the semiconductor device. The transistor of the semiconductor device includes: a recess with a predetermined depth in a semiconductor substrate; a first gate electrode disposed within the recess; and a second gate electrode disposed on the first gate electrode into which ions of one or more of nitrogen (N), oxygen (O), arsenic (As), aluminum (Al), and hydrogen (H) are doped.

Integrated circuit and method for fabricating the same having a replacement gate structure

A method for fabricating an integrated circuit includes forming a first layer of a workfunction material in a first trench of a plurality of trench structures formed over a silicon substrate, the first trench having a first length and forming a second layer of a workfunction material in a second trench, the second trench having a second length that is longer than the first length. The method further includes depositing a low-resistance fill material onto the integrated circuit to fill any unfilled trenches with the low-resistance fill material and etching the low resistance fill material, the first layer, and the second layer to re-expose a portion of each trench of the plurality of trenches, while leaving a portion of each of the first layer, the second layer, and the low-resistance fill material in place. Still further, the method includes depositing a gate fill material into each re-exposed trench portion.

Device active channel length/width greater than channel length/width

A device including a drain, a channel, and a gate. The channel surrounds the drain and has a channel length to width ratio. The gate is situated over the channel to provide an active channel region that has an active channel region length to width ratio that is greater than the channel length to width ratio.

Semiconductor device and method for fabricating the same

A semiconductor device is formed by depositing a nitride material having a lower etch rate than an oxide material over or between buried gates when forming a metal contact at an end portion of a cell region, to prevent a lower substrate from being etched during an etching process forming a metal contact hole. The semiconductor device includes at least one buried gate formed in a device isolation film of a semiconductor substrate, an etch stop film formed over and between the buried gates, and a metal contact formed perpendicular to the buried gate in the etch stop film.

Method of manufacturing a semiconductor device

A method of manufacturing a semiconductor device having patterns with different widths. The method includes etching a sacrificial pattern using a protective pattern that has a greater width and remains during an etch process of a spacer layer. Since the sacrificial pattern that has a greater width and remains under the protective pattern having a greater width is used as a pad mask pattern, a separate process of forming a pad mask pattern may not be necessary. Therefore, a method of manufacturing a semiconductor device may be simplified.

METAL GATE STRUCTURE AND METHOD OF MAKING THE SAME

A metal gate structure includes a substrate including a dense region and an iso region. A first metal gate structure is disposed within the dense region, and a second metal gate structure is disposed within the iso region. The first metal gate structure includes a first trench disposed within the dense region, and a first metal layer disposed within the first trench. The second metal gate structure includes a second trench disposed within the iso region, and a second metal layer disposed within the second trench. The height of the second metal layer is greater than the height of the first metal layer. 1. A method of making a metal gate structure , the method being applied to a semi-finished product of a metal gate structure , the semi-finished product comprising a substrate , the substrate comprising a dense region and an iso region , a dielectric layer covering the dense region and the iso region , a first trench disposed in the dielectric layer within the dense region , a first gate dielectric layer , a first material layer , and a first metal layer disposed in the first trench , the first gate dielectric layer contacting the substrate , the first material layer disposed between the first metal layer and the first gate dielectric layer , wherein the first material layer is U shaped , and the first material layer has a first vertical sidewall , the method of making a metal gate structure comprising the following steps:Step (a): removing part of the first vertical sidewall of the first material layer;Step (b): after removing part of the first vertical sidewall, removing part of the first metal layer to make a top surface of the first metal layer aligned with a top surface of the first vertical sidewall; andStep (d): removing part of the first gate dielectric layer to make a top surface of the first gate dielectric layer aligned with the top surface of the first vertical sidewall.2. The method of making a metal gate structure of claim 1 , further comprising:Step (c): ...

VERTICAL TRANSISTOR WITH VARIABLE GATE LENGTH

A method of forming a vertical transistor includes forming a first pair of fins on a substrate; forming a second pair of fins on the substrate; forming a first trench in the substrate and interposed between each one of the first pair of fins; forming a second trench in the substrate and interposed between each one of the second pair of fins, wherein the second trench is deeper than the first trench; forming a first semiconductor structure interposed between each one of the first pair of fins, the first semiconductor structure having a first gate region interposed between a first source region and a first drain region; and forming a second semiconductor structure interposed between each one of the second pair of fins, the second semiconductor structure having a first gate region interposed between a second source region and a second drain region. 1. A method of forming a vertical transistor , the method comprising:forming a first pair of fins on a substrate;forming a second pair of fins on the substrate;forming a first trench in the substrate and interposed between each one of the first pair of fins;forming a second trench in the substrate and interposed between each one of the second pair of fins, wherein the second trench is deeper than the first trench;forming a doped source or a doped drain at a base of the first trench in direct contact with the substrate;forming a doped source or a doped drain at a base of the second trench in direct contact with the substrate, wherein the doped source or the doped drain at the base of the second trench is deeper than the doped source or the doped drain at the base of the first trench;forming a first semiconductor structure interposed between each one of the first pair of fins, the first semiconductor structure having a first gate region interposed between a first source region and a first drain region; andforming a second semiconductor structure interposed between each one of the second pair of fins, the second semiconductor ...

VERTICAL FET DEVICES WITH MULTIPLE CHANNEL LENGTHS

A semiconductor device comprises a first source/drain region arranged on a semiconductor substrate, a second source/drain region arranged on the semiconductor substrate, a bottom spacer arranged on the first source/drain region, and a bottom spacer arranged on the second source/drain region. A first gate stack having a first length is arranged on the first source/drain region. A second gate stack having a second length is arranged on the second source/drain region, the first length is shorter than the second length. A top spacer is arranged on the first gate stack, and a top spacer is arranged on the second gate stack. 1. A method for forming a semiconductor device , the method comprising:forming a first source/drain region and a second source/drain region on a semiconductor substrate;forming a first channel region and a second channel region on the substrate;forming bottom spacer on the first source/drain region and the second source/drain region;forming a first gate stack over the sidewalls of the first channel region and a second gate stack over the sidewalls of the second channel region;forming a gate conductor layer over exposed portions of the bottom spacer and around the first gate stack and the second gate stack;removing a portion of the gate conductor layer adjacent to the first gate stack;removing a portion of the gate conductor layer adjacent to the second gate stack such that the gate conductor has a first thickness adjacent to the first gate stack and a second thickness adjacent to the second gate stack, the first thickness is less than the second thickness;removing portions of the first gate stack and the second gate stack to expose portions of the first channel region and the second channel region;forming a sacrificial spacer over exposed portions of the first channel region and the second channel region;removing exposed portions of the gate conductor layer to expose portions of the bottom spacer;depositing a top spacer over the first gate stack and ...

DEVICE HAVING AN ACTIVE CHANNEL REGION

In some examples, a transistor includes a drain, a channel, and a gate. The channel surrounds the drain and has a channel length to width ratio. The gate is over the channel to provide an active channel region that has an active channel region length to width ratio that is greater than the channel length to width ratio. 1. A transistor comprising:a substrate;a drain in the substrate;a source in the substrate;a channel between the drain and the source, the channel surrounding the drain and having a channel length to width ratio; anda gate over the channel to provide an active channel region that has an active channel region length to width ratio that is greater than the channel length to width ratio.2. The transistor of claim 1 , wherein the gate comprises polysilicon.3. The transistor of claim 1 , wherein the channel comprises a plurality of channel regions claim 1 , and the gate comprises a plurality of gate regions over respective channel regions of the plurality of channel regions.4. The transistor of claim 3 , further comprising a gate lead electrically contacted to the gate regions claim 3 , a drain lead electrically contacted to the drain claim 3 , and a source lead electrically contacted to the source claim 3 , the gate lead claim 3 , the drain lead claim 3 , and the source lead formed by a first metal layer.5. The transistor of claim 1 , wherein the gate is disposed over a first portion of the channel claim 1 , and is not disposed over a second portion of the channel claim 1 , wherein the active channel region is provided by the first portion claim 1 , and the inactive channel region is provided by the second portion.6. The transistor of claim 5 , further comprising a dielectric layer between the gate and the first portion of the channel.7. The transistor of claim 5 , wherein a width of the active channel region is less than a width of the channel.8. The transistor of claim 7 , wherein the width of the active channel region is defined by a width of the gate. ...

Power Semiconductor Device Having Different Gate Crossings, and Method for Manufacturing Thereof

A power semiconductor device includes a semiconductor substrate having a first side. A plurality of active transistor cells is formed in an active area of the semiconductor substrate. Each of the plurality of active transistor cells includes a spicular trench which extends from the first side into the semiconductor substrate and has a field electrode. A gate electrode structure has a plurality of intersecting gate trenches running between the spicular trenches. The intersecting gate trenches form gate crossing regions of different shape when seen in a plan projection onto the first side of the power semiconductor device. 1. A power semiconductor device , comprising:a semiconductor substrate having a first side;a plurality of active transistor cells formed in an active area of the semiconductor substrate, each of the plurality of active transistor cells comprising a spicular trench which extends from the first side into the semiconductor substrate and comprises a field electrode; anda gate electrode structure comprising a plurality of intersecting gate trenches running between the spicular trenches, the intersecting gate trenches forming gate crossing regions of different shape when seen in a plan projection onto the first side of the power semiconductor device.2. The power semiconductor device of claim 1 , wherein the gate crossing regions comprise first gate crossing regions and second gate crossing regions claim 1 , wherein claim 1 , when seen in the plan projection onto the first side claim 1 , each of the first gate crossing regions defines a round transition between intersecting gate trenches with a first radius and each of the second gate crossing regions defines a sharp transition between intersecting gate trenches with a second radius claim 1 , and wherein the first radius is larger than the second radius.3. The power semiconductor device of claim 2 , wherein the first radius is at least twice as large as the second radius.4. The power semiconductor device ...

Integrated device having multiple transistors

An integrated device includes a semiconductor well formed in an epitaxial layer, and a guard ring formed in the epitaxial layer and surrounding the semiconductor well. The semiconductor well and the guard ring include a type of semiconductor different from that of the epitaxial layer. The integrated device also includes an insulating layer formed atop the guard ring, and multiple gate electrodes formed on a top surface of the insulating layer, overlapping the guard ring and surrounding the semiconductor well. The gate electrodes include a first gate electrode and a second gate electrode separated by a gap. An intersecting line between the top surface of the insulating layer and a side wall of the first gate electrode partially overlaps an area that is defined based on an intersecting line between the top surface of the insulating layer and a side wall of the second gate electrode above the guard ring.

PROCESS FOR INTEGRATED CIRCUIT FABRICATION INCLUDING A UNIFORM DEPTH TUNGSTEN RECESS TECHNIQUE

Dummy gates are removed from a pre-metal layer to produce a first opening (with a first length) and a second opening (with a second length longer than the first length). Work function metal for a metal gate electrode is provided in the first and second openings. Tungsten is deposited to fill the first opening and conformally line the second opening, thus leaving a third opening. The thickness of the tungsten layer substantially equals the length of the first opening. The third opening is filled with an insulating material. The tungsten is then recessed in both the first and second openings using a dry etch to substantially a same depth from a top surface of the pre-metal layer to complete the metal gate electrode. Openings left following the recess operation are then filled with a dielectric material forming a cap on the gate stack which includes the metal gate electrode. 1. An integrated circuit , comprising:a substrate including a first region and a second region;a pre-metal layer over the substrate, the pre-metal layer having a top planar surface and including a first gate stack opening having a first length and a second gate stack opening having a second length longer than the first length;a gate oxide region at a bottom of each of the first and second gate stack openings;a work force metal region in each of the first and second gate stack openings; andan overlying metal region in each of the first and second gate stack openings, wherein an upper surface of the overlying metal regions in both the first and second gate stack openings is recessed from said top planar surface by substantially a same distance.2. The circuit of claim 1 , further comprising an insulating gate cap on the overlying metal region in each of the first and second gate stack openings.3. The circuit of claim 2 , further comprising a metal contact extending through the insulating gate cap to make electrical contact with the overlying metal region in each of the first and second gate stack ...

Methods for producing integrated circuits using long and short regions and integrated circuits produced from such methods

Integrated circuits and methods for producing the same are provided. In an exemplary embodiment, a method for producing an integrated circuit includes forming a work function layer overlying a substrate and a plurality of dielectric columns. The dielectric columns and the substrate define a short region having a short region width and a long region having a long region width greater than the short region width. The work function layer is recessed in the long region to a long region work function height that is between a dielectric column top surface and a substrate top surface. The work function layer is also recessed in the short region to a short region work function height that is between the dielectric column top surface and the substrate top surface. Recessing the work function layer in the long and short regions is conducted in the absence of lithography techniques.

Semiconductor device and a method for fabricating the same

In a method of manufacturing a semiconductor device, a dummy gate structure is formed over a substrate. A first insulating layer is formed over the dummy gate structure. The dummy gate structure is removed so as to form a gate space in the first insulating layer. A first conductive layer is formed in the gate space so as to form a reduced gate space. The reduced gate space is filled with a second conductive layer made of a different material from the first conductive layer. The filled first conductive layer and the second conductive layer are recessed so as to form a first gate recess. A third conductive layer is formed over the first conductive layer and the second conductive layer in the first gate recess. After recessing the filled first conductive layer and the second conductive layer, the second conductive layer protrudes from the first conductive layer.

DEVICES AND METHODS FOR LAYOUT-DEPENDENT VOLTAGE HANDLING IMPROVEMENT IN SWITCH STACKS

Devices and methods for layout-dependent voltage handling improvement in switch stacks. In some embodiments, a switching device can include a first terminal and a second terminal, a radio-frequency signal path implemented between the first terminal and the second terminal, and a plurality of switching elements connected in series to form a stack between the second terminal and ground. The stack can have an orientation relative to the radio-frequency signal path, and the switching elements can have a non-uniform distribution of a first parameter based in part on the orientation of the stack. 1providing a semiconductor substrate;forming a plurality of field-effect transistors (FETs) on the semiconductor substrate such that the field-effect transistors have a non-uniform distribution of a parameter based at least in part on an orientation of the field-effect transistors relative to a radio-frequency signal path; andconnecting the field-effect transistors to form a stack, such that the non-uniform distribution results in the stack having a first voltage handling capacity that is greater than a second voltage handling capacity corresponding to a similar stack having a substantially uniform distribution of the parameter.. A method for fabricating a radio-frequency (RF) switching device, the method comprising: This application is a continuation of U.S. patent application Ser. No. 16/234,099, filed on Dec. 27, 2018, entitled “DEVICES AND METHODS FOR LAYOUT-DEPENDENT VOLTAGE HANDLING IMPROVEMENT IN SWITCH STACKS,” which claims the benefit of U.S. Provisional Application No. 62/612,594, filed on Dec. 31, 2017, entitled “DEVICES AND METHODS FOR LAYOUT-DEPENDENT VOLTAGE HANDLING IMPROVEMENT IN SWITCH STACKS,” each of which is incorporated herein by reference in its entirety.The present disclosure generally relates to improved radio-frequency (RF) switching devices.In some radio-frequency applications, switches are commonly arranged in a stack configuration to facilitate ...

High threshold voltage fet with the same fin height as regular threshold voltage vertical fet

A technique relates to a semiconductor device. A first vertical fin is formed with a first gate stack and a second vertical fin with a second gate stack. The second vertical fin has a hardmask on top. The first vertical fin is adjacent to a first bottom source or drain (S/D) region and the second vertical fin is adjacent to a second bottom S/D region. The first gate stack is reduced to a first gate length and the second gate stack to a second gate length, the second gate length being greater than the first gate length because of the hardmask. The hardmask is removed. A first top S/D region is adjacent to the first vertical fin and a second top S/D region is adjacent to the second vertical fin.

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes a substrate including a circuit region and a scribe lane region, an active fin protruding from the substrate in the circuit region, a first gate structure extending over the active fin in the circuit region, and a second gate structure formed in the scribe lane region.

SEMICONDUCTOR DEVICE INCLUDING A VERTICAL GATE-ALL-AROUND TRANSISTOR AND A PLANAR TRANSISTOR

A semiconductor device includes a first transistor and a second transistor. Each of the first and second transistors includes a channel. The channel of the first transistor extends in a substantially vertical direction. The channel of the second transistor extends in a substantially horizontal direction. A method for fabricating the semiconductor device is also disclosed.

Vertical structure for semiconductor device

The present disclosure describes a method to form a fin field effect transistor (finFET) and a nano-sheet transistor on a substrate. The method can include forming first and second vertical structures over a substrate, where each of the first and the second vertical structures can include a buffer region and a first channel layer formed over the buffer region. The method can further include disposing a masking layer over the first channel layer of the first and second vertical structures, removing a portion of the first vertical structure to form a first recess, forming a second channel layer in the first recess, forming a second recess in the second channel layer, and disposing an insulating layer in the second recess.

GATE-END STRUCTURE ENGINEERING FOR SEMICONDUCTOR APPLICATIONS

Semiconductor device structures with reduced gate end width formed at gate structures and methods for manufacturing the same are provided. In one example, a semiconductor device structure includes a plurality of gate structures formed over a plurality of fin structures, the gate structures formed substantially orthogonal to the fin structures, wherein the plurality of gate structures includes a first gate structure having a first gate end width and a second gate structure having a second gate end width, wherein the second gate end width is shorter than the first gate end width 1. A semiconductor device structure , comprising: a first gate structure having a first gate end and a first gate end width, wherein the outermost fin structure is a closest fin structure to the first gate end, wherein the first gate end width is measured from the outermost fin structure to the first gate end; and', 'a second gate structure having second gate end and a second gate end width, wherein the outermost fin structure is a closest fin structure to the second gate end, wherein the second gate end width is shorter than the first gate end width, wherein the second gate end width is measured from the outermost fin structure to the second gate end., 'a plurality of gate structures formed over a plurality of fin structures, the gate structures formed substantially orthogonal to the fin structures, wherein the plurality of fin structures comprises an outermost fin structure, wherein the plurality of gate structures includes2. The semiconductor device structure of claim 1 , wherein the second gate end width is between about 20% and 60% shorter than the first gate end width.3. The semiconductor device structure of claim 1 , wherein the first and the second gate end widths are defined between an end of the first and second gate structures claim 1 , respectively claim 1 , and a sidewall of the outermost fin structure disposed closest to the end of the first and second gate structures.4. The ...

SEMICONDUCTOR DEVICE

A semiconductor device including a substrate includes a first region and a second region and first and second transistors in the first and second regions, respectively. The first transistor includes a first gate insulating layer on the substrate, a first lower TiN layer on and in contact with the first gate insulating layer, a first etch-stop layer on the first lower TiN layer and a first upper gate electrode on the first etch-stop layer. The second transistor includes a second gate insulating layer on the substrate, a second lower TiN layer on and in contact with the second gate insulating layer, a second etch-stop layer on the second lower TiN layer and a second upper gate electrode on the second etch-stop layer. A thickness of the first lower TiN layer is less than a thickness of the second lower TiN layer. 1. A semiconductor device , comprising:a substrate including first through fourth regions;an interlayer insulating film on the substrate, the interlaying insulating film including first through fourth trenches in the first through fourth regions, respectively, andfirst through fourth transistors of the same conductivity type located in the first through fourth trenches, respectively, in the first through fourth regions,wherein each of the first through fourth transistor includes at least one insulating layer on a bottom and sides of a respective trench of the first through fourth trenches, a lower conductive layer on the insulating layer conforming to the bottom and sides of the trench, an etch-stop layer conforming to a bottom and sides of the lower conductive layer, a work function control layer conforming to a bottom and at least a portion of sides of the etch-stop layer, an insertion layer conforming to a bottom and sides of the work function control layer, and a filling layer filling a remaining space of the trench,wherein, in at least one of the first through fourth transistors, the work function control layer is chamfered.2. The semiconductor device as ...

SEMICONDUCTOR DEVICE INCLUDING VERTICAL FIELD EFFECT TRANSISTORS HAVING DIFFERENT GATE LENGTHS

A semiconductor device including a semiconductor substrate having a recessed top portion and a non-recessed top portion, a first fin protruding upward from a non-recessed top portion with a first thickness, a second fin protruding upward from the recessed top portion with a second thickness greater than the first thickness, a first gate structure on the non-recessed top portion and surrounding the first fin to a first height from the non-recessed top portion, and a second gate structure on the recessed top portion and surrounding the second fin to a second height different from the first height from the recessed top portion may be provided. 1. A semiconductor device including at least two vertical field effect transistors (VFETs) having different gate lengths , the semiconductor device comprising:a semiconductor substrate including a top surface and a bottom surface, the top surface including a first top surface portion at a first height with respect to the bottom surface of the semiconductor substrate and a second top surface portion at a second height with respect to the bottom surface of the semiconductor substrate, the first height being different from the second height;a first fin protruding from the first top surface portion of the semiconductor substrate;a second fin protruding from the second top surface portion of the semiconductor substrate, a top of the first fin and a top of the second fin being at a same level;a first gate structure on the first top surface portion of the semiconductor substrate, the first gate structure including a first gate insulating layer and a first gate conductive layer on the first gate insulating layer, the first gate structure surrounding the first fin to a first thickness from the top surface of the semiconductor substrate; anda second gate structure on the second top surface portion of the semiconductor substrate, the second gate structure including a second gate insulating layer and a second gate conductive layer on the ...

SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME

Semiconductor device having less defects in a gate insulating film and improved reliability and methods of forming the semiconductor devices are provided. The semiconductor devices may include a gate insulating film on a substrate and a gate electrode structure on the gate insulating film. The gate electrode structure may include a lower conductive film, a silicon oxide film, and an upper conductive film sequentially stacked on the gate insulating film. The lower conductive film may include a barrier metal layer. 1. A method of fabricating a semiconductor device , the method comprising:forming a gate insulating layer on a substrate;sequentially forming a lower gate electrode and a silicon layer on the gate insulating layer;oxidizing the silicon layer to form a silicon oxide layer;performing a heat treatment process while the silicon oxide layer is exposed; andforming an upper gate electrode on the silicon oxide layer after performing the heat treatment process.2. The method of claim 1 , wherein forming the lower gate electrode comprises forming a barrier metal layer.3. The method of claim 2 , wherein forming the barrier metal layer and forming the silicon layer are performed without exposing the substrate to oxygen.4. The method of claim 2 , wherein the silicon layer is formed to directly contact the barrier metal layer.5. The method of claim 1 , wherein oxidizing the silicon layer comprises oxidizing an upper portion of the silicon layer claim 1 , and a lower portion of the silicon layer remains between the silicon oxide layer and the lower gate electrode after oxidizing the silicon layer.6. The method of claim 1 , further comprising:removing the upper gate electrode using the silicon oxide layer as an etch stopping layer.7. A method of fabricating a semiconductor device claim 1 , the method comprising:forming a first gate insulating layer on a first region of a substrate and forming a second gate insulating layer on a second region of the substrate;sequentially ...

METHOD FOR FABRICATING A FINFET IN A LARGE SCALE INTEGRATED CIRCUIT

Systems and methods of fabricating a FinFET in large scale integrated circuit are disclosed. One illustrative method relates to a dummy gate process, wherein the fin structure is only formed in the gate electrode region by performing a photolithography process and an etching of a first dummy gate on a flat STI surface using chemical mechanical polishing, forming drain and source regions, depositing a medium dielectric layer, polishing the medium dielectric layer till the top of the first dummy gate is exposed through the chemical mechanical polishing process again, removing the dummy gate material via a dry etching and a wet etching, and continuously etching the STI dielectric layer with the hard mask formed by the medium dielectric layer, thereafter performing the deposition of real gate dielectric and gate electrode material to complete the device structure. 1. A method for fabricating a FinFET , comprising the following steps:1) forming a STI isolation layer on a bulk silicon substrate, performing a well implantation and channel ion implantation to an active region and performing an annealing;2) exposing a silicon surface of the active region, depositing a sacrificial gate oxide layer, forming a dummy gate on the sacrificial gate oxide layer, wherein the top of the dummy gate is covered by a composite hard mask of silicon oxide and silicon nitride;3) removing the sacrificial gate oxide layer covered on the drain and source regions, depositing a thin film of silicon nitride as an implantation mask for the drain and source regions to perform a drain and source LDD implantation and a Halo implantation, and performing a rapid flash annealing of milliseconds;4) depositing a silicon nitride layer, performing a photolithgraphy process, performing an anisotropic dry etching to the silicon nitride layer with the photoresist as a mask, to form silicon nitride sidewalls of the dummy gate and expose the silicon mesa of the drain and source regions, and then performing an ...

SEMICONDUCTOR DEVICE

A semiconductor device includes a plurality of active patterns protruding from a substrate, a gate structure intersecting the plurality of active patterns, a plurality of source/drain regions respectively on the plurality of active patterns at opposite sides of the gate structure, and source/drain contacts intersecting the plurality of active patterns, each of the source/drain contacts connected in common to the source/drain regions thereunder, each of the plurality of source/drain regions including a first portion in contact with a top surface of the active pattern thereunder, the first portion having a width substantially increasing as a distance from the substrate increases, and a second portion extending from the first portion, the second portion having a width substantially decreasing as a distance from the substrate increases, bottom surfaces of the source/drain contacts being lower than an interface between the first and second portions. 135-. (canceled)36. (canceled)37. A semiconductor device , comprising:a first active pattern and a second active pattern, the first and second active patterns protruding from a substrate;a first source/drain region and a second source/drain region on the first and second active patterns, respectively; anda first source/drain contact connected in common to the first and second source/drain regions,wherein the first source/drain region includes:a first portion in contact with a top surface of the first active pattern thereunder, the first portion having a width substantially increasing as a distance from the substrate increases; anda second portion extending from the first portion, the second portion having a width substantially decreasing as a distance from the substrate increases,wherein a bottom surface of the first source/drain contact on a center of the first active pattern is lower than an interface between the first and second portions, andwherein an air gap is defined between the first and second active patterns.38. The ...

INTEGRATED CIRCUITS WITH RECESSED GATE ELECTRODES

Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit. 1. An integrated circuit structure , comprising:a gate electrode over a semiconductor channel region, the gate electrode comprising a bulk material having a bottom surface, a first side, a second side, and a top surface, and the gate electrode comprising a workfunction material along the bottom surface and partially along the first and second sides of the bulk material, the workfunction material having a top surface below the top surface of the bulk material;a first dielectric spacer adjacent to a first side of the gate electrode;a second dielectric spacer adjacent to a second side of the gate electrode, the second side opposite the first side; anda high-k dielectric layer between the gate electrode and the semiconductor channel region, the high-k dielectric layer laterally between the first dielectric spacer and the portion of the workfunction material partially along the first side of the bulk material, and the high-k dielectric layer laterally between the second dielectric spacer and the portion of the workfunction material partially along the second side of the bulk material, wherein the high-k dielectric layer has a top surface above the top surface of the bulk material, the top surface of the high-k dielectric layer below a top surface of the first and second dielectric ...

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a substrate, a first nanowire spaced apart from a first region of the substrate, a first gate electrode surrounding a periphery of the first nanowire, a second nanowire spaced apart from a second region of the substrate and extending in a first direction and having a first width in a second direction intersecting the first direction, a supporting pattern contacting the second nanowire and positioned under the second nanowire, and a second gate electrode extending in the second direction and surrounding the second nanowire and the supporting pattern. 1. A method for fabricating a semiconductor device , comprising:providing a substrate including a first region and a second region,forming a first fin-type structure on the first region and a second fin-type structure on the second region, wherein the first fin-type structure and the second fin-type structure respectively include a first semiconductor pattern and a second semiconductor pattern alternately stacked on the substrate,forming a blocking film covering the first region and exposing the second region,performing an ion implantation on the second region to lower an etch selectivity of the first semiconductor pattern on the second region,forming a first dummy gate electrode intersecting the first fin-type pattern and a second dummy gate electrode intersecting the second fin-type pattern,forming a first spacer on a side wall of the first dummy gate electrode and a second spacer on a side wall of the second dummy gate electrode, andetching the first semiconductor pattern, wherein the first semiconductor pattern on the first region is completely removed, and the first semiconductor pattern on the second region remains to form a supporting pattern.2. The method for fabricating the semiconductor device of claim 1 , wherein the etching the first semiconductor pattern includes:etching a portion of the second ...

Semiconductor device and method of forming same

A semiconductor device and a method of forming the device are disclosed. In the semiconductor device, a shielded gate trench field effect transistor (FET) is formed in a cell region, and a super barrier rectifier (SBR) is formed in a non-cell region. In the SBR, a second dielectric layer has an upper dielectric layer and a lower dielectric layer, which are joined to each other smoothly by virtue of a beak-like portion. This avoids the presence of any sharp corner between the upper and lower dielectric layers and effectively mitigates the problem of an excessively small thickness of the upper dielectric layer at a bottom portion thereof, which tends to cause current leakage.

Semiconductor device and method for fabricating the same

The present application discloses a method for fabricating a semiconductor device with a flat surface. The method for fabricating a semiconductor device including providing a substrate, forming a gate structure on the substrate, and forming a plurality of word lines having top surfaces at a same vertical level as a top surface of the gate structure.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD

A semiconductor device including a semiconductor substrate; a trench formed in a front surface of the semiconductor substrate; a gate conducting portion formed within the gate trench; and a first region formed adjacent to the trench in the front surface of the semiconductor substrate and having a higher impurity concentration than the semiconductor substrate. A shoulder portion is provided on a side wall of the gate trench between the top end of the gate conducting portion and the front surface of the semiconductor substrate and has an average slope, relative to a depth direction of the semiconductor substrate, that is greater than a slope of the side wall of the gate trench at a position opposite the top end of the gate conducting portion, and a portion of the first region that contacts the gate trench is formed as a deepest portion thereof 1. A semiconductor device including a first semiconductor region with a second conductivity type formed on a side of a front surface of a semiconductor substrate with a first conductivity type and a second semiconductor region with the first conductivity type selectively formed on closer to a portion of the side of the front surface than the first semiconductor region , the semiconductor device comprising:a plurality of trenches extending in a predetermined extension direction in the side of the front surface of the semiconductor substrate and reaching below the first semiconductor region;a conducting portion filled within the plurality of trenches;an interlayer insulating film covering the front surface of the front surface of the semiconductor substrate with a prescribed pattern;a first electrode connecting to the semiconductor substrate via a region exposed from the interlayer insulating film in a mesa region sandwiched between the trenches, whereinin a cross section perpendicular to the extension direction, a first trench portion and a second trench portion are provided, the first trench portion having a predetermined ...

SEMICONDUCTOR DEVICES AND METHOD OF MANUFACTURING THE SAME

A semiconductor device includes a first transistor in a first region of a substrate and a second transistor in a second region of the substrate. The first transistor includes multiple first semiconductor patterns; a first gate electrode; a first gate dielectric layer; a first source/drain region; and an inner-insulating spacer. The second transistor includes multiple second semiconductor patterns; a second gate electrode; a second gate dielectric layer; and a second source/drain region. The second gate dielectric layer extends between the second gate electrode and the second source/drain region and is in contact with the second source/drain region. The first source/drain region is not in contact with the first gate dielectric layer. 1. A semiconductor device , comprising:a first transistor in a first region of a substrate and a second transistor in a second region of the substrate,wherein the first transistor comprises:a plurality of first channel regions spaced apart from each other in a first direction perpendicular to a top surface of the substrate;a first gate electrode surrounding the plurality of first channel regions;a first external insulating spacer on upper sidewalls of the first gate electrode,a first source/drain region connected to an edge of the plurality of first channel regions, the first source/drain region contacting the first external insulating spacer, the first source/drain region having a top surface at a level higher than a top surface of an uppermost first channel region; anda plurality of inner-insulating spacers between the first gate electrode and the first source/drain region and between two adjacent first channel regions of the plurality of first channel regions, the plurality of inner-insulating spacers having a curved sidewall facing the first gate electrode, andthe second transistor comprises:a plurality of second channel regions spaced apart from each other in the first direction;a second gate electrode surrounding the plurality of ...

Semiconductor device

A semiconductor device includes an active region defined by a device isolation layer and including first and second sections or regions, a gate electrode extending in a first direction across the active region over a channel between the first region and the second region and including at least one first gate tab protruding in a second direction toward the first region, and first and second contact plugs. The first gate tab covers and extends along a boundary between the active region and the device isolation layer. The first contact plug is disposed over the first region, the second contact plug is disposed over the second region, and the second contact plug has an effective width, as measured in the first direction, greater than that of the first contact plug.

INTEGRATED NANOWIRE & NANORIBBON PATTERNING IN TRANSISTOR MANUFACTURE

Fabrication of narrow and wide structures based on lithographic patterning of exclusively narrow mask structures. Multi-patterning may be employed to define narrow mask structures. Wide mask structures may be derived through a process-based merging of multiple narrow mask structures. The merge may include depositing a cap layer over narrow structures, filling in minimum spaces. The cap layer may be removed leaving residual cap material only within minimum spaces. Narrow and wide structures may be etched into an underlayer based on a summation of the narrow mask structures and residual cap material. A plug pattern may further mask portions of the cap layer not completely filling space between adjacent mask structures. The underlayer may then be etched based on a summation of the narrow mask structures, plug pattern, and residual cap material. Such methods may be utilized to integrate nanoribbon transistors with nanowire transistors in an integrated circuit (IC). 1. An integrated circuit (IC) structure , comprising:a first plurality of transistors, wherein individual ones of the first plurality comprise a semiconductor material of a first lateral width and are separated by a first spacing; anda second plurality of transistors, wherein individual ones of the second plurality comprise a semiconductor material of a second lateral width that is more than twice the first lateral width by less than the first spacing.2. The IC structure of claim 1 , wherein the second lateral width is equal to a first integer multiple of the first lateral width summed with a second integer multiple of a predetermined distance that is less than claim 1 , or equal to claim 1 , the first spacing.3. The IC structure of claim 2 , wherein the predetermined distance is less than the first spacing.4. The IC structure of claim 2 , wherein the second plurality of transistors comprises:a first transistor including semiconductor material having a second lateral width that is equal to twice the first ...

INTEGRATED CIRCUITS WITH SELECTIVE GATE ELECTRODE RECESS

Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit. 1. (canceled)2. An integrated circuit structure , comprising: a first gate dielectric over a first fin;', 'a first gate electrode over the first gate dielectric, the first gate electrode having a first work function layer and a first bulk material, the first gate electrode having a first gate length;', 'a first source or drain structure adjacent a first side of the first gate electrode; and', 'a second source or drain structure adjacent a second side of the first gate electrode, the second side opposite the first side;, 'a first MOS transistor, comprisinga first conductive contact structure in direct contact with the first source or drain structure, wherein the first bulk material of the first gate electrode has an uppermost surface below an uppermost surface of the first conductive contact structure; and a second gate dielectric over a second fin;', 'a second gate electrode over the second gate dielectric, the second gate electrode having a second work function layer and a second bulk material, the second gate electrode having a second gate length, the second gate length greater than the first gate length;', 'a third source or drain structure adjacent a first side of the second gate electrode; and', 'a fourth source or drain structure adjacent a second side of the second gate ...

Threshold Voltage Adjustment for a Gate-All-Around Semiconductor Structure

A semiconductor structure includes a plurality of first semiconductor layers interleaved with a plurality of second semiconductor layers. The first and second semiconductor layers have different material compositions. A dummy gate stack is formed over an uppermost first semiconductor layer. A first etching process is performed to remove portions of the second semiconductor layer that are not disposed below the dummy gate stack, thereby forming a plurality of voids. The first etching process has an etching selectivity between the first semiconductor layer and the second semiconductor layer. Thereafter, a second etching process is performed to enlarge the voids. 1. A device , comprising:a first nanostructure and a second nanostructure each having an elongated shape, wherein the first nanostructure and the second nanostructure each contain a semiconductive material;a first gate located at least above or below the first nanostructure in a cross-sectional view; anda second gate located at least above or below the second nanostructure in the cross-sectional view, wherein the first gate and the second gate have different sizes.2. The device of claim 1 , wherein the first gate at least partially wraps around the first nanostructure claim 1 , and wherein the second gate at least partially wraps around the second nanostructure.3. The device of claim 1 , further including:a third nanostructure located above or below the first nanostructure in the cross-sectional view; anda fourth nanostructure located above or below the second nanostructure in the cross-sectional view.4. The device of claim 1 , wherein:the first nanostructure and the second nanostructure each extend in a first direction; andthe first gate and the second gate have different sizes in the first direction.5. The device of claim 4 , wherein:the first gate corresponds to a first transistor with a first threshold voltage;the second gate corresponds to a second transistor with a first threshold voltage that is greater ...

GATE STACK OPTIMIZATION FOR WIDE AND NARROW NANOSHEET TRANSISTOR DEVICES

A method of forming a nanosheet device is provided. The method includes forming a plurality of narrow nanosheets on a first region of a substrate, and forming a plurality of wide nanosheets on a second region of the substrate. The method further includes forming an interfacial layer on the plurality of narrow nanosheets and the plurality of wide nanosheets. The method further includes depositing a gate dielectric layer on the plurality of narrow nanosheets and the plurality of wide nanosheets. The method further includes depositing a dummy gate layer on the gate dielectric layer on the plurality of narrow nanosheets and the plurality of wide nanosheets. The method further includes forming a dummy cover layer on the dummy gate layer on the plurality of narrow nanosheets and the plurality of wide nanosheets. 1. A method of forming a nanosheet device , comprising:forming a plurality of narrow nanosheets on a first region of a substrate;forming a plurality of wide nanosheets on a second region of the substrate;forming an interfacial layer on the plurality of narrow nanosheets and the plurality of wide nanosheets;depositing a gate dielectric layer on the plurality of narrow nanosheets and the plurality of wide nanosheets;depositing a dummy gate layer on the gate dielectric layer on the plurality of narrow nanosheets and the plurality of wide nanosheets; andforming a dummy cover layer on the dummy gate layer on the plurality of narrow nanosheets and the plurality of wide nanosheets.2. The method of claim 1 , wherein adjacent narrow nanosheets of the plurality of narrow nanosheets on the first region of a substrate and the adjacent wide nanosheets of the plurality of wide nanosheets on the second region of a substrate are separated by a distance claim 1 , D claim 1 , in a range of about 5.5 nm to about 17.5 nm.3. The method of claim 1 , wherein the dummy cover layer is formed on the dummy gate layer by a non-confoiiiial deposition.4. The method of claim 3 , wherein foaming ...

FINFET SEMICONDUCTOR DEVICE

A semiconductor device is disclosed that includes a plurality of fins on a substrate. A long channel gate is disposed over a first portion of the plurality of fins. A gate contact is provided having an extended portion that extends into an active area from a gate contact base outside the active area. 1. A semiconductor device , comprising:a plurality of fins on a substrate;a long channel gate disposed over a first portion of the plurality of fins; anda gate contact comprising a gate contact base and an extended portion that extends into an active area from the gate contact base outside the active area.2. The semiconductor device of claim 1 , wherein the extended portion has a smaller length than the gate contact base.3. The semiconductor device of claim 1 , wherein the extended portion has generally a same length as the gate contact base.4. The semiconductor device of claim 1 , wherein the extended portion extends over at least one of the plurality of fins.5. The semiconductor device of claim 1 , wherein the extended portion extends over the plurality of fins.6. The semiconductor device of claim 1 , wherein the long channel gate is disposed over the first portion of the plurality of fins on a first portion of the substrate and the active area is a first active area of the first portion of the plurality of fins claim 1 , the semiconductor device further comprising:a short channel gate disposed over a second portion of the plurality of fins on a second portion of the substrate; anda second gate contact outside a second active area of the second portion of the plurality of fins.7. The semiconductor device of claim 6 , further comprising:another long channel gate disposed over a third portion of the plurality of fins on a third portion of the substrate; anda third gate contact comprising another gate contact base and another extended portion that extends into a third active area of the third portion of the plurality of fins from the another gate contact base outside the ...

Metal Gate Structure

A method comprises depositing a dielectric layer on sidewalls and a bottom of a trench of a gate structure, depositing a metal layer on the dielectric layer, depositing a protection layer on the metal layer, wherein an upper portion of a sidewall portion of the protection layer is thinner than a lower portion of the sidewall portion of the protection layer and etching back the metal wherein an upper portion of a first metal sidewall of the metal layer is thinner than a lower portion of the first metal sidewall and an upper portion of a second metal sidewall of the metal layer is thinner than a lower portion of the second metal sidewall. 1. A method comprising:forming a first gate trench and an second gate trench, wherein a width of the second gate trench is greater than a width of the first gate trench;depositing a first dielectric layer in the first gate trench and a second dielectric layer in the second gate trench;depositing a first metal layer on the first dielectric layer and a second metal layer on the second dielectric layer; 'an upper portion of a sidewall portion of the second protection layer is thinner than a lower portion of the sidewall portion of the second protection layer; and', 'depositing a first protection layer on the first metal layer and a second protection layer on the second metal layer, wherein 'an upper portion of a sidewall of the second metal layer is thinner than a lower portion of the sidewall of the second metal layer.', 'performing an etch-back process on the first protection layer and the second protection layer to expose sidewalls of the first metal layer and sidewalls of the second metal layer, wherein2. The method of claim 1 , further comprising:removing a bottom portion of the first protection layer and a bottom portion of the second protection layer to form a first step and a second step in the first gate trench, and a third step and a fourth step in the second gate trench.3. The method of claim 2 , wherein:the first step is ...

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

A semiconductor device includes a first gate electrode structure having a first gate insulating layer on a substrate and a first gate electrode on the first gate insulating layer. A first spacer structure includes a first spacer and a second spacer on side walls of the first gate electrode structure. The first spacer is disposed between the second spacer and the first gate electrode. A source/drain region is disposed on opposite sides of the first gate electrode structure. The first gate electrode includes a lower part of the first gate electrode, an upper part of the first gate electrode disposed on the lower part of the first gate electrode, and the first spacer is disposed on the side wall of the upper pan of the first gate electrode and is not disposed on the side wall of the lower part of the first gate electrode. 1. A semiconductor device , comprising:a first gate electrode structure which includes a first gate insulating layer disposed on a substrate and a first gate electrode disposed on the first gate insulating layer;a first spacer structure including a first spacer and a second spacer each disposed on side walls of the first gate electrode structure, the first spacer being disposed between the second spacer and the first gate electrode; anda source/drain region disposed on opposite sides of the first gate electrode structure,wherein the first gate electrode includes a lower part of the first gate electrode, an upper part of the first gate electrode disposed on the lower part of the first gate electrode, andwherein the first spacer is disposed on a side wall of the upper part of the first gate electrode and is omitted from a side wall of the lower part of the first gate electrode.2. The semiconductor device of claim 1 , wherein the second spacer extends along the side wall of the upper part of the first gate electrode and the side wall of the lower part of the first gate electrode.3. The semiconductor device of claim 1 , wherein a width of the lower part ...

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

A semiconductor device including a substrate including first and second regions along a first direction, and a third region between the first region and the second region, an active pattern extending in the first direction, on the substrate, and first to third gate electrodes spaced apart from each other and extending in a second direction, on the active pattern, the active pattern of the first region including first semiconductor patterns spaced apart from each other and penetrating the first gate electrode, the active pattern of the second region including second semiconductor patterns spaced apart from each other and penetrating the second gate electrode, the active pattern of the third region including a transition pattern protruding from the substrate and intersecting the third gate electrode and including a sacrificial pattern and a third semiconductor pattern alternately stacked on the third region and including different materials from each other. 1. A semiconductor device comprising:a substrate including a first region and a second region arranged along a first direction, and a third region between the first region and the second region;an active pattern extending in the first direction, on the substrate; andfirst to third gate electrodes spaced apart from each other and each extending in a second direction intersecting the first direction, on the active pattern,wherein the active pattern of the first region includes a plurality of first semiconductor patterns spaced apart from each other and penetrating the first gate electrode,the active pattern of the second region includes a plurality of second semiconductor patterns spaced apart from each other and penetrating the second gate electrode,the active pattern of the third region includes a transition pattern protruding from the substrate and intersecting the third gate electrode, andthe transition pattern includes a sacrificial pattern and a third semiconductor pattern alternately stacked on the third ...

Vertical FET with Various Gate Lengths by an Oxidation Process

Techniques for forming VFETs with differing gate lengths Lg on the same wafer using a gas cluster ion beam (GCIB) process to produce fins of differing heights are provided. In one aspect, a method of forming fins having different heights includes: patterning the fins having a uniform height in a substrate, the fins including at least one first fin and at least one second fin; forming an oxide at a base of the at least one second fin using a low-temperature directional oxidation process (e.g., GCIB oxidation); and removing the oxide from the base of the at least one second fin to reveal the at least one first fin having a height H and the at least one second fin having a height H, wherein H>H. VFETs and methods for forming VFETs having different fin heights using this process are also provided. 1. A method of forming a vertical field effect transistor (VFET) device , the method comprising the steps of:patterning fins having a uniform height in a substrate, the fins comprising at least one first fin and at least one second fin;{'b': 1', '2', '2', '1, 'selectively recessing the at least one second fin using a low-temperature directional oxidation process such that the at least one first fin has a height H′ and the at least one second fin has a height H′, wherein H′>H′;'}forming bottom source and drains at a base of the fins;forming bottom spacers on the bottom source and drains;{'b': 1', '2', '2', '1, 'forming gates above the bottom spacers alongside the fins, wherein the gates alongside the at least one first fin have a first gate length Lg′, wherein the gates alongside the at least one second fin have a second gate length Lg′, and wherein Lg′>Lg′;'}forming top spacers above the gates at tops of the fins; andforming top source and drains above the top spacers.2. The method of claim 1 , wherein the low-temperature directional oxidation process comprises a gas cluster ion beam (GCIB) oxidation process.3. The method of claim 2 , wherein the GCIB oxidation process is ...

Semiconductor Device and Method

Nanowire devices and fin devices are formed in a first region and a second region of a substrate. To form the devices, alternating layers of a first material and a second material are formed, inner spacers are formed adjacent to the layers of the first material, and then the layers of the first material are removed to form nanowires without removing the layers of the first material within the second region. Gate structures of gate dielectrics and gate electrodes are formed within the first region and the second region in order to form the nanowire devices in the first region and the fin devices in the second region.

Vertical Transistors with Different Gate Lengths

Techniques for forming VFETs with differing gate lengths are provided. In one aspect, a method for forming a VFET device includes: patterning fins in a substrate, wherein at least one of the fins includes a vertical fin channel of a FET and at least another one of the fins includes a vertical fin channel of a FET forming a bottom source and drain; forming bottom spacers on the bottom source and drain; forming gates surrounding the vertical fin channel of the FET and FET forming top spacers on the gate; and forming top source and drains at the tops of the fins by varying a positioning of the top source and drains relative to at least one of the vertical fin channel of the FET and the FET such that the FETFET have an effective gate length LgateLgate wherein LgateLgate A VFET device is also provided. 1. A method for forming a vertical field-effect-transistor (VFET) device , comprising the steps of:depositing a doped epitaxial layer onto a substrate;{'b': 1', '2, 'patterning fins in the doped epitaxial layer and the substrate using fin hardmasks, wherein at least one of the fins comprises a vertical fin channel of a first FET device (FET) and at least another one of the fins comprises a vertical fin channel of a second FET device (FET);'}forming a bottom source and drain in the substrate beneath the fins;forming bottom spacers on the bottom source and drain;{'b': 1', '2, 'forming gates surrounding the vertical fin channel of the FET and the vertical fin channel of the FET;'}forming top spacers on the gates; and{'b': 1', '2', '1', '1', '2', '2', '1', '2, 'forming top source and drains at the tops of the fins, wherein the step of forming the top source and drains comprises varying a positioning of the top source and drains relative to at least one of the vertical fin channel of the FET and the vertical fin channel of the FET such that the FET has an effective gate length Lgate and the FET has an effective gate length Lgate, and wherein Lgate>Lgate.'}2. The method of claim ...

Vertical Transistors with Different Gate Lengths

Techniques for forming VFETs with differing gate lengths are provided. In one aspect, a method for forming a VFET device includes: patterning fins in a substrate, wherein at least one of the fins includes a vertical fin channel of a FET1 and at least another one of the fins includes a vertical fin channel of a FET2; forming a bottom source and drain; forming bottom spacers on the bottom source and drain; forming gates surrounding the vertical fin channel of the FET1 and FET2; forming top spacers on the gate; and forming top source and drains at the tops of the fins by varying a positioning of the top source and drains relative to at least one of the vertical fin channel of the FET1 and the FET2 such that the FET1/FET2 have an effective gate length Lgate1/Lgate2, wherein Lgate1>Lgate2. A VFET device is also provided. 1. A vertical field-effect-transistor (VFET) device , comprising:fins patterned in a substrate, wherein at least one of the fins comprises a vertical fin channel of a first FET device (FET1) and at least another one of the fins comprises a vertical fin channel of a second FET device (FET2), and wherein the fins extend partway through the substrate;a bottom source and drain in the substrate beneath the fins;bottom spacers on the bottom source and drain;gates surrounding the vertical fin channel of the FET1 and the vertical fin channel of the FET2;top spacers on the gates; andtop source and drains at the tops of the fins, wherein a positioning of the top source and drains relative to the vertical fin channel of the FET1 and the vertical fin channel of the FET2 is different such that the FET1 has an effective gate length Lgate1 and the FET2 has an effective gate length Lgate2, and wherein Lgate1>Lgate2.2. The VFET device of claim 1 , wherein the vertical fin channel of the FET1 and the vertical fin channel of the FET2 are undoped.3. The VFET device of claim 1 , wherein the gates surrounding the vertical fin channel of the FET1 and the vertical fin channel ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

In a method of manufacturing a semiconductor device, a fin structure protruding from a first isolation insulating layer is formed. A second isolation insulating layer made of different material than the first isolation insulating layer is formed so that a first upper portion of the fin structure is exposed. A dummy gate structure is formed over the exposed first upper portion of the first fin structure. The second isolation insulating layer is etched by using the dummy gate structure as an etching mask. The dummy gate structure is removed so that a gate space is formed. The second isolation insulating layer is etched in the gate space so that a second upper portion of the fin structure is exposed from the first isolation insulating layer. A gate dielectric layer and a gate electrode layer are formed over the exposed second portion of the fin structure. 1. A semiconductor device , comprising:a fin structure protruding from an isolation insulating layer provided over a substrate;a gate dielectric layer disposed over a channel region of the fin structure;a gate electrode layer disposed over the gate dielectric layer; andsidewall spacers disposed over opposing side faces of the gate electrode layer, wherein:the sidewall spacers includes lower sidewall spacers and upper sidewall spacers vertically disposed on the lower sidewall spacers, andthe lower sidewall spacers are made of a different insulating material than the isolation insulating layer.2. The semiconductor device of claim 1 , wherein the lower sidewall spacers are made of a different insulating material than the upper sidewall spacer layers.3. The semiconductor device of claim 2 , wherein the isolation insulating layer is made of a different insulating material than the upper sidewall spacer layers.4. The semiconductor device of claim 1 , wherein the lower sidewall spacers are made of at least one of SiCO and SiCON.5. The semiconductor device of claim 1 , wherein the gate dielectric layer is disposed between the ...

Gate structures for semiconductor devices with a conductive etch stop layer

One illustrative gate structure of a transistor device disclosed herein includes a high-k gate insulation layer and a work function metal layer positioned on the high-k gate insulation layer. The device further includes a first bulk metal layer positioned on the work function metal layer. The device further includes a second bulk metal layer. The first and second bulk metal layers have upper surfaces that are at substantially the same height level, and the first and second bulk metal layers are made of substantially the same material. The device further includes a conductive etch stop layer between the first and second bulk metal layers.

SEMICONDUCTOR DEVICE

A semiconductor device includes a plurality of channels, source/drain layers, and a gate structure. The channels are sequentially stacked on a substrate and are spaced apart from each other in a first direction perpendicular to a top surface of the substrate. The source/drain layers are connected to the channels and are at opposite sides of the channels in a second direction parallel to the top surface of the substrate. The gate structure encloses the channels. The channels have different lengths in the second direction and different thicknesses in the first direction. 1. A semiconductor device , comprising:first, second and third semiconductor patterns sequentially stacked on a substrate and spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, each of the first, second and third semiconductor patterns extending in a second direction parallel to the upper surface of the substrate;a gate structure extending on the substrate in a third direction parallel to the upper surface of the substrate and crossing the second direction and at least partially enclosing each of the first, second and third semiconductor patterns, the gate structure including first, second and third portions sequentially stacked in the first direction, the first portion disposed between the upper surface of the substrate and the first semiconductor pattern, the second portion disposed between the first semiconductor pattern and the second semiconductor pattern, and the third portion disposed between the second semiconductor pattern and the third semiconductor pattern; andan epitaxial layer at a side of the gate structure in the second direction, the epitaxial layer being connected to the first, second and third semiconductor patterns,wherein first, second and third channels are formed in the first, second and third semiconductor patterns, respectively, andwherein a minimum length in the second direction of the first channel is greater than a minimum ...

METHODS AND SYSTEMS OF REALIZING MULTIPLE GATE LENGTH IN TRANSISTOR

A method of fabricating a semiconductor structure includes forming a plurality of Fin structures, doping first dopants at both sides of a first Fin structure of the Fin structures, and providing a first thermal diffusion operation to the semiconductor structure. The method also includes doping second dopants at both sides of a second Fin structure of the Fin structures, and providing a second thermal diffusion operation to the semiconductor structure. A first gate length for the first Fin structure is formed using the first and the second thermal diffusion operations, and a second gate length for the second Fin structure using the second thermal diffusion operation. The first dopants are of the same type or a different type. 19-. (canceled)10. A method of fabricating a semiconductor structure , comprising:forming a plurality of Fin structures;doping first dopants at both sides of a first Fin structure of the plurality of Fin structures;providing a first thermal diffusion operation to the semiconductor structure;doping second dopants at both sides of a second Fin structure of the plurality of Fin structures; andproviding a second thermal diffusion operation to the semiconductor structure,wherein a first gate length for the first Fin structure is formed using the first and the second thermal diffusion operations, and wherein a second gate length for the second Fin structure is formed using the second thermal diffusion operation, wherein the first gate length and the second gate length are different, wherein the first dopants and the second dopants are the same type or are different type dopants.11. The method of fabricating the semiconductor structure of claim 10 , wherein providing the first thermal diffusion operation comprises applying the semiconductor structure to a first temperature that reaches or is above a temperature threshold for a thermal diffusion operation of the semiconductor structure.12. The method of fabricating the semiconductor structure of claim ...

Dishing prevention structure embedded in a gate electrode

Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes a semiconductor substrate. A gate dielectric is disposed over the semiconductor substrate. A first source/drain region and a second source/drain region are disposed in the semiconductor substrate and on opposite sides of the gate dielectric. A gate electrode is disposed over the gate dielectric. A first dishing prevention structure is embedded in the gate electrode, where a perimeter of the first dishing prevention structure is disposed within a perimeter of the gate electrode.

Fabrication of Long Gate Devices

Semiconductor devices and methods of forming the same are provided. An example method includes providing a workpiece including a first dummy gate stack and a second dummy gate stack in a first area of the workpiece, a third dummy gate stack and a fourth dummy gate stack in a second area of the workpiece, a hard mask layer over each of the first dummy gate stack, the second dummy gate stack, the third dummy gate stack, and the fourth dummy gate stack. The method further includes depositing a photoresist (PR) layer over the workpiece to form a first PR layer portion over the first area and a second PR layer portion over the second area; and selectively forming a first opening through the second PR layer portion over the third dummy gate stack and a second opening through the second PR layer portion over the fourth dummy gate stack.

High Voltage Device

Semiconductor devices and methods are provided. A semiconductor device according to the present disclosure includes a substrate having a first area and a second area, a plurality of fin structures extending along a direction over the first area and the second area of the substrate, a first transistor and a second transistor in the first area, a first isolation structure disposed between the first transistor and the second transistor, a first isolation structure disposed between the first transistor and the second transistor, a third transistor and a fourth transistor in the second area, and a second isolation structure disposed between the third transistor and the fourth transistor. The first isolation structure includes a first width along the direction and the second isolation structure includes a second width along the direction. The second width is greater than the first width.

Semiconductor device and method of fabricating the same

A semiconductor device includes a substrate that includes peripheral and logic cell regions, a device isolation layer that defines a first active pattern on the peripheral region and second and third active patterns on the logic cell region, and first to third transistors on the first to third active patterns. Each of the first to third transistors includes a gate electrode, a gate spacer, a source pattern and a drain pattern. The second active pattern includes a semiconductor pattern that overlaps the gate electrode. At least a portion of a top surface of the device isolation layer is higher than a top surface of the second and third active patterns. A profile of the top surface of the device isolation layer includes two or more convex portions between the second and third active patterns.

CHEMICAL MECHANICAL POLISHING METHOD FOR FIRST INTERLAYER DIELECTRIC LAYER

A method for manufacturing a semiconductor device includes providing a semiconductor substrate comprising a low-density region and a high-density region, forming a first gate structure in the low-density region and a second gate structure in the high-density region, form an etch stop layer on the first and second gate structures, and forming an interlayer dielectric layer on the etch stop layer and on the semiconductor substrate. The method further includes performing a first chemical mechanical polishing (CMP) process on the etch stop layer to expose a surface of a portion of the etch stop layer disposed on the first gate structure, performing a second CMP process on the etch stop layer to expose a surface of a portion of the etch stop layer disposed on the second gate structure, and performing a third CMP process to completely remove the etch stop layer. 1. A method for manufacturing a semiconductor device , the method comprising:providing a semiconductor substrate comprising a low-density region and a high-density region;forming a first gate structure in the low-density region and a second gate structure in the high-density region;form an etch stop layer on the first and second gate structures;forming an interlayer dielectric layer on the etch stop layer and on the semiconductor substrate;performing a first chemical mechanical polishing (CMP) process on the etch stop layer to expose a surface of a portion of the etch stop layer disposed on the first gate structure;performing a second CMP process on the etch stop layer to expose a surface of a portion of the etch stop layer disposed on the second gate structure; andperforming a third CMP process to completely remove the etch stop layer.2. The method of claim 1 , wherein the etch stop layer comprises silicon nitride and the interlayer dielectric layer comprises an oxide.3. The method of claim 2 , wherein the first and second gate structures each comprise polysilicon.4. The method of claim 3 , wherein the first CMP ...

Metal gate structure and manufacturing method thereof

A semiconductor structure includes a substrate including a first active region, a second active region and an isolation disposed between the first active region and the second active region; a plurality of gates disposed over the substrate and including a first gate extended over the first active region, the isolation and the second active region, and a second gate over the first active region and the second active region; and an inter-level dielectric (ILD) disposed over the substrate and surrounding the plurality of gates, wherein the second gate is configured not to conduct current flow and includes a first section disposed over the first active region and a second section disposed over the second active region, a portion of the ILD is disposed between the first section and the second section.

Vertical channel field-effect transistor (fet) process compatible long channel transistors

Embodiments of the present invention provide methods and systems for co-integrating a short-channel vertical transistor and a long-channel transistor. One method may include: from a starting substrate, forming a wide fin, wherein the wide fin comprises a wide active region; depositing a recess mask over a top surface of the starting substrate; recessing a long channel based on the deposited recess mask; depositing a gate electrode and a gate material, to form a gate structure; and forming SD contacts in an SD region of the long-channel transistor.

FINFET PCM ACCESS TRANSISTOR HAVING GATE-WRAPPED SOURCE AND DRAIN REGIONS

Embodiments are directed to a method of forming portions of a fin-type field effect transistor (FinFET) device. The method includes forming at least one source region having multiple sides, forming at least one drain region having multiple sides, forming at least one channel region having multiple sides, forming at least one gate region around the multiple sides of the at least one channel region and forming the at least one gate region around the multiple sides of the at least one drain region. 1. A method of forming portions of a fin-type effect transistor (FinFET) device , the method comprising:forming at least one source region having multiple sides;forming at least one drain region having multiple sides;forming at least one channel region having multiple sides; and around the multiple sides of the at least one channel region; and', 'wrapped around the multiple sides of the at least one drain region., 'forming at least one gate region2. The method of further comprising forming a common source substrate.3. The method of further comprising coupling the common source substrate to the at least one source region.4. The method of claim 1 , wherein forming the at least one drain region comprises forming a drain contact region coupled to a drain pillar region.5. The method of further comprising doping the drain contact region and the drain pillar region.6. The method of claim 5 , wherein doping the drain contact region comprises doping the drain contact region to include a level of doping equal to approximately one dopant atom per 10 claim 5 ,000 atoms.7. The method of claim 5 , wherein doping the drain pillar region comprises doping the drain pillar region to include a level of doping equal to approximately one dopant atom per 100 claim 5 ,000 claim 5 ,000 atoms.8. A method of forming portions of a fin-type effect transistor (FinFET) device claim 5 , the method comprising:forming at least one source region having multiple sides;forming at least one drain region having ...

Asymmetric Gate Pitch

The present disclosure describes an exemplary asymmetric CPP layout for a semiconductor structure with a different gate pitch over the source and the drain regions to mitigate gate-to-gate parasitic capacitances over the drain region, thus improving cutoff frequency. For example, the semiconductor structure can include a fin on a substrate. The semiconductor structure can also include first and second gate structures formed on the fin and separated by a first space. The semiconductor structure can also include a third gate structure formed on the fin between the first and the second gate structures. The third gate structure can be separated from the first gate structure by a second pitch and separated from the second gate structure by a third pitch that is greater than the second pitch. The semiconductor structure further includes a source region formed between the first and third gate structures, and a drain region formed between the third and the second gate structures.

METHOD AND STRUCTURE FOR FORMING VERTICAL TRANSISTORS WITH VARIOUS GATE LENGTHS

Various methods and structures for fabricating a plurality of vertical fin FETs on the same semiconductor substrate in which a first gate length of a first gate in a first vertical fin FET is less than a second gate length of a second gate in a second vertical fin FET. A difference in gate lengths between different vertical fin FETs can be precisely fabricated by using atomic layer silicon germanium epitaxy. Gate length offset is formed at a bottom source/drain junction region of each vertical fin FET transistor, which allows downstream processing for all vertical fin FET transistors to be the same. 1. A semiconductor structure comprising:a first vertical fin field-effect transistor formed on a semiconductor substrate, the first vertical fin field-effect transistor comprising a first vertical fin, a first bottom source/drain junction layer disposed on the semiconductor substrate and a first gate disposed on the first bottom source/drain junction layer, the first gate having a first gate length; anda second vertical fin field-effect transistor formed on the semiconductor substrate, the second vertical fin field-effect transistor comprising a second vertical fin, a second bottom source/drain junction layer disposed on the semiconductor substrate and a second gate disposed on the second bottom source/drain junction layer, the second gate having a second gate length that is greater than the first gate length, the first vertical fin including a staircase feature inside the first bottom source/drain junction layer and the second vertical fin does not include a staircase feature inside the second bottom source/drain junction layer.2. The semiconductor structure of claim 1 , wherein the staircase feature includes a step from a vertically lower portion of the first vertical fin to a vertically higher portion of the first vertical fin.3. The semiconductor structure of claim 2 , wherein the vertically lower portion of the first vertical fin in the staircase feature has a first ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A method includes forming in sequence a metallic capping layer and a dummy gate electrode layer over a semiconductor substrate; patterning the metallic capping layer and the dummy gate electrode layer to form a first stacked structure including a first portion of the metallic capping layer and a first portion of the dummy gate electrode layer; forming a plurality of first gate spacers on opposite sides of the first stacked structure; removing the first portion of the dummy gate electrode layer to expose the first portion of the metallic capping layer; and forming a first work function metal layer on the first portion of the metallic capping layer. 1. A method , comprising:forming in sequence a metallic capping layer and a dummy gate electrode layer over a semiconductor substrate;patterning the metallic capping layer and the dummy gate electrode layer to form a first stacked structure comprising a first portion of the metallic capping layer and a first portion of the dummy gate electrode layer;forming a plurality of first gate spacers on opposite sides of the first stacked structure;removing the first portion of the dummy gate electrode layer to expose the first portion of the metallic capping layer; andforming a first work function metal layer on the first portion of the metallic capping layer.2. The method of claim 1 , further comprising:forming a gate dielectric layer over the semiconductor substrate prior to forming the metallic capping layer.3. The method of claim 2 , wherein patterning the metallic capping layer and the dummy gate electrode layer is performed such that the gate dielectric layer is patterned.4. The method of claim 1 , wherein forming the first work function metal layer comprises a deposition process claim 1 , and a deposition rate of the first work function metal layer on the metallic capping layer is faster than a deposition rate of the first work function metal layer on the first gate spacers.5. The method of claim 1 , wherein patterning the ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A method of forming a nonvolatile memory device includes forming first, second, and third gate structures, with the second and third gate structures including first and second spacer structures formed on a sidewall of the second gate structure and sidewalls of the third gate structure. Impurity regions are formed through ion implantation and the first spacer structure shields the second and third gate structures during ion implantation. The second spacer structure defines resulting impurity regions. 118.-. (canceled)19. A method of forming a semiconductor device , the method comprising:forming a gate structure layer on a substrate;partially etching the gate structure layer to form a plurality of first gate structures on a region of the substrate through a first patterning process, wherein each of the plurality of first gate structures has a first width;forming a capping insulation layer covering an upper portion of the plurality of first gate structures and the gate structure layer;partially etching the capping insulation layer and the gate structure layer to form a plurality of second gate structures having sidewalls and a plurality of first capping insulation patterns through a second patterning process, wherein each of the plurality of second gate structures has a second width greater than the first width, and sidewalls of neighboring ones of the plurality of second gate structures opposing each other;forming a first spacer structure on sidewalls of each of the plurality of second gate structures and each of the plurality of first capping insulations, the first spacer structure including a first spacer and a second spacer; andforming an impurity region at an upper portion of the substrate between the plurality of first gate structures.20. The method of claim 19 , wherein forming the first spacer structure includes:forming a first spacer layer on a sidewall of each of the plurality of second gate structures and a sidewall and an upper surface of each of the ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device includes a substrate having an active region, a gate structure on the active region, the gate structure including a gate dielectric layer and a gate electrode layer, and the gate electrode layer having a rounded upper corner, and gate spacer layers on side surfaces of the gate structure, the gate spacer layers having an upper surface at a lower height level than an upper surface of the gate electrode layer. 1. A semiconductor device , comprising:a substrate having an active region;a gate structure on the active region, the gate structure including a gate dielectric layer and a gate electrode layer, and the gate electrode layer having a rounded upper corner; andgate spacer layers on side surfaces of the gate structure, the gate spacer layers having upper surfaces at a lower height level than an upper surface of the gate electrode layer.2. The semiconductor device as claimed in claim 1 , wherein the gate electrode layer extends in a first direction to intersect the active region claim 1 , the gate electrode layer having rounded corners on both sides in a second direction perpendicular to the first direction.3. The semiconductor device as claimed in claim 1 , wherein the upper surface of the gate electrode layer has an upwardly convex shape.4. The semiconductor device as claimed in claim 1 , further comprising a gate capping layer covering upper surfaces of the gate electrode layer and the gate spacer layers.5. The semiconductor device as claimed in claim 4 , wherein external side surfaces of the gate spacer layers that are not in contact with the gate structure are coplanar with side surfaces of the gate capping layer.6. The semiconductor device as claimed in claim 1 , wherein the upper surfaces of the gate spacer layers have downwardly convex shapes.7. The semiconductor device as claimed in claim 1 , wherein the gate dielectric layer covers a lower surface and a side surface of the gate electrode layer claim 1 , the gate dielectric layer having ...

METAL GATE STRUCTURE TO REDUCE TRANSISTOR GATE RESISTANCE

A method for manufacturing a semiconductor device includes forming a channel layer on a semiconductor substrate and forming at least two spacers on the channel layer. A first portion of a gate metal layer is formed between the spacers, and a dielectric layer is conformally deposited on the spacers and the first portion of the gate metal layer. In the method, part of the dielectric layer is directionally removed from surfaces which are parallel to an upper surface of the substrate. A second portion of the gate metal layer is formed between remaining portions of the dielectric layer and on the first portion of the gate metal layer, and a cap layer is deposited on the second portion of the gate metal layer. A lateral width the second portion of the gate metal layer is less than a lateral width of the first portion of the gate metal layer. 1. A semiconductor device , comprising:a channel layer disposed on a semiconductor substrate; the gate metal layer comprises a second portion disposed on a first portion; and', 'a lateral width the second portion of the gate metal layer is less than a lateral width of the first portion of the gate metal layer;, 'a gate metal layer disposed on the channel layer, whereina plurality of spacer layers disposed on sides of the gate metal layer;a dielectric layer on each of the plurality of spacer layers and positioned between the second portion of the gate metal layer and a spacer layer of the plurality of spacer layers; anda cap layer disposed on the second portion of the gate metal layer.2. The semiconductor device according to claim 1 , further comprising:a plurality of source/drain regions adjacent the channel layer; andan inter-layer dielectric (ILD) layer disposed on the source/drain regions and adjacent each of the plurality of spacer layers.3. The semiconductor device according to claim 2 , further comprising at least one source/drain contact disposed through the ILD layer.4. The semiconductor device according to claim 2 , wherein ...

SEMICONDUCTOR DEVICE

A semiconductor device includes a semiconductor part between first and second electrodes, first and second control electrodes between the semiconductor part and the second electrode. The semiconductor part includes a first region and a second region around the first region. The semiconductor part includes first and third layers of a first conductivity type and second layers of a second conductivity type. The second layers are provided between the first layer and the second electrode. A second layer faces the first control electrode in the second region. Another second layer faces the second control electrode in the second region. A third layer is provided between the second layer and the second electrode. Another third layer is provided between another second layer and the second electrode. The second layer includes a second conductivity type impurity with a concentration lower than that of a second conductivity type impurity in another second layer. 1. A semiconductor device comprising:a semiconductor part;a first electrode provided on the semiconductor part;a second electrode, the semiconductor part being provided between the first electrode and the second electrode; anda plurality of control electrodes provided between the semiconductor part and the second electrode, the control electrodes each being electrically isolated from the semiconductor part by a first insulating film, the control electrodes each being electrically isolated from the second electrode by a second insulating film,the second electrode including a center portion and a peripheral portion, the peripheral portion being provided at an outer side of the center portion in a direction along a surface of the semiconductor part,the semiconductor part including a first region and a second region, the first region being provided between the first electrode and the center portion of the second electrode, the second region being provided between the first electrode and the peripheral portion of the second ...

FABRICATING METHOD OF TRANSISTORS WITHOUT DISHING OCCURRED DURING CMP PROCESS

A fabricating method of transistors includes providing a substrate with numerous transistors thereon. Each of the transistors includes a gate structure. A gap is disposed between gate structures adjacent to each other. Later, a protective layer and a first dielectric layer are formed in sequence to cover the substrate and the transistors and to fill in the gap. Next, numerous buffering particles are formed to contact the first dielectric layer. The buffering particles do not contact each other. Subsequently, a second dielectric layer is formed to cover the buffering particles. After that, a first planarization process is performed to remove part of the first dielectric layer, part of the second dielectric layer and buffering particles by taking the protective layer as a stop layer, wherein a removing rate of the second dielectric layer is greater than a removing rate of the buffering particles during the first planarization process. 1. A fabricating method of transistors , comprising:providing a substrate with a plurality of transistors thereon, wherein each of the plurality of transistors comprises a gate structure, and a gap is disposed between gate structures which are adjacent to each other;forming a protective layer and a first dielectric layer in sequence to cover the substrate and the plurality of transistors and to fill in the gap;forming a plurality of buffering particles contacting the first dielectric layer, wherein the plurality of buffering particles do not contact each other;forming a second dielectric layer to cover the plurality of buffering particles;performing a first planarization process to remove part of the first dielectric layer, part of the second dielectric layer and the plurality of buffering particles by taking the protective layer as a stop layer, wherein a removing rate of the second dielectric layer is greater than a removing rate of the plurality of buffering particles during the first planarization process.2. The fabricating method of ...

Semiconductor device and electronic system including the same

A semiconductor device includes: a cell area including a cell substrate, a memory cell array, and a first bonding metal pad on the memory cell array, the memory cell array including a plurality of word lines stacked on the cell substrate and a plurality of bit lines on the plurality of word lines; and a peripheral circuit area having the cell area stacked thereon and including a peripheral circuit substrate, a plurality of circuits on the peripheral circuit substrate, and a second bonding metal pad bonded to the first bonding metal pad, wherein the plurality of circuits include: a plurality of planar channel transistors respectively including a channel along a top surface of the peripheral circuit substrate; and at least one recess channel transistor including a channel along a surface of a recess trench arranged in the peripheral circuit.

Method for preparing semiconductor device with t-shaped buried gate electrode

The present disclosure provides a method for preparing a semiconductor device with a T-shaped buried gate electrode. The method includes forming an isolation structure in a semiconductor substrate to define an active region, and forming a doped region in the active region. The method also includes etching the semiconductor substrate to form a first trench and a second trench. The first trench has a first portion extending across the doped region and a second portion extending away from the first portion, and the second trench has a third portion extending across the doped region and a fourth portion extending away from the third portion. The method further includes forming a first gate electrode in the first trench and a second gate electrode in the second trench.

Semiconductor device structure with metal gate stack

A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a metal gate stack over the substrate. The metal gate stack has a gate dielectric layer and a work function layer over the gate dielectric layer. The semiconductor device structure also includes a spacer structure over a sidewall of the metal gate stack. A topmost surface of the gate dielectric layer is lower than a topmost surface of the spacer structure. The topmost surface of the gate dielectric layer is closer to the topmost surface of the spacer structure than a topmost surface of the work function layer.

Native pmos device with low threshold voltage and high drive current and method of fabricating the same

A native p-type metal oxide semiconductor (PMOS) device that exhibits a low threshold voltage and a high drive current over a varying range of short channel lengths and a method for fabricating the same is discussed in the present disclosure. The source and drain regions of the native PMOS device, each include a strained region, a heavily doped raised region, and a lightly doped region. The gate region includes a stacked layer of a gate oxide having a high-k dielectric material, a metal, and a contact metal. The high drive current of the native PMOS device is primarily influenced by the increased carrier mobility due to the strained regions, the lower drain resistance due to the raised regions, and the higher gate capacitance due to the high-k gate oxide of the native PMOS device.

Fin Critical Dimension Loading Optimization

Integrated circuit devices having optimized fin critical dimension loading are disclosed herein. An exemplary integrated circuit device includes a core region that includes a first multi-fin structure and an input/output region that includes a second multi-fin structure. The first multi-fin structure has a first width and the second multi-fin structure has a second width. The first width is greater than the second width. In some implementations, the first multi-fin structure has a first fin spacing and the second multi-fin structure has a second fin spacing. The first fin spacing is less than the second fin spacing. In some implementations, a first adjacent fin pitch of the first multi-fin structure is greater than or equal to three times a minimum fin pitch and a second adjacent fin pitch of the second multi-fin structure is less than or equal to two times the minimum fin pitch.

Colored self-aligned subtractive patterning

A computing device including tight pitch features and a method of fabricating a computing device using colored spacer formation is disclosed. The computing device includes a memory and an integrated circuit coupled to the memory. The integrated circuit includes a first multitude of features above a substrate. The integrated circuit die includes a second multitude of features above the substrate. The first multitude of features and the second multitude of features are same features disposed in a first direction. The first multitude of features interleave with the second multitude of features. The first multitude of features has a first size and the second multitude of features has a second size.

Method of Manufacture of a FinFET Device

A semiconductor device and method of manufacture are provided in which an the physical characteristics of a dielectric material are modified in order to provide additional benefits to surrounding structures during further processing. The modification may be performed by implanting ions into the dielectric material to form a modified region. Once the ions have been implanted, further processing relies upon the modified structure of the modified region instead of the original structure. 1. A method of manufacturing a semiconductor device , the method comprising:forming a fin protruding from a substrate;depositing a first dummy gate stack over the fin;depositing an interlayer dielectric around the first dummy gate stack;planarizing the first dummy gate stack and the interlayer dielectric;after planarizing the first dummy gate stack, implanting ions into the interlayer dielectric to form an implanted region;after implanting ions into the interlayer dielectric, removing the first dummy gate stack using an etching process, wherein the etching process reduces a height of the interlayer dielectric; andforming a replacement gate stack in place of the removed dummy gate stack.2. The method of claim 1 , wherein forming a replacement gate stack comprises depositing a conductive material in place of the removed dummy gate stack and recessing the conductive material.3. The method of claim 2 , further comprising depositing a capping material over the conductive material.4. The method of claim 3 , further comprising planarizing the capping material and the interlayer dielectric in a single planarization step.5. The method of claim 1 , wherein the implanting the ions generate tetra-dentate ligands in the interlayer dielectric.6. The method of claim 1 , wherein the interlayer dielectric has a sidewall with a bending angle of greater than 135°.7. The method of claim 1 , further comprising forming a second dummy gate stack over the fin claim 1 , wherein the second dummy gate stack has ...

Fin Field Effect Transistor (FinFET) Device and Method

A FinFET device structure is provided. The FinFET device structure includes an isolation structure formed over a substrate and a fin structure formed over the substrate. The FinFET device structure includes a first gate structure and a second gate structure formed over the fin structure, and the first gate structure has a first width in a direction parallel to the fin structure, the second gate structure has a second width in a direction parallel to the fin structure, and the first width is smaller than the second width. The first gate structure includes a first work function layer having a first height. The second gate structure includes a second work function layer having a second height and a gap between the first height and the second height is in a range from about 1 nm to about 6 nm. 1. A method comprising:forming a fin structure over a substrate;forming a first dummy gate structure and a second dummy gate structure over the fin structure;forming an inter-layer dielectric (ILD) structure over the substrate and adjacent to the first dummy gate structure and the second dummy gate structure;removing the first dummy gate structure to form a first trench in the ILD structure;removing the second dummy gate structure to form a second trench in the ILD structure;forming a first gate structure in the first trench and a second gate structure in the second trench, the first gate structure comprising a first work function layer and a first gate electrode layer, and the second gate structure comprising a second work function layer and a second gate electrode layer;removing portions of the first gate structure and the second gate structure outside of the first and second trenches;performing a first etch process on the first work function layer and the second work function layer, wherein after the first etch process the first work function layer has a top surface lower than a top surface of the first gate electrode layer, and wherein after the first etch process the second ...

FINFETS HAVING GATES PARALLEL TO FINS

Methods form devices by patterning a lower layer to form a fin, and forming a sacrificial gate along sidewalls of the fin. Such methods form a mask with cut openings on the sacrificial gate and remove sections of the fin and the sacrificial gate exposed through the cut openings to divide the fin into fin portions and create cut areas between the fin portions. Additionally, these methods remove the mask, epitaxially grow source/drains in the cut areas, replace the sacrificial gate with a gate conductor, and form a gate contact on the gate conductor over a center of the fin portions. 1. An apparatus comprising:fin portions aligned along a fin centerline, wherein the fin portions are separated along the fin centerline by cut areas;gate insulators on at least sidewalls of the fin portions;gate conductors on the gate insulators, wherein the gate conductors are positioned only along the sidewalls of the fin portions between the cut areas;a gate contact on the gate conductors, wherein the gate contact is positioned over a center of the fin portions; andsource/drain structures in the cut areas.2. The apparatus according to claim 1 , wherein the gate conductors extend a distance from each sidewall of the fin portions equal to a width of the fin portions.3. The apparatus according to claim 1 , wherein the gate conductors extend a first distance from one sidewall of the fin portions and extend a second distance from an opposite sidewall of the fin portions.4. The apparatus according to claim 1 , wherein the cut areas have a cut length along the fin centerline claim 1 , and wherein the cut length is less than a width of the fin portions.5. The apparatus according to claim 1 , wherein the gate insulators and the gate conductors are over a full amount of the fin portions claim 1 , and wherein the gate contact is over less than the full amount of the fin portions.6. The apparatus according to claim 1 , wherein the center of the fin portions is equidistant between the cut areas.7. ...

Integration of input/output device in vertical field-effect transistor technology

A method for fabricating a semiconductor device includes forming a vertical field-effect transistor (FET) device including a plurality of first fin structures in a vertical FET device area of a substrate, and forming an input/output (IO) FET device including at least two second fin structures in an IO FET device area of the substrate. The at least two fin structures are connected by a channel having a length determined based on at least one voltage for implementing the IO FET device. Forming the vertical FET and IO FET devices includes selectively exposing a portion of the IO FET device area by selectively removing a portion of a first spacer formed on the substrate in the IO FET device area.

INTEGRATED CIRCUITS WITH SELECTIVE GATE ELECTRODE RECESS

Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit. 1. A method of fabricating an integrated circuit , the method comprising:forming a first gate electrode having a first bottom electrode surface proximate to a first gate dielectric disposed over a first semiconductor channel region and having a first top electrode surface at a first height from the first bottom gate electrode surface;forming a second gate electrode having a second bottom electrode surface proximate to a second gate dielectric disposed over a second semiconductor channel region and having a second top electrode surface at a second height from the second bottom electrode surface; andrecessing at least a portion of a first top electrode surface below at least a portion of the second top electrode surface.2. The method of claim 1 , wherein the first gate electrode is associated with a first gate length claim 1 , wherein the second gate electrode is associated with a second gate length claim 1 , greater than the first gate length claim 1 , and wherein recessing at least a portion of the first top electrode surface below at least a portion of the second top electrode surface further comprises:forming a protective mask over the second top electrode surface;etching back the first gate electrode; andremoving the protective mask.3. The method of claim 2 , wherein forming the ...

VERTICAL TRANSISTORS HAVING DIFFERENT GATE LENGTHS

A method of forming a semiconductor device and resulting structures having vertical transistors with different gate lengths are provided. A sacrificial gate is formed over a channel region of a semiconductor fin. The sacrificial gate includes a first material. The first material in a first portion of the sacrificial gate adjacent to the semiconductor fin is converted to a second material, the first portion having a first depth. The first portion of the sacrificial gate is then removed. 1. A semiconductor device , the device comprising:a first semiconductor fin formed on a first portion of a doped region of a substrate and a second semiconductor fin formed on a second portion of the doped region of the substrate, the first portion and the second portion of the doped region separated by an isolation region;a first gate formed over a channel region of the first semiconductor fin, the channel region of the first semiconductor fin comprising a first length, the first length determined by a first implant energy; anda second gate formed over a channel region of the second semiconductor fin, the channel region of the second semiconductor fin comprising a second length, the second length determined by a second implant energy;wherein the first implant energy and the second implant energy are different;wherein the first length and the second length are different.2. The semiconductor device of claim 1 , wherein the difference between the first length and the second length is about 10 nm to about 40 nm.3. The semiconductor device of claim 1 , wherein the first gate comprises a first height and the second gate comprises a second height claim 1 , the first height greater than the second height.4. The semiconductor device of claim 1 , further comprising:a third semiconductor fin formed on a third portion of the doped region of the substrate, the third portion separated from the first portion and the second portion of the doped region by an isolation region;a third gate formed over ...

INTEGRATED CIRCUIT LAYOUT AND METHOD THEREOF

An integrated circuit (IC) structure includes a first transistor and a second transistor. The first transistor includes a first active region and a first gate disposed on the first active region, in which the first gate has a first effective gate length along a first direction parallel to a lengthwise direction of the first active region. The second transistor includes a second active region and a second gate disposed on the second active region, and includes a plurality of gate structures arranged along the first direction and separated from each other, in which the second gate has a second effective gate length along the first direction, the second effective gate length is n times the first effective gate length, and n is a positive integer greater than 1. 1. An integrated circuit (IC) structure , comprising: a first active region; and', 'a first gate disposed on the first active region, wherein the first gate has a first effective gate length along a first direction parallel to a lengthwise direction of the first active region; and, 'a first transistor comprising a second active region; and', 'a second gate disposed on the second active region and comprising a plurality of gate structures arranged along the first direction and separated from each other, wherein the second gate has a second effective gate length along the first direction, the second effective gate length is n times the first effective gate length, and n is a positive integer greater than 1., 'a second transistor comprising2. The IC structure of claim 1 , wherein the gate structures of the second gate are electrically connected to a same voltage node.3. The IC structure of claim 1 , wherein each of the gate structures has a gate length substantially the same as the first effective gate length claim 1 , and wherein a number of the gate structures is n.4. The IC structure of claim 1 , wherein the second transistor further comprises a plurality of gate spacers disposed adjacent opposite sidewalls of ...

Methods of Manufacturing Transistor Gate Structures by Local Thinning of Dummy Gate Stacks Using an Etch Barrier

Example embodiments relating to forming gate structures, e.g., for Fin Field Effect Transistors (FinFETs), are described. In an embodiment, a structure includes first and second device regions comprising first and second FinFETs, respectively, on a substrate. A distance between neighboring gate structures of the first FinFETs is less than a distance between neighboring gate structures of the second FinFETs. A gate structure of at least one of the first FinFETs has a first and second width at a level of and below, respectively, a top surface of a first fin. The first width is greater than the second width. A second gate structure of at least one of the second FinFETs has a third and fourth width at a level of and below, respectively a top surface of a second fin. A difference between the first and second widths is greater than a difference between the third and fourth widths. 1. A method of semiconductor processing , the method comprising:forming a first fin and a second fin over a substrate;forming isolation regions adjacent the first fin and the second fin;forming a first dummy gate structure over the first fin;forming a second dummy gate structure over the second fin;simultaneously forming an etch barrier layer along sidewalls of the first dummy gate structure and the second dummy gate structure, wherein the etch barrier layer along a lower portion of a sidewall of the first dummy gate structure is thinner than the etch barrier layer along a lower portion of a sidewall of the second dummy gate structure; andetching the etch barrier layer, the first dummy gate structure, and the second dummy gate structure, wherein the lower portion of the sidewall the first dummy gate structure is etched a greater amount than the lower portion of the sidewall of the second dummy gate structure.2. The method of further comprising repeating the simultaneously forming the etch barrier layer and the etching the etch barrier layer one or more times.3. The method of claim 1 , wherein ...

Methods of Manufacturing Transistor Gate Structures by Local Thinning of Dummy Gate Stacks Using an Etch Barrier

Example embodiments relating to forming gate structures, e.g., for Fin Field Effect Transistors (FinFETs), are described. In an embodiment, a structure includes first and second device regions comprising first and second FinFETs, respectively, on a substrate. A distance between neighboring gate structures of the first FinFETs is less than a distance between neighboring gate structures of the second FinFETs. A gate structure of at least one of the first FinFETs has a first and second width at a level of and below, respectively, a top surface of a first fin. The first width is greater than the second width. A second gate structure of at least one of the second FinFETs has a third and fourth width at a level of and below, respectively a top surface of a second fin. A difference between the first and second widths is greater than a difference between the third and fourth widths. 1. A structure comprising:a first device region comprising first fin Field Effect Transistors (FinFETs) on a substrate; and a first distance between neighboring gate structures of the first FinFETs is less than a second distance between neighboring gate structures of the second FinFETs;', 'a first gate structure of at least one of the first FinFETs has a first width at a level of a top surface of a first fin on which the first gate structure is disposed and a second width at a level below the top surface of the first fin, the first width being greater than the second width;', 'a second gate structure of at least one of the second FinFETs has a third width at a level of a top surface of a second fin on which the second gate structure is disposed and a fourth width at a level below the top surface of the second fin; and', 'a difference between the first width and the second width is greater than a difference between the third width and the fourth width., 'a second device region comprising second FinFETs on the substrate, wherein2. The structure of claim 1 , wherein the third width is equal to the ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device includes a first semiconductor channel, a second semiconductor channel, a first gate stack and a second gate stack. The first gate stack is present on the first semiconductor channel. The second gate stack is present on the second semiconductor channel. The first gate stack and the second gate stack are different at least in tantalum nitride amount. 1. A semiconductor device , comprising:a first semiconductor channel;a second semiconductor channel;a first gate stack present on the first semiconductor channel; anda second gate stack present on the second semiconductor channel, wherein the first gate stack and the second gate stack are different at least in tantalum nitride amount, wherein the first gate stack comprises a first tantalum nitride layer and a first filling conductor layer embedded in the first tantalum nitride layer, the second gate stack comprises a second tantalum nitride layer and a second filling conductor layer embedded in the second tantalum nitride layer, the first filling conductor layer and the first semiconductor channel define a first distance, the second filling conductor layer and the second semiconductor channel define a second distance, and the first distance is different from the second distance.2. The semiconductor device of claim 1 , wherein the first tantalum nitride layer and the second tantalum nitride layer have different thicknesses.3. The semiconductor device of claim 2 , wherein the first tantalum nitride layer is thinner than the second tantalum nitride layer claim 2 , and the second gate stack further comprises a work function layer made of a material other than tantalum nitride.4. The semiconductor device of claim 3 , wherein the second tantalum nitride layer is present between the work function layer and the second semiconductor channel.5. (canceled)6. The semiconductor device of claim 1 , wherein the first tantalum nitride layer is thinner than the second tantalum nitride layer claim 1 , and the first ...

Semiconductor Device

A semiconductor device is provided. The semiconductor device includes a field insulating film on a substrate, a first fin type pattern which is formed on the substrate and protrudes upward from an upper surface of the field insulating film, and a gate electrode which intersects with the first fin type pattern on the field insulating film and includes a first portion and a second portion, the first portion being located on one side of the first fin type pattern and including a first terminal end of the gate electrode, and the second portion being located on the other side of the first fin type pattern, wherein a height from the substrate to a lowest part of the first portion is different from a height from the substrate to a lowest part of the second portion. 1. A semiconductor device comprising:a field insulating film on a substrate;first and second fin type patterns which are formed on the substrate so as to be closest to each other and protrude upward from an upper surface of the field insulating film, respectively;a first gate electrode which intersects with the first fin type pattern on the field insulating film and includes a first portion and a second portion, the first portion and the second portion being placed with the first fin type pattern interposed therebetween, and the first portion including a first terminal end of the first gate electrode; anda second gate electrode which intersects with the second fin type pattern on the field insulating film and includes a third portion and a fourth portion, the third portion and the fourth portion being placed with the second fin type pattern interposed therebetween, and the third portion including a second terminal end of the second gate electrode facing the first terminal end of the first gate electrode,wherein a height from the substrate to a lowest part of the first portion is different from a height from the substrate to a lowest part of the second portion.2. The semiconductor device of claim 1 , wherein the ...

REPLACEMENT METAL GATE STACK FOR DIFFUSION PREVENTION

A method of forming a semiconductor structure includes depositing a gate dielectric layer lining a recess of a gate structure formed on a substrate with a first portion of the gate dielectric layer covering sidewalls of the recess and a second portion of the gate dielectric layer covering a bottom of the recess. A protective layer is deposited above the gate dielectric layer and then recessed selectively to the gate dielectric layer so that a top surface of the protective layer is below of the recess. The first portion of the gate dielectric layer is recessed until a top of the first portion of the gate dielectric layer is approximately coplanar with the top surface of the protective layer. The protective layer is removed and a conductive barrier is deposited above the recessed first portion of the gate dielectric layer to cut a diffusion path to the gate dielectric layer. 1. A semiconductor structure comprising:a gate structure formed above a substrate, the gate structure comprising:a metal gate above a conductive barrier, anda gate dielectric layer below the conductive barrier; anda capping layer above the gate structure, wherein the conductive barrier separates the capping layer from the gate dielectric layer.2. The semiconductor structure of claim 1 , wherein the gate structure comprises a length less than 20 nm.3. The semiconductor structure of claim 1 , wherein the conductive barrier comprises an n-type workfunction metal.4. The semiconductor structure of claim 1 , wherein the gate dielectric layer comprises a high-k dielectric material.5. The semiconductor structure of claim 1 , wherein the gate dielectric layer has a vertical portion and a horizontal portion claim 1 , the vertical portion of the gate dielectric layer having a height less than a height of the metal gate measured from a top surface of the substrate.6. The semiconductor structure of claim 5 , wherein the height of the vertical portion of the gate dielectric layer is within a range from 1 nm to ...

EPITAXIAL STRUCTURE OF N-FACE AlGaN/GaN, ACTIVE DEVICE, AND METHOD FOR FABRICATING THE SAME WITH INTEGRATION AND POLARITY INVERSION

The present invention provides an epitaxial structure of N-face AlGaN/GaN, its active device, and the method for fabricating the same. The structure comprises a substrate, a C-doped buffer layer on the substrate, a C-doped i-GaN layer on the C-doped buffer layer, a i-Al y GaN buffer layer on the C-doped i-GaN layer, an i-GaN channel layer on the C-doped i-Al y GaN buffer layer, and an i-Al x GaN layer on the i-GaN channel layer, where x=0.1˜0.3 and y=0.05˜0.75. By using the p-GaN inverted trapezoidal gate or anode structure in device design, the 2DEG in the epitaxial structure of N-face AlGaN/GaN below the p-GaN inverted trapezoidal gate structure will be depleted. Then the 2DEG is located at the junction between the i-GaN channel layer and the i-Al y GaN layer, and thus fabricating p-GaN gate enhancement-mode (E-mode) AlGaN/GaN high electron mobility transistors (HEMTs).

Methods of forming fine patterns in the fabrication of semiconductor devices

In a method of forming a semiconductor device, a feature layer is provided on a substrate and a mask layer is provided on the feature layer. A portion of the mask layer is removed in a first region of the semiconductor device where fine features of the feature layer are to be located, the mask layer remaining in a second region of the semiconductor device where broad features of the feature layer are to be located. A mold mask pattern is provided on the feature layer in the first region and on the mask layer in the second region. A spacer layer is provided on the mold mask pattern in the first region and in the second region. An etching process is performed to etch the spacer layer so that spacers remain at sidewalls of pattern features of the mold mask pattern, and to etch the mask layer in the second region to provide mask layer patterns in the second region. The feature layer is etched using the mask layer patterns as an etch mask in the second region and using the spacers as an etch mask in the first region to provide a feature layer pattern having fine features in the first region and broad features in the second region.

Semiconductor device and method for fabricating the same

A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a substrate, a first nanowire spaced apart from a first region of the substrate, a first gate electrode surrounding a periphery of the first nanowire, a second nanowire spaced apart from a second region of the substrate and extending in a first direction and having a first width in a second direction intersecting the first direction, a supporting pattern contacting the second nanowire and positioned under the second nanowire, and a second gate electrode extending in the second direction and surrounding the second nanowire and the supporting pattern.

Vertical transistors having multiple gate thicknesses

Embodiments of the invention are directed to methods of forming a configuration of semiconductor devices. A non-limiting example method includes forming a first channel fin structure over a performance region of a major surface of a substrate. A first gate structure is formed along at least a portion of a sidewall surface of the first channel fin structure, where the first gate structure includes a first gate thickness dimension. A second channel fin structure si formed over a density region of the major surface of the substrate. A second gate structure is formed along at least a portion of a sidewall surface of the second channel fin structure, where the second gate structure includes a second gate thickness dimension that is less than the first gate thickness dimension.

Multi-threshold voltage devices and associated techniques and configurations

Embodiments of the present disclosure describe multi-threshold voltage devices and associated techniques and configurations. In one embodiment, an apparatus includes a semiconductor substrate, a channel body disposed on the semiconductor substrate, a first gate electrode having a first thickness coupled with the channel body and a second gate electrode having a second thickness coupled with the channel body, wherein the first thickness is greater than the second thickness. Other embodiments may be described and/or claimed.

VERTICAL STRUCTURE FOR SEMICONDUCTOR DEVICE

The present disclosure describes a method to form a fin field effect transistor (finFET) and a nano-sheet transistor on a substrate. The method can include forming first and second vertical structures over a substrate, where each of the first and the second vertical structures can include a buffer region and a first channel layer formed over the buffer region. The method can further include disposing a masking layer over the first channel layer of the first and second vertical structures, removing a portion of the first vertical structure to form a first recess, forming a second channel layer in the first recess, forming a second recess in the second channel layer, and disposing an insulating layer in the second recess. 1. A method , comprising:forming first and second vertical structures over a substrate, wherein each of the first and the second vertical structures comprises a buffer region and a first channel layer formed over the buffer region;removing a portion of the first vertical structure to form a first recess;forming a second channel layer in the first recess;forming a second recess in the second channel layer; anddisposing an insulating layer in the second recess.2. The method of claim 1 , wherein the removing the portion of the first vertical structure comprises:forming a masking layer over the first channel layer of the first and second vertical structures;removing the masking layer of the first vertical structure to expose the first channel layer of the first vertical structure; andetching the first channel layer of the first vertical structure.3. The method of claim 1 , wherein the forming the second channel layer over the first recess comprises epitaxially growing a semiconductor layer in the first recess.4. The method of claim 1 , wherein the forming the second channel layer in the first recess comprises capping the first channel of the second vertical structure with a masking layer.5. The method of claim 1 , wherein the forming the second recess in ...

GATE STRUCTURES WITH VARIOUS WIDTHS AND METHOD FOR FORMING THE SAME

Embodiments of a semiconductor device structure and a method for forming the same are provided. The semiconductor device structure includes a substrate and a first metal gate structure formed over the substrate. The first metal gate structure has a first width. The semiconductor device structure further includes a first contact formed adjacent to the first metal gate structure and a second metal gate structure formed over the substrate. The second metal gate structure has a second width smaller than the first width. The semiconductor device structure further includes an insulating layer formed over the second metal gate structure and a second contact self-aligned to the second metal gate structure. 1. A method for forming a semiconductor device structure , comprising:forming a first metal gate structure and a second metal gate structure in an inter-layer dielectric (ILD) layer over a substrate;forming a mask structure on the first metal gate structure and exposing a top surface of the second metal gate structure;etching a top portion of the second metal gate structure to shorten the second metal gate structure;forming an insulating layer on the second metal gate structure; andforming a first contact adjacent to the first metal gate structure and a second contact self-aligned to the second metal gate structure,wherein the first metal gate structure has a first width and the second metal gate structure has a second width smaller than the first width.2. The method for forming a semiconductor device structure as claimed in claim 1 , further comprising:removing the mask structure before insulating layer is formed on the second metal gate structure.3. The method for forming a semiconductor device structure as claimed in claim 1 , wherein a portion of the second contact is formed on the insulating layer and is separated from the second metal gate structure by the insulating layer.4. The method for forming a semiconductor device structure as claimed in claim 1 , wherein the ...

ASYMMETRIC GATE PITCH

The present disclosure describes an exemplary asymmetric CPP layout for a semiconductor structure with a different gate pitch over the source and the drain regions to mitigate gate-to-gate parasitic capacitances over the drain region, thus improving cutoff frequency. For example, the semiconductor structure can include a fin on a substrate. The semiconductor structure can also include first and second gate structures formed on the fin and separated by a first space. The semiconductor structure can also include a third gate structure formed on the fin between the first and the second gate structures. The third gate structure can be separated from the first gate structure by a second pitch and separated from the second gate structure by a third pitch that is greater than the second pitch. The semiconductor structure further includes a source region formed between the first and third gate structures, and a drain region formed between the third and the second gate structures. 1. A semiconductor structure , comprising:a substrate with one or more fins disposed thereon;a first gate structure disposed on the one or more fins;a second gate structure disposed on the one or more fins and separated from the first gate structure by at least a first pitch;a third gate structure disposed on the one or more fins so that the second gate structure is between the first and third gate structures, wherein the third gate structure is separated from the second gate structure by at least a second pitch larger than the first pitch;a source region formed in a portion of the one or more fins between the first and second gate structures; anda drain region formed in a portion of the one or more fins between the second and third gate structures.2. The semiconductor structure of claim 1 , wherein:the first gate structure comprises a first top portion over the one or more fins, a first side portion on a sidewall of the one or more fins, and a first bottom portion on an isolation region between ...