SEMICONDUCTOR DEVICE MANUFACTURING METHOD

Hereinafter, reference to the drawing objects of the present invention preferred embodiment detailed as follows.

The present invention refers to various modification may have bar can apply in various forms, in the embodiment herein detailed drawing and example are specific to broadcast receiver. However, the present invention is defined with respect to a particular disclosure form be but is, all changing range of idea and techniques of the present invention, including the water to replacement should understood to evenly. Each drawing are described as well as a component while similar references in a similar.

Number 1, number 2 describes various components such as term can be used but, in terms of said components are defined by said back like. Components are mounted to one of said terms are used only distinguished from other components of the object. For example, number 1 number 2 outside of the range of the present invention rights without components can be termed components, similarly number 2 of the elements can be termed component number 1.

A term used in a particular application only is used to account for in the embodiment, the present invention intending to be define is endured. It is apparent that a single representation of the differently in order not providing language translators, comprising plurality of representation. In the application, the term "comprising" or "having disclosed" specification of articles feature, number, step, operation, component, piece or specify a combination not present included, another aspect of one or more moveable number, step, operation, component, piece or a combination of pre-times the number should not understood to presence or additional possibility.

Not defined differently, scientific or technical terms so that all terms in the present invention thus is provided to the person with skill in the art will generally have the meanings etc. by same. Dictionary used for such as generally defined on the context of respective technical terms have the meanings must be consistent semantics and having interprets, the application manifest in not ideal or overly formal sense broadly define not interpreted.

Figure 1 shows a perspective view also in one embodiment of the present invention representing forming semiconductor which, 1 representing the layout of semiconductor device shown in Figure 2 also are disclosed. Also shown in Figure 3 shows a plane view and also 1 of semiconductor, a semiconductor element is shown in Figure 4 also 1 of Figure 2 I a-I ' cross-section cutting along the direction are disclosed.

The reference also 1 to 4 also, in one embodiment of the present invention forming semiconductor (1000) is isolation layer (200) defined by a plurality of active region (A) (A) (x) number 1 so as to intersect the plurality of active region and said direction extending along a pair of gates gate trench (190) said active region (A) having the gate said gate trench (190) located the bottom of the pair of the gate (G) (G) (A) of said active region between said gate region and a centrally positioned number 1 junction region (J1) and said active region is divided into a number 2 (J2) (A) junction region at an end of the semiconductor substrate (100), said gate gate trench (190) and bottom along a lower sidewall of the gate insulating film (310), said gate insulating film (310) and the surfaces of the upper surface of said gate and gate trench (190) is filled with the lower part of the gate line (320) and said gate line (320) covering said gate insulating film (310) equal to said an upper gate line (320) a cap placed on top of dizzily line (330) having a conductive line number 1 (300) and said number 1 and number 2 (J1, J2) to an upper junction region equal to gate said gate trench (190) having a buried conductive lines of said number 1 (300) covering said gate gate trench (190) having a width the same sealing line (400) comprises.

Said substrate (100) silicon substrate includes, silicon - germanium (Si-a Ge) or SOI (silicon provided on a non-insulation) and semiconductor substrate such as, a plurality of conductive structures disposed active region (A) (A) (F) are divided into said active region and defining a field region. (F) of insulating material is disposed inside said field region adjacent active region disposed on the electrically conductive structures are divided into each other (A).

For example, narrow trench isolation (shallow trench isolation, STI) process (F) said field region is formed by silicon oxide film such as isolation layer (200) (A) disposed adjacent active region disposed on the gate structures electrically isolated each other.

In particular, unlike that of said floating gate layer core/peripheral cell isolation (200) is a die pad to said trench field region (F) (200) (device isolation trench) number is not part of an element isolation layer sufficiently the size of the ball. The, sidewall oxide layer sidewall oxidation layer coated liner (liner) (sidewall oxide layer) or cell region isolation trench is disclosed. In the case of a in the embodiment, said isolation layer (200) an inner sidewall function layer number the device isolation oxide films co 1308.

Isolation (200) (A) defined by a plurality of active region substrate having (100) extending along a constant margin that is number 1 direction (x) gate gate trench (190) is number 2 direction (y) spaced at regular intervals along a plurality disposed thereon.

The, said gate trench (190) is engaging the active region (A) said gate trench (190) while forming a partially number that are adjacent an upper active region is equal to lower than the wetting ability. Said gate trench (190) engaging the upper surface of the substrate active region lower than a top surface of the gate structure is disposed gate region (G) number and ball, gate trench (190) located in the gate region (G) and adjacent surface of the substrate active region (J) encoded number ball bond region to separate insulating layer pattern. , the semiconductor element in the embodiment (1000) of a gate structure substrate (100) disposed so as to be lower than the upper surface of the sealing line and carry cap dizzily line (330,400) encoded by a filling gate structure (buried gate structure) to ball number.

In particular, said gate trench (190) defining along isolation gate region (G) (200) (G) disposed so as to be lower than an upper surface of the gate region on the upper surface of said gate trench (190) a bottom portion of isolation layer (200) between said number 1 (G1, G2) are gate region along a direction projecting depression structure.

In the case of a in the embodiment, the active region (A) said substrate (100) of number 1 and number 2 (x, y) obliquely along direction angle one to the other and, said number 1 number 1 and number 2 (y) direction extending along direction (x) include light emitting diodes disposed adjacent along a pair of gate trench (190) on the basis of the disposed thereon.

The, said active region (A) cross each gate trench (190) a pair of the gate (G1, G2) are located inside each gate trench (190) a substrate (190) the number 1 and number 2 (J1, J2) are divided into junction region disposed on the upper surface. Said number 1 and number 2 (J1, J2) impurities are injected into the junction region by the ion implantation process of the gate structure connected to said junction layer etched layer has ball number.

The, a single active region (A) said gate located between a pair of gate structure is disposed active region number 1 (J1) (A) junction region of the gate structure to said drain region (D) central wife the ball number encoded. Said drain region (D) such as the direct contact (direct contact) structure is disposed through bit line number 2 such as conductive lines with said interconnect structure connected thereto. In addition, said active region (A) number 2 (J2) located at both ends of the junction region of the gate structure etched source region each ball number. Said source region (S) through capacitor structure such as a buried contact (buried contact) such as charge storage unit for storing connected thereto.

The same gate trench (190) disposed along a plurality of gate structures have number 1 number 1 direction (x) connected to conductive lines (300) encoded into ball number. Said number 1 conductive lines (300) word line of a semiconductor memory device serving as a substrate.

For example, said number 1 conductive lines (300) is a plurality of gate structures may be connected number 1 (G) said gate region disposed conductive pattern gate line extending along a direction (x) (320) and said gate line (320) that it can be placed on top of dizzily line (330) comprises.

Having an uneven structure feature profile along said gate trench (190) covering said side wall of said portion and the bottom of the junction region (J) isolation (200) formed to cover sidewalls of gate insulating film (310) is disposed said gate line (320) is said gate insulating film (310) in contact with said gate trench (190) to gap-fill number 1 (x) extended in a first direction along the lower part of the.

For example, a gate insulating film (310) comprising a silicon gate line (320) includes a tungsten (W), titanium (Ti), tantalum (Ta) comprising such as conductive metal layer. In the case of a in the embodiment, gate line (320) is said gate insulating film (310) contacted to the surface of barrier layer (321) and barrier layer (321) in contact with the metal film (322) having a multi-layered film structure. For example, said barrier layer (321) and said metal film is titanium nitride film (TiN) (322) is can be including tungsten layer.

The, gate insulating film (310) and said upper surface of said junction region (J) lower than a top surface of the gate line (320) said top surface of the gate insulating film (310) lower than said upper surface of proximately located with the gate line (320) is said gate trench (190) in the interior of the gate insulating film (310) arranged to be surrounded by completely by disposed thereon.

Said gate line (320) of photosensitive film (310) and an upper extending along substantially the same direction (x) number 1 and capping line (330) disposed thereon. Said cap dizzily line (330) are subsequently formed by wiring lines or contact structure such as conductive structure said gate line (320) and subsequent etching process for electrically isolating the gate from the line (320) to protect other. For example, said cap dizzily line (330) comprises silicon nitride.

Cap dizzily line (330) and the gate insulation film (310) is expected in the periphery of the upper surface, gate trench (190) of upper region is cap dizzily line (330) by non-embedded and exposed substrate. In particular, cap dizzily line (330) the surface of the trench (190) a gate insulating film formed on the side wall (310) disposed not gate trench (190) active region (A) constituting the side wall of the insulation layer (200) are exposed.

Said capping line (330) number 1 extends along part of the gate trench (190) a mask is formed to sealing line (sealing line, 400) disposed thereon. For example, said sealing line (400) is said cap dizzily line (330) made of an insulating material and the same said gate trench (190) in parallel to the joint region (J) on insulation layer (200) equal to the upper surface of an upper disposed thereon.

The, said gate line (320) to remain of dizzily line (330) and sealing line (400) being extended double gate line (320) and external ground substrate. In particular, in subsequent contact structure layer for sealing line (400) and a cap dizzily line (330) includes a gate line (320) to function under the first as well as protection of the second contact structure for aligning the be. The, gate line (320) to reduce the data of the damage can be exposed.

In particular, said gate trench (190) from upper sidewall of gate insulating film (310) and a stand-alone said sealing line number (400) by replacing said active region (A) (J) junction region along the longitudinal direction of a gate insulating film on a perimeter of said insulating regions (310) of the sample can be extended.

As well as, said gate trench (190) at the top of the gate insulating film defining a junction region number 1 (J1) (310) number a bit line contact hole can be produced in a stand-alone due to bit line contact bridge can be prevent residual gate insulating film. The, integrated increased despite said semiconductor device and enables the reduction of line width (1000) can be stably maintain the of operating stability.

In the case of a in the embodiment, said cap dizzily line (330) and sealing line (400) is made of an insulating material in the same way as said gate trench (190) in the interior of the gate line (320) gate mask protecting functions as a substrate. The, said gate line (320) for protecting a gate mask line (320) and relatively narrow contact with mask and gate trench (190) is embedded in an upper region of an overlying mask composed of a mushroom shape and relatively wider (mushroom shape) of 2 stage structure can be arranged.

In the case of a in the embodiment, said junction region (J) from the surface of said gate line (320) to upper surface depth (D_G ) To about 60 nm to 70 nm and ball number, depth of about 30 nm to 35 nm (Ds) applied to said sealing line ball number. The, said cap dizzily line (330) from about 30 nm to about 25 nm depth of ball number can be disclosed.

Said gate insulating film (310) is said number 1 junction region (J1) by recessing the bit line contact hole partially generated in the process where the dummy bit line contact bridge for residual upper channel since, if said bridge failure do not affect process efficiency range may be filled partially remain.

In the embodiment shown in 4a cross-sectional drawing representing deformation of semiconductor is also 4b also are disclosed.

The 4b also reference, said gate trench (190) in an upper region of sealing line (400) and gate trench (190) of a gate insulating film formed on the semiconductor substrate remaining (residual Gox, 311) disposed thereon.

Said gate insulating film (310) for driving the industry a number of process conditions by the difference between the variable precision etching said gate insulating film (310) is partially gate trench (190) to a gate insulating film formed on a sidewall of said remaining residual (311) JPO.

A gate insulating film (310) stand-alone without in subsequent processing bit line contact completely number unless the injection hole completely number need be volatile strongly bridge low disclosed. The, gate insulating film (310) of the mask remaining after said gate insulating film (311) formed therein carry the CMP and the remaining gate insulating film (311) can be a stand-alone number actual profit is free.

For example, residual said gate insulating film (311) for about 1 nm to 2 nm have a thickness of the bit line can be coupled to the bridge failure is non-negligible. In the case of a in the embodiment, said gate line (320) constituting the gate insulating film (310) has a thickness of about 6 nm to 8 nm (tG). The, said gate insulating film (310) to the etching process is a stand-alone number 33% remaining maximum thickness quality allows precision that can be performed.

Said number 1 and number 2 (J1, J2) junction region is doped with impurity by ion implantation process are respectively drain region (D) and source regions (S) encoded into ball number. The, said source and drain regions (S, D) is said number 1 conductive lines (300) number 1 at regular intervals along selective direction (x) disposed thereon.

Said gate region (G) buried gate structure and source and drain regions disposed said semiconductor device (1000) unit cell of a JPO. The, said semiconductor device (1000) is a buried channel array transistor (buried channel array transistor, BCAT).

In the case of a in the embodiment, said semiconductor device (1000) said number 1 and number 2 gate region (G1, G2) is embedded gate structure is disposed a bit line contact to butt against said number 1 junction region (J1) connected along an upper contact to butt against said number 2 junction region (J2) cache memory the other module. In addition, conductive lines extending along said number 1 number 1 direction (300) to carry the of forming a wordline in number and hole number 2 conductive lines (600) co number encoded bit line. The, said semiconductor device (1000) is 6F² (F: minimum feature size) the layout of said word line by arranging a word line pitch gaps between 0. 5F respective to the amplifiers are can be reduced by reducing the footprint. The, effective channel length can be reduced while increasing overall shapes and sizes.

Buried channel array transistor structure such as described above by placing a conductive lines and charge storage part number 2 on top of said semiconductor device (1000) memory element a number [...] substrate.

The present invention is also 5a by a memory element of Figure 2 II a-II 'cross-sectional drawing and cutting along the direction, the present invention is also 5b by a memory element of Figure 2 III a-III' cross-sectional drawing cutting along the direction are disclosed. In addition, the present invention is also 5c by a memory element of Figure 2 IV a-IV ' cross-sectional drawing cutting along the direction are disclosed.

The reference also 5a to 5c also, said sealing line (400) insulation layer (200) defined by said predetermined depth is recessed sealing line (400) and the surfaces (D) having number 1 (C1) and (C1) is connected to the drain region contact said number 2 (y) extending along said number 1 and number 2 direction contact connected with conductive lines (600) and said sealing line (400) a source region (S) defined by the semiconductor contact number 2 (C2) and said number 2 connected with the charge storage part contact (C2) (800) is disposed thereon.

For example, interlayer dielectric pattern number 1 (500) are exposed through said opening (not shown) the drain region to said drain region (D) partially number (D) stand-alone for filling the sealing line (400) lower than an upper surface of the contact hole (H1) in the interior of said drain region (D) number 1 (C1) placed in contact with a contact number 1.

Said number 1 interlayer dielectric pattern (500) is comprised of an oxide (not shown) including a lower pattern (not shown) consisting of a double film pattern encoded number ball and nitride upper pattern.

Said number 1 contact hole the interlayer insulating film pattern corresponding to said drain region (D) number 1 (H1) (500) (D) and the upper surface of exposed mask pattern or said drain region exposed only drain disposed adjacent said drain region covers only a source (S) (D) and peripheral regions on the interlayer dielectric pattern number 1 (500) can be formed using a mask pattern by exposing the covered source.

In the case of a in the embodiment, the drain region (D) said gate insulating film (310) and said cap dizzily line (330) to the upper surface of an upper or high disposed thereon. , the sealing line contact hole said number 1 (H1) (400) has a depth of 30 nm to 35 nm corresponding to depth of (Ds).

The, said drain region (D) that is adjacent the gate trench (190) gate insulating film at a side section (31) not covered by said mask pattern arranged mask pattern misalignment even if the mask pattern to the bottom of the source or drain exposed gate insulating film is equal to each sport does not exist. The, said number 1 (H1) remaining on the periphery of the contact hole is not present or is constant residual thickness hereinafter to gate insulating film disposed thereon. The, each upper channel number 1 (C1) would become incomplete contact sport number that are adjacent the bridge connects with number 1 are cut and can be made of a specific material.

Said number 1 is a low resistance metal or conductive material such as polysilicon contact hole (H1) (C1) (D) and said drain region disposed contact number 1 consisting r11. Said number 1 contact (C1) is coupled to the part of the number 1 number 2 (y) contact (C1) with a conductive pattern extending along direction and second tubular bit line (610) and said bit line (610) covering the ground with the exterior of the conductive line and said number 2 (600) controlling the height of the bit line mask (620) having conductive line number 2 (600) disposed thereon.

In the case of a in the embodiment, said number 2 conductive lines (600) serving as a conductive line number 1 word lines (300) and extends in a direction perpendicular read bit line serving as a substrate.

(C1) and a bit line contact said number 1 (610) can be disposed in various ways to improve the performance of the memory element. For example, the aspect ratio of contact hole number 1 (H1) (leaning) for leaning due to the dummy bit line can also be ball plug form number (610) can extend his or her number ball contact area to partially shape can also be disclosed.

In particular, said drain region (D) by a given depth by recessing by lowering a bit line (610) is reduced by reducing the height of the overall memory device can be reduce. In the case of a in the embodiment, said bit line (620) that of the peripheral/core peripheral TFT disposed on the same plane (gate bit line, GBL) bit line gate 1308. ball number.

Conductive lines extending along the direction (y) number 2 number 2 (600) are disposed on the spacer (630) and said number 2 conductive lines by an insulation region (600) number 2 [...] between interlayer insulation film pattern (700) are buried. Said number 2 interlayer dielectric pattern (700) (S) number 2 (H2) of contact holes exposing the source region through the contact (C2) arranging said number 2 number 2 inner interlayer insulation film pattern (700) in contact with the upper surface of said number 2 contact (C2) charge storage unit (800) placed. The, said source region (S) contact (C2) the number 2 via store (800) for electrically connected thereto. In the case of a in the embodiment, the junction region of said number 2 (C2) contact said number 2 (J2) inserted into the buried contact (buried contact, BC) and said charge storage unit (800) is buried contact comprises connecting said capacitor.

The, said memory device said gate region (G) number 1 and number 2 (BG) buried gate structure disposed (J1, J2) number 1 and number 2 contact (C1, C2) and junction region disposed buried channel array transistor (BCAT) consisting of, said number 1 and number 2 conductive lines (300,600) and said charge storage unit (800) to consists of.

Semiconductor memory device such as described above (1000) is, gate trench (190) and upper sidewall of gate insulating layer from a stand-alone sealing line number (400) by replacing (A) junction region along the longitudinal direction of the active region (J) can be a conductive layer extending on a perimeter of said gate insulating regions.

The, gate line (320) to remain of dizzily line (330) and sealing line (400) being extended double, contact structure layer for sealing line in (400) and a cap dizzily line (330) includes a gate line (320) by protecting functions under the first gate line (320) can be operation of stability.

In hereinafter, also shown in buried channel array transistor 1 has a supporting structure on a passing word lines number bath method described substrate. In hereinafter of drawing, [...] 'a' of Figure 2 II a-II is' direction cutting along the cross-sectional drawing and, [...] ' b of Figure 2 III a-III is' cross-sectional drawing cutting along the direction are disclosed. In addition, [...] 'c'is of Figure 2 IV a-IV' cross-sectional drawing cutting along the direction are disclosed.

In one embodiment of the present invention is shown in which a semiconductor element 1 also 6a to also 15c along manufacturing method of representing cross-sectional drawing memory device also are disclosed.

The reference also 6a to 6c also, isolation layer (200) having an active region defined by the semiconductor substrate (A) (100) (A) direction (x) number 1 so as to intersect on said active region extends along the trench (190) to said substrate (A) said active region formed on the (100) surface (G) and lower than a surface of said gate region is divided into a joint region (J) 2000.

For example, said substrate (100) (not shown) is formed on the device isolation layer buried in said active region for device isolation trench element isolation layer defining (A) (200) formed on the substrate.

Said substrate (100) single crystal silicon having a silicon substrate, silicon - germanium (Si-a Ge) or SOI (silicon provided on a non-insulation) comprising a substrate such as semiconductor, a plurality of conductive structures disposed active region (A) (A) (F) are divided into said active region and defining a field region. Said inner layer is field region (F) (200) (A) disposed adjacent active region disposed on the conductive structures are divided into each other.

Isolation layer (200) by natural environments trench isolation (shallow trench isolation, STI) formed on the substrate. For example, the substrate surface using a plasma etch process (100) and said element inside said trench to form an isolation trench for device isolation BPSG, USG or HDP oxide such as isolation material filled substrate.

In the case of a in the embodiment, said isolation layer (200) is at an angle with respect to the active region number 1 (x) (A) direction length than width angle are formed in the bar (bar) to only the isolated disposed thereon. The, inclined bar (bar) shape having a plurality of active region (A) are said isolation layer (200) separated by a constant interval disposed thereon.

Then, buried trench gate line shape along said number 1 direction (x) (190) and form. (A) active region through said recess forming substrate (100) defining active region isolation (A) (200) (x) number 1 to number a prescribed depth along a direction to have a stand-alone said gate trench (190) and form.

The, isolation region (200) on the upper surface of the upper surface of the active region layer is formed to be lower than level (A) (200) (A) from the surface of the active region are formed so as to have other. The, said active region (A) trench (190) are arranged on the bottom of the (100) surface of the gate region (G) and lower than said trench (190) adjacent to said substrate (100) placed to surface of a joint region (J) is divided into a substrate.

In the case of a in the embodiment, at an angle with respect to said number 1 direction (x) tilted from the bar (bar) with a active region (A) number 2 (y) a pair of spaced apart by a distance along the direction gate trench (190) engaging the are formed on the base. The, said gate region (G) is said trench (190) (G1, G2) disposed in the top and bottom gate region is divided into a number 1 and number 2 (J) said junction region is disposed in the active region (A) said central junction region (J1) number 1 and number 2 (J2) are divided into junction region is disposed at both ends.

Also 7a to 7c also reference surface, said gate region comprising a buried gate structure disposed on said number 1 (G) (BG) disposed along the gate line direction (x) (320) and a preliminary capping (330a) formed on the substrate.

For example, chemical vapor deposition (chemical vapor deposition, CVD) or thermal (thermal oxidation) process by said trench (190) and the bottom of the preliminary gate sidewall insulating film (310a) is formed, said preliminary gate insulating film (310a) or a sputtering (physical vapor deposition, PVD) by physical vapor deposition on said gate trench (190) is formed a preliminary gate conductive layer (not shown) buried in, said preliminary gate partially planarization process and back (etch-a back) to a stand-alone number by said gate trench (190) are formed on said number 1 (x) direction extending portion of the gate line (320) formed on the substrate.

The, said gate trench (190) and the inside wall of preliminary gate insulating film (310a) and covered with said gate line (320) pre-top surface of the gate insulating film (310a) and [cep clause (J) formed lower than the upper surface of the region.

Then, substrate (100) on said gate trench (190) is embedded in a combustible gas preliminary capping (330a) formed on the substrate. For example, said gate trench (190) is embedded in a combustible gas (not shown) is formed to have sufficient original capping gate trench (190) extends parallel to said gate trench (190) of said mask pattern (not shown) form said gate trench is planarized capping portion is original (190) the top of the buried said gate line (320) covering the pre-capping (330a) formed on the substrate.

Said preliminary gate insulating film (310) is formed of silicon, said gate line (320) doped polysilicon or metal and metal compound having high conductivity can be formed. In the case of a in the embodiment, said gate line (320) with the titanium nitride film (WN) or tungsten (TiN) barrier metal layer (321) and tungsten having high conductivity metal such as titanium or a gate having conductive film (322) JPO. Said pre-capping (330a) silicon nitride å. an insulating and superior corrosion resistance.

The reference also 8a to 8c also, said pre-capping (330a) stand-alone partially number gate line (320) covering the cap dizzily line (330) formed on the substrate.

For example, said gate trench mask pattern as an etch mask to etch-back process using the top number using a stand-alone, gate trench (190) number 1 in the interior of the direction as it extends along said gate lines (320) covering the upper surface of cap dizzily line (330) is formed on the substrate. In addition, gate trench (190) covering a bottom surface of the preliminary gate insulating film (310a) are exposed.

The, said pre-capping (330a) subsequent sealing line (400) (Ds) number by a height corresponding to the depth of a stand-alone substrate.

Alternatively, said preliminary gate insulating film (310a) is partially removed to wet etching using the photoresist to control said pre-capping (330a) stand-alone a number disapproval.

Also 9a to 9c also reference the, gate trench (190) is then through a gate insulating film (310a) number to a stand-alone said gate trench (190) unit separated into said cap dizzily line (330) and a gate line (320) and gate trench (190) only between the lower sidewall of the gate insulating film (310) formed on the substrate.

For example, cap dizzily line said gate trench mask pattern (330) is partially removed to the photoresist to control wet etching performed said cap dizzily line (330) equal to the upper surface of an upper preliminarily gate insulating film (310a) number can be a stand-alone.

The, said gate trench (190) of upper region is opens again and the bottom gate insulating space (310) surrounded by a gate line (320) and cap dizzily line (330) are buried.

The reference also 10a to 10c also, opens again gate trench (190) embedded in the insulating material in the upper area of sealing line (400) formed on the substrate.

For example, said substrate (100) on said gate trench (190) is embedded in the upper area of the shilling just enough (not shown) is formed having a thickness of, gate trench mask pattern is planarized to expose the upper surfaces of said shilling screen, (J) can be formed by back portion is of said junction region. The, said gate trench mask pattern number together 1308. wetting ability.

The, said sealing line (400) is said cap dizzily line (330) covering said gate trench (190) by contact the sides of said cap dizzily line (330) and the gate insulating film (310) has a predetermined width greater of the sample.

For example, said sealing line (400) employs a dizzily line (330) insulating material or materials (porosity) equal to said gap characteristic of a material can be improved. For example, said sealing line (400) silicon nitride or silicon nitride bromide å..

Also 11a to 11c also reference surface, said contact holes exposing the drain region (D) number 1 (H1) formed on the substrate.

Said buried gate structure (BG) and isolation (200) as an ion implantation mask by performing an ion implantation process using a source region (S) and drain regions (D) formed on the substrate. The, source/drain regions buried gate structure (BG) (S. D) with buried channel array transistor (buried channel array transistor, BCAT) layer 4 on a substrate. As one in the embodiment, said buried channel array transistor (BCAT) 1 is also shown in semiconductor device (1000) has the structure the same.

In said buried channel array transistor, number 1 (x) direction along the sealing line (330) and said exposed sealing line (330) between the isolation layer (200) source/drain regions (S, D) defined by minor axis length is 1 in a row.

The, number 2 (A) spaced apart by a distance along said active region is a pair of number 1 conductive lines (300) so as to intersect, the central part of the drain region (D) (A) said active region is formed at either end source region (S) formed therein.

Then, said substrate (100) are covered with the interlayer insulating layer is formed of said pluralities to discharge the drain region (D) and/or drain region that is adjacent the sealing line (D) (400) insulation layer (200) plug is partially etched by a stand-alone a number pattern (500) and number 1 (H1) contact hole formed on the substrate.

For example, chemical vapor deposition (CVD) process said substrate (100) through the upper surface and the front surface of said interlayer dielectric contact hole mask pattern formed on the substrate.

Said contact hole mask pattern represented by the drawing coarse 16a and 16b is also also are disclosed.

Also as shown in 16a and 16 also, said contact hole mask patterns are exposed (D) said drain region overlapping said upper conductive (M1) or said drain region (D) mask pattern for exposing the drain source region (S) surrounding said sidewall and said drain regions overlap with the interlayer dielectric (D) corresponding to a sidewall of the interlayer dielectric mask pattern for standard and its peripheral parts (M2) can be performed using source.

Said contact hole mask pattern (M1, M2) at the fifth step preliminary (D) defining said drain region to the drain region (D) by lower interlayer dielectric isolation layer (200) and sealing line (400) stand-alone partially number 2000.

In the case of a in the embodiment, said sealing line (400) (Ds) depth of the upper part of a stand-alone cap dizzily line number corresponding to the depth (D) said drain region (330) of the gate electrode (310) to such an extent that drain region (D) recess adjacent the top of the lamp housing.

The, upper part of the thin film transistor is said number 1 (D) sealing line contact hole (H1) and (400) insulation layer (200) space limited by having to be coated.

The, other in said interlayer dielectric such as silicon oxide film comprises a conductive layer such as polysilicon. Said interlayer dielectric (500) performed on the insulating film, formed by a subsequent process for electrically isolating the bit line contact interlayer insulating films serving as a substrate. In addition, conductive film formed on the gate conductive layer using the self-performed on the peripheral gate structure are disclosed. In this case, electromotor while forming said interlayer dielectric peripheral region gate conductive layer gate structure can be formed.

Also 12a to 12c also reference surface, said contact hole mask pattern (M1, M2) is embedded in a contact hole after said number 1 (H1) stand-alone a number sufficient to have said interlayer dielectric pattern (500) number 1 (not shown) is formed on the upper surface of conductive layer, second insulating said number 1 (H1) number 1 to number of contact holes by conductive layer remaining only stationary substrate. The, said number 1 (H1) contact number 1 (C1) both sides of contact holes formed on the substrate. For example, contact said number 1 (610) is an silicon and metal of direct contact (direct contact) polysilicon mixtures can be formed.

Then, contact said number 1 (610) with interlayer dielectric pattern (500) of number 2 are covered with the conductive layer (610a) and method of bit line mask (620a) sequentially to form. Said number 2 conductive film (610a) (Cu) having high conductivity such as copper or aluminum (Al) metallic material formed said bit line mask (640a) silicon, silicon nitride and silicon oxynitride comprising can be.

Then, said bit line mask (620a) and said number 2 (y) direction extending along the upper surface of number 1 direction (x) at regular intervals along the line having a shaped photoresist pattern (660) formed on the substrate. The, said photoresist pattern (660) said number 2 (y) arranged in a row along the direction to cover the drain layer (D) disposed thereon.

The reference also 13a to 13c also, said photoresist pattern (660) connected to the bit line mask using lithography process (620a), number 2 conductive film (610a) and said interlayer dielectric pattern (500) stand-alone partially number 2000.

The, said number 2 conductive film (610a) number 2 (y) direction extending along the bit line (610) said bit line mask formed (620a) is said bit line (610) number 2 direction extending along the top of the bit line mask (620) JPO.

In addition, said bit line (640) interlayer disposed (500) the remainder [...] a number said substrate (100) is of special number from said source region (S) (S) used as the mask for defining isolation layer (200) partially minor axis length is 1.

I.e., interlayer dielectric pattern (500) are laminated onto the bit line (610) and method of bit line mask (620) number 2 (y) arranged in a row along the direction (D) drain region covering the conductive line number 2 (600) is formed. Said drain junction layer (D) said part of the interlayer dielectric pattern (500) disposed to send a bit line contact number 1 (C1) (610) (D) are connected to the drain region electrically.

Selectively, said number 2 conductive lines (600) extending along the side of the bit line spacer (630) can be further more than that. The, if necessary, the interior of the contact hole said number 1 (H1) said spacer (630) (C1) (S) extending adjacent the source region contact number 1 billion can be electrical interference between number.

The reference also 14a to 14c also, said number 2 conductive lines (600) are formed (100) (not shown) is formed on said preliminary insulating layer, said bit line mask (620) a preliminary insulation planarization process to expose partly due to a stand-alone number to number 2 conductive lines (600) this standing space between filled with insulating film (700) formed on the substrate. Then, said insulating film (700) number to said source junction layer (S) stand-alone partially exposing the contact hole number 2 (H2) formed on the substrate.

The reference also 15a to 15c also, said number 2 (H2) is embedded in a contact hole (not shown) insulating said conductive layer to have a sufficient number 3 (700) is planarized said number 2 number 2 (H2) are formed on the contact hole on both sides of contact (C2) is formed, said number 2 connected with the charge storage part contact (C2) (800) and form. The, said source junction layer (S) connected to the charge storage unit (800) to 135. For example, said charge storage unit (800) at the bottom electrode, dielectric film consisting of a storage capacitor, said number 2 contact (C2) as the lower electrode of capacitor-coupled with each other.

Figure 17 shows a memory card including a memory element by the present invention also one in the embodiment representing configuration are disclosed.

17 also reference surface, in one embodiment of the present invention memory by card (2000) by the aforementioned is such as can be constructed using memory devices of the present invention in the embodiment.

For example, said memory card (2000) includes a plurality of memory devices capable of storing data from the external host (not shown) are arranged in a memory unit (2100) and said host memory unit is connected to the exchange of data between host number plower memory controller (2200) without using a tool.

Said memory unit (2100) is described using a plurality of dram memory device are arranged such that the 1 also host (2300) machine data for sparse subtrees. Said dram memory device disposed along said number match the capacity of the memory unit (2100) are determined and a storage capacity of, depending upon the capabilities of said memory card determined performance of said memory device.

Said memory controller (2200) host memory unit (2100) for performing data exchanges between the number it will be small [...] central processing device (2210), memory card (2000) said host interface to a host connected to a data exchange protocol (2220), said memory unit (2100) and a memory interface coupled to (2230), and said memory unit (2100) detected from the error correction code can be encoded data error detection and correction (2240) without using a tool. Selectively said central processing device (2110) operation of memory functioning as a memory device (e.g., SRAM) can be further arranged.

Said memory unit (2100) supported dram memory device includes a plurality of gate lines gate trench having a width equal to a width of a gate line with each other along a sealing line between adjacent cell can be minimize electrical interference. In addition, bit line contact with residual upper channel in bit line bridge the defective rate can be stably operated by greatly.

The, said memory device integrated and size reduction of the cell region of said operating stability despite driving stability can be improved. In addition, BCAT said dram memory element performs the memory card (2000) integrated also, storage capacity, can be simultaneously improving the stability of the system and operating speed.

In one embodiment of the present invention memory by element also Figure 18 shows a configuration representing information processing system are disclosed.

The reference also 18, in one embodiment of the present invention by information processing system (3000) also can be configured by employing semiconductor device 1 is shown. Said information processing system (3000) provided to combine a smart phone or mobile equipment such as notebook or desktop computer various such comprise traditional computer system.

For example, said information processing system (3000) memory system (3100) each system bus (3600) modem electrically connected (3200), central processing device (3300), ram (3400) and user interface (3500) can be a. Memory system (3100) is a central processing device (3300) processing by the data or the input data can be stored. Memory system (3100) memory unit (3140) to the memory controller (3120) can be a, 17 also described with reference to memory card (2000) can be on substantially the same configuration.

In particular, said memory unit (3140) BCAT structure being constituted by a mobile dram cell array region and an integration degree can be reflected to the input port. A conductive layer having a thickness which extended gate cell footprint despite sealing line stably by bit line contact structure in order memory unit (3140) can be a structure.

The manufacturing method described above such as semiconductor device and method for, junction region at the top of the gate trench in contact with the gate insulating layer made of an insulating material and a stand-alone (J) number sealing line (400) by replacing (A) junction region along the longitudinal direction of the active region (J) can be a conductive layer extending on a perimeter of said gate insulating regions.

The, gate line (320) to remain of dizzily line (330) and sealing line (400) being extended double, contact structure layer for sealing line in (400) and a cap dizzily line (330) includes a gate line (320) to function under the first as well as protection of the second contact structure for aligning the be. The, gate line (320) to reduce the data of the damage can be exposed.

As well as, said gate trench (190) at the top of the gate insulating film defining a junction region number 1 (J1) (310) number a bit line contact hole of semiconductor produced in a stand-alone due to bit line contact bridge to prevent the residual gate insulating film can be. The, integrated increased despite said semiconductor device and enables the reduction of line width (1000) can be stably maintain the of operating stability.

The present invention refers to an integrated circuit device or a semiconductor integrated circuit device or storage device communication device number tank industrial application such as a computer operation producing electronic number article number widely throughout useful employed can be used.

In a of the present invention preferred embodiment said through a browser but, if a corresponding splicing one skilled art poriae patent idea of the present invention within a range that the present invention not and area away from may be understand various modifying and changing it will rain.