Настройки

Укажите год
-

Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

Подробнее
-

Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

Подробнее

Форма поиска

Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
Ведите корректный номера.
Ведите корректный номера.
Ведите корректный номера.
Ведите корректный номера.
Укажите год
Укажите год

Применить Всего найдено 10899. Отображено 200.
31-12-2020 дата публикации

HALBLEITERVORRICHTUNG UND HERSTELLUNGSVERFAHREN

Номер: DE102020104370A1
Принадлежит:

Es werden ein Halbleiter-Bauelement und ein Verfahren bereitgestellt, mit dem eine Mehrzahl von Abstandshaltern in einem ersten Bereich und einem zweiten Bereich eines Substrats hergestellt wird. Die Mehrzahl von Abstandshaltern in dem ersten Bereich wird strukturiert, während die Mehrzahl von Abstandshaltern in dem zweiten Bereich geschützt wird, um die Eigenschaften der Abstandshalter in dem ersten Bereich von den Eigenschaften der Abstandshalter in dem zweiten Bereich zu trennen.

Подробнее
22-12-2016 дата публикации

Halbleiterstruktur mit lokaler zu einer Gate-Struktur selbstjustierten Zwischenverbindungsstruktur und statische Speicherzelle diese beinhaltend und Verfahren diese zu bilden

Номер: DE112012001220B4

Halbleiterstruktur, die eine Vielzahl von parallelen, ein leitfähiges Material beinhaltenden Strukturen aufweist, die parallele Seitenwände aufweisen und sich auf einem Halbleitersubstrat 8 befinden und ein konstantes Rastermaß in einer horizontalen Richtung senkrecht zu den parallelen Seitenwänden aufweisen, wobei: eine der Vielzahl von parallelen, ein leitfähiges Material beinhaltenden Strukturen (76, 80, 36, 38, 73) ein U-förmiges Gate-Dielektrikum 80 und einen metallischen Gate-Leiter-Elektroden-Anteil 76 beinhaltet, der ein metallisches Material aufweist; und eine weitere der Vielzahl von parallelen, ein leitfähiges Material beinhaltenden Strukturen eine Kontakt-Durchkontakt-Struktur 73 beinhaltet, die das metallische Material aufweist und mit einem von einem Source-Bereich und einem Drain-Bereich 34 eines Transistors leitfähig verbunden ist, der sich auf dem Halbleitersubstrat befindet; und ein Abstand zwischen einer Außenwand des U-förmigen Gate-Dielektrikums und einer Seitenwand ...

Подробнее
23-08-2007 дата публикации

Halbleitervorrichtung und Verfahren zur Herstellung derselben

Номер: DE102007007096A1
Принадлежит:

Eine Halbleitervorrichtung (100), die ein Hochspannungselement und ein Niederspannungselement beinhaltet, weist auf: ein Halbleitersubstrat (1) mit einem Hochspannungselementbereich (110), in dem das Hochspannungselement ausgebildet ist, und einem Niederspannungselementbereich (120), in dem das Niederspannungselement ausgebildet ist; eine erste LOCOS-Trennstruktur, die in dem Hochspannungselementbereich (110) angeordnet ist; und eine zweite LOCOS-Trennstruktur, die in dem Niederspannungselementbereich (120) angeordnet ist, wobei die erste LOCOS-Trennstruktur eine LOCOS-Oxidschicht (9a) beinhaltet, welche auf einer Oberfläche des Halbleitersubstrates (1) ausgebildet ist, und eine CVD-Oxidschicht (12), welche auf der LOCOS-Oxidschicht (9a) ausgebildet ist, und die zweite LOCOS-Trennstruktur eine LOCOS-Oxidschicht (9b) beinhaltet.

Подробнее
08-07-2010 дата публикации

Verfahren zur Bildung eines Source-Kontakts eines Flash-Speicherbauelements

Номер: DE102005022372B4

Verfahren zur Bildung eines Source-Kontakts eines Flash-Speicherbauelements mit den Schritten: Bilden einer ersten Zwischenschichtisolationsschicht auf einem Halbleitersubstrat, in welchem eine Verbindungsregion und eine Gate-Elektrodenstruktur für SSL einer Zellenregion gebildet werden; Strukturieren der ersten Zwischenschichtisolationsschicht, um ein Source-Kontaktloch zu bilden, durch welches die Verbindungsregion für die SSL auf einer Seite der Gate-Elektrodenstruktur für SSL exponiert wird; Bilden einer Schicht auf der gesamten Oberfläche, einschließlich des Source-Kontaktlochs; Ausführen eines Polierprozesses bis die erste Zwischenschichtisolationsschicht exponiert ist, um einen Source-Kontakt zu bilden; Bilden einer zweiten Zwischenschichtisolationsschicht auf der gesamten Oberfläche einschließlich des Source-Kontakts; Strukturieren der zweiten Zwischenschichtisolationsschicht, um die in einer peripheren Region des Halbleitersubstrats gebildeten ersten Verbindungsregionen zu exponieren ...

Подробнее
15-05-2008 дата публикации

Nichtflüchtige Speicherbauelementstruktur und Verfahren zur Herstellung derselben

Номер: DE102007050358A1
Принадлежит:

Die Erfindung bezieht sich auf eine nichtflüchtige Speicherbauelementstruktur mit einem Substrat (101), das einen Zellenbereich, einen Bereich für niedrige Spannung und einen Bereich für hohe Spannung beinhaltet, wobei ein Masseauswahltransistor (110), ein Kettenauswahltransistor (111) und ein Zellentransistor (112) in dem Zellenbereich ausgebildet sind und der Transistor (120) für niedrige Spannung in dem Bereich für niedrige Spannung ausgebildet ist und der Transistor (130) für hohe Spannung in dem Bereich für hohe Spannung ausgebildet ist, sowie auf ein Verfahren zur Herstellung einer derartigen Bauelementstruktur. Eine nichtflüchtige Speicherbauelementstruktur der Erfindung beinhaltet einen gemeinsamen Sourcekontakt (151) auf einem Störstellenbereich des Masseauswahltransistors und einen ersten Kontakt (153) für niedrige Spannung auf einem Störstellenbereich des Transistors für niedrige Spannung, wobei sich die Kontakte bis zu einer Höhe einer ersten Zwischenisolationsschicht (140) ...

Подробнее
25-04-2012 дата публикации

Semiconductor device structure and manufacturing method thereof

Номер: GB0002484862A
Принадлежит:

A semiconductor device structure and a manufacturing method thereof are provided. The method includes: forming gate lines (3005) on a semiconductor substrate (3000); forming gate sidewalls (3006) around the gate lines; forming source/drain regions (3007) embedded into the semiconductor substrate on both sides of the gate lines; forming conductive sidewalls (3009) around the gate sidewalls; and cutting off the gate lines, the gate sidewalls and the conductive sidewalls in predetermined regions. The cut gate lines form gate electrodes (3011) being electrically isolated, and the cut conductive sidewalls form the subjacent contact portions (3012) being electrically isolated. The semiconductor device structure is suitable for fabrication of the contact portion of the integrated circuit.

Подробнее
06-05-2003 дата публикации

Integrated circuit having interconnect to a substrate and method therefor

Номер: AU2002327714A1
Принадлежит:

Подробнее
31-05-2018 дата публикации

Field effect transistor (FET) structure with integrated gate connected diodes

Номер: AU2016355154A1

A structure having: a plurality of field effect transistors (FETs) connected between a common input and a common output, each one of the field effect transistors comprises: a source region, a drain region, and a gate electrode for controlling carriers through a channel region of a transistor region of the structure between the source region and the drain region; a plurality of diodes, each one of the diodes being associated with a corresponding one of the plurality of FETs, each one of the diodes having an electrode in Schottky contact with a diode region of the corresponding one of the FETs. The gate electrode and the diode electrode extend along parallel lines. The source region, the drain region, the channel region, and a diode region having therein the diode are disposed along a common line.

Подробнее
11-08-2017 дата публикации

SEMICONDUCTOR DEVICE AND A METHOD FOR FABRICATING THE SAME

Номер: CN0107039348A
Принадлежит:

Подробнее
02-12-2015 дата публикации

And a buried insulating layer-containing vertical through the conductive structure of the electronic device and method

Номер: CN0102169898B
Автор:
Принадлежит:

Подробнее
07-12-2016 дата публикации

Semiconductor device layout, memory device layout, and method of manufacturing semiconductor device

Номер: CN0106206567A
Автор: JHON JHY LIAW
Принадлежит:

Подробнее
04-09-2020 дата публикации

INTERNAL VIA WITH IMPROVED CONTACT FOR UPPER SEMICONDUCTOR LAYER OF 3D CIRCUIT

Номер: FR0003082050B1
Принадлежит:

Подробнее
25-01-2019 дата публикации

AN INTEGRATED CIRCUIT HAVING A SHARED CONTACT MASK

Номер: FR0003069369A1
Принадлежит:

Подробнее
19-10-2017 дата публикации

매립된 절연 층 및 그를 통해 연장하는 수직 도전 구조를 포함하는 전자 디바이스 및 이를 형성하는 공정

Номер: KR0101787352B1

... 전자 디바이스는 매립된 도전 영역, 매립된 도전 영역 위의 매립된 절연 층, 및 매립된 절연 층 위에 배치된 반도체 층을 포함할 수 있고, 반도체 층은 주 표면 및 대향 표면을 갖고, 매립된 도전 영역은 주 표면보다 대향 표면에 더 가깝게 배치된다. 전자 디바이스는 또한, 제 1 트랜지스터의 전류-운반 전극을 포함할 수 있고, 전류 운반 전극은 주 표면을 따라 배치되고, 매립된 도전 층으로부터 이격된다. 전자 디바이스는 매립된 절연 층을 통해 연장하는 수직 도전 구조를 또한 포함할 수 있고, 수직 도전 구조는 전류-운반 전극 및 매립된 도전 영역에 전기적으로 접속된다.

Подробнее
25-01-2007 дата публикации

METHOD FOR FABRICATION OF SEMICONDUCTOR DEVICE CAPABLE OF PROTECTING ATTACK BY WET CLEANING

Номер: KR0100673884B1
Автор:
Принадлежит:

Подробнее
05-04-2016 дата публикации

A METHOD FOR SELECTIVELY FORMING A SELF ALIGNED LOCAL INTERCONNECT TO GATE

Номер: KR0101609329B1
Автор: 슐츠 리차드 티.

... 반도체 디바이스 제조 공정은 하드 마스크를 사용하여 반도체 기판에 트랜지스터 게이트(102)를 형성하는 것을 포함한다. 하드 마스크(112)는 게이트 위 하나 이상의 선택된 영역들에서 선택적으로 제거된다. 선택된 영역들에서 하드 마스크의 제거는 트랜지스터보다 실질적으로 위에 있는 적어도 하나의 절연층을 통해 상부 금속층에 게이트가 연결될 수 있게 한다. 전도성 물질이 적어도 하나의 절연층을 통해 하나 이상의 트렌치들에 증착된다. 전도성 물질은 선택된 영역들 중 적어도 하나에서 게이트에 로컬 배선을 형성한다.

Подробнее
06-05-2005 дата публикации

Semiconductor device having a contact hole disposed on a gate electrode overlapped with an active region

Номер: KR0100487950B1
Автор:
Принадлежит:

Подробнее
11-04-2003 дата публикации

A method for forming gate spacer of self-aligned contact

Номер: KR0100380348B1
Автор:
Принадлежит:

Подробнее
17-04-2012 дата публикации

SEMICONDUCTOR DEVICE FOR REDUCING AN INCREASE OF CONTACT RESISTANCE AND A MANUFACTURING METHOD THEREOF

Номер: KR1020120036185A
Принадлежит:

PURPOSE: A semiconductor device and a manufacturing method thereof are provided to prevent process failure by including an etching stop pattern which covers source/drain regions under the upper surface of a metal gate electrode. CONSTITUTION: A metal gate electrode(163) is laminated by arranging a gate insulating film on a semiconductor substrate(100). Spacer structures are arranged on the semiconductor substrate. A source/drain region is formed within the semiconductor substrate. An etching stop pattern(141) comprises a sidewall part and a bottom part for covering the source/drain region. The sidewall part covers a part of a sidewall of the spacer structure by being extended from the bottom part. COPYRIGHT KIPO 2012 ...

Подробнее
24-05-2019 дата публикации

Номер: KR1020190056284A
Автор:
Принадлежит:

Подробнее
20-04-2016 дата публикации

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

Номер: KR1020160042529A
Принадлежит:

In a semiconductor device, a first gate structure having a first end portion is formed on a substrate. Provided is a second gate structure which is separated from the first gate structure, and has a second end portion diagonally facing the first end portion. A cross-connect pattern is disposed between the first and second gate structures while being in contact with sidewalls of the first and second gate structures, and electrically connects the first and second gate structures to each other. A first contact plug is provided to directly connect an upper portion of the first end portion of the first gate structure and a first upper sidewall of the cross-connect pattern. A second contact plug is provided to directly connect an upper portion of the second end portion of the second gate structure and a second upper sidewall of the cross-connect pattern. In the semiconductor device, a parasitic capacitance may decrease due to the cross-connect pattern. COPYRIGHT KIPO 2016 (AA) First region (BB ...

Подробнее
13-02-2019 дата публикации

양쪽 사이드들 상의 금속화가 있는 반도체 디바이스들에 대한 후면 콘택트 저항 감소

Номер: KR1020190015269A
Принадлежит:

MOBS(metallization on both sides)가 있는 반도체 디바이스들에 대한 후면 콘택트 저항 감소를 위한 기술들이 개시된다. 일부 실시예들에서, 본 명세서에서 설명되는 기술들은 후면 콘택트들을 이루는 것에 있어서 그렇지 않으면 존재할 낮은 콘택트 저항을 복구하는 방법들을 제공하고, 그렇게 함으로써 트랜지스터 성능을 저하시키는 기생 외부 저항을 감소시키거나 또는 제거한다. 일부 실시예들에서, 이러한 기술들은 후면 콘택트 트렌치들에서의 고도로 도핑된 결정질 반도체 재료의 에피택셜 퇴적을 추가하여 강화된 오믹 콘택트 특성들을 제공하는 것을 포함한다. 일부 경우들에서, 후면 S/D(source/drain) 에칭 정지 층은 (전면 처리 동안) 전사 웨이퍼 상에 형성되는 하나 이상의 트랜지스터의 대체 S/D 영역들 아래에 형성될 수 있어, 후면 콘택트 트렌치들이 형성될 때, 후면 S/D 에칭 정지 층은 S/D 재료의 일부 또는 전부를 소비하기 이전에 후면 콘택트 에칭 프로세스를 정지하는데 도움이 될 수 있다. 다른 실시예들이 설명 및/또는 개시될 수 있다.

Подробнее
23-05-2002 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Номер: KR20020038508A
Автор: KOGA HIROKI
Принадлежит:

PURPOSE: To provide a semiconductor device comprising a MOS element together with its manufacturing method wherein an oxide film or nitride film provided on the side surface of a gate electrode is prevented from becoming in overhanging state, and the MOS element is prevented from degrading in characteristics. CONSTITUTION: A polysilicon film 103, a high-melting-point metal film or high- melting-point metal silicide film 104, and an insulating film 105 are sequentially laminated on a gate insulating film 102 formed on a semiconductor substrate 101. The insulating film 105 and the high-melting-point metal or high-melting- point metal silicide film 104 are etched into a prescribed shape so that a thermal nitride film 106 is formed on the side surface of an upper-layer electrode 104. Then the polysilicon film 103 is etched with the cap layer 105, the upper-layer electrode 104, and the thermal nitride film 106 as a mask to provide a lower- layer electrode 103. A thermal oxide film 107 is formed ...

Подробнее
23-06-2016 дата публикации

반도체 장치 및 이의 제조 방법

Номер: KR1020160072476A
Автор: 송현승
Принадлежит:

... 굴곡진 바닥면을 갖는 소오스/드레인 컨택을 형성함으로써, 신뢰성 및 소자 성능을 개선할 수 있는 반도체 장치를 제공하는 것이다. 상기 반도체 장치는 서로 간에 이격되는 제1 활성 영역 및 제2 활성 영역, 상기 제1 활성 영역 및 상기 제2 활성 영역 상에, 상기 제1 활성 영역 및 상기 제2 활성 영역과 교차하는 게이트 전극, 상기 게이트 전극의 일측에 배치되고, 서로 간에 이격되는 제1 소오스/드레인 및 제2 소오스/드레인, 및 상기 제1 소오스/드레인 및 상기 제2 소오스/드레인 상에 각각 배치되는 제1 부분 및 제2 부분과, 상기 제1 부분과 상기 제2 부분을 서로 연결하는 연결 부분을 포함하는 컨택으로, 상기 제1 부분의 상면 및 상기 제2 부분의 상면은 상기 연결 부분의 상면과 동일 평면 상에 놓이고, 상기 제1 부분의 높이 및 상기 제2 부분의 높이는 상기 연결 부분의 높이와 다른 컨택을 포함한다.

Подробнее
20-12-2010 дата публикации

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, HAVING AN N CHANNEL TYPE MOS TRANSISTOR

Номер: KR1020100132937A
Принадлежит:

PURPOSE: A semiconductor integrated circuit device is provided to reduce a leakage current without destroying data. CONSTITUTION: The source electrode of a first P channel type metal oxide semiconductor transistor(MP102) is connected to a power line. The source electrode of the first N channel MOS transistor(MN102) is connected to the source line. The drain electrode of the first N channel MOS transistor is connected to the drain electrode of the first P channel type metal oxide semiconductor transistor. The source electrode of the second P channel type metal oxide semiconductor transistor is connected to the power line. The source electrode of the second N channel MOS transistor is connected to the source line. The drain electrode of the second N channel MOS transistor is connected to the drain electrode of the second P channel type metal oxide semiconductor transistor. The drain electrode of the second N channel MOS transistor is connected to the gate electrode of the first N channel ...

Подробнее
17-03-2023 дата публикации

에어 갭을 가지는 후면 유전체 층을 갖는 집적 회로 구조체

Номер: KR102511810B1

... 집적 회로(IC) 구조체는 게이트 구조체, 소스 에피택셜 구조체, 드레인 에피택셜 구조체, 전면 상호연결 구조체, 후면 유전체 층 및 후면 비아를 포함한다. 소스 에피택셜 구조체와 드레인 에피택셜 구조체는 제각기 게이트 구조체의 양측에 있다. 전면 상호연결 구조체는 소스 에피택셜 구조체의 전면 및 드레인 에피택셜 구조체의 전면 상에 있다. 후면 유전체 층은 소스 에피택셜 구조체의 후면 및 드레인 에피택셜 구조체의 후면 상에 있으며 내부에 에어 갭을 갖는다. 후면 비아는 후면 유전체 층을 관통하여 소스 에피택셜 구조체 및 드레인 에피택셜 구조체의 첫 번째 것까지 연장된다.

Подробнее
01-07-2019 дата публикации

Semiconductor devices and methods of fabricating the same

Номер: TW0201926505A
Принадлежит:

A method and structure for forming a via-first metal gate contact includes depositing a first dielectric layer over a substrate having a gate structure with a metal gate layer. An opening is formed within the first dielectric layer to expose a portion of the substrate, and a first metal layer is deposited within the opening. A second dielectric layer is deposited over the first dielectric layer and over the first metal layer. The first and second dielectric layers are etched to form a gate via opening. The gate via opening exposes the metal gate layer. A portion of the second dielectric layer is removed to form a contact opening that exposes the first metal layer. The gate via and contact openings merge to form a composite opening. A second metal layer is deposited within the composite opening, thus connecting the metal gate layer to the first metal layer.

Подробнее
01-03-2017 дата публикации

Semiconductor device and method for fabricating semiconductor device

Номер: TW0201709324A
Принадлежит:

A semiconductor device includes: a semiconductor substrate; a wiring layer provided on a front-surface side of the semiconductor substrate; a through-via that penetrates through the semiconductor substrate from a back-surface side of the semiconductor substrate and is coupled to a wire included in the wiring layer; and a stress relaxation part that protrudes toward a through-via side and is disposed on a section in the wire and coupled to the through-via, the stress relaxation part including at least one insulating portion containing an insulating material having a smaller thermal expansion coefficient than a material of the through-via.

Подробнее
01-06-2016 дата публикации

Technique for filling high aspect ratio, narrow structures with multiple metal layers and associated configurations

Номер: TW0201620053A
Принадлежит:

Embodiments of the present disclosure describe techniques for filling a high aspect ratio, narrow structure with multiple metal layers and associated configurations. In one embodiment, an apparatus includes a transistor structure comprising a semiconductor material, a dielectric material having a recess defined over the transistor structure, the recess having a height in a first direction, an electrode terminal disposed in the recess and coupled with the transistor structure, wherein a first portion of the electrode terminal comprises a first metal in direct contact with the transistor structure and a second portion of the electrode terminal comprises a second metal disposed on the first portion and wherein an interface between the first portion and the second portion is planar and extends across the recess in a second direction that is substantially perpendicular to the first direction. Other embodiments may be described and/or claimed.

Подробнее
01-07-2018 дата публикации

Transistor connected diodes and connected III-N devices and their methods of fabrication

Номер: TW0201824508A
Принадлежит:

A transistor connected diode structure is described. In an example, the transistor connected diode structure includes a group III-N semiconductor material disposed on substrate. A raised source structure and a raised drain structure are disposed on the group III-N semiconductor material. A mobility enhancement layer is disposed on the group III-N semiconductor material. A polarization charge inducing layer is disposed on the mobility enhancement layer, the polarization charge inducing layer having a first portion and a second portion separated by a gap. A gate dielectric layer disposed on the mobility enhancement layer in the gap. A first metal electrode having a first portion disposed on the raised drain structure, a second portion disposed above the second portion of the polarization charge inducing layer and a third portion disposed on the gate dielectric layer in the gap. A second metal electrode disposed on the raised source structure.

Подробнее
01-07-2021 дата публикации

Method for fabricating semiconductor device

Номер: TW202125705A
Принадлежит:

The structure of a semiconductor device with source/drain contact structures and via structures and a method of fabricating the semiconductor device are disclosed. A method for fabricating a semiconductor device includes forming a source/drain (S/D) region on a substrate, forming a S/D contact structure on the S/D region, and forming a via structure on the S/D contact structure. The forming of the via structure includes forming a via opening on the S/D contact structure, forming a non-metal passivation layer on sidewalls of the via opening, and depositing a via plug within the via opening in a bottom-up deposition process.

Подробнее
01-02-2021 дата публикации

Semiconductor device and method for fabricating the same

Номер: TW202105625A
Принадлежит:

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a semiconductor substrate, a plurality of first set conductive elements separately positioned above the semiconductor substrate, a plurality of first set supporting pillars respectively correspondingly positioned between an adjacent pairs of the plurality of first set conductive elements, and a plurality of spaces respectively correspondingly positioned adjacent to the plurality of first set supporting pillars.

Подробнее
01-08-2021 дата публикации

Semiconductor apparatus having stacked devices and method of manufacture thereof

Номер: TW202129845A
Принадлежит:

Aspects of the disclosure provide a semiconductor apparatus including a plurality of structures. A first one of the structures comprises a first stack of transistors that includes a first transistor formed on a substrate and a second transistor stacked on the first transistor along a Z direction substantially perpendicular to a substrate plane of the semiconductor apparatus. The first one of the structures further includes local interconnect structures. The first transistor is sandwiched between two of the local interconnect structures. The first one of the structures further includes vertical conductive structures substantially parallel to the Z direction. The vertical conductive structures are configured to provide at least power supplies for the first one of the structures by electrically coupling with the local interconnect structures. A height of one of the vertical conductive structures along the Z direction is at least a height of the first one of the structures.

Подробнее
16-07-2009 дата публикации

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Номер: WO000002009087846A1
Автор: TANAKA, Toshihiko
Принадлежит:

By combining a negative exposure mask of a wiring pattern with a positive resist, a reverse pattern is formed first and then a positive wiring pattern is formed by using the reverse pattern. Namely, a positive resist (107) applied over a semiconductor substrate (101) is pattern-exposed by using an exposure mask (108) having an opening in a region corresponding to the wiring pattern, and then a resist pattern (107a) is formed by removing the exposed portions through development and a wiring pattern (104a) is formed in a region corresponding to the opening of the resist pattern (107a). By this procedure, influence of a flare, which occurs during mask exposure, can be reduced, thereby forming a fine wiring pattern with high exposure tolerance.

Подробнее
15-09-2011 дата публикации

SEMICONDUCTOR APPARATUS AND MANUFACTURING METHOD OF THE SAME

Номер: WO2011111133A1
Автор: OIKAWA, Kota
Принадлежит:

A source/drain region (106) is formed at both sides of a gate electrode (103) on a semiconductor substrate (100). A shared contact has a lower level contact (113) that is connected to the source/drain region (106) and not connected to the gate electrode (103), and an upper level contact (118) connected to both the lower contact (113) and the gate electrode (103).

Подробнее
14-07-2011 дата публикации

SYSTEMS AND METHODS EMPLOYING A PHYSICALLY ASYMMETRIC SEMICONDUCTOR DEVICE HAVING SYMMETRICAL ELECTRICAL BEHAVIOR

Номер: WO2011084501A1
Принадлежит:

An integrated circuit device comprising a first elongate structure and a second elongate structure arranged parallel to each other and defining a space therebetween. The integrated circuit device also includes conductive structures distributed in the space between the first and second elongate structures. At least a first one of the conductive structures is placed closer to the first elongate structure than to the second elongate structure. At least a second one of the conductive structures is placed closer to the second elongate structure than to the first elongate structure.

Подробнее
26-10-2017 дата публикации

Semiconductor Device Including a Semiconductor Sheet Interconnecting a Source Region and a Drain Region

Номер: US20170309707A1
Принадлежит:

A semiconductor device includes a substrate, a first source/drain (S/D) region, a second S/D region, and a semiconductor sheet. The first S/D region is disposed on the substrate. The second S/D region is disposed above the first S/D region. The semiconductor sheet interconnects the first and second S/D regions and includes a plurality of turns. A method for fabricating the semiconductor device is also disclosed.

Подробнее
08-11-2012 дата публикации

Method of Forming Metal Gates and Metal Contacts in a Common Fill Process

Номер: US20120282765A1
Принадлежит: GLOBALFOUNDRIES INC.

The method described herein involves a method of forming metal gates and metal contacts in a common fill process. The method may involve forming a gate structure comprising a sacrificial gate electrode material, forming at least one conductive contact opening in a layer of insulating material positioned adjacent the gate structure, removing the sacrificial gate electrode material to thereby define a gate electrode opening, and performing a common deposition process to fill the conductive contact opening and the gate electrode opening with a conductive fill material.

Подробнее
22-09-2015 дата публикации

Integrated circuit having a contact etch stop layer and method of forming the same

Номер: US0009142462B2

A method of forming an integrated circuit structure includes providing a gate stack and a gate spacer on a sidewall of the gate stack. A contact etch stop layer (CESL) is formed overlying the gate spacer and the gate stack. The CESL includes a top portion over the gate stack, a bottom portion lower than the top portion, and a sidewall portion over a sidewall of the gate spacer. The top and bottom portions are spaced apart from each other by the sidewall portion. The sidewall portion has a thickness less than a thickness of the top portion or a thickness of the bottom portion.

Подробнее
18-03-2021 дата публикации

SEMICONDUCTOR DEVICE INCLUDING SOURCE/DRAIN CONTACT HAVING HEIGHT BELOW GATE STACK

Номер: US20210082903A1

A method is disclosed, including the following operations: arranging a first gate structure extending continuously above a first active region and a second active region of a substrate; arranging a first separation spacer disposed on the first gate structure to isolate an electronic signal transmitted through a first gate via and a second gate via that are disposed on the first gate structure, in which the first gate via and the second gate via are arranged above the first active region and the second active region respectively; and arranging a first local interconnect between the first active region and the second active region, in which the first local interconnect is electrically coupled to a first contact disposed on the first active region and a second contact disposed on the second active region.

Подробнее
13-07-2021 дата публикации

Method to form a 3D semiconductor device and structure

Номер: US0011063024B1

A method to form a 3D semiconductor device, the method including: providing a first level including first circuits, the first circuits including first transistors and first interconnection; preparing a second level including a silicon layer; forming second circuits over the second level, the second circuits including second transistors and second interconnection; transferring with bonding the second level on top of the first level; and then thinning the second level to a thickness of less than ten microns, where the bonding includes oxide to oxide bonds, and where the bonding includes metal to metal bonds.

Подробнее
20-07-2021 дата публикации

Passivation layer for integrated circuit structure and forming the same

Номер: US0011069562B1

A method includes forming metal lines over an interconnect structure that is formed above transistors; depositing a liner layer over the metal lines using a first high density plasma chemical vapor deposition (HDPCVD) process with a zero RF bias power depositing a first passivation layer over the liner layer using a second HDPCVD process with a non-zero RF bias power; and depositing a second passivation layer in contact with a top surface of the first passivation layer using a third HDPCVD process with a non-zero RF bias power.

Подробнее
20-05-1986 дата публикации

Method of making semiconductor integrated circuits having backside gettered with phosphorus

Номер: US0004589928A1
Принадлежит: AT&T Bell Laboratories

For achieving dense packing of MOS transistors at the top surface of a silicon semiconductor body, second level metallization including arsenic doped polysilicon contacts are used in conjunction with a phosphorus gettering step at a time when the top surface is sealed against the introduction of phosphorus by an undoped sacrificial glass layer, i.e., which is essentially free of phosphorus. The second level metallization is thereafter completed by coating the polysilicon with a high conductivity metal, such as aluminum. During the gettering, the polysilicon contacts are insulated from the first level metallization by a planarized glass layer doped with phosphorus to a concentration below the saturation level of phosphorus in the glass.

Подробнее
01-05-2003 дата публикации

Semiconductor device

Номер: US20030080429A1
Принадлежит:

A plurality of MOS type FET devices 14 and 16 are provided on a semiconductor substrate 12. A lower interlayer insulating film 20 is provided thereon. Each of through holes 22, which extends from each of gate electrodes 14c of the plural FET devices via source/drain regions 14b and 16a, is defined in the lower interlayer insulating film 20. A local wiring 24 is buried in the through hole 22 to connect each gate electrode 14c and the source/drain regions 14b and 16a. Further, an upper interlayer insulating film 26 is provided on the local wiring 24 and the lower interlayer insulating film 20. Upper electrode layers 28 are placed on the surface of the upper interlayer insulating film 26.

Подробнее
17-03-2022 дата публикации

Power Gating Cell Structure

Номер: US20220085005A1
Принадлежит:

A power gating cell on an integrated circuit is provided. The power gating cell includes: a central area; a peripheral area surrounding the central area; a first active region located in the central area, the first active region having a first width in a first direction corresponding to at least four fin structures extending in a second direction perpendicular to the first direction; and a plurality of second active regions located in the peripheral area, each second active region having a second width in the first direction corresponding to at least one and no more than three fin structures extending in the second direction.

Подробнее
24-03-2022 дата публикации

SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME

Номер: US20220093471A1

A semiconductor device structure, along with methods of forming such, are described. The structure includes a first and second gate electrode layers, and a dielectric feature disposed between the first and second gate electrode layers. The dielectric feature has a first surface. The structure further includes a first conductive layer disposed on the first gate electrode layer. The first conductive layer has a second surface. The structure further includes a second conductive layer disposed on the second electrode layer. The second conductive layer has a third surface, and the first, second, and third surfaces are coplanar. The structure further includes a third conductive layer disposed over the first conductive layer, a fourth conductive layer disposed over the second conductive layer, and a dielectric layer disposed on the first surface of the dielectric feature. The dielectric layer is disposed between the third conductive layer and the fourth conductive layer.

Подробнее
26-10-1999 дата публикации

Method of making thin film transistor with anodic oxidation

Номер: US0005972742A
Автор:
Принадлежит:

An improved method of forming insulated gate field effect transistors is described. In accordance with the method, gate electrodes are formed from metal such as aluminum together with wirings electrically connecting the gate electrodes. The gate electrodes are anodic oxidized by dipping them as an anode in an electrolyte to form an oxide of the metal covering them. Since the connecting wirings are covered with a suitable organic film before the anodizing, no aluminum oxide is formed thereon so that it is easy to remove the connecting wiring by usual etching.

Подробнее
19-11-1996 дата публикации

Method of forming electric circuit using anodic oxidation

Номер: US0005576225A
Автор:
Принадлежит:

An improved method of forming insulated gate field effect transistors is described. In accordance with the method, gate electrodes are formed from metal such as aluminum together with wirings electrically connecting the gate electrodes. The gate electrodes are anodic oxidized by dipping them as an anode in an electrolyte to form an oxide of the metal covering them. Since the connecting wirings are covered with a suitable organic film before the anodizing, no aluminum oxide is formed thereon so that it is easy to remove the connecting wiring by usual etching.

Подробнее
30-06-2016 дата публикации

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

Номер: US20160190128A1
Принадлежит:

A semiconductor device includes a fin type active pattern extended in a first direction and disposed on a substrate. A first gate electrode and a second gate electrode are disposed on the fin type active pattern. The first gate electrode and the second gate electrode are extended in a second direction crossing the first direction. A trench region is disposed in the fin type active pattern and between the first gate electrode and the second gate electrode. A source/drain region is disposed on a surface of the trench region. A source/drain contact is disposed on the source/drain region. The source/drain contact includes a first insulating layer disposed on the source/drain region and a metal oxide layer disposed on the first insulating layer.

Подробнее
30-06-2016 дата публикации

ELONGATED CONTACTS USING LITHO-FREEZE-LITHO-ETCH PROCESS

Номер: US20160190016A1
Принадлежит:

A process of forming an integrated circuit containing elongated contacts which connect to three active areas and/or MOS gates, and elongated contacts which connect to two active areas and/or MOS gates and directly connect to a first level interconnect, using a litho-freeze-litho-etch process for a contact etch mask. A process of forming an integrated circuit containing elongated contacts which connect to three active areas and/or MOS gates, and elongated contacts which connect to two active areas and/or MOS gates and directly connect to a first level interconnect, using a litho-freeze-litho-etch process for a first level interconnect trench etch mask. A process of forming the integrated circuit using a litho-freeze-litho-etch process for a contact etch mask and a litho-freeze-litho-etch process for a first level interconnect trench etch mask.

Подробнее
06-09-2018 дата публикации

INTEGRATED CIRCUIT DEVICE

Номер: US20180254246A1
Принадлежит:

An integrated circuit device includes an insulating film on a substrate, a lower wiring layer penetrating at least a portion of the insulating film, the lower wiring layer including a first metal, a lower conductive barrier film surrounding a bottom surface and a sidewall of the lower wiring layer, the lower conductive barrier film including a second metal different from the first metal, a first metal silicide capping layer covering a top surface of the lower wiring layer, the first metal silicide capping layer including the first metal, and a second metal silicide capping layer contacting the first metal silicide capping layer and disposed on the lower conductive barrier film, the second metal silicide capping layer including the second metal.

Подробнее
22-11-2005 дата публикации

Gate stack structure

Номер: US0006967408B1
Автор: Kei-Yu Ko, KO KEI-YU

The present invention relates to gate stack structure that is fabricated by a process for selectively plasma etching a structure upon a semiconductor substrate to form a designated topographical structure thereon utilizing an undoped silicon dioxide layer as an etch stop. In one embodiment, a substantially undoped silicon dioxide layer is formed upon a layer of semiconductor material. A doped silicon dioxide layer is then formed upon said undoped silicon dioxide layer. The doped silicon dioxide layer is etched to create the topographical structure. The etch has a material removal rate that is at least 10 times higher for doped silicon dioxide than for undoped silicon dioxide or the semiconductor material. One application of the inventive process includes selectively plasma etching a multilayer structure to form a self-aligned contact between adjacent gate stacks and a novel gate structure resulting therefrom. In the application, a multilayer structure is first formed comprising layers of ...

Подробнее
03-11-2009 дата публикации

Semiconductor device having self-aligned contact

Номер: US0007612433B2

A method of manufacturing semiconductor devices having self-aligned contacts is provided. Multiple isolation structures are formed on the substrate to define an active area. Multiple gate structures are formed on the substrate. Multiple doped areas are formed in the substrate beside each gate structure. Multiple first spacers are formed on the sidewalls of each of the gate structure. Multiple second spacers are formed on the sidewalls of each of the isolation structure. A dielectric layer is formed on the substrate. Then, a self-aligned process is performed to form multiple contact openings in the dielectric layer between the gate structures. The conductive material is filled in the contact openings.

Подробнее
09-06-2016 дата публикации

SEMICONDUCTOR APPARATUS

Номер: US20160163698A1
Принадлежит:

A semiconductor apparatus includes a first area, a first transistor being formed in two or more divided areas of the first area, and a second area, a second transistor being formed in two or more divided areas of the second area. The number of areas of the second area is greater than the number of areas of the first area, the divided areas of the first area and the second area are alternately arranged, and the gate pad of the first transistor and the gate pad of the second transistor are formed in the second area.

Подробнее
11-10-2018 дата публикации

Low-Resistance Contact Plugs and Method Forming Same

Номер: US20180294184A1
Принадлежит:

A method includes forming a first and a second contact opening to reveal a first and a second source/drain region, respectively, forming a mask layer having a first and a second portion in the first and the second contact openings, respectively, forming a first and a second sacrificial ILD in the first and the second contact openings, respectively, removing the first sacrificial ILD from the first contact opening, filling a filler in the first contact opening, and etching the second sacrificial ILD. The filler protects the first portion of the mask layer from being etched. An ILD is formed in the second contact opening and on the second portion of the mask layer. The filler and the first portion of the mask layer are removed using a wet etch to reveal the first contact opening. A contact plug is formed in the first contact opening.

Подробнее
15-03-2007 дата публикации

Power semiconductor device and method therefor

Номер: US2007057289A1
Принадлежит:

A power transistor includes a plurality of transistor cells. Each transistor cell has a first electrode coupled to a first electrode interconnection region overlying a first major surface, a control electrode coupled to a control electrode interconnection region overlying the first major surface, and a second electrode coupled to a second electrode interconnection region overlying a second major surface. Each transistor cell has an approximately constant doping concentration in the channel region. A dielectric platform is used as an edge termination of an epitaxial layer to maintain substantially planar equipotential lines therein. The power transistor finds particular utility in radio frequency applications operating at a frequency greater than 500 megahertz and dissipating more than 5 watts of power. The semiconductor die and package are designed so that the power transistor can efficiently operate under such severe conditions.

Подробнее
02-01-2020 дата публикации

LOCAL INTERCONNECT FOR GROUP IV SOURCE/DRAIN REGIONS

Номер: US20200006229A1
Принадлежит: INTEL CORPORATION

Techniques are disclosed for forming transistor devices having reduced interfacial resistance in a local interconnect. The local interconnect can be a material having similar composition to that of the source/drain material. That composition can be a metal alloy of a group IV element such as nickel germanide. The local interconnect of the semiconductor integrated circuit can function in the absence of barrier and liner layers. The devices can be used on MOS transistors including PMOS transistors.

Подробнее
13-02-2020 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20200051913A1
Принадлежит:

Reliability of a semiconductor device is improved. The semiconductor device includes a silicon pattern for a fuse element, a metal silicide layer formed on an upper surface and a side surface of the silicon pattern, a gate electrode for MISFET, and a metal silicide layer formed on an upper surface of the gate electrode. The height from the lower surface of the silicon pattern to the lower end of the metal silicide layer is lower than the height from the lower surface of the gate electrode to the lower end of the metal silicide layer.

Подробнее
01-09-2016 дата публикации

Layout Architecture for Performance Improvement

Номер: US20160254194A1
Принадлежит:

An integrated circuit is provided. The integrated circuit includes a first contact disposed over a first source/drain region, a second contact disposed over a second source/drain region, a polysilicon disposed over a gate, the polysilicon interposed between the first contact and the second contact, a first polysilicon contact bridging the polysilicon and the first contact within an active region, and an output structure electrically coupled to the first polysilicon contact.

Подробнее
13-02-2020 дата публикации

MINIMIZE MIDDLE-OF-LINE CONTACT LINE SHORTS

Номер: US20200051866A1
Принадлежит:

Semiconductor structures and methods of forming such structures are disclosed. In an embodiment, the semiconductor structure comprises a substrate, a dielectric layer, and a plurality of gates, including a first gate and a pair of adjacent gates. The method comprises forming gate caps on the adjacent gates, including etching portions of the gate electrodes in the adjacent gates to recess the gate electrodes therein, and forming the caps above the recessed gate electrodes. Conductive metal trenches are formed in the dielectric layer, on the sides of the first gate; and after forming the trenches, a contact is formed over the gate electrode of the first gate and over and on one of the conductive trenches. In embodiments, the contact is a gate contact, and in other embodiments, the contact is a non-gate contact.

Подробнее
01-09-2020 дата публикации

Metal rail conductors for non-planar semiconductor devices

Номер: US0010763365B2

The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices. This isolation prevents electrical connection between the one or ...

Подробнее
19-06-2014 дата публикации

Coarse Grid Design Methods and Structures

Номер: US20140167183A1
Принадлежит: Tela Innovations, Inc.

A layer of a mask material is deposited on a substrate. A beam of energy is scanned across the mask material in a rasterized linear pattern and in accordance with a scan pitch that is based on a pitch of conductive structure segments to be formed on the substrate. The beam of energy is defined to transform the mask material upon which the beam of energy is incident into a removable state. During scanning the beam of energy across the mask material, the beam of energy is turned on at locations where a conductive structure is to be formed on the substrate, and the beam of energy is turned off at locations where a conductive structure is not to be formed on the substrate.

Подробнее
12-03-2020 дата публикации

FABRICATION OF VERTICAL FIN FIELD EFFECT TRANSISTORS HAVING TOP AIR SPACERS AND A SELF-ALIGNED TOP JUNCTION

Номер: US20200083217A1
Принадлежит:

A method of fabricating adjacent vertical fins with top source/drains having an air spacer and a self-aligned top junction, including, forming two or more vertical fins on a bottom source/drain, forming a top source/drain on each of the two or more vertical fins, wherein the top source/drains are formed to a size that leaves a gap between the adjacent vertical fins, and forming a source/drain liner on the top source/drains, where the source/drain liner occludes the gap between adjacent top source/drains to form a void space between adjacent vertical fins.

Подробнее
27-08-2013 дата публикации

Through wafer vias and method of making same

Номер: US0008518787B2

A method of forming and structure for through wafer vias and signal transmission lines formed of through wafer vias. The method of forming through wafer vias includes forming an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via through a semiconductor substrate having a top surface and an opposite bottom surface, each through wafer via of the array of through wafer vias extending from the top surface of the substrate to the bottom surface of the substrate.

Подробнее
14-01-2020 дата публикации

Integrated circuit with conductive line having line-ends

Номер: US0010535556B2

A semiconductor device is disclosed, including a plurality of conductive features disposed over a substrate. A dielectric layer separates the conductive features. A conductive line is provided, connecting a subset of the conductive features. The conductive line includes a line-like portion and a line-end portion.

Подробнее
21-02-2019 дата публикации

SELF ALIGNED ACTIVE TRENCH CONTACT

Номер: US20190057969A1
Принадлежит:

An integrated circuit and method includes self-aligned contacts. A gapfill dielectric layer fills spaces between sidewalls of adjacent MOS gates. The gapfill dielectric layer is planarized down to tops of gate structures. A contact pattern is formed that exposes an area for multiple self-aligned contacts. The area overlaps adjacent instances of the gate structures. The gapfill dielectric layer is removed from the area. A contact metal layer is formed in the areas where the gapfill dielectric material has been removed. The contact metal abuts the sidewalls along the height of the sidewalls. The contact metal is planarized down to the tops of the gate structures, forming the self-aligned contacts.

Подробнее
23-08-2016 дата публикации

Methods of manufacturing transistors including forming a depression in a surface of a covering of resist material

Номер: US0009425193B2

A method of manufacturing a transistor comprising: providing a substrate, a region of semiconductive material supported by the substrate, and a region of electrically conductive material supported by the region of semiconductive material; forming at least one layer of resist material over said regions to form a covering of resist material over said regions; forming a depression in a surface of the covering of resist material, said depression extending over a first portion of said region of conductive material, said first portion separating a second portion of the conductive region from a third portion of the conductive region; removing resist material located under said depression so as to form a window, through said covering, exposing said first portion of the electrically conductive region; removing said first portion to expose a connecting portion of the region of semiconductive material, said connecting portion connecting the second portion to the third portion of the conductive region ...

Подробнее
28-02-2019 дата публикации

Buried Metal Track and Methods Forming Same

Номер: US20190067290A1
Принадлежит:

An integrated circuit includes a semiconductor substrate, an isolation region extending into, and overlying a bulk portion of, the semiconductor substrate, a buried conductive track comprising a portion in the isolation region, and a transistor having a source/drain region and a gate electrode. The source/drain region or the gate electrode is connected to the buried conductive track.

Подробнее
29-01-2019 дата публикации

Integrated circuit structure incorporating stacked field effect transistors

Номер: US0010192819B1
Принадлежит: GLOBALFOUNDRIES INC., GLOBALFOUNDRIES INC

Disclosed are integrated circuit (IC) structure embodiments that incorporate a stacked pair of field effect transistors (FETs) (e.g., gate-all-around FETs) and metal components that enable power and/or signal connections to source/drain regions of those FETs. Specifically, the IC includes a first FET and a second FET stacked on and sharing a gate with the first FET. The metal components include an embedded contact in a source/drain region of the first FET and connected to a wire (e.g., a power or signal wire). The wire can be a front end of the line (FEOL) wire positioned laterally adjacent to the source/drain region and the embedded contact can extend laterally from the source/drain region to the FEOL wire. Alternatively, the wire can be a back end of the line (BEOL) wire and an insulated contact can extend vertically from the embedded contact through the second FET to the BEOL wire.

Подробнее
05-02-2019 дата публикации

Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one chamfer short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective tip-to-side short, chamfer short, and via open test areas

Номер: US0010199287B1
Принадлежит: PDF Solutions, Inc., PDF SOLUTIONS INC

A method for processing a semiconductor wafer uses non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one chamfer short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective tip-to-side short, chamfer short, and via open test areas.

Подробнее
05-02-2019 дата публикации

Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one side-to-side short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective side-to-side short, corner short, and via open test areas

Номер: US0010199288B1
Принадлежит: PDF Solutions, Inc., PDF SOLUTIONS INC

A method for processing a semiconductor wafer uses non-contact electrical measurements indicative of at least one side-to-side short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective side-to-side short, corner short, and via open test areas.

Подробнее
22-10-2015 дата публикации

METHODS FOR FABRICATING INTEGRATED CIRCUTIS AND COMPONENTS THEREOF

Номер: US20150303117A1
Автор: Ming Zhu, Yiang Aun Nga
Принадлежит: GLOBALFOUNDRIES Singapore Pte. Ltd.

Methods for fabricating integrated circuits and components thereof are provided. In accordance with an exemplary embodiment, a method for a fabricating a semiconductor device is provided. The method includes providing a partially fabricated semiconductor device and forming silicide regions outside of the first and second gates. The partially fabricated semiconductor device includes a semiconductor substrate, a first gate formed over the semiconductor substrate, and a second gate formed over the semiconductor substrate and spaced apart from the first gate. Silicide formation between the first gate and the second gate is inhibited.

Подробнее
29-12-2016 дата публикации

SEMICONDUCTOR DEVICE PRODUCTION METHOD AND SEMICONDUCTOR DEVICE

Номер: US20160380080A1

A semiconductor device production method includes a first step of forming a planar silicon layer on a silicon substrate and forming first and second pillar-shaped silicon layers on the planar silicon layer; a second step of forming a gate insulating film around the first and second pillar-shaped silicon layers, forming a metal film and a polysilicon film around the gate insulating film, controlling a thickness of the polysilicon film to be smaller than a half of a distance between the first and second pillar-shaped silicon layers, depositing a resist, exposing the polysilicon film on side walls of upper portions of the first and second pillar-shaped semiconductor layers, etching-away the exposed polysilicon film, stripping the third resist, and etching-away the metal film; and a third step of forming a resist for forming a gate line and performing anisotropic etching to form a gate line and first and second gate electrodes.

Подробнее
30-05-2019 дата публикации

ETCHING METHOD AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME

Номер: US20190164774A1
Принадлежит:

An etching method includes providing a plasma of a first treatment gas to an etching-object to form a deposition layer on the etching-object, the first treatment gas including a fluorocarbon gas and an inert gas, and the etching-object including a first region including silicon oxide and a second region including silicon nitride, providing a plasma of an inert gas to the etching-object having the deposition layer thereon to activate an etching reaction of the silicon oxide, wherein a negative direct current voltage is applied to an opposing part that is spaced apart from the etching-object so as to face an etching surface of the etching-object, the opposing part including silicon, and subsequently, providing a plasma of a second treatment gas to remove an etching reaction product, the second treatment gas including an inert gas and an oxygen-containing gas.

Подробнее
06-04-2017 дата публикации

Integrated Circuit With Conductive Line Having Line-Ends

Номер: US20170098574A1
Принадлежит:

A semiconductor device is disclosed, including a plurality of conductive features disposed over a substrate. A dielectric layer separates the conductive features. A conductive line is provided, connecting a subset of the conductive features. The conductive line includes a line-like portion and a line-end portion.

Подробнее
10-12-2020 дата публикации

1D VERTICAL EDGE BLOCKING (VEB) VIA AND PLUG

Номер: US20200388534A1
Принадлежит:

Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment a semiconductor device comprises a first interlayer dielectric (ILD), a plurality of source/drain (S/D) contacts in the first ILD, a plurality of gate contacts in the first ILD, wherein the gate contacts and the S/D contacts are arranged in an alternating pattern, and wherein top surfaces of the gate contacts are below top surfaces of the S/D contacts so that a channel defined by sidewall surfaces of the first ILD is positioned over each of the gate contacts, mask layer partially filling a first channel over a first gate contact, and a fill metal filling a second channel over a second gate contact that is adjacent to the first gate contact.

Подробнее
27-04-2021 дата публикации

Source/drain contact depth control

Номер: US0010991796B2

A dielectric fill layer within source/drain metallization trenches limits the depth of an inlaid metallization layer over isolation regions of a semiconductor device. The modified geometry decreases parasitic capacitance as well as the propensity for electrical short circuits between the source/drain metallization and adjacent conductive structures, which improves device reliability and performance.

Подробнее
29-05-2018 дата публикации

Vertically aligned nanowire channels with source/drain interconnects for nanosheet transistors

Номер: US0009985138B2

A nano-sheet semiconductor structure and a method for fabricating the same. The nano-sheet structure includes a substrate and at least one alternating stack of semiconductor material layers and metal gate material layers. The nano-sheet semiconductor structure further comprises a source region and a drain region. A first plurality of epitaxially grown interconnects contacts the source region and the semiconductor layers in the alternating stack. A second plurality of epitaxially grown interconnects contacts the drain region and the semiconductor layers in the alternating stack. The method includes removing a portion of alternating semiconductor layers and metal gate material layers. A first plurality of interconnects is epitaxially grown between and in contact with the semiconductor layers and the source region. A second plurality of interconnects is epitaxially grown between and in contact with the semiconductor layers and the drain region.

Подробнее
04-11-2021 дата публикации

Contact Conductive Feature Formation and Structure

Номер: US20210343590A1
Принадлежит:

Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back by a wet etching process. After etching back the portion of the barrier layer, an underlying dielectric welding layer is exposed. A conductive material is formed along the barrier layer.

Подробнее
01-03-2018 дата публикации

VERTICAL FUSE STRUCTURES

Номер: US20180061757A1
Принадлежит:

Semiconductor devices and methods are provided in which vertical fuse devices are integrally formed with FINFET (Fin Field Effect Transistor) devices, wherein the vertical fuse devices are formed as part of a process flow for fabricating the FINFET devices. For example, a semiconductor device comprises first and second vertical semiconductor fins, a vertical fuse device, and a FINFET device. The vertical fuse device comprises a metal fuse element formed over a portion of the first vertical semiconductor fin, and the FINFET device comprises a metal gate electrode formed over a portion of the second vertical semiconductor fin. The metal fuse element and the metal gate electrode are concurrently formed as part of a replacement metal gate process flow.

Подробнее
23-09-2021 дата публикации

Conductive Feature Formation and Structure

Номер: US20210296168A1
Принадлежит:

Generally, examples are provided relating to conductive features that include a barrier layer, and to methods thereof. In an embodiment, a metal layer is deposited in an opening through a dielectric layer(s) to a source/drain region. The metal layer is along the source/drain region and along a sidewall of the dielectric layer(s) that at least partially defines the opening. The metal layer is nitrided, which includes performing a multiple plasma process that includes at least one directional-dependent plasma process. A portion of the metal layer remains un-nitrided by the multiple plasma process. A silicide region is formed, which includes reacting the un-nitrided portion of the metal layer with a portion of the source/drain region. A conductive material is disposed in the opening on the nitrided portions of the metal layer.

Подробнее
21-02-2017 дата публикации

Non-volatile memory device and method of fabricating the same

Номер: US0009577059B2
Принадлежит: SK Hynix Inc., SK HYNIX INC, SK hynix Inc.

A non-volatile memory device may include a control plug formed over a substrate. A floating gate may be formed over the substrate, the floating gate surrounding the control plug and being separated from the control plug by a gap. A first charge blocking layer may be formed over sidewalls of the floating gate to fill the gap.

Подробнее
10-04-2018 дата публикации

Series resistor over drain region in high voltage device

Номер: US0009941268B2

Some embodiments relate to a semiconductor device. The semiconductor device includes a drain region and a channel region surrounding the drain region. A source region surrounds the channel region such that the channel region separates the drain region from the source region. A gate electrode is arranged over the channel region and has an inner edge proximate to the drain. A resistor structure, which is made up of a curved or polygonal path of resistive material, is arranged over the drain and is coupled to the drain. The resistor structure is perimeterally bounded by the inner edge of the gate electrode.

Подробнее
22-06-2017 дата публикации

INTEGRATING A PLANAR FIELD EFFECT TRANSISTOR (FET) WITH A VERTICAL FET

Номер: US20170179116A1
Принадлежит:

One embodiment provides a method of integrating a planar field-effect transistor (FET) with a vertical FET. The method comprises masking and etching a semiconductor of the vertical FET to form a fin, and providing additional masking, additional etching, doping and depositions to isolate a bottom source/drain (S/D) region. A dielectric is formed on the bottom S/D region to form a spacer. The method further comprises depositing gate metals, etching a vertical gate for the vertical FET and a planar gate for the planar FET using a shared gate mask, depositing dielectric, etching the dielectric to expose one or more portions of the fin, growing epitaxy on a top S/D region, masking and etching S/D contact openings for the bottom S/D region, forming silicide regions in S/D regions, depositing contact metal in the silicide regions to form contacts, and planarizing the contacts.

Подробнее
16-02-2012 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20120037965A1
Принадлежит: RENESAS ELECTRONICS CORPORATION

In an LCD driver, in a high voltage resistant MISFET, end portions of a gate electrode run onto electric field relaxing insulation regions. Wires to become source wires or drain wires are formed on an interlayer insulation film of the first layer over the high voltage resistant MISFET. At this moment, when a distance from an interface between a semiconductor substrate and a gate insulation film to an upper portion of the gate electrode is defined as a, and a distance from the upper portion of the gate electrode to an upper portion of the interlayer insulation film on which the wires are formed is defined as b, a relation of a>b is established. In such a high voltage resistant MISFET structured in this manner, the wires are arranged so as not to be overlapped planarly with the gate electrode of the high voltage resistant MISFET.

Подробнее
16-05-2019 дата публикации

Integrated Circuit with Sidewall Spacers for Gate Stacks

Номер: US20190148501A1
Принадлежит:

Various examples of an integrated circuit with a sidewall spacer and a technique for forming an integrated circuit with such a spacer are disclosed herein. In some examples, the method includes receiving a workpiece that includes a substrate and a gate stack disposed upon the substrate. A spacer is formed on a side surface of the gate stack that includes a spacer layer with a low-k dielectric material. A source/drain region is formed in the substrate; and a source/drain contact is formed coupled to the source/drain region such that the spacer layer of the spacer is disposed between the source/drain contact and the gate stack.

Подробнее
10-08-2021 дата публикации

Trench contact structures for advanced integrated circuit structure fabrication

Номер: US0011088261B2
Принадлежит: Intel Corporation, INTEL CORP

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. A gate dielectric layer is over the top of the fin and laterally adjacent the sidewalls of the fin. A gate electrode is over the gate dielectric layer over the top of the fin and laterally adjacent the sidewalls of the fin. First and second semiconductor source or drain regions are adjacent the first and second sides of the gate electrode, respectively. First and second trench contact structures are over the first and second semiconductor source or drain regions, respectively, the first and second trench contact structures both comprising a U-shaped metal layer and a T-shaped metal layer on and over the entirety of the U-shaped metal layer.

Подробнее
29-07-2014 дата публикации

Semiconductor device including contact structure, method of fabricating the same, and electronic system including the same

Номер: US8791510B2
Автор: LEE YOUNG-KYU

A semiconductor device includes a gate structure on a semiconductor substrate, an impurity region at a side of the gate structure and the impurity region is within the semiconductor substrate, an interlayer insulating layer covering the gate structure and the impurity region, a contact structure extending through the interlayer insulating layer and connected to the impurity region, and an insulating region. The contact structure includes a first contact structure that has a side surface surrounded by the interlayer insulating layer and a second contact structure that has a side surface surrounded by the impurity region. The insulating region is under the second contact structure.

Подробнее
17-08-2023 дата публикации

DUAL METAL CAPPED VIA CONTACT STRUCTURES FOR SEMICONDUCTOR DEVICES

Номер: US20230261070A1

The structure of a semiconductor device with dual metal capped via contact structures and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a source/drain (S/D) region and a gate structure on a fin structure, forming S/D and gate contact structures on the S/D region and the gate structure, respectively, forming first and second via contact structures on the S/D and gate contact structures, respectively, and forming first and second interconnect structures on the first and second via contact structures, respectively. The forming of the first and second via contact structures includes forming a first via contact plug interposed between first top and bottom metal capping layers and a second via contact plug interposed between second top and bottom metal capping layers, respectively.

Подробнее
09-02-2012 дата публикации

N-well/p-well strap structures

Номер: US20120032276A1
Принадлежит: Altera Corp

Embodiments of N-well or P-well strap structures are disclosed with lower space requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers.

Подробнее
29-03-2012 дата публикации

High-voltage tolerant voltage regulator

Номер: US20120077551A1
Принадлежит: Skyworks Solutions Inc

Circuits and methodologies related to high-voltage tolerant regulators are disclosed. In some implementations, a voltage regulator can be configured to be capable of being in a regulating state and a bypass state. In the regulating state, an input voltage greater than a selected value can be regulated so as to yield a desired output voltage such as a substantially constant voltage. In the bypass state, an input voltage at or less than the selected value can be regulated so as to yield an output voltage that substantially tracks the input voltage. Such a capability of switching between two modes can provide advantageous features such as reducing the likelihood of damage in a powered circuit due to high input voltage, and extending the operating duration of a power source such as a rechargeable battery. Also disclosed are examples of how the foregoing features can be implemented in different products and methods of operation and fabrication.

Подробнее
10-05-2012 дата публикации

Metal-insulator-semiconductor tunneling contacts

Номер: US20120115330A1
Принадлежит: Individual

A contact to a source or drain region. The contact has a conductive material, but that conductive material is separated from the source or drain region by an insulator.

Подробнее
17-05-2012 дата публикации

3d semiconductor devices and methods of fabricating same

Номер: US20120119287A1
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A three dimensional (3D) semiconductor device includes; a vertical channel extending from a lower end proximate a substrate to an upper end and connecting a plurality of memory cells, and a cell array comprising the plurality of cells, wherein the cell array is arranged in a gate stack of layers having a stair-stepped structure disposed on the substrate. The gate stack includes a lower layer including a lower select line coupled to a lower non-memory transistor proximate the lower end, upper layers including conductive lines respectively coupled to an upper non-memory transistor proximate the upper end and connected as a single conductive piece to form an upper select line, and intermediate layers respectively including a word line and coupled to a cell transistor, wherein the intermediate layers are disposed between the lower select line and the upper select line.

Подробнее
17-05-2012 дата публикации

Metal gate transistor, integrated circuits, systems, and fabrication methods thereof

Номер: US20120119306A1

A method of forming an integrated circuit structure includes providing a gate strip in an inter-layer dielectric (ILD) layer. The gate strip comprises a metal gate electrode over a high-k gate dielectric. An electrical transmission structure is formed over the gate strip and a conductive strip is formed over the electrical transmission structure. The conductive strip has a width greater than a width of the gate strip. A contact plug is formed above the conductive strip and surrounded by an additional ILD layer.

Подробнее
05-07-2012 дата публикации

field effect transistor having ohmic body contact(s), an integrated circuit structure incorporating stacked field effect transistors with such ohmic body contacts and associated methods

Номер: US20120168878A1
Принадлежит: International Business Machines Corp

Disclosed is a field effect transistor (FET), in which ohmic body contact(s) are placed relatively close to the active region. The FET includes a semiconductor layer, where the active region and body contact region(s) are defined by a trench isolation structure and where a body region is below and abuts the active region, the trench isolation structure and the body contact region(s). A gate traverses the active region. Dummy gate(s) are on the body contact region(s). A contact extends through each dummy gate to the body contact region below. Dielectric material isolates the contact(s) from the dummy gate(s). During processing, the dummy gate(s) act as blocks to ensure that the body contact regions are not implanted with source/drain dopants or source/drain extension dopants and, thereby to ensure that the body contacts, as formed, are ohmic. Also disclosed are an integrated circuit structure with stacked FETs, having such ohmic body contacts, and associated methods.

Подробнее
30-08-2012 дата публикации

Semiconductor device and method of manufacturing the same, and power supply apparatus

Номер: US20120217591A1
Автор: Yoichi Kamada
Принадлежит: Fujitsu Ltd

A semiconductor device includes an electrode material diffusion suppression layer provided either between a gate electrode and a gate insulation film, between Al-containing ohmic electrodes and an Au interconnection, and below the gate electrode and above the Al-containing ohmic electrodes, the electrode material diffusion suppression layer having a structure wherein a first the TaN layer, a Ta layer, and a second the TaN layer are stacked in sequence.

Подробнее
27-12-2012 дата публикации

Through wafer vias and method of making same

Номер: US20120329219A1
Принадлежит: International Business Machines Corp

A method of forming and structure for through wafer vias and signal transmission lines formed of through wafer vias. The method of forming through wafer vias includes forming an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via through a semiconductor substrate having a top surface and an opposite bottom surface, each through wafer via of the array of through wafer vias extending from the top surface of the substrate to the bottom surface of the substrate.

Подробнее
24-01-2013 дата публикации

Borderless Contacts in Semiconductor Devices

Номер: US20130020615A1
Принадлежит: International Business Machines Corp

A method includes depositing a dummy fill material over exposed portions of a substrate and a gate stack disposed on the substrate, removing portions of the dummy fill material to expose portions of the substrate, forming a layer of spacer material over the exposed portions of the substrate, the dummy fill material and the gate stack, removing portions of the layer of spacer material to expose portions of the substrate and the dummy fill material, depositing a dielectric layer over the exposed portions of the spacer material, the substrate, and the gate stack, removing portions of the dielectric layer to expose portions of the spacer material, removing exposed portions of the spacer material to expose portions of the substrate and define at least one cavity in the dielectric layer, and depositing a conductive material in the at least one cavity.

Подробнее
24-01-2013 дата публикации

Memory device and method of manufacturing the same

Номер: US20130021834A1
Автор: Kazuhide Koyama
Принадлежит: Sony Corp

A memory device includes a plurality of memory elements, each having a first electrode, a second electrode, and a memory layer between the first electrode and the second electrode. The plurality of memory layers are in a dotlike pattern. Two adjacent first electrodes share a same memory layer.

Подробнее
28-03-2013 дата публикации

Reliable contacts

Номер: US20130075823A1
Автор: Hong Yu, Huang Liu
Принадлежит: GLOBALFOUNDRIES SINGAPORE PTE LTD

A method for forming a device is disclosed. The method includes providing a substrate prepared with first and second contact regions and a dielectric layer over the contact region. First and second vias are formed in the dielectric layer. The first via is in communication with the first contact region and the second via is in communication with the second contact region. A buried void provides a communication path between the first and second vias. The vias and buried void are at least partially filled with a dielectric filler. The partially filled buried void blocks the communication path between the first and second vias created by the buried void. The dielectric filler in the vias is removed, leaving remaining dielectric filler in the buried void to block the communication path between the first and second vias and contact plugs are formed in the vias.

Подробнее
11-07-2013 дата публикации

Device and methods for forming partially self-aligned trenches

Номер: US20130175629A1
Автор: Ya Hui Chang

A semiconductor device and methods for small trench patterning are disclosed. The device includes a plurality of gate structures and sidewall spacers, an etch stop layer disposed over the sidewall spacers, an interlayer dielectric (ILD) layer disposed on a bottom portion of the etch stop layer, an etch buffer layer disposed on an upper portion of the etch stop layer, and a plurality of metal plugs between the gate structures. An upper portion of the metal plugs is adjacent to the etch buffer layer and a lower portion of the metal plugs is adjacent to the ILD layer.

Подробнее
11-07-2013 дата публикации

Device and methods for small trench patterning

Номер: US20130175637A1
Автор: Ya Hui Chang

A semiconductor device and methods for small trench patterning are disclosed. The device includes a plurality of gate structures and sidewall spacers, and an etch buffer layer disposed over the sidewall spacers. The etch buffer layer includes an overhang component disposed on the upper portion of the sidewall spacers with an edge that extends laterally. The width between the edges of adjacent overhang components is narrower than the width between adjacent sidewall spacers.

Подробнее
25-07-2013 дата публикации

Integrated circuit devices having buried interconnect structures therein that increase interconnect density

Номер: US20130187291A1
Принадлежит: Individual

Integrated circuit devices include a semiconductor substrate having a plurality of trench isolation regions therein that define respective semiconductor active regions therebetween. A trench is provided in the semiconductor substrate. The trench has first and second opposing sidewalls that define opposing interfaces with a first trench isolation region and a first active region, respectively. A first electrical interconnect is provided at a bottom of the trench. An electrically insulating capping pattern is provided, which extends between the first electrical interconnect and a top of the trench. An interconnect insulating layer is also provided, which lines the first and second sidewalls and bottom of the trench. The interconnect insulating layer extends between the first electrical interconnect and the first active region. A recess is provided in the first active region. The recess has a sidewall that defines an interface with the interconnect insulating layer. A second electrical interconnect is also provided, which extends on: (i) an upper surface of the first trench isolation region, (ii) the electrically insulating capping pattern; and (iii) the sidewall of the recess. The first and second electrical interconnects extend across the semiconductor substrate in first and second orthogonal directions, respectively.

Подробнее
01-08-2013 дата публикации

Transistor with counter-electrode connection amalgamated with the source/drain contact

Номер: US20130193494A1
Автор: Maud Vinet, Qing Liu

The field effect device includes an active area made from semi-conducting material and a gate electrode separated from the active area by a dielectric gate material. A counter-electrode is separated from the active area by a layer of electrically insulating material. Two source/drain contacts are arranged on the active area on each side of the gate electrode. One of the source/drain contacts is made from a single material, overspills from the active area and connects the active area with the counter-electrode. The counter-electrode contact is delineated by a closed peripheral insulating pattern.

Подробнее
01-08-2013 дата публикации

Cross-Coupled Transistor Circuit Having Diffusion Regions of Common Node on Opposing Sides of Same Gate Electrode Track and Gate Node Connection Through Single Interconnect Layer

Номер: US20130193524A1
Принадлежит: Individual

A first gate level feature forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second gate level feature forms a gate electrode of a second transistor of the first transistor type. A third gate level feature forms a gate electrode of a second transistor of the second transistor type. The gate electrodes of the second transistors of the first and second transistor types are electrically connected to each other through an electrical connection formed by linear-shaped conductive structures. The gate electrodes of the second transistors of the first and second transistor types are positioned on opposite sides of a gate electrode track along which the gate electrodes of the first transistors of the first and second transistor types are positioned.

Подробнее
08-08-2013 дата публикации

Cross-Coupled Transistor Circuit Defined on Three Gate Electrode Tracks

Номер: US20130200464A1
Принадлежит: Individual

A first PMOS transistor is defined by a gate electrode extending along a first gate electrode track. A second PMOS transistor is defined by a gate electrode extending along a second gate electrode track. A first NMOS transistor is defined by a gate electrode extending along the second gate electrode track. A second NMOS transistor is defined by a gate electrode extending along a third gate electrode track. The gate electrodes of the first PMOS transistor and the first NMOS transistor are electrically connected to a first gate node. The gate electrodes of the second PMOS transistor and the second NMOS transistor are electrically connected to a second gate node. Each of the first PMOS transistor, the first NMOS transistor, the second PMOS transistor, and the second NMOS transistor has a respective diffusion terminal electrically connected to a common output node.

Подробнее
26-09-2013 дата публикации

Process for producing an integrated circuit

Номер: US20130252412A1

A process for producing an integrated circuit on the surface of a substrate, the process including: producing a first layer, including active zones and insulating zones, on the surface of the substrate; producing gate zones on the surface of the first layer, the gate zones each being surrounded by insulating spacers; producing source/drain electrodes; producing a dielectric layer between the insulating spacers, the dielectric layer having an upper surface level with the upper surfaces of the gate zones; partially etching each gate zone so as to lower the upper surface of a first part of each gate zone; and depositing an insulating dielectric layer on the first parts of the gate zones.

Подробнее
07-11-2013 дата публикации

Method for forming gate, source, and drain contacts on a mos transistor

Номер: US20130295734A1

A method for forming gate, source, and drain contacts on a MOS transistor having an insulated gate including polysilicon covered with a metal gate silicide, this gate being surrounded with at least one spacer made of a first insulating material, the method including the steps of a) covering the structure with a second insulating material and leveling the second insulating material to reach the gate silicide; b) oxidizing the gate so that the gate silicide buries and covers the a silicon oxide; c) selectively removing the second insulating material; and d) covering the structure with a first conductive material and leveling the first conductive material all the way to a lower level at the top of the spacer.

Подробнее
07-11-2013 дата публикации

Methods of forming contacts for semiconductor devices using a local interconnect processing scheme

Номер: US20130295756A1
Принадлежит: Globalfoundries Inc

One method disclosed herein includes forming a plurality of source/drain contacts that are conductively coupled to a source/drain region of a plurality of transistor devices, wherein at least one of the source/drain contacts is a local interconnect structure that spans the isolation region and is conductively coupled to a first source/drain region in a first active region and to a second source/drain region in a second active region, and forming a patterned mask layer that covers the first and second active regions and exposes at least a portion of the local interconnect structure positioned above an isolation region that separates the first and second active regions. The method further includes performing an etching process through the patterned mask layer to remove a portion of the local interconnect structure, thereby defining a recess positioned above a remaining portion of the local interconnect structure, and forming an insulating material in the recess.

Подробнее
05-12-2013 дата публикации

Gate aligned contact and method to fabricate same

Номер: US20130320456A1
Принадлежит: Intel Corp

Gate aligned contacts and methods of forming gate aligned contacts are described. For example, a method of fabricating a semiconductor structure includes forming a plurality of gate structures above an active region formed above a substrate. The gate structures each include a gate dielectric layer, a gate electrode, and sidewall spacers. A plurality of contact plugs is formed, each contact plug formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. A plurality of contacts is formed, each contact formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. The plurality of contacts and the plurality of gate structures are formed subsequent to forming the plurality of contact plugs.

Подробнее
02-01-2014 дата публикации

DRIVING CIRCUIT, FLAT PANEL DISPLAY DEVICE HAVING THE SAME AND METHOD OF REPAIRING THE DRIVING CIRCUIT

Номер: US20140002423A1
Принадлежит: Samsung Display Co., Ltd.

A driving circuit includes: an input terminal; an output terminal; a first transistor having a source electrode coupled to the input terminal, a drain electrode coupled to the output terminal, and a gate electrode; a second transistor having a source electrode, a drain electrode, and a gate electrode respectively coupled to the source electrode, the drain electrode, and the gate electrode of the first transistor; a first capacitor having a first electrode coupled to the input terminal and a second electrode coupled to the output terminal; and a second capacitor coupled in parallel with the first capacitor and having a first electrode coupled to the first electrode of the first capacitor and a second electrode that is floated. 1. A driving circuit comprising:an input terminal;an output terminal; a source electrode coupled to the input terminal;', 'a drain electrode coupled to the output terminal; and', 'a gate electrode;, 'a first transistor comprising a first electrode coupled to the input terminal; and', 'a second electrode coupled to the output terminal; and, 'a first capacitor comprising a first electrode coupled to the first electrode of the first capacitor; and', 'a second electrode that is floated., 'a second capacitor coupled in parallel with the first capacitor and comprising2. The driving circuit according to claim 1 , wherein the second electrodes of the first and second capacitors comprise metal.3. The driving circuit according to claim 2 , wherein the second electrode of the first capacitor and the output terminal are coupled to each other by melting the metal.4. The driving circuit according to claim 1 , wherein the first electrode and the second electrode of the second capacitor are short-circuited to each other.5. The driving circuit according to claim 1 , wherein a floated ending portion of the second electrode of the second capacitor has an irregular cross section.6. The driving circuit according to claim 1 , further comprising a second transistor ...

Подробнее
09-01-2014 дата публикации

BODY-GATE COUPLING TO IMPROVE LINEARITY OF RADIO-FREQUENCY SWITCH

Номер: US20140009212A1
Принадлежит:

Radio-frequency (RF) switch circuits are disclosed having one or more transistors coupled to provide improved switching performance. RF switches include at least one field-effect transistor (FET) disposed between first and second nodes, each the at least one FET having a respective body and a corresponding gate. A coupling circuit couples the respective body and corresponding gate of the at least one FET. The coupling circuit may include a diode in series with a resistor and may be configured to facilitate removal of excess charge from the respective body. 1. A radio-frequency (RF) switch comprising:at least one field-effect transistor (FET) disposed between first and second nodes, each the at least one FET having a respective body and a corresponding gate; anda coupling circuit that couples the respective body and corresponding gate of the at least one FET, the coupling circuit including a diode in series with a resistor and configured to facilitate removal of excess charge from the respective body.2. The switch of wherein the FET is a silicon-on-insulator (SOI) FET.3. The switch of wherein an anode of the diode is connected to the body claim 1 , and a cathode of the diode is connected to one end of the resistor with the other end of the resistor being connected to the gate.4. The switch of wherein the diode and the resistor are configured to yield improved P1 dB and IMD performance of the switch.5. The switch of further comprising a gate resistor connected to the gate to facilitate floating of the gate.6. The switch of wherein the first node is configured to receive an RF signal having a power value and the second node is configured to output the RF signal when the FET is in an ON state.7. The switch of wherein the at least one FET includes N FETs connected in series claim 6 , the quantity N selected to allow the switch circuit to handle the power of the RF signal.8. (canceled)9. (canceled)10. (canceled)11. (canceled)12. A method for fabricating a semiconductor ...

Подробнее
23-01-2014 дата публикации

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

Номер: US20140021555A1
Принадлежит: KABUSHIKI KAISHA TOSHIBA

A manufacturing method of a semiconductor device according to an embodiment includes forming element isolation regions and active areas on a surface of a semiconductor substrate. A plurality of gate electrodes are formed above the active areas. Recesses that recess below surfaces of the element isolation regions are formed in the active areas by selectively etching the active areas between the gate electrodes. An interlayer dielectric film is deposited on the active areas, the element isolation regions, and the gate electrodes. A contact holes are formed on the recesses by etching the interlayer dielectric film using anisotropic etching. A bottom of each contact holes is widened by further etching the interlayer dielectric film on an inner wall of each contact hole using isotropic etching. Contacts contacting the recesses in the active areas are formed by embedding a conductive material in the contact holes. 1. A manufacturing method of a semiconductor device , comprising:forming a plurality of element isolation regions and a plurality of active areas on a surface of a semiconductor substrate;forming a plurality of gate electrodes above the active areas;forming a plurality of recesses that recess below surfaces of the element isolation regions in the active areas by selectively etching the active areas between the gate electrodes;depositing an interlayer dielectric film on the active areas, the element isolation regions, and the gate electrodes;forming a plurality of contact holes on the recesses by etching the interlayer dielectric film using anisotropic etching;widening a bottom of each contact hole by further etching the interlayer dielectric film on an inner wall of the contact hole using isotropic etching; andforming a plurality of contacts contacting the recesses in the active areas by embedding a conductive material in the contact holes.2. The method of claim 1 , comprising forming a protective insulation film covering the gate electrodes after forming the ...

Подробнее
06-02-2014 дата публикации

Device and Methods for Small Trench Patterning

Номер: US20140035054A1
Автор: Ya Hui Chang

A semiconductor device and methods for small trench patterning are disclosed. The device includes a plurality of gate structures and sidewall spacers, and an etch buffer layer disposed over the sidewall spacers. The etch buffer layer includes an overhang component disposed on the upper portion of the sidewall spacers with an edge that extends laterally. The width between the edges of adjacent overhang components is narrower than the width between adjacent sidewall spacers.

Подробнее
06-02-2014 дата публикации

3D SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING SAME

Номер: US20140038400A1
Принадлежит:

A three dimensional (3D) semiconductor device includes; a vertical channel extending from a lower end proximate a substrate to an upper end and connecting a plurality of memory cells, and a cell array comprising the plurality of cells, wherein the cell array is arranged in a gate stack of layers having a stair-stepped structure disposed on the substrate. The gate stack includes a lower layer including a lower select line coupled to a lower non-memory transistor proximate the lower end, upper layers including conductive lines respectively coupled to an upper non-memory transistor proximate the upper end and connected as a single conductive piece to form an upper select line, and intermediate layers respectively including a word line and coupled to a cell transistor, wherein the intermediate layers are disposed between the lower select line and the upper select line. 1. A method of fabricating a semiconductor device , the method comprising:forming a plurality of vertical channels extending from a substrate; andforming a gate stack having a stair-stepped structure by vertically stacking a plurality of layers each respectively including a gate, wherein at least one of an uppermost layer and a lowermost layer comprises vertically adjacent multi layers connected via a conductor.2. The method of claim 1 , wherein the forming of the gate stack comprises:forming a first mold stack by stacking a plurality of sacrificial layers spaced apart from one to another on the substrate;forming the stair structure by patterning the first mold stack; andreplacing the sacrificial layers with conductive layers to form the gates.3. The method of claim 2 , wherein the forming of the stair structure of the first mold stack comprises claim 2 , repeatedly forming a portion of the stair structure by sequentially performing etching processes using sequentially decreasing or increasing masks so as to sequentially pattern the plurality of sacrificial layers.4. The method of claim 3 , further ...

Подробнее
13-02-2014 дата публикации

Trench transistors and methods with low-voltage-drop shunt to body diode

Номер: US20140042535A1
Принадлежит: MaxPower Semiconductor Inc

Methods and systems for power semiconductor devices integrating multiple trench transistors on a single chip. Multiple power transistors (or active regions) are paralleled, but one transistor has a lower threshold voltage. This reduces the voltage drop when the transistor is forward-biased. In an alternative embodiment, the power device with lower threshold voltage is simply connected as a depletion diode, to thereby shunt the body diodes of the active transistors, without affecting turn-on and ON-state behavior.

Подробнее
13-02-2014 дата публикации

Semiconductor device and method for fabricating the same

Номер: US20140042554A1
Автор: Ahn Sook YOON
Принадлежит: SK hynix Inc

A semiconductor device is formed by depositing a nitride material having a lower etch rate than an oxide material over or between buried gates when forming a metal contact at an end portion of a cell region, to prevent a lower substrate from being etched during an etching process forming a metal contact hole. The semiconductor device includes at least one buried gate formed in a device isolation film of a semiconductor substrate, an etch stop film formed over and between the buried gates, and a metal contact formed perpendicular to the buried gate in the etch stop film.

Подробнее
05-01-2017 дата публикации

DISTRIBUTED DECOUPLING CAPACITOR

Номер: US20170005087A1
Принадлежит:

The electrical device includes a plurality of fin structures, the plurality of fin structures including at least one decoupling fin and at least one semiconductor fin. Each of the plurality of fin structures having substantially a same geometry. The electrical device includes at least one semiconductor device including a channel region present in the at least one semiconductor fin, a gate structure present on the channel region of the at least one semiconductor fin, and source and drain regions present on source and drain region portion of the at least one semiconductor fin. The electrical device includes at least one decoupling capacitor including the decoupling fin structure as a first electrode of the decoupling capacitor, a node dielectric layer and a second electrode provided by the metal contact to the source and drain regions of the semiconductor fin structures, wherein the decoupling capacitor is present underlying the power line to the semiconductor fin structures. 1. An electrical device comprising:a plurality of fin structures including at least one decoupling fin structure and at least one semiconductor fin structure;at least one semiconductor device including a channel region present in the at least one semiconductor fin structure, a gate structure present on the channel region of the at least one semiconductor fin structure, and source and drain regions present on source and drain region portions of the at least one semiconductor fin structure; andat least one decoupling capacitor including the at least one decoupling fin structure, wherein the decoupling capacitor is present underlying the power line to the at least one semiconductor fin structure.2. The electrical device of claim 1 , wherein the at least one decoupling fin structure provides as a first electrode of the at least one decoupling capacitor.3. The electrical device of further comprising a second electrode for the at least one decoupling capacitor provided by a metal contact.4. The ...

Подробнее
05-01-2017 дата публикации

DISTRIBUTED DECOUPLING CAPACITOR

Номер: US20170005088A1
Принадлежит:

An electrical device including a plurality of fin structures. The plurality of fin structures including at least one decoupling fin and at least one semiconductor fin. The electrical device includes at least one semiconductor device including a channel region present in the at least one semiconductor fin, a gate structure present on the channel region of the at least one semiconductor fin, and source and drain regions present on source and drain region portion of the at least one semiconductor fin. The electrical device includes at least one decoupling capacitor including the decoupling fin structure as a first electrode of the decoupling capacitor, a node dielectric layer and a second electrode provided by the metal contact to the source and drain regions of the semiconductor fin structures. The decoupling capacitor is present underlying the power line to the semiconductor fin structures. 1. A method of forming an electrical device comprising:forming a plurality of fin structures, wherein at least one of the plurality of fin structures is a decoupling fin structure, and at least one of the plurality of fin structures is a semiconductor fin structure;forming fin type field effect transistors (FinFETs) from each of said semiconductor fin structure; andforming a decoupling capacitor from each of said decoupling fin structures, the decoupling capacitor including a first electrode provided by the decoupling fin structure, a node dielectric and a second electrode provided by a metal contact that transmits electrical current from a power line to the FinFETs, wherein the decoupling capacitor is present directly underlying the power line.2. The method of claim 1 , wherein each of the plurality of fin structures have substantially a same geometry.3. The method of claim 2 , wherein said each of the plurality of fin structures have substantially a same composition.4. The method claim 1 , wherein the decoupling fin structure has a length substantially parallel to a length of ...

Подробнее
05-01-2017 дата публикации

SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD OF THE SAME

Номер: US20170005089A1
Принадлежит:

In a non-insulated DC-DC converter having a circuit in which a power MOS•FET high-side switch and a power MOS•FET low-side switch are connected in series, the power MOS•FET low-side switch and a Schottky barrier diode to be connected in parallel with the power MOS•FET low-side switch are formed within one semiconductor chip. The formation region SDR of the Schottky barrier diode is disposed in the center in the shorter direction of the semiconductor chip, and on both sides thereof, the formation regions of the power MOS•FET low-side switch are disposed. From the gate finger in the vicinity of both long sides on the main surface of the semiconductor chip toward the formation region SDR of the Schottky barrier diode, a plurality of gate fingers are disposed so as to interpose the formation region SDR between them. 1. A method of forming a semiconductor device , comprising:(a) preparing a semiconductor wafer having a semiconductor device forming region,wherein the semiconductor device forming region includes a first long side, a second long side located on the opposite side of the first long side, a first short side and a second short side located on the opposite side of the first short side,wherein a schottky barrier diode is formed in a first region of the semiconductor device forming region and includes an anode and a cathode,wherein a plurality of power MOSFETs are formed in a plurality of second regions of the semiconductor forming region and respectively include a gate electrode, a source region and a drain region,(b) forming an insulating film over the semiconductor device forming region;(c) forming a metal layer over the insulating film; and(d) forming a first metal layer and a second metal layer by patterning the metal layer;wherein the first region is arranged between the first long side and a second long side,wherein the plurality of second regions are arranged along the first long side, and are arranged between the first long side and the first region, ...

Подробнее
05-01-2017 дата публикации

LOW END PARASITIC CAPACITANCE FINFET

Номер: US20170005092A1
Автор: Leobandung Effendi
Принадлежит:

Embodiments of the present invention provide methods for fabricating a semiconductor device. One method may include providing a semiconductor substrate with fins etched into the semiconductor substrate; forming a gate structure and depositing an insulating material around the gate structure; selectively etching an active device area; forming a set of spacers on the sides of the gate structure; growing a doped source and drain region; depositing an insulator over an upper surface of a deposited etch stop layer; and depositing a metal into a contact opening to form one or more contacts. 1. A method for fabricating a semiconductor device comprising:providing a semiconductor substrate comprising a plurality of fins etched in the semiconductor substrate;forming a set of gate structures;depositing a first insulating material between the set of gate structures;selectively etching an active device area;depositing an oxide material over a top surface of the active device area;removing the first insulating material selective to the plurality of fins;forming a set of spacers adjacent to the set of gate structures;growing a doped source and drain region adjacent to the plurality of fins;depositing an etch stop layer over an upper surface of the deposited oxide material;depositing a second insulating material over an upper surface of the deposited etch stop layer; anddepositing a metal within a contact opening to form a plurality of contacts.2. The method of claim 1 , further comprising:creating device regions in the semiconductor substrate using shallow trench isolation (STI);filling the device regions with an insulator;planarizing the insulator; andrecessing the insulator, wherein the insulator has a thickness which is less than a height of the plurality of fins.3. The method of claim 1 , wherein forming a set of gate structures comprises one of:atomic layer deposition (ALD), molecular layer deposition (MLD), chemical vapor deposition (CVD), and physical vapor deposition (PVD ...

Подробнее
05-01-2017 дата публикации

METHODS OF FABRICATING SEMICONDUCTOR DEVICE

Номер: US20170005099A1
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A method of fabricating a semiconductor device includes forming a device isolation layer in a substrate to define active regions, forming a conductive layer on the active regions, forming first mask patterns intersecting the active regions on the conductive layer, etching the conductive layer using the first mask patterns as etch masks to form bit lines, growing second mask patterns from top surfaces of the first mask patterns, and performing a patterning process using the second mask patterns as etch masks to form contact holes exposing the active regions between the bit lines. 1. A method of fabricating a semiconductor device , the method comprising:defining active regions by forming a device isolation layer in a substrate;forming a conductive layer on the active regions;forming first mask patterns intersecting the active regions on the conductive layer;forming bit lines by etching the conductive layer using the first mask patterns as etch masks;growing second mask patterns on surfaces of the first mask patterns that are opposite to the substrate; andforming contact holes by performing a patterning process using the second mask patterns as etch masks exposing the active regions between the bit lines.2. The method of claim 1 , further comprising:filling the contact holes with a conductive material; andforming storage node contacts by performing an etch-back process on the conductive material,wherein at least a portion of the second mask patterns is removed during the etch-back process.3. The method of claim 2 , further comprising:forming capacitors on the storage node contacts.4. The method of claim 3 , further comprising:forming landing pads between the storage node contacts and the capacitors.5. The method of claim 1 , wherein a thickness of one or more of the second mask patterns ranges from about 25% to about 50% of a thickness of one or more of the first mask patterns.6. The method of claim 1 , wherein the second mask patterns are locally formed on the ...

Подробнее
07-01-2016 дата публикации

Systems and Methods of Sectioned Bit Line Memory Arrays, Including Hierarchical and/or Other Features

Номер: US20160005458A1
Принадлежит:

A sectioned bit line of an SRAM memory device, an SRAM memory device having a sectioned bit line, and associated systems and methods are described, including embodiments having sectioned bit lines with hierarchical aspects. In one illustrative implementation, each sectioned bit line may comprise a local bit line, a memory cell connected to the local bit line, and a pass gate coupled to the local bit line, wherein the pass gate is configured to be coupled to a global bit line. Further, in some embodiments, the sectioned bit lines are arranged in hierarchical arrays. In other implementations, SRAM memory devices may be configured involving sectioned bit lines (including hierarchical) and a global bit line wherein the pass gates are configured to connect and isolate the sectioned bit line and the global bit line. 1. An SRAM memory device comprising: [ a local bit line;', 'one or more memory cells connected to the local bit line;', 'a local complement bit line connected to the memory cell; &', 'a pass gate coupled to the local bit line;, 'a plurality of sectioned bit lines (SBLs), each comprising, 'a local sense amplifier;', 'a local shared data driver;', 'a global bit line;, 'a local section bit line includingwherein the local sense amplifier is configured to amplify a signal on a local sense line and provide an output to the global bit line.2. The device of wherein the pass gates are configured to connect and/or isolate the sectioned bit line and local sense line.3. A local section bit line (LSBL) of an SRAM including: a local bit line;', 'one or more memory cells connected to the local bit line;', 'a local complement bit line connected to the memory cell; and', 'a pass gate coupled to the local bit line;, 'a plurality of sectioned bit lines (SBLs), each comprisinga local shared sense amplifier;a local shared data driver;a global bit line;wherein the local sense amplifier is configured to amplify a signal on a local sense line and provide an output to the global bit ...

Подробнее
13-01-2022 дата публикации

Semiconductor device and method

Номер: US20220013364A1

An embodiment includes a method including forming an opening in a cut metal gate region of a metal gate structure of a semiconductor device, conformally depositing a first dielectric layer in the opening, conformally depositing a silicon layer over the first dielectric layer, performing an oxidation process on the silicon layer to form a first silicon oxide layer, filling the opening with a second silicon oxide layer, performing a chemical mechanical polishing on the second silicon oxide layer and the first dielectric layer to form a cut metal gate plug, the chemical mechanical polishing exposing the metal gate structure of the semiconductor device, and forming a first contact to a first portion of the metal gate structure and a second contact to a second portion of the metal gate structure, the first portion and the second portion of the metal gate structure being separated by the cut metal gate plug.

Подробнее
07-01-2016 дата публикации

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Номер: US20160005659A1
Автор: Song Hyun-Seung
Принадлежит:

Embodiments provide methods of manufacturing a semiconductor device. The method includes forming an interlayer insulating layer on a substrate; forming a plurality of contact holes penetrating the interlayer insulating layer, the plurality of contact holes arranged along a first direction and a second direction perpendicular to the first direction; and forming contacts in the contact holes, each contact hole being formed using a photo mask that is distinct from a photo mask used for forming a contact hole immediately adjacent to each contact hole in the first direction and distinct from a photo mask used for forming a contact hole immediately adjacent to each contact hole in the second direction, and top surfaces of the contacts being at a same level from the substrate. 1. A method of manufacturing a semiconductor device , the method comprising:forming an interlayer insulating layer on a substrate;forming a plurality of contact holes penetrating the interlayer insulating layer, the plurality of contact holes arranged along a first direction and a second direction perpendicular to the first direction; andforming contacts in the contact holes,each contact hole being formed using a photo mask that is distinct from a photo mask used for forming a contact hole immediately adjacent to each contact hole in the first direction and distinct from a photo mask used for forming a contact hole immediately adjacent to each contact hole in the second direction, andtop surfaces of the contacts being at a same level from the substrate.2. The method as claimed in claim 1 , further comprising:forming a plurality of active patterns extending in the first direction on the substrate;forming a plurality of gate structures intersecting the active patterns and extending in the second direction; andforming source/drain regions in the active patterns at both sides of each gate structure,wherein the interlayer insulating layer covers the active patterns, the gate structures, and the source/ ...

Подробнее
13-01-2022 дата публикации

Quantum well stacks for quantum dot devices

Номер: US20220013658A1
Принадлежит: Intel Corp

Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include a (111) silicon substrate, a (111) germanium quantum well layer above the substrate, and a plurality of gates above the quantum well layer. In some embodiments, a quantum dot device may include a silicon substrate, an insulating material above the silicon substrate, a quantum well layer above the insulating material, and a plurality of gates above the quantum well layer.

Подробнее
07-01-2016 дата публикации

Semiconductor Constructions, and Semiconductor Processing Methods

Номер: US20160005742A1
Автор: Mark Kiehlbauch
Принадлежит: Micron Technology Inc

Some embodiments include methods in which a pair of spaced-apart adjacent features is formed over a substrate. The features have silicon dioxide surfaces. Silicon nitride is deposited between the features. A first region of the silicon nitride is protected with a mask while a second region is not. The second region is removed to form an opening between the features. Some embodiments include semiconductor constructions that contain a pair of spaced-apart adjacent features. The features are lines extending along a first direction, and are spaced from one another by a trench. Alternating plugs and intervening materials are within the trench, with the plugs and intervening materials alternating along the first direction. The intervening materials consist of silicon nitride, and the plugs have lateral peripheries that directly contact silicon dioxide of the features, and that directly contact silicon nitride of the intervening regions.

Подробнее
04-01-2018 дата публикации

SEMICONDUCTOR STRUCTURE HAVING CONTACT HOLES BETWEEN SIDEWALL SPACERS

Номер: US20180005894A1
Принадлежит:

The disclosed subject matter provides a semiconductor structure and fabrication method thereof. In a semiconductor structure, a dielectric layer, a plurality of discrete gate structures, and a plurality of sidewall spacers are formed on a semiconductor substrate. The plurality of discrete gate structures and sidewall spacers are formed in the dielectric layer, and a sidewall spacer is formed on each side of each gate structure. A top portion of each gate structure and a top portion of the dielectric layer between neighboring sidewall spacers of neighboring gate structures are removed. A protective layer is formed on each of the remaining dielectric layer and the remaining gate structures. Contact holes are formed on the semiconductor substrate, between neighboring sidewall spacers, and on opposite sides of the protective layer on the remaining dielectric layer. A metal plug is formed in each contact hole. 117.-. (canceled)18. A semiconductor structure , comprising:a dielectric layer, a plurality of discrete gate structures, and a plurality of sidewall spacers, disposed on a semiconductor substrate, wherein the plurality of discrete gate structures and the sidewall spacers are disposed in the dielectric layer, and one sidewall spacer is on each side of each gate structure;a first protective layer on a surface portion of the dielectric layer between neighboring sidewall spacers of neighboring gate structures, wherein the first protective layer is located corresponding to a portion of a length of the neighboring sidewall spacers;a second protective layer on each gate structure;contact holes on the semiconductor substrate, between neighboring sidewall spacers, and on opposite sides of the first protective layer; anda metal plug in each contact hole.19. The semiconductor structure according to claim 18 , wherein:{'sub': 'x', 'each of the first and second protective layers is made of a material including SiN, SiON, SiC, SiCO, or a combination thereof, and'}the first and ...

Подробнее
04-01-2018 дата публикации

METHOD FOR CAPPING CU LAYER USING GRAPHENE IN SEMICONDUCTOR

Номер: US20180005952A1
Автор: ZHOU MING
Принадлежит:

An interconnect structure includes a substrate, a dielectric layer on the substrate, a metal interconnect layer in the dielectric layer and in contact with the substrate, the metal interconnect layer having an upper surface flush with an upper surface of the dielectric layer, and a graphene layer on the metal interconnect layer. The graphene layer insulates a metal from air and prevents the metal from being oxidized by oxygen in the air, thereby increasing the queue time for the CMP process and the device reliability. 1. A method of manufacturing an interconnect structure , the method comprising:providing a semiconductor structure comprising a substrate, a dielectric layer on the substrate, and a metal interconnect layer in the dielectric layer and in contact with the substrate; andforming a graphene layer on the metal interconnect layer.2. The method of claim 1 , wherein forming the graphene layer comprises forming an amorphous carbon layer on the dielectric layer claim 1 , the amorphous carbon layer being adjacent to the graphene layer.3. The method of claim 1 , wherein forming the graphene layer comprises introducing methane and a carrier gas into a reaction chamber to form a mixed gas claim 1 , the mixed gas having a volume ratio of methane in a range between 0.1% and 50% claim 1 , at a temperature in a range between 300° C. and 450° C. claim 1 , under a pressure in a range between 0.1 mTorr and 10 Torr claim 1 , and a radio frequency power in a range between 10 W and 1000 W.4. The method of claim 3 , wherein the carrier gas comprises nitrogen claim 3 , or hydrogen claim 3 , or nitrogen and hydrogen.5. The method of claim 1 , further comprising claim 1 , prior to forming the graphene layer: performing a hydrogen plasma cleaning process on an upper surface of the metal interconnect layer.6. The method of claim 5 , wherein performing the hydrogen plasma cleaning process comprises: introducing a hydrogen gas into a reaction chamber at a flow rate in a range between ...

Подробнее
07-01-2021 дата публикации

PROCESS FLOW FOR FABRICATION OF CAP METAL OVER TOP METAL WITH SINTER BEFORE PROTECTIVE DIELECTRIC ETCH

Номер: US20210005560A1
Принадлежит: TEXAS INSTRUMENTS INCORPORATED

A method of forming a semiconductor device for improving an electrical connection. The semiconductor device includes a top metal layer. A protective dielectric layer is formed over the top metal layer. A sintering operation is performed while the top metal layer is covered by the protective dielectric layer. After the sintering operation, the protective dielectric layer is patterned to expose areas on the top metal layer for bond pads of the semiconductor device. A bond pad cap is formed on the top metal layer where exposed by the protective dielectric layer. 1. A method of forming a semiconductor device , comprising:providing a device substrate containing the semiconductor device, the device substrate including a semiconductor material;forming an active component extending into the semiconductor material;forming an interconnect region on the semiconductor material; andforming a top metal layer in the interconnect region;forming a protective dielectric layer on the top metal layer, the protective dielectric layer being at least 1 micron thick;heating the semiconductor device in a sintering operation while the protective dielectric layer covers the top metal layer;after the sintering operation, removing the protective dielectric layer from a bond pad opening in the protective dielectric layer to expose a portion of the top metal layer; andforming a bond pad cap on the top metal layer in the bond pad opening.2. The method of claim 1 , wherein the sintering operation has a sinter thermal profile sufficient to passivate the active component.3. The method of claim 2 , wherein the sinter thermal profile includes heating the semiconductor device to a sinter temperature for a sinter time claim 2 , wherein a product of the sinter time claim 2 , in minutes claim 2 , and an Arrhenius factor of the sinter temperature is greater than 0.0027 minutes claim 2 , the Arrhenius factor of the sinter temperature being determined by the expression:{'br': None, 'i': E', 'k', '+T, 'sub': A ...

Подробнее
04-01-2018 дата публикации

INTERCONNECTS FOR VERTICAL-TRANSPORT FIELD-EFFECT TRANSISTORS

Номер: US20180006023A1
Принадлежит:

Structures and fabrication methods for vertical-transport field-effect transistors. The structure includes a vertical-transport field-effect transistor having a source/drain region located in a semiconductor layer, a fin projecting from the source/drain region in the semiconductor layer, and a gate electrode on the semiconductor layer and coupled with the fin. The structure further includes an interconnect located in a trench defined in the semiconductor layer. The interconnect is coupled with the source/drain region or the gate electrode of the vertical-transport field-effect transistor, and may be used to couple the source/drain region or the gate electrode of the vertical-transport field-effect transistor with a source/drain region or a gate electrode of another vertical-transport field-effect transistor. 1. A structure comprising:a first vertical-transport field-effect transistor having a source/drain region located in a semiconductor layer, a fin projecting from the source/drain region in the semiconductor layer, and a gate electrode on the semiconductor layer and coupled with the fin; andan interconnect located in a trench defined in the semiconductor layer, the interconnect coupled with the source/drain region or the gate electrode of the first vertical-transport field-effect transistor.2. The structure of wherein the interconnect is coupled with the source/drain region of the first vertical-transport field-effect transistor claim 1 , further comprising:a second vertical-transport field-effect transistor having a source/drain region located in the semiconductor layer, a fin projecting from the source/drain region in the semiconductor layer, and a gate electrode on the semiconductor layer and coupled with the fin,wherein the source/drain region of the first vertical-transport field-effect transistor is coupled by the interconnect with the source/drain region or the gate electrode of the second vertical-transport field-effect transistor.3. The structure of ...

Подробнее
04-01-2018 дата публикации

Long channel and short channel vertical fet co-integration for vertical fet vtfet

Номер: US20180006025A1
Принадлежит: International Business Machines Corp

A semiconductor and a method of forming a semiconductor on a single chip, including forming a shallow trench isolation (STI) region on a short channel device and a long channel device, forming at least two vertical fins connected in the long channel device, and forming contacts on a source and drain regions for the long channel device and short channel device, wherein the contacts connect a top surface of the source or drain region for series FET (Field-Effect Transistor) connection for the long channel device.

Подробнее
04-01-2018 дата публикации

FinFET VARACTOR

Номер: US20180006162A1
Автор: Zhou Fei
Принадлежит:

A varactor transistor includes a semiconductor fin having a first conductivity type, a plurality of gate structures separated from each other and surrounding a portion of the semiconductor fin. The plurality of gates structures include a dummy gate structure on an edge of the semiconductor fin, and a first gate structure spaced apart from the dummy gate structure. The dummy gate structure and the gate structure each include a gate insulator layer on a surface portion of the semiconductor fin, a gate on the gate insulator layer, and a spacer on the gate. The varactor transistor also includes a raised source/drain region on the semiconductor fin and between the dummy gate structure and the first gate structure, the raised source/drain region and the gate of the dummy gate structure being electrically connected to a same potential. 1. A varactor transistor , comprising:a semiconductor fin having a first conductivity type;a plurality of gate structures separated from each other and surrounding a portion of the semiconductor fin, the plurality of gates structures comprising a dummy gate structure on an edge of the semiconductor fin, and a first gate structure spaced apart from the dummy gate structure, the dummy gate structure and the gate structure each comprising a gate insulator layer on a surface portion of the semiconductor fin, a gate on the gate insulator layer, and a spacer on the gate; anda raised source/drain region on the semiconductor fin and between the dummy gate structure and the first gate structure, the raised source/drain region and the gate of the dummy gate structure being electrically connected to a same potential.2. The varactor transistor of claim 1 , further comprising a substrate having a second conductivity type different from the first conductivity type claim 1 , the semiconductor fin on the substrate and a reverse pn junction formed between the semiconductor fin and the substrate.3. The varactor transistor of claim 1 , wherein the dummy gate ...

Подробнее
07-01-2021 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20210005729A1
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device comprises a gate electrode on a substrate, an upper capping pattern on the gate electrode, and a lower capping pattern between the gate electrode and the upper capping pattern. The lower capping pattern comprises a first portion between the gate electrode and the upper capping pattern, and a plurality of second portions extending from the first portion onto corresponding side surfaces of the upper capping pattern. The upper capping pattern covers a topmost surface of each of the second portions. 126.-. (canceled)27. A semiconductor device comprising:a gate electrode on a substrate;a capping pattern on the gate electrode; andgate spacers on corresponding side surfaces of the gate electrode, the gate spacers spaced apart from each other with the gate electrode interleaved therebetween,wherein a width of a lower portion of the capping pattern increases as a distance from an upper surface of the gate electrode, andwherein each of the gate spacers extends onto a side surface of the lower portion of the capping pattern, and an upper end of each of the gate spacers has a tapered shape.28. The device of claim 27 , wherein each of the gate spacers is in contact with the side surface of the lower portion of the capping pattern.29. The device of claim 28 , further comprising:a gate dielectric pattern between the substrate and the gate electrode,wherein the gate dielectric pattern extends between each of the gate spacers and the gate electrode and is in contact with the lower portion of the capping pattern.30. The device of claim 29 , wherein the capping pattern comprises:an upper capping pattern on the gate electrode; anda lower capping pattern between the gate electrode and the upper capping pattern, andwherein each of the gate spacers is in contact with a side surface of the lower capping pattern, and the gate dielectric pattern is in contact with a bottom surface of the lower ...

Подробнее
02-01-2020 дата публикации

Forming Nitrogen-Containing Low-K Gate Spacer

Номер: US20200006151A1
Автор: Kao Wan-Yi, Ko Chung-Chi
Принадлежит:

A method includes forming a dummy gate stack over a semiconductor region of a wafer, and depositing a gate spacer layer using Atomic Layer Deposition (ALD) on a sidewall of the dummy gate stack. The depositing the gate spacer layer includes performing an ALD cycle to form a dielectric atomic layer. The ALD cycle includes introducing silylated methyl to the wafer, purging the silylated methyl, introducing ammonia to the wafer, and purging the ammonia. 1. A method comprising:forming a dummy gate stack over a semiconductor region of a wafer; and introducing silylated methyl to the wafer;', 'purging the silylated methyl;', 'introducing ammonia to the wafer; and', 'purging the ammonia., 'depositing a gate spacer layer using Atomic Layer Deposition (ALD) on a sidewall of the dummy gate stack, wherein the depositing the gate spacer layer comprises performing an ALD cycle to form a dielectric atomic layer, wherein the ALD cycle comprises2. The method of further comprising performing an anneal on the wafer after the gate spacer layer is formed claim 1 , wherein the anneal is performed with the wafer placed in an oxygen-containing gas.3. The method of claim 2 , wherein the anneal is performed at a temperature in a range between about 400° C. and about 500° C.4. The method of claim 2 , wherein before the anneal claim 2 , the gate spacer layer has a first nitrogen atomic percentage claim 2 , and after the anneal claim 2 , a portion of the gate spacer layer has a second nitrogen atomic percentage lower than the first nitrogen atomic percentage.5. The method of claim 2 , wherein before the anneal claim 2 , the gate spacer layer has a first k value higher than a k value of silicon oxide claim 2 , and after the anneal claim 2 , a portion of the gate spacer layer has a second k value lower than the k value of silicon oxide.6. The method of claim 1 , wherein the depositing the gate spacer layer further comprises introducing ammonia to the wafer before performing the ALD cycle.7. The ...

Подробнее
02-01-2020 дата публикации

Methods for Improving Interlayer Dielectric Layer Topography

Номер: US20200006152A1
Принадлежит:

Methods for improving interlayer dielectric (ILD) layer topography and resulting integrated circuit devices are disclosed herein. An exemplary method includes forming a first contact etch stop layer having a first thickness over a first region of a wafer, forming a second contact etch stop layer having a second thickness over a second region of the wafer, and forming an ILD layer over the first contact etch stop layer and the second contact etch stop layer. A first topography variation exists between the first region and the second region. The second thickness is different than the first thickness to achieve a second topography variation that is less than the first topography variation. The first topography variation can be caused by a height difference between a first gate structure disposed over the wafer in the first region and a second gate structure disposed over the wafer in the second region. 1. A method comprising:forming a first contact etch stop layer over a first region of a wafer, wherein a first topography variation exists between the first region and a second region of the wafer and the first contact etch stop layer has a first thickness;forming a second contact etch stop layer over the second region of the wafer, wherein the second contact etch stop layer has a second thickness that is different than the first thickness to reduce the first topography variation to a second topography variation between the first region and the second region; andforming an interlayer dielectric (ILD) layer over the first contact etch stop layer and the second contact etch stop layer.2. The method of claim 1 , wherein the second topography variation is a difference in a height of a topmost surface of the first contact etch stop layer in the first region and a height of a topmost surface of the second contact etch stop layer in the second region claim 1 , wherein the difference is less than or equal to about 10%.3. The method of claim 1 , wherein: depositing the first ...

Подробнее
02-01-2020 дата публикации

Semiconductor Device Including a Conductive Feature Over an Active Region

Номер: US20200006217A1
Принадлежит:

A semiconductor device includes a substrate having an active region, a first gate structure over a top surface of the substrate, a second gate structure over the top surface of the substrate, a pair of first spacers on each sidewall of the first gate structure, a pair of second spacers on each sidewall of the second gate structure, an insulating layer over at least the first gate structure, a first conductive feature over the active region and a second conductive feature over the substrate. Further, the second gate structure is adjacent to the first gate structure and a top surface of the first conductive feature is coplanar with a top surface of the second conductive feature. 1. A method comprising:forming an active region in a substrate;forming a first gate structure and a second gate structure on the substrate, wherein the second gate structure is adjacent to the first gate structure;forming an insulating layer on the first gate structure and the second gate structure;forming a pair of first spacers on each sidewall of the first gate structure;forming a pair of second spacers on sidewalls of the second gate structure;forming a first conductive feature over the active region;etching a portion of the insulating layer over the first gate structure;etching a portion of the first gate structure; anddepositing a second conductive feature over at least the first gate structure, wherein a portion of a top surface of the second conductive feature is coplanar with a top surface of the insulating layer remaining over the second gate structure.2. The method of further comprising:forming a third conductive feature over the substrate, wherein a top surface of the first conductive feature is coplanar with a top surface of the third conductive feature.3. The method of further comprising:forming a fourth conductive feature, wherein the fourth conductive feature is over the first gate structure or the second gate structure.4. The method of claim 3 , wherein the second conductive ...

Подробнее
02-01-2020 дата публикации

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Номер: US20200006223A1
Принадлежит:

A semiconductor structure includes a conductive structure, a dielectric layer, and a plurality of conductive features. The dielectric layer is present on the conductive structure. The dielectric layer has a plurality of through holes therein, and at least one of the through holes exposes the conductive structure. The conductive features are respectively present in the through holes. At least one of the conductive features has a bottom surface and at least one sidewall. The bottom surface and the sidewall of the conductive feature intersect to form an interior angle. The interior angles of adjacent two of the conductive features have a difference less than or substantially equal to about 3 degrees. 1. A semiconductor structure , comprising:a first dielectric layer over a first source/drain feature and a second source/drain feature;a gate structure disposed between the first source/drain feature and the-a second source/drain feature, wherein a top of the first dielectric layer is at or above a top surface of the gate structure;a second dielectric layer over the first dielectric layer and over the top surface of the gate structure;a first conductive feature extending through the first dielectric layer and the second dielectric layer; anda second conductive feature extending through the second dielectric layer.2. (canceled)3. The semiconductor structure of claim 1 , wherein the top of the first dielectric layer is co-planar with the top surface of the gate structure.4. The semiconductor structure of claim 1 , wherein the first conductive feature overlies the first source/drain feature.5. The semiconductor structure of claim 1 , comprising:a silicide contact between the first source/drain feature and the first conductive feature.6. The semiconductor structure of claim 1 , comprising:a silicide contact, wherein the first source/drain feature contacts a bottom surface of the silicide contact and the first conductive feature contacts a top surface of the silicide contact.7. ...

Подробнее
02-01-2020 дата публикации

Integrated Circuit Interconnect Structures with Air Gaps

Номер: US20200006228A1
Принадлежит:

Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece having an interconnect structure that includes a first conductive feature, a second conductive feature disposed beside the first conductive feature, and an inter-level dielectric disposed between the first conductive feature and the second conductive feature. A conductive material of an etch stop layer is selectively deposited on the first conductive feature and on the second conductive feature without depositing the conductive material on the inter-level dielectric, and the inter-level dielectric is removed to form a gap between the first conductive feature and the second conductive feature. 1. A method of forming an integrated circuit device comprising: a first conductive feature;', 'a second conductive feature disposed beside the first conductive feature; and', 'an inter-level dielectric (ILD) disposed between the first conductive feature and the second conductive feature;, 'receiving a workpiece having an interconnect structure that includesselectively depositing a conductive material of an etch stop layer on the first conductive feature and on the second conductive feature without depositing the conductive material on the ILD; andremoving the ILD to form a gap between the first conductive feature and the second conductive feature.2. The method of claim 1 , wherein the depositing of the conductive material includes performing a treatment on the first conductive feature and the second conductive feature to promote bonding between the conductive material and each of the first conductive feature and the second conductive feature.3. The method of claim 2 , wherein the treatment changes a hydrophilicity of a top surface the first conductive feature based on a hydrophilicity of the conductive material.4. The method of further comprising depositing a dielectric material of the ...

Подробнее
04-01-2018 дата публикации

ELECTROSTATIC DISCHARGE MEMRISTIVE ELEMENT SWITCHING

Номер: US20180006449A1
Принадлежит:

In the examples provided herein, an electrostatic discharge (ESD) recording circuit has a first memristive element coupled to a pin of an integrated circuit. The first memristive element switches from a first resistance to a second resistance when an ESD event occurs at the pin, and the first resistance is less than the second resistance. The ESD recording circuit also has shunting circuitry to shunt energy from an additional ESD event away from the first memristive element. 1. An electrostatic discharge (ESD) recording circuit comprising:first memristive element coupled to a pin of an integrated circuit, wherein the first memristive element switches from a first resistance to a second resistance when an ESD event occurs at the pin, wherein the first resistance is less than the second resistance; andshunting circuitry to shunt energy from an additional ESD event away from the first memristive element.9. The ESD recording circuit of claim 1 , further comprising an electrical vying circuit to apply a reset voltage to the first memristive element to reset the first memristive element to the first resistance.3. The ESD recording circuit of claim 1 , further comprising an electrical reading circuit to determine a resistance of the first memristive element.4. The ESD recording circuit of claim 1 , wherein the shunting circuitry comprises a first resistive element in parallel with the first memristive element that has a third resistance greater than the first resistance and less than the second resistance claim 1 , and further wherein a resistance of the first memristive element is maintained at the second resistance after switching from the first resistance until the resistance is reset to the first resistance.5. The ESD recording circuit of claim w herein the shunting circuitry comprises a first resistive element in parallel with the first memristive element that has a third resistance greater than the first resistance and less than the second resistance claim 1 , and ...

Подробнее
03-01-2019 дата публикации

SEMICONDUCTOR DEVICES, FINFET DEVICES, AND MANUFACTURING METHODS THEREOF

Номер: US20190006244A1
Принадлежит:

Semiconductor devices, fin field effect transistor (FinFET) devices, and methods of manufacturing semiconductor devices are disclosed. In some embodiments, a semiconductor device includes a substrate comprising a first fin and a second fin. A first epitaxial fin is disposed over the first fin, and a second epitaxial fin is disposed over the second fin. The second fin is proximate the first fin. The first epitaxial fin and the second epitaxial fin have an upper portion with a substantially pillar shape. 1. A semiconductor device comprising:a substrate comprising a first fin;an isolation region surrounding a lower portion of the first fin;a first epitaxial fin disposed over the first fin, the first epitaxial fin extending above a top surface of the isolation region;a gate electrode over the first fin and the first epitaxial fin; anda first epitaxial source/drain region on the first fin and adjacent the first epitaxial fin, the first epitaxial source/drain region having a first portion extending above the top surface of the isolation region and a second portion below the top surface of the isolation region, a lowest portion of the first portion of the first epitaxial source/drain region being the widest portion of the first epitaxial source/drain region.2. The semiconductor device of claim 1 , wherein an upper portion of the first portion of the first epitaxial source/drain region has parallel sidewalls.3. The semiconductor device of claim 1 , wherein an upper portion of the first portion of the first epitaxial source/drain region has a first width claim 1 , wherein the second portion of the first epitaxial source/drain region has a second width claim 1 , the second width being less than the first width.4. The semiconductor device of claim 1 , wherein the widest portion of the first epitaxial source/drain region contacts the top surface of the isolation region.5. The semiconductor device of further comprising:a first barrier portion residue disposed under first edges ...

Подробнее
03-01-2019 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20190006246A1
Принадлежит: ROHM CO., LTD.

This semiconductor device comprises: an n-type semiconductor substrate which is connected to an output terminal; a first p-type well which is formed in the n-type semiconductor substrate; a first n-type semiconductor region which is formed in the first p-type well and is connected to a control terminal; and a potential separation part which is connected between the first p-type well and a ground terminal. The potential separation part sets the first p-type well and the ground terminal to a same potential when the output terminal is held at a higher potential than the ground terminal, and sets the first p-type well and the output terminal to a same potential when the output terminal is held at a lower potential than the ground terminal. 1. A semiconductor device comprising:an n-type semiconductor substrate connected to an output terminal;a first p-type well formed in the n-type semiconductor substrate;a first n-type semiconductor region which is formed in the first p-type well and which is connected to a control terminal; anda potential separator connected between the first p-type well and a ground terminal, whereinthe potential separator is configured to give the first p-type well and the ground terminal an equal potential when the output terminal has a potential higher than a potential of the ground terminal, and to give the first p-type well and the output terminal an equal potential when the output terminal has a potential lower than the potential of the ground terminal.2. The semiconductor device of claim 1 , wherein the potential separator has:a second p-type well which is formed in the n-type semiconductor substrate and which is connected to the ground terminal; anda second n-type semiconductor region formed in the second p-type well, wherein the first p-type well and the second n-type semiconductor region are connected to the ground terminal via a shared resistor.3. A semiconductor device comprising:an n-type semiconductor substrate connected to an output ...

Подробнее
03-01-2019 дата публикации

Power Gating for Three Dimensional Integrated Circuits (3DIC)

Номер: US20190006346A1

A device comprises a first interconnect structure over a first active device layer, a first power circuit in the first active device layer, a second active device layer over and in contact with the first interconnect structure, a first switch in the second active device layer, a second interconnect structure over and in contact with the second active device layer, a third active device layer over and in contact with the second interconnect structure, a second power circuit in the third active device layer and a third interconnect structure over and in contact with the third active device layer and connected to a power source, wherein the power source is configured to provide power to the first power circuit through the first switch.

Подробнее
03-01-2019 дата публикации

PASSIVE DEVICE STRUCTURE AND METHODS OF MAKING THEREOF

Номер: US20190006350A1
Автор: Liu Bingwu, Zang Hui
Принадлежит:

Structures for a passive device of an integrated circuits and associated fabrication methods. A semiconductor substrate having raised fins and an dielectric isolation layer between the fins is formed. An etch stop layer is formed over the dielectric isolation layer between fins of a passive device. An interlayer dielectric layer is formed over the fins and etch stop layer. The interlayer dielectric layer is selectively etched to form an opening for conductive contact to the fins, where the etch stop layer prevents etching of the dielectric isolation layer. A conductive contact is formed to contact the plurality of fins, with the conductive contact terminating at the etch stop layer. 1. A structure comprising:a dielectric isolation layer;a conformal dielectric layer disposed on the dielectric isolation layer;a passive device including a semiconductor body and a plurality of fins extending from the semiconductor body through the dielectric isolation layer and through the conformal dielectric layer; anda first conductive contact disposed on the plurality of fins and the conformal dielectric layer, the first conductive contact connected with the plurality of fins and terminating at the conformal dielectric layer between the plurality of fins.2. The structure of wherein the passive device includes a semiconductor body over a semiconductor substrate claim 1 , a well formed in the semiconductor body claim 1 , and a doped region within the well claim 1 , the well has a first conductivity type claim 1 , the doped region has a second conductivity type opposite the first conductivity type claim 1 , the doped region and the well adjoin along a p-n junction claim 1 , the doped region is disposed between the plurality of fins and the well claim 1 , and the plurality of fins are connected with the doped region.3. The structure of wherein the plurality of fins have the second conductivity type.4. The structure of wherein the conformal dielectric layer is a nitride material claim 1 ...

Подробнее
02-01-2020 дата публикации

High density capacitor implemented using finfet

Номер: US20200006467A1

A first and a second gate structure each extend in a first direction. A first and a second conductive contact extend in the first direction and are separated from the first and second gate structures in a second direction. A first isolation structure extends in the second direction and separates the first gate structure from the second gate structure. A second isolation structure extends in the second direction and separates the first conductive contact from the second conductive contact. The first gate structure is electrically coupled to a first electrical node. The second gate structure is electrically coupled to a second electrical node different from the first electrical node. The first conductive contact is electrically coupled to the second electrical node. The second conductive contact is electrically coupled to the first electrical node.

Подробнее
03-01-2019 дата публикации

Field effect transistor devices having gate contacts formed in active region overlapping source/drain contacts

Номер: US20190006515A1
Автор: Kangguo Cheng, Peng Xu
Принадлежит: International Business Machines Corp

Semiconductor devices and methods are provided to fabricate FET devices having overlapping gate and source/drain contacts while preventing electrical shorts between the overlapping gate and source/drain contacts. For example, a semiconductor device includes a FET device, a vertical source/drain contact, a source/drain contact capping layer, and a vertical gate contact. The FET device includes a source/drain layer, and a gate structure. The vertical source/drain contact is formed in contact with a source/drain layer of the FET device. The source/drain contact capping layer is formed on an upper surface of the vertical source/drain contact. The vertical gate contact is formed in contact with a gate electrode layer of the gate structure. A portion of the vertical gate contact overlaps a portion of the vertical source/drain contact, wherein the source/drain contact capping layer electrically insulates the overlapping portions of the vertical gate and source/drain contacts.

Подробнее
02-01-2020 дата публикации

Structure and Method for FinFET Device with Asymmetric Contact

Номер: US20200006563A1
Автор: LIAW Jhon Jhy
Принадлежит:

The present disclosure provides one embodiment of a method of forming an integrated circuit structure. The method includes forming a shallow trench isolation (STI) structure in a semiconductor substrate of a first semiconductor material, thereby defining a plurality of fin-type active regions separated from each other by the STI structure; forming gate stacks on the fin-type active regions; forming an inter-layer dielectric (ILD) layer filling in gaps between the gate stacks; patterning the ILD layer to form a trench between adjacent two of the gate stacks; depositing a first dielectric material layer that is conformal in the trench; filling the trench with a second dielectric material layer; patterning the second dielectric material layer to form a contact opening; and filling a conductive material in the contact opening to form a contact feature. 1. A semiconductor structure , comprising:an active region on a semiconductor substrate;a gate stack disposed on the active region;an elongated contact feature landing on a source/drain feature; anda first dielectric material layer disposed on sidewalls of the contact feature and free from ends of the elongated contact feature, wherein the sidewalls of the elongated contact feature are parallel with the gate stack.2. The semiconductor structure of claim 1 , whereinthe gate stack includes a gate dielectric feature, a gate electrode on the gate dielectric feature, and a spacer on sidewalls of the gate electrode; andthe first dielectric material layer is interposed between the spacer and the contact feature and directly contacts the spacer and the contact feature.3. The semiconductor structure of claim 2 , wherein the gate dielectric feature includes a first high k dielectric material and the first dielectric material layer includes a second high-k dielectric material different from the first high k dielectric material in composition.4. The semiconductor structure of claim 3 , wherein the dielectric material layer is ...

Подробнее
20-01-2022 дата публикации

Back Biasing of FD-SOI Circuit Block

Номер: US20220020741A1
Принадлежит:

A microelectronic circuit structure comprises a stack of bonded layers comprising a bottom layer and at least one upper layer. At least one of the upper layers comprises an oxide layer having a back surface and a front surface closer to the bottom layer than the back surface, and a plurality of FD-SOI transistors built on the from surface. At least a first back gate line and a second back gate line extend separate from each other above the back surface for independently providing a first back gate bias to a first group of transistors and a second back gate bias to a second different group of transistors. 1. A microelectronic circuit structure comprising:a stack of bonded layers including a bottom layer and at least one upper layer through direct bonding interconnect (DBI), the at least one upper layer comprising an oxide layer having a back surface and a front surface closer to the bottom layer than the back surface;a plurality of fully depleted silicon-on-insulator (FD-SOI) transistors built on the front surface of the oxide layer; anda plurality of back gate lines on the back surface of the oxide layer configured to provide back gate bias to the plurality of FD-SOI transistors, wherein each back gate line is electrically connected to a metal of an interconnection separated from the back gate lines by a passivation layer, wherein each back gate line is electrically connected to the metal through a single conductive pathway in the passivation layer.2. The microelectronic circuit structure of claim 1 , wherein the metal is disposed on an upper surface of the passivation layer.3. The microelectronic circuit structure of claim 1 , wherein at least one of the back gate line extends on the back surface of the oxide layer corresponding to multiple FD-SOI transistors and provides the same back gate bias to the multiple FD-SOI transistors.4. The microelectronic circuit structure of claim 1 , further comprising:a group of FD-SOI transistors of the plurality of FD-SOI ...

Подробнее
12-01-2017 дата публикации

Interconnect structures and fabrication method thereof

Номер: US20170011966A1
Автор: Yihua Shen, Yunchu Yu

An interconnect structure is provided. The interconnect structure includes a substrate; and at least a first interconnect component having a first contact region and a second interconnect component having a second contact region. The interconnect structure also includes an interlayer dielectric layer formed on the semiconductor substrate at a same layer as the first interconnect component and the second interconnect component. Further, the interconnect structure includes an interconnect line layer electrically connecting the first contact region and the second contact region formed inside the interlayer dielectric layer.

Подробнее
12-01-2017 дата публикации

SEMICONDUCTOR DEVICE AND METHOD FOR FILLING PATTERNS

Номер: US20170012033A1
Принадлежит:

A semiconductor device is disclosed. The semiconductor device includes: a substrate having a cell region defined thereon, in which the cell region includes a first edge and a second edge extending along a first direction; and a plurality of patterns on the substrate extending along the first direction, in which the patterns includes a plurality of first patterns and a plurality of second patterns, and one of the first patterns closest to the first edge and one of the second patterns closest to the second edge are different. 1. A semiconductor device , comprising:a substrate having a cell region defined thereon, wherein the cell region comprises a first edge and a second edge extending along a first direction; anda plurality of patterns on the substrate extending along the first direction, wherein the patterns comprises a plurality of first patterns and a plurality of second patterns, an edge of the plurality of first patterns is aligned with an edge of the plurality of second patterns along a second direction, and one of the first patterns closest to the first edge and one of the second patterns closest to the second edge are different.2. The semiconductor device of claim 1 , wherein the patterns comprise gate patterns and contact plug patterns.3. The semiconductor device of claim 1 , wherein the first patterns comprise gate patterns and the second patterns comprise contact plug patterns.4. The semiconductor device of claim 1 , wherein the first patterns comprise contact plug patterns and the second patterns comprise gate patterns.5. The semiconductor device of claim 1 , further comprising a plurality of fin-shaped structures extending along a second direction intersecting part of the patterns.6. The semiconductor device of claim 5 , wherein each of the fin-shaped structures comprises a first end and a second end claim 5 , and the quantity of the patterns between the pattern contacting the first end and the first edge and the quantity of the patterns between the ...

Подробнее
12-01-2017 дата публикации

BRIDGING LOCAL SEMICONDUCTOR INTERCONNECTS

Номер: US20170012061A1
Принадлежит:

A semiconductor device includes a plurality of gates formed upon a semiconductor substrate that includes a plurality of outer active areas (e.g. CMOS/PMOS areas, source/drain regions, etc.) and one or more inner active areas. An isolator is formed upon one or more inner gates associated with the one or more inner active areas. A contact bar electrically connects the outer active areas and/or outer gates and is formed upon the isolator. The isolator electrically insulates the contact bar from the one or more inner active areas and/or the one or more inner gates. 1. A semiconductor device comprising:a plurality of transistor gates comprising one or more inner gates and a plurality of outer gates, the plurality of transistor gates at least directly upon a buried-dielectric layer of a semiconductor substrate, the semiconductor substrate comprising a plurality of outer active areas and one or more inner active areas, wherein the plurality of outer active areas are of opposite polarity relative to at least one inner active area;an isolator directly upon the one or more inner gates associated with the one or more inner active areas and offset from the plurality of outer active areas, the isolator comprising a protective barrier portion directly upon a dielectric layer, the dielectric layer directly upon the one or more inner gates; anda monolithic contact bar electrically connecting the plurality of outer active areas, the monolithic contact bar directly upon the protective barrier portion, wherein the isolator electrically insulates the monolithic contact bar from the one or more inner gates.2. The semiconductor device of claim 1 , wherein the isolator also insulates the monolithic contact bar from the one or more inner active areas.3. The semiconductor device of claim 1 , further comprising an interlayer dielectric claim 1 , wherein a top surface of the monolithic contact bar and a top surface of the interlayer dielectric are coplanar.4. The semiconductor device of claim ...

Подробнее
10-01-2019 дата публикации

Design layouts for connecting contacts with metal tabs or vias

Номер: US20190012422A1
Принадлежит: Globalfoundries Inc

The present disclosure relates to methodologies for designing semiconductor structures, and, more particularly, creating a methodology to connect contacts of semiconductor elements to a metal line using marker tabs to reserve space for future connections between the contacts and the metal line, and then reassigning the marker tabs to connections between the contacts and the metal line on different levels of a metal stack formed over the semiconductor elements.

Подробнее
11-01-2018 дата публикации

METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES

Номер: US20180012775A1
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

In a method of manufacturing a semiconductor memory device, a plurality of first conductive structures including a first conductive pattern and a hard mask are sequentially stacked on a substrate. A plurality of preliminary spacer structures including first spacers, sacrificial spacers and second spacers are sequentially stacked on sidewalls of the conductive structures. A plurality of pad structures are formed on the substrate between the preliminary spacer structures, and define openings exposing an upper portion of the sacrificial spacers. A first mask pattern is formed to cover surfaces of the pad structures, and expose the upper portion of the sacrificial spacers. The sacrificial spacers are removed to form first spacer structures having respective air spacers, and the first spacer structures include the first spacers, the air spacers and the second spacers sequentially stacked on the sidewalls of the conductive structures. 1. A method of manufacturing a semiconductor device , the method comprising:forming a plurality of conductive structures on a substrate, each of the conductive structures including a first conductive pattern and a hard mask sequentially stacked;forming a plurality of preliminary spacer structures on sidewalls of the conductive structures, respectively, the preliminary spacer structures including first spacers, sacrificial spacers and second spacers sequentially stacked;forming a plurality of pad structures on the substrate between the preliminary spacer structures, respectively, the plurality of pad structures defining openings exposing upper portions of the sacrificial spacers;forming a first mask pattern on the pad structures, the first mask pattern covering surfaces of the pad structures and exposing the upper portions of the sacrificial spacers; andremoving the sacrificial spacers to form first spacer structures having respective air spacers, the first spacer structures including the first spacers, the air spacers and the second spacers ...

Подробнее
11-01-2018 дата публикации

SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF

Номер: US20180012807A1
Принадлежит:

A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a third metal connect in contact with a first metal connect in a first active region and a second metal connect in a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes forming a first opening over the first metal connect, the STI region, and the second metal connect, and forming the third metal connect in the first opening. Forming the third metal connect over the first metal connect and the second metal connect mitigates RC coupling. 1. A semiconductor device , comprising:a first metal connect overlying a first active region;a second metal connect overlying a second active region;a gate overlying the first active region and the second active region; and a longest dimension of the gate extends in a first direction, and', 'a longest dimension of the third metal connect extends in the first direction., 'a third metal connect overlying the first metal connect and the second metal connect and electrically coupling the first metal connect to the second metal connect, wherein2. The semiconductor device of claim 1 , further comprising a first dielectric layer disposed between the first metal connect and the second metal connect and disposed between the first metal connect and the gate.3. The semiconductor device of claim 2 , further comprising a second dielectric layer overlying the first dielectric layer claim 2 , wherein the third metal connect is in contact with the second dielectric layer.4. The semiconductor device of claim 1 , wherein the first metal connect and the third metal connect overlie a first source/drain region of the first active region.5. The semiconductor device of claim 1 , further comprising:a metal contact in contact with the gate; anda first dielectric layer disposed between the metal contact and the ...

Подробнее
11-01-2018 дата публикации

SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF

Номер: US20180012808A1
Принадлежит:

A method for fabricating a semiconductor device is provided. A substrate having a dummy gate thereon is prepared. A spacer is disposed on a sidewall of the dummy gate. A source/drain region is disposed adjacent to the dummy gate. A sacrificial layer is then formed on the source/drain region. A cap layer is then formed on the sacrificial layer. A top surface of the cap layer is coplanar with a top surface of the dummy gate. A replacement metal gate (RMG) process is performed to transform the dummy gate into a replacement metal gate. An opening is then formed in the cap layer to expose a top surface of the sacrificial layer. The sacrificial layer is removed through the opening, thereby forming a lower contact hole exposing a top surface of the source/drain region. A lower contact plug is then formed in the lower contact hole. 1: A method for fabricating a semiconductor device , comprising:providing a substrate having a dummy gate thereon, a spacer on a sidewall of the dummy gate, and a source/drain region adjacent to the dummy gate;forming a sacrificial layer on the source/drain region;forming a cap layer on the sacrificial layer, wherein a top surface of the cap layer is coplanar with a top surface of the dummy gate;performing a replacement metal gate (RMG) process to transform the dummy gate into a replacement metal gate;forming an opening in the cap layer to expose a top surface of the sacrificial layer;removing the sacrificial layer through the opening to thereby form a lower contact hole exposing a top surface of the source/drain region; andforming a lower contact plug in the lower contact hole.2: The method for fabricating a semiconductor device according to claim 1 , further comprising:depositing an inter-layer dielectric (ILD) layer on the replacement metal gate, the cap layer, and the lower contact plug; andforming an upper contact plug in the ILD layer, wherein the upper contact plug is electrically connected to the lower contact plug.3: The method for ...

Подробнее
11-01-2018 дата публикации

METHOD AND APPARATUS FOR PLACING A GATE CONTACT INSIDE AN ACTIVE REGION OF A SEMICONDUCTOR

Номер: US20180012887A1
Принадлежит: GLOBALFOUNDRIES INC.

A method provides a structure having a FinFET in an Rx region, the FinFET including a channel, source/drain (S/D) regions and a gate, the gate including gate metal. A cap is formed over the gate having a liner and a core. Trench silicide (TS) is disposed on sides of the gate. The TS is recessed to a level above a level of the gate and below a level of the core. The liner is etched to the level of the TS. An oxide layer is disposed over the structure. A CB trench is patterned into the oxide layer within the Rx region to expose the core at a shelf portion of the CB trench. The core is etched to extend the CB trench to a bottom at the gate metal. The shelf portion having a larger area than the bottom. The CB trench is metalized to form a CB contact. 1. A method comprising:providing a structure having a FinFET disposed in an Rx region, the FinFET including a channel disposed between a pair of source/drain (S/D) regions and a gate (CB) disposed over the channel, the gate including gate metal disposed between gate spacers;forming a cap over the gate, the cap having an outer liner disposed around an inner core;forming trench silicide (TS) layers on opposing sides of the gate over the S/D regions;recessing the TS layers to a level above a level of the gate and below a level of the core;etching the liner down to a level proximate the level of the TS layers;disposing an oxide layer over the structure;patterning a CB trench into the oxide layer to expose the core at a shelf portion of the CB trench, the CB trench located within the Rx region;etching the core to further extend the CB trench to a trench bottom and to expose the gate metal, the shelf portion of the CB trench having a larger area than the trench bottom; andmetallizing the CB trench to form a CB contact electrically connected to the gate metal.2. The method of wherein the cap outer liner has a first material composition and the cap inner core has a second material composition different from the first material ...

Подробнее
15-01-2015 дата публикации

Sense amplifier layout for finfet technology

Номер: US20150015335A1

A sense amplifier (SA) comprises a semiconductor substrate having an oxide definition (OD) region, a pair of SA sensing devices, a SA enabling device, and a sense amplifier enabling signal (SAE) line for carrying an SAE signal. The pair of SA sensing devices have the same poly gate length Lg as the SA enabling device, and they all share the same OD region. When enabled, the SAE signal turns on the SA enabling device to discharge one of the pair of SA sensing devices for data read from the sense amplifier.

Подробнее
10-01-2019 дата публикации

CONTACTING SOURCE AND DRAIN OF A TRANSISTOR DEVICE

Номер: US20190013241A1
Принадлежит:

A method of manufacturing a semiconductor device is provided including forming raised source and drain regions on a semiconductor layer, forming a first insulating layer over the semiconductor layer, forming a first contact to one of the source and drain regions in the first insulating layer, forming a second insulating layer over the first contact, forming a trench in the second insulating layer to expose the first contact, removing a portion of the first contact below the trench, thereby forming a recessed surface of the first contact, removing a portion of the first insulating layer, thereby forming a recess in the trench and exposing a portion of a sidewall of the first contact below the recessed surface of the first contact, and filling the trench and the recess formed in the trench with a contact material to form a second contact in contact with the first contact. 1. A method of manufacturing a semiconductor device , comprising:forming raised source and drain regions on a semiconductor layer;forming a first insulating layer over said semiconductor layer;forming a first contact to one of said raised source and drain regions in said first insulating layer;forming a second insulating layer over and above said first contact after forming said first contact;forming a trench in said second insulating layer to remove a portion of said second insulating layer and expose said first contact, wherein said forming of said trench in said second insulating layer comprises a first reactive ion etching;performing a first etching process through said trench to remove a portion of said first contact exposed below said trench, thereby forming a recessed surface of said first contact lower than an uppermost surface of said first contact, wherein said first etching process comprises a second reactive ion etching;removing a portion of said first insulating layer exposed by said trench to form a recess in said first insulating layer, said recess exposing a portion of a sidewall of ...

Подробнее
10-01-2019 дата публикации

GATE NETWORKS HAVING POSITIVE TEMPERATURE COEFFICIENTS OF RESISTANCE (PTC) FOR SEMICONDUCTOR POWER CONVERSION DEVICES

Номер: US20190013311A1
Принадлежит:

A gate network of a silicon-carbide (SiC) power conversion device includes a plurality of gate electrodes of SiC metal-oxide-semiconductor-based (MOS-based) transistor device cells disposed in an active area of the SiC power conversion device, and a gate pad disposed in a gate pad and bus area of the SiC power conversion device. The gate network also includes a gate bus disposed in the gate pad and bus area of the SiC power conversion device, wherein the gate bus extends between and electrically connects the gate pad to at least a portion of the plurality of gate electrodes in the active area of the SiC power conversion device. At least a portion of the gate pad, the gate bus, the plurality of gate electrodes, or a combination thereof, of the gate network have a positive temperature coefficient of resistance greater than approximately 2000 parts-per-million per degree Celsius (ppm/° C.). 1. A silicon-carbide (SiC) power conversion device , comprising: a plurality of gate electrodes of a respective plurality of SiC metal-oxide-semiconductor-based (MOS-based) transistor device cells disposed in an active area of the SiC power conversion device;', 'a gate pad disposed in a gate pad and bus area of the SiC power conversion device;', 'a gate bus disposed in the gate pad and bus area of the SiC power conversion device, wherein the gate bus extends between and electrically connects the gate pad to at least a portion of the plurality of gate electrodes in the active area of the SiC power conversion device, wherein at least a portion of the gate pad, the gate bus, the plurality of gate electrodes, or a combination thereof, of the gate network have a positive temperature coefficient of resistance greater than approximately 2000 parts-per-million per degree Celsius (ppm/° C.)., 'a gate network, including2. The device of claim 1 , wherein the positive temperature coefficient of resistance is greater than approximately 2250 ppm/° C.3. The device of claim 2 , wherein the positive ...

Подробнее
10-01-2019 дата публикации

Integrated circuit device and method of manufacturing the same

Номер: US20190013314A1
Принадлежит: SAMSUNG ELECTRONICS CO LTD

An integrated circuit device may include a fin-type active region extending in a first direction on a substrate; an insulating separation structure extending in a second direction that intersects the first direction on the fin-type active region; a pair of split gate lines spaced apart from each other with the insulating separation structure therebetween and extending in the second direction to be aligned with the insulating separation structure; a pair of source/drain regions located on the fin-type active region and spaced apart from each other with the insulating separation structure therebetween; and a jumper contact located over the insulating separation structure and connected between the pair of source/drain regions.

Подробнее
10-01-2019 дата публикации

DAMASCENE-BASED APPROACHES FOR EMBEDDING SPIN HALL MTJ DEVICES INTO A LOGIC PROCESSOR AND THE RESULTING STRUCTURES

Номер: US20190013354A1
Автор: Lee Kevin J., Wang Yih
Принадлежит:

Damascene-based approaches for embedding spin hall MTJ devices into a logic processor, and the resulting structures, are described. In an example, a logic processor includes a logic region including a metallization layer. The logic processor also includes a memory array including a plurality of two-transistor one magnetic tunnel junction (MTJ) spin hall effect electrode (2T-1MTJ SHE electrode) bit cells. The spin hall effect electrodes of the 2T-1MTJ SHE electrode bit cells are disposed in a lower dielectric layer laterally adjacent to the metallization layer of the logic region. The MTJs of the 2T-1MTJ SHE electrode bit cells are disposed in an upper dielectric layer laterally adjacent to the metallization layer of the logic region. 1. A logic processor , comprising:a logic region comprising a metallization layer; anda memory array comprising a plurality of two-transistor one magnetic tunnel junction (MTJ) spin hall effect electrode (2T-1MTJ SHE electrode) bit cells, wherein the spin hall effect electrodes of the 2T-1MTJ SHE electrode bit cells are disposed in a lower dielectric layer laterally adjacent to the metallization layer of the logic region, and the MTJs of the 2T-1MTJ SHE electrode bit cells are disposed in an upper dielectric layer laterally adjacent to the metallization layer of the logic region.2. The logic processor of claim 1 , wherein the memory array comprises an insulating spacer layer disposed adjacent to sidewalls of the MTJs of the 2T-1MTJ SHE electrode bit cells and across a top surface of the spin hall effect electrodes of the 2T-1MTJ SHE electrode bit cells.3. The logic processor of claim 1 , wherein the insulating spacer layer extends across a top surface of the lower dielectric layer.4. The logic processor of claim 1 , wherein a top surface of the spin hall effect electrodes of the 2T-1MTJ SHE electrode bit cells is co-planar with a top surface of the lower dielectric layer.5. The logic processor of claim 1 , wherein the metallization ...

Подробнее
14-01-2021 дата публикации

SEMICONDUCTOR DEVICE WITH ELONGATED PATTERN

Номер: US20210013103A1

A semiconductor device includes a semiconductor substrate, a source/drain region, a source/drain contact, a conductive via and a first polymer layer. The source/drain region is in the semiconductor substrate. The source/drain contact is over the source/drain region. The source/drain via is over the source/drain contact. The first polymer layer extends along a first sidewall of the conductive via and is separated from a second sidewall of the conductive via substantially perpendicular to the first sidewall of the conductive via. 1. A semiconductor device , comprising:a semiconductor substrate;a source/drain region in the semiconductor substrate;a source/drain contact over the source/drain region;a conductive via over the source/drain contact; anda first polymer layer extending along a first sidewall of the conductive via and separated from a second sidewall of the conductive via substantially perpendicular to the first sidewall of the conductive via.2. The semiconductor device of claim 1 , further comprising:an etch stop layer around the conductive via, wherein the first polymer layer has a bottom end separated from the source/drain contact by the etch stop layer.3. The semiconductor device of claim 1 , wherein the conductive via has a bottom end lower than a bottom end of the first polymer layer.4. The semiconductor device of claim 1 , wherein from a top view the first sidewall of the conductive via extends past opposite edges of the first polymer layer.5. The semiconductor device of claim 1 , wherein the first sidewall of the conductive via is longer than the second sidewall of the conductive via from a top view.6. The semiconductor device of claim 1 , wherein the second sidewall of the conductive via is more curved than the first sidewall of the conductive via from a top view.7. The semiconductor device of claim 1 , further comprising:a gate stack over the semiconductor substrate;a gate contact over the gate stack; anda second polymer layer extending along a first ...

Подробнее
14-01-2021 дата публикации

VERTICAL FIELD EFFECT TRANSISTOR REPLACEMENT METAL GATE FABRICATION

Номер: US20210013106A1
Принадлежит:

A method for fabricating a semiconductor device includes forming a semiconductor structure including a substrate, a first vertical fin and a second vertical fin longitudinally spaced from the first vertical fin with each of the first and second vertical fin having a hardmask cap, and a bottom spacer layer on the substrate. The method further includes forming first and second bottom source/drains within the substrate respectively beneath the first and second vertical fins, forming first and second top source/drains respectively on the first and second vertical fins, forming a vertical oxide pillar between the first and second vertical fins, removing a portion of the oxide pillar to reduce a cross-sectional dimension to define a lower recessed region, and depositing a metal gate material about the first and second vertical fins wherein portions of the metal gate material are disposed within the recessed region of the oxide pillar. 1. A method for fabricating a semiconductor device , comprising:forming a semiconductor structure, including a substrate defining a longitudinal axis, a first vertical fin and a second vertical fin longitudinally spaced from the first vertical fin, each of the first and second vertical fins having a hardmask cap and a bottom spacer layer on the substrate;forming a first bottom source/drain within the substrate beneath the first vertical fin and a second bottom source/drain within the substrate beneath the second vertical fin;forming a first top source/drain on the first vertical fin and a second top source/drain on the second vertical fin;forming a vertical oxide pillar between the first and second vertical fins;removing a portion of the oxide pillar to reduce a cross-sectional dimension of a lower end of the oxide pillar to define a recessed region of the oxide pillar; anddepositing a metal gate material about the first and second vertical fins wherein portions of the metal gate material are disposed within the recessed region of the oxide ...

Подробнее
14-01-2021 дата публикации

STANDARD CELL AND AN INTEGRATED CIRCUIT INCLUDING THE SAME

Номер: US20210013149A1
Принадлежит:

An integrated circuit including: a power rail including first and second conductive lines spaced apart from each other in a vertical direction, wherein the first and second conductive lines extend in parallel to each other in a first horizontal direction, and are electrically connected to each other, to supply power to a first standard cell, wherein the first and second conductive lines are disposed at a boundary of the first standard cell; and a third conductive line between the first and second conductive lines and extending in a second horizontal direction orthogonal to the first horizontal direction, to transfer an input signal or an output signal of the first standard cell. 1. An integrated circuit , comprising:a plurality of standard cells, each comprising at least one active region extending in a first direction, at least one gate line extending in a second direction and at least one pattern formed in a first conductive layer; anda plurality of power rails extending in the first direction along boundaries of the plurality of standard cells,wherein a first power rail of the plurality of power rails comprises a first pattern formed in a second conductive layer upper than the first conductive layer and extending in the first direction along a boundary of a first standard cell of the plurality of standard cells, anda length of the first pattern in the first direction is less than a length of the first standard cell in the first direction.2. The integrated circuit of claim 1 , wherein the first standard cell comprises a plurality of second patterns formed in the second conductive layer and extending in the second direction claim 1 ,each of the plurality of second patterns has a first width and is spaced apart from an adjacent second pattern by a first distance in the first direction, andthe length of the first pattern is greater than a sum of the first width and the first distance.3. The integrated circuit of claim 2 , wherein the length of the first pattern is ...

Подробнее
14-01-2021 дата публикации

SEMICONDUCTOR DEVICE WITH TRANSISTOR LOCAL INTERCONNECTS

Номер: US20210013150A1
Принадлежит:

A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate. The first transistor and a second transistor are formed on the semiconductor substrate. Each transistor comprises a source, a drain, and a gate. The gate of the first transistor extends longitudinally as part of a first linear strip and the gate of the second transistor extends longitudinally as part of the second linear strip parallel to and spaced apart from the first linear strip. A first CB layer forms a local interconnect layer electrically connected to the gate of the first transistor. A second CB layer forms a local interconnect layer electrically connected to the gate of the second transistor. A CA layer forms a local interconnect layer extending longitudinally between a first end and a second end of the CA layer. The CA layer is electrically connected to the first and second CB layers. The first CB layer is electrically connected adjacent the first end of the CA layer and the second layer is electrically connected adjacent the second end of the CA layer. The first CB layer, the second CB layer and the CA layer are disposed between a first metal layer and the semiconductor substrate. The first metal layer being disposed above each source, each drain, and each gate of the first and second transistors. The CA layer extends substantially parallel to the first and second linear strips and is substantially perpendicular to the first and second CB layers. At least one via selectively provides an electrical connection between the CA or CB layers and the at least one metal layer. 1. A semiconductor device comprising:a semiconductor substrate;a first transistor and a second transistor formed on the semiconductor substrate, wherein each transistor comprises a source, a drain, and a gate, wherein the gate of the first transistor extends longitudinally as part of a first linear strip and wherein the gate of the second transistor ...

Подробнее
14-01-2021 дата публикации

High Density Capacitor Implemented Using FinFET

Номер: US20210013300A1
Принадлежит:

A first and a second gate structure each extend in a first direction. A first and a second conductive contact extend in the first direction and are separated from the first and second gate structures in a second direction. A first isolation structure extends in the second direction and separates the first gate structure from the second gate structure. A second isolation structure extends in the second direction and separates the first conductive contact from the second conductive contact. The first gate structure is electrically coupled to a first electrical node. The second gate structure is electrically coupled to a second electrical node different from the first electrical node. The first conductive contact is electrically coupled to the second electrical node. The second conductive contact is electrically coupled to the first electrical node. 1. A method , comprising:forming a plurality of gate structures that each extend in a first direction;forming a plurality of conductive contacts that each extend in the first direction, wherein the gate structures and the conductive contacts are spaced apart from one another in a second direction different from the first direction;forming an opening in each of the gate structures;filling the opening with one or more dielectric materials; andforming a capacitor at least in part using the gate structures, the conductive contacts, and the one or more dielectric materials.2. The method of claim 1 , wherein the forming the capacitor comprises:electrically coupling a first subset of the gate structures and a first subset of the conductive contacts with a first electrical node; andelectrically coupling a second subset of the gate structures and a second subset of the conductive contacts with a second electrical node that is different than the first electrical node.3. The method of claim 2 , further comprising:applying a first electrical signal to the first electrical node; andapplying a second electrical signal to the second ...

Подробнее
14-01-2021 дата публикации

PLUGS FOR INTERCONNECT LINES FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION

Номер: US20210013323A1
Принадлежит:

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An isolation structure surrounds a lower fin portion, the isolation structure comprising an insulating material having a top surface, and a semiconductor material on a portion of the top surface of the insulating material, wherein the semiconductor material is separated from the fin. A gate dielectric layer is over the top of an upper fin portion and laterally adjacent the sidewalls of the upper fin portion, the gate dielectric layer further on the semiconductor material on the portion of the top surface of the insulating material. A gate electrode is over the gate dielectric layer. 1. A method of fabricating integrated circuit structure , the method comprising:forming a line trench in an upper portion of an interlayer dielectric (ILD) material layer formed above an underlying metallization layer;forming a via trench in a lower portion of the ILD material layer, the via trench exposing a metal line of the underlying metallization layer;forming a sacrificial material above the ILD material layer and in the line trench and the via trench;patterning the sacrificial material to form an opening to break a continuity of the sacrificial material in the line trench;filling the opening in the sacrificial material with a dielectric material to form a dielectric plug having an upper surface above an upper surface of the ILD material;removing the sacrificial material and leaving the dielectric plug to remain;filling the line trench and the via trench with a conductive material; andplanarizing the dielectric plug and the conductive material to provide a planarized dielectric plug breaking a continuity of the conductive material in the line trench.2. The method of claim 1 , wherein filling the opening ...

Подробнее
09-01-2020 дата публикации

Array Of Gated Devices And Methods Of Forming An Array Of Gated Devices

Номер: US20200013669A1
Принадлежит: MICRON TECHNOLOGY, INC.

An array of gated devices includes a plurality of gated devices arranged in rows and columns and individually including an elevationally inner region, a mid region elevationally outward of the inner region, and an elevationally outer region elevationally outward of the mid region. A plurality of access lines are individually laterally proximate the mid regions along individual of the rows. A plurality of data/sense lines are individually elevationally outward of the access lines and electrically coupled to the outer regions along individual of the columns. A plurality of metal lines individually extends along and between immediately adjacent of the rows elevationally inward of the access lines. The individual metal lines are directly against and electrically coupled to sidewalls of the inner regions of each of immediately adjacent of the rows. The metal lines are electrically isolated from the data/sense lines. Other arrays of gated devices and methods of forming arrays of gated devices are disclosed. 121-. (cancelled)22. An array of gated devices , comprising:a plurality of gated devices arranged in rows and columns and individually comprising an elevationally inner region, a mid region elevationally outward of the inner region, and an elevationally outer region elevationally outward of the mid region;a plurality of access lines that individually are laterally proximate the mid regions along individual of the rows;a plurality of data/sense lines that individually are elevationally outward of the access lines and electrically coupled to the outer regions along individual of the columns; anda plurality of metal lines that individually longitudinally extend along and between immediately adjacent of the rows elevationally inward of the access lines, the individual metal lines being directly against and electrically coupled to sidewalls of the inner regions of each of immediately adjacent of the rows, the metal lines being electrically isolated from the data/sense lines ...

Подробнее
09-01-2020 дата публикации

INTEGRATED CIRCUIT STRUCTURE TO REDUCE SOFT-FAIL INCIDENCE AND METHOD OF FORMING SAME

Номер: US20200013678A1
Принадлежит:

This disclosure is directed to an integrated circuit (IC) structure. The IC structure may include a semiconductor structure including two source/drain regions; a metal gate positioned on the semiconductor structure adjacent to and between the source/drain regions; a metal cap with a different metal composition than the metal gate and having a thickness in the range of approximately 0.5 nanometer (nm) to approximately 5 nm positioned on the metal gate; a first dielectric cap layer positioned above the semiconductor structure; an inter-layer dielectric (ILD) positioned above the semiconductor structure and laterally abutting both the metal cap and the metal gate, wherein an upper surface of the ILD has a greater height above the semiconductor structure than an upper surface of the metal gate; a second dielectric cap layer positioned on the ILD and above the metal cap; and a contact on and in electrical contact with the metal cap. 1. An integrated circuit (IC) structure comprising:a semiconductor structure;a first source/drain region formed in the semiconductor structure;a second source/drain region formed in the semiconductor structure;a metal gate positioned on the semiconductor structure adjacent to and between the first source/drain region and the second source/drain region, the metal gate including a first metal;a metal cap positioned on the metal gate, wherein the metal cap has a different metal composition than the first metal, and wherein the metal cap has a thickness in the range of approximately 0.5 nanometer (nm) to approximately 5 nm;a first dielectric cap layer positioned on at least a portion of the semiconductor structure;a first inter-layer dielectric (ILD) positioned above the semiconductor structure and laterally abutting both the metal cap and the metal gate, wherein a height of an upper surface of the first ILD above the semiconductor structure is greater than a height of an upper surface of the metal gate above the semiconductor structure;a second ...

Подробнее
09-01-2020 дата публикации

Fin cut and fin trim isolation for advanced integrated circuit structure fabrication

Номер: US20200013876A1
Принадлежит: Intel Corp

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. A first isolation structure separates a first end of a first portion of the fin from a first end of a second portion of the fin, the first end of the first portion of the fin having a depth. A gate structure is over the top of and laterally adjacent to the sidewalls of a region of the first portion of the fin. A second isolation structure is over a second end of a first portion of the fin, the second end of the first portion of the fin having a depth different than the depth of the first end of the first portion of the fin.

Подробнее
21-01-2016 дата публикации

Semiconductor memory device

Номер: US20160019965A1
Автор: Shoichi Watanabe
Принадлежит: Toshiba Corp

A semiconductor memory device includes a memory cell, a peripheral circuit configured to drive the memory cell, and a protection element. The peripheral circuit includes a first p-type MOS transistor including a gate electrode and a gate insulating film having a first film thickness, a second p-type MOS transistor including a gate electrode and a gate insulating film having a second film thickness, and an n-type MOS transistor. The gate electrode of the first p-type MOS transistor is connected to the protection element. The gate electrodes included in the second p-type MOS transistor and the n-type MOS transistor are connected only to an impurity region of another transistor or only to a gate electrode of the another transistor.

Подробнее
21-01-2016 дата публикации

METHODS OF FABRICATING SEMICONDUCTOR DEVICES WITH BLOCKING LAYER PATTERNS

Номер: US20160020145A1
Принадлежит:

A semiconductor device includes a circuit device on a substrate and a first insulating interlayer on the substrate and covering the circuit device. An electrode structure extends through the first insulating interlayer and at least partially through the substrate. An etch-stop layer pattern is disposed on a sidewall of the electrode structure on a side of the first insulating layer opposite the substrate. A blocking layer pattern is disposed on the etch-stop layer pattern. The device further includes an interconnection structure including a via portion passing through the blocking layer pattern to contact the through electrode structure and a wiring portion on the via portion and having a different width than the via portion. The semiconductor device may further include a contact plug electrically connected to the circuit device through the first insulating interlayer. The contact plug and the through electrode structure may include different metals.

Подробнее
21-01-2016 дата публикации

METHOD OF FABRICATING SEMICONDUCTOR DEVICE HAVING A RESISTOR STRUCTURE

Номер: US20160020148A1
Принадлежит:

Provided is a method of fabricating a semiconductor device. The method includes providing a substrate including a transistor area and a resistor area, forming dummy gate structures on the substrate in the resistor area, and a lower interlayer insulating layer; forming a resistor structure having a buffer insulating pattern, a resistor element and an etch-retard pattern disposed sequentially on the lower interlayer insulating layer; and forming resistor contact structures configured to pass through the etch-retard pattern and to contact with the resistor element. 1. A method of fabricating a semiconductor device , comprising:providing a substrate including a transistor area and a resistor area;forming active gate structures on the substrate in the transistor area;forming dummy gate structures on the substrate in the resistor area;forming a lower interlayer insulating layer on the substrate to cover side walls of the active gate structures and the dummy gate structures;forming a resistor structure comprising a buffer insulating pattern, a resistor element, and an etch-retard pattern stacked sequentially on the dummy gate structures and the lower interlayer insulating layer in the resistor area;forming an intermediate interlayer insulating layer on the lower interlayer insulating layer to cover the resistor structure;forming resistor contact structures configured to pass through the intermediate interlayer insulating layer and the etch-retard pattern, and to contact the resistor element; andforming an upper interlayer insulating layer on the intermediate interlayer insulating layer and the resistor contact structures.2. The method according to claim 1 , further comprising forming source/drain areas in the substrate between the active gate structures claim 1 ,wherein the source/drain areas are covered by the lower interlayer insulating layer.3. The method according to claim 2 , further comprising forming gate contact structures configured to pass through the ...

Подробнее
19-01-2017 дата публикации

SEMICONDUCTOR STRUCTURE WITH SELF-ALIGNED SPACERS AND METHOD OF FABRICATING THE SAME

Номер: US20170018460A1
Принадлежит:

A method of fabricating a semiconductor with self-aligned spacer includes providing a substrate. At least two gate structures are disposed on the substrate. The substrate between two gate structures is exposed. A silicon oxide layer is formed to cover the exposed substrate. A nitride-containing material layer covers each gate structure and silicon oxide layer. Later, the nitride-containing material layer is etched to form a first self-aligned spacer on a sidewall of each gate structure and part of the silicon oxide layer is exposed, wherein the sidewalls are opposed to each other. Then, the exposed silicon oxide layer is removed to form a second self-aligned spacer. The first self-aligned spacer and the second self-aligned spacer cooperatively define a recess on the substrate. Finally, a contact plug is formed in the recess. 1. A method of fabricating a semiconductor structure with self-aligned spacers comprising:providing a substrate with at least two gate structures disposed on the substrate, wherein the substrate between the gate structures is exposed;forming a silicon oxide layer covering the exposed substrate;forming a nitride-containing material layer covering the gate structures and the silicon oxide layer;etching the nitride-containing material layer to form a first self-aligned spacer at a sidewall of each gate structure, and exposing part of the silicon oxide layer, wherein the sidewalls of each gate structure are opposed to each other;removing the exposed silicon oxide layer to form a second self-aligned spacer, wherein the first self-aligned spacer and the second self-aligned spacer cooperatively define a recess on the substrate; andforming a contact plug in the recess.2. The method of fabricating a semiconductor structure with self-aligned spacers of claim 1 , wherein a method of forming the silicon oxide layer comprises oxidizing the exposed substrate to form the silicon oxide layer.3. The method of fabricating a semiconductor structure with self- ...

Подробнее
21-01-2016 дата публикации

OFFSET CONTACTS FOR REDUCED OFF CAPACITANCE IN TRANSISTOR SWITCHES

Номер: US20160020173A1
Автор: WAN Bin
Принадлежит:

Systems, apparatuses and methods for reduced OFF capacitance in switching devices are disclosed. A semiconductor die may include a semiconductor substrate, first and second elongated doped regions, said first region serving as a source of a first transistor, said second region serving as a drain of the first transistor and a source of a second transistor. The semiconductor die further includes a plurality of elongated gate structures including a first gate structure disposed between the first and second regions and serving as a gate of the first transistor. The semiconductor die further includes a first set of evenly-spaced electrical contact pads disposed on the first region, and a second set of evenly-spaced electrical contact pads disposed on the second region, the second set of contact pads being offset with respect to the first set of contact pads in a longitudinal direction of the first and second regions. 1. A semiconductor die comprising:a semiconductor substrate;first and second elongated doped regions, said first region serving as a source of a first transistor, said second region serving as a drain of the first transistor and a source of a second transistor;a plurality of elongated gate structures including a first gate structure disposed between the first and second regions and serving as a gate of the first transistor;a first set of evenly-spaced electrical contact pads disposed on the first region; anda second set of evenly-spaced electrical contact pads disposed on the second region, the second set of contact pads being offset with respect to the first set of contact pads in a longitudinal direction of the first and second regions.2. The semiconductor die of wherein the offset position of the second set of contact pads provides reduced OFF-state capacitance for a switch device of the semiconductor die compared to a non-offset position of the second set of contact pads.3. The semiconductor die of further comprising a buried oxide layer disposed ...

Подробнее
21-01-2016 дата публикации

Finfet source-drain merged by silicide-based material

Номер: US20160020208A1
Принадлежит: Globalfoundries Inc

A method includes conducting a laser-based anneal treatment on a metal layer positioned above and in direct contact with a first diamond shaped epitaxial layer surrounding a first fin and a second diamond shaped epitaxial layer surrounding a second fin, the metal layer extends from the first diamond shaped epitaxial layer to the second diamond shaped epitaxial layer, the laser-based anneal treatment forms a silicide layer, a portion of the silicide layer between the first and the second diamond shaped epitaxial layers is substantially thicker than a portion of the silicide layer in contact with the first and the second diamond shaped epitaxial layers, and the silicide layer takes on a crystal orientation of the first and the second epitaxial layers.

Подробнее
21-01-2016 дата публикации

FINFET SOURCE-DRAIN MERGED BY SILICIDE-BASED MATERIAL

Номер: US20160020209A1
Принадлежит:

A method includes conducting a laser-based anneal treatment on a metal layer positioned above and in direct contact with a top portion of a silicon cap layer located in direct contact with a first diamond shaped epitaxial layer surrounding a first fin and a second diamond shaped epitaxial layer surrounding a second fin. The metal layer extends from the top portion of the silicon cap layer in direct contact with the first diamond shaped epitaxial layer to the top portion of the silicon cap layer in direct contact with the second diamond shaped epitaxial layer. The conducted laser-based anneal treatment forms a silicide layer, a portion of the silicide layer between the first and the second diamond shaped epitaxial layers is substantially thicker than a portion of the silicide layer in contact with the first and the second diamond shaped epitaxial layers.

Подробнее
19-01-2017 дата публикации

TECHNIQUES FOR FORMING A COMPACTED ARRAY OF FUNCTIONAL CELLS

Номер: US20170018543A1
Принадлежит: Intel Corporation

Techniques are disclosed for forming a compacted array of functional cells using next-generation lithography (NGL) processes, such as electron-beam direct write (EBDW) and extreme ultraviolet lithography (EUVL), to form the boundaries of the cells in the array. The compacted array of cells may be used for field-programmable gate array (FPGA) structures configured with logic cells, static random-access memory (SRAM) structures configured with bit cells, or other memory or logic devices having cell-based structures. The techniques can be used to gain a reduction in area of 10 to 50 percent, for example, for the array of functional cells, because the NGL processes allow for higher precision and closer cuts for the cell boundaries, as compared to conventional 193 nm photolithography. In addition, the use of NGL processes to form the boundaries for the cells may also reduce lithography induced variations that would otherwise be present with conventional 193 nm photolithography. 1. An integrated circuit comprising:a substrate; andan array of functional cells formed on the substrate, each cell having a boundary;wherein the distance between the boundaries of two adjacent cells in the array is less than 50 nm.2. The integrated circuit of claim 1 , wherein the substrate comprises silicon (Si) and/or germanium (Ge).3. The integrated circuit of claim 1 , wherein the distance between the boundaries of two adjacent cells in the array is less than 20 nm.4. The integrated circuit of claim 1 , wherein the cells include gate array logic cells and/or memory bit cells.5. The integrated circuit of claim 1 , wherein the cells are formed on a grid of diffusion lines and gate lines.6. The integrated circuit of claim 1 , wherein there are no gate or diffusion lines between the boundaries of two adjacent cells.7. The integrated circuit of claim 1 , wherein the array of cells is between 10 and 50 percent more dense than the densest effective structure capable of being formed using 193 nm ...

Подробнее
03-02-2022 дата публикации

Spacers for Semiconductor Devices Including a Backside Power Rails

Номер: US20220037193A1

Semiconductor devices including air spacers formed in a backside interconnect structure and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure; and a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including a first dielectric layer on the backside of the first transistor structure; a first via extending through the first dielectric layer, the first via being electrically coupled to a first source/drain region of the first transistor structure; a first conductive line electrically coupled to the first via; and an air spacer adjacent the first conductive line, the first conductive line defining a first side boundary of the air spacer.

Подробнее
03-02-2022 дата публикации

PREPARATION METHOD FOR SEMICONDUCTOR DEVICE

Номер: US20220037211A1
Автор: LIAO Yuanbao
Принадлежит:

The present application relates to a preparation method for a semiconductor device, comprising: sequentially forming an isolating dielectric layer and a doped semiconductor layer of a first conductivity type on a non-primitive cell area of a semiconductor substrate; performing a first conductivity type of well injection by using the semiconductor layer and the isolating dielectric layer as masks, and forming a well area in a primitive cell area; forming an operation structure in the well area, and forming a protection structure in the semiconductor layer; and forming an interlayer dielectric layer on the operation structure and the protection structure, forming a contact hole in the interlayer dielectric layer, forming a metal interconnection layer connected to the contact hole on the interlayer dielectric layer, and connecting the operation structure and the protection structure by means of the metal interconnection layer and the contact hole. 1. A method for manufacturing a semiconductor device , the semiconductor device comprising a work structure and a protection structure configured to protect the work structure , the method comprising:providing a semiconductor substrate comprising a cell region and a non-cell region, forming an isolation dielectric layer on the non-cell region of the semiconductor substrate, and forming a semiconductor layer having a first-conductivity-type doping on the isolation dielectric layer;performing a first-conductivity-type well implantation to the semiconductor substrate by using the semiconductor layer and the isolation dielectric layer as masks, and forming a well region in the cell region of the semiconductor substrate;doping the well region to form the work structure in the cell region, and doping the semiconductor layer to form the protection structure on the non-cell region; andforming an interlayer dielectric layer on the work structure and the protection structure, forming a contact hole in the interlayer dielectric layer, ...

Подробнее
03-02-2022 дата публикации

Semiconductor device and method for fabricating the same

Номер: US20220037316A1
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor device includes an active region that extends in a first direction and has a first width in a second direction that intersects the first direction, a first gate structure disposed on the active region that has a second width in the first direction and extends in the second direction, a first metal contact spaced apart from the first gate structure in the first direction, a first trench formed in the active region, and an insulating material that fills the first trench and forms a first active cut, wherein the first active cut defines a first metal region in the active region in which the first metal contact is located, and the first metal contact is placed off-center inside the first metal region and a length of a region where the first gate structure and the active region overlap is greater than that of the first and second trenches.

Подробнее
03-02-2022 дата публикации

Multigate device with air gap spacer and backside rail contact and method of fabricating thereof

Номер: US20220037496A1

Methods and devices that include a multigate device having a channel layer disposed between a source feature and a drain feature, a metal gate that surrounds the channel layer, and a first air gap spacer interposing the metal gate and the source feature and a second air gap spacer interposing the metal gate and the drain feature. A backside contact extends to the source feature. A power line metallization layer is connected to the backside contact.

Подробнее
03-02-2022 дата публикации

Gate capping structures in semiconductor devices

Номер: US20220037510A1
Автор: Chung-Liang Cheng

A semiconductor device and methods of fabricating the same are disclosed. The semiconductor device includes a substrate, a fin structure disposed on the substrate, a source/drain (S/D) region disposed on the fin structure, and a gate structure disposed on the fin structure adjacent to the S/D region. The gate structure includes a gate stack disposed on the fin structure and a gate capping structure disposed on the gate stack. The gate capping structure includes a conductive gate cap disposed on the gate stack and an insulating gate cap disposed on the conductive gate cap. The semiconductor device further includes a first contact structure disposed over the gate stack. A portion of the first contact structure is disposed within the gate capping structure and is separated from the gate stack by a portion of the conductive gate cap.

Подробнее
19-01-2017 дата публикации

METHOD FOR MANUFACTURING A DIGITAL CIRCUIT AND DIGITAL CIRCUIT

Номер: US20170019104A1
Автор: KUENEMUND Thomas
Принадлежит:

A method for manufacturing a digital circuit is described including forming a plurality of field effect transistor pairs, connecting the field effect transistors of the field effect transistor pairs such that in response to a first transition from a first state of two nodes of the digital circuit and in response to a second transition from a second state of the nodes of the digital circuit the nodes each have an undefined logic state when, for each field effect transistor pair, the threshold voltages of the field effect transistors of the field effect transistor pair are equal and setting the threshold voltages of the field effect transistors of the field effect transistor pairs such that the nodes each have a predetermined defined logic state in response to the first transition and in response to the second transition. 1. A method for manufacturing a digital circuit comprising:forming a plurality of field effect transistor pairs;connecting the field effect transistors of the field effect transistor pairs such that in response to a first transition from a first state of two nodes of the digital circuit and in response to a second transition from a second state of the nodes of the digital circuit the nodes each have an undefined logic state when, for each field effect transistor pair, the threshold voltages of the field effect transistors of the field effect transistor pair are equal;setting the threshold voltages of the field effect transistors of the field effect transistor pairs such that the nodes each have a predetermined defined logic state in response to the first transition and in response to the second transition;forming one or more pairs of competing paths such that, for each field effect transistor pair, the two field effect transistors are in different competing paths of a pair of competing paths; andconnecting the one or more pairs of competing paths and the nodes such that for each pair of competing paths, the competing paths are connected to different ...

Подробнее
18-01-2018 дата публикации

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

Номер: US20180019205A1
Принадлежит:

A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a first dielectric layer is formed on the substrate, in which a first conductor is embedded within the first dielectric layer. Next, a second dielectric layer is formed on the first dielectric layer, part of the second dielectric layer is removed to form a contact hole, and a lateral etching process is conducted to expand the contact hole to form a funnel-shaped opening. Next, a metal layer is formed in the funnel-shaped opening, and the metal layer is planarized to form a second conductor. 1. A method for fabricating semiconductor device , comprising:providing a substrate;forming a first dielectric layer on the substrate;forming a via hole in the first dielectric layer; andperforming a lateral etching process to expand the via hole for forming a funnel-shaped opening.2. The method of claim 1 , further comprising:forming a second dielectric layer on the substrate;forming a first conductor in the second dielectric layer;forming the first dielectric layer on the second dielectric layer; andforming the via hole in the first dielectric layer to expose the first conductor.3. The method of claim 2 , wherein a top surface of the first conductor and a top surface of the second dielectric layer are coplanar.4. The method of claim 2 , further comprising:forming a first mask layer on the first dielectric layer;performing a first etching process to pattern the first mask layer for forming a patterned first mask layer;forming a second mask layer on the patterned first mask layer; andperforming a second etching process to form the via hole in the second mask layer and the first dielectric layer.5. The method of claim 4 , further comprising using a chlorine-containing gas to perform the first etching process.6. The method of claim 4 , further comprising using a fluorine-containing gas to perform the second etching process.7. The method of claim 1 , wherein an etching gas used to perform ...

Подробнее
17-01-2019 дата публикации

ELECTRICAL FUSE AND/OR RESISTOR STRUCTURES

Номер: US20190019752A1
Принадлежит:

Electrical fuse (eFuse) and resistor structures and methods of manufacture are provided. The method includes forming metal gates having a capping material on a top surface thereof. The method further includes protecting the metal gates and the capping material during an etching process which forms a recess in a dielectric material. The method further includes forming an insulator material and metal material within the recess. The method further includes forming a contact in direct electrical contact with the metal material. 1. A semiconductor structure , comprising:metal gates having a capping material on a top surface thereof;contact structures in recesses in a dielectric material between the metal gates;an opening in the dielectric material, wherein the opening is between the contact structures; andan insulator material and metal material within the opening.2. The semiconductor structure of wherein the metal material contacts surfaces of the dielectric material in the opening.3. The semiconductor structure of claim 2 , wherein the insulator material is in a trench in the metal material.4. The semiconductor structure of claim 1 , wherein the contact structures each comprise a liner formed in one of the recesses in the dielectric material.5. The semiconductor structure of claim 4 , wherein the metal material contacts the liner of each of the contact structures.6. The semiconductor structure of claim 1 , wherein top surfaces of the dielectric layer claim 1 , the capping material claim 1 , the contact structures claim 1 , the insulator material claim 1 , and the metal material are co-planar.7. The semiconductor structure of claim 1 , further comprising:another dielectric layer over the dielectric layer, the capping material, the contact structures, the insulator material, and the metal material; andadditional contacts in the other dielectric layer.8. The semiconductor structure of claim 7 , wherein the additional contacts contact the contact structures claim 7 , ...

Подробнее
17-01-2019 дата публикации

Field effect transistor (fet) structure with integrated gate connected diodes

Номер: US20190019790A1
Принадлежит: Raytheon Co

A structure having: a plurality of field effect transistors (FETs) connected between a common input and a common output, each one of the field effect transistors comprises: a source region, a drain region, and a gate electrode for controlling carriers through a channel region of a transistor region of the structure between the source region and the drain region; a plurality of diodes, each one of the diodes being associated with a corresponding one of the plurality of FETs, each one of the diodes having an electrode in Schottky contact with a diode region of the corresponding one of the FETs. The gate electrode and the diode electrode extend along parallel lines. The source region, the drain region, the channel region, and a diode region having therein the diode are disposed along a common line.

Подробнее
16-01-2020 дата публикации

Contact Conductive Feature Formation and Structure

Номер: US20200020578A1

Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back by a wet etching process. After etching back the portion of the barrier layer, an underlying dielectric welding layer is exposed. A conductive material is formed along the barrier layer.

Подробнее
16-01-2020 дата публикации

DUMMY MOL REMOVAL FOR PERFORMANCE ENHANCEMENT

Номер: US20200020588A1
Принадлежит:

The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a plurality of gate structures over a substrate, and forming a plurality of source and drain regions along opposing sides of the plurality of gate structures. A plurality of middle-of-the-line (MOL) structures are formed at locations laterally interleaved between the plurality of gate structures. The plurality of MOL structures are redefined by getting rid of a part but not all of one or more of the plurality of MOL structures. Redefining the plurality of MOL structures results in a plurality of MOL active structures arranged over the plurality of source and drain regions at an irregular pitch. 1. A method of forming an integrated chip , comprising:forming a plurality of gate structures over a substrate;forming a plurality of source and drain regions along opposing sides of the plurality of gate structures;defining a plurality of middle-of-the-line (MOL) structures at locations laterally interleaved between the plurality of gate structures; andredefining the plurality of MOL structures by getting rid of a part but not all of one or more of the plurality of MOL structures, wherein redefining the plurality of MOL structures results in a plurality of MOL active structures arranged over the plurality of source and drain regions at an irregular pitch.2. The method of claim 1 ,wherein the plurality of MOL structures are defined according to a first photomask; andwherein the plurality of MOL structures are redefined according to a cut mask.3. The method of claim 1 , wherein redefining the plurality of MOL structures forms two separate MOL active structures from a single one of the plurality of MOL structures.4. The method of claim 1 , wherein the plurality of MOL structures are defined to be at a substantially regular pitch that is smaller than the irregular pitch.5. The method of claim 1 , further comprising:forming an inter-level ...

Подробнее