Substrat-Bondingstruktur und Substrat-Bondingverfahren

Eine Vorrichtung (2) ist auf einer Hauptoberfläche eines Substrats (1) ausgebildet. Die Hauptoberfläche des Substrats (1) ist über das Bonding-Bauteil (11, 12, 13) in einem hohlen Zustand an die Unterseite des Gegensubstrats (14) gebondet. Eine Schaltung (17) und eine Höckerstruktur (26) sind auf der Oberseite des Gegensubstrats (14) ausgebildet. Die Höckerstruktur (26) ist in einem Bereich positioniert, der zumindest dem Bonding-Bauteil (11, 12, 13) entspricht, und weist eine größere Höhe als diejenige der Schaltungsstruktur (17) auf.

Halbleitervorrichtung mit einer Kupfersäule-Zwischenverbindungsstruktur

Ein Verfahren zur Herstellung einer Halbleitervorrichtung wird beschrieben. Das Verfahren umfasst das Abscheiden einer Photoresist-Schicht über einem Halbleitersubstrat. Die Photoresist-Schicht wird strukturiert, um eine Öffnung in der Photoresist-Schicht zu bilden. Eine Kupfersäule wird in der Öffnung gebildet. Eine Diffusionsbarriereschicht wird über der Kupfersäule und über einem Photoresist-Abschnitt der Photoresist-Schicht, der direkt an die Öffnung angrenzt, gebildet. Eine Lotstruktur wird über der Diffusionsbarriereschicht abgeschieden.

Method for manufacturing semiconductor device

An amorphous Ni-P layer (10) which cancels crystallinity of a base metal layer is formed on the base metal layer, such as an FET electrode, by electroless gilding and then an electrolytic Au gilding layer (9) is formed on the amorphous Ni-P layer. Thus, luster nonuniformity of the electrolytic Au gilding layer formed on the base metal layer, such as the FET electrode, is avoided so that a position of an electrode pad can be mechanically detected in an easy manner, during auto- bonding, and its appearance is improved. Processing of MMICs is thus improved. ...

ELECTRO-CHEMICAL SEPARATING OF SOLDERING BALLS WITH UNIFORM HEIGHT ON SEMICONDUCTOR SUBSTRATES

SOLDERING PEAK MANUFACTURING PROCESS AND STRUCTURES WITH A TITANIUM BARRIER LAYER

Verfahren zum Herstellen weichlötfähiger Metallkontakte

Method for galvanising and forming a contact boss

Semiconductor device having align mark layer and method of fabricating the same

Semiconductor device

Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion (2) formed on the upper surface of a semiconductor substrate (1), a passivation layer (3) so formed on the upper surface of the semiconductor substrate (1) as to overlap a part of the electrode pad portion (2) and having a first opening portion (3a) where the upper surface of the electrode pad portion (2) is exposed, a barrier metal layer (5) formed on the electrode pad portion (2), and a solder bump (6) formed on the barrier metal layer (5). The barrier metallayer (5) is formed such that an outer peripheral end (5b) lies within the first opening portion (3a) of the passivation layer (3) when viewed in plan.

Semiconductor sealing baseplate structure of electric padding metal protective layer and producing method thereof

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME

반도체 패키지 및 반도체 패키지 모듈

... 범프를 통하여 회로 기판과 연결되는 반도체 패키지가 제공된다. 본 발명의 일 실시예에 따른 반도체 패키지는, 복수개의 접속 패드가 노출되도록 형성된 반도체 칩; 상기 각 접속 패드 상에 형성되며, 제1 필라부 및 상기 제1 필라부 상측에 형성되는 제1 솔더부를 포함하는 연결용 범프들; 상기 접속 패드 주변에서 상기 접속 패드의 상부 표면 보다 높은 위치에 형성되며, 솔더 유도부가 형성되어 있는 제2 필라부 및 상기 제2 필라부 상측에 형성되는 제2 솔더부를 포함하는 지지용 범프들;을 포함한다.

SEMICONDUCTOR DEVICE WITH A SOLDER BUMP AND METHODS FOR MANUFACTURING THE SEMICONDUCTOR DEVICE AND A WIRING SUBSTRATE

PURPOSE: A semiconductor device and methods for manufacturing the same and a wiring substrate are provided to precisely form a solder layer on a desirable area of a wiring pad by forming the solder layer using a patterned photoresist layer. CONSTITUTION: An electrode pad(9) is formed on a semiconductor substrate(5). A passivation film(6) covers the semiconductor substrate and the periphery of the electrode pad. A contact layer(7) and a seed metal layer(8) are formed on the electrode pad in order. A barrier metal layer(2) and a solder layer(3) are formed on the seed metal layer in order. A stopper film(4) is formed on the upper part of the barrier metal layer. COPYRIGHT KIPO 2013 ...

Semiconductor product with interlocking metal-to-metal bonds and method for manufacturing thereof

Semiconductor device and process for manufacturing the same

A semiconductor device has a pad structure with a ring-shaped stress buffer layer between a metal pad and an under-bump metallization (UBM) layer. The stress buffer layer is formed of a dielectric layer with a dielectric constant less than 3.5, a polymer layer, or an aluminum layer. The stress buffer layer is a circular ring, a square ring, an octagonal ring, or any other geometric ring.

Semiconductor device and method of manufacturing semiconductor device

A semiconductor device includes a semiconductor element; a pad electrode that is formed on the semiconductor element; an alignment mark that is formed on the semiconductor element; a connection electrode that is formed on the pad electrode; and an underfill resin that is formed to cover the connection electrode. The height of the alignment mark from the semiconductor element is greater than that of the connection electrode.

Semiconductor element and a producing method for the same, and a semiconductor device and a producing method for the same

A columnar bump formed of copper etc. is formed on a wiring film of a semiconductor chip through an interconnected film and an adhesive film in a wafer unit by electrolytic plating in which package formation is possible. An oxidation prevention film is formed of such as gold on an upper surface or a part of the upper surface and side surface. A wet prevention film of such as an oxide film is formed on the columnar bump side as needed. If this bump is soldered to the pad on a packaging substrate, solder gets wet in the whole region of the columnar bump upper surface and only a part of the side surface. Stabilized and reliable junction form can be thus formed. Moreover, since the columnar bump does not fuse, the distance between a semiconductor board and a packaging board is not be narrowed by solder.

Semiconductor device and method of fabricating the same

A semiconductor device includes a semiconductor substrate and an array of protruding electrodes arranged at a pitch X1. Each of the protruding electrodes has a height X3 and is formed on a barrier metal base of diameter X2 coupled to an electrode arranged on the semiconductor substrate so as to satisfy the relations (X1/2) <= X2 <= (3*X1/4) and (X1/2) <= X3 <= (3*X1/4).

Semiconductor device, method of manufacturing the same, and method of manufacturing wiring board

Electronic device, method for manufacturing the electronic device, and electronic apparatus

An electronic device includes: a first circuit board; a second circuit board located above a first region of the first circuit board; a first semiconductor element located above a second region of the first circuit board, which is different from the first region, and above a third region of the second circuit board; a first connection interposed between the first semiconductor element and the second region so as to electrically interconnect the first semiconductor element and the first circuit board; and a second connection interposed between the first semiconductor element and the third region so as to electrically interconnect the first semiconductor element and the second circuit board.

Method of making a pillar structure having a non-metal sidewall protection structure and integrated circuit including the same

An integrated circuit device includes a semiconductor substrate; and a pad region over the semiconductor substrate. The integrated circuit device further includes an under-bump-metallurgy (UBM) layer over the pad region. The integrated circuit device further includes a conductive pillar on the UBM layer, wherein the conductive pillar has a sidewall surface and a top surface. The integrated circuit device further includes a protection structure over the sidewall surface of the conductive pillar, wherein sidewalls of the UBM layer are substantially free of the protection structure, and the protection structure is a non-metal material.

Method for fabricating low resistance, low inductance interconnections in high current semiconductor devices

A method for fabricating a low resistance, low inductance device for high current semiconductor flip-chip products. A structure is produced, which comprises a semiconductor chip with metallization traces, copper lines in contact with the traces, and copper bumps located in an orderly and repetitive arrangement on each line so that the bumps of one line are positioned about midway between the corresponding bumps of the neighboring lines. A substrate is provided which has elongated copper leads with first and second surfaces, the leads oriented at right angles to the lines. The first surface of each lead is connected to the corresponding bumps of alternating lines using solder elements. Finally, the assembly is encapsulated in molding compound so that the second lead surfaces remain un-encapsulated.

Low fabrication cost, fine pitch and high reliability solder bump

A barrier layer is deposited over a layer of passivation including in an opening to a contact pad created in the layer of passivation. A column of three layers of metal is formed overlying the barrier layer and aligned with the contact pad and having a diameter that is about equal to the surface of the contact pad. The three metal layers of the column comprise, in succession when proceeding from the layer that is in contact with the barrier layer, a layer of pillar metal, a layer of under bump metal and a layer of solder metal. The layer of pillar metal is reduced in diameter, the barrier layer is selectively removed from the surface of the layer of passivation after which reflowing of the solder metal completes the solder bump of the invention.

Electronic component, semiconductor device, methods of manufacturing the same, circuit board, and electronic instrument

The present invention is a semiconductor device capable of relieving thermal stress without breaking wire. It comprises a semiconductor chip (12), a solder ball (20) for external connection, wiring (18) for electrically connecting the semiconductor chip (12) and the solder ball (20), a stress relieving layer (16) provided on the semiconductor chip (12), and a stress transmission portion (22) for transmitting stress from the solder ball (20) to the stress relieving layer (16) in a peripheral position of an electrical connection portion (24a) of the solder ball (20) and wiring (18).

SEMICONDUCTOR DEVICE

A semiconductor device has a semiconductor substrate, and multiple first bipolar transistors on the first primary surface side of the semiconductor substrate. The first bipolar transistors have a first height between an emitter layer and an emitter electrode in the direction perpendicular to the first primary surface. The semiconductor device further has at least one second bipolar transistor on the first primary surface side of the semiconductor substrate. The second bipolar transistor have a second height, greater than the first height, between an emitter layer and an emitter electrode in the direction perpendicular to the first primary surface. Also, the semiconductor has a first bump stretching over the multiple first bipolar transistors and the at least one second bipolar transistor.

Substrate Stand-Offs for Semiconductor Devices

Substrate stand-offs for use with semiconductor devices are provided. Active pillars and dummy pillars are formed on a first substrate such that the dummy pillars may have a height greater than a height of the active pillars. The dummy pillars act as stand-offs when joining the first substrate to a second substrate, thereby creating greater uniformity. In an embodiment, the dummy pillars may be formed simultaneously as the active pillars by forming a patterned mask having openings with a smaller width for the dummy pillars than for the active pillars. When an electro-plating process of the like is used to form the dummy and active pillars, the smaller width of the dummy pillar openings in the patterned mask causes the dummy pillars to have a greater height than the active pillars.

Fabrication method of semiconductor structure

The present invention provides a semiconductor structure and a method of fabricating the same. The method includes: providing a chip having conductive pads, forming a metal layer on the conductive pads, forming a passivation layer on a portion of the metal layer, and forming conductive pillars on the metal layer. Since the metal layer is protected by the passivation layer, the undercut problem is solved, the supporting strength of the conductive pillars is increased, and the product reliability is improved.

ELECTRONIC DEVICE

An electronic device is disclosed. In one embodiment, the electronic device includes a substrate, a plurality of conducting lines formed on a first conducting material that is disposed on the substrate, and a layer of a second conducting material disposed on the plurality of conducting lines. The conducting lines include a top face and a side face. The layer of the second conducting material includes a first thickness disposed on each of the top faces and a second thickness disposed on each of the side faces. To this end, the first thickness is greater than the second thickness.

PRE-MOLDED CLIP STRUCTURE

A method for making a premolded clip structure is disclosed. The method includes obtaining a first clip and a second clip, and forming a molding material around the first clip comprising a first surface and the second clip comprising a second surface. The first surface of the first clip structure and the second surface of the second clip structure are exposed through the molding material, and a premolded clip structure is then formed.

Semiconductor device and manufacturing method thereof

An electronic device and a method of making an electronic device. As non-limiting examples, various aspects of this disclosure provide various methods of making electronic devices, and electronic devices made thereby, that utilize a film assist mold process.

INDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

A manufacturing method of an inductor structure includes the following steps. A protection layer is formed on a substrate, such that bond pads of the substrate are respectively exposed form protection layer openings of the protection layer. A conductive layer is formed on the bond pads and the protection layer. A patterned first photoresist layer is formed on the conductive layer. Copper bumps are respectively formed on the conductive layer located in the first photoresist layer openings. A patterned second photoresist layer is formed on the first photoresist layer, such that at least one of the copper bumps is exposed through second photoresist layer opening and the corresponding first photoresist layer opening. A diffusion barrier layer and an oxidation barrier layer are formed on the copper bump. The first and second photoresist layers, and the conductive layer not covered by the copper bumps are removed.

Method of forming a dummy die of an integrated circuit having an embedded annular structure

An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.

Conical-shaped or tier-shaped pillar connections

A pillar structure, and a method of forming, for a substrate is provided. The pillar structure may have one or more tiers, where each tier may have a conical shape or a spherical shape. In an embodiment, the pillar structure is used in a bump-on-trace (BOT) configuration. The pillar structures may have circular shape or an elongated shape in a plan view. The substrate may be coupled to another substrate. In an embodiment, the another substrate may have raised conductive traces onto which the pillar structure may be coupled.

Methods of electroplating solder bumps of uniform height on integrated circuit substrates

Methods of electroplating solder bumps of uniform height on integrated circuit substrates include the steps of drawing plating current through an integrated circuit wafer by electrically shorting an integrated circuit's ground, power and signal pads together using an ultra-thin plating base layer (e.g., < 0.075um thick) and then using a backside wafer contact to draw electroplating current along parallel paths which extend through the ground and signal pads and into the substrate. The ground pads are preferably electrically coupled to the substrate at substrate contact regions (e.g., N + or P + diffusion regions) and the signal pads are preferably electrically coupled to the substrate through active semiconductor devices (e.g., FETs, BJTs, ...) to which the signal pads are attached. Plating current is preferably drawn in parallel through an integrated circuit's active semiconductor devices and substrate contact regions. The combined contributions of the plating currents drawn through the ...

PLATING BUMP FORMATION METHOD AND WAFER PLATING JIGS ADOPTED

PURPOSE: To provide a plating bump formation method capable of reducing dramatically the variability of the height of a bump electrode by providing an electric current into a semiconductor wafer equally and a wafer plating jig adopted for the above formation method. CONSTITUTION: By means of a jig, a jig electrode layer 11 is fixed on the entire rear side of a semiconductor wafer 5 which faces a barrier metal layer 9 which is a conductor layer in a scribe line 5a in such a fashion that the electrode layer 11 may adhere to the rear side of the semiconductor wafer. The scribe line 5a is equally distributed on the whole surface of the semiconductor wafer 5. Therefore, the electrode layer 11 connected to a power source 14 is capable of providing an electric current into the barrier metal layer 9 by way of the semiconductor wafer, which makes it possible to reduce the variability of the height of the bump electrode at an opening portion 9a. COPYRIGHT: (C)1993,JPO&Japio ...

MANUFACTURE OF BUMP ELECTRODE FOR INTEGRATED CIRCUIT DEVICE

PURPOSE: To form a bump electrode on a flip chip of an integrate circuit device with its protective film protected by a resin film in a simple process with a high yield. CONSTITUTION: A protective film 4 is deposited on a wiring film 3 where a bump electrode 7 is to be formed, and then a resin film 5 is applied thereto. A window determining a bump electrode pattern is formed in a photoresist film 30, and further an upper window 5a is formed in the resin film 5 using a dedicated developer. A lower window 4a is formed in the protective film 4 by etching using the resin film 5 as mask. Metal for the bump electrode 7 is grown on a base film 6 connected to the wiring layer 3 exposed in the lower window 4a by electroplating. COPYRIGHT: (C)1993,JPO&Japio ...

Löt-Anschlusskontakt und Verfahren zu seiner Herstellung

PRODUCTION OF SOFT-SOLDERABLE CONTACTS FOR THE INSTALLATION OF SEMICONDUCTOR COMPONENTS INTO HOUSINGS

微细间距倒装焊凸点电镀制备技术

A process for soldering by electrolysis is used for package of semiconductor device with good reliable solder balls in miniature space. The process is usable for various solders such as lead-tin ones or leadless tin based ones, for instance: copper-tin, tin-copper-silver, tin-silver, tin-bismuth, etc. It can meet the demands where the space between solder balls with diameters of 50 - 300um is >50um. In the invention, projecting dots returning flow control layer is taken to avoid waste of solder and to achieve reliable solder balls with mini-gaps. The micro-structure of the electroplating layer can be regulated by control of vital arts and the said electroplating layer. The process can be used in preparation of solder balls for downward assembled package. Also, some special design of photo-engraving adhesive coating unit and process thereof are used.

Power management applications of interconnect substrates

Various applications of interconnect substrates in power management systems are described.

Semiconductor device

Semiconductor device and manufacturing method thereof

Semiconductor device

Semiconductor bare chip and form the conductive element of the method

Manufactoring process of bumps for chips

Un procédé de fabrication d'une bosse (7) en métal pour puce comprend les étapes consistant à: former une couche de métal d'arrêt (5) sur un substrat sur lequel est formée une pastille; former une couche de photorésist (6) sur la couche de métal d'arrêt (5) et ouvrir une zone de la pastille; former une bosse (7) pour puce par électrodéposition sur la zone ouverte; sélectivement éliminer la couche de photorésist (6) en utilisant la bosse (7) en tant que masque; attaquer une zone prédéterminée de la couche de métal d'arrêt (5) en utilisant comme masque la couche de photorésist restante (10); et former une bosse (7) pour puce sur la pastille en éliminant la couche de photorésist restante (10).

METHOD OF FORMING CONDUCTIVE INTERCONNECTS ON A SUBSTRATE AND INTERCONNECTIONS THUS OBTAINED

Procédé de réalisation d'une structure de connexion, comprenant des étapes consistant à : a) former au moins un pilier conducteur sur une couche conductrice d'accroche disposée sur un support, la couche conductrice d'accroche étant à base d'au moins un premier matériau conducteur, b) déposer un deuxième matériau conducteur sur le pilier conducteur, le deuxième matériau conducteur étant fusible, c) effectuer au moins un traitement thermique de sorte à faire fondre le deuxième matériau conducteur pour qu'une portion du deuxième matériau conducteur coule contre le pilier conducteur et réagisse avec la couche conductrice en formant une zone (45) à base d'un alliage située autour et contre une base du pilier conducteur, d) graver sélectivement la couche conductrice d'accroche autour du pilier conducteur par rapport à ladite zone (45) d'alliage, la zone (45) d'alliage formant une protection à la gravure de la couche conductrice d'accroche située en regard du pilier conducteur (figure 1F).

지문센서 패키지

... 본 발명은 지문센서 패키지에 관한 것으로, 해결하고자 하는 기술적 과제는 도전성 범프와 지문센싱부가 반도체 다이의 일면에 구비되고, 타면에 구비된 보호판이나 보호막에 지문이 인접할 경우, 정전용량 변화를 통해 지문을 센싱할 수 있고, 지문센싱부가 구비된 반도체 다이가 기판에 플립칩 타입으로 안착되므로, 공정을 간소화하는데 있다.

Self-assembled interconnection particles

SEMICONDUCTOR INTEGRATED CIRCUIT AND FABRICATION PROCESS THEREFOR

SEMICONDUCTOR POWER DEVICE METAL STRUCTURE AND METHOD OF FORMATION

In accordance with one embodiment, a stress buffer (40) is formed between a power metal structure (90) and passivation layer (30). The stress buffer (40) reduces the effects of stress imparted upon the passivation layer (30) by the power metal structure (90). In accordance with an alternative embodiment, a power metal structure (130A) is partitioned into segments (1091), whereby electrical continuity is maintained between the segments (1091) by remaining portions of a seed layer (1052) and adhesion/barrier layer (1050). The individual segments (1091) impart a lower peak stress than a comparably sized continuous power metal structure (90).

METHODS AND STRUCTURES FOR A VERTICAL PILLAR INTERCONNECT

In wafer-level chip-scale packaging and flip-chip packaging and assemblies, a solder cap is formed on a vertical pillar. In one embodiment, the vertical pillar overlies a semiconductor substrate. A solder paste, which may be doped with at least one trace element, is applied on a top surface of the pillar structure. A reflow process is performed after applying the solder paste to provide the solder cap.

Semiconductor devices having through electrodes, methods of manufacturing the same, and semiconductor packages including the same

A semiconductor device includes a semiconductor layer having a first surface and a second surface, a through electrode penetrating the semiconductor layer and having a protruding portion that protrudes over the second surface of the semiconductor layer, a front-side bump disposed on the first surface of the semiconductor layer and electrically coupled to the through electrode, a passivation pattern including a first insulation pattern that surrounds a sidewall of the protruding portion of the through electrode and extends onto the second surface of the semiconductor layer and a second insulation pattern that covers the first insulation pattern and has an etch selectivity with respect to the first insulation pattern, and a back-side bump covering an end surface of the protruding portion of the through electrode and extending onto the passivation pattern.

Solder bumps in flip-chip technologies

A solder bump structure and method for forming the same. The structure includes (a) a dielectric layer including a dielectric layer top surface (b) an electrically conducting bond pad on and in direct physical contact with the dielectric layer top surface; (c) a patterned support/interface layer on the dielectric layer top surface and thicker than the electrically conducting bond pad in the reference direction, wherein the patterned support/interface layer comprises a hole and a trench, wherein the hole is directly above the electrically conducting bond pad, and wherein the trench is not filled by any electrically conducting material; and (d) an electrically conducting solder bump filling the hole and electrically coupled to the electrically conducting bond pad.

FLIP CHIP SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF

There is provide a flip chip semiconductor package comprising: an electrode pad formed a semiconductor substrate; a lower metal bonding layer formed on the electrode pad; an upper metal bonding layer formed on the lower metal bonding layer and having a post shape of a predetermined height; and a conductive bump formed on the upper metal bonding layer, and a solder bump covers at least partially the surface of the upper metal bonding layer. An insulating layer for electrode reconfiguration is formed around the electrode pad on the substrate, and the insulating layer has a predetermined thickness to prevent the penetration of a particles from the solder bump. The semiconductor package may further comprise an oxidation preventing layer between the solder bump and the upper metal bonding layer. In accordance with the present invention, there is realized the flip chip semiconductor package which improves the adhesive strength of the solder bump and which more improves the reliability in the ...

[METHOD FOR TREATING WAFER SURFACE]

The present invention provides a method for treating the wafer surface, suitable for removing residues on the wafer surface. The method includes forming a photo-sensitive material layer over the wafer surface covering the bumps and the under bump metallurgy layer on the wafer surface. Using the bumps as masks, the photo-sensitive material layer is exposed and developed, to expose the wafer surface between the bumps. A wet etching process is then performed to remove residues on the exposed wafer surface and then the remained photo-sensitive material layer is removed. Therefore, no residues remain on the wafer surface, and the yield of the bumps is increased.

METHOD FOR SELECTIVE ELECTROPLATING OF SEMICONDUCTOR DEVICE I/O PADS USING A TITANIUM-TUNGSTEN SEED LAYER

A method for selective electroplating of a semiconductor input/output (I/O) pad includes forming a titanium-tungsten (TiW) layer over a passivation layer on a semiconductor substrate, the TiW layer further extending into an opening formed in the passivation layer for exposing the I/O pad, such that the TiW layer covers sidewalls of the opening and a top surface of the I/O pad. A seed layer is formed over the TiW layer, and portions of the seed layer are selectively removed such that remaining seed layer material corresponds to a desired location of interconnect metallurgy for the I/O pad. At least one metal layer is electroplated over the remaining seed layer material, using the TiW layer as a conductive electroplating medium.

Mounting spring elements on semiconductor devices, and wafer-level testing methodology

Resilient contact structures are mounted directly to bond pads on semiconductor dies, prior to the dies being singulated (separated) from a semiconductor wafer. This enables the semiconductor dies to be exercised (e.g., tested and/or burned-in) by connecting to the semiconductor dies with a circuit board or the like having a plurality of terminals disposed on a surface thereof. Subsequently, the semiconductor dies may be singulated from the semiconductor wafer, whereupon the same resilient contact structures can be used to effect interconnections between the semiconductor dies and other electronic components (such as wiring substrates, semiconductor packages, etc.). Using the all-metallic composite interconnection elements of the present invention as the resilient contact structures, burn-in can be performed at temperatures of at least 150° C., and can be completed in less than 60 minutes.

Coaxial-Interconnect Structure for a Semiconductor Component

The present disclosure describes a coaxial-interconnect structure that is integrated into a semiconductor component and methods of forming the coaxial-interconnect structure. The coaxial interconnect-structure, which electrically couples circuitry of an integrated-circuit (IC) die to traces of a packaging substrate, comprises a signal core elongated about an axis, a ground shield elongated about the axis, and an insulator disposed between the signal core and the ground shield.

Method of manufacturing semiconductor packaging

The present disclosure is related to a method of providing a die structure for semiconductor packaging. The method includes providing a substrate with a bonding pad; forming a patterned mask layer on the substrate; forming an opening on the mask layer; depositing a conductive layer in the opening; forming a cap layer on the conductive layer, and removing the mask layer. The cap layer forming step allows the contacting area between the cap layer and the conductive layer to be substantially equal to the top surface area of the conductive layer by reflowing solder material prior to the removal of the mask layer.

Semiconductor device and a method of manufacturing the same

A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP.

CONTACT STRUCTURES WITH POROUS NETWORKS FOR SOLDER CONNECTIONS, AND METHODS OF FABRICATING SAME

A contact pad includes a solder-wettable porous network () which wicks the molten solder () and thus restricts the lateral spread of the solder, thus preventing solder bridging between adjacent contact pads. 1. An assembly comprising:a first contact pad of a first microelectronic component, the first contact pad comprising a porous network; anda second contact pad of a second microelectronic device, the second contact pad bonded to the first contact pad via a solder at least partly disposed in pores of the porous network.2. The assembly of claim 1 , wherein the porous network comprises gold or a gold alloy.3. The assembly of claim 1 , wherein the first contact pad comprises an open-pore sponge with 70-80% porosity.4. The assembly of claim 1 , wherein the porous network comprises pore sizes from 15 nm to 360 nm.5. The assembly of claim 1 , further comprising a film deposited on pores of the porous network claim 1 , the film comprising titanium claim 1 , nickel claim 1 , or copper in a thickness of 2-5 nm.6. The assembly of claim 1 , wherein both the first contact pad and the second contact pad comprise porous networks.7. The assembly of claim 6 , wherein the solder penetrates at least 15 nm into each of the first contact pad and the second contact pad.8. The assembly of claim 1 , wherein the solder has been diffusion bonded to the porous network via thermocompression bonding.9. The assembly of claim 8 , wherein the solder that has been diffusion bonded to the porous network of the first contact pad contains indium and has a melting temperature below 180° C.10. A contact pad resistant to solder-bridges between adjacent contact pads claim 8 , for making a microelectronic component with contact pads at fine pitch claim 8 , comprising:a gold alloy at a bonding interface of the microelectronic component; anda wicking layer of the gold alloy comprising a porous network, the wicking layer comprising pores with diameters between 15-360 nm to absorb a solder at least 15 nm ...

Conductive external connector structure and method of forming

External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure.

SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To provide a semiconductor device of which operational reliability is improved. SOLUTION: A bump electrode 8s for a source electrode is provided as an oscillation shield between a bump electrode 8g for the gate electrode of a semiconductor chip 1 constituting an RF power module and a bump electrode 8d for a drain electrode. The bump electrode 8s for the source electrode is formed like a longer band pattern than the other bump electrodes 8g and 8d. The bump electrodes 8g, 8d and 8s have a vertical structure wherein a metal layer is formed on a bonding pad with a base metal in-between and a solder layer is formed thereon. COPYRIGHT: (C)2007,JPO&INPIT ...

Elektronikbauelement

Es wird ein Elektronikbauelement offenbart. Das Elektronikbauelement enthält bei einer Ausführungsform ein Substrat, mehrere auf einem ersten leitenden Material, das auf dem Substrat angeordnet ist, ausgebildete Leitungen und eine auf den mehreren Leitungen angeordnete Schicht aus einem zweiten leitenden Material. Die Leitungen enthalten eine obere Fläche und eine Seitenfläche. Die Schicht aus dem zweiten leitenden Material beinhaltet eine auf jeder der oberen Flächen angeordnete erste Dicke und eine auf jeder der Seitenflächen angeordnete zweite Dicke. Dazu ist die erste Dicke größer als die zweite Dicke.

Procedure for manufacturing soft-solderable metallic contacts for the electrical connection of semiconductor components in housings

SOLDERING CONNECTION CONTACT AND PROCEDURE FOR ITS PRODUCTION

SOLDERING PEAK MANUFACTURING PROCESS AND STRUCTURES WITH A TITANIUM BARRIER LAYER

Semiconductor device and manufacturing method

CTOR COMPONENTS INTO HOUSINGS METHOD OF PRODUCING SOFT SOLDERABLE CONTACTS FOR INSTALLING SEMICONDU

MANUFACTORING PROCESS OF STUDS OF ELECTRIC CONNECTION Of a PLATE

Procédé de fabrication de plots de connexion électrique sur une face d'une plaque, comprenant : la réalisation de zones conductrices de l'électricité (6a, 6b) et de branches de connexion électrique (7) reliant ces zones; le dépôt d'une couche (8) en une matière de masque; la réalisation, dans cette couche de masque, d'ouvertures (9a, 9b) qui s'étendent au-dessus desdites zones conductrices et dont au moins certaines (9a) s'étendent au moins en partie au-delà des bords périphériques des zones conductrices sous-jacentes (6a) ; la réalisation de blocs (12a, 12b) en une matière de soudure dans lesdites ouvertures par dépôt électrolytique dans un bain; la suppression de la matière de masque; la coupure des branches de connexion (7) ; et le passage ou la mise dans un four de façon à conformer, sur les zones conductrices, lesdits blocs en des plots de connexion électrique (3a, 3b) substantiellement bombés.

제1 및 제2 구성요소들의 조립 후에 금속 커넥터를 도금함으로써 마이크로전자 조립체를 형성하는 방법 및 대응하는 장치

... 마이크로전자 조립체들 및 이의 제조 방법들이 본 명세서에 개시된다. 일 실시예에서, 마이크로전자 조립체의 형성 방법은 제1 및 제2 구성요소(102, 128)들의 제1 주 표면(104, 130)들이 서로 대면하고 사전결정된 간격만큼 서로 이격되도록 제1 및 제2 구성요소(102, 128)들을 조립하는 단계로서, 제1 구성요소(102)는 반대편을 향하는 제1 및 제2 주 표면(104, 106)들, 제1 주 표면(104)과 제2 주 표면(106) 사이에서 제1 방향으로 연장되는 제1 두께, 및 제1 주 표면(104)에 있는 복수의 제1 금속 접속 요소(112)들을 구비하고, 제2 구성요소(128)는 제2 구성요소(128)의 제1 주 표면(130)에 있는 복수의 제2 금속 접속 요소(132)들을 구비하는, 상기 제1 및 제2 구성요소들을 조립하는 단계; 및 이어서 각자의 제1 접속 요소(112)와 각자의 제1 접속 요소(112)의 반대편의 대응하는 제2 접속 요소(132) 사이에서 각각 제1 방향으로 연속적으로 연장되어 접속하는 복수의 금속 커넥터 영역(146)들을 도금(전기 도금 또 무전해 도금)하는 단계를 포함한다. 제1 및 제2 금속 접속 요소(112, 132)들은 구성요소(102, 128)들 내의 금속 비아(116, 134)들 또는 구성요소(102, 128)들의 표면에 있는 금속 패드(118)들을 포함할 수 있는데, 금속 비아(116, 134)들 또는 금속 패드(118)들은 도금 금속 영역(114)들에 의해 덮인다. 제1 시드 층(126)이 도금 공정 전에 제1 구성요소(102)의 주 표면 위에 놓이게 형성될 수 있는데, 여기서 금속 커넥터 영역(146)들을 도금한 후에 제1 시드 층(126)의 덮이지 않은 부분들이 제거된다. 유사하게, 제2 시드 층(144)이 제2 구성요소(128)의 주 표면 위에 놓이게 형성될 수 있다. 복수의 장벽 영역(152)들이 금속 커넥터 영역(146)들, 제1 도금 금속 영역(114)들 또는 제2 도금 금속 영역들 중 적어도 하나의 ...

Bump structure and the method for fabricating the same

Substrate, semiconductor chip, and semiconductor package having bump, and methods of fabricating the same

Chip having metal pillar structure

The present invention relates to a chip having metal pillar structure. The chip includes a chip body, at least one chip pad, a first passivation layer, an under ball metal layer and at least one metal pillar structure. The chip body has an active surface. The chip pad is disposed on the active surface. The first passivation layer is disposed on the active surface, and has at least one first opening so as to expose part of the chip pad. The under ball metal layer is disposed on the chip pad. The metal pillar structure is disposed on the under ball metal layer, and includes a metal pillar and a solder. The metal pillar is disposed on the under ball metal layer. The solder is disposed on the metal pillar, and the diameter of the solder is smaller than or equals to that of the metal pillar. Therefore, when the pitch between two metal pillar structures of the chip is fine pitch, the problem of solder bridge can be avoided, so that the yield rate is raised.

Semiconductor device and method of forming interconnect structure over seed layer on contact pad of semiconductor die without undercutting seed layer beneath interconnect structure

A semiconductor device has a semiconductor die with a first conductive layer formed over the die. A first insulating layer is formed over the die with a first opening in the first insulating layer disposed over the first conductive layer. A second conductive layer is formed over the first insulating layer and into the first opening over the first conductive layer. An interconnect structure is constructed by forming a second insulating layer over the first insulating layer with a second opening having a width less than the first opening and depositing a conductive material into the second opening. The interconnect structure can be a conductive pillar or conductive pad. The interconnect structure has a width less than a width of the first opening. The second conductive layer over the first insulating layer outside the first opening is removed while leaving the second conductive layer under the interconnect structure.

Solder bump, flip chip structure and method for preparing the same

The present disclosure provides a flip chip structure comprising a substrate, a bond pad, a passivation layer surrounding the bond pad, a first solder bump and a second solder bump. The first solder bump includes a first pillar formed on the bond pad and an adjacent portion of the passivation layer and extending in a vertical direction, a first coated layer fittingly formed on the first pillar, and a first solder ball formed on the first coated layer. The second solder bump includes a second pillar formed on a portion of the passivation layer and extending in the vertical direction, a second coated layer fittingly formed on the second pillar, and a second solder ball formed on the second coated layer. The first pillar includes a depression formed in the shape of an inverted cone and formed in a top surface of the first pillar.

Low fabrication cost, fine pitch and high reliability solder bump

A barrier layer is deposited over a layer of passivation including in an opening to a contact pad created in the layer of passivation. A column of three layers of metal is formed overlying the barrier layer and aligned with the contact pad and having a diameter that is about equal to the surface of the contact pad. The three metal layers of the column comprise, in succession when proceeding from the layer that is in contact with the barrier layer, a layer of pillar metal, a layer of under bump metal and a layer of solder metal. The layer of pillar metal is reduced in diameter, the barrier layer is selectively removed from the surface of the layer of passivation after which reflowing of the solder metal completes the solder bump of the invention.

METHOD OF MAKING A BUMP ON A SUBSTRATE USING MULTIPLE PHOTORESIST LAYERS

A method of forming a bump on a substrate such as a semiconductor wafer or flip chip. The method includes the step of providing a semiconductor device having a contact pad and an upper passivation layer and an opening formed in the upper passivation layer exposing a portion of the contact pad. An under bump metallurgy is deposited over the upper passivation layer and the contact pad. A first photoresist layer is deposited in a liquid state so that the first photoresist layer covers the under bump metallurgy. A second photoresist layer is deposited and the second photoresist layer is a dry film photoresist. The unexposed portions of the first photoresist layer are removed. The remaining portions of the first photoresist layers are removed. The electrically conductive material is reflown to provide a bump on the semiconductor device.

Process of making pad structure for solder ball limiting metallurgy having reduced edge stress

A two-step masking process is disclosed for forming a ball limiting metallurgy (BLM) pad structure for a solder joint interconnection used between a support substrate and a semiconductor chip. A solder non-wettable layer and a solder wettable layer are deposited on the surface of a support substrate or semiconductor chip which are to be connected. A phased transition layer is deposited between the wettable and non-wettable layers. A thin photo-resist mask defines an area of the solder wettable and phased layers which are etched to form a raised, wettable frustum cone portion. A second mask is deposited on the surface of the support substrate or semiconductor chip, and has an opening concentrically positioned about the frustum cone. Solder is deposited in the opening and covers the frustum cone and the area about its periphery. When solidified, the solder, acting as a mask, is used to sub-etch the underlying solder non-wettable layer thereby defining the BLM pad. When reflowed, the solder ...

Semiconductor device with flip chip bonding pads and manufacture thereof

A semiconductor substrate is prepared which has a principal surface, an exposed pad made of conductive material being formed in a partial area of the principal surface, and the other area of the principal surface being covered with a first insulating film. A base conductive film is formed on the first insulating film and the pad. A photoresist film having a thickness of 50 mum or thicker is formed on the base conductive film. An opening is formed through the photoresist film in an area corresponding to the pad to expose a partial surface area of the base conductive film. A conductive bump electrode is deposited on the base conductive film exposed on a bottom of the opening. The photoresist film is removed. This method is suitable for making a fine pitch between bump electrodes.

FORMING ROBUST SOLDER INTERCONNECT STRUCTURES BY REDUCING EFFECTS OF SEED LAYER UNDERETCHING

A method for forming an interconnect structure for a semiconductor device includes defining a via in a passivation layer so as expose a top metal layer in the semiconductor device. A seed layer is formed over the passivation layer, sidewalls of the via, and the top metal layer. A barrier layer is formed over an exposed portion of the seed layer, the exposed portion defined by a first patterned opening of a first diameter, and a solder material is formed over the barrier layer using a second patterned opening of a second diameter. The second patterned opening is configured such that the second diameter is larger than the first diameter.

Etchant and method for manufacturing semiconductor device using same

Disclosed are an etchant which is used for redistribution of a semiconductor substrate having an electrode and which is capable of selectively etching copper without etching nickel; and a method for manufacturing a semiconductor device using the same. Specifically disclosed are an etchant which is used for redistribution of a semiconductor substrate and which contains hydrogen peroxide and citric acid and has a content of hydrogen peroxide of from 0.75 to 12% by mass and a content of citric acid of from 1 to 20% by mass, with a molar ratio of hydrogen peroxide and citric acid being in the range of from 0.3 to 5; an etchant for selective etching of copper which is used for redistribution of a semiconductor substrate and which contains hydrogen peroxide and malic acid and has a content of hydrogen peroxide of from 0.75 to 12% by mass and a content of malic acid of from 1.5 to 25% by mass, with a molar ratio of hydrogen peroxide and malic acid being in the range of from 0.2 to 6; and a method ...

Method of manufacturing a through electrode

A through electrode that offers excellent performance and can be manufactured through a simple process is to be provided. In a silicon spacer including a silicon substrate, an insulative thick film is provided so as to be in contact with a surface of the silicon substrate and a side wall of a through hole penetrating the silicon substrate. An upper surface of a through plug is retreated to a lower level than an interface between the silicon substrate and the insulative thick film, thus to define a height gap. A first bump is then formed, which is connected to the retreated surface of the through plug and has a larger diameter than that of the through plug at the upper surface of the insulative thick film.

Semiconductor device

Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion formed on the upper surface of a semiconductor substrate, a passivation layer so formed on the upper surface of the semiconductor substrate as to overlap a part of the electrode pad portion and having a first opening portion where the upper surface of the electrode pad portion is exposed, a barrier metal layer formed on the electrode pad portion, and a solder bump formed on the barrier metal layer. The barrier metal layer is formed such that an outer peripheral end lies within the first opening portion of the passivation layer when viewed in plan.

SEMICONDUCTOR DEVICE

A semiconductor chip includes a substrate, an electrode pad formed on the substrate, an insulating layer covering the substrate and the electrode pad, and having an opening exposing a portion of a surface of the electrode pad, a first conductive layer formed on the exposed portion of the surface of the electrode pad and extending to a surface of the insulating layer, and a second conductive layer formed on the first conductive layer, covering the first conductive layer in a plan view, and having an outer edge portion which is located further out than an outer edge of the first conductive layer in a plan view. The outer edge portion of the second conductive layer has at least one curved portion. At least one portion of the curved portion is located between the outer edge of the first conductive layer and an outer edge of the second conductive layer in a plan view.

MULTI-FACED MOLDED SEMICONDUCTOR PACKAGE AND RELATED METHODS

Implementations of a method of forming a semiconductor package may include forming electrical contacts on a first side of a wafer, applying a photoresist layer to the first side of the wafer, patterning the photoresist layer, and etching notches into the first side of the wafer using the photoresist layer. The method may include applying a first mold compound into the notches and over the first side of the wafer, grinding a second side of the wafer opposite the first side of the wafer to the notches formed in the first side of the wafer, applying one of a second mold compound and a laminate resin to a second side of the wafer, and singulating the wafer into semiconductor packages. Six sides of each semiconductor package may be covered by one of the first mold compound, the second mold compound, and the laminate resin.

Visibility event navigation method and system

A method of visibility event navigation includes receiving, via processing circuitry of a client device, a first visibility event packet from a server, the first visibility event packet including information representing 3D surface elements of an environmental model that are occluded from a first viewcell and not occluded from a second viewcell, the first and second viewcells representing spatial regions of a specified navigational route within a real environment modeled by the environmental model. The method also includes acquiring, surface information representing the visible surfaces of the real environment at a sensor and determining, a position in the real environment by matching the surface information to the visibility event packet information. The method further includes transmitting, the position from the client device to the server and receiving a second visibility event packet from the server if the at least one position is within the specified navigational route.

METHOD FOR FABRICATING HIGH-EFFICIENCY MICRO-LED MODULE

Disclosed is a method for fabricating a high-efficiency micro-LED module. The method includes: preparing a micro-LED in which an epilayer is grown on a sapphire substrate, a plurality of LED cells are formed on the epilayer, a plurality of individual electrode pads are disposed such that one individual electrode pad is assigned to each LED cell, and a common electrode pad is formed on an area surrounding the plurality of LED cells; preparing a submount substrate including a plurality of individual electrodes corresponding to the individual electrode pads and a common electrode corresponding to the common electrode pad; mounting the micro-LED on the submount substrate such that the plurality of individual electrodes are connected to the plurality of individual electrode pads and the common electrode pad is connected to the common electrode through a plurality of bonding connection members; forming a buffer layer between the micro-LED and the submount substrate; and irradiating a laser around ...

Pillar on pad interconnect structures, semiconductor dice and die assemblies including such interconnect structures, and related methods

Methods of fabricating interconnect structures for semiconductor dice comprise forming conductive elements in contact with bond pads on an active surface over a full pillar diameter of the conductive elements, followed by application of a photodefinable material comprising a photoresist to the active surface and over the conductive elements. The polyimide material is selectively exposed and developed to remove photodefinable material covering at least tops of the conductive elements. Semiconductor dice and semiconductor die assemblies are also disclosed.

Wafer to wafer bonding process and structures

Bonded structures and method of forming the same are provided. A conductive layer is formed on a first surface of a bonded structure, the bonded structure including a first substrate bonded to a second substrate, the first surface of the bonded structure being an exposed surface of the first substrate. A patterned mask having first openings and second openings is formed on the conductive layer, the first openings and the second openings exposing portions of the conductive layer. First portions of first bonding connectors are formed in the first openings and first portions of second bonding connectors are formed in the second openings. The conductive layer is patterned to form second portions of the first bonding connectors and second portions of the second bonding connectors. The bonded structure is bonded to a third substrate using the first bonding connectors and the second bonding connectors.

FABRICATION METHOD OF SEMICONDUCTOR STRUCTURE

The present invention provides a semiconductor structure and a method of fabricating the same. The method includes: providing a chip having conductive pads, forming a metal layer on the conductive pads, forming a passivation layer on a portion of the metal layer, and forming conductive pillars on the metal layer. Since the metal layer is protected by the passivation layer, the undercut problem is solved, the supporting strength of the conductive pillars is increased, and the product reliability is improved.

Fabrication method of semiconductor package with stacked semiconductor chips

A semiconductor package includes a build-up structure; a semiconductor disposed on the build-up structure in a flip-chip manner and having a plurality of bumps penetrating therethrough; an electronic element disposed on the semiconductor chip; and an encapsulant formed on the build-up structure and encapsulating the semiconductor chip and the electronic element, thereby improving the product yield and the overall heat dissipating efficiency.

Connector structure and method of forming same

Connector structures and methods of forming the same are provided. A method includes forming a first patterned passivation layer on a workpiece, the first patterned passivation layer having a first opening exposing a conductive feature of the workpiece. A seed layer is formed over the first patterned passivation layer and in the first opening. A patterned mask layer is formed over the seed layer, the patterned mask layer having a second opening exposing the seed layer, the second opening overlapping with the first opening. A connector is formed in the second opening. The patterned mask layer is partially removed, an unremoved portion of the patterned mask layer remaining in the first opening. The seed layer is patterned using the unremoved portion of the patterned mask layer as a mask.

Method of forming cu pillar capped by barrier layer

A nickel barrier layer is formed on an upper sidewall surface of a Cu pillar. A mask layer with an opening for defining the Cu pillar window has an upper portion and a lower portion. The upper portion of the mask layer is removed after the formation of the Cu pillar so as to expose the upper sidewall surface of the Cu pillar. The nickel barrier layer is then deposited on the exposed sidewall surface of the Cu pillar followed by removing and the lower portion of the mask layer.

Interconnections for flip-chip using lead-free solders and having reaction barrier layers

An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting composition including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components. With a two-layer ball-limiting composition comprising an adhesion/reaction barrier layer, wherein the adhesion/reaction barrier layer serves both as an adhesion layer and a reaction barrier layer, the adhesion/reaction barrier layer can be comprised of a material selected from the group consisting of Zr and ZrN

Mechanisms for forming copper pillar bumps using patterned anodes

The mechanisms of preparing bump structures described by using patterned anodes may simplify bump-making process, reduce manufacturing cost, and improve thickness uniformity within die and across the wafer. In addition, the mechanisms described above allow forming bumps with different heights to allow bumps to be integrated with elements on a substrate with different heights. Bumps with different heights expand the application of copper post bumps to enable further chip integration.

Conductive connection structure with stress reduction arrangement for a semiconductor device, and related fabrication method

A semiconductor device disclosed herein includes a conductive connection structure having a stepped profile that serves as a stress relief feature. The conductive connection structure includes a stress buffer arrangement for a contact pad. The stress buffer arrangement has a stepped via that terminates at the contact pad, and the stepped via has a plurality of inwardly sloped and concentric sections in a stacked orientation. The connection structure also includes underbump metallization overlying at least a portion of the contact pad and lining the stepped via, and a conductive connection element coupled to the underbump metallization. The conductive connection element fills the lined recess.

Semiconductor device having pad structure with stress buffer layer

A semiconductor device has a pad structure with a ring-shaped stress buffer layer between a metal pad and an under-bump metallization (UBM) layer. The stress buffer layer is formed of a dielectric layer with a dielectric constant less than 3.5, a polymer layer, or an aluminum layer. The stress buffer layer is a circular ring, a square ring, an octagonal ring, or any other geometric ring.

Semiconductor device and manufacturing method thereof

Semiconductor devices of embodiments include a plurality of solder bumps electrically connected on a plurality of electrode pads disposed on a semiconductor substrate in parallel at a pitch of 40 μm or less via under bump metals. The ratio of the diameter (the top diameter) of the portion of each solder bump most away from the semiconductor substrate and the diameter (the bottom diameter) of the bottom side of each solder bump is 1:1 to 1:4.

Semiconductor assembly and semiconductor package including a solder channel

Semiconductor packages connecting a semiconductor chip to an external device by bumps are provided. The semiconductor packages may include a connection pad on a semiconductor chip, a connecting bump on and configured to be electrically connected to the connection pad and a supporting bump on the semiconductor chip and configured to be electrically isolated from the connection pad. The connection bump may include a first pillar and a first solder ball and the supporting bump may include a second pillar and a second solder ball. The semiconductor packages may further include a solder channel in the second pillar configured to allow a portion of the second solder ball to extend into the solder channel along a predetermined direction.

Conductive feature for semiconductor substrate and method of manufacture

A conductive feature on a semiconductor component is disclosed. A first passivation layer is formed over a substrate. A bond pad is formed over the first passivation layer. A second passivation layer overlies the first passivation layer and the bond pad. The second passivation layer has a first opening overlying the bond pad and a plurality of second openings exposing a top surface of the first passivation layer. A buffer layer overlies the second passivation layer and fills the plurality of second openings. The buffer layer has a third opening overlapping the first opening and together exposes a portion the bond pad. The combined first opening and third opening has sidewalls. An under bump metallurgy (UBM) layer overlies the sidewalls of the combined first opening and third opening, and contacts the exposed portion of the bond pad. A conductive feature overlies the UBM layer.

Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device including the following steps: forming an insulator layer over a first conductor over a semiconductor substrate; forming a barrier layer to coat the surface of the insulator layer; forming a second conductor over the barrier layer; melting the second conductor in an atmosphere containing either hydrogen or carboxylic acid in a condition that the surface of the insulator layer over the first conductor is coated with the barrier layer; and removing the barrier layer partially from the surface of the insulator layer with the second conductor as a mask.

Semiconductor chip and flip-chip package comprising the same

A semiconductor chip includes stress-relief to mitigate the effects of differences in coefficients of thermal expansion (CTE) between a printed circuit board (PCB) and a semiconductor chip and a flip-chip package including the semiconductor chip. The semiconductor chip includes a stress-relief buffer coupling a bump and a semiconductor chip pad.

Semiconductor Device with Solder Bump Formed on High Topography Plated Cu Pads

A semiconductor device has a first conductive layer formed over a substrate. A first insulating layer is formed over the substrate and first conductive layer. A second conductive layer is formed over the first conductive layer and first insulating layer. A second insulating layer is formed over the first insulating layer and second conductive layer. The second insulating layer has a sidewall between a surface of the second insulating material and surface of the second conductive layer. A protective layer is formed over the second insulating layer and surface of the second conductive layer. The protective layer follows a contour of the surface and sidewall of the second insulating layer and second conductive layer. A bump is formed over the surface of the second conductive layer and a portion of the protective layer adjacent to the second insulating layer. The protective layer protects the second insulating layer.

Solder Bump with Inner Core Pillar in Semiconductor Package

A flip chip semiconductor package has a substrate with a plurality of active devices. A contact pad is formed on the substrate in electrical contact with the plurality of active devices. A passivation layer, second barrier layer, and adhesion layer are formed between the substrate and an intermediate conductive layer. The intermediate conductive layer is in electrical contact with the contact pad. A copper inner core pillar is formed by plating over the intermediate conductive layer. The inner core pillar has a rectangular, cylindrical, toroidal, or hollow cylinder form factor. A solder bump is formed around the inner core pillar by plating solder material and reflowing the solder material to form the solder bump. A first barrier layer and wetting layer are formed between the inner core pillar and solder bump. The solder bump is in electrical contact with the intermediate conductive layer.

Power management applications of interconnect substrates

Various applications of interconnect substrates in power management systems are described.

Adjusting Sizes of Connectors of Package Components

A device includes a plurality of connectors on a top surface of a package component. The plurality of connectors includes a first connector having a first lateral dimension, and a second connector having a second lateral dimension. The second lateral dimension is greater than the first lateral dimension. The first and the second lateral dimensions are measured in directions parallel to a major surface of the package component.

Semiconductor device and method of manufacturing the same

A semiconductor device includes a first bump that is located over a surface of a semiconductor element, and is formed on a first bump formation face distanced from a back surface of the semiconductor element at a first distance, and a second bump that is located over the surface of the semiconductor element, and is formed on a second bump formation face distanced from the back surface of the semiconductor element at a second distance being longer than the first distance, the second bump having a diameter larger than a diameter of the first bump.

Cleaning Methods and Compositions

Methods and chemical solvents used for cleaning residues on metal contacts during a semiconductor device packaging process are disclosed. A chemical solvent for cleaning a residue formed on a metal contact may comprise a reactive inorganic component and a reactive organic component. The method may comprise spraying a semiconductor device with a chemical solvent at a first pressure, and spraying the semiconductor device with the chemical solvent at a second pressure less than the first pressure.

Low-temperature flip chip die attach

A mechanism for electrically coupling a semiconductor device die to a semiconductor device package substrate that avoids introduction of excessive temperature induced stresses to the semiconductor device die interconnect is provided. In one embodiment, the semiconductor device die is mechanically attached to the package substrate (or another semiconductor device die) at room temperature through the use of a plug-in socket or wedge connection having corresponding mating features formed on the die and substrate. The mechanical interconnect features can be formed on the die and substrate interconnects using an electroplating process. The surfaces of the semiconductor device die and package substrate can then be coupled using an underfill material. A low-temperature solid state bonding process can then be used to diffuse the materials forming the plug and socket features in order to form the electrical connection.

Packaging Structures and Methods with a Metal Pillar

A package component is free from active devices therein. The package component includes a substrate, a through-via in the substrate, a top dielectric layer over the substrate, and a metal pillar having a top surface over a top surface of the top dielectric layer. The metal pillar is electrically coupled to the through-via. A diffusion barrier is over the top surface of the metal pillar. A solder cap is disposed over the diffusion barrier.

Semiconductor devices having through electrodes, methods of manufacturing the same, and semiconductor packages including the same

A semiconductor device includes a semiconductor layer having a first surface and a second surface, a through electrode penetrating the semiconductor layer and having a protruding portion that protrudes over the second surface of the semiconductor layer, a front-side bump disposed on the first surface of the semiconductor layer and electrically coupled to the through electrode, a passivation pattern including a first insulation pattern that surrounds a sidewall of the protruding portion of the through electrode and extends onto the second surface of the semiconductor layer and a second insulation pattern that covers the first insulation pattern and has an etch selectivity with respect to the first insulation pattern, and a back-side bump covering an end surface of the protruding portion of the through electrode and extending onto the passivation pattern.

BUMP STRUCTURES FOR INTERCONNECTING FOCAL PLANE ARRAYS

A method of forming bump structures for interconnecting components includes dry etching a layer of insulating material to create a pattern for bump structures. A seed layer is deposited on the insulating material over the pattern. The seed layer is patterned with a photo resist material. The method also includes forming bump structures over the seed layer and the photo resist material with a plating material to form bump structures in the pattern, wherein the bump structures are isolated from one another. 1. A system comprising:a layer of insulating material with holes therein;a seed layer seated within the holes, wherein the seed layer is recessed below a top surface of the insulating material that is opposite a bottom surface of the holes; anda respective bump structure seated in the seed layer of each hole.2. The system as recited in claim 1 , wherein the bump structures are on one of a photodiode array (PDA) or a read-out integrated circuit (ROIC) claim 1 , and wherein the PDA and ROIC are joined together by the bump structures.3. The system as recited in claim 2 , wherein the PDA and ROIC define a plurality of pixels claim 2 , wherein the plurality of pixels have a pitch size claim 2 , wherein the pitch size is less than 10 μm.4. The system as recited in claim 1 , wherein the bump structures each have a diameter less than 5 um.5. The system as recited in claim 1 , wherein the bump structures each have a height to diameter ratio of greater than 1:1.6. The system as recited in claim 1 , wherein a portion of the bump structures extend from the seed layer proud of the top surface of the insulating material.7. The system as recited in claim 1 , further comprising a dielectric layer on the top surface of the insulating material claim 1 , wherein the seed layer is recessed below the insulating material to provide a gap between the bump structures and the insulating material claim 1 , wherein the gap between the bump structures and the insulating material is also ...

Semiconductor Devices, Methods of Manufacture Thereof, and Semiconductor Device Packages

Semiconductor devices, methods of manufacture thereof, and semiconductor device packages are disclosed. In one embodiment, a semiconductor device includes an insulating material layer having openings on a surface of a substrate. One or more insertion bumps are disposed over the insulating material layer. The semiconductor device includes signal bumps having portions that are not disposed over the insulating material layer. 1. A method of manufacturing a semiconductor device , the method comprising:forming a insulating material layer over a first substrate;removing a first portion of the insulating material layer to expose a contact pad at a top surface of the first substrate;forming one or more first insertion bumps over the insulating material layer; andwhile forming the one or more first insertion bumps, forming a first signal bump extending through the insulating material layer and electrically connected to the contact pad.2. The method according to claim 1 , wherein forming the one or more first insertion bumps and forming the first signal bump comprises:patterning a mask to form a first opening over the contact pad on the top surface of the first substrate, and to form one or more second openings over one or more areas of the insulating material layer over which the one or more first insertion bumps will be formed;performing a first plating process with a first conductive material to deposit the first conductive material in the first opening and the one or more second openings; andremoving the mask.3. The method according to claim 2 , further comprising:before removing the mask, performing a second plating process with a second conductive material to deposit the second conductive material in the first opening of the mask and the one or more second openings of the mask, wherein the second conductive material is different than the first conductive material.4. The method according to claim 2 , further comprising patterning the insulating material layer to remove ...

Leadframes in Semiconductor Devices

In one instance, a method of forming a semiconductor package with a leadframe includes cutting, such as with a laser, a first side of a metal strip to a depth D according to a cutting pattern to form a first plurality of openings, which may be curvilinear. The method further includes etching the second side of the metal strip to a depth D according to a photoresist pattern to form a second plurality of openings. At least some of the first plurality of openings are in fluid communication with at least some of the second plurality of openings to form a plurality of leadframe leads. The depth D is shallower than a height H of the metal strip, and the depth D is also shallower than the height H. Other embodiments are presented. 1. A method for forming a semiconductor package , the method comprising:cutting a first side of the metal strip to a first depth according to a cutting pattern to form a plurality of first channels, wherein the first depth is less than a height of the metal strip;etching a second side of the metal strip, opposing the first side to form a second plurality of channels including a second depth less than the height of the metal strip;coupling a plurality of bumps of a semiconductor die to the first side of the metal strip; andcovering at least a portion of the semiconductor die and at least a portion of the metal strip with a molding compound, wherein the cutting pattern is non-linear.2. The method of claim 1 , wherein the cutting is performed after etching.3. The method of claim 1 , wherein the height of the metal strip is between the first side and the second side of the metal strip.4. The method of claim 1 , wherein the plurality of bumps are aligned in multiple rows claim 1 , at least one of the plurality of bumps from at least two adjacent rows of the multiple rows overlap with each other from a side view of the semiconductor package.5. The method of claim 1 , wherein the second depth is more than the first depth.6. The method of claim 1 , ...

METHOD FOR FORMING BUMP STRUCTURE

Methods for forming semiconductor structures are provided. The method for forming a semiconductor structure includes forming a metal pad over a first substrate and forming a resist layer having an opening over the metal layer. The method for forming a semiconductor structure further includes forming a conductive pillar and a solder layer over the conductive pillar in the opening of the resist layer and removing the resist layer. The method for forming a semiconductor structure further includes removing a portion of the conductive pillar so that the conductive pillar has an angled sidewall. 1. A method for forming a semiconductor structure , comprising:forming a metal pad over a first substrate;forming a resist layer having an opening over the metal layer;forming a conductive pillar and a solder layer over the conductive pillar in the opening of the resist layer;removing the resist layer; andremoving a portion of the conductive pillar so that the conductive pillar has an angled sidewall.2. The method for forming a semiconductor structure as claimed in claim 1 , wherein the angled sidewall includes a first sidewall at a top portion of the conductive pillar and a second sidewall at a bottom portion of the conductive pillar claim 1 , and the first sidewall is in a first direction and the second sidewall is in a second direction different from the first direction.3. The method for forming a semiconductor structure as claimed in claim 2 , further comprising:reflowing the solder layer after the removing the portion of the conductive pillar to form the angled sidewall.4. The method for forming a semiconductor structure as claimed in claim 3 , wherein an inter-metal compound is formed partially covering the first sidewall of the top portion of the conductive pillar after reflowing the solder layer.5. The method for forming a semiconductor structure as claimed in claim 1 , further comprising:forming a seed layer over the metal pad before the conductive pillar is formed, ...

Semiconductor product with interlocking metal-to-metal bonds and method for manufacturing thereof

A structure and method for performing metal-to-metal bonding in an electrical device. For example and without limitation, various aspects of this disclosure provide a structure and method that utilize an interlocking structure configured to enhance metal-to-metal bonding.

Semiconductor Devices and Methods of Forming Thereof

In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes forming a contact layer over a first major surface of a substrate. The substrate includes device regions separated by kerf regions. The contact layer is disposed in the kerf region and the device regions. A structured solder layer is formed over the device regions. The contact layer is exposed at the kerf region after forming the structured solder layer. The contact layer and the substrate in the kerf regions are diced.

METHOD FOR FORMING BUMP STRUCTURE

Methods for forming semiconductor structures are provided. The method for forming a semiconductor structure includes forming a metal pad over a first substrate and forming a polymer layer over the metal pad. The method for forming a semiconductor structure further includes forming a seed layer over the metal pad and extending over the polymer layer and forming a conductive pillar over the seed layer. The method for forming a semiconductor structure further includes wet etching the seed layer using an etchant comprising H2O2. In addition, the step of wet etching the seed layer is configured to form an extending portion having a slope sidewall. 1. A method for forming a semiconductor structure , comprising:forming a metal pad over a first substrate;forming a polymer layer over the metal pad;forming a seed layer over the metal pad and extending over the polymer layer;forming a conductive pillar over the seed layer; and{'sub': 2', '2, 'wet etching the seed layer using an etchant comprising HO, wherein the step of wet etching the seed layer is configured to form an extending portion having a slope sidewall.'}2. The method for forming a semiconductor structure as claimed in claim 1 , wherein the slope sidewall extends from a bottommost of a sidewall of the conductive pillar to a top surface of the polymer layer.3. The method for forming a semiconductor structure as claimed in claim 2 , wherein an inclination of the slope sidewall of the extending portion of the seed layer is different from an inclination of the sidewall of the conductive pillar.4. The method for forming a semiconductor structure as claimed in claim 3 , wherein an angle between the slope sidewall and a bottom surface of the seed layer is in a range from about 20° to about 80°.5. The method for forming a semiconductor structure as claimed in claim 1 , wherein the conductive pillar is directly formed on the seed layer.6. The method for forming a semiconductor structure as claimed in claim 1 , further ...

Etching liquid, etching method, and method of manufacturing solder bump

An etching liquid which can selectively remove only a copper layer in an etching process of a multilayer structure including a cobalt layer and the copper layer is disclosed. The etching liquid is an etching liquid for etching the copper layer in the multilayer structure including the copper layer and the cobalt layer. This etching liquid includes at least one acid selected from a group consisting of citric acid, oxalic acid, malic acid, and malonic acid, and hydrogen peroxide, the etching liquid having pH in a range of 4.3 to 5.5.

Single-Shot Encapsulation

A semiconductor device includes a semiconductor wafer. A plurality of pillar bumps is formed over the semiconductor wafer. A solder is deposited over the pillar bumps. The semiconductor wafer is singulated into a plurality of semiconductor die after forming the pillar bumps while the semiconductor wafer is on a carrier. An encapsulant is deposited around the semiconductor die and pillar bumps while the semiconductor die remains on the carrier. The encapsulant covers an active surface of the semiconductor die between the pillar bumps.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A flip-chip mounting technique with high reliability is provided in flip-chip mounting using a Cu pillar. In a semiconductor device to be coupled to a mounting board via a Cu pillar, the Cu pillar is caused to have a laminated structure including a pillar layer, a barrier layer, and a bump in this order from below, and the bump is formed to be smaller than the barrier layer. 1. A manufacturing method of a semiconductor device , comprising the steps of:(a) applying a resist film over a terminal pad formed over a main surface of a semiconductor substrate;(b) forming an opening in the resist film for exposing the terminal pad in the bottom thereof;(c) forming a Cu film, an Ni film, and an SnAg film in the opening in this order from below;(d) removing the resist film; and(e) etching an outer peripheries of the SnAg film.2. The manufacturing method of a semiconductor device according to claim 1 ,wherein, in the step (e), the etching is performed by using dilute hydrofluoric acid.3. The manufacturing method of a semiconductor device according to claim 1 ,wherein, in the step (b), the forming the opening is performed by using photolithography.4. The manufacturing method of a semiconductor device according to claim 1 ,wherein, in the step (c), the Cu film, the Ni film, and the SnAg film are formed by electrolytic plating.5. The manufacturing method of a semiconductor device according to claim 1 ,wherein, in the step (d), the resist film is removed by ashing.6. The manufacturing method of a semiconductor device according to claim 1 ,wherein, in the step (e), the outer peripheries of the SnAg film is wet etched.7. A manufacturing method of a semiconductor device claim 1 , comprising the steps of:(a) applying a first resist film over a terminal pad formed over a main surface of a semiconductor substrate;(b) forming a first opening in the first resist film for exposing the terminal pad in the bottom thereof;(c) forming a Cu film and an Ni film in this order from below;(d) ...

Logic drive based on standardized commodity programmable logic semiconductor ic chips

A chip package includes an interposer comprising a silicon substrate, multiple metal vias passing through the silicon substrate, a first interconnection metal layer over the silicon substrate, a second interconnection metal layer over the silicon substrate, and an insulating dielectric layer over the silicon substrate and between the first and second interconnection metal layers; a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip over the interposer; multiple first metal bumps between the interposer and the FPGA IC chip; a first underfill between the interposer and the FPGA IC chip, wherein the first underfill encloses the first metal bumps; a non-volatile memory (NVM) IC chip over the interposer; multiple second metal bumps between the interposer and the NVM IC chip; and a second underfill between the interposer and the NVM IC chip, wherein the second underfill encloses the second metal bumps.

Barrier materials between bumps and pads

Disclosed are barrier materials between bumps and pads, and related devices and methods. A semiconductor device includes an interconnect, a top material, a pad on the interconnect and at least a portion of the top material, a bump on the pad, and a barrier material between the pad and the bump. The top material defines a via therethrough to the interconnect. The pad includes electrically conductive material. The bump includes electrically conductive material. The bump is configured to electrically connect the interconnect to another device. The barrier material is between the pad and the bump. The barrier material includes a conductive material that is resistant to electromigration, intermetallic compound reaction, or both electromigration and intermetallic compound reaction.

ELECTROSTATIC DISCHARGE PROTECTION APPARATUS AND PROCESS

In a process, at least one circuit element is formed in a substrate. A conductive layer is formed over the substrate and in electrical contact with the at least one circuit element. Electrostatic charges are discharged from the substrate via the conductive layer. 1. A method forming a semiconductor device , comprising:forming at least one circuit element in each die of a plurality of dies in a substrate, where an outer region of the substrate surrounds each die of the plurality of dies;forming a conductive layer over the substrate, wherein the conductive layer is over and vertically aligned with at least one die of the plurality of dies and over and vertically aligned with a portion of the outer region, the conductive layer in electrical contact with the at least one circuit element in the at least one die;discharging electrostatic charges from the substrate via the conductive layer, wherein the discharging includes directly contacting a grounded electrode to a top surface of the conductive layer; andafter the discharging electrostatic charges removing a portion of the conductive layer.2. The method of claim 1 , whereindischarging the electrostatic charges comprises causing the grounded electrode to temporarily contact the conductive layer over the outer region.3. The method of claim 2 , whereinthe outer region comprises at least one scribe line,said discharging the electrostatic charges comprises causing the grounded electrode to temporarily contact the conductive layer over the at least one scribe line.4. The method of claim 1 , wherein the plurality of dies includes at least one interposer.5. The method of claim 1 , further comprising:forming a conductive bump over the substrate prior to the discharging electrostatic charges.6. The method of claim 1 , wherein the conductive layer includes an under-bump metal (UBM) structure.7. The method of claim 1 , wherein the removing the portion of the conductive layer includes performing photolithographic masking and etching ...

Design Scheme for Connector Site Spacing and Resulting Structures

A system and method for preventing cracks in a passivation layer is provided. In an embodiment a contact pad has a first diameter and an opening through the passivation layer has a second diameter, wherein the first diameter is greater than the second diameter by a first distance of about 10 μm. In another embodiment, an underbump metallization is formed through the opening, and the underbump metallization has a third diameter that is greater than the first diameter by a second distance of about 5 μm. In yet another embodiment, a sum of the first distance and the second distance is greater than about 15 μm. In another embodiment the underbump metallization has a first dimension that is less than a dimension of the contact pad and a second dimension that is greater than a dimension of the contact pad. 1. A device comprising:a first contact pad on a first substrate, the first contact pad having a first line of symmetry and a second line of symmetry, the first line of symmetry being perpendicular to the second line of symmetry, the first contact pad having a first width along the first line of symmetry, the first contact pad having a second width along the second line of symmetry;a first underbump metallization on the first contact pad; anda first conductive bump on the first underbump metallization, the first conductive bump, having a third line of symmetry and a fourth line of symmetry, the third line of symmetry being perpendicular to the fourth line of symmetry, the first conductive bump having a third width along the third line of symmetry, the first conductive bump having a fourth width along the fourth line of symmetry, the third width being greater than the first width, the fourth width being less than the second width.2. The device of claim 1 , wherein the first width is equal to the second width.3. The device of claim 1 , wherein the first width is different from the second width.4. The device of further comprising:a second contact pad on the first substrate; ...

Fabrication method of semiconductor structure

A fabrication method of a semiconductor structure includes providing a chip having at least an electrode pad, forming a titanium layer on the electrode pad, forming a dielectric layer on the chip and a portion of the titanium layer, forming a copper layer on the dielectric layer and the titanium layer, forming a conductive pillar on the copper layer corresponding in position to the titanium layer, and removing a portion of the copper layer that is not covered by the conductive pillar. When the portion of the copper layer is removed by etching, undercutting of the titanium layer is avoided since the titanium layer is covered by the dielectric layer, thereby providing an improved support for the conductive pillar to increase product reliability.

Metal Routing Architecture for Integrated Circuits

A device includes a substrate, a metal pad over the substrate, and a metal trace electrically disconnected from the metal pad. The metal pad and the metal trace are level with each other. A passivation layer includes a portion overlapping an edge portion of the metal pad. A metal pillar is overlying the metal pad, and is electrically connected to the metal pad. The metal trace has a portion overlapped by the metal pillar.

Semiconductor device and a method of manufacturing the same

A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP.

Advanced Device Assembly Structures And Methods

A microelectronic assembly includes a first substrate having a surface and a first conductive element and a second substrate having a surface and a second conductive element. The assembly further includes an electrically conductive alloy mass joined to the first and second conductive elements. First and second materials of the alloy mass each have a melting point lower than a melting point of the alloy. A concentration of the first material varies in concentration from a relatively higher amount at a location disposed toward the first conductive element to a relatively lower amount toward the second conductive element, and a concentration of the second material varies in concentration from a relatively higher amount at a location disposed toward the second conductive element to a relatively lower amount toward the first conductive element. 1. A microelectronic assembly , comprising:a first substrate having a first surface and first conductive elements;a second substrate having a second surface and second conductive elements; anda plurality of electrically conductive masses, each mass joined to a respective pair of the first and second conductive elements,wherein each electrically conductive mass includes a first material, a second material, and a third material, the third material selected to increase the melting point of an alloy including the third material and at least one of the first material or the second material,wherein a concentration of the first material varies from a relatively higher amount at a location disposed toward the respective first conductive element to a relatively lower amount toward the respective second conductive element,wherein a concentration of the second material varies in concentration from a relatively higher amount at a location disposed toward the respective second conductive element to a relatively lower amount toward the respective first conductive element, andwherein the third material has a highest concentration at a location ...

SEMICONDUCTOR CONTACT STRUCTURE HAVING STRESS BUFFER LAYER FORMED BETWEEN UNDER BUMP METAL LAYER AND COPPER PILLAR

Semiconductor apparatus and method for manufacturing semiconductor apparatus are provided. Semiconductor apparatus includes a semiconductor substrate having metal pads, a first passivation layer, a second passivation layer, an under bump metal layer, a stress buffer layer, a copper pillar and a solder structure. First passivation layer is formed on the semiconductor substrate and covers a portion of each metal pad, the first passivation layer has first passivation layer openings to expose a first portion of each metal pad. Second passivation layer is formed on the first passivation layer, the second passivation layer has second passivation layer openings to expose a second portion of each metal pad. Under bump metal layer is formed on the second portion of each metal pad exposed by the second passivation layer opening. Stress buffer layer is formed on the under bump metal layer, and the copper pillar is disposed on the stress buffer layer. 1. A semiconductor apparatus , comprising:a semiconductor substrate having at least one metal pad;a first passivation layer formed on the semiconductor substrate and covering a portion of the at least one metal pad, the first passivation layer having at least one first passivation layer opening to expose a first portion of the at least one metal pad;a second passivation layer formed on the first passivation layer, the second passivation layer having at least one second passivation layer opening to expose a second portion of the at least one metal pad;an under bump metal layer at least formed on the second portion of the at least one metal pad exposed by the second passivation layer opening;a stress buffer layer formed on the under bump metal layer, wherein the material of the stress buffer layer comprises tin, tin-silver, tin alloy, indium or indium alloy; anda copper pillar disposed on the stress buffer layer.2. The semiconductor apparatus according to claim 1 , wherein the material of the under bump metal layer comprises ...

Semiconductor Device

Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion () formed on the upper surface of a semiconductor substrate (), a passivation layer () so formed on the upper surface of the semiconductor substrate () as to overlap a part of the electrode pad portion () and having a first opening portion () where the upper surface of the electrode pad portion () is exposed, a barrier metal layer () formed on the electrode pad portion (), and a solder bump () formed on the barrier metal layer (). The barrier metal layer () is formed such that an outer peripheral end () lies within the first opening portion () of the passivation layer () when viewed in plan. 110.-. (canceled)11. A semiconductor device comprising: an electrode pad portion on a face of a substrate;', 'a first protection layer including a first opening through which a top face of the electrode pad portion is exposed, the first protection layer disposed on the face of the substrate and overlapping part of the electrode pad portion;', 'a barrier metal layer on the electrode pad portion;', 'a second protection layer covering a region on the first protection layer and a region on the electrode par portion; and', 'a plurality of bump electrodes on the barrier metal layer;, 'a semiconductor chip includinga circuit board on which the semiconductor chip is mounted, the circuit board having, formed on a first face thereof facing the semiconductor chip, a connection pad portion connected to the bump electrodes;a plurality of electrode terminals formed on a second face of the circuit board facing away from the semiconductor chip, the electrode terminals being electrically connected to the connection pad portion; anda resin member filling a gap between the semiconductor chip and the circuit board,wherein the barrier metal layer has a circumferential end part thereof formed inward of the first opening in the first protection layer as seen in a plan ...

Manufacturing method of wafer level chip scale package structure

A manufacturing method of wafer level chip scale package structure is provided. Firstly, a wafer including a plurality of semiconductor devices is provided. An active surface of one of the semiconductor devices has an active an active region and an outer region. A first electrode and a second electrode are arranged on the active region, and the outer region has a cutting portion and a channel portion. Next, a patterned protecting layer having a plurality of openings is formed on the active surface to respectively expose the first and second electrodes and channel portion. Subsequently, a wafer back thinning process is performed and then a back electrode layer is deposited. Subsequently, the channel portion is etched to form a trench exposing the back electrode layer, and a conductive structure connected to the back electrode layer is formed through the trench. Thereafter, the wafer is cut along the cutting portion.

Semiconductor structure

The invention provides a semiconductor structure. The semiconductor structure includes a substrate. A first passivation layer is disposed on the substrate. A conductive pad is disposed on the first passivation layer. A second passivation layer is disposed on the first passivation layer. A passive device is disposed on the conductive pad, passing through the second passivation layer. An organic solderability preservative film covers the passive device.

Alignment Marks in Substrate Having Through-Substrate Via (TSV)

A device includes a substrate, and an alignment mark including a conductive through-substrate via (TSV) penetrating through the substrate.

Zinc Layer For A Semiconductor Die Pillar

A method for fabricating a copper pillar. The method includes forming a layer of titanium tungsten (TiW) over a semiconductor wafer, forming a layer of zinc (Zn) over the layer of TiW, and forming a copper pillar over the via. In addition, the method includes performing an anneal to diffuse the layer of Zn into the copper pillar. A semiconductor device that includes a layer of TiW coupled to a via of a semiconductor wafer and a copper pillar coupled to the layer of TiW. The copper pillar has interdiffused Zn within its bottom portion. Another method for fabricating a copper pillar includes forming a layer of TiW over a semiconductor wafer, forming a first patterned photoresist, forming a layer of Zn, and then removing the first patterned photoresist. The method further includes forming a second patterned photoresist and forming a copper pillar.

Pre-Molded Leadframes in Semiconductor Devices

In one instance, a semiconductor package includes a metal leadframe having a first plurality of openings extending partially into the leadframe from the first side and a second plurality of openings extending partially into the leadframe from the second side together forming a plurality of leads. A pre-mold compound is positioned in the second plurality of openings that at least partially supports the plurality of leads. The seminconductor package has a plurality of bumps extending from the landing sites to a semiconductor die and a molding compounding at least partially covering the plurality of bumps and the metal leadframe. Other packages and methods are disclosed.

Chip stack with electrically insulating walls

A chip stack is provided and includes two or more chips, a solder joint operably disposed between adjacent ones of the two or more chips, the solder joint occupying about 25-30% or more of an area of the chip stack and insulating walls disposed on at least one of the two or more chips to separate the solder joint from an adjacent solder joint.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor device includes: an integrated circuit having an electrode pad; a first insulating layer disposed on the integrated circuit; a redistribution layer including a plurality of wirings and disposed on the first insulating layer, at least one of the plurality of wirings being electrically coupled to the electrode pad; a second insulating layer having a opening on at least a portion of the plurality of wirings; a metal film disposed on the opening and on the second insulating layer, and electrically coupled to at least one of the plurality of wirings; and a solder bump the solder bump overhanging at least one of the plurality of wirings not electrically coupled to the metal film. 1. A semiconductor device , comprising:a substrate that includes a pad;a first wiring disposed in a redistribution layer, the first wiring being electrically connected to the pad;a second wiring that is separated from the first wiring, and that is disposed in same layer of the redistribution layer as the first wiring; anda first bump disposed over the first wiring and electrically connected to the first wiring, the first bump overlying the first wiring and the second wiring.2. The semiconductor device according to claim 1 , whereinthe first wiring extends first direction in a plan view, andthe second wiring extends second direction that is different from the first direction in a plan view.3. The semiconductor device according to claim 2 , whereinthe first direction is perpendicular to the second direction in a plan view.4. The semiconductor device according to claim 1 , further comprising:a first insulating film disposed between the substrate and the first wiring; anda second insulating film disposed between the first wiring and the first bump.5. The semiconductor device according to claim 4 , whereinthe first insulating film includes a first opening,a part of the first wiring is disposed in the hole and on the pad, anda part of the first insulating film covers a part of the pad6. ...

Semiconductor Devices, Methods of Manufacture Thereof, and Semiconductor Device Packages

Semiconductor devices, methods of manufacture thereof, and semiconductor device packages are disclosed. In one embodiment, a semiconductor device includes an insulating material layer having openings on a surface of a substrate. One or more insertion bumps are disposed over the insulating material layer. The semiconductor device includes signal bumps having portions that are not disposed over the insulating material layer.

FABRICATION METHOD OF PACKAGING SUBSTRATE

A packaging substrate includes a base body having at least a conductive pad on a surface thereof, a dielectric layer formed on the surface of the base body and having at least a first opening for exposing the conductive pad and at least a second opening formed at a periphery of the first opening, and a metal layer formed on the conductive pad and the dielectric layer and extending to a sidewall of the second opening, thereby effectively eliminating side-etching of the metal layer under a solder bump. 111-. (canceled)12. A fabrication method of a packaging substrate , comprising:providing a base body having at least a conductive pad on a surface thereof and a dielectric layer formed on the surface of the base body and at least a first opening formed in the dielectric layer for exposing the at least a conductive pad;forming at least a second opening in the dielectric layer around a periphery of the at least a first opening;forming a metal layer on the dielectric layer and the at least a conductive pad, wherein the metal layer extends to a sidewall of the at least a second opening; andforming at least a solder bump on the metal layer.13. The method of claim 12 , wherein forming the at least a solder bump on the metal layer comprises:forming a resist layer on the metal layer, wherein the resist layer has at least an opening corresponding in position to the at least a conductive pad and the opening has a wall located on the sidewall of the at least a second opening;forming the at least solder bump on the metal layer in the opening of the resist layer;removing the resist layer; andetching a portion of the metal layer uncovered by the at least a solder bump.14. The method of claim 13 , after removing the resist layer claim 13 , further comprising reflowing the at least a solder bump.15. The method of claim 12 , wherein the dielectric layer comprises a first sub-dielectric layer formed on the surface of the base body claim 12 , and a second sub-dielectric layer formed on ...

Alignment Marks in Substrate Having Through-Substrate Via (TSV)

A device includes a substrate, and an alignment mark including a conductive through-substrate via (TSV) penetrating through the substrate. 1. A device comprising:a substrate having a first surface and a second surface opposite the first surface;an interconnect adjacent the first surface of the substrate;a plurality of conductive features adjacent the second surface of the substrate;a plurality of first through-substrate vias (TSVs) extending from the first surface of the substrate to the second surface of the substrate, the first TSVs electrically connecting the conductive features to the interconnect; anda first alignment mark comprising a plurality of second TSVs extending from the first surface of the substrate to the second surface of the substrate, the second TSVs being electrically isolated from the conductive features and the interconnect, the second TSVs being disposed in an alignment mark region of the substrate, the alignment mark region being free from the first TSVs.2. The device of claim 1 , wherein the alignment mark region of the substrate has a length of between about 50 μm and about 400 μm claim 1 , and the alignment mark region of the substrate has a width of between about 50 μm and about 400 μm.3. The device of claim 1 , wherein a first subset of the second TSVs are disposed along a first axis claim 1 , and a second subset of the second TSVs are disposed along a second axis claim 1 , the first axis and the second axis being parallel to the second surface of the substrate.4. The device of claim 3 , wherein the first axis intersects the second axis at first point disposed at a center of the alignment mark region.5. The device of claim 3 , wherein the first axis intersects the second axis at a first point disposed offset from a center of the alignment mark region.6. The device of claim 1 , wherein the interconnect comprises a second alignment mark claim 1 , the second alignment mark being aligned to the first alignment mark.7. The device of claim 1 , ...

Semiconductor Device and Bump Formation Process

A semiconductor device includes a solder bump overlying and electrically connected to a pad region, and a metal cap layer formed on at least a portion of the solder bump. The metal cap layer has a melting temperature greater than the melting temperature of the solder bump.

Semiconductor device and method of manufacturing the same

A semiconductor chip includes a chip body and a plurality of solder-including electrodes provided on an element-formation surface of the chip body. A packaging substrate includes a substrate body, and a plurality of wirings and a solder resist layer that are provided on a front surface of the substrate body. The plurality of solder-including electrodes include a plurality of first electrodes and a plurality of second electrodes. The plurality of first electrodes supply a first electric potential, and the plurality of second electrodes supply a second electric potential different from the first electric potential. The plurality of first electrodes and the plurality of second electrodes are disposed alternately in both a row direction and a column direction, in a central part of the chip body. The plurality of wirings include a plurality of first wirings and a plurality of second wirings. The plurality of first wirings connect the plurality of first electrodes, and the plurality of second wirings connect the plurality of second electrodes.

Copper pillar bump having annular protrusion

A copper pillar bump for an electrode pad of a semiconductor chip includes a first copper layer, a first metal layer formed directly on the first copper layer, a second copper layer formed directly on the first metal layer, and a second metal layer formed directly on the second copper layer, wherein the first metal layer and the second metal layer are made of a metal having a different etching rate than copper, wherein an outer perimeter ring of the first metal layer protrudes beyond a lateral surface of the first copper layer, and wherein an outer perimeter ring of the second metal layer protrudes beyond a lateral surface of the second copper layer.

MULTIPLE PLATED VIA ARRAYS OF DIFFERENT WIRE HEIGHTS ON SAME SUBSTRATE

Apparatus(es) and method(s) relate generally to via arrays on a substrate. In one such apparatus, the substrate has a conductive layer. First plated conductors are in a first region extending from a surface of the conductive layer. Second plated conductors are in a second region extending from the surface of the conductive layer. The first plated conductors and the second plated conductors are external to the first substrate. The first region is disposed at least partially within the second region. The first plated conductors are of a first height. The second plated conductors are of a second height greater than the first height. A second substrate is coupled to first ends of the first plated conductors. The second substrate has at least one electronic component coupled thereto. A die is coupled to second ends of the second plated conductors. The die is located over the at least one electronic component. 1. An apparatus , comprising:a first substrate having a conductive layer;first plated conductors in a first region extending from a surface of the conductive layer;second plated conductors in a second region extending from the surface of the conductive layer;wherein the first plated conductors and the second plated conductors are external to the first substrate;wherein the first region is disposed at least partially within the second region;wherein the first plated conductors are of a first height;wherein the second plated conductors are of a second height greater than the first height;a second substrate coupled to first ends of the first plated conductors;the second substrate having at least one electronic component coupled thereto;a die coupled to second ends of the second plated conductors; andthe die located over the at least one electronic component.2. The apparatus according to claim 1 , wherein the at least one electronic component includes a discrete passive component.3. The apparatus according to claim 2 , wherein the second substrate includes a ...

SEMICONDUCTOR PACKAGE

A semiconductor package includes a substrate, through-electrodes penetrating the substrate, first bumps spaced apart from each other in a first direction parallel to a top surface of the substrate and electrically connected to the through-electrodes, respectively, and at least one second bump disposed between the first bumps and electrically insulated from the through-electrodes. The first bumps and the at least one second bump constitute one row in the first direction. A level of a bottom surface of the at least one second bump from the top surface of the substrate is a substantially same as levels of bottom surfaces of the first bumps from the top surface of the substrate. 120-. (canceled)21. A semiconductor package , comprising:a substrate;through-electrodes penetrating the substrate;first bumps spaced apart from each other in a first direction parallel to a top surface of the substrate, the first bumps being electrically connected to the through-electrodes, respectively;at least one second bump disposed between the first bumps, the at least one second bump being electrically insulated from the through-electrodes; andan underfill covering the substrate, the first bumps, and the at least one second bump,wherein the first bumps and the at least one second bump constitute one row in the first direction, andwherein at least one second bump is disposed at a higher level from the substrate than the first bumps.22. The semiconductor package as claimed in claim 21 , further comprising:an insulating pattern disposed between the substrate and the at least one second bump.23. The semiconductor package as claimed in claim 22 , wherein the insulating pattern has through-holes overlapping top surfaces of the through-electrodes claim 22 , respectively claim 22 , andwherein the first bumps are provided in the through-holes so as to be electrically connected to the through-electrodes, respectively.24. The semiconductor package as claimed in claim 21 , further comprising:a pad ...

Semiconductor device

A semiconductor device that includes a bipolar transistor, wherein a third opening, through which a pillar bump and a second wiring line, which is electrically connected to an emitter layer, contact each other, is shifted in a longitudinal direction of the emitter layer away from a position at which the third opening would be directly above the emitter layer. The third opening is arranged, with respect to the emitter layer, such that an end portion of the emitter layer in the longitudinal direction of the emitter layer and the edge of the opening of the third opening are substantially aligned with each other.

CHIP PACKAGE

A chip package may include a first polymer layer and a first semiconductor chip in the first polymer layer. The first semiconductor chip may include a first semiconductor device and a first semiconductor substrate supporting the first semiconductor device. The first semiconductor chip may also have a first contact pad coupled to the first semiconductor device. The first semiconductor chip may further include a first conductive interconnect on the first contact pad. The chip package may also include a second polymer layer on the first polymer layer and across an edge of the first semiconductor chip. The chip package may further include a first conductive layer in the second polymer layer and directly on a surface of the first conductive interconnect, and across the edge of the first semiconductor chip. 1. A chip package comprising:a first polymer layer; a first semiconductor device,', 'a first semiconductor substrate to support the first semiconductor device,', 'a first contact pad coupled to the first semiconductor device, and', 'a first conductive interconnect on the first contact pad;, 'a first semiconductor chip in the first polymer layer, in which the first semiconductor chip comprisesa second polymer layer on the first polymer layer and extending across an edge of the first semiconductor chip; anda first conductive layer in the second polymer layer and directly on a surface of the first conductive interconnect, and extending across the edge of the first semiconductor chip.2. The chip package of claim 1 , in which the semiconductor substrate comprises silicon.3. The chip package of claim 1 , in which the first polymer layer comprises an epoxy molding compound.4. The chip package of claim 1 , in which the first polymer layer has a thickness between 250 and 1000 micrometers.5. The chip package of claim 1 , in which the first conductive layer comprises a redistribution layer having a thickness between 1 and 20 micrometers.6. The chip package of claim 1 , in which ...

Structure and Method of Forming a Joint Assembly

A method of manufacturing a semiconductor device structure includes forming a bond or joint between a first device and a second device. The first device comprises an integrated passive device (IPD) and a first contact pad disposed over the IPD. The second device comprises a second contact pad. The first contact pad has a first surface with first lateral extents. The second contact pad has a second surface with second lateral extents. The width of the second lateral extents is less than the width of the first lateral extents. The joint structure includes the first contact pad, the second contact pad, and a solder layer interposed therebetween. The solder layer has tapered sidewalls extending in a direction away from the first surface of the first contact pad to the second surface of the second contact pad. At least one of the first surface or the second surface is substantially planar. 1. A device comprising:a first semiconductor device comprising a first contact pad having a first surface contacting a metal feature, the first contact pad having a second surface opposite the first surface, the second surface being planar, wherein a ratio of a first width of the first surface to a second width of the second surface is 2:5;a solder layer bonded to the first contact pad; anda second semiconductor device comprising a second contact pad, the second contact pad having a third surface bonded to the solder layer, the second contact pad having a fourth surface opposite the third surface, the third surface being planar, wherein a ratio of a third width of the third surface to a fourth width of the fourth surface is 5:2, wherein the solder layer has tapered sidewalls continuously diminishing from the second width at a fifth surface adjoining the first contact pad to the third width at a sixth surface adjoining the second contact pad.2. The device of claim 1 , wherein the first semiconductor device further comprises an integrated passive device.3. The device of claim 2 , wherein ...

Conductive External Connector Structure and Method of Forming

External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure.

SEMICONDUCTOR PACKAGE

A semiconductor package includes a substrate, through-electrodes penetrating the substrate, first bumps spaced apart from each other in a first direction parallel to a top surface of the substrate and electrically connected to the through-electrodes, respectively, and at least one second bump disposed between the first bumps and electrically insulated from the through-electrodes. The first bumps and the at least one second bump constitute one row in the first direction. A level of a bottom surface of the at least one second bump from the top surface of the substrate is a substantially same as levels of bottom surfaces of the first bumps from the top surface of the substrate. 120.-. (canceled)21. A semiconductor package comprising:a substrate;a first chip on the substrate, the first chip has first through-electrodes penetrating the first chip;a second chip on the first chip;bumps between the first chip and the second chip; andan underfill filling a space between the first chip and the second chip, first bumps spaced apart from each other in a first direction parallel to a top surface of the first chip, the first bumps being electrically connected to the through-electrodes, respectively, and', 'at least one second bump between the first bumps, the at least one second bump being electrically insulated from the through-electrodes,, 'wherein the bumps includewherein the first bumps and the at least one second bump constitute one row in the first direction,wherein a level of a bottom surface of the at least one second bump from the top surface of the substrate is a substantially same level as levels of bottom surfaces of the first bumps from the top surface of the substrate, andwherein the underfill covers a space between the first bumps and covers a space between the first bumps and the at least one second bump.22. The semiconductor package as claimed in claim 21 , wherein:the first bumps have a first thickness in a second direction perpendicular to the top surface of ...

Reducing solder pad topology differences by planarization

A technique is disclosed for causing the top surfaces of solder bumps on a chip to be in the same plane to ensure a more reliable bond between the chip and a substrate. The chip is provided with solder pads that may have different heights. A dielectric layer is formed between the solder pads. A relatively thick metal layer is plated over the solder pads. The metal layer is planarized to cause the top surfaces of the metal layer portions over the solder pads to be in the same plane and above the dielectric layer. A substantially uniformly thin layer of solder is deposited over the planarized metal layer portions so that the top surfaces of the solder bumps are substantially in the same plane. The chip is then positioned over a substrate having corresponding metal pads, and the solder is reflowed or ultrasonically bonded to the substrate pads.

SEMICONDUCTOR STRUCTURE

The invention provides a semiconductor structure. The semiconductor structure includes a substrate. A first passivation layer is disposed on the substrate. A conductive pad is disposed on the first passivation layer. A second passivation layer is disposed on the first passivation layer. A conductive structure is disposed on the conductive pad, and a passive device is also disposed on the conductive pad, wherein the passive device has a first portion located above the second passivation layer and a second portion passing through the second passivation layer. A solderability preservative film covers the first portion of the passive device, and an under bump metallurgy (UBM) layer covers the second portion of the passive device and a portion of the conductive structure. 1. A semiconductor structure , comprising:a substrate;a first passivation layer disposed on the substrate;a conductive pad disposed on the first passivation layer;a second passivation layer disposed on the first passivation layer;a conductive structure disposed on the conductive pad;a passive device disposed on the conductive pad, the passive device having a first portion located above the second passivation layer and a second portion passing through the second passivation layer;a solderability preservative film covering the first portion of the passive device; andan under bump metallurgy (UBM) layer covering the second portion of the passive device and a portion of the conductive structure, wherein the UBM layer and the solderability preservative film entirely wrap the passive device, wherein the under bump metallurgy layer extends over a top surface of the second passivation layer such that the solderability preservative film does not contact the second passivation layer.2. The semiconductor structure as claimed in claim 1 , wherein the passive device comprises a balun device claim 1 , an inductor claim 1 , a transformer claim 1 , a routing or an antenna.3. The semiconductor device as claimed in claim ...

Pre-Molded Leadframes in Semiconductor Devices

In one instance, a semiconductor package includes a metal leadframe having a first plurality of openings extending partially into the leadframe from the first side and a second plurality of openings extending partially into the leadframe from the second side together forming a plurality of leads. A pre-mold compound is positioned in the second plurality of openings that at least partially supports the plurality of leads. The semiconductor package has a plurality of bumps extending from the landing sites to a semiconductor die and a molding compounding at least partially covering the plurality of bumps and the metal leadframe. Other packages and methods are disclosed. 1. A semiconductor package comprising:a semiconductor die including a plurality of bumps electrically connected to the semiconductor die;a portion of a leadframe attached to the plurality of bumps, wherein the leadframe includes a first side and a second side opposing the first side, a first plurality of openings extending into the leadframe from the first side, and a second plurality of openings extending into the leadframe from the second side, the first plurality of openings including a first lateral width and the second plurality of openings including a second lateral width, wherein the second lateral width is greater than the first lateral width;a first molding compound covering portions of the semiconductor die, the plurality of bumps and filling the first plurality of openings; anda second molding compound filling the second plurality of openings; wherein the first plurality of openings is nonlinear from a top view of the semiconductor package.2. The semiconductor package of claim 1 , wherein the second plurality of openings is linear from a bottom view of the semiconductor package.3. The semiconductor package of claim 1 , wherein a width of some of the plurality of bumps is different than the others of the plurality of bumps.4. The semiconductor package of claim 1 , wherein each of the plurality ...

Wafer to Wafer Bonding Process and Structures

Bonded structures and method of forming the same are provided. A conductive layer is formed on a first surface of a bonded structure, the bonded structure including a first substrate bonded to a second substrate, the first surface of the bonded structure being an exposed surface of the first substrate. A patterned mask having first openings and second openings is formed on the conductive layer, the first openings and the second openings exposing portions of the conductive layer. First portions of first bonding connectors are formed in the first openings and first portions of second bonding connectors are formed in the second openings. The conductive layer is patterned to form second portions of the first bonding connectors and second portions of the second bonding connectors. The bonded structure is bonded to a third substrate using the first bonding connectors and the second bonding connectors.

PACKAGING ASSEMBLY AND METHOD OF MAKING THE SAME

A packaging assembly includes a semiconductor device. The semiconductor device includes a conductive pad having a first width, and an under-bump metallization (UBM) layer on the conductive pad, wherein the UBM layer has a second width greater than the first width. The semiconductor device further includes a conductive pillar on the UBM layer, and a cap layer over the conductive pillar, wherein the cap layer exposes sidewalls of the UBM layer. The packaging assembly further includes a substrate. The substrate includes a conductive region, and a mask layer overlying the substrate and exposing a portion of the conductive region. The packaging assembly further includes a joint solder structure between the conductive pillar and the conductive region. 1. A packaging assembly , comprising: a conductive pad having a first width,', 'an under-bump metallization (UBM) layer on the conductive pad, wherein the UBM layer has a second width greater than the first width,', 'a conductive pillar on the UBM layer, and', 'a cap layer over the conductive pillar, wherein the cap layer exposes sidewalls of the UBM layer;, 'a semiconductor device comprising a conductive region, and', 'a mask layer overlying the substrate and exposing a portion of the conductive region; and, 'a substrate comprisinga joint solder structure between the conductive pillar and the conductive region.2. The packaging assembly of claim 1 , wherein the mask layer has a mask opening exposing a portion of the conductive region claim 1 , and the width of the mask opening is smaller than and the second width.3. The packaging assembly of claim 2 , wherein a ratio between the width of the mask opening and the second width ranges from about 0.7 and about 0.8.4. The packaging assembly of claim 1 , wherein the conductive pillar comprises a copper pillar claim 1 , and the conductive region is a copper trace.5. The packaging assembly of claim 1 , wherein the mask layer is a solder resist layer.6. A packaging assembly claim 1 , ...

Contact structures with porous networks for solder connections, and methods of fabricating same

A contact pad includes a solder-wettable porous network ( 310 ) which wicks the molten solder ( 130 ) and thus restricts the lateral spread of the solder, thus preventing solder bridging between adjacent contact pads.

Wafer Level Molded PPGA (Pad Post Grid Array) for Low Cost Package

A method to fabricate a land grid array wafer level chip scale package is described. A silicon die is provided. A dielectric layer is deposited on the silicon die. An opening is etched through the dielectric layer to a metal pad on the silicon die. At least one redistribution layer is formed over the dielectric layer and contacting the metal pad. At least one copper post is formed on the at least one redistribution layer and forms a land grid array. The wafer is sawed partially through on scribe lines to form cuts exposing sides of the silicon die. Thereafter, a molding compound is applied over the at least one redistribution layer and in the cuts wherein the molding compound encapsulates top and side surfaces of the silicon die.

Passivation layer for integrated circuit structure and forming the same

A method includes forming metal lines over an interconnect structure that is formed above transistors; depositing a liner layer over the metal lines using a first high density plasma chemical vapor deposition (HDPCVD) process with a zero RF bias power depositing a first passivation layer over the liner layer using a second HDPCVD process with a non-zero RF bias power; and depositing a second passivation layer in contact with a top surface of the first passivation layer using a third HDPCVD process with a non-zero RF bias power.

Semiconductor product with interlocking metal-to-metal bonds and method for manufacturing thereof

A structure and method for performing metal-to-metal bonding in an electrical device. For example and without limitation, various aspects of this disclosure provide a structure and method that utilize an interlocking structure configured to enhance metal-to-metal bonding.

Mechanisms for Forming Post-Passivation Interconnect Structure

Mechanisms for forming a semiconductor device are provided. The semiconductor device includes a contact pad over a substrate. The semiconductor device also includes a passivation layer over the substrate and a first portion of the contact pad, and a second portion of the contact pad is exposed through an opening. The semiconductor device further includes a post-passivation interconnect layer over the passivation layer and coupled to the second portion of the contact pad. In addition, the semiconductor device includes a bump over the post-passivation interconnect layer and outside of the opening. The semiconductor device also includes a diffusion barrier layer physically insulating the bump from the post-passivation interconnect layer while electrically connecting the bump to the post-passivation interconnect layer. 1. A semiconductor device , comprising:an integrated circuit;an insulating layer overlying the integrated circuit;a post-passivation interconnect layer over the insulating layer; and a bump comprising a first material, and', 'a diffusion barrier region enclosing the bump and comprising the first material doped with a dopant., 'a connector electrically connected to the post-passivation layer, the connector including2. The semiconductor device as claimed in claim 1 , wherein the dopant in the diffusion barrier region includes nickel.3. The semiconductor device as claimed in claim 1 , wherein the first material includes a solder material or copper.4. The semiconductor device as claimed in claim 1 , wherein a portion of the diffusion barrier region is between a bottom of the bump and the post-passivation interconnect layer.5. The semiconductor device as claimed in claim 4 , further comprising a diffusion barrier layer directly below a diffusion barrier region of the bump and directly above the post-passivation interconnect layer.6. The semiconductor device as claimed in claim 1 , wherein the bump comprises a solder bump.7. The semiconductor device as claimed ...

Semiconductor device and method of manufacturing the same

A semiconductor device includes a wiring substrate including a first electrode in which a cross-sectional shape is an inverted trapezoidal shape, a semiconductor chip including a second electrode in which a cross-sectional shape is an inverted trapezoidal shape, a metal bonding material bonding a tip end of the first electrode and a tip end of the second electrode which face each other, and an underfill resin filled between the wiring substrate and the semiconductor chip, the underfill resin covering a side face of each of the first electrode and the second electrode and a side face of the metal bonding material.

Semiconductor device having a bump structure and method for manufacturing the same

A method for manufacturing a semiconductor device includes an extra etching process. A bump or a UBM layer is etched additionally in the extra etching process after forming the semiconductor device such that the semiconductor device can conform to the standard of performance and appearance.

SEMICONDUCTOR DEVICE

A semiconductor device that includes a bipolar transistor, wherein a third opening, through which a pillar bump and a second wiring line, which is electrically connected to an emitter layer, contact each other, is shifted in a longitudinal direction of the emitter layer away from a position at which the third opening would be directly above the emitter layer. The third opening is arranged, with respect to the emitter layer, such that an end portion of the emitter layer in the longitudinal direction of the emitter layer and the edge of the opening of the third opening are substantially aligned with each other. 1. A semiconductor device comprising: a collector layer,', 'a base layer on the collector layer,', 'an emitter layer on the base layer,', 'an emitter wiring line electrically connected to the emitter layer,', 'an insulating film covering the emitter wiring line and having an opening through which the emitter wiring line is exposed, the opening being arranged outside the emitter layer in plan view or being arranged so as to cover a portion of the emitter layer in plan view, and', 'a bump formed on the insulating film so as to bury the opening and electrically connected to the emitter layer via the emitter wiring line., 'a bipolar transistor including2. The semiconductor device according to claim 1 ,wherein a center of the opening is positioned, in plan view, offset from a center of the emitter layer.3. The semiconductor device according to claim 2 ,wherein a center of the opening is positioned, in plan view, offset in a longitudinal direction in which the emitter layer extends.4. The semiconductor device according to claim 1 ,wherein an entirety of the emitter layer or another portion of the emitter layer is arranged under the bump in plan view.5. The semiconductor device according to claim 2 ,wherein an entirety of the emitter layer or another portion of the emitter layer is arranged under the bump in plan view.6. A semiconductor device comprising: a collector ...

Semiconductor device having under-bump metallization (ubm) structure and method of forming the same

A semiconductor device comprises a semiconductor substrate, an under-bump metallization (UBM) structure overlying the semiconductor substrate, and a solder bump overlying and electrically connected to the UBM structure. The UBM structure comprises a first metallization layer comprising a first metal, a second metallization layer comprising a second metal different from the first metal, and a first intermetallic compound (IMC) layer between the first metallization layer and the second metallization layer, the first IMC layer comprising the first metal and the second metal.

VISIBILITY EVENT NAVIGATION METHOD AND SYSTEM

A method of visibility event navigation includes receiving, via processing circuitry of a client device, a first visibility event packet from a server, the first visibility event packet including information representing 3D surface elements of an environmental model that are occluded from a first viewcell and not occluded from a second viewcell, the first and second viewcells representing spatial regions of a specified navigational route within a real environment modeled by the environmental model. The method also includes acquiring, surface information representing the visible surfaces of the real environment at a sensor and determining, a position in the real environment by matching the surface information to the visibility event packet information. The method further includes transmitting, the position from the client device to the server and receiving a second visibility event packet from the server if the at least one position is within the specified navigational route. 1receiving, via processing circuitry of a client device, at least one visibility event packet of the one or more visibility event packets from the server;detecting, via the circuitry, surface information representing one or more visible surfaces of the real environment at a sensor in communication with the client device;calculating, via the circuitry, at least one position of the client device in the real environment by matching the surface information to the visibility event packet information corresponding to a first visibility event packet of the one or more visibility event packets;transmitting, via the circuitry, the at least one position from the client device to the server; andreceiving, via the circuitry, at least one second visibility event packet of the one or more visibility event packets when the at least one position is within the navigational route at the client device from the server.. A method of visibility event navigation, including one or more visibility event packets located ...

Semiconductor Device And Bump Formation Process

A semiconductor device includes a solder bump overlying and electrically connected to a pad region, and a metal cap layer formed on at least a portion of the solder bump. The metal cap layer has a melting temperature greater than the melting temperature of the solder bump. 1. A method of forming a packaging assembly , the method comprising:forming a solder material layer over a pad region of a first substrate;reshaping the solder material layer;forming a metal cap layer over the solder material layer, the metal cap layer being formed of a material different from the solder material layer; andbonding the solder material layer to a second substrate.2. The method of claim 1 , wherein forming the solder material layer comprises:forming a patterned mask layer over the first substrate, an opening in the patterned mask layer exposing the pad region;forming a solder material in the opening of the patterned mask layer; andremoving the patterned mask layer.3. The method of claim 2 , wherein forming the solder material layer further comprises:forming an under-bump-metallurgy (UBM) layer over the first substrate and over the pad region before forming the patterned mask layer; andremoving portions of the UBM layer uncovered by the solder material layer after removing the patterned mask layer.4. The method of claim 1 , wherein reshaping the solder material layer comprises performing a thermal reflow process.5. The method of claim 4 , wherein the solder material layer has straight sidewalls before the reshaping claim 4 , and wherein the solder material layer has curved sidewalls after the reshaping.6. The method of claim 1 , wherein forming the metal cap layer is performed before reshaping the solder material layer.7. The method of claim 1 , wherein reshaping the solder material layer changes a profile of the metal cap layer.8. The method of claim 1 , wherein the metal cap layer has a higher melting point than the solder material layer.9. The method of claim 1 , wherein the metal ...

Chip and manufacturing method thereof

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has an active surface. The semiconductor device includes at least a connecting element and at least a bump. The connecting element is disposed on the activate surface and has a minimum dimension smaller than 100 microns. The bump is disposed on the connecting element and is electrically connected to the active surface by the connecting element. The bump includes a pillar part disposed on the connecting element and a top part disposed at the top of the pillar part. The pillar part has a first dimension and a second dimension both parallel to the active surface. The first dimension is longer than 1.2 times the second dimension. The top part is composed of solder and will melt under the determined temperature. The pillar part will not melt under a determined temperature.

MICRO-LED MODULE AND METHOD FOR FABRICATING THE SAME

A method for fabricating a micro-LED module is disclosed. The method includes: preparing a micro-LED including a plurality of electrode pads and a plurality of LED cells; preparing a submount substrate including a plurality of electrodes corresponding to the plurality of electrode pads; and flip-bonding the micro-LED to the submount substrate through a plurality of solders located between the plurality of electrode pads and the plurality of electrodes. The flip-bonding includes heating the plurality of solders by a laser. 1. A method for flip-bonding a micro-LED to a submount substrate , comprising:forming a plurality of LED cells on an LED substrate to prepare the micro-LED;preparing the submount substrate having a coefficient of thermal expansion different from that of the micro-LED; andflip-bonding the micro-LED to the submount substrate through solders located therebetween,wherein the submount substrate and the micro-LED are controlled to different temperatures corresponding to different heating-cooling curves during the flip-bonding such that a difference in strain caused by the different coefficients of thermal expansion of the LED substrate and the submount substrate is suppressed.2. The method according to claim 1 , wherein the submount substrate and the micro-LED are controlled to different temperatures in a heating zone claim 1 , a holding zone claim 1 , and a cooling zone during the flip-bonding.3. The method according to claim 2 , wherein claim 2 , in the heating zone claim 2 , the LED substrate is heated from room temperature to a first holding temperature along a first heating slope and the submount substrate is heated from room temperature to a second holding temperature higher than the first holding temperature along a second heating slope steeper than the first heating slope.4. The method according to claim 2 , wherein claim 2 , in the holding zone claim 2 , the LED substrate is maintained at the first holding temperature for an indicated time and ...

FABRICATION METHOD OF SEMICONDUCTOR PACKAGE WITH STACKED SEMICONDUCTOR CHIPS

A semiconductor package includes a build-up structure; a semiconductor disposed on the build-up structure in a flip-chip manner and having a plurality of bumps penetrating therethrough; an electronic element disposed on the semiconductor chip; and an encapsulant formed on the build-up structure and encapsulating the semiconductor chip and the electronic element, thereby improving the product yield and the overall heat dissipating efficiency. 126-. (canceled)27. A fabrication method of a semiconductor package , comprising the steps of:providing a carrier having opposite first and second surfaces, wherein a build-up structure is formed on the first surface of the carrier and has a plurality of conductive pads exposed from the a top surface thereof;disposing a first semiconductor chip on the build-up structure in a flip-chip manner, wherein the first semiconductor chip has a first active surface and a first non-active surface opposite to the first active surface, and the first active surface has a plurality of first electrode pads electrically connected to the conductive pads, respectively;thinning the first semiconductor chip from the first non-active surface thereof;forming a plurality of first through holes in the first semiconductor chip via the first non-active surface thereof;forming in the first through holes a plurality of first bumps electrically connected to the first electrode pads;disposing an electronic element on the first semiconductor chip for electrically connecting the electronic element to the first bumps; andforming on the build-up structure an encapsulant that encapsulates the first semiconductor chip and the electronic element.28. The fabrication method of claim 27 , wherein the first electrode pads are exposed through the first through holes claim 27 , respectively.29. The fabrication method of claim 27 , wherein a circuit layer that is electrically connected to the first electrode pads is exposed through the first through holes.30. The ...

Semiconductor device and method of manufacturing semiconductor device

A semiconductor device including a semiconductor element; a pad electrode that is formed on the semiconductor element; an alignment mark that is formed on the semiconductor element; a connection electrode that is formed on the pad electrode; and an underfill resin that is formed to cover the connection electrode. The height of the alignment mark from the semiconductor element is greater than that of the connection electrode.

SEMICONDUCTOR APPARATUS AND METHOD FOR MANUFACTURING SEMICONDUCTOR APPARATUS

Semiconductor apparatus and method for manufacturing semiconductor apparatus are provided. Semiconductor apparatus includes a semiconductor substrate having metal pads, a first passivation layer, a second passivation layer, an under bump metal layer, a stress buffer layer, a copper pillar and a solder structure. First passivation layer is formed on the semiconductor substrate and covers a portion of each metal pad, the first passivation layer has first passivation layer openings to expose a first portion of each metal pad. Second passivation layer is formed on the first passivation layer, the second passivation layer has second passivation layer openings to expose a second portion of each metal pad. Under bump metal layer is formed on the second portion of each metal pad exposed by the second passivation layer opening. Stress buffer layer is formed on the under bump metal layer, and the copper pillar is disposed on the stress buffer layer. 1. A semiconductor apparatus , comprising:a semiconductor substrate having at least one metal pad;a first passivation layer formed on the semiconductor substrate and covering a portion of the at least one metal pad, the first passivation layer having at least one first passivation layer opening to expose a first portion of the at least one metal pad;a second passivation layer formed on the first passivation layer, the second passivation layer having at least one second passivation layer opening to expose a second portion of the at least one metal pad;an under bump metal layer at least formed on the second portion of the at least one metal pad exposed by the second passivation layer opening;a stress buffer layer formed on the under bump metal layer; anda copper pillar disposed on the stress buffer layer.2. The semiconductor apparatus according to claim 1 , wherein the material of the stress buffer layer comprises tin claim 1 , tin-silver claim 1 , tin alloy claim 1 , indium or indium alloy claim 1 , and the material of the under ...

FABRICATION METHOD OF SEMICONDUCTOR STRUCTURE

The present invention provides a semiconductor structure and a method of fabricating the same. The method includes: providing a chip having conductive pads, forming a metal layer on the conductive pads, forming a passivation layer on a portion of the metal layer, and forming conductive pillars on the metal layer. Since the metal layer is protected by the passivation layer, the undercut problem is solved, the supporting strength of the conductive pillars is increased, and the product reliability is improved. 113-. (canceled)14. A method of fabricating a semiconductor structure , comprising:providing a chip having a plurality of conductive pads and a protective layer that has a plurality of protective-layer openings, with a portion of each of the conductive pads exposed from each of the protective-layer openings;forming a metal layer on the protective layer, and electrically connecting the metal layer to the conductive pads, with a portion of the protective layer exposed from the metal layer;forming on a portion of the metal layer and on the protective layer a first passivation layer that covers a lateral side of the metal layer, and forming a plurality of first openings in the first passivation layer, with a portion of the metal layer exposed from the first openings; andforming a plurality of conductive pillars on the exposed portion of the metal layer in the first openings.15. The method of claim 14 , wherein the first openings are positioned above the protective-layer opening claim 14 , and each of the first openings has a width greater than or equal to a width of each of the protective-layer openings.16. The method of claim 14 , wherein the metal layer is formed by:forming a metal material on the conductive pads and the protective layer;forming a resist layer on the metal material, with a portion of the metal material exposed therefrom;removing the exposed portion of the metal material, so as for a remaining portion of the metal material to form the metal layer; ...

Dummy Flip Chip Bumps for Reducing Stress

A device includes a metal pad over a substrate. A passivation layer includes a portion over the metal pad. A post-passivation interconnect (PPI) is electrically coupled to the metal pad, wherein the PPI comprises a portion over the metal pad and the passivation layer. A polymer layer is over the PPI. A dummy bump is over the polymer layer, wherein the dummy bump is electrically insulated from conductive features underlying the polymer layer. 1. A method comprising: bonding a first solder region to be between and joining to both of an electrical connector of the device die and a metal trace of the package component, wherein the first solder region contacts a bottom surface and sidewalls of the metal trace, and the metal trace is in a surface dielectric layer of the package component; and', 'contacting a second solder region to a bottom surface of the surface dielectric layer or a bond pad of the package component, wherein the bond pad is in the surface dielectric layer, and wherein the second solder region is joined to a dummy bump of the device die., 'bonding a package component to a device die, wherein the bonding comprises2. The method of further comprising forming the device die comprising:forming an additional dielectric layer; andforming the dummy bump over the additional dielectric layer, with an entirety of a bottom surface of the dummy bump contacting a top surface of the additional dielectric layer.3. The method of claim 2 , wherein the dummy bump is electrically disconnected from all conductive components that are lower than the top surface of the additional dielectric layer.4. The method of claim 1 , wherein after the bonding claim 1 , the dummy bump is electrically floating.5. The method of claim 1 , wherein the first solder region extends into an opening in the surface dielectric layer of the package component.6. The method of further comprising claim 5 , after the package component is bonded to the device die claim 5 , dispensing an underfill between ...

VISIBILITY EVENT NAVIGATION METHOD AND SYSTEM

A method of visibility event navigation includes receiving, via processing circuitry of a client device, a first visibility event packet from a server, the first visibility event packet including information representing 3D surface elements of an environmental model that are occluded from a first viewcell and not occluded from a second viewcell, the first and second viewcells representing spatial regions of a specified navigational route within a real environment modeled by the environmental model. The method also includes acquiring, surface information representing the visible surfaces of the real environment at a sensor and determining, a position in the real environment by matching the surface information to the visibility event packet information. The method further includes transmitting, the position from the client device to the server and receiving a second visibility event packet from the server if the at least one position is within the specified navigational route. 1receiving, via processing circuitry of a client device, at least one visibility event packet of the one or more visibility event packets from the server;detecting, via the circuitry, surface information representing one or more visible surfaces of the real environment at a sensor in communication with the client device;calculating, via the circuitry, at least one position of the client device in the real environment by matching the surface information to the visibility event packet information corresponding to a first visibility event packet of the one or more visibility event packets;transmitting, via the circuitry, the at least one position from the client device to the server; andreceiving, via the circuitry, at least one second visibility event packet of the one or more visibility event packets when the at least one position is within the navigational route at the client device from the server.. A method of visibility event navigation, including one or more visibility event packets located ...

EXPANDED HEAD PILLAR FOR BUMP BONDS

A microelectronic device has a bump bond structure including an electrically conductive pillar with an expanded head, and solder on the expanded head. The electrically conductive pillar includes a column extending from an I/O pad to the expanded head. The expanded head extends laterally past the column on at least one side of the electrically conductive pillar. In one aspect, the expanded head may have a rounded side profile with a radius approximately equal to a thickness of the expanded head, and a flat top surface. In another aspect, the expanded head may extend past the column by different lateral distances in different lateral directions. In a further aspect, the expanded head may have two connection areas for making electrical connections to two separate nodes. Methods for forming the microelectronic device are disclosed. 1. A device comprising:an I/O pad of a substrate;a column on the I/O pad; anda head on the column and extending on all lateral sides of the column, a portion of a surface of the head, aligned with the column in a cross-sectional view of the device, is substantially parallel to a surface of the substrate.2. The device of claim 1 , wherein a plane along the portion of a surface of the head is parallel to a plane along a surface of the head adjacent to the column.3. The device of claim 1 , wherein the head has a rounded side profile with a radius that is approximately equal to the thickness of the head.4. The device of further comprising solder on the head.5. The device of further comprising a barrier layer between the surface of the head and the solder.6. The device of claim 5 , wherein the barrier layer impacts formation of intermetallic compounds between a material of the head and solder.7. The device of claim 1 , wherein the head extends past the column on all lateral sides of the column by a lateral distance that is approximately equal to a vertical thickness of the head.8. The device of further comprising a seed layer between the column ...

LARGE SCALE INTEGRATED CIRCUIT CHIP AND LARGE SCALE INTEGRATED CIRCUIT WAFER

A large scale integrated circuit chip includes a semiconductor circuit having a multilayered wiring structure, a metal guard ring surrounding the semiconductor circuit, and a plurality of external connection terminals, on a semiconductor circuit. The plurality of external connection terminals connect to an uppermost-layer wiring of the multilayered wiring structure and are exposed on a surface of the large scale integrated circuit chip. A predetermined external connection terminal conducts to a predetermined wiring through a conductive via within the guard ring and conducts to a conductive piece through another conductive via outside the guard ring. One side of the external connection terminal extending over the guard ring connects to the conductive piece, and the other side of the external connection terminal connects to the uppermost-layer wiring within the guard ring. Thus, a cutout part is not necessary in the guard ring. 1. A large scale integrated circuit chip comprising:a semiconductor substrate;a semiconductor circuit formed above the semiconductor substrate and having a vertically multilayered wiring structure;a metal guard ring formed above the semiconductor substrate and surrounding the semiconductor circuit; anda plurality of external connection terminals connecting to a predetermined wiring of the multilayered wiring structure of the semiconductor circuit and exposed on a surface of the large scale integrated circuit chip,wherein a predetermined external connection terminal among the plurality of external connection terminals conducts to the predetermined wiring through a conductive via within the guard ring and conducts to a conductive piece through another conductive via outside the guard ring, andwherein the conductive piece is a piece of a test lead-out wiring and is a wiring having a cut surface that is exposed by dicing.2. The large scale integrated circuit chip according to claim 1 , wherein the external connection terminals are made of a noble ...

VISIBILITY EVENT NAVIGATION METHOD AND SYSTEM

A method of visibility event navigation includes receiving, via processing circuitry of a client device, a first visibility event packet from a server, the first visibility event packet including information representing 3D surface elements of an environmental model that are occluded from a first viewcell and not occluded from a second viewcell, the first and second viewcells representing spatial regions of a specified navigational route within a real environment modeled by the environmental model. The method also includes acquiring, surface information representing the visible surfaces of the real environment at a sensor and determining, a position in the real environment by matching the surface information to the visibility event packet information. The method further includes transmitting, the position from the client device to the server and receiving a second visibility event packet from the server if the at least one position is within the specified navigational route. 1receiving, via processing circuitry of a client device, at least one visibility event packet of the one or more visibility event packets from the server;detecting, via the circuitry, surface information representing one or more visible surfaces of the real environment at a sensor in communication with the client device;calculating, via the circuitry, at least one position of the client device in the real environment by matching the surface information to the visibility event packet information corresponding to a first visibility event packet of the one or more visibility event packets;transmitting, via the circuitry, the at least one position from the client device to the server; andreceiving, via the circuitry, at least one second visibility event packet of the one or more visibility event packets when the at least one position is within the navigational route at the client device from the server.. A method of visibility event navigation, including one or more visibility event packets located ...

Semiconductor package

A semiconductor device including an integrated circuit, a dielectric layer, a plurality of connecting terminals and at least one dummy conductor is provided. The integrated circuit has a plurality of connecting pads, and the dielectric layer is disposed thereon and partially exposes the plurality of the connecting pads by a plurality of openings defined therein. The plurality of the connecting terminals is disposed on the plurality of the connecting pads exposed by the plurality of the openings. The at least one dummy conductor is disposed on the dielectric layer and electrically isolated from the integrated circuit. A substantial topology variation is between the plurality of the connecting terminals and the at least one dummy conductor. A semiconductor package having the semiconductor device is also provided.

Connector Structure and Method of Forming Same

Connector structures and methods of forming the same are provided. A method includes forming a first patterned passivation layer on a workpiece, the first patterned passivation layer having a first opening exposing a conductive feature of the workpiece. A seed layer is formed over the first patterned passivation layer and in the first opening. A patterned mask layer is formed over the seed layer, the patterned mask layer having a second opening exposing the seed layer, the second opening overlapping with the first opening. A connector is formed in the second opening. The patterned mask layer is partially removed, an unremoved portion of the patterned mask layer remaining in the first opening. The seed layer is patterned using the unremoved portion of the patterned mask layer as a mask. 1. A structure comprising:a substrate comprising active devices;a metallization layer over the substrate, the metallization layer comprising a conductive feature, the conductive feature being electrically coupled to the active devices;a first passivation layer over the metallization layer, the first passivation layer contacting a first portion of the conductive feature, a second portion of the conductive feature being free from the first passivation layer, the second portion of the conductive feature having a first width;a seed layer over the second portion of the conductive feature, the seed layer being a continuous conductive material having a second width, the second width being less than the first width; anda connector over the seed layer, the connector having a third width, the third width being less than the second width.2. The structure of further comprising:a second passivation layer over the first passivation layer.3. The structure of further comprising:a protection layer having a first portion disposed between the conductive feature and the seed layer, and a second portion disposed between the first passivation layer and the second passivation layer.4. The structure of claim ...

Semiconductor device

There is a need to improve reliability of the semiconductor device. A semiconductor device includes a printed circuit board and a semiconductor chip mounted over the printed circuit board. The semiconductor chip includes a pad, an insulation film including an opening to expose part of the pad, and a pillar electrode formed over the pad exposed from the opening. The printed circuit board includes a terminal and a resist layer including an opening to expose part of the terminal. The pillar electrode of the semiconductor chip and the terminal of the printed circuit board are coupled via a solder layer. Thickness h 1 of the pillar electrode is measured from the upper surface of the insulation film. Thickness h 2 of the solder layer is measured from the upper surface of the resist layer. Thickness h 1 is greater than or equal to a half of thickness h 2 and is smaller than or equal to thickness h 2 .

LAYERED CONTACT STRUCTURE

A three dimensional multi-die package includes a first die and second die. The first die includes a contact attached to solder. The second die is thinned by adhesively attaching a handler to a top side of the second die and thinning a bottom side of the second die. The second die includes a multilayer contact of layered metallurgy that inhibits transfer of adhesive thereto. The layered metallurgy includes at least one layer that is wettable to the solder. The multilayer contact may include a Nickel layer, a Copper layer upon the Nickel layer, and a Nickel-Iron layer upon the Copper layer. The multilayer contact may also include a Nickel layer, a Copper-Tin layer upon the Nickel layer, and a Tin layer upon the Copper-Tin layer. 1. A semiconductor device fabrication method comprising: forming a barrier layer upon a dielectric layer;forming an electrically conductive plating layer upon the barrier layer, and;forming a multilayered contact upon the plating layer by plating a Nickel layer upon the plating layer, plating a Copper layer upon the Nickel layer, and plating a Tin layer upon the Nickel layer.2. The semiconductor device fabrication method of claim 1 , further comprising:heat treating the multilayered contact to at least partially reflow the Tin layer with the Copper layer to form a Copper-Tin layer.3. The semiconductor device fabrication method of claim 2 , wherein Copper-Tin layer is upon the Nickel layer.4. The semiconductor device fabrication method of claim 2 , wherein a portion of the Tin layer is retained upon the Copper-Tin layer.5. The semiconductor device fabrication method of claim 1 , further comprising:attaching a handler wafer to the multilayered contact side of the semiconductor device with adhesive.6. The semiconductor device fabrication method of claim 1 , further comprising: forming a photoresist upon the conductive layer;forming an contact trench in the photoresist layer, the contact trench exposing a portion of the conductive layer;forming ...

Three-Dimensional Chip Stack and Method of Forming the Same

A three-dimensional chip stack includes a first chip bonded to a second chip to form an electrical interconnection therebetween. The bonded interconnection includes a first conductive pillar overlying a first substrate of the first chip, a second conductive pillar overlying a second substrate of the second chip, and a joint structure between the first conductive pillar and the second conductive pillar. The joint structure includes a first IMC region adjacent to the first conductive pillar, a second IMC region adjacent to the second conductive pillar, and a metallization layer between the first IMC region and the second IMC region.

Backmetal removal methods

Various implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; forming an organic material over the first side of the semiconductor substrate and the plurality of notches; thinning a second side of the semiconductor substrate opposite the first side one of to or into the plurality of notches; stress relief etching the second side of the semiconductor substrate; applying a backmetal over the second side of the semiconductor substrate; removing one or more portions of the backmetal through jet ablating the second side of the semiconductor substrate; and singulating the semiconductor substrate through the permanent coating material into a plurality of semiconductor packages.

Semiconductor Device

Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion ( 2 ) formed on the upper surface of a semiconductor substrate ( 1 ), a passivation layer ( 3 ) so formed on the upper surface of the semiconductor substrate ( 1 ) as to overlap a part of the electrode pad portion ( 2 ) and having a first opening portion ( 3 a ) where the upper surface of the electrode pad portion ( 2 ) is exposed, a barrier metal layer ( 5 ) formed on the electrode pad portion ( 2 ), and a solder bump ( 6 ) formed on the barrier metal layer ( 5 ). The barrier metal layer ( 5 ) is formed such that an outer peripheral end ( 5 b ) lies within the first opening portion ( 3 a ) of the passivation layer ( 3 ) when viewed in plan.

Multiple bond via arrays of different wire heights on a same substrate

Apparatuses relating generally to a substrate are disclosed. In such an apparatus, first wire bond wires (“first wires”) extend from a surface of the substrate. Second wire bond wires (“second wires”) extend from the surface of the substrate. The first wires and the second wires are external to the substrate. The first wires are disposed at least partially within the second wires. The first wires are of a first height. The second wires are of a second height greater than the first height for coupling of at least one electronic component to the first wires at least partially disposed within the second wires.

Dummy Flip Chip Bumps for Reducing Stress

A device includes a metal pad over a substrate. A passivation layer includes a portion over the metal pad. A post-passivation interconnect (PPI) is electrically coupled to the metal pad, wherein the PPI comprises a portion over the metal pad and the passivation layer. A polymer layer is over the PPI. A dummy bump is over the polymer layer, wherein the dummy bump is electrically insulated from conductive features underlying the polymer layer. 1. A device comprising:a substrate;a metal pad over the substrate;a passivation layer comprising a portion over the metal pad;a post-passivation interconnect (PPI) electrically coupling to the metal pad, wherein the PPI comprises a portion over the metal pad and the passivation layer;a polymer layer over the PPI; a first portion extending into the polymer layer to electrically couple to the metal pad; and', 'a second portion having a bottom surface contacting a top surface of the polymer layer; and, 'a non-solder electrical connector comprisinga dummy bump having a bottom surface contacting the top surface of the polymer layer.2. The device of claim 1 , wherein the dummy bump comprises:a non-solder bump and a solder cap over the non-solder bump.3. The device of further comprising a device over the non-solder electrical connector and the dummy bump claim 1 , wherein the device comprises a dielectric layer claim 1 , and a bottom surface of the dielectric layer in the device is in contact with a top surface of the dummy bump.4. The device of claim 3 , wherein the dummy bump comprises a solder region claim 3 , and the bottom surface of the dielectric layer is in contact with the top surface of the dummy bump.5. The device of claim 4 , wherein the dummy bump further comprises a non-solder portion underlying the solder region.6. The device of claim 1 , wherein the polymer layer is a polyimide layer claim 1 , and wherein the dummy bump comprises a copper-containing material.7. The device of claim 1 , wherein the dummy bump is ...

Semiconductor Device

Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion ( 2 ) formed on the upper surface of a semiconductor substrate ( 1 ), a passivation layer ( 3 ) so formed on the upper surface of the semiconductor substrate ( 1 ) as to overlap a part of the electrode pad portion ( 2 ) and having a first opening portion ( 3 a ) where the upper surface of the electrode pad portion ( 2 ) is exposed, a barrier metal layer ( 5 ) formed on the electrode pad portion ( 2 ), and a solder bump ( 6 ) formed on the barrier metal layer ( 5 ). The barrier metal layer ( 5 ) is formed such that an outer peripheral end ( 5 b ) lies within the first opening portion ( 3 a ) of the passivation layer ( 3 ) when viewed in plan.