Alignment Marks in Substrate Having Through-Substrate Via (TSV)

This application is a continuation of U.S. patent application Ser. No. 14/586,276, entitled “Alignment Marks in Substrate Having Through-Substrate Via (TSV),” filed on Dec. 30, 2014, which application is a continuation of U.S. patent application Ser. No. 12/874,952, entitled “Alignment Marks in Substrate Having Through-Substrate Via (TSV),” filed on Sep. 2, 2010, now U.S. Pat. No. 8,928,159 issued on Jan. 6, 2015, which applications are incorporated herein by reference.

In order to form three-dimensional (3D) integrated circuit structures, through-substrate vias (TSVs) are used to electrically couple front-side features to the backside features of a wafer. On the front side, there may be interconnect structures and metal bumps, for example. On the backside, there may be metal bumps and redistribution lines. Dual-side alignment needs to be performed in order to accurately align the backside features and the front-side features with each other.

Typically, the front-side features are formed on the wafer first, followed by a backside grinding to thin a silicon substrate in the wafer, until the TSVs are exposed. Front-side alignment marks are incorporated in the front-side features. The dual-side alignment is performed from the backside using an infra-red (IR) alignment system for locating the front-side alignment marks, wherein the infra-red light emitted by the IR alignment system penetrates through the thinned silicon substrate to reach the front-side alignment marks. Backside alignment marks are then made on the backside of the wafers by etching into the backside layer(s) and into the silicon substrate.

Due to the limitation of the IR alignment system, and further due to the thickness variation in the grinded silicon substrate, the accuracy of the dual-side alignment is low, and the misalignment may be as high as about 2 μm.

The making and using of the embodiments of the disclosure are discussed in detail below. It should be appreciated, however, that the embodiments provide many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative, and do not limit the scope of the disclosure.

A novel dual-side alignment mark and methods of forming the same are provided in accordance with an embodiment. The intermediate stages of manufacturing the dual-side alignment marks are illustrated in accordance with an embodiment. The variations of the embodiments are then discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements.

Referring to FIG. 1, wafer 2, which includes substrate 10, is provided. In an embodiment, substrate 10 is a semiconductor substrate, such as a bulk silicon substrate, although it may include other semiconductor materials such as group III, group IV, and/or group V elements. Integrated circuit devices 16, which may include transistors, may be formed at front surface 10a of substrate 10. In alternative embodiments, wafer 2 is an interposer or a package substrate, which may not include active devices such as transistors therein. However, passive devices such as transistors and capacitors may be included in wafer 2. Substrate 10 thus may be formed of a semiconductor material such as silicon or formed of a dielectric material. Interconnect structure 12 including metal lines and vias formed therein is formed over substrate 10, and may be electrically coupled to the integrated circuit devices. The metal lines and vias may be formed of copper or copper alloys, and may be formed using the well-known damascene processes. Interconnect structure 12 may include commonly known inter-layer dielectric (ILD) 11 and inter-metal dielectrics (IMDs), which are formed over ILD 11.

Alignment mark 14 is formed on the front side of substrate 10, and may be formed, for example, in the first-level metal layer (the bottom IMD layer), although it may be formed in other-level metal layers. A top view of an exemplary alignment mark 14 is illustrated in FIG. 8. Alignment mark 14 may have different shapes other than what is shown in FIG. 8.

Through-substrate vias (TSVs) 20 are formed in substrate 10, and extend from front surface 10a of substrate 10 into substrate 10. Depending on whether TSVs 20 are formed using a via-first approach or a via-last approach, TSVs 20 may extend into ILD 11 that is used to cover the active devices, but not into the IMD layers in interconnect structure 12. Alternatively, TSVs 20 may penetrate through both substrate 10, ILD 11, and possibly interconnect structure 12. Isolation layers 22 are formed on the sidewalls of TSVs 20, and electrically insulate the respective TSVs 20 from substrate 10. Isolation layers 22 may be formed of commonly used dielectric materials such as silicon nitride, silicon oxide (for example, tetra-ethyl-ortho-silicate (TEOS) oxide), and the like.

TSVs 20 include functional TSVs 20A and alignment-mark TSVs 20B. Although only one alignment-mark TSV 20B is illustrated, there may be a plurality of alignment-mark TSVs 20B, as illustrated in FIGS. 9A through 9G and FIGS. 11A through 11D. Functional TSVs 20A may be used to electrically couple the conductive features on the front side of substrate 10 to the conductive features on the backside of substrate 10. Alignment-mark TSVs 20B are used for aligning the features on the backside to the features on the front side of wafer 2. Alignment-mark TSVs 20B and alignment mark 14 are aligned to each other. In an embodiment, functional TSVs 20A and alignment-mark TSVs 20B are formed simultaneously. In alternative embodiments, functional TSVs 20A and alignment-mark TSVs 20B are formed at different times by separate formation processes. Further, functional TSVs 20A may have a same diameter, a same pitch, and/or a same height as alignment-mark TSVs 20B. Alternatively, the diameter, the pitch, and/or the height of functional TSVs 20A may be different from that of alignment-mark TSVs 20B. Metal bumps 18 may then be formed on the front side of wafer 2.

Referring to FIG. 2, wafer 2 is bonded to carrier 27, for example, through adhesive 25, which may be ultra-violet (UV) glue. Next, as shown in FIG. 3, a backside grinding is performed to remove excess portions of substrate 10. An etch may further be performed to lower back surface 10b of substrate 10, so that TSVs 20 protrude above back surface 10b.

In FIG. 4, passivation layer 24 is formed to cover back surface 10b of substrate 10 and TSVs 20. In an exemplary embodiment, passivation layer 24 includes silicon nitride layer 24a and silicon oxynitride layer 24b over silicon nitride layer 24a, although passivation layer 24 may be formed different materials and/or have different structures.

Next, using a patterned photo resist, portions of passivation layer 24 are etched, and the ends of TSVs 20 (including functional TSVs 20A and alignment-mark TSVs 20B) are exposed. The patterned photo resist is then removed, resulted in a structure shown in FIG. 5. The exposed alignment-mark TSVs 20B may thus be used as alignment mark 32, which are used for the alignment in the formation of backside features such as redistribution lines (RDLs) and/or metal bumps, so that the backside features on the backside of wafer 2 may be accurately aligned to desirable positions, and aligned to front-side alignment mark 14.

FIG. 6 illustrates the formation of under-bump metallurgy (UBM) layer 28, which may be blanket formed on passivation layer 24 and exposed TSVs 20, for example. UBM layer 28 may be formed using sputtering or other applicable methods. UBM layer 28 may include a barrier layer 28a and a seed layer 28b on barrier layer 28a. In some embodiments, barrier layer 28a includes a Ti layer, a Ta layer, a TiN layer, a TaN layer, or combinations thereof, although other materials may also be used. In some embodiments, the seed layer 28b includes copper.

FIG. 7 illustrates the formation of exemplary backside features on the backside of wafer, wherein the backside features may include metal layers, metal bumps, passivation layers, micro bumps, and/or the like. In the exemplary embodiment as shown in FIG. 7, backside features 30 represent metal bumps and/or redistribution lines (RDLs). It is appreciated that although one layer of metal bumps/RDLs is shown, there may be one or more layer of RDLs, and metal bumps over and connected to the RDLs. In an exemplary embodiment, the formation of features 30 includes forming a mask (not shown) over UBM layer 28, with a portion of UBM layer 28 exposed through openings in the mask. A plating is then performed to plate a conductive material into the openings to form backside features 30. The mask is then removed, and the portions of the UBM layer 28 previously covered by the mask are etched. Alignment-mark TSVs 20B are also exposed, and may be used for the alignment in the formation of additional features such as RDLs and/or metal bumps over backside features 30.

FIGS. 9A through 9G illustrate top views of exemplary alignment marks 32, each formed of a plurality of alignment-mark TSVs 20B. When the plurality of alignment-mark TSVs 20B are grouped to form alignment mark 32, the plurality of alignment-mark TSVs 20B may be arranged in an rectangular region (also marked as 32) having length L and width W, wherein the rectangular region may be free from functional TSVs. Length L and width W may be between about 50 μm and about 400 μm, and may be between about 100 μm and about 200 μm. Accordingly, the rectangular region may have a top-view area smaller than about 400 μm×400 μm, or less than about 200 μm×200 μm.

In FIGS. 9A through 9G, alignment-mark TSVs 20B may be arranged as different patterns. For example, in FIGS. 9A and 9F, alignment-mark TSVs 20B are aligned to lines 36A and 36B that cross each other. In FIGS. 9B, 9C, and 9G, alignment-mark TSVs 20B are aligned to lines 38A and 38B that terminate at common points 40. FIGS. 9D and 9E illustrate other exemplary patterns.

FIG. 10 illustrates an exemplary lithography mask 33 for forming TSVs 20, wherein alignment mark patterns 32′ are formed in lithography mask 33 along with patterns 20A′ for forming functional TSVs 20. Alignment-mark patterns 32′ define the patterns of alignment-mark TSVs 20B, while patterns 20A′ define the patterns of functional TSVs 20A.

FIGS. 11A through 11D illustrate alternative embodiments in which alignment marks 32 are formed of trench-type TSVs 20B, which, instead of having circular top-view shapes, may have other shapes including, but are not limited to, rectangles, crosses, and combinations thereof. Trench-type TSVs 20B may be formed at the same time as, or at different times than, forming functional TSVs 20A. Similarly, trench-type TSVs 20B also penetrate through substrate 10.

By using the embodiments, alignment marks may be formed at the same time functional TSVs are formed. Therefore, the cost incurred in conventional alignment-mark formation processes, including forming a photo resist for defining the patterns of backside alignment marks on the backside of wafer 2, etching wafer 2 for forming the backside alignment marks, and stripping off the photo resist is saved. Further, the accuracy for forming the alignment marks is improved. In conventional alignment mark formation techniques, the misalignment may be as great as about 2 μm. While in the embodiments, the misalignment is reduced to less than 1 μm.

In an embodiment, a device includes: a substrate having a first surface and a second surface opposite the first surface; an interconnect adjacent the first surface of the substrate; a plurality of conductive features adjacent the second surface of the substrate; a plurality of first through-substrate vias (TSVs) extending from the first surface of the substrate to the second surface of the substrate, the first TSVs electrically connecting the conductive features to the interconnect; and a first alignment mark including a plurality of second TSVs extending from the first surface of the substrate to the second surface of the substrate, the second TSVs being electrically isolated from the conductive features and the interconnect, the second TSVs being disposed in an alignment mark region of the substrate, the alignment mark region being free from the first TSVs.

In some embodiments of the device, the alignment mark region of the substrate has a length of between about 50 μm and about 400 μm, and the alignment mark region of the substrate has a width of between about 50 μm and about 400 μm. In some embodiments of the device, a first subset of the second TSVs are disposed along a first axis, and a second subset of the second TSVs are disposed along a second axis, the first axis and the second axis being parallel to the second surface of the substrate. In some embodiments of the device, the first axis intersects the second axis at first point disposed at a center of the alignment mark region. In some embodiments of the device, the first axis intersects the second axis at a first point disposed offset from a center of the alignment mark region. In some embodiments of the device, the interconnect includes a second alignment mark, the second alignment mark being aligned to the first alignment mark. In some embodiments of the device, the first TSVs and the second TSVs have the same top-view shape. In some embodiments of the device, the first TSVs and the second TSVs have different top-view shapes. In some embodiments of the device, the first TSVs and the second TSVs have the same width. In some embodiments of the device, the first TSVs and the second TSVs have the same height. In some embodiments of the device, the substrate is free from active devices.

In an embodiment, a device includes: a substrate having a first surface and a second surface opposite the first surface; an interconnect on the first surface of the substrate, the interconnect including conductive features disposed in dielectric layers; a passivation layer on the second surface of the substrate; a first through-substrate via (TSV) extending through the passivation layer and the substrate, the first TSV being electrically connected to the conductive features of the interconnect; a redistribution line (RDL) on the passivation layer and the first TSV, the RDL being electrically connected to the first TSV; and a second TSV extending through the passivation layer and the substrate, the second TSV being electrically isolated from the RDL and the conductive features of the interconnect.

In some embodiments of the device, the second TSV has a first end contacting one of the dielectric layers of the interconnect. In some embodiments of the device, the passivation layer has an opening exposing a second end of the second TSV. In some embodiments of the device, the first TSV and the second TSV extend through the passivation layer and the substrate by the same distance. In some embodiments of the device, the substrate is free from active devices.

In an embodiment, a device includes: a substrate having a first region and a second region; an interconnect on a first surface of the substrate; a passivation layer on a second surface of the substrate; a plurality of first through-substrate vias (TSVs) extending through the passivation layer and the first region of the substrate, the second region of the substrate being free from the first TSVs, the first TSVs being electrically connected to the interconnect; and a plurality of second TSVs extending through the passivation layer and the second region of the substrate, the first region of the substrate being free from the second TSVs, the second TSVs being electrically isolated from the interconnect.

In some embodiments, the device further includes: a plurality of conductive features on the first TSVs, the first TSVs being electrically connected to the conductive features, the second TSVs being electrically isolated from the conductive features. In some embodiments of the device, the first TSVs and the second TSVs extend through the passivation layer and the substrate by the same distance. In some embodiments of the device, the substrate is free from active devices.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.