SEMICONDUCTOR LASER MOUNTING WITH INTACT DIFFUSION BARRIER LAYER

A first contact (310) surface of a semiconductor laser chip (302) is formed to a surface roughness selected to have a maximum peak to valley height that is substantially smaller than a diffusion barrier layer thickness. A diffusion barrier layer that includes a non-metallic, electrically-conducting compound and that has the barrier layer thickness is applied to the first contact surface, and the semiconductor laser chip is soldered to a carrier mounting (304) along the first contact surface using a solder composition (306) by heating the soldering composition to less than a threshold temperature at which dissolution of the barrier layer into the soldering composition occurs. Thereby the diffusion barrier remains contiguous. The non-metallic, electrically conducting compound may comprise at least one of titanium nitride, titanium oxy-nitride, tungsten nitride, cerium oxide and cerium gadolinium oxy-nitride ...

Conductive particles, anisotropic conductive material and connection structure

SEMICONDUCTOR COMPONENT HAVING INCREASED STABILITY RELATIVE TO THERMOMECHANICAL INFLUENCES, AND METHOD FOR CONTACTING A SEMICONDUCTOR

The invention relates to a semiconductor component, wherein the surface of a semiconductor (11) is contacted by means of a wiring (15), wherein an electrically conductive layer (12) is disposed between the surface of the semiconductor (11) and the wiring, the thermal coefficient of expansion thereof being between that of the semiconductor (11) and that of the material of the wiring. The invention further relates to a method for contacting a semiconductor (11), wherein an electrically conductive layer is at least partially disposed on the surface of the semiconductor (11), and wherein wiring takes place subsequently, wherein the thermal coefficient of expansion of the electrically conductive layer is between that of the semiconductor (11) and that of the material for the wiring.

Semiconductor device comprising a chip substrate, a mold, and a buffer layer

A semiconductor device and a method of manufacturing the semiconductor device are disclosed. The semiconductor device includes a chip substrate, a mold, and a buffer layer. The mold is disposed over the chip substrate. The buffer layer is externally embedded between the chip substrate and the mold. The buffer layer has an elastic modulus or a coefficient of thermal expansion less than that of the mold. The method includes disposing a buffer layer at least covering scribe lines of a substrate, forming a mold over the substrate and covering the buffer layer, and cutting along the scribe lines and through the mold, the buffer layer and the substrate.

NON-DESTRUCTIVE TESTING OF INTEGRATED CIRCUIT CHIPS

Semiconductor devices and electronics packaging methods include integrated circuit chips having redundant signal bond pads along with signal bond pads connected to the same signal port for non-destructive testing of the integrated circuit chips prior to packaging. Electrical testing is made via the redundant signal bond after which qualified integrated circuit chips can be attached to a pristine and bumped final interposer or printed circuit board to provide increased reliability to the assembled electronic package.

Semiconductor device having a junction portion contacting a schottky metal

A semiconductor device according to the present invention includes a first conductive-type SiC semiconductor layer, and a Schottky metal, comprising molybdenum and having a thickness of 10 nm to 150 nm, that contacts the surface of the SiC semiconductor layer. The junction of the SiC semiconductor layer to the Schottky metal has a planar structure, or a structure with recesses and protrusions of equal to or less than 5 nm. A method for manufacturing a semiconductor device according to the present invention includes: a step of forming a Schottky metal, comprising molybdenum and having a thickness of 10 nm to 150 nm, on the surface of a first conductive-type SiC semiconductor layer; and a step for heat treating the Schottky metal while the surface thereof is exposed, and structuring the junction of the SiC semiconductor layer to the Schottky metal to be planar, or to have recesses and protrusions of equal to or less than 5 nm.

Semiconductor integrated circuit device

In semiconductor integrated circuit devices for vehicle use, an aluminum pad on a semiconductor chip and an external device are coupled to each other by wire bonding using a gold wire for the convenience of mounting. Such a semiconductor integrated circuit device, however, causes a connection failure due to the interaction between aluminum and gold in use for a long time at a relatively high temperature (about 150 degrees C.). A semiconductor integrated circuit device can include a semiconductor chip as a part of the device, an electrolytic gold plated surface film (gold-based metal plated film) provided over an aluminum-based bonding pad on a semiconductor chip via a barrier metal film, and a gold bonding wire (gold-based bonding wire) for interconnection between the plated surface film and an external lead provided over a wiring board (wiring substrate).

ELECTROCONDUCTIVE BONDING MATERIAL, METHOD FOR BONDING CONDUCTOR, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

An electro-conductive bonding material includes: metal components of a high-melting-point metal particle that have a first melting point or higher; a middle-melting-point metal particle that has a second melting point which is first temperature or higher, and second temperature or lower, the second temperature is lower than the first melting point and higher than the first temperature; and a low-melting-point metal particle that has a third melting point or lower, the third melting point is lower than the first temperature.

DISPLAY BACKPLANE AND MANUFACTURING METHOD THEREOF AND DISPLAY DEVICE

A display backplane is provided, including a base, wherein pixel circuits, bonding electrodes, and bonding connection wires are on the base; the bonding electrodes are coupled to the bonding connection wires in a one-to-one correspondence; the bonding electrodes and the bonding connection wires are on two opposite surfaces of the base; the pixel circuits and the bonding connection wires are on a same side of the base; one end of each bonding connection wire is coupled to the bonding electrode through the first via in the base; the other end of each of at least some bonding connection wires is coupled to the pixel circuit; and an orthographic projection of at least one of the bonding electrodes and the bonding connection wires on the base is not coincident with an orthographic projection of the pixel circuit on the base.

Power semiconductor module and method of manufacturing a power semiconductor module

The present invention relates to a power semiconductor module comprising a semiconductor device (12), in particular an insulated gate bipolar transistor, a reverse conductive insulated gate bipolar transistor, or a bi-mode insulated gate transistor, with an emitter electrode and a collector electrode, wherein an electrically conductive upper layer (14) is sintered to the emitter electrode, the upper layer (14) at least partly being capable of forming an eutecticum with the semiconductor of the semiconductor device (12) and at least partly having a coefficient of thermal expansion which differs from the coefficient of thermal expansion of the semiconductor in a range of ≤ 250%, in particular ≤ 50%, and wherein an electrically conductive base plate (20) is sintered to the collector electrode, and wherein the semiconductor module (10) further comprises an electrically conductive area (24) being electrically isolated from the base plate (20) and being connected to the upper layer (14) via a ...

СВЕТОИЗЛУЧАЮЩЕЕ УСТРОЙСТВО И СПОСОБ ЕГО ИЗГОТОВЛЕНИЯ

Предложено светоизлучающее устройство и способ изготовления устройства, которое может испускать свет с малой неравномерностью цвета и высокой яркостью. Устройство включает светоизлучающий прибор, светопроницаемый элемент, принимающий падающий свет от светоизлучающего прибора, и покрывающий элемент. Светопроницаемый элемент сформирован из неорганического материала и является преобразующим свет элементом, включающим непокрытую снаружи светоизлучающую поверхность и боковую поверхность, примыкающую к светоизлучающей поверхности. Покрывающий элемент содержит отражающий материал и покрывает, по меньшей мере, боковые поверхности светопроницаемого элемента. По существу, только светоизлучающая поверхность выполняет функцию области излучения устройства. Имеется возможность обеспечить испускаемый свет, имеющий превосходную направленность и яркость. Испускаемый свет можно легко оптически регулировать. Если каждое светоизлучающее устройство используется в качестве единичного источника света, светоизлучающее ...

Halbleiterbauelemente und Verfahren zur Herstellung von Halbleiterbauelementen

Bauelement, umfassend:ein Halbleitermaterial (1), das eine erste Hauptoberfläche (2), eine gegenüberliegende Oberfläche (3), die der ersten Hauptoberfläche gegenüberliegt, und eine seitliche Oberfläche (4), die sich von der ersten Hauptoberfläche zur gegenüberliegenden Oberfläche erstreckt, umfasst, wobei das Halbleitermaterial eine Funktionsfläche umfasst, die in einem Hochfrequenzbereich betrieben wird;ein erstes elektrisches Kontaktelement (5), das auf der ersten Hauptoberfläche (2) des Halbleitermaterials angeordnet ist;ein Glasmaterial (6), das eine zweite Hauptoberfläche (7) umfasst, wobei das Glasmaterial die seitliche Oberfläche (4) des Halbleitermaterials kontaktiert und wobei die erste Hauptoberfläche (2) des Halbleitermaterials und die zweite Hauptoberfläche des Glasmaterials in einer gemeinsamen Ebene angeordnet sind; undeine Metallschicht (11), die über der ersten Hauptoberfläche (2) des Halbleitermaterials und über dem Glasmaterial angeordnet ist, wobei eine passive elektronische ...

Semiconductor laser mounting with intact diffusion barrier layer

A first contact (310) surface of a semiconductor laser chip (302) is formed to a surface roughness selected to have a maximum peak to valley height that is substantially smaller than a diffusion barrier layer thickness. A diffusion barrier layer that includes a non-metallic, electrically-conducting compound and that has the barrier layer thickness is applied to the first contact surface, and the semiconductor laser chip is soldered to a carrier mounting (304) along the first contact surface using a solder composition (306) by heating the soldering composition to less than a threshold temperature at which dissolution of the barrier layer into the soldering composition occurs. Thereby the diffusion barrier remains contiguous. The non-metallic, electrically conducting compound may comprise at least one of titanium nitride, titanium oxy-nitride, tungsten nitride, cerium oxide and cerium gadolinium oxy-nitride ...

SEMICONDUCTOR DEVICE

METHOD FOR FLATTENING RECESSES FILLED WITH COPPER

L'invention concerne un procédé d'aplanissement d'une structure comportant un substrat (20) présentant une surface supérieure munie d'évidements et revêtue d'une couche barrière (26) continue surmontée d'une couche de cuivre continue remplissant au moins les évidements, le procédé comprenant les étapes successives suivantes : a) polissage mécano-chimique du cuivre, ce polissage étant sélectif par rapport à la couche barrière (26) de sorte que du cuivre reste dans les évidements (22) en retrait par rapport à la surface supérieure du substrat ; b) dépôt sur la surface exposée de la structure d'un matériau (34) recouvrant au moins le cuivre au niveau des évidements ; et c) polissage mécano-chimique aplanissant de la structure jusqu'à mettre à nu le substrat (20), le cuivre restant enfoui sous le matériau (34).

BIOSENSOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

SEMICONDUCTOR PACKAGE

A semiconductor package including a first semiconductor chip having a first thickness, a second semiconductor chip on the first semiconductor chip and having a second thickness, the second thickness being smaller than the first thickness, a third semiconductor chip on the second semiconductor chip and having a third thickness, the third thickness being smaller than the second thickness, a fourth semiconductor chip on the third semiconductor chip and having a fourth thickness, the fourth thickness being greater than the third thickness, and a fifth semiconductor chip disposed on the fourth semiconductor chip and having a fifth thickness, the fifth thickness being greater than the fourth thickness may be provided.

Package Level Tuning Techniques for Propagation Channels of High-Speed Signals

Various semiconductor chip carrier substrate circuit tuning apparatus and methods are disclosed. In one aspect, a method of manufacturing is provided that includes assembling a semiconductor chip carrier substrate with a first input/output site adapted to electrically connect to an external component and a second input/output site adapted to electrically connect to an input/output site of a semiconductor chip. An inductor is placed in the semiconductor chip carrier substrate. The inductor is electrically connected between the first and second input/output sites. The inductor has a preselected inductance to reduce an impedance discontinuity between the first input/output site or the second input/output site due to coupling to a second conductor in the semiconductor chip carrier substrate.

Method for fabricating semiconductor component with adjustment circuitry for electrical characteristics or input/output configuration

A semiconductor component includes adjustment circuitry configured to adjust selected physical and electrical characteristics of the component or elements thereof, and an input/output configuration of the component. The component includes a semiconductor die, a substrate attached to the die, and terminal contacts on the substrate. The adjustment circuitry includes conductors and programmable links, such as fuses or anti-fuses, in electrical communication with the die and the terminal contacts. The adjustment circuit can also include capacitors and inductance conductors. The programmable links can be placed in a selected state (e.g., short or open) using a laser or programming signals. A method for fabricating the component includes the steps of forming the adjustment circuitry, and then placing the programmable links in the selected state to achieve the selected adjustment.

POWER SEMICONDUCTOR MODULE AND METHOD OF MANUFACTURING A POWER SEMICONDUCTOR MODULE

A power semiconductor module including a semiconductor device (e.g., an insulated gate bipolar transistor (IGBT), a reverse conductive (RC IGBT), or a bi-mode insulated gate transistor (BIGT)) with an emitter electrode and a collector electrode is provided. An electrically conductive upper layer is sintered to the emitter electrode. The upper layer is capable of forming an eutecticum with the semiconductor of the semiconductor device, and has a coefficient of thermal expansion which differs from the coefficient of thermal expansion of the semiconductor in a range of 250%, for example 50%. An electrically conductive base plate is sintered to the collector electrode. The semiconductor module includes an electrically conductive area which is electrically isolated from the base plate and connected to the upper layer via a direct electrical connection. The semiconductor module is easy to prepare, has an improved reliability and exhibits short circuit failure mode capacity.

SEMICONDUCTOR MODULE, DISPLAY DEVICE, AND SEMICONDUCTOR MODULE MANUFACTURING METHOD

Resin covers a side surface and a back surface of a blue LED and holds the blue LED level. An electrode is disposed between a top surface of a wiring substrate and a back surface of the blue LED, extends through the resin, and electrically connects the wiring substrate and the blue LED to each other. A light-outgoing surface (top-surface) of the blue LED is exposed without being covered with the resin, and the light-outgoing surface (top-surface) is flush with a top surface of the resin.

СВЕТОИЗЛУЧАЮЩЕЕ УСТРОЙСТВО И СПОСОБ ЕГО ИЗГОТОВЛЕНИЯ

... 1. Светоизлучающее устройство, содержащее: ! светоизлучающий прибор, ! светопроницаемый элемент, принимающий падающий свет от светоизлучающего прибора, и ! покрывающий элемент, ! причем светопроницаемый элемент образован преобразующим свет элементом из неорганического материала, который имеет светоизлучающую поверхность, непокрытую снаружи, и боковую поверхность, примыкающую к светоизлучающей поверхности, ! а покрывающий элемент содержит светоотражающий материал и покрывает по меньшей мере боковую поверхность светопроницаемого элемента. ! 2. Светоизлучающее устройство по п.1, в котором покрывающий элемент окружает светоизлучающий прибор. ! 3. Светоизлучающее устройство по п.2, в котором светопроницаемый элемент имеет форму пластины и содержит принимающую свет поверхность, противоположную указанной светоизлучающей поверхности, причем светоизлучающий прибор соединен с принимающей свет поверхностью. ! 4. Светоизлучающее устройство по п.3, в котором светоизлучающий прибор смонтирован на монтажной ...

Electroconductive bonding material comprising three types of metal particles with different melting points and its use for bonding an electronic component to a substrate

An electro-conductive bonding material (20,30) includes: high-melting-point metal particles with a component having a first melting point, middle-melting-point metal particles having a second melting point, lower than the first melting point, low-melting-point metal particles having a third melting point, lower than the second melting point and preferably a flux. The high-melting-point metal particles include Au, Ag, Cu, Au-plated Cu, Sn-Bi-plated Cu and Ag-plated Cu particles. The middle-melting-point metal particles include Sn-Bi and Sn-Bi-Ag particles. The low-melting-point metal particles include Sn-Bi-ln and Sn-Bi-Ga particles. The electro-conductive bonding material (20,30) is used for bonding a substrate (6) and an electronic component (8). A method for bonding comprises supplying the electro-conductive bonding material (e.g. by paste printing) to any one of an electrode (7) of a substrate (6) and a terminal of an electronic component (8) (e.g. an Au bump (9)), heating the supplied ...

Conductive bump and electroless Pt plating bath

The present invention provides a bump that can prevent diffusion of a metal used as a base conductive layer of the bump into a surface of an Au layer or an Ag layer. A conductive bump of the present invention is s conductive bump formed on a substrate. The conductive bump comprises, at least in order from the substrate: a base conductive layer; a Pd layer; a Pt layer; and an Au layer or an Ag layer having directly contact with the Pd layer, wherein a diameter of the conductive bump is 20 [mu]m or less.

SEMICONDUCTOR ELEMENT AND ELECTRIC DEVICE

A semiconductor element (20) is provided with a plurality of field effect transistors (90) and Schottky electrodes (9a). The Schottky electrodes (9a) are arranged along an outer circumference of a region wherein the field effect transistors (90) are formed.

Wire bonding process for copper-metallized integrated circuits

A robust, reliable and low-cost metal structure and process enabling electrical wire/ribbon connections to the interconnecting copper metallization of integrated circuits. The structure comprises a layer of barrier metal that resists copper diffusion, deposited on the non-oxidized copper surface in a thickness such that the barrier layer reduces the diffusion of copper at 250° C. by more than 80% compared with the absence of the barrier metal. The structure further comprises an outermost bondable layer which reduces the diffusion of the barrier metal at 250° C. by more than 80% compared with the absence of the bondable metal. Finally, a metal wire is bonded to the outermost layer for metallurgical connection. The barrier metal is selected from a group consisting of nickel, cobalt, chromium, molybdenum, titanium, tungsten, and alloys thereof. The outermost bondable metal layer is selected from a group consisting of gold, platinum, and silver.

Light emitting diode module for surface mount technology and method of manufacturing the same

An LED is provided to include: a first conductive type semiconductor layer; an active layer positioned over the first conductive type semiconductor layer; a second conductive type semiconductor layer positioned over the active layer; and a defect blocking layer comprising a masking region to cover at least a part of the top surface of the second conductive semiconductor layer and an opening region to partially expose the top surface of the second conductive type semiconductor layer, wherein the active layer and the second conductive type semiconductor layer are disposed to expose a part of the first conductive type semiconductor layer, and wherein the defect blocking layer comprises a first region and a second region surrounding the first region, and a ratio of the area of the opening region to the area of the masking region in the first region is different from a ratio of the area of the opening region to the area of the masking region in the second region.

Metallformkörper zur Schaffung einer Verbindung eines Leistungshalbleiterchips mit oberseitigen Potentialflächen zu Dickdrähten

Metallformkörper zur Schaffung einer Verbindung eines Leistungshalbleiters mit oberseitigen Potentialflächen zu Dickdrähten oder Bändchen, gekennzeichnet durch einen Metallformkörper (6a, 6b), der eine oder mehrere Potentialflächen überragt, und aus dem elektrisch vom übrigen Metallformkörper getrennt wenigstens ein Segment (6b) abgeteilt ist, das von einem Kontaktierungsabschnitt an eine Potentialfläche des Leistungshalbleiters zu einem davon lateral beabstandeten Befestigungsabschnitt für Dickdrähte reicht.

HALBLEITERBAUELEMENT UND VERFAHREN ZU SEINER HERSTELLUNG

Light emitting device package and lighting system

The use of low value capacitor integrated high voltage isolation

METHOD FOR FLATTENING RECESSES FILLED WITH COPPER

CONDUCTIVE PARTICLES, CONDUCTIVE MATERIAL AND CONNECTION STRUCTURE

Provided are: conductive particles capable of suppressing the clumping of a plurality of conductive particles, and reducing the connection resistance between electrodes when used in the connection between electrodes; and a conductive material using the conductive particles. These conductive particles (1) have substrate particles (2), and a conductive layer (3) disposed on the surface of the substrate particles (2) and including at least one type of metal component selected from the following: nickel, boron, tungsten and molybdenum. This conductive material includes the conductive particles (1) and a binder resin.

NON-DESTRUCTIVE TESTING OF INTEGRATED CIRCUIT CHIPS

Semiconductor devices and electronics packaging methods include integrated circuit chips having redundant signal bond pads along with signal bond pads connected to the same signal port for non-destructive testing of the integrated circuit chips prior to packaging. Electrical testing is made via the redundant signal bond after which qualified integrated circuit chips can be attached to a pristine and bumped final interposer or printed circuit board to provide increased reliability to the assembled electronic package.

SEMICONDUCTOR DEVICE STRUCTURE INCLUDING A BONDING STRUCTURE

A semiconductor device structure and method for manufacturing the same are provided. The semiconductor device structure includes a substrate, a dielectric structure, a pad, a conductive structure, and a buffer structure. The dielectric structure is disposed on the substrate. The pad is embedded in the dielectric structure. The conductive structure is disposed on the pad. The buffer structure is disposed on the pad and separates the conductive structure from the dielectric structure. A coefficient of thermal expansion (CTE) of the buffer structure ranges between a CTE of the dielectric structure and a CTE of the conductive structure.

Verfahren zum Drahtbonden

마이크로전자 구조체 내의 상호연결 패드를 위한 표면 마감부

... 표면 마감부가 마이크로전자 구조체 내에 형성될 수 있는데, 표면 마감부는 다층 층간부 구조체를 포함할 수 있다. 그러므로, 층간부 구조체의 필요한 특성, 예를 들어 유연성 및 일렉트로-마이그레이션 저항은, 단일 층으로써 이들 특성을 얻으려고 시도하기보다, 상이한 재료 층들에 의해 만족될 수 있다. 하나의 실시예에서, 다층 층간부 구조체는 이층 구조체를 포함할 수 있는데, 제1 층은 솔더 상호연결부에 근접하여 형성되고, 솔더 상호연결부와의 연성 조인트를 형성하는 재료를 포함하며, 제2 층은 제1 층 및 상호연결 패드 간에 형성된 강한 일렉트로-마이그레이션 저항을 가지는 재료를 포함한다. 추가의 실시예에서, 제3 층이 상호연결 패드에 인접하여 형성될 수 있는데 상호연결 패드와의 연성 조인트를 형성한다.

Conductive particle, conductive material and connecting structure

Provided are: a conductive particle whereby connection resistance can be reduced in the cases where electrodes are connected to each other; and a conductive material using the conductive particle. A conductive particle (1) of the present invention is provided with a base material particle (2), and a conductive material (4) that is disposed on a region of the base material particle (2), said region being a part of the surface of the base material particle, and the conductive material (4) is a material having a Mohs hardness higher than that of nickel.

INJECTION MOLDED SOLDER BUMPING

Methods for depositing material on a chip include forming a mold layer. The mold layer includes one or more openings over respective contact areas, each of the one or more openings having an upper volume and a lower volume. The upper volume has a smaller diameter than a diameter of the lower volume. Each contact area is within the respective lower volume. A material is injected into the one or more openings under pressure.

HETERO-BIPOLAR TRANSISTOR AND METHOD FOR PRODUCING THE SAME

A semiconductor device provided with a substrate made of material except for semiconductors and having thermal conductivity greater than that of the semiconductor material. The semiconductor device provides, on the support, a metal layer, a primary mesa, and electrodes formed on the primary mesa. The metal layer, which is in contact with the primary mesa, may be made of at least one of tungsten (W), molybdenum (Mo), and tantalum (Ta) with a thickness of the 10 to 60 nm.

SEMICONDUCTOR ELEMENT AND ELECTRICAL APPARATUS

A semiconductor element (20) of the present invention includes a plurality of field effect transistors (90) and a schottky electrode (9a), and the schottky electrode (9a) is formed along an outer periphery of a region where the plurality of field effect transistors (90) are formed.

Backlight Unit and Display Device Including the Same

A backlight unit and a display device including the same are disclosed. More specifically, a backlight unit is disclosed that includes a plurality of light sources disposed on a glass substrate and disposed in a plurality of rows and a plurality of columns, and first and second transistors disposed on the glass substrate and spaced apart from each other, wherein each of the first transistor and the second transistor is disposed so as not to overlap the plurality of light sources disposed at points where two rows and two columns cross each other. Thus, image quality is excellent.

Verbindungsstruktur mit Begrenzungsschicht

Es werden eine Verbindungsstruktur sowie ein Verfahren für die Bereitstellung einer Verbindungsstruktur, die leitfähige Elemente mit verringerten topografischen Schwankungen aufweist, offenbart. Die Verbindungsstruktur umfasst ein Kontaktpad, das über einem Substrat angeordnet ist. Das Kontaktpad umfasst eine erste Schicht auf einem ersten leitfähigen Material sowie eine zweite Schicht aus einem zweiten leitfähigen Material über der ersten Schicht. Das erste leitfähige Material und das zweite leitfähige Material bestehen im Wesentlichen aus demselben Material und sie weisen eine erste mittlere Korngröße und eine zweite mittlere Korngröße, die kleiner als die erste mittlere Korngröße ist, auf. Die Verbindungsstruktur umfasst weiterhin eine Passivierungsschicht, welche das Substrat und das Kontaktpad bedeckt, wobei die Passivierungsschicht eine Öffnung aufweist, welche das Kontaktpad freilegt.

Verfahren zum Drahtbonden

Verfahren zur Herstellung einer Leistungs-Halbleitervorrichtung und Leistungs-Halbleitervorrichtung

Aufgabe der Erfindung ist es, Folgendes anzugeben: ein Verfahren zur Herstellung einer besonders zuverlässigen Leistungs-Halbleitervorrichtung, die einem Bruch eines Leitungsmusters und einer isolierenden Schicht vorbeugt, und die eine Bondingstärke aufweist, die höher als die beim herkömmlichen Bonding zwischen dem Elektrodenanschluss und des Leitungsmusters ist; und eine derartige Leistungs-Halbleitervorrichtung. Dem Bruch des Leitungsmusters und der isolierenden Schicht wird vorgebeugt, indem folgende Maßnahmen einbezogen werden: ein Schritt, bei dem ein Elektrodenanschluss (3) auf einen Vorsprung (52c) gesetzt wird, der auf dem Leitungsmuster (52a) angeordnet ist, das auf der Schaltungsflächen-Seite der Keramikplatte (5) ausgerichtet ist, so dass ein zentraler Bereich einer zu bondenden Oberfläche (3j) des Elektrodenanschlusses in Kontakt mit einem Kopfbereich des Vorsprungs gelangt; und ein Schritt, in dem eine der zu bondenden Oberfläche (3j) gegenüberliegende Oberfläche (3z) des ...

Halbleitervorrichtung und Verfahren zum Fertigen einer Halbleitervorrichtung

Eine Elementelektrode (103) ist auf einer Oberfläche eines Halbleiterelements (101) angeordnet. Eine Metallschicht (105) ist auf der Elementelektrode (103) angeordnet und umfasst eine innere Region (105a) und eine äußere Region (105b1), die um die innere Region (105a) herum angeordnet ist. Die Metallschicht (105) weist eine Öffnung (TR) auf, welche die Elementelektrode (103) zwischen der inneren Region (105a) und der äußeren Region (105b1) freilegt. Die Elementelektrode (103) weist eine Lotbenetzbarkeit auf, die niedriger als eine Lotbenetzbarkeit der Metallschicht (105) ist. Eine externe Elektrode (117) ist an die innere Region (105a) der Metallschicht (105) angelötet.

SEMICONDUCTOR LASER MOUNTING WITH INTACT DIFFUSION BARRIER LAYER

A first contact (310) surface of a semiconductor laser chip (302) is formed to a surface roughness selected to have a maximum peak to valley height that is substantially smaller than a diffusion barrier layer thickness. A diffusion barrier layer that includes a non-metallic, electrically-conducting compound and that has the barrier layer thickness is applied to the first contact surface, and the semiconductor laser chip is soldered to a carrier mounting (304) along the first contact surface using a solder composition (306) by heating the soldering composition to less than a threshold temperature at which dissolution of the barrier layer into the soldering composition occurs. Thereby the diffusion barrier remains contiguous. The non-metallic, electrically conducting compound may comprise at least one of titanium nitride, titanium oxy-nitride, tungsten nitride, cerium oxide and cerium gadolinium oxy-nitride ...

Light-emitting device and its manufacturing method

Method for manufacturing terminal structure and method for manufacturing electronic device

SEMICONDUCTOR DEVICE

CONDUCTIVE PARTICLES

Silicon Carbide Device and Method for Forming a Silicon Carbide Device

A silicon carbide device includes a silicon carbide substrate, a contact layer including nickel, silicon and aluminum, a barrier layer structure including titanium and tungsten, and a metallization layer including copper. The contact layer is located on the silicon carbide substrate. The contact layer is located between the silicon carbide substrate and at least a part of the barrier layer structure. The barrier layer structure is located between the silicon carbide substrate and the metallization layer.

Methods of Integrated Chip of Ultra-Fine Pitch Bonding and Resulting Structures

A first and second semiconductor device are bonded together using a bonding contact pad embedded within a bonding dielectric layer of the first semiconductor device and at least one bonding via embedded within a bonding dielectric layer of the second semiconductor device. The bonding contact pad extends a first dimension in a first direction perpendicular to the major surface of the first semiconductor device and a second dimension in a second direction parallel to the plane of the first semiconductor wafer, the second dimension being at least twice the first dimension. The bonding via extends a third dimension in the first direction and a fourth dimension in the second direction, the third dimension being at least twice the first dimension. The bonding contact pad and bonding via may be at least partially embedded in respective bonding dielectric layers in respective topmost dielectric layers of respective stacked interconnect layers.

Halbleiterchip und Leistungsmodul und dessen Herstellungsverfahren

Ein Halbleiter-Chip enthält ein Halbleitersubstrat aus SiC, eine Stirnflächenelektrode, die an einer Hauptfläche des Halbleitersubstrats ausgebildet ist, und eine Rückflächenelektrode (eine Drain-Elektrode), die an einer Rückfläche des Halbleitersubstrats ausgebildet ist. Die Stirnflächenelektrode ist an einen Draht gebondet und enthält einen Al-Legierungs-Film, der ein Metall mit hohem Schmelzpunkt enthält. Der Al-Legierungs-Film enthält einen säulenförmigen Al-Kristall, der sich entlang einer Dickenrichtung des Al-Legierungs-Films erstreckt, wobei darin eine intermetallische Verbindung abgeschieden ist.

Fabricating method of light emitting device

... 색 온도를 조절할 수 있는 발광 장치의 제조 방법이 제공된다. 상기 발광 장치의 제조 방법은 기판 상에 다수의 발광 유닛을 형성하고, 다수의 발광 유닛 각각의 광특성을 측정하고, 다수의 발광 유닛 상에 프린트 방식을 이용하여 형광체를 도포하되, 각 발광 유닛 상에 도포되는 형광체는 상기 측정된 상기 각 발광 유닛의 광특성에 따라 조절되고, 상기 기판을 절삭하여, 상기 형광체가 도포된 다수의 발광 유닛을 유닛별로 분리하는 것을 포함한다.

Semiconductor devices and methods for manufacturing the same

Warpage-compensated bonded structure including a support chip and a three-dimensional memory chip

A first semiconductor die and a second semiconductor die can be bonded in a manner that enhances alignment of bonding pads. Non-uniform deformation of a first wafer including first semiconductor dies can be compensated for by forming a patterned stress-generating film on a backside of the first wafer. Metallic bump portions can be formed on concave surfaces of metallic bonding pads by a selective metal deposition process to reduce gaps between pairs of bonded metallic bonding pads. Pad-to-pad pitch can be adjusted on a semiconductor die to match the pad-to-pad pitch of another semiconductor die employing a tilt-shift operation in a lithographic exposure tool. A chuck configured to provide non-uniform displacement across a wafer can be employed to hold a wafer in a contoured shape for bonding with another wafer in a matching contoured position. Independently height-controlled pins can be employed to hold a wafer in a non-planar configuration.

반도체 실장용 접착제 및 반도체 센서

... 반도체를 실장하는 경우에, 갭을 고정밀도로 제어할 수 있고, 또한 내열성을 높일 수 있는 반도체 실장용 접착제를 제공한다. 본 발명에 따른 반도체 실장용 접착제는, 반도체의 실장에 사용되는 접착제로서, 실리콘 수지와 스페이서를 포함하고, 상기 스페이서의 함유량이, 상기 접착제 100중량％ 중, 0.1중량％ 이상 5중량％ 이하이고, 상기 스페이서의 10％ 압축 탄성률이 5000N/mm2 이상 15000N/mm2 이하이고, 상기 스페이서의 평균 입자 직경이 10㎛ 이상 200㎛ 이하이다.

Semiconductor structure having lateral through silicon via and manufacturing method thereof

The present invention provides a semiconductor structure having a lateral TSV and a manufacturing method thereof. The semiconductor structure includes a chip having an active side, a back side disposed relatively to the active side, and a lateral side disposed between the active side and the back side. The chip further includes a contact pad, a lateral TSV and a patterned conductive layer. The contact pad is disposed on the active side. The lateral TSV is disposed on the lateral side. The patterned conductive layer is disposed on the active side and is electrically connected to the lateral TSV and the contact pad.

Sensor package and sensor package module including the same

Method for fabricating semiconductor component with adjustment circuit for adjusting physical or electrical characteristics of substrate conductors

A semiconductor component includes adjustment circuitry configured to adjust selected physical and electrical characteristics of the component or elements thereof, and an input/output configuration of the component. The component includes a semiconductor die, a substrate attached to the die, and terminal contacts on the substrate. The adjustment circuitry includes conductors and programmable links, such as fuses or anti-fuses, in electrical communication with the die and the terminal contacts. The adjustment circuit can also include capacitors and inductance conductors. The programmable links can be placed in a selected state (e.g., short or open) using a laser or programming signals. A method for fabricating the component includes the steps of forming the adjustment circuitry, and then placing the programmable links in the selected state to achieve the selected adjustment.

SEMICONDUCTOR ELEMENT AND ELECTRIC DEVICE

In a semiconductor element (20) including a field effect transistor (90), a schottky electrode (9a) and a plurality of bonding pads (12S, 12G), at least one of the plurality of bonding pads (12S, 12G) is disposed so as to be located above the schottky electrode (9a).

Halbleiterbauelemente und Verfahren zur Herstellung von Halbleiterbauelementen

Ein Bauelement enthält ein Halbleitermaterial, das eine erste Hauptoberfläche, eine gegenüberliegende Oberfläche, die der ersten Hauptoberfläche gegenüberliegt, und eine seitliche Oberfläche, die sich von der ersten Hauptoberfläche bis zur gegenüberliegenden Oberfläche erstreckt, aufweist. Das Bauelement enthält weiterhin ein erstes elektrisches Kontaktelement, das auf der ersten Hauptoberfläche des Halbleitermaterials angeordnet ist, und ein Glasmaterial. Das Glasmaterial enthält eine zweite Hauptoberfläche, wobei das Glasmaterial die seitliche Oberfläche des Halbleitermaterials kontaktiert und wobei die erste Hauptoberfläche des Halbleitermaterials und die zweite Hauptoberfläche des Glasmaterials in einer gemeinsamen Ebene angeordnet sind.

Semiconductor laser mounting with intact diffusion barrier layer

A first contact (310) surface of a semiconductor laser chip (302) is formed to a surface roughness selected to have a maximum peak to valley height that is substantially smaller than a diffusion barrier layer thickness. A diffusion barrier layer that includes a non-metallic, electrically-conducting compound and that has the barrier layer thickness is applied to the first contact surface, and the semiconductor laser chip is soldered to a carrier mounting (304) along the first contact surface using a solder composition (306) by heating the soldering composition to less than a threshold temperature at which dissolution of the barrier layer into the soldering composition occurs. Thereby the diffusion barrier remains contiguous. The non-metallic, electrically conducting compound may comprise at least one of titanium nitride, titanium oxy-nitride, tungsten nitride, cerium oxide and cerium gadolinium oxy-nitride ...

WIRE BONDING PROCESS FOR COPPER-METALLIZED INTEGRATED CIRCUITS

도전성 입자, 이방성 도전 재료 및 접속 구조체

... 본 발명은, 도전성 입자에 큰 힘이 부여되어도 도전층에 큰 균열이 발생하기 어려운 도전성 입자, 및 상기 도전성 입자를 사용한 이방성 도전 재료 및 접속 구조체를 제공한다. 본 발명에 관한 도전성 입자 (1)은, 기재 입자 (2)와, 상기 기재 입자 (2)의 표면 (2a) 상에 설치된 구리-주석층 (3)을 구비한다. 구리-주석층 (3)은 구리와 주석의 합금을 포함한다. 구리-주석층 (3) 전체에서의 구리의 함유량은 20 중량％ 초과 75 중량％ 이하이며, 주석의 함유량은 25 중량％ 이상 80 중량％ 미만이다. 본 발명에 관한 이방성 도전 재료는 도전성 입자 (1)과, 결합제 수지를 포함한다. 본 발명에 관한 접속 구조체는 제1 접속 대상 부재와, 제2 접속 대상 부재와, 상기 제1, 제2 접속 대상 부재를 접속하고 있는 접속부를 구비한다. 상기 접속부가 도전성 입자 (1), 또는 도전성 입자 (1)을 포함하는 이방성 도전 재료에 의해 형성되어 있다.

Process for protecting solder joints and structure for alleviating electromigration and joule heating in solder joints

This invention provides a process for protecting solder joints, comprising forming an UBM or pad metallurgy in solder joints and then further forming a small solder bump on UBM or pad metallurgy between substrate and chip. Wherein a material of high electric resistance is coated at the ends of UBM or pad metallurgy where substrate is connected to chip, as to equalize the current distribution of solder bump, therefore the electromigration resistance of solder joints is improved by suppressing the current crowding and joule heating phenomenon.

Integrated high voltage isolation using low value capacitors

High voltage rated isolation capacitors are formed on a face of a primary integrated circuit die. The isolation capacitors AC couple the primary integrated circuit in a first voltage domain to a second integrated circuit in a second voltage domain. The isolation capacitors DC isolate the primary integrated circuit from the second integrated circuit die. Isolated power transfer from the first voltage domain to the second voltage domain is provided through the high voltage rated isolation capacitors with an AC oscillator or PWM generator. The AC oscillator voltage amplitude may be increased for an increase in power through the high voltage rated isolation capacitors, and a larger value capacitor in the second voltage domain may provide for peak current demand from circuits in the second voltage domain.

Methods for manufacturing a display device

Methods for manufacturing a display device are provided. The methods include providing a plurality of light-emitting units and a substrate. The methods also include transferring the light-emitting units to a transfer head. The methods further include attaching at least one of the plurality of light-emitting units on the transfer head to the substrate by a bonding process, wherein the transfer head and the substrate satisfy the following equation during the bonding process:Q≤|∫T1T2A(T)dT−∫T1T3E(T)dT|<0.01,wherein A(T) is the coefficient of thermal expansion of the transfer head, E(T) is the coefficient of thermal expansion of the substrate, T1 is room temperature, T2 is the temperature of the transfer head, and T3 is the temperature of the substrate.

DIE ATTACH SURFACE COPPER LAYER WITH PROTECTIVE LAYER FOR MICROELECTRONIC DEVICES

A microelectronic device is formed by thinning a substrate of the microelectronic device from a die attach surface of the substrate, and forming a copper-containing layer on the die attach surface of the substrate. A protective metal layer is formed on the copper-containing layer. Subsequently, the copper-containing layer is attached to a package member having a package die mount area. The protective metal layer may optionally be removed prior to attaching the copper-containing layer to the package member. Alternatively, the protective metal layer may be left on the copper-containing layer when the copper-containing layer is attached to the package member. A structure formed by the method is also disclosed.

METHOD OF PLANARIZING RECESSES FILLED WITH COPPER

A structure includes a substrate having an upper surface provided with recesses and coated with a continuous barrier layer topped with a continuous copper layer filling at least the recesses. The structure is planarized by a chemical-mechanical polishing of the copper, such a polishing being selective with respect to the barrier layer so that copper remains in the recesses and is coplanar with the upper surface of the substrate. Two such structures are then direct bonded to each other (copper to copper) with opposite areas having a same topology.

Discrete semiconductor device having polymer resin as insulator and method for making the same

Disclosed is a discrete semiconductor device comprising a Si body having an emitter region, a base region and a collector region, an SiO2 layer disposed on the surface of the body, a polyimide resin having a thickness of 5 mu disposed on the SiO2 layer, electrodes penetrating through the SiO2 layer and the polyimide resin thereby contacting the emitter region and the base region, respectively and extending on the surface of the polyimide resin, whereby it becomes easy to bond a wire connected to an external electrode with the electrodes.

CONDUCTIVE PARTICLES AND METHOD AND DEVICE FOR MANUFACTURING THE SAME, ANISOTROPIC CONDUCTIVE ADHESIVE AND CONDUCTIVE CONNECTION STRUCTURE, AND ELECTRONIC CIRCUIT COMPONENTS AND METHOD OF MANUFACTURING THE SAME

An electrical connection is formed by using a double laminated conductive fine particle provided with a conductive metal layer on the surface of a spherical elastic base particle by electroless plating and electroplating and a layer of a low-melting-point metal on the surface of the conductive metal layer and wherein the conductive metal layer comprises a plurality of metal layers.

ELECTRONIC DEVICE

An electronic device is provided in the present disclosure. The electronic device includes a substrate and a light emitting diode. The light emitting diode is bonded to the substrate through a solder alloy. The solder alloy includes tin and a metal element M, and the metal element M is one of the indium and bismuth. The atomic percentage of tin in the sum of tin and the metal element M ranges from 60% to 90% in the solder alloy.

Semiconductor chip and power module, and manufacturing method of the same

A semiconductor chip includes a semiconductor substrate made of SiC, a front surface electrode formed in a principal surface of the semiconductor substrate, and a rear surface electrode (drain electrode) formed in a rear surface of the semiconductor substrate. The front surface electrode is bonded to a wire, and includes an Al alloy film containing a high melting-point metal. The Al alloy film contains a columnar Al crystal which extends along a thickness direction of the Al alloy film, and an intermetallic compound is precipitated therein.

SEMICONDUCTOR DEVICE STRUCTURE INCLUDING A BONDING STRUCTURE

A semiconductor device structure and method for manufacturing the same are provided. The semiconductor device structure includes a substrate, a dielectric structure, a pad, a conductive structure, and a buffer structure. The dielectric structure is disposed on the substrate. The pad is embedded in the dielectric structure. The conductive structure is disposed on the pad. The buffer structure is disposed on the pad and separates the conductive structure from the dielectric structure. A coefficient of thermal expansion (CTE) of the buffer structure ranges between a CTE of the dielectric structure and a CTE of the conductive structure.

SEMICONDUCTOR DEVICE

A semiconductor device has a contact pad formed on a substrate. The contact pad has an exposed surface made of a metal material having low diffusion with respect to a dielectric layer than the metal material of a wiring layer connected to the contact pad. The semiconductor device comprises: a first semiconductor substrate; a first pad formed on the first semiconductor substrate; a second semiconductor substrate; and a second pad formed on the second semiconductor substrate. COPYRIGHT KIPO 2016 ...

LIGHT EMITTING APPARATUS AND METHOD FOR PRODUCING THE SAME

A light emitting apparatus includes a mount substrate; two or more light emitting devices mounted on the mount substrate such that adjacent light emitting devices face each other at lateral surfaces thereof; a light transparent member positioned on upper surfaces of the light emitting devices, the light transparent member having a plate shape and being positioned to receive incident light emitted from the light emitting devices; and a covering member. In a plan view, the light transparent member is larger than each of the light emitting devices. The covering member contains a light reflective material and covers at least a lateral surface of the light transparent member. 1. A light emitting apparatus comprising:a mount substrate;two or more light emitting devices mounted on the mount substrate such that adjacent light emitting devices face each other at lateral surfaces thereof;a light transparent member positioned on upper surfaces of the light emitting devices, the light transparent member having a plate shape and being positioned to receive incident light emitted from the light emitting devices; anda covering member,wherein, in a plan view, the light transparent member is larger than each of the light emitting devices, andwherein the covering member contains a light reflective material and covers at least a lateral surface of the light transparent member.2. The light emitting apparatus according to claim 1 , wherein claim 1 , in a plan view claim 1 , an entirety of each light emitting device is positioned within a periphery of the light transparent member.3. The light emitting apparatus according to claim 1 , wherein claim 1 , in a plan view claim 1 , the light transparent member is larger than two of the light emitting devices.4. The light emitting apparatus according to claim 1 , wherein each of the light emitting devices is attached to the light transparent member via an adhesive material.5. The light emitting apparatus according to claim 1 , wherein the light ...

Adhesive for semiconductor sensor chip mounting, and semiconductor sensor

Provided is an adhesive for semiconductor sensor chip mounting that can reduce detection of noise and can increase heat resistance and thermal cycle resistance characteristics. An adhesive for semiconductor sensor chip mounting according to the present invention is an adhesive used for mounting a semiconductor sensor chip and contains a silicone resin and a spacer, the 10% compressive elasticity modulus of the spacer being 10 N/mm2 or more and 2000 N/mm2 or less, the compression recovery rate of the spacer being 20% or less, and the average particle diameter of the spacer being 10 μm or more and 200 μm or less.

SEMICONDUCTOR DEVICE

... 1414245 Polyimides HITACHI Ltd 17 Oct 1973 [18 Oct 1972] 48406/73 Heading C3R [Also in Division H1] Polyimides of formula wherein m+n=x+y and m, n groups alternate with x, y groups are made by the reaction of diaminoaryl carbonamides, diaminoarylene compounds, and arylene acid dianhydrides. Preferably Ar 1 and Ar 3 are derived from benzene, naphthalene, diphenyl ether, diphenyl sulphone or di(phenoxyphenyl)sulphone, while Ar 2 and Ar 4 are derived from benzene, diphenyl ether or benzophenone. In the embodiment a solution of diaminodiphenyl-ether-3 carbonamide, diaminophenylether, pyromellitic acid dianhydride and benzophenonetetracarboxylic acid dianhydride in a molar ratio of 1 : 9 : 5 : 5 is coated on a silica surface on a semi-conductor device and polymerized in situ.

Semiconductor device having a junction portion contacting a Schottky metal

A semiconductor device according to the present invention includes a first conductive-type SiC semiconductor layer, and a Schottky metal, comprising molybdenum and having a thickness of 10 nm to 150 nm, that contacts the surface of the SiC semiconductor layer. The junction of the SiC semiconductor layer to the Schottky metal has a planar structure, or a structure with recesses and protrusions of equal to or less than 5 nm.

Semiconductor package structure, semiconductor device and method for manufacturing the same

A semiconductor package structure includes a substrate, at least one first semiconductor element, a heat dissipation structure and an insulation layer. The at least one first semiconductor element is attached to the substrate, and has a first surface and a second surface opposite to the first surface. The first surface of the at least one first semiconductor element faces the substrate. The heat dissipation structure is disposed on the second surface of the at least one first semiconductor element. The insulation layer is disposed on the heat dissipation structure, and defines a plurality of openings extending through the insulation layer and exposing a plurality of exposed portions of the heat dissipation structure.

Semiconductor device with a connection pad in a substrate and method for production thereof

A semiconductor device with a connection pad in a substrate, the connection pad having an exposed surface made of a metallic material that diffuses less readily into a dielectric layer than does a metal of a wiring layer connected thereto.

SEMICONDUCTOR LASER MOUNTING WITH INTACT DIFFUSION BARRIER LAYER

A first contact surface of a semiconductor laser chip can be formed to a target surface roughness selected to have a maximum peak to valley height that is substantially smaller than a barrier layer thickness. A barrier layer that includes a non-metallic, electrically-conducting compound and that has the barrier layer thickness can be applied to the first contact surface, and the semiconductor laser chip can be soldered to a carrier mounting along the first contact surface using a solder composition by heating the soldering composition to less than a threshold temperature at which dissolution of the barrier layer into the soldering composition occurs. Related systems, methods, articles of manufacture, and the like are also described.

Semiconductor device having a junction portion contacting a Schottky metal

A semiconductor device according to the present invention includes a first conductive-type SiC semiconductor layer, and a Schottky metal, comprising molybdenum and having a thickness of 10 nm to 150 nm, that contacts the surface of the SiC semiconductor layer. The junction of the SiC semiconductor layer to the Schottky metal has a planar structure, or a structure with recesses and protrusions of equal to or less than 5 nm.

Conductive material, connection structure body, and connection structure body production method

Provided is a conductive material that allows solder on conductive particles to be disposed efficiently on an electrode even after the conductive material has been left standing for a set period of time, and is such that the yellowing of the conductive material can be sufficiently suppressed during heating. This conductive material contains a plurality of conductive particles having solder on the outer surface portion of a conductive portion, a curable compound, and a boron trifluoride complex.

SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCTION OF SEMICONDUCTOR DEVICE

A semiconductor device with a connection pad in a substrate, the connection pad having an exposed surface made of a metallic material that diffuses less readily into a dielectric layer than does a metal of a wiring layer connected thereto.

Semiconductor laser mounting with intact diffusion barrier layer

A first contact surface of a semiconductor laser chip can be formed to a target surface roughness selected to have a maximum peak to valley height that is substantially smaller than a barrier layer thickness. A barrier layer that includes a non-metallic, electrically-conducting compound and that has the barrier layer thickness can be applied to the first contact surface, and the semiconductor laser chip can be soldered to a carrier mounting along the first contact surface using a solder composition by heating the soldering composition to less than a threshold temperature at which dissolution of the barrier layer into the soldering composition occurs. Related systems, methods, articles of manufacture, and the like are also described.

Method of Forming an Interconnection between an Electric Component and an Electronic Component

A method of forming an interconnection includes: providing an electronic component having a first main face and a first metallic layer disposed on the first main face; providing an electric component having a second main face and a second metallic layer disposed on the second main face, at least one of the first or second metallic layers including an oxide layer provided on a main face thereof; disposing a reducing agent on one or both of the electronic component and the electric component such that the reducing agent is enabled to remove the oxide layer; and connecting the electronic component to the electric component by directly connecting the first metallic layer of the electronic component with the second metallic layer of the electric component by applying pressure and heat.

Interconnection Structure with Confinement Layer

An interconnection structure and method disclosed for providing an interconnection structure that includes conductive features having reduced topographic variations. The interconnection structure includes a contact pad disposed over a substrate. The contact pad includes a first layer of a first conductive material and a second layer of a second conductive material over the first layer. The first conductive material and the second conductive material are made of substantially the same material and have a first average grain size and a second average grain size that is smaller than the first average grain size. The interconnection structure also includes a passivation layer covering the substrate and the contact pad, and the passivation layer has an opening exposing the contact pad.

Manufacturing method of residue-free wafer

The invention relates to a manufacturing method of residue-free wafer. Organic-adhesive tapes are often used to secure and protect the bumps during wafer processing after bump formation. While residual organic-adhesive tape may remain on the wafer after tape de-lamination, applying a bump template layer on the bumps before laminating the tape allows any residue to be removed afterwards and results in a residue-free wafer.

Wire welding tech. for copper metallized integrated circuit

CONDUCTIVE PARTICLES, CONDUCTIVE MATERIAL AND CONNECTION STRUCTURE

Glass carrier with embedded semiconductor device and metal layers on the top surface

A device includes a semiconductor material having a first main surface, an opposite surface opposite to the first main surface and a side surface extending from the first main surface to the opposite surface. The device further includes a first electrical contact element arranged on the first main surface of the semiconductor material and a glass material. The glass material includes a second main surface wherein the glass material contacts the side surface of the semiconductor material and wherein the first main surface of the semiconductor material and the second main surface of the glass material are arranged in a common plane.

Microelectronic package interconnect and method of fabrication thereof

A method of interconnecting and an interconnect is provided to connect a first component and a second component of an integrated circuit. The interconnect includes a plurality of Carbon Nanotubes (CNTs), which provide a conducting path between the first component and the second component. The interconnect further includes a passivation layer to fill the gaps between adjacent CNTs. A method of producing Anisotropic Conductive Film (ACF) and an ACF is provided. The ACF includes a plurality of CNTs, which provide a conducting path between a first side of the ACF and a second side of the ACF. The sides of the ACF can also include a conductive curable adhesive layer. In an embodiment, the conductive curable adhesive layer can incorporate a B-stage cross-linkable polymer and silver particles.

Integrated high voltage isolation using low value capacitors

High voltage rated isolation capacitors are formed on a face of a primary integrated circuit die. The isolation capacitors AC couple the primary integrated circuit in a first voltage domain to a second integrated circuit in a second voltage domain. The isolation capacitors DC isolate the primary integrated circuit from the second integrated circuit die. Isolated power transfer from the first voltage domain to the second voltage domain is provided through the high voltage rated isolation capacitors with an AC oscillator or PWM generator. The AC oscillator voltage amplitude may be increased for an increase in power through the high voltage rated isolation capacitors, and a larger value capacitor in the second voltage domain may provide for peak current demand from circuits in the second voltage domain.

DISPLAY DEVICE

A display device includes a circuit substrate, a plurality of pad sets and a plurality of light-emitting elements. The plurality of pad sets is disposed on the circuit substrate, and each pad set includes a first pad and a second pad surrounding the first pad. The plurality of light-emitting elements is disposed above the circuit substrate, and each light-emitting element includes a first electrode, a second electrode and a light-emitting stack between the first electrode and the second electrode, wherein the first electrode is electrically connected to the first pad, the second electrode is electrically connected to the second pad, and an orthographic projection of the second electrode on the circuit substrate is overlapped with an orthographic projection of the first pad on the circuit substrate.

반도체 센서 칩 실장용 접착제 및 반도체 센서

... 노이즈의 감지를 저감시키고, 또한 내열성 및 내냉열 사이클 특성을 높일 수 있는 반도체 센서 칩 실장용 접착제를 제공한다. 본 발명에 따른 반도체 센서 칩 실장용 접착제는, 반도체 센서 칩의 실장에 사용되는 접착제로서, 실리콘 수지와 스페이서를 포함하고, 상기 스페이서의 10％ 압축 탄성률이 10N/mm2 이상 2000N/mm2 이하이고, 상기 스페이서의 압축 회복률이 20％ 이하이고, 상기 스페이서의 평균 입자 직경이 10㎛ 이상 200㎛ 이하이다.

Method for manufacture of integrated circuit package system with protected conductive layers for pads

A method for manufacture of an integrated circuit package system includes: providing an integrated circuit die having a contact pad; forming a protection cover over the contact pad; forming a passivation layer having a first opening over the protection cover with the first opening exposing the protection cover; developing a conductive layer over the passivation layer; forming a pad opening in the protection cover for exposing the contact pad having the conductive layer partially removed; and an interconnect directly on the contact pad and only adjacent to the protection cover and the passivation layer.

Conductive connection structure with stress reduction arrangement for a semiconductor device, and related fabrication method

A semiconductor device disclosed herein includes a conductive connection structure having a stepped profile that serves as a stress relief feature. The conductive connection structure includes a stress buffer arrangement for a contact pad. The stress buffer arrangement has a stepped via that terminates at the contact pad, and the stepped via has a plurality of inwardly sloped and concentric sections in a stacked orientation. The connection structure also includes underbump metallization overlying at least a portion of the contact pad and lining the stepped via, and a conductive connection element coupled to the underbump metallization. The conductive connection element fills the lined recess.

Process for assembling two parts of a circuit

A three-dimensional integrated structure is fabricated by assembling at least two parts together, wherein each part contains at least one metallic line covered with a covering region and having a free side. A cavity is formed in the covering region of each part, that cavity opening onto the metallic line. The two parts are joined together with the free sides facing each other and the cavities in each covering region aligned with each other. The metallic lines are then electrically joined to each other through an electromigration of the metal within at least one of the metallic lines, the electromigrated material filling the aligned cavities.

Semiconductor device having pad structure with stress buffer layer

A semiconductor device has a pad structure with a ring-shaped stress buffer layer between a metal pad and an under-bump metallization (UBM) layer. The stress buffer layer is formed of a dielectric layer with a dielectric constant less than 3.5, a polymer layer, or an aluminum layer. The stress buffer layer is a circular ring, a square ring, an octagonal ring, or any other geometric ring.

Contact pad

The present disclosure relates to forming multi-layered contact pads for a semiconductor device, wherein the various layers of the contact pad are formed using one or more thin-film deposition processes, such as an evaporation process. Each contact pad includes an adhesion layer, which is formed over the device structure for the semiconductor device; a titanium nitride (TiN) barrier layer, which is formed over the adhesion layer; and an overlay layer, which is formed over the barrier layer. At least the titanium nitride (TiN) barrier layer is formed using an evaporation process.

Package carrier

A package carrier including a substrate, at least an under bump metallurgic (UBM) layer and at least a conductive bump is provided. The substrate has a conductive structure and at least a pad connected with the conductive structure. A region of the pad connected with the conductive structure is a signal source region. The UBM layer is disposed on the pad and includes a first conductive pattern and a second conductive pattern. A side wall of the second conductive pattern is directly connected to a side wall of the first conductive pattern, and the second conductive pattern is disposed close to the signal source region. The conductivity of the second conductive pattern is smaller than the conductivity of the first conductive pattern. The conductive bump is disposed on the UBM layer.

Solder ball contact susceptible to lower stress

A solder ball contact and a method of making a solder ball contact includes: a first insulating layer with a via formed on an integrated circuit (IC) chip and a metal pad; an under bump metallurgy (UBM) structure disposed within the via and on a portion of the first insulating layer, surrounding the via; a second insulating layer formed on an upper surface of an outer portion of the UBM structure that is centered on the via; and a solder ball that fills the via and is disposed above an upper surface of an inner portion of the UBM structure that contacts the via, in which the UBM structure that underlies the solder ball is of a greater diameter than the solder ball.

Methods and structures for forming integrated semiconductor structures

The invention provides methods and structures for fabricating a semiconductor structure and particularly for forming a semiconductor structure with improved planarity for achieving a bonded semiconductor structure comprising a processed semiconductor structure and a number of bonded semiconductor layers. Methods for forming semiconductor structures include forming a dielectric layer over a non-planar surface of a processed semiconductor structure, planarizing a surface of the dielectric layer on a side thereof opposite the processed semiconductor structure, and attaching a semiconductor structure to the planarized surface of the dielectric layer. Semiconductor structures include a dielectric layer overlaying a non-planar surface of a processed semiconductor structure, and a masking layer overlaying the dielectric layer on a side thereof opposite the processed semiconductor structure. The masking layer includes a plurality of mask openings over conductive regions of the non-planar surface of the processed semiconductor structure.

Semiconductor laser mounting with intact diffusion barrier layer

A first contact surface of a semiconductor laser chip can be formed to a target surface roughness selected to have a maximum peak to valley height that is substantially smaller than a barrier layer thickness. A barrier layer that includes a non-metallic, electrically-conducting compound and that has the barrier layer thickness can be applied to the first contact surface, and the semiconductor laser chip can be soldered to a carrier mounting along the first contact surface using a solder composition by heating the soldering composition to less than a threshold temperature at which dissolution of the barrier layer into the soldering composition occurs. Related systems, methods, articles of manufacture, and the like are also described.

Multi-chip semiconductor package and method of fabricating the same

A first semiconductor chip having a first projection electrode formed on an upper surface thereof is prepared. A second semiconductor chip having a second projection electrode is mounted on the first semiconductor chip to expose the first projection electrode. An insulating film is formed between the first projection electrode and the second projection electrode. A groove is formed in the insulating film. An interconnection configured to fill an inside of the groove and connected to the first projection electrode and the second projection electrode is formed.

On-Chip Heat Spreader

A three dimensional (3D) stacked chip structure with chips having on-chip heat spreader and method of forming are described. A 3D stacked chip structure comprises a first die having a first substrate with a dielectric layer formed on a front surface. One or more bonding pads and a heat spreader may be simultaneously formed in the dielectric layer. The first die is bonded with corresponding bond pads on a surface of a second die to form a stacked chip structure. Heat generated in the stacked chip structure may be diffused to the edges of the stacked chip structure through the heat spreader.

Methods of manufacturing stress buffer structures in a mounting structure of a semiconductor device

A mounting structure for a semiconductor device is formed to include a stepwise stress buffer layer under a stepwise UBM structure.

Semiconductor Device and Method of Forming RDL Under Bump for Electrical Connection to Enclosed Bump

A semiconductor device has a semiconductor wafer with a plurality of semiconductor die. A first conductive layer is formed over a surface of the wafer. A first insulating layer is formed over the surface of the wafer and first conductive layer. A second conductive layer has first and second segments formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and second conductive layer. A UBM layer is formed over the second insulating layer and the first segment of the second conductive layer. A first bump is formed over the UBM layer. The first bump is electrically connected to the second segment and electrically isolated from the first segment of the second conductive layer. A second bump is formed over the surface of the wafer and electrically connected to the first segment of the second conductive layer.

Wafer Level Semiconductor Package

There are disclosed herein various implementations of improved wafer level semiconductor packages. One exemplary implementation comprises forming a post-fabrication redistribution layer (post-Fab RDL) between first and second dielectric layers affixed over a surface of a wafer, and forming a window for receiving an electrical contact body in the second dielectric layer, the window exposing the post-Fab RDL. At least one of the first and second dielectric layers is a pre-formed dielectric layer, which may be affixed over the surface of the wafer using a lamination process. In one implementation, the window is formed using a direct laser ablation process.

Semiconductor device and method for production of semiconductor device

A semiconductor device with a connection pad in a substrate, the connection pad having an exposed surface made of a metallic material that diffuses less readily into a dielectric layer than does a metal of a wiring layer connected thereto.

Bump structure and electronic packaging solder joint structure and fabricating method thereof

A bump structure includes a substrate, a pad, an electrode and a protruding electrode. The pad is disposed on the substrate. The electrode is formed by a first metal material and disposed on the pad. The protruding electrode is formed by a second metal material and disposed on the electrode, wherein a cross-sectional area of the protruding electrode is less than a cross-sectional area of the electrode.

Via plugs

The present disclosure relates to providing via plugs in vias of a semiconductor material. The via plugs may be formed of a polymer, such as a polyimide, that can withstand subsequent soldering and operating temperatures. The via plugs effectively fill the vias to prevent the vias from being filled substantially with solder during a subsequent soldering processes.

Bonded processed semiconductor structures and carriers

Methods of fabricating semiconductor structures include implanting atom species into a carrier die or wafer to form a weakened region within the carrier die or wafer, and bonding the carrier die or wafer to a semiconductor structure. The semiconductor structure may be processed while using the carrier die or wafer to handle the semiconductor structure. The semiconductor structure may be bonded to another semiconductor structure, and the carrier die or wafer may be divided along the weakened region therein. Bonded semiconductor structures are fabricated using such methods.

Semiconductor Device and Method of Forming Guard Ring Around Conductive TSV Through Semiconductor Wafer

A semiconductor device has a plurality of conductive vias formed into a semiconductor wafer. An insulating lining is formed around the conductive vias and a conductive layer is formed over the insulating lining. A portion of the semiconductor wafer is removed so the conductive vias extend above a surface of the semiconductor wafer. A first insulating layer is formed over the surface of the semiconductor wafer and conductive vias. A first portion of the first insulating layer is removed and a second portion of the first insulating layer remains as guard rings around the conductive vias. A conductive layer is formed over the conductive vias. A second insulating layer is formed over the surface of the semiconductor wafer, guard rings, and conductive vias. A portion of the second insulating layer is removed to expose the conductive vias and a portion of the guard rings.

Semiconductor integrated circuit device

In semiconductor integrated circuit devices for vehicle use, an aluminum pad on a semiconductor chip and an external device are coupled to each other by wire bonding using a gold wire for the convenience of mounting. Such a semiconductor integrated circuit device, however, causes a connection failure due to the interaction between aluminum and gold in use for a long time at a relatively high temperature (about 150 degrees C.). A semiconductor integrated circuit device can include a semiconductor chip as a part of the device, an electrolytic gold plated surface film (gold-based metal plated film) provided over an aluminum-based bonding pad on a semiconductor chip via a barrier metal film, and a gold bonding wire (gold-based bonding wire) for interconnection between the plated surface film and an external lead provided over a wiring board (wiring substrate).

Packaging Structures and Methods with a Metal Pillar

A package component is free from active devices therein. The package component includes a substrate, a through-via in the substrate, a top dielectric layer over the substrate, and a metal pillar having a top surface over a top surface of the top dielectric layer. The metal pillar is electrically coupled to the through-via. A diffusion barrier is over the top surface of the metal pillar. A solder cap is disposed over the diffusion barrier.

Power MOSFET Having Selectively Silvered Pads for Clip and Bond Wire Attach

A packaged power field effect transistor device includes a power field effect transistor die, a DBA substrate, a clip, a wire bond, leads, and an amount of plastic encapsulant. The top of the DBA has a plurality of metal plate islands. A sintered silver feature is disposed on one of the islands. A silvered backside of the die is directly bonded to the sintered silver structure of the DBA. The upper surface of the die includes a first aluminum pad (a source pad) and a second aluminum pad (a gate pad). A sintered silver structure is disposed on the first aluminum pad, but there is no sintered silver structure disposed on the second aluminum pad. A high current clip is attached via soft solder to the sintered silver structure on the first aluminum pad (the source pad). A bond wire is ultrasonically welded to the second aluminum pad (gate pad).

Semiconductor device including a buffer layer structure for reducing stress

A semiconductor device includes a semiconductor chip, wiring that is included in the semiconductor chip and has a coupling part between parts with different widths, a pad being formed above the wiring and in a position overlapping the coupling part, a bump being formed on the pad, a buffer layer being formed in a position between the coupling part and the pad so as to cover the entire coupling part, and inorganic insulating layers being formed between the wiring and the buffer layer and between the buffer layer and the pad, respectively. The buffer layer is made of a material other than resin and softer than the inorganic insulating layer

Semiconductor device

A semiconductor device includes a protective layer, a redistribution pattern, a pad pattern and an insulating polymer layer. The protective layer may be formed on a substrate. The redistribution pattern may be formed on the protective layer. An upper surface of the redistribution may be substantially flat. The pad pattern may be formed directly on the redistribution pattern. An upper surface of the pad pattern may be substantially flat. The insulating polymer layer may be formed on the redistribution pattern and the pad pattern. An upper surface of the insulating polymer layer may be lower than the upper surface of the pad pattern. The semiconductor device may have a high reliability.

SEMICONDUCTOR DEVICE, MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, CIRCUIT SUBSTRATE, AND ELECTRONIC APPARATUS

A semiconductor device includes an integrated circuit that is disposed at a first face side of a semiconductor substrate, the semiconductor substrate having a first face and a second face, the second face opposing the first face, the semiconductor substrate having a through hole from the first face to the second face; an external connection terminal that is disposed at the first face side; a conductive portion that is disposed in the through hole, the conductive portion being electrically connected to the external connection terminal; and an electronic element that is disposed at a second face side. 1. A device comprising:a semiconductor substrate including a first face and a second face on a side opposite to the first face;a foundation layer formed on the first face of the semiconductor substrate;a first electrode formed on the foundation layer;a second electrode formed on the foundation layer;an integrated circuit comprising at least two interconnected semiconductor devices, the at least two interconnected semiconductor devices formed on the first face of the semiconductor substrate, and the integrated circuit being electrically connected to the first electrode and the second electrode;a groove portion formed through the semiconductor substrate;an insulating film formed on a side wall of the groove portion;a conductive portion formed inside the groove portion on the insulating film and electrically connected to the second electrode;a first insulation layer formed on the foundation layer;a first interconnection formed on the first insulation layer, the first interconnection being electrically connected to the first electrode;a second insulation layer formed on the first interconnection and the first insulation layer;a second interconnection formed on the second insulation layer, the second interconnection being electrically connected to the first interconnection; anda third insulation layer formed on the second interconnection and the second insulation layer; ...

Semiconductor structure and method of forming the same

The present invention relates to a semiconductor structure and method of forming the same. The semiconductor structure includes a first substrate, a first adhesive/bonding stack on the surface of first substrate, wherein the first adhesive/bonding stack includes at least one first adhesive layer and at least one first bonding layer. The material of first bonding layer includes dielectrics such as silicon, nitrogen and carbon, the material of first adhesive layer includes dielectrics such as silicon and nitrogen, and the first adhesive/bonding stack of semiconductor structure is provided with higher bonding force in bonding process.

Heat Spreading Device and Method

In an embodiment, a device includes: an integrated circuit die having a first side and a second side opposite the first side; a die stack on the first side of the integrated circuit die; a dummy semiconductor feature on the first side of the integrated circuit die, the dummy semiconductor feature laterally surrounding the die stack, the dummy semiconductor feature electrically isolated from the die stack and the integrated circuit die; a first adhesive disposed between the die stack and the dummy semiconductor feature; and a plurality of conductive connectors on the second side of the integrated circuit die.

Metal pad modification

The present invention provides a structure. In an exemplary embodiment, the structure includes a base material, at least one metal pad, where a first surface of the metal pad is in contact with the base material, and a metal pedestal, where the metal pedestal is in contact with the metal pad, where a radial alignment of the metal pad is shifted by an offset distance, with respect to the metal pedestal, such that the metal pad is shifted towards a center axis of the base material, where a first dimension of the metal pad is smaller than a second dimension of the metal pad, where the second dimension is orthogonal to a line running from a center of the metal pad to the center axis of the base material, where the first dimension is parallel to the line.

SUPERCONDUCTING BUMP BONDS

A device includes a first chip having a first circuit element, a first interconnect pad in electrical contact with the first circuit element, and a barrier layer on the first interconnect pad, a superconducting bump bond on the barrier layer, and a second chip joined to the first chip by the superconducting bump bond, the second chip having a first quantum circuit element, in which the superconducting bump bond provides an electrical connection between the first circuit element and the first quantum circuit element. 18.-. (canceled)9. A method comprising:providing a first chip comprising a first circuit element;forming a first aluminum interconnect pad on a first surface of the first chip so that the first aluminum interconnect pad is electrically connected to the first circuit element;forming a first titanium nitride barrier layer on the first aluminum interconnect pad;providing a second chip comprising a second circuit element;forming an indium bump bond; andjoining the first chip to the second chip with the indium bump bond so that the first circuit element is electrically connected to the second circuit element.10. (canceled)11. The method of claim 9 , further comprising removing a native oxide from the first aluminum interconnect pad prior to forming the first titanium nitride barrier layer.12. The method of claim 11 , wherein removing the native oxide comprises ion milling a surface of the first aluminum interconnect pad.13. The method of claim 9 , wherein forming the first titanium nitride barrier comprises reactive sputtering titanium nitride on the first aluminum interconnect pad.14. The method of claim 9 , further comprising ion milling a surface of the first titanium nitride barrier layer prior to joining the first chip to the second chip.15. The method of claim 9 , further comprising exposing a surface of the indium bump bond to a Hplasma.16. The method of claim 9 , further comprising:forming a second aluminum interconnect pad on a first surface of the ...

SUPERCONDUCTING BUMP BONDS

A device includes a first chip having a first circuit element, a first interconnect pad in electrical contact with the first circuit element, and a barrier layer on the first interconnect pad, a superconducting bump bond on the barrier layer, and a second chip joined to the first chip by the superconducting bump bond, the second chip having a first quantum circuit element, in which the superconducting bump bond provides an electrical connection between the first circuit element and the first quantum circuit element. 1. A device comprising:a first chip comprising a first circuit element, a first interconnect pad in electrical contact with the first circuit element, and a barrier layer on the first interconnect pad, wherein the barrier layer is titanium nitride;a superconducting bump bond on the barrier layer; anda second chip joined to the first chip by the superconducting bump bond, the second chip comprising a first quantum circuit element, wherein the superconducting bump bond provides an electrical connection between the first circuit element and the first quantum circuit element.2. The device of claim 1 , wherein the first interconnect pad is aluminum.3. The device of claim 1 , wherein the superconducting bump bond is indium.4. The device of claim 1 , wherein the first circuit element comprises a rapid single flux quantum (RSFQ) device.5. The device of claim 1 , wherein the first circuit element comprises a second quantum circuit element.6. The device of claim 1 , wherein at least one of the first chip and the second chip comprises a silicon substrate.7. The device of claim 1 , wherein at least one of the first chip and the second chip comprises a sapphire substrate.8. The device of claim 1 , wherein a first surface of the first chip is spaced apart from and faces a first surface of the second chip to form a gap. This application claims priority to and is a divisional of U.S. patent application Ser. No. 16/062,064, filed on Jun. 13, 2018, which claims priority ...

Unified semiconductor devices having processor and heterogeneous memories and methods for forming the same

Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a semiconductor device includes NAND memory cells and a first bonding layer including first bonding contacts. The semiconductor device also includes a second semiconductor structure including DRAM cells and a second bonding layer including second bonding contacts. The semiconductor device also includes a third semiconductor structure including a processor, SRAM cells, and a third bonding layer including third bonding contacts. The semiconductor device further includes a first bonding interface between the first and third bonding layers, and a second bonding interface between the second and third bonding layers. The first bonding contacts are in contact with a first set of the third bonding contacts at the first bonding interface. The second bonding contacts are in contact with a second set of the third bonding contacts at the second bonding interface. The first and second bonding interfaces are in a same plane.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

An improvement is achieved in the reliability of a semiconductor device. Over a semiconductor substrate, an interlayer insulating film is formed and, over the interlayer insulating film, a pad is formed. Over the interlayer insulating film, an insulating film is formed so as to cover the pad. In the insulating film, an opening is formed to expose a part of the pad. The pad is a pad to which a copper wire is to be electrically coupled and which includes an Al-containing conductive film containing aluminum as a main component. Over the Al-containing conductive film in a region overlapping the opening in plan view, a laminated film including a barrier conductor film, and a metal film over the barrier conductor film is formed. The metal film is in an uppermost layer. The barrier conductor film is a single-layer film or a laminated film including one or more layers of films selected from the group consisting of a Ti film, a TiN film, a Ta film, a TaN film, a W film, a WN film, a TiW film, and a TaW film. The metal film is made of one or more metals selected from the group consisting of Pd, Au, Ru, Rh, Pt, and Ir. 1. A semiconductor device , comprising:a semiconductor substrate;a first insulating film formed over the semiconductor substrate;a pad formed over the first insulating film;a second insulating film formed over the first insulating film so as to cover the pad; andan opening formed in the second insulating film to expose a part of the pad,wherein the pad is a pad to which a copper wire is to be electrically coupled and which includes an Al-containing conductive film containing aluminum as a main component,wherein, over the Al-containing conductive film in a region overlapping the opening in plan view, a first laminated film including a first conductor film, and a second conductor film over the first conductor film is formed,wherein the second conductor film is in an uppermost layer of the first laminated film,wherein the first conductor film is a single-layer film ...

Package assembly

In some embodiments, the present disclosure relates to a package assembly having a bump on a first substrate. A molding compound is on the first substrate and contacts sidewalls of the bump. A no-flow underfill layer is on a conductive region of a second substrate. The no-flow underfill layer and the conductive region contact the bump. A mask layer is arranged on the second substrate and laterally surrounds the no-flow underfill layer. The no-flow underfill layer contacts the substrate between the conductive region and the mask layer.

3D Integrated Circuit and Methods of Forming the Same

An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer. 1. A semiconductor device comprising:a first contact extending away from a planar surface of a substrate, the first contact having straight sidewalls;a first dielectric layer surrounding a first portion of the first contact, the first dielectric layer being separated from the planar surface;a second dielectric layer surrounding a second portion of the first contact, wherein the second dielectric layer has a larger porosity than the first dielectric layer and wherein the first dielectric layer is located between the second dielectric layer and the substrate; anda dielectric barrier layer surrounding a third portion of the first contact, the dielectric barrier layer sharing a planar surface with the first contact.2. The semiconductor device of claim 1 , wherein the straight sidewalls are perpendicular to a major surface of the substrate.3. The semiconductor device of claim 1 , wherein the straight sidewalls are tilted with respect to a major surface of the substrate.4. The semiconductor device of claim 1 , wherein the first dielectric layer has a porosity of less than about 5%.5. The semiconductor device of claim 4 , wherein the first dielectric layer comprises un-doped silicate glass (USG).6. The semiconductor device of claim 1 , wherein the second dielectric layer ...

Semiconductor Device and Method

In an embodiment, a device includes: a first reflective structure including first doped layers of a semiconductive material, alternating ones of the first doped layers being doped with a p-type dopant; a second reflective structure including second doped layers of the semiconductive material, alternating ones of the second doped layers being doped with a n-type dopant; an emitting semiconductor region disposed between the first reflective structure and the second reflective structure; a contact pad on the second reflective structure, a work function of the contact pad being less than a work function of the second reflective structure; a bonding layer on the contact pad, a work function of the bonding layer being greater than the work function of the second reflective structure; and a conductive connector on the bonding layer.

Semiconductor device with recessed pad layer and method for fabricating the same

The present application discloses a semiconductor device with a recessed pad layer and a method for fabricating the semiconductor device. The semiconductor device includes a first die, a second die positioned on the first die, a pad layer positioned in the first die, a filler layer including an upper portion and a recessed portion, and a barrier layer positioned between the second die and the upper portion of the filler layer, between the first die and the upper portion of the filler layer, and between the pad layer and the recessed portion of the filler layer. The upper portion of the filler layer is positioned along the second die and the first die, and the recessed portion of the filler layer is extending from the upper portion and positioned in the pad layer.

SURFACE FINISHES FOR INTERCONNECTION PADS IN MICROELECTRONIC STRUCTURES

A surface finish may be formed in a microelectronic structure, wherein the surface finish may include a multilayer interlayer structure. Thus, needed characteristics, such as compliance and electro-migration resistance, of the interlayer structure may be satisfied by different material layers, rather attempting to achieve these characteristics with a single layer. In one embodiment, the multilayer interlayer structure may comprises a two-layer structure, wherein a first layer is formed proximate a solder interconnect and comprises a material which forms a ductile joint with the solder interconnect, and a second layer comprising a material having strong electro-migration resistance formed between the first layer and an interconnection pad. In a further embodiment, third layer may be formed adjacent the interconnection pad comprising a material which forms a ductile joint with the interconnection pad. 125.-. (canceled)26. A microelectronic structure , comprising:an interconnection pad;a surface finish on the interconnection pad, wherein the surface finish comprises a multilayer interlayer structure including at least one ductile layer and at least one electro-migration resistant layer; anda solder interconnect on the surface finish.27. The microelectronic structure of claim 26 , wherein the at least one ductile layer comprises a nickel material having phosphorus content of between about 2% and 10% by weight.28. The microelectronic structure of claim 26 , wherein the at least one electro-migration resistant layer comprises a nickel material having phosphorus content of between about 11% and 20% by weight.29. The microelectronic structure of claim 26 , wherein the at least one electro-migration resistant layer comprises a high atomic weight metal.30. The microelectronic structure of claim 29 , wherein the high atomic weight metal is selected from the group consisting of nickel claim 29 , cobalt claim 29 , and iron.31. The microelectronic structure of claim 26 , wherein ...

SEMICONDUCTOR DEVICE INCLUDING A BUFFER LAYER STRUCTURE FOR REDUCING STRESS

A semiconductor device includes a semiconductor chip, wiring that is included in the semiconductor chip and his a coupling part between parts with different widths, a pad being formed above the wiring and in a position overlapping the coupling part, a bump being formed on the pad, a buffer layer being formed in a position between the coupling part and the pad so as to cover the entire couple part, and inorganic insulating layers being formed between the wiring and the buffer layer and between the buffer layer and the pad, respectively. The buffer layer is made of a material other than resin and softer than the inorganic insulating layer. 1. A semiconductor device comprising: a pad;', 'a wiring made of polysilicon, first and second portions of the wiring having different widths and being connected together at a junction;', 'a conductive material between the junction and the pad; and', 'a diffusion layer, at least a part of which is overlapped with the second portion of the wiring,', 'wherein the pad is above the junction, the diffusion layer is below the wiring, and the conductive material overlaps the pad, the junction, and the diffusion layer in a plan view from above the pad., 'a semiconductor chip having2. The semiconductor device according to claim I , wherein:the first portion of the wiring is disposed along a first direction; andthe second portion of the wiring is disposed along a second direction orthogonal to the first direction.3. The semiconductor device according to claim 2 , wherein:a third portion of the wiring, which has a width different than the width of the first portion of the wiring, is connected to the first portion at a second junction; andthe third portion is disposed along the second direction.4. The semiconductor device according to claim 2 , whereinthe width of the first portion is wider than the width of the second portion.5. The semiconductor device according to claim 3 , whereinthe width of the first portion is width than the widths of ...

CONDUCTIVE BUMP AND ELECTROLESS Pt PLATING BATH

The present invention provides a bump that can prevent diffusion of a metal used as a base conductive layer of the bump into a surface of an Au layer or an Ag layer. A conductive bump of the present invention is a conductive bump formed on a substrate. The conductive bump comprises, at least in order from the substrate: a base conductive layer; a Pd layer; a Pt layer; and an Au layer or an Ag layer having directly contact with the Pd layer, wherein a diameter of the conductive bump is 20 μm or less.

Semiconductor devices having crack-inhibiting structures

Semiconductor devices having metallization structures including crack-inhibiting structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a metallization structure formed over a semiconductor substrate. The metallization structure can include a bond pad electrically coupled to the semiconductor substrate via one or more layers of conductive material, and an insulating material—such as a low-κ dielectric material—at least partially around the conductive material. The metallization structure can further include a crack-inhibiting structure positioned beneath the bond pad between the bond pad and the semiconductor substrate. The crack-inhibiting structure can include (a) a metal lattice extending laterally between the bond pad and the semiconductor substrate and (b) barrier members extending vertically between the metal lattice and the bond pad.

Semiconductor devices and processing methods

Various embodiments provide a semiconductor device, including a final metal layer having a top side and at least one sidewall; and a passivation layer disposed over at least part of at least one of the top side and the at least one sidewall of the final metal layer; wherein the passivation layer has a substantially uniform thickness.

A 3d semiconductor device and system

A 3D semiconductor device, the device including: a first crystalline silicon layer including a plurality of first transistors; a first metal layer interconnecting the first transistors, a portion of the first transistors forming a plurality of first logic gates; a first array of memory cells including second transistors; a second metal layer overlying the first and second transistors; a second crystalline silicon layer overlaying the second metal layer and the second crystalline silicon layer including a plurality of third transistors; a third metal layer interconnecting the third transistors, a portion of the third transistors forming a plurality of second logic gates; a second array of memory cells including fourth transistors and overlaying the second crystalline silicon layer; a fourth metal layer overlying the third and fourth transistors, where at least one of the fourth transistors is overlaying at least another one of the fourth transistors such that they are self-aligned, having been processed following the same lithography step, where the second array of memory cells include NAND flash type memory cells.

SEMICONDUCTOR DEVICES, SEMICONDUCTOR PACKAGES, AND METHODS OF MANUFACTURING THE SEMICONDUCTOR DEVICES

A semiconductor device includes a conductive component on a substrate, a passivation layer on the substrate and including an opening that exposes at least a portion of the conductive component, and a pad structure in the opening and located on the passivation layer, the pad structure being electrically connected to the conductive component. The pad structure includes a lower conductive layer conformally extending on an inner sidewall of the opening, the lower conductive layer including a conductive barrier layer, a first seed layer, an etch stop layer, and a second seed layer that are sequentially stacked, a first pad layer on the lower conductive layer and at least partially filling the opening, and a second pad layer on the first pad layer and being in contact with a peripheral portion of the lower conductive layer located on the top surface of the passivation layer. 1. A semiconductor device comprising:a conductive component on a substrate;a passivation layer on the substrate and including an opening therein, wherein the opening exposes at least a portion of the conductive component; and a lower conductive layer conformally extending on an inner sidewall of the opening and on a top surface of the passivation layer around the opening, the lower conductive layer including a conductive barrier layer, a first seed layer, an etch stop layer, and a second seed layer that are sequentially stacked,', 'a first pad layer on the lower conductive layer, the first pad layer at least partially filling the opening, and', 'a second pad layer on the first pad layer, the second pad layer laterally extending beyond the first pad layer to contact a peripheral portion of the lower conductive layer located on the top surface of the passivation layer., 'a pad structure on the passivation layer and in the opening, the pad structure electrically connected to the conductive component, the pad structure comprising2. The semiconductor device of claim 1 , wherein the second pad layer is ...

SEMICONDUCTOR DEVICES

A semiconductor device includes a substrate, a protection layer on the substrate that includes a trench that penetrates therethrough, a lower bump that includes a first part that fills at least a portion of the trench and a second part on the protection layer; and an upper bump on the lower bump. The protection layer includes a first part that surrounds the trench and a second part that surrounds the first part. A first height from an upper surface of the substrate to an upper surface of the first part of the protection layer is greater than a second height from the upper surface of the substrate to an upper surface of the second part of the protection layer. 1. A semiconductor device , comprising:a substrate;a protection layer on the substrate, the protection layer including a trench that penetrates therethrough;a lower bump that includes a first part that fills at least a portion of the trench and a second part on the protection layer, wherein an upper surface of the first art of the lower bump is curved downward toward the substrate; andan upper bump on the lower bump,wherein the protection layer includes a first part that surrounds the trench and a second part that surrounds the first part, anda first height from an upper surface of the substrate to an upper surface of the first part of the protection layer is greater than a second height from the upper surface of the substrate to an upper surface of the second part of the protection layer.2. The semiconductor device according to claim 1 , wherein the lower bump includes a recess claim 1 , andthe upper bump includes a first part in the recess and a second part on the first part.3. The semiconductor device according to claim 1 , wherein an upper surface of the first part of the lower bump includes a second point spaced apart by a first distance from a first point on a sidewall of the trench in a first direction parallel to the upper surface of the substrate and a third point spaced apart by a second distance from ...

METHOD FOR FABRICATING GLASS SUBSTRATE PACKAGE

A substrate comprising a solid glass core having a first surface and a second surface opposed to the first surface; multiple conductors extending through the solid glass core beginning at the first surface and ending at the second surface, wherein one of the conductors has a third surface and a fourth surface, wherein the third surface and the first surface are substantially coplanar, wherein the second surface and the fourth surface are substantially coplanar, wherein one of the conductors comprise a copper-tungsten alloy material, wherein the solid glass core is directly contact with the conductor; and a first dielectric layer and a first metal layer formed at the first surface, wherein the first metal layer at the first surface is electrically coupled with one of the conductors. 1. A chip packaging structure comprising:a glass substrate having a first surface and a second surface opposed to said first surface, wherein said first surface is parallel to said second surface, multiple metal conductors extending through said glass substrate beginning at said first surface and ending at said second surface, wherein one of said metal conductors comprises a cross-section surface parallel to said first surface, wherein said cross-section surface comprises a first edge, a second edge opposite to and substantially parallel with said first edge, a third edge and a fourth edge opposite to said third edge, wherein said first edge has a first length is greater than that of said third and fourth edges, wherein said second edge has a second length is greater than that of said third and fourth edges, wherein said metal conductors comprises a first sidewall, a second sidewall opposite to and substantially parallel with said first sidewall, a third sidewall and a fourth sidewall opposite to said third sidewall;a first metal connection structure is on said first surface, wherein said first metal connection structure comprises a first dielectric layer on said first surface, wherein a ...

BONDED ASSEMBLY CONTAINING OXIDATION BARRIERS AND/OR ADHESION ENHANCERS AND METHODS OF FORMING THE SAME

A method of forming a bonded assembly includes providing a first semiconductor die containing a first substrate, first semiconductor devices, and first bonding pads that are electrically connected to a respective node of the first semiconductor devices, forming a first oxidation barrier layer on physically exposed surfaces of the first bonding pads, providing a second semiconductor die containing a second substrate, second semiconductor devices, and second bonding pads that are electrically connected to a respective node of the second semiconductor devices, and bonding the second bonding pads to the first bonding pads with at least the first oxidation barrier layer located between the respective first and second bonding pads. 1. A method of forming a bonded assembly , comprising:providing a first semiconductor die comprising a first substrate, first semiconductor devices, and first bonding pads that are electrically connected to a respective node of the first semiconductor devices;forming a first oxidation barrier layer on physically exposed surfaces of the first bonding pads;providing a second semiconductor die comprising a second substrate, second semiconductor devices, and second bonding pads that are electrically connected to a respective node of the second semiconductor devices; andbonding the second bonding pads to the first bonding pads with at least the first oxidation barrier layer located between the respective first and second bonding pads.2. The method of claim 1 , wherein:the first bonding pads are located within a first bonding dielectric layer;the second bonding pads are located within a second bonding dielectric layer; andthe oxidation barrier layer is selectively formed on physically exposed surfaces of the first bonding pads without forming the first oxidation barrier layer on physically exposed surfaces of the first bonding dielectric layer.3. The method of claim 2 , wherein:the first bonding dielectric layer and the second bonding dielectric ...

PAD STRUCTURE FOR FRONT SIDE ILLUMINATED IMAGE SENSOR

The present disclosure relates to an integrated circuit. The integrated circuit includes a plurality of interconnects within a dielectric structure over a substrate. A passivation structure is arranged over the dielectric structure. The passivation structure has sidewalls connected to one or more upper surfaces of the passivation structure. A bond pad is arranged directly between the sidewalls of the passivation structure. An upper passivation layer is disposed over the passivation structure and the bond pad. The upper passivation layer extends from over an upper surface of the bond pad to within a recess in the upper surface of the bond pad. 1. An integrated circuit , comprising:a plurality of interconnects within a dielectric structure over a substrate;a passivation structure arranged over the dielectric structure and having sidewalls connected to one or more upper surfaces of the passivation structure;a bond pad arranged directly between the sidewalls of the passivation structure; andan upper passivation layer disposed over the passivation structure and the bond pad, wherein the upper passivation layer extends from over an upper surface of the bond pad to within a recess in the upper surface of the bond pad.2. The integrated circuit of claim 1 ,wherein the upper passivation layer comprises both a first sidewall and a second sidewall laterally between the bond pad and the passivation structure; andwherein the first sidewall and the second sidewall of the upper passivation layer face one another and are separated from one another by a non-zero distance.3. The integrated circuit of claim 1 , wherein the upper passivation layer has surfaces defining a ‘U’ shaped segment between an outermost sidewall of the bond pad and one of the sidewalls of the passivation structure.4. The integrated circuit of claim 1 , wherein the passivation structure comprises a first material and a second material over the first material claim 1 , the upper passivation layer having a sidewall ...

Source Down Semiconductor Devices and Methods of Formation Thereof

A method for forming a semiconductor device includes forming device regions in a semiconductor substrate having a first side and a second side. The device regions are formed adjacent the first side. The method further includes forming a seed layer over the first side of the semiconductor substrate, and forming a patterned resist layer over the seed layer. A contact pad is formed over the seed layer within the patterned resist layer. The method further includes removing the patterned resist layer after forming the contact pad to expose a portion of the seed layer underlying the patterned resist layer, and forming a protective layer over the exposed portion of the seed layer.

Integrated circuit chip and display device including the same

An exemplary embodiment provides a driving circuit chip including: a substrate; a terminal electrode disposed on the substrate; and an electrode pad disposed on the terminal electrode, wherein the electrode pad includes: a bump structure protruded from the substrate to include a short side and a long side; and a bump electrode disposed on the bump structure and connected with the terminal electrode around a short edge portion of the bump structure, wherein the bump electrode is disposed to not cover at least a part of a long edge portion of the bump structure.

3D Integrated Circuit and Methods of Forming the Same

An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer. 1. A method of manufacturing a semiconductor device , the method comprising:pre-bonding a first dielectric barrier layer and a second dielectric barrier layer at room temperature for a time of less than about one minute, wherein the first dielectric barrier layer is adjacent to a first high porosity dielectric layer and the second dielectric barrier layer is adjacent to a second high porosity dielectric layer, wherein the first high porosity dielectric layer is adjacent to a first low porosity dielectric layer and the second high porosity dielectric layer is adjacent to a second low porosity dielectric layer, and wherein a first contact extends through the first low porosity dielectric layer, the first high porosity dielectric layer, and the first dielectric barrier layer to make contact with a second contact, the second contact extending through the second dielectric barrier layer, the second high porosity dielectric layer, and the second low porosity dielectric layer; andannealing the first dielectric barrier layer and the second dielectric barrier layer at a temperature of between about 300° C. and about 400° C.2. The method of claim 1 , further comprising curing the first dielectric barrier layer and the second dielectric barrier layer.3. The method of claim 1 ...

Integrated circuit device structures and double-sided fabrication techniques

Integrated circuit cell architectures including both front-side and back-side structures. One or more of back-side implant, semiconductor deposition, dielectric deposition, metallization, film patterning, and wafer-level layer transfer is integrated with front-side processing. Such double-side processing may entail revealing a back side of structures fabricated from the front-side of a substrate. Host-donor substrate assemblies may be built-up to support and protect front-side structures during back-side processing. Front-side devices, such as FETs, may be modified and/or interconnected during back-side processing. Back-side devices, such as FETs, may be integrated with front-side devices to expand device functionality, improve performance, or increase device density.

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

A semiconductor package includes a chip, a redistribution structure, and first under-ball metallurgies patterns. The chip includes conductive posts exposed at an active surface. The redistribution structure is disposed on the active surface. The redistribution structure includes a first dielectric layer, a topmost metallization layer, and a second dielectric layer. The first dielectric layer includes first openings exposing the conductive posts of the chip. The topmost metallization layer is disposed over the first dielectric layer and is electrically connected to the conductive posts. The topmost metallization layer comprises first contact pads and routing traces connected to the first contact pads. The second dielectric layer is disposed on the topmost metallization layer and includes second openings exposing the first contact pads. The first under-ball metallurgies patterns are disposed on the first contact pads, extending on and contacting sidewalls and top surfaces of the first contact pads. 1. A semiconductor package , comprising:a chip comprising conductive posts exposed at an active surface of the chip; a first dielectric layer, including first openings exposing the conductive posts of the chip;', 'a topmost metallization layer, disposed over the first dielectric layer and electrically connected to the conductive posts, wherein the topmost metallization layer comprises first contact pads and routing traces connected to the first contact pads; and', 'a second dielectric layer, disposed on the topmost metallization layer and including second openings exposing the first contact pads; and, 'a redistribution layer disposed on the active surface of the chip, comprisingfirst under-ball metallurgies patterns disposed on the first contact pads, wherein the first under-ball metallurgy patterns extend on and contact sidewalls and top surfaces of the first contact pads.2. The semiconductor package of claim 1 , wherein the topmost metallization layer further comprises ...

Methods and Apparatus of Packaging Semiconductor Devices

Methods and apparatus are disclosed which reduce the stress concentration at the redistribution layers (RDLs) of a package device. A package device may comprise a seed layer above a passivation layer, covering an opening of the passivation layer, and covering and in contact with a contact pad. A RDL is formed above the passivation layer, above and in contact with the seed layer, covering the opening of the passivation layer, and electrically connected to the contact pad through the seed layer. The RDL has an end portion with a surface that is smooth without a right angle. The surface of the end portion of the RDL may have an obtuse angle, or a curved surface. 1. A method comprising:forming a dielectric layer on a surface of a substrate, the dielectric layer having a first opening exposing a contact pad;forming a seed layer over the dielectric layer, the seed layer extending into the first opening to the contact pad;forming a first mask layer over the seed layer, the first mask layer having a second opening exposing the seed layer;forming a second mask layer in the second opening;forming a third mask layer over the second mask layer, the third mask layer having a third opening exposing the second mask layer;removing the second mask layer, thereby forming a fourth opening; andforming a conductive material in the fourth opening.2. The method of claim 1 , wherein the third mask layer does not extend over an upper surface of the first mask layer.3. The method of claim 1 , wherein a first slope a sidewall of the second opening is different than a second slope of a sidewall of the fourth opening.4. The method of claim 1 , further comprising removing the first mask layer and the second mask layer claim 1 , wherein the conductive material comprises an indent extending between a first sidewall adjacent the seed layer and second sidewall extending to an uppermost surface of the conductive material.5. The method of claim 4 , wherein the second sidewall is non-perpendicular.6. ...

SEMICONDUCTOR DEVICE, MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, CIRCUIT SUBSTRATE, AND ELECTRONIC APPARATUS

A semiconductor device includes an integrated circuit that is disposed at a first face side of a semiconductor substrate, the semiconductor substrate having a first face and a second face, the second face opposing the first face, the semiconductor substrate having a through hole from the first face to the second face; an external connection terminal that is disposed at the first face side; a conductive portion that is disposed in the through hole, the conductive portion being electrically connected to the external connection terminal; and an electronic element that is disposed at a second face side. 1. A device comprising:a semiconductor substrate including a first face and a second face on a side opposite to the first face;an external connection terminal formed on the first face of the semiconductor substrate;a first electrode formed on the first face of the semiconductor substrate and electrically connected to the external connection terminal;a second electrode formed on the first face of the semiconductor substrate;an integrated circuit formed on the first face, the integrated circuit being electrically connected to the first electrode and the second electrode;a rear face electrode formed on the second face of the semiconductor substrate;a groove portion formed in the semiconductor substrate, the groove portion having an inner wall;an insulating film formed on side walls of the groove portion; anda conductive portion formed inside the groove portion on the insulating portion and electrically connected to the second electrode and the rear face electrode;wherein the integrated circuit and the first electrode are electrically disposed between the second electrode and the external connection terminal.2. The device of claim 1 , wherein the semiconductor substrate is silicon.3. The device of claim 2 , wherein:the second electrode comprises a second electrode rear face facing the first face of the semiconductor substrate;the rear face electrode comprises a rear face ...

Interconnect Structure and Method of Forming Same

A device includes a first side interconnect structure over a first side of a substrate, wherein active circuits are in the substrate and adjacent to the first side of the substrate, a dielectric layer over a second side of the substrate, a pad embedded in the dielectric layer, the pad comprising an upper portion and a bottom portion formed of two different materials and a passivation layer over the dielectric layer. 1. A device comprising:a dielectric layer on a first side of a semiconductor substrate;a first redistribution line in a first recess in the dielectric layer, the first redistribution line comprising a first layer, the first layer completely filling the first recess;a contact pad in a second recess in the dielectric layer, wherein a width of the contact pad is greater than a width of a first redistribution line, wherein the contact pad comprises a second layer and a third layer over the second layer, wherein the second layer and the first layer are a same material, wherein the second layer and the third layer completely fills the second recess, the second layer and the third layer comprising different materials; anda passivation layer over the dielectric layer.2. The device of further comprising a transistor on a second side of the semiconductor substrate.3. The device of further comprising:a front-side interconnect structure on the second side of the semiconductor substrate; anda through via extending from a conductive feature in the front-side interconnect structure through the semiconductor substrate to the first side of the semiconductor substrate, wherein the contact pad is electrically coupled to the through via.4. The device of claim 3 , wherein the contact pad directly contacts the through via.5. The device of claim 1 , wherein the dielectric layer is interposed between the contact pad and the first side of the semiconductor substrate.6. The device of further comprising a passivation layer over the dielectric layer.7. The device of claim 6 , ...

Light-emittng device

A light-emitting device includes a first light-emitting element, a second light-emitting element having a peak emission wavelength different from that of the first light-emitting element, a light-guide member covering a light extracting surface and lateral surfaces of the first light-emitting element and a light extracting surface and lateral surfaces of the second light-emitting element, and a wavelength conversion layer continuously covering the light extracting surface of each of the first and second light-emitting elements and disposed apart from each of the first and second light-emitting elements, and a first reflective member covering outer lateral surfaces of the light-guide member. An angle defined by an active layer of the first light-emitting element and an active layer of the second light-emitting element is less than 180° at a wavelength conversion layer side.

Structures and methods for low temperature bonding

A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements.

SEMICONDUCTOR DEVICE STRUCTURE WITH CONDUCTIVE POLYMER LINER AND METHOD FOR FORMING THE SAME

The present disclosure relates to a semiconductor device structure with a conductive polymer liner and a method for preparing the semiconductor device structure. The semiconductor device structure includes a first metal layer disposed over a semiconductor substrate, and a second metal layer disposed over the first metal layer. The semiconductor device structure also includes a conductive structure disposed between the first metal layer and the second metal layer. The conductive structure includes a first conductive via and a first conductive polymer liner surrounding the first conductive via.

Hybrid Bonding Systems and Methods for Semiconductor Wafers

Hybrid bonding systems and methods for semiconductor wafers are disclosed. In one embodiment, a hybrid bonding system for semiconductor wafers includes a chamber and a plurality of sub-chambers disposed within the chamber. A robotics handler is disposed within the chamber that is adapted to move a plurality of semiconductor wafers within the chamber between the plurality of sub-chambers. The plurality of sub-chambers includes a first sub-chamber adapted to remove a protection layer from the plurality of semiconductor wafers, and a second sub-chamber adapted to activate top surfaces of the plurality of semiconductor wafers prior to hybrid bonding the plurality of semiconductor wafers together. The plurality of sub-chambers also includes a third sub-chamber adapted to align the plurality of semiconductor wafers and hybrid bond the plurality of semiconductor wafers together. 1. A method comprising:depositing a first protection layer on a first bonding surface of a first semiconductor wafer;removing the first protection layer from the first bonding surface of the first semiconductor wafer to expose the first bonding surface of the first semiconductor wafer;applying a plasma process to the first bonding surface of the first semiconductor wafer;performing a cleaning process on the first bonding surface of the first semiconductor wafer;coupling the first semiconductor wafer to a second semiconductor wafer; andannealing the first semiconductor wafer and the second semiconductor wafer to bond the first bonding surface of the first semiconductor wafer to a second bonding surface of the second semiconductor wafer, wherein bonding the first bonding surface of the first semiconductor wafer to the second bonding surface of the second semiconductor wafer comprises:forming a first bond between a first insulating layer of the first bonding surface and a second insulating layer of the second bonding surface; andforming a second bond between a first conductive pad of the first bonding ...

Barrier materials between bumps and pads

Disclosed are barrier materials between bumps and pads, and related devices and methods. A semiconductor device includes an interconnect, a top material, a pad on the interconnect and at least a portion of the top material, a bump on the pad, and a barrier material between the pad and the bump. The top material defines a via therethrough to the interconnect. The pad includes electrically conductive material. The bump includes electrically conductive material. The bump is configured to electrically connect the interconnect to another device. The barrier material is between the pad and the bump. The barrier material includes a conductive material that is resistant to electromigration, intermetallic compound reaction, or both electromigration and intermetallic compound reaction.

Semiconductor device having through silicon vias

The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, a conductive feature, a redistribution layer, at least one through silicon via and at least one bump. The conductive feature is disposed over a front surface of the substrate, and the redistribution layer is disposed over a back surface opposite to the front surface. The through silicon via penetrates through the substrate and contacts the conductive feature embedded in an insulative layer. The bump contacts the redistribution layer and the through silicon via and serves as an electrical connection therebetween.

Polymer Layers Embedded with Metal Pads for Heat Dissipation

An integrated circuit structure includes a metal pad, a passivation layer including a portion over the metal pad, a first polymer layer over the passivation layer, and a first Post-Passivation Interconnect (PPI) extending into to the first polymer layer. The first PPI is electrically connected to the metal pad. A dummy metal pad is located in the first polymer layer. A second polymer layer is overlying the first polymer layer, the dummy metal pad, and the first PPI. An Under-Bump-Metallurgy (UBM) extends into the second polymer layer to electrically couple to the dummy metal pad. 1. An integrated circuit structure comprising:a metal pad;a passivation layer comprising a portion over the metal pad;a first polymer layer comprising a portion over the passivation layer;a dummy metal pad in the first polymer layer, wherein the dummy metal pad is electrically floating;a second polymer layer over the first polymer layer and the dummy metal pad; anda first Under-Bump-Metallurgy (UBM) extending into the second polymer layer to electrically couple to the dummy metal pad.2. The integrated circuit structure of claim 1 , wherein a top surface and a bottom surface of the dummy metal pad are coplanar with a top surface and a bottom surface claim 1 , respectively claim 1 , of the first polymer layer.3. The integrated circuit structure of further comprising:a package component comprising a surface metallic feature; anda solder region bonding the surface metallic feature in the package component to the first UBM, wherein the dummy metal pad, the solder region, and the surface metallic feature in combination are electrically floating.4. The integrated circuit structure of further comprising:a third polymer layer between the first polymer layer and the second polymer layer; anda Post-Passivation Interconnect (PPI) extending into to the third polymer layer, wherein the PPI electrically couples the dummy metal pad to the first UBM.5. The integrated circuit structure of further comprising: ...

Chip with programmable shelf life

A structure includes a first interconnect structure and a second interconnect structure each located within an interlevel dielectric (ILD), a first top metal layer and a second top metal layer disposed on and in direct electrical connection with the first interconnect, a third top metal layer and a fourth top metal layer disposed on and in direct electrical connection with the second interconnect, a silicon dioxide layer above the first, second, third and fourth top metal layers, the silicon layer is in direct contact with the first and fourth top metal layers, and a barrier layer separating the silicon dioxide layer from each of the second and third top metal layers, a high resistance connection exist between the third top metal layer and the fourth top metal layer due to the presence of the silicon dioxide layer.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device includes a first carrier including a first pad, a second carrier including a second pad disposed opposite to the first pad, a joint coupled with and standing on the first pad, a joint encapsulating the post and bonding the first pad with the second pad, a first entire contact interface between the first pad and the joint, a second entire contact interface between the first pad and the post, and a third entire contact interface between the joint and the second pad. The first entire contact interface, the second entire contact interface and the third entire contact interface are flat surfaces. A distance between the first entire contact interface and the third entire contact interface is equal to a distance between the second entire contact interface and the third entire contact interface. The second entire contact interface is a continuous surface. 1. A semiconductor device , comprising:a silicon substrate;a carrier;a first pad on the silicon substrate;a second pad on the carrier;a post on a surface of the first pad, wherein the post consists of a metal or a metal alloy;a joint disposed between the silicon substrate and the carrier, contacted with the first pad and the second pad, and encapsulating the post;a first entire contact interface between the first pad and the joint;a second entire contact interface between the first pad and the post; anda third entire contact interface between the joint and the second pad,wherein an outer surface of the joint is concaved and curved towards the post, and a height of the post is greater than or equal to ⅓ of a height of the joint between the first pad and the second pad, the first entire contact interface, the second entire contact interface and the third entire contact interface are flat surfaces, wherein a distance between the first entire contact interface and the third entire contact interface is equal to a distance between the second entire contact interface and the third entire contact interface, ...

Semiconductor device

A semiconductor device suitable for preventing malfunction is provided. The semiconductor device includes a semiconductor chip 1 , a first electrode pad 21 laminated on the semiconductor chip 1 , an intermediate layer 4 having a rectangular shape defined by first edges 49 a and second edges, and a plurality of bumps 5 arranged to sandwich the intermediate layer 4 by cooperating with the semiconductor chip 1 . The first edges 49 a extend in the direction x, whereas the second edges extend in the direction y. The plurality of bumps 5 include a first bump 51 electrically connected to the first electrode pad 21 and a second bump 52 electrically connected to the first electrode pad 21 . The first bump 51 is arranged at one end in the direction x and one end in the direction y.

SEMICONDUCTOR PACKAGING AND MANUFACTURING METHOD THEREOF

The present disclosure provides a semiconductor package, which includes a substrate, a passivation layer, a post-passivation interconnect (PPI) having a top surface; and a conductive structure. The top surface of the PPI includes a first region receiving the conductive structure, and a second region surrounding the first region. The second region includes metal derivative transformed from materials made of the first region. The present disclosure provide a method of manufacturing a semiconductor package, including forming a first flux layer covering a portion of a top surface of a PPI; transforming a portion of the top surface of the PPI uncovered by the first flux layer into a metal derivative layer; removing the first flux layer; forming a second flux layer on the first region of the PPI; dropping a solder ball on the flux layer; and forming electrical connection between the solder ball and the PPI. 1. A method of manufacturing a semiconductor package , comprising:patterning a metal derivative in a second region of a post-passivation interconnect (PPI);forming a flux layer in a first region of the PPI, wherein the first region is surrounded by the second region;dropping a solder ball on the flux layer; andforming electrical connection between the solder ball and the PPI.2. The method of manufacturing a semiconductor package in claim 1 , wherein the to patterning the metal derivative in the second region of the PPI further comprising forming a mask layer over the PPI.3. The method of manufacturing a semiconductor package in claim 2 , wherein the forming the mask layer over the PPI comprises forming a mask layer on the PPI.4. The method of manufacturing a semiconductor package in claim 2 , wherein the forming the mask layer over the PPI comprises positioning a first stencil plate over the PPI.5. The method of manufacturing a semiconductor package in claim 1 , wherein the patterning the metal derivative in the second region of the PPI comprises an oxygen plasma ...

Semiconductor package

A semiconductor package including a package substrate, a semiconductor chip on a top surface of the package substrate, a connection terminal between the package substrate and the semiconductor chip, the connection terminal connecting the package substrate to the semiconductor chip, a non-conductive film (NCF) between the package substrate and semiconductor chip, the NCF surrounding the connection terminal and bonding the semiconductor chip to the package substrate, and a side encapsulation material covering a side surface of the semiconductor chip, contacting the package substrate, and including a first portion between a bottom surface of the semiconductor chip and the top surface of the package substrate may be provided. At least a portion of the NCF includes a second portion that horizontally protrudes from the semiconductor chip when viewed, and a portion of the side encapsulation material is in contact with the bottom surface of the semiconductor chip.

Semiconductor device with slanted conductive layers and method for fabricating the same

The present application discloses a semiconductor device with slanted conductive layers and a method for fabricating the semiconductor device with the slanted conductive layers. The semiconductor device includes a substrate, a first insulating layer positioned above the substrate, first slanted conductive layers positioned in the first insulating layer, and a top conductive layer positioned covering the first slanted conductive layers.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

To enhance reliability of a test by suppressing defective bonding of a solder in the test of a semiconductor device, a method of manufacturing the semiconductor device includes: preparing a semiconductor wafer that includes a first pad electrode provided with a first cap film and a second pad electrode provided with a second cap film. Further, a polyimide layer that includes a first opening on the first pad electrode and a second opening on the second pad electrode is formed, and then, a rearrangement wiring that is connected to the second pad electrode via the second opening is formed. Next, an opening is formed in the polyimide layer such that an organic reaction layer remains on each of the first pad electrode and a bump land of the rearrangement wiring, then heat processing is performed on the semiconductor wafer, and then, a bump is formed on the rearrangement wiring. 1(a) preparing a semiconductor substrate that includes a first pad electrode and a second pad electrode, the first pad electrode being formed at an uppermost layer of a plurality of wiring layers and having a first metal film formed on a surface of the first pad electrode, and the second pad electrode being electrically connected to the first pad electrode, being formed at the uppermost layer of the plurality of wiring layers and having a second metal film formed on a surface of the second pad electrode;(b) foaming a first insulating film having a first opening, for exposing the first metal film in the first pad electrode, and a second opening for exposing the second metal film in the second pad electrode;(c) forming a mask layer on the first insulating film for covering the first opening and exposing the second opening;(d) forming a wiring which is electrically connected to the second pad electrode via the second opening;(e) forming a second insulating film on the first pad electrode and on the wiring;(f) forming a third opening in the second insulating film above the first pad electrode and ...

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

A mechanism of a semiconductor structure with composite barrier layer under redistribution layer is provided. A semiconductor structure includes a substrate comprising a top metal layer on the substrate; a passivation layer over the top metal layer having an opening therein exposing the top metal layer; a composite barrier layer over the passivation layer and the opening, the composite barrier layer includes a center layer, a bottom layer, and an upper layer, wherein the bottom layer and the upper layer sandwich the center layer; and a redistribution layer (RDL) over the composite barrier layer and electrically connecting the underlying top metal layer. 1. A semiconductor structure comprising:a metal layer;a passivation layer over the metal layer;a composite barrier layer in a recess that extends into the metal layer through the passivation layer; anda redistribution layer (RDL) over the composite barrier layer.2. The semiconductor structure of claim 1 , wherein the composite barrier layer comprises:a bottom layer in contact with metal layer; anda center layer over the bottom layer.3. The semiconductor structure of claim 2 , wherein the composite barrier layer further comprises an upper layer over the center layer.4. The semiconductor structure of claim 2 , wherein the bottom layer includes a first portion claim 2 , a second portion above the first portion claim 2 , and a third portion between the first and second portions.5. The semiconductor structure of claim 1 , wherein an external portion of the composite barrier layer is in contact with a surface of the passivation layer outside of the recess.6. The semiconductor structure of claim 5 , wherein the external portion of the composite barrier layer is between the RDL and the passivation layer.7. The semiconductor structure of claim 1 , wherein the metal layer comprises a different material than the RDL.8. A semiconductor structure comprising:a passivation layer having a recess therein; a bottom layer; and', 'a ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A method of manufacturing a semiconductor device includes providing a semiconductor substrate, forming, over a main surface the semiconductor substrate, a first insulating film, forming, over the first insulating film, an Al-containing conductive film containing aluminum as a main component, patterning the Al-containing conductive film to form a pad, forming, over the first insulating film, a second insulating film to cover the pad therewith, forming an opening in the second insulating film, and electrically coupling a copper wire to the pad exposed from the opening. 1. A method of manufacturing a semiconductor device , the method comprising:(a) providing a semiconductor substrate;(b) forming, over a main surface the semiconductor substrate, a first insulating film;(c) forming, over the first insulating film, an Al-containing conductive film containing aluminum as a main component;(d) patterning the Al-containing conductive film to form a pad;(e) forming, over the first insulating film, a second insulating film to cover the pad therewith;(f) forming an opening in the second insulating film;(g) electrically coupling a copper wire to the pad exposed from the opening;(h) after the (c) and before the (g), forming a first conductor film over the Al-containing conductive film; and(i) after the (h) and before the (g), forming a second conductor film over the first conductor film,wherein the first conductor film includes a single-layer film or a laminated film including one or more layers of films selected from a group consisting of a titanium film, a titanium nitride film, a tantalum film, a tantalum nitride film, a tungsten film, a tungsten nitride film, a titanium-tungsten film, and a tantalum-tungsten film,wherein the second conductor film comprises one or more metals selected from a group consisting of palladium, gold, ruthenium, rhodium, platinum, and iridium, andwherein, in the (g), the copper wire is bonded to the second conductor film.2. The method of manufacturing ...

Method of forming a chip assembly and chip assembly

A method of forming a chip assembly may include forming a plurality of cavities in a carrier; The method may further include arranging a die attach liquid in each of the cavities; arranging a plurality of chips on the die attach liquid, each chip comprising a rear side metallization and a rear side interconnect material disposed over the rear side metallization, wherein the rear side interconnect material faces the carrier; evaporating the die attach liquid; and after the evaporating the die attach liquid, fixing the plurality of chips to the carrier.

Semiconductor device, manufacturing method for semiconductor device, electronic component, circuit substrate, and electronic apparatus

A semiconductor device includes an integrated circuit that is disposed at a first face side of a semiconductor substrate, the semiconductor substrate having a first face and a second face, the second face opposing the first face, the semiconductor substrate having a through hole from the first face to the second face; an external connection terminal that is disposed at the first face side; a conductive portion that is disposed in the through hole, the conductive portion being electrically connected to the external connection terminal; and an electronic element that is disposed at a second face side.

SEMICONDUCTOR DEVICE

A semiconductor device includes a first substrate and a second substrate that is stacked on a first surface of the first substrate in a stacking direction and includes a second surface facing the first surface. A plurality of first terminals is provided on the first surface of the first substrate. A plurality of second terminals is provided on the second surface of the second substrate. A plurality of metallic portions is respectively provided between the plurality of first terminals and the plurality of second terminals. In a cross-section substantially perpendicular to the stacking direction, at least one of (i) each of the plurality of first terminals or (ii) each of the plurality of second terminals (a) includes a recessed portion in a first direction toward an adjacent first terminal or second terminal or (b) includes a projecting portion in a second direction intersecting with the first direction. 1. A semiconductor device comprising:a first substrate having a first surface;a second substrate stacked on the first surface of the first substrate in a stacking direction, the second substrate having a second surface facing the first surface;a plurality of first terminals provided on the first surface of the first substrate;a plurality of second terminals provided on the second surface of the second substrate; anda plurality of metallic portions respectively provided between the plurality of first terminals and the plurality of second terminals,wherein, in a cross-section substantially perpendicular to the stacking direction, at least one of (i) each of the plurality of first terminals or (ii) each of the plurality of second terminals (a) includes a recessed portion in a first direction toward an adjacent first terminal or second terminal or (b) includes a projecting portion in a second direction intersecting with the first direction.2. The semiconductor device according to claim 1 , wherein each of the metallic portions is made from a material having a lower ...

Package with ubm and methods of forming

Package structures and methods of forming package structures are discussed. A package structure, in accordance with some embodiments, includes an integrated circuit die, an encapsulant at least laterally encapsulating the integrated circuit die, a redistribution structure on the integrated circuit die and the encapsulant, a connector support metallization coupled to the redistribution structure, a dummy pattern, a second dielectric layer, and an external connector on the connector support metallization. The redistribution structure comprises a first dielectric layer having a first surface disposed distally from the encapsulant and the integrated circuit die. The dummy pattern is on the first surface of the first dielectric layer and around the connector support metallization. The second dielectric layer is on the first surface of the first dielectric layer and on at least a portion of the dummy pattern. The second dielectric layer does not contact the connector support metallization.

COLLARS FOR UNDER-BUMP METAL STRUCTURES AND ASSOCIATED SYSTEMS AND METHODS

The present technology is directed to manufacturing collars for under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects and associated systems. A semiconductor die includes a semiconductor material having solid-state components and an interconnect extending at least partially through the semiconductor material. An under-bump metal (UBM) structure is formed over the semiconductor material and is electrically coupled to corresponding interconnects. A collar surrounds at least a portion of the side surface of the UBM structure, and a solder material is disposed over the top surface of the UBM structure. 1. A semiconductor die , comprising:a semiconductor material having solid-state components;an interconnect extending at least partially through the semiconductor material;an under-bump metal (UBM) structure electrically coupled to the interconnect, wherein the UBM structure has a top surface, a bottom surface, and a sidewall extending between the top and bottom surfaces;a collar surrounding at least a portion of the sidewall of the UBM structure, wherein the collar does not extend above the top surface of the UBM structure; anda solder material disposed over the top surface of the UBM structure,wherein the collar comprises an anti-wetting material to which the solder material does not readily wet in liquid phase.2. The semiconductor die of wherein the collar comprises at least one of: an oxide claim 1 , a nitride claim 1 , or polyimide.3. The semiconductor die of wherein the collar has a thickness of between about 2000 and about 2500 Å.4. The semiconductor die of wherein the UBM structure is a pillar claim 1 , and wherein the collar covers only the sidewall of the pillar.5. The semiconductor die of wherein the collar extends along only a portion of a height of the sidewall of the UBM.6. The semiconductor die of wherein the collar extends along at least 80% of the height of the sidewall of the UBM structure.7. The semiconductor die of ...

SEMICONDUCTOR DEVICE

A semiconductor device includes a substrate, a plurality of pads disposed over the substrate, and a solder mask disposed over the substrate. The substrate includes a pair of first edges parallel to each other, a pair of second edges orthogonal to the pair of first edges, and a center point. The solder mask includes four recess portions exposing an entire top surface and sidewalls of four of the pads in four corners of the regular array, and a plurality of second recess portions exposing a portion of a top surface of other pads in the regular array. A pad size of the four pads in the four corners of the regular array exposed through the first recess portions and a pad size of the other pads exposed through the second recess portions are the same. 2. The semiconductor device of claim 1 , wherein the plurality of pads comprise four non-solder mask defined (NSMD) pads in the four corners of the regular array and a plurality of solder mask defined (SMD) pads disposed away from the four corners of the regular array.3. The semiconductor of claim 2 , wherein each of the four NSMD pads is adjacent to one of the SMD pads in a same horizontal row and another one of the SMD pads in a same vertical column.4. The semiconductor device of claim 1 , wherein the first vertical distances are similar to the second vertical distances.5. The semiconductor device of claim 1 , wherein the first vertical distances are different from the second vertical distances.6. The semiconductor device of claim 1 , wherein a first distance is defined as a distance between the center point and each of the four first recess portions claim 1 , and the first distance is greater than at least one of the first vertical distance and the second vertical distance.7. The semiconductor device of claim 6 , wherein a second distance is defined as a distance between the center point and each of the second recess portions claim 6 , and the second distance is less than the first vertical distance and the second ...

Chip package, method of forming a chip package and method of forming an electrical contact

In various embodiments, a method of forming an electrical contact is provided. The method may include depositing, by atomic layer deposition, a passivation layer over at least a region of a metal surface, wherein the passivation layer may include aluminum oxide, and electrically contacting the region of the metal surface with a metal contact structure, wherein the metal contact structure may include copper.

Semiconductor structure and manufacturing method thereof

A semiconductor structure includes a substrate; a pad disposed over the substrate; a first passivation disposed over the substrate, partially covering the pad, and including a protrusion protruded from the first passivation and away from the substrate; a conductive layer disposed over the first passivation and a portion of the pad exposed from the first passivation; and a second passivation disposed over the conductive layer, wherein the conductive layer disposed over the protrusion is exposed from the second passivation.

SEMICONDUCTOR DEVICE

A semiconductor device includes a substrate including a surface, a plurality of pads disposing on the surface of the substrate, the plurality of pads includes a non-solder mask defined (NSMD) pad and a solder mask defined (SMD) pad, and the NSMD pad is arranged at a predetermined location. Further, a method of manufacturing a semiconductor device includes providing a substrate, disposing a plurality of pads on a surface of the substrate, disposing a solder mask over the surface of the substrate and the plurality of pads, forming a first recess in the solder mask to surround one of the plurality of pads, and forming a second recess in the solder mask and above one of the plurality of pads. 2. The semiconductor device of claim 1 , wherein the plurality of pads are arranged in a regular array including a plurality of horizontal rows and a plurality of vertical columns.3. The semiconductor device of claim 1 , wherein the plurality of pads comprise a plurality of non-solder mask defined (NSMD) pads and a plurality of solder mask defined (SMD) pads.4. The semiconductor of claim 3 , wherein the first recess portion entirely exposes one of the NSMD pads claim 3 , and the second recess portion partially exposes one of the SMD pads.5. The semiconductor device of claim 1 , wherein first recess portion is disposed on a corner of the semiconductor device and the second recess portion is disposed away from the corner of the semiconductor device.6. The semiconductor device of claim 1 , wherein the first distance between the central point and the first edge is greater than a fourth distance between the central point and the second recess portion claim 1 , and the second distance between the central point and the second edge is greater than the fourth distance between the central point and the second recess portion.7. A semiconductor device claim 1 , comprising:a substrate comprising a pair of first edges parallel to each other, a pair of second edges orthogonal to the first edge, ...

Semiconductor Device and Method of Forming Patterned Repassivation Openings Between RDL and UBM to Reduce Adverse Effects of Electro-Migration

A semiconductor device has a semiconductor wafer with a first conductive layer formed over a surface of the semiconductor wafer. A first insulating layer is formed over the surface of the semiconductor wafer and first conductive layer. A second conductive layer is formed over the first insulating layer and first conductive layer. A second insulating layer is formed over the first insulating layer and second conductive layer. A plurality of openings is formed in the second insulating layer in a bump formation area of the semiconductor wafer to expose the second conductive layer and reduce adverse effects of electro-migration. The openings are separated by portions of the second insulating layer. A UBM layer is formed over the openings in the second insulating layer in the bump formation area electrically connected to the second conductive layer. A bump is formed over the UBM layer.

CHIP AND MANUFACTURING METHOD THEREOF, AND ELECTRONIC DEVICE

Embodiments of this application provide a chip and a manufacturing method thereof, and an electronic device, and belong to the field of chip heat dissipation technologies. The chip includes a die and a thermal conductive sheet. An active surface of the die is connected to the thermal conductive sheet by using a first bonding layer. Heat generated at a part with a relatively high temperature on the active surface of the die can be quickly conducted and dispersed by using the thermal conductive sheet, so that temperatures on the active surface are evenly distributed to avoid an excessively high local temperature of the chip, thereby preventing running of the chip from being affected. 1. A chip , comprising:a die; anda thermal conductive sheet, wherein an active surface of the die is connected to the thermal conductive sheet by using a first bonding layer.2. The chip according to claim 1 , further comprising:a plurality of conductive pillars run through the thermal conductive sheet,wherein the first bonding layer comprises an insulated connection layer and a plurality of electrical interconnection structures, wherein the electrical interconnection structures are located in the insulated connection layer; anda plurality of pads of the active surface arc connected to the conductive pillars through bonding by using the electrical interconnection structures, and wherein a region of the active surface other than the pads is connected to the thermal conductive sheet through bonding by using the insulated connection layer.3. The chip according to claim 1 , further comprising:a plurality of conductive pillars run through the thermal conductive sheet; andwherein the first bonding layer comprises an insulated connection layer, wherein the conductive pillars are deposited on pads of the active surface, and wherein a region of the active surface other than the pads is connected to the thermal conductive sheet through bonding by using the insulated connection layer.4. The chip ...

Method of manufacturing semiconductor device

The present disclosure provides a method of manufacturing a semiconductor device. The method includes forming an interconnect layer on a semiconductor component, wherein the interconnect layer contains at least one metal pad electrically coupled to the semiconductor component; depositing an insulating layer on the interconnect layer; depositing a bonding dielectric on the insulating layer; and forming a re-routing layer penetrating through the bonding dielectric and the insulating layer and contacting the interconnect layer.

Nonvolatile memory device, system including the same and method of fabricating the same

A nonvolatile memory device including a substrate extending in a first direction, a ground selection line extending in the first direction on the substrate, a plurality of word lines stacked sequentially on the ground selection line and extending in the first direction, a landing pad spaced apart from the ground selection line and the plurality of word lines in the first direction, a rear contact plug connected to a lower face of the landing pad and extending in a second direction intersecting the first direction, a front contact plug connected to an upper face of the landing pad opposite the lower face and extending in the second direction, an input/output pad electrically connected to the rear contact plug, and an upper bonding pad electrically connected to the front contact plug and connected to at least a part of a plurality of circuit elements of the nonvolatile memory device.

METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE

The present disclosure provides a method for manufacturing a semiconductor structure employing a via structure. The method includes forming a first conductive pad on a first semiconductor device; forming a second conductive pad on the first conductive pad; connecting a second semiconductor device to the first semiconductor device; and forming a via structure in the second semiconductor device, The via structure contacts the second conductive pad, and the first conductive pad and the second conductive pad are formed of different metal materials. 1. A method of manufacturing a semiconductor structure , comprising:forming a first conductive pad on a first semiconductor device;forming a second conductive pad on the first conductive pad;connecting a second semiconductor device to the first semiconductor device; andforming a via structure in the second semiconductor device, wherein the via structure contacts the second conductive pad;wherein the first conductive pad and the second conductive pad are formed of different metal materials.2. The method of claim 1 , wherein the forming of the second conductive pad on the first conductive pad comprises: forming a dielectric layer on the first conductive pad; and forming an opening in the dielectric layer to expose the first conductive pad.3. The method of claim 2 , wherein the forming of the second conductive pad on the first conductive pad comprises: forming the second conductive pad in the opening.4. The method of claim 1 , further comprising: forming the first conductive pad and the second conductive pad with chemical reactivity that increase at positions along a direction from the via structure to the first semiconductor device.5. The method of claim 1 , further comprising: forming the second conductive pad with a thickness less than a thickness of the first conductive pad.6. The method of claim 1 , further comprising: forming a step structure of the first conductive pad and the second conductive pad claim 1 , wherein a ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

A semiconductor device of an embodiment includes: a semiconductor substrate; a first insulating layer provided on or above the semiconductor substrate; an aluminum layer provided on the first insulating layer; a second insulating layer provided on the first insulating layer, the second insulating layer covering a first region of a surface of the aluminum layer; and an aluminum oxide film provided on a second region other than the first region of the surface of the aluminum layer, the aluminum oxide film including α-alumina as a main component, and a film thickness of the aluminum oxide film being equal to or larger than 0.5 nm and equal to or smaller than 3 nm. 1. A semiconductor device comprising:a semiconductor substrate;a first insulating layer provided on or above the semiconductor substrate;an aluminum layer provided on the first insulating layer;a second insulating layer provided on the first insulating layer, the second insulating layer covering a first region of a surface of the aluminum layer; andan aluminum oxide film provided on a second region other than the first region of the surface of the aluminum layer, the aluminum oxide film including α-alumina as a main component, and a film thickness of the aluminum oxide film being equal to or larger than 0.5 nm and equal to or smaller than 3 nm.2. The semiconductor device according to claim 1 , wherein the aluminum layer includes at least one of silicon and copper.3. The semiconductor device according to claim 1 , further comprising a polyimide layer provided on the second insulating layer.4. The semiconductor device according to claim 1 , further comprising a bonding wire provided on the second region.5. The semiconductor device according to claim 4 , wherein the aluminum oxide film exists in a part between the bonding wire and the aluminum layer.6. A method of manufacturing a semiconductor device claim 4 , comprising:forming a first insulating layer on or above a semiconductor substrate;forming an aluminum ...

Method of forming a temporary test structure for device fabrication

A method of forming a temporary test structure for device fabrication is provided. The method allows for electrically testing conductive interconnects during controlled collapse chip connections (C4) fabrication and/or through-silicon vias (TSVs) during interposer fabrication. The method includes providing a substrate containing a plurality of electrically conductive interconnects extending vertically to top surface of the substrate. A temporary test structure is formed to connect the plurality of interconnects for electrical testing. Electrical testing is performed on the substrate by probing at different test locations on the temporary test structure. All or part of the temporary test structure is removed so as not to affect product performance. The temporary test structure can contain electrical test pads which provide a way to make temporary connections to small interconnect landings or features at extreme tight pitch to fan them out to testable pads sizes and pitches.

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

A method of manufacturing a semiconductor device includes forming a first metal film on a first insulating region and a first metal region directly adjacent to the first insulating region, wherein the first metal film comprises a metal other than the metal of the first metal region, forming a second metal film on a second insulating region and a second metal region directly adjacent to the second insulating region, wherein the second metal film comprises a metal other than the metal of the second metal region, bringing the first metal film and the second metal film into contact with each other, and heat treating the first substrate and the second substrate and thereby electrically connecting the first metal region and the second metal region to each other and simultaneously forming an insulating interface film between the first insulating region and the second insulating region. 1. A method of manufacturing a semiconductor device comprising:providing a first substrate comprising a first surface including a first insulating region and at least one first metal region directly adjacent to the first insulating region;forming a first metal film on the first insulating region and the first metal region, wherein the first metal film comprises a metal other than the metal of the first metal region;providing a second substrate comprising a second surface including a second insulating region and at least one second metal region directly adjacent to the second insulating region;forming a second metal film on the second insulating region and the second metal region, wherein the second metal film comprises a metal other than the metal of the second metal region;bringing the first metal film and the second metal film into contact with each other so that the first surface of the first substrate faces the second surface of the second substrate; andheat treating the first substrate and the second substrate and thereby electrically connecting the first metal region and the second ...

Semiconductor device and data storage system including the same

A semiconductor device includes a first substrate structure including a first substrate, circuit devices, first interconnection lines, bonding metal layers on upper surfaces of the first interconnection lines, and a first bonding insulating layer on the upper surfaces of the first interconnection lines and on lateral surfaces of the bonding metal layers, and a second substrate structure on the first substrate structure, and including a second substrate, gate electrodes, channel structures, second interconnection lines, bonding vias connected to the second interconnection lines and the bonding metal layers and having a lateral surface that is inclined such that widths of the bonding vias increase approaching the first substrate structure, and a second bonding insulating layer in contact with at least lower portions of the bonding vias. The bonding metal layers include dummy bonding metal layers not connected to the bonding vias and that contacts the second bonding insulating layer.

LIGHT EMITTING APPARATUS AND METHOD FOR PRODUCING THE SAME

A light emitting apparatus includes: a mount substrate; at least one light emitting device mounted on the mount substrate; a light transparent member, wherein a lower surface of the light transparent member is attached to an upper surface of the at least one light emitting device via at least one adhesive material layer, wherein the light transparent member has a plate shape and is positioned to receive incident light emitted from the light emitting devices, and wherein a lateral surface of the light transparent member is located laterally inward of a lateral surface of the at least one light emitting device; and a covering member that contains a light reflective material and covers at least the lateral surface of the light transparent member.

Method and apparatus for die-to-die pad contact

A semiconductor device includes at least a first semiconductor die and a second semiconductor die. The first semiconductor dies comprises a first and second side, and includes at least a first contact pad located on the first side of the first semiconductor die. The second semiconductor die comprises a first and second side, and includes at least a second contact pad located on the first side of the second semiconductor die, wherein the first semiconductor die is stacked on the second semiconductor die and wherein the first side of the first semiconductor die faces the first side of the second semiconductor die. At least one voltage-guided conductive filament is created between the first contact pad and the second contact pad.

Semiconductor device structure with bottle-shaped through silicon via and method for forming the same

A semiconductor device structure includes a silicon layer disposed over a first semiconductor die, and a first mask layer disposed over the silicon layer. The semiconductor device structure also includes a second semiconductor die disposed over the first mask layer, and a through silicon via penetrating through the silicon layer and the first mask layer. A bottom surface of the through silicon via is greater than a top surface of the through silicon via, and the top surface of the through silicon via is greater than a cross-section of the through silicon via between and parallel to the top surface and the bottom surface of the through silicon via.

Semiconductor apparatus

A semiconductor apparatus according to an embodiment of the present invention includes: a plurality of semiconductor chips that are laminated; a plurality of penetration electrodes that penetrate in a lamination direction through the plurality of semiconductor chips and that electrically connect together the plurality of semiconductor chips; and a plurality of input/output elements that are configured to perform a signal input/output operation to the plurality of penetration electrodes, wherein the semiconductor chips are joined together via no bump, one of the plurality of input/output elements is connected to each of the plurality of penetration electrodes such that a functional element connected to each of the plurality of penetration electrodes performs an ON or OFF operation at a predetermined timing, and the input/output element connected to a first of two adjacent penetration electrodes among the plurality of penetration electrodes and the input/output element connected to a second of two adjacent penetration electrodes are configured to perform the signal input/output operation at a different timing from each other.

SEMICONDUCTOR DEVICES INCLUDING A THICK METAL LAYER

A semiconductor device includes a plurality of middle interconnections and a plurality of middle plugs, which are disposed in an interlayer insulating layer and on a substrate. An upper insulating layer is disposed on the interlayer insulating layer. A first upper plug, a first upper interconnection, a second upper plug, and a second upper interconnection are disposed in the upper insulating layer. Each of the plurality of middle interconnections has a first thickness. The first upper interconnection has a second thickness that is greater than the first thickness. The second upper interconnection has a third thickness that is greater than the first thickness. The third thickness is twice to 100 times the first thickness. The second upper interconnection includes a material different from the second upper plug. 1. A semiconductor device comprising:an interlayer insulating layer disposed on a substrate;a plurality of middle interconnections disposed in the interlayer insulating layer;a plurality of middle plugs disposed in the interlayer insulating layer and between the plurality of middle interconnections;an upper insulating layer disposed on the interlayer insulating layer;a first upper plug disposed in the upper insulating layer and connected to one middle interconnection of the plurality of middle interconnections, the one middle interconnection having a first thickness;a first upper interconnection disposed in the upper insulating layer on the first upper plug and having a second thickness, wherein the second thickness is greater than the first thickness;a second upper plug disposed in the upper insulating layer on the first upper interconnection;a second upper interconnection disposed in the upper insulating layer on the second upper plug and having a third thickness, wherein the third thickness is greater than the first thickness; andan opening configured to pass through the upper insulating layer to expose the second upper interconnection,wherein the third ...

Wafer Level Package (WLP) and Method for Forming the Same

A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a conductive pad formed on the substrate. The semiconductor device structure includes a protection layer formed over the conductive pad and a post-passivation interconnect (PPI) structure formed at least in the protection layer. The PPI structure is electrically connected to the conductive pad. The semiconductor device structure also includes a first moisture-resistant layer formed over the protection layer, and the protection layer and the first moisture-resistant layer are made of different materials. The semiconductor device structure further includes an under bump metallurgy (UBM) layer formed over the first moisture-resistant layer and connected to the PPI structure. 1. A semiconductor device comprising:a first conductive pad over a chip structure;a passivation layer over the first conductive pad;a first protection layer over the passivation layer;a post-passivation interconnect (PPI) pad extending through the first protection layer and the passivation layer, the PPI pad being coupled to the first conductive pad;an insulating layer surrounding sidewalls of the chip structure and the first protection layer;a second protection layer over the first protection layer and the insulating layer;a PPI structure extending through the second protection layer, the PPI structure being coupled to the PPI pad;a first moisture-resistant layer over the second protection layer and the PPI structure;a ball-like bump over the first moisture-resistant layer; anda second conductive pad over the ball-like bump.2. The semiconductor device of claim 1 , wherein at least a portion of the passivation layer is disposed between the PPI structure and the first conductive pad in a direction perpendicular to a major surface of the chip structure.3. The semiconductor device of claim 1 , further comprising an under bump metallurgy (UBM) extending through the ...

Bonded Structures for Package and Substrate

The embodiments described provide elongated bonded structures near edges of packaged structures free of solder wetting on sides of copper posts substantially facing the center of the packaged structures. Solder wetting occurs on other sides of copper posts of these bonded structures. The elongated bonded structures are arranged in different arrangements and reduce the chance of shorting between neighboring bonded structures. In addition, the elongated bonded structures improve the reliability performance.

Package With UBM and Methods of Forming

Package structures and methods of forming package structures are discussed. A package structure, in accordance with some embodiments, includes an integrated circuit die, an encapsulant at least laterally encapsulating the integrated circuit die, a redistribution structure on the integrated circuit die and the encapsulant, a connector support metallization coupled to the redistribution structure, a dummy pattern, a second dielectric layer, and an external connector on the connector support metallization. The redistribution structure comprises a first dielectric layer having a first surface disposed distally from the encapsulant and the integrated circuit die. The dummy pattern is on the first surface of the first dielectric layer and around the connector support metallization. The second dielectric layer is on the first surface of the first dielectric layer and on at least a portion of the dummy pattern. The second dielectric layer does not contact the connector support metallization. 1. A method comprising:encapsulating an integrated circuit die with an encapsulant;forming a redistribution structure on the integrated circuit die and the encapsulant, the redistribution structure comprising a first dielectric layer having a first surface distal from the integrated circuit die and the encapsulant;forming an under ball metallization (UBM) and a dummy pattern on the redistribution structure, the dummy pattern surrounding the UBM on the first surface of the first dielectric layer, the dummy pattern being electrically isolated; andforming a second dielectric layer on the first surface of the first dielectric layer and at least a portion of the dummy pattern, wherein after the forming the second dielectric layer, the second dielectric layer is physically spaced apart from the UBM, wherein the second dielectric layer covers an exterior portion of the dummy pattern laterally distal from the UBM and exposes an interior portion of the dummy pattern proximate the UBM.2. The ...

BUMP BONDED CRYOGENIC CHIP CARRIER

A technique relates to a device. First thin films are characterized by having a first opposing surface and a first connection surface in which the first connection surface is in physical contact with a first superconducting region. Second thin films are characterized by having a second opposing surface and a second connection surface in which the first and second opposing surfaces are opposite one another. The second connection surface is in physical contact with a second superconducting region. A solder material electrically connects the first and second opposing surfaces, and the solder material is characterized by maintaining a low ohmic electrical contact between the first and second opposing surfaces at temperatures below 100 degrees Kelvin. The first and second superconducting regions are formed of materials that have a melting point of at least 700 degrees Celsius. 1. A device comprising:a first plurality of thin films, the first plurality of thin films characterized by having a first opposing surface and a first connection surface, wherein the first connection surface is in physical contact with a first superconducting region;a second plurality of thin films, the second plurality of thin films characterized by having a second opposing surface and a second connection surface, the first and second opposing surfaces being opposite one another, wherein the second connection surface is in physical contact with a second superconducting region; anda solder material electrically connecting the first and second opposing surfaces, the solder material characterized by maintaining a low ohmic electrical contact between the first and second opposing surfaces at temperatures below 100 degrees Kelvin, wherein the first and second superconducting regions are comprised of materials that have a melting point of at least 700 degrees Celsius.2. The device of claim 1 , wherein the first and second plurality of thin films are electrically conductive.3. The device of claim 1 , ...