Leiterplatte mit verbesserten Positionierungsmitteln

Verfahren zur Positionierung eines elektrischen Schaltungselementes und Halterungselement zur Durchführung eines solchen Verfahrens

ELECTRICAL COMPONENTS AND MOUNTING THEREOF

Method for assembling e.g. two components in face to face manner, involves depositing volume of welding material on surface, where welding material comprises melting point, which is higher than that of another welding material

The method involves producing wetable surface (36) by a welding material on a face of a component (34), which is surrounded by a non-wetable surface by another welding material. Volume (40) of the latter welding material is deposited on the wetable surface, where the latter welding material comprises a melting point, which is higher than a melting point of the former welding material. A heating volume of latter welding material is applied to temperature greater than or equal to temperature at the melting point of latter welding material.

SEMICONDUCTOR INTEGRATED CIRCUIT

Semiconductor device and method of manufacturing semiconductor device

A semiconductor device includes a semiconductor element; a pad electrode that is formed on the semiconductor element; an alignment mark that is formed on the semiconductor element; a connection electrode that is formed on the pad electrode; and an underfill resin that is formed to cover the connection electrode. The height of the alignment mark from the semiconductor element is greater than that of the connection electrode.

FLIP-CHIP MODULE AND METHOD FOR THE PRODUCTION THEREOF

The invention relates to a flip-chip module comprising a semiconductor chip provided with contact columns, which are electrically and mechanically connected to a substrate. A spacer is provided between the substrate and the semiconductor chip and mechanically coupled with the substrate and/or the chip. Thermal stresses in the flip chip module are absorbed by the spacer and are kept away from the semiconductor chip. Said invention also relates to a method for producing a flip chip module consisting in placing the spacer between the semiconductor chip and the substrate and in soldering the contact columns with the substrate contact points. The use of the spacer makes it possible to accurately adjust the distance between the semiconductor chip and the substrate, thereby improving the quality of the soldering points.

METHOD FOR FORMING SOLDER BUMP INTERCONNECTIONS TO A SOLDER-PLATED CIRCUIT TRACE

A method for attaching an integrated circuit component (10) to a printed circuit board (12) by a plurality of solder bump interconnections (40) utilizes a printed circuit board comprising a solder-plated circuit trace. The trace includes terminals (20), each including a terminal pad (22) and a runner section (24). A solder plate (28) formed of a first solder alloy is applied to the terminal to extend continuously between the pad and the runner section. Solder bumps (30, 32) formed of second compositionally distinct solder alloy having a melting temperature greater than the first alloy are affixed to the component. The component and board are then assembled so that the bump (30) rests against the solder-plated terminal pads, and heated to a temperature effective to melt the solder plate but not the bump alloy. Upon cooling to resolidify the solder, the solder plate is fused to the bumps to form the interconnections.

Low stress vias

A component can include a substrate having a front surface and a rear surface remote therefrom, an opening extending from the rear surface towards the front surface, and a conductive via extending within the opening. The substrate can have a CTE less than 10 ppm/° C. The opening can define an inner surface between the front and rear surfaces. The conductive via can include a first metal layer overlying the inner surface and a second metal region overlying the first metal layer and electrically coupled to the first metal layer. The second metal region can have a CTE greater than a CTE of the first metal layer. The conductive via can have an effective CTE across a diameter of the conductive via that is less than 80% of the CTE of the second metal region.

Ball grid array IC package and manufacturing method thereof

A ball grid array IC package and manufacturing method thereof comprise spherical conductive balls that are changed into a shape having an hourglass type feature. A semiconductor chip having a plurality of chip pads, a substrate having ball lands, hourglass type conductive balls electrically connected to the chip pads and to the ball lands, and an interval maintaining member maintaining a uniform interval between the semiconductor chip and substrate. The method includes a heat treatment that expands the interval maintaining member to provide a uniform width between the surface of the chip and the substrate so that the conductive balls change into the hourglass shape, after which removal of the heat treatment decreases the size of the interval maintaining member so that the physical separation between the surfaces is provided by the connecting members having the hourglass shapes.

Mechanisms for forming hybrid bonding structures with elongated bumps

Embodiments of mechanisms for forming a package structure are provided. The package structure includes a semiconductor die and a substrate. The package structure includes a pillar bump and an elongated solder bump bonded to the semiconductor die and the substrate. A height of the elongated solder bump is substantially equal to a height of the pillar bump. The elongated solder bump has a first width, at a first horizontal plane passing through an upper end of a sidewall surface of the elongated solder bump, and a second width, at a second horizontal plane passing through a midpoint of the sidewall surface. A ratio of the second width to the first width is in a range from about 0.5 to about 1.1.

Stereolithographic method and apparatus for fabricating stabilizers for flip-chip type semiconductor devices and resulting structures

Stabilizers for placement on a surface of a semiconductor device component and methods for fabricating placing the stabilizers on semiconductor device components. Upon assembly of the semiconductor device component face down upon a higher level substrate and joining conductive structures between the contact pads of the semiconductor device component and corresponding contact pads of the higher level substrate, the stabilizers at least partially stabilize the semiconductor device component on the higher level substrate to prevent tilting or tipping of the semiconductor device component relative to the higher level substrate. The stabilizers can also be positioned and configured to define a minimum, substantially uniform distance between the semiconductor device component and the higher level substrate. The stabilizers may be either preformed structures or formed on the surface of the semiconductor device component. A stereolithographic method of fabricating the stabilizers is disclosed.

Semiconductor device

스택되는 다이들의 위치들을 제어하는 기술

... 조립 부품(100) 및 조립 부품을 이용하여 칩 패키지를 조립하는 기술이 설명된다. 이 칩 패키지는 수직 방향으로 스택 내에 배열되는 반도체 다이들(310-1 내지 310-N)의 세트를 포함하는데, 반도체 다이들은 수직 스택의 일 측에 계단형 테라스(112-1)를 정의하도록 수평 방향에서 서로 오프셋된다. 또한, 칩 패키지는 조립 부품(100)을 이용하여 조립될 수 있다. 특히, 조립 부품은 대략 칩 패키지의 계단형 테라스를 대략 미러링하는 계단형 테라스들(112-1, 112-2)의 쌍을 포함할 수 있고, 이 경사형 테라스들의 쌍은 칩 패키지의 조립 동안 수직 스택으로 반도체 다이들의 세트를 배치하는 조립 도구에 대해 수직 위치 레퍼런스를 제공한다.

OPTICAL CONNECTION THROUGH SINGLE ASSEMBLY OVERHANG FLIP CHIP OPTICS DIE WITH MICRO STRUCTURE ALIGNMENT

A system includes an optical transceiver assembly, including a flip chip connection of a semiconductor die with a photonic transceiver that overhangs a substrate to which it is to be connected. The assembly further includes an alignment pin that is held to the semiconductor die at a micro-engineered structure in the semiconductor die. The alignment pin provides passive alignment of the photonic transceiver with an optical lens that interfaces the photonic transceiver to one or more optical channels.

Integrated circuit package including in-situ formed cavity

A flip chip packaged component includes a die having a first surface and a dielectric barrier disposed on the first surface of the die. The dielectric barrier at least partially surrounds a designated location on the first surface of the die. A plurality of bumps is disposed on the first surface of the die on an opposite side of the dielectric barrier from the designated location. The flip chip packaged component further includes a substrate having a plurality of bonding pads on a second surface thereof. A cavity is defined by the first surface of the die, the dielectric barrier, and the substrate. A molding compound encapsulates the die and at least a portion of the substrate.

STACKING OF MULTIPLE DIES FOR FORMING THREE DIMENSIONAL INTEGRATED CIRCUIT (3DIC) STRUCTURE

Some embodiments of the present disclosure relate to a three dimensional integrated circuit (3DIC) structure. The 3DIC structure has a first die and a second die that is bonded to the first die by one or more bonding structures. The one or more bonding structures respectively have a first metal pad arranged on the first die and a second metal pad arranged on the second die. A first plurality of support structures are disposed between the first die and the second die. The first plurality of support structures include polymers and are laterally spaced apart from a closest one of the one or more bonding structures. The first plurality of support structures extend below an upper surface of the second metal pad.

RAMP-STACK CHIP PACKAGE WITH STATIC BENDS

Flip-chip module comprises a semiconductor chip having contact columns on a surface, a substrate with contact sites joined to the free ends of the contact columns and a rigid spacer arranged between the substrate and chip

Flip-chip module comprises a semiconductor chip (2) having contact columns (4) on a surface (3), a substrate (8) with contact sites (7) joined to the free ends of the contact columns and a rigid spacer (10) arranged between the substrate and chip. The spacer and substrate are connected to each other at sites distributed over its contact surfaces. An independent claim is also included for a method for producing a flip-chip module.

Low-stress vias

A component can include a substrate having a front surface and a rear surface remote therefrom, an opening extending from the rear surface towards the front surface, and a conductive via extending within the opening. The substrate can have a CTE less than 10 ppm/ DEG C. The opening can define an inner surface between the front and rear surfaces. The conductive via can include a first metal layer overlying the inner surface and a second metal region overlying the first metal layer and electrically coupled to the first metal layer. The second metal region can have a CTE greater than a CTE of the first metal layer. The conductive via can have an effective CTE across a diameter of the conductive via that is less than 80% of the CTE of the second metal region.

MODULE AND PRODUCTION METHOD

Die Erfindung gibt ein Modul an, welches ein Trägersubstrat (6) mit einer elektrische Verdrahtung und einen in Flip-Chip-Technik auf dem Trägersubstrat (6) montierten Bauelementchip aufweist, wobei der Bauelementchip (1) auf seiner zum Trägersubstrat (6) weisenden Oberfläche (2) Bauelementstrukturen (3), einen Stützrahmen (4) und Stützelemente (5) aufweist, die Stützelemente (5) eine elektrische Verbindung zwischen den Bauelementstrukturen (3) und der elektrischen Verdrahtung des Trägersubstrats (6) herstellen und die Höhe der Stützelemente und die Höhe des Stützrahmens (4) übereinstimmen. Ferner gibt die Erfindung ein Herstellungsverfahren für das Modul an.

Process for flip chip connecting a semiconductor chip

A process for a flip chip connection of a semiconductor chip includes the steps of forming a plurality of stud bumps on the semiconductor chip, on which a plurality of solder bumps are formed, in the vicinity of the outer periphery thereof and on the outside of the solder bumps, providing a cut groove between a plurality of the solder bumps and the stud bumps, mating the solder bumps on the semiconductor chip and the corresponding solder bumps on the circuit board and heating for subsequent integration of the mating solder bumps, and breaking way the outer peripheral portion of the semiconductor chip along the cutting groove after a flip chip connection in order to remove the stud bumps.

Electrical Component Having an Electrical Connection Arrangement and Method for the Manufacture Thereof

An electrical component and a method for the manufacture thereof, comprising a connection arrangement between an active surface of an electrical component and a carrier, wherein electrical connecting elements are disposed in a connection zone on the active surface and/or on the carrier, and at least one spacer element is provided, which is disposed on the active surface and/or on the carrier. The at least one spacer element has a smaller height than the connecting elements before the connecting elements are reflowed to produce the electrically conductive connection, and is preferably disposed in an edge region of the connection zone.

Solder ball protection in packages

An integrated circuit structure includes a substrate, a metal pad over the substrate, a passivation layer having a portion over the metal pad, and a polymer layer over the passivation layer. A Post-Passivation Interconnect (PPI) has a portion over the polymer layer, wherein the PPI is electrically coupled to the metal pad. The integrated circuit structure further includes a first solder region over and electrically coupled to a portion of the PPI, a second solder region neighboring the first solder region, a first coating material on a surface of the first solder region, and a second coating material on a surface of the second solder region. The first coating material and the second coating material encircle the first solder region and the second solder region, respectively. The first coating material is spaced apart from the second coating material.

ELECTRIC COMPONENT WITH A FLIP-CHIP CONSTRUCTION

The invention relates to an electric component comprising a carrier substrate (1), which has a thermal expansion coefficient αp and a chip (2), which is fixed onto the carrier substrate (1) in a flip-chip construction by means of bumps (31 to 34). In a preferred orientation x1, the chip (2) has a thermal expansion co-efficient α1, whereby Δα1 = |αp - α1| represents the first expansion differential. In a second preferred orientation x2, the chip (2) has a thermal expansion coefficient α2, whereby Δα2 = |αp - α2| represents the second expansion differential. Δx1 is the distance between the centres (310, 320) of the terminal bumps (31, 32) in the x1 orientation. Δx2 is the distance between the centres (330, 340) of the terminal bumps (33, 34) in the x2 orientation. The following applies: Δx1 < Δx2 when Δαx1 > Δα2 and Δx1 > Δx2 when Δα1 < Δα2. This enables the shear force that occurs during temperature modifications and that acts on the terminal bumps to be minimised.

Method for Aligning Micro-Electronic Components

Alignment of a first micro-electronic component to a receiving surface of a second micro-electronic component is realized by a capillary force-induced self-alignment, combined with an electrostatic alignment. The latter is accomplished by providing at least one first electrical conductor line along the periphery of the first component, and at least one second electrical conductor along the periphery of the location on the receiving surface of the second component onto which the component is to be placed. The contact areas surrounded by the conductor lines are covered with a wetting layer. The electrical conductor lines may be embedded in a strip of anti-wetting material that runs along the peripheries to create a wettability contrast. The wettability contrast helps to maintain a drop of alignment liquid between the contact areas so as to obtain self-alignment by capillary force. By applying appropriate charges on the conductor lines, electrostatic self-alignment is realized, which improves the alignment obtained through capillary force and maintains the alignment during evaporation of the liquid. 1. An assembly of at least two components , comprising:a first component and a second component;wherein each of the first component and the second component comprises a contact area covered by a wetting layer;wherein each of the first component and the second component comprises means for containing a liquid on the respective wetting layer;wherein each of the first component and the second component comprises one or more conductor lines running along a circumference of the respective contact area, wherein the one or more conductor lines of the first component are arranged to face the one or more conductor lines of the second component;and wherein at least one of the first component or the second component is provided with means for applying an electrical charge to the respective one or more conductor lines.2. The assembly according to claim 1 , wherein on at least one of ...

Semiconductor device of chip-on-chip structure

A semiconductor device including a first semiconductor chip, a second semiconductor chip bonded to the first semiconductor chip in a stacked relation, and a registration structure which causes the first and second semiconductor chips to be positioned with respect to each other by depression-projection engagement therebetween. The registration structure includes, for example, a registration recess provided on a surface of the first semiconductor chip, and a registration projection provided on a surface of the second semiconductor chip for engagement with the registration recess. The registration projection may be a spherical member provided on the surface of the second semiconductor chip.

Semiconductor chip for mounting on a semiconductor package substrate by a flip-clip process

A semiconductor chip for mounting on a package substrate by a flip-chip process includes a plurality of electrode pads of a first group provided on a major surface of the semiconductor chip for external electrical connection such that the electrode pads of the first group cover a major surface of the semiconductor chip in rows and columns; and a plurality of electrode pads of a second group each having a size substantially larger than the electrode pads of the first group and provided on the major surface of the semiconductor chip in electrical connection with an active part of the semiconductor chip that is used for a burn-in process. Each of the electrode pads of the first group is covered by a solder bump that projects from the major surface of the semiconductor chip a first distance. Each of the electrode pads of the second group is formed of a conductor material having a melting point higher than the solder bump and projecting from the major surface of the semiconductor chip a second ...

A reconnectable chip interface and chip package

An assembly of the present invention has a substrate and an integrated circuit device adapted to be electrically and mechanically connected to the substrate. Electrical connection pads on the circuit device and on the substrate contact one another when the circuit device and the substrate are connected. At least one first projection on one of the device and on the substrate and at least two second projections on the other of the device and the substrate each have a respective axial length and are sized and shaped for a close friction fit along their axial lengths when the projections are interdigitated relative to one another. An integrated circuit device package of the present invention includes an integrated circuit device and an interconnect substrate for mounting the circuit device on an electronic circuit substrate. The interconnect substrate mates with the active side of the circuit device to form an enclosed space.

Process for forming elongated solder connections between a semiconductor device and a supporting substrate

A process for forming elongated solder terminals (38) to connect a plurality of pads (21) on a semiconductor device (20) to a corresponding plurality of pads (12) on a supporting substrate (10) by, forming a means (32, 42) to maintain a predetermined vertical spacing between the semiconductor (20) and the supporting substrate (10) outside area of the pads, forming and fixing solder extenders (16) to each of the solder wettable pads on the substrate or the device to be joined, positioning the semiconductor device provided with solder mounds (22) on the solder mountable pads (21) over the supporting substrate with the solder mounds in registry with the pads (12) on the substrate with the solder extenders (16) positioned therebetween, the means to maintain vertical spacing located between and in abutting relation to the device and substrate, and heating the resulting assembly to reflow the solder mounds and the solder extenders while maintaining a predetermined spacing thus forming a plurality ...

Circuit board with improved positioning means

はんだバンプのセルフアライメントに利用するスタッドの作成

ダイ積層を介した小直径、高密度スルーウェーハのためのアラインメント/センタリングガイドの生成方法

... ダイ積層を形成するための方法が提供される。本方法は第一のダイに、複数のスルーウェーハビア(105)および第一の複数のアラインメントフィーチャ(104)を形成するステップを含む。第二の複数のアラインメントフィーチャ(116)は、第二のダイに形成され、第一のダイは第二のダイ上に積層され、第一の複数のアラインメントフィーチャは、第二の複数のアラインメントフィーチャと係合する。ダイ積層を製造する方法もまた提供され、その方法は、第一のダイ上に複数のスルーウェーハビアを形成するステップ、第一のダイ上に複数の凹部(104)を形成するステップ、ならびに第二のダイ上に複数の凸部(116)を形成するステップを含む。ダイ積層およびシステムも提供される。 ...

Halbleitervorrichtung

Es ist eine Halbleitervorrichtung vorgesehen mit einem Flip-Chip-Aufbau. Der Chip (1) des Aufbaus ist elektrisch mit dem Chipanbringungsteil (4) des Aufbaus über Funktionsbumps (2) verbunden, die auf dem Chip (1) vorgesehen sind. Blindbumps, die gegen eine lokale Biegekraft des Chips (1) wirken, sind zwischen dem Chip (1) und dem Chipanbringungsteil (4) vorgesehen. A semiconductor device with a flip-chip structure is provided. The chip (1) of the structure is electrically connected to the chip attachment part (4) of the structure via function bumps (2) which are provided on the chip (1). Blind bumps, which act against a local bending force of the chip (1), are provided between the chip (1) and the chip attachment part (4).

RFID tag and method of manufacturing the same

IMPROVED METHOD FOR PRODUCING A STRUCTURE FOR ASSEMBLING MICROELECTRONIC DEVICES

L'invention concerne la réalisation d'un dispositif microélectronique comprenant un substrat comportant au moins un plot conducteur ledit plot étant doté d'une face inférieure reposant sur le substrat et d'une face supérieure opposée à ladite face inférieure, ladite face supérieure dudit plot étant recouverte d'un empilement formé d'une couche conductrice et d'une couche de protection diélectrique comportant une ouverture dite première ouverture en regard dudit du plot et dévoilant ladite couche conductrice, au moins un bloc isolant (120a, 120b) étant agencé sur une zone périphérique de ladite face supérieure dudit plot, ledit bloc de isolant (120a, 120b) ayant une section transversale formant un contour fermé et comportant une ouverture dite deuxième ouverture, un pilier conducteur (130a, 130b) étant situé au centre dudit contour dans ladite deuxième ouverture. The invention relates to the production of a microelectronic device comprising a substrate comprising at least one conductive pad, said pad being provided with a lower face resting on the substrate and with an upper face opposite to said lower face, said upper face of said being covered with a stack formed of a conductive layer and a dielectric protection layer comprising an opening called the first opening facing said pad and revealing said conductive layer, at least one insulating block (120a, 120b) being arranged on a peripheral zone of said upper face of said pad, said insulating block (120a, 120b) having a cross section forming a closed contour and comprising an opening called a second opening, a conductive pillar (130a, 130b) being located at the center of said contour in said second opening.

RFID TAG AND METHOD OF MANUFACTURING THE SAME

본 발명은 비접촉으로 외부 기기와 정보의 교환을 행하는 RFID(Radio_ Frequency_IDentification) 태그 등에 관한 것으로, 안테나의 재료로서 페이스트를 채용하여 범프의 함몰을 방지한다. BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an RFID (Radio_Frequency_IDentification) tag or the like for exchanging information with an external device in a non-contact manner, and employs paste as a material of an antenna to prevent bumps from sinking. 회로 칩(11) 혹은 베이스(13)의 범프(16)에 인접한 위치에 범프(16)가 부착된 회로 칩(11)이 안테나(122)에 접속될 때의 압박력에 의한 범프(16)의 함몰을 억제하는 스토퍼(21)를 갖는다. Recession of bump 16 due to the pressing force when the circuit chip 11 with bump 16 is connected to antenna 122 at a position adjacent to bump 16 of circuit chip 11 or base 13. It has the stopper 21 which suppresses this.

Technique for controlling positions of stacked dies

Electronic device and method of manufacturing electronic device

An electronic device includes: a first electronic component; first members that are provided on a first surface of the first electronic component and that include outside surfaces configured to face diagonally upward with respect to the first surface; a second electronic component provided above the first surface; second members that are provided corresponding to the first members on a second surface of the second electronic component which faces the first surface and that include inside surfaces configured to face diagonally downward with respect to the second surface and configured to face the outside surfaces; and solder that is provided between the first surface and the second surface and that electrically connects the first electronic component and the second electronic component.

In-situ cavity integrated circuit package

Chip encapsulation body

SEMICONDUCTOR CHIP PACKAGE

A semiconductor chip package includes an integrated circuit chip and a substrate. A chip contact pad is formed on a first side of the chip. A stud is formed on the chip contact pad from wire using a wire bonding machine. The stud has a partially squashed ball portion bonded to the chip contact pad. The stud also has an elongated portion extending from the partially squashed ball portion. A first layer of insulating material is on a first side of the substrate. A bottomed well is formed in the first layer and opens to the first side of the substrate. A first conductive material at least partially fills the well. The first conductive material is electrically connected to at least one trace line in the substrate. The stud is partially embedded in the first conductive material to form an electrical connection between the chip and the substrate. © KIPO & WIPO 2007 ...

CHIP PACKAGING METHOD AND CHIP PACKAGE USING HYDROPHOBIC SURFACE

소수성 표면(hydrophobic surface)을 이용한 칩 패키징 방법은 제1 칩 또는 제1 보드 중 어느 하나 및 제2 칩 또는 제2 보드 중 어느 하나 각각의 표면에 미리 설정된 크기의 초소수성 표면을 형성하는 단계; 상기 제1 칩 또는 상기 제1 보드 중 어느 하나 및 상기 제2 칩 또는 상기 제2 보드 중 어느 하나 각각에 형성된 초소수성 표면 상의 미리 설정된 위치에 친수성 표면(hydrophilic surface)을 형성하는 단계; 상기 제1 칩 또는 상기 제1 보드 중 어느 하나 및 상기 제2 칩 또는 상기 제2 보드 중 어느 하나 각각에 형성된 친수성 표면에 액체 금속 볼(liquid metal ball)을 생성하는 단계; 및 상기 제1 칩 또는 상기 제1 보드 중 어느 하나의 액체 금속 볼 및 상기 제2 칩 또는 상기 제2 보드 중 어느 하나의 액체 금속 볼을 결합시킴으로써, 상기 제1 칩 또는 상기 제1 보드 중 어느 하나 및 상기 제2 칩 또는 상기 제2 보드 중 어느 하나를 패키징 하는 단계를 포함한다. A method of chip packaging using a hydrophobic surface includes forming a super-hydrophobic surface of a predetermined size on a surface of either the first chip or the first board and the second chip or the second board, respectively; Forming a hydrophilic surface at a predetermined position on a super-hydrophobic surface formed on either the first chip or the first board and on either the second chip or the second board; Forming a liquid metal ball on a hydrophilic surface formed on either the first chip or the first board and on either the second chip or the second board; And either one of the liquid metal ball of the first chip or the first board and the liquid metal ball of either the second chip or the second board, And packaging either the second chip or the second board.

Technique for controlling positions of stacked dies

An assembly component and a technique for assembling a chip package using the assembly component are described. This chip package includes a set of semiconductor dies that are arranged in a stack in a vertical direction, which are offset from each other in a horizontal direction to define a stepped terrace at one side of the vertical stack. Moreover, the chip package may be assembled using the assembly component. In particular, the assembly component may include a pair of stepped terraces that approximately mirror the stepped terrace of the chip package and which provide vertical position references for an assembly tool that positions the set of semiconductor dies in the vertical stack during assembly of the chip package.

METHOD OF ALIGNING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR STRUCTURE THEREOF

The invention relates to a method of aligning semiconductor devices in die stacking and a semiconductor structure fabricated by the method. In stacking a die on a wafer, for example, a first semiconductor device on the wafer and a second semiconductor device on the die are aligned by a magnetic force between at least a first magnetic body belonging to the wafer and at least a second magnetic body belonging to the die. After the alignment, the die is made not to move by the magnetic force between the magnetic bodies to maintain the alignment which is necessary for the fabrication of a semiconductor structure.

SEMICONDUCTOR CHIP PACKAGE

A semiconductor chip package includes an integrated circuit chip and a substrate. A chip contact pad is formed on a first side of the chip. A stud is formed on the chip contact pad from wire using a wire bonding machine. The stud has a partially squashed ball portion bonded to the chip contact pad. The stud also has an elongated portion extending from the partially squashed ball portion. A first layer of insulating material is on a first side of the substrate. A bottomed well is formed in the first layer and opens to the first side of the substrate. A first conductive material at least partially fills the well. The first conductive material is electrically connected to at least one trace line in the substrate. The stud is partially embedded in the first conductive material to form an electrical connection between the chip and the substrate.

THREE DIMENSIONAL INTEGRATED CIRCUIT (3DIC) WITH SUPPORT STRUCTURES

The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure has a first conductive layer on a first substrate and a second conductive layer on a second substrate. A bonding structure is disposed between the first conductive layer and the second conductive layer. A support structure is disposed between the first substrate and the second substrate. A passivation layer covers a bottom surface of the first conductive layer and has a lower surface facing an uppermost surface of the support structure.

Solder in cavity interconnection technology

An interconnection technology may use molded solder to define solder balls. A mask layer may be patterned to form cavities and solder paste deposited in the cavities. Upon heating, solder balls are formed. The cavity is defined by spaced walls to keep the solder ball from bridging during a bonding process. In some embodiments, the solder bumps connected to the solder balls may have facing surfaces which are larger than the facing surfaces of the solder ball.

Semiconductor package for flip-chip mounting process

Process for flip chip connecting semiconductor chip

PROCESS FOR FLIP CHIP CONNECTING SEMICONDUCTOR CHIP

PROCESS FOR FLIP CHIP CONNECTING SEMICONDUCTOR CHIP

A process for a flip chip connection is capable of improving the reliability of connection and the process can be easily practiced. The process comprises the steps of forming a plurality of stud bumps on the semiconductor chip, on which a plurality of solder bumps are formed, in the vicinity of the outer periphery thereof and outer side of the solder bumps, providing a cutting groove between a plurality of the solder bumps and the stud bumps, mating the solder bumps on the semiconductor chip and the corresponding solder bumps on the circuit board and heating for subsequent integration of the mating solder bumps, and breaking way the outer peripheral portion of the semiconductor chip along the cutting groove after a flip chip connection in order to remove the stud bumps.

Integrated circuit chip stack and electronic device

Semiconductor device and semiconductor manufacturing process

ELECTRIC COMPONENT WITH A FLIP-CHIP CONSTRUCTION

The invention relates to an electric component comprising a carrier substrate (1), which has a thermal expansion coefficient αp and a chip (2), which is fixed onto the carrier substrate (1) in a flip-chip construction by means of bumps (31 to 34). In a preferred orientation x1, the chip (2) has a thermal expansion co-efficient α1, whereby Δα1 = |αp - α1| represents the first expansion differential. In a second preferred orientation x2, the chip (2) has a thermal expansion coefficient α2, whereby Δα2 = |αp - α2| represents the second expansion differential. Δx1 is the distance between the centres (310, 320) of the terminal bumps (31, 32) in the x1 orientation. Δx2 is the distance between the centres (330, 340) of the terminal bumps (33, 34) in the x2 orientation. The following applies: Δx1 < Δx2 when Δαx1 > Δα2 and Δx1 > Δx2 when Δα1 < Δα2. This enables the shear force that occurs during temperature modifications and that acts on the terminal bumps to be minimised. © KIPO & WIPO 2007 ...

RAMP-STACK CHIP PACKAGE WITH STATIC BENDS

A ramp-stack chip package is described. This chip package includes a vertical stack of semiconductor dies or chips that are offset from each other in a horizontal direction, thereby defining a terrace with exposed pads. A high-bandwidth ramp component, which is positioned approximately parallel to the terrace, is electrically and mechanically coupled to the exposed pads. For example, the ramp component may be coupled to the semiconductor dies using: solder, microsprings and/or an anisotropic conducting film. Furthermore, each of the semiconductor dies includes a static bend so that an end segment of each of the semiconductor dies is parallel to the direction and is mechanically coupled to the ramp component. These end segments may facilitate high-bandwidth communication of signals between the chips and the ramp component, for example, via proximity communication.

BONDING APPARATUS AND BONDING METHOD

Provided is a bonding device that bonds electrodes on a semiconductor die and a substrate by using a metal nano-paste. A semiconductor die (12) having electrodes (12a) on which bumps are formed by injecting fine droplets of a metal nano-paste is placed face down on a circuit board (19) having electrodes (19a) on which bumps are formed, and the electrodes (12a) on the semiconductor die (12) and the electrodes (19a) on the circuit board (19) are overlapped each other with bonding bumps (250) interposed therebetween. After that, the gap between each of the overlapped electrodes (12a, 19a) is compressed to a predetermined gap (H3) smaller than the gap obtained when the electrodes (12a, 19a) are overlapped, thereby applying pressure on the bumps between the respective electrodes (12a, 19a). In addition, the bumps between the respective electrodes (12a, 19a) are heated and metal nano-particles of the bumps are pressed and sintered to form joint metals (300), so that the electrodes (12a, 19a) ...

RFID tag and method of manufacturing the same

The present invention provides a radio frequency identification (RFID) tag which exchanges information with an external device in a noncontact manner, in which a paste is used as a material for an antenna, and which is designed to prevent sinking of bumps. A stopper for limiting sinking of bumps of a circuit chip caused by a pressing force when the circuit chip is connected to an antenna is provided on the circuit chip or a base at a position adjacent to the bumps.

SINGLE-MELT ENHANCED RELIABILITY SOLDER ELEMENT INTERCONNECT

A method of joining first and second substrates through a solder element interconnect, the method including the steps of forming solder elements, such as solder balls, in a first array on a first substrate, forming pads of solder paste in a second array on a second substrate wherein the first and second arrays are mirror images of one another, establishing a standoff element on one of the first or second substrates, assembling the first and second substrates such that each of the solder elements on the first substrate are embedded in each of the solder paste pads and the standoff element is interposed between the first and second substrates, heating the first and second substrates at a preferred temperature to cause melting of the solder elements and the solder pads into single solder elements, wherein the standoff controls the separation distance between the first and second substrates.

Solder in cavity interconnection structures

The present disclosure relates to the field of fabricating microelectronic packages, wherein cavities are formed in a dielectric layer deposited on a first substrate to maintain separation between soldered interconnections. In one embodiment, the cavities may have sloped sidewalls. In another embodiment, a solder paste may be deposited in the cavities and upon heating solder structures may be formed. In other embodiments, the solder structures may be placed in the cavities or may be formed on a second substrate to which the first substrate may be connected. In still other embodiments, solder structures may be formed on both the first substrate and a second substrate. The solder structures may be used to form solder interconnects by contact and reflow with either contact lands or solder structures on a second substrate.

SURFACE-MOUNT COMPONENTS, METHODS OF MANUFACTURE THEREOF, AND MOUNTING METHODS EMPLOYING THE COMPONENTS

A surface-mount electronic component (20) comprises a substrate (2), a contact pad (8) on a first surface (2a) of the substrate (2), and a solder-stop frame (6) surrounding the contact pad (8). The solder-stop frame (6) delimits a solder-reception space (7) designed to receive solder material in contact with an accessible portion of the contact pad (8). During mounting of the surface-mount electronic component (20) on a mounting board (40), the contact pad of the surface-mount electronic component (20) becomes bonded to a landing pad (42) on the mounting board (40) using solder in the solder-reception space (7), whereby there is reduced tilt of the mounted component. The surface-mount component may be pre-bumped, that is, provided with a flat bonding bump in the solder-reception space (7). Methods of manufacture of the surface-mount components, and mounting methods using the surface-mount components are also described.

RFID TAG AND MANUFACTURING METHOD THEREFOR

PROBLEM TO BE SOLVED: To provide an RFID (Radio_Frequency_IDentification) tag and the like for exchanging information with an external device in a non-contact fashion, in which a bump is prevented from sinking by adopting paste as an antenna material. SOLUTION: A stopper 21 for preventing the sinking of the bump 16 caused by pressing force applied when a circuit chip 11 with the bump 16 is connected to an antenna 122 is provided at a position where the circuit chip 11 or a base 13 is adjacent to the bump 16. COPYRIGHT: (C)2006,JPO&NCIPI ...

ELECTRICAL COMPONENTS AND MOUNTING THEREOF

... 1299541 Beam lead integrated circuits; assembing components WESTERN ELECTRIC CO Inc 15 Jan 1970 [21 Jan 1969 (2) 29 April 1969] 1998/70 Headings H1K and H1R A method of assembling an electrical component, e.g. a beam lead integrated circuit, in a predetermined position relative to external circuitry comprises providing co-operating ferromagnetic means in or affixed to the electrical component and the external circuitry such that the magnetic force exerted by the co-operating magnetic means serves to align the component in the predetermined position. The ferromagnetic means associated with the component may be in the leads or on the body of the component and may be in the form of a coating applied by, for example, sputtering, evaporating or plating or may be deposited during production of the component as an embedded layer. The ferromagnetic means associated with the external circuitry may be integral therewith or in the form of a coating. Alternatively, an electromagnet may be affixed to ...

PROCESS FOR FLIP CHIP CONNECTING SEMICONDUCTOR CHIP

Layered semiconductor device and manufacturing method thereof

Semiconductor device, solid-state imaging device and imaging apparatus

IMPROVED PROCESS FOR PRODUCING A STRUCTURE FOR ASSEMBLING MICROELECTRONIC DEVICES

L'invention concerne la réalisation d'un dispositif microélectronique comprenant un substrat comportant au moins un plot conducteur ledit plot étant doté d'une face inférieure reposant sur le substrat et d'une face supérieure opposée à ladite face inférieure, ladite face supérieure dudit plot étant recouverte d'un empilement formé d'une couche conductrice et d'une couche de protection diélectrique comportant une ouverture dite première ouverture en regard dudit du plot et dévoilant ladite couche conductrice, au moins un bloc isolant (120a, 120b) étant agencé sur une zone périphérique de ladite face supérieure dudit plot, ledit bloc de isolant (120a, 120b) ayant une section transversale formant un contour fermé et comportant une ouverture dite deuxième ouverture, un pilier conducteur (130a, 130b) étant situé au centre dudit contour dans ladite deuxième ouverture.

IN-SITU CAVITY INTEGRATED CIRCUIT PACKAGE

Semiconductor device and method of manufacturing the semiconductor device

According to one embodiment, a first electrode is formed on a first face of a first semiconductor chip, and a second electrode and a protrusion are formed on a second face of a second semiconductor chip. The first semiconductor chip and the second semiconductor chip are spaced from one another by the protrusion in such a manner that the first face and the second face face each other. The first semiconductor chip and the second semiconductor chip are subject to reflow to be electrically connected to each other, and then the protrusion is cured at a temperature lower than a reflow temperature.

Rfid tag and method of manufacturing the same

SOLDER IN CAVITY INTERCONNECTION STRUCTURES

The present disclosure relates to the field of fabricating microelectronic packages, wherein cavities are formed in a dielectric layer deposited on a first substrate to maintain separation between soldered interconnections. In one embodiment, the cavities may have sloped sidewalls. In another embodiment, a solder paste may be deposited in the cavities and upon heating solder structures may be formed. In other embodiments, the solder structures may be placed in the cavities or may be formed on a second substrate to which the first substrate may be connected. In still other embodiments, solder structures may be formed on both the first substrate and a second substrate. The solder structures may be used to form solder interconnects by contact and reflow with either contact lands or solder structures on a second substrate.

Method of fabricating integrated circuit module

An integrated circuit module having microscopic self-alignment features comprises: 1) an integrated circuit chip having a plurality of input/output pads in a pattern on a surface thereof; 2) an interconnect member having a surface which includes input/output pads in a pattern that matches the pattern of pads on the integrated circuit chip; and, 3) one of the surfaces has a predetermined number of holes of one-half to fifty mils deep and the other surface has a predetermined number of protrusions of one-half to fifty mils high which are shaped to fit into the holes and prevent the surfaces from sliding on each other when the input/output pads on both of the surfaces are aligned.

Semiconductor structure and manufacturing method thereof

A semiconductor structure includes a semiconductor substrate and a pad. The pad is on a top surface of the semiconductor substrate. The semiconductor structure further includes a circuit board and a bump. The circuit board has a contact area corresponding to the pad on the top surface of the semiconductor substrate, and the bump is between the pad on the top surface of the semiconductor substrate and the contact area, wherein the contact area is a non-metallic surface.

Air cavity mold

Conventional packages for 5G applications suffer from disadvantages including high mold stress on the die, reduced performance, and increased keep-out zone. To address these and other issues of the conventional packages, it is proposed to pre-apply a wafer-applied material, which remains in place, to form an air cavity between the die and the substrate. The air cavity can enhance the die's performance. Also, since the wafer-applied material can remain in place, the keep-out zone can be reduced. As a result, higher density modules can be fabricated.

Method of fabricating integrated circuit chip package

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

PROBLEM TO BE SOLVED: To provide a semiconductor package which assures an easier and stable sealing process and also provide a method of manufacturing the same package. SOLUTION: A semiconductor package comprises a tape substrate 5 in which wirings are provided on the front surface thereof, a bump 3, a supporting member 4, and a semiconductor chip 1 provided on the tape substrate 5 via the bump 3 and supporting member 4. The bump 3 is electrically connected to the wirings of tape substrate 5 but the supporting member 4 is not electrically connected to the wirings on the tape substrate. COPYRIGHT: (C)2003,JPO ...

ANORDNUNG AUS SUBSTRAT UND BAUELEMENT UND VERFAHREN ZUR HERSTELLUNG

Halbleitersubstrat, Halbleiterchip, Halbleiterbauteil und Verfahren zur Herstellung eines Halbleiterbauteils

Halbleiterbauteil mit zumindest einem Halbleiterchip, der ein Halbleitersubstrat aus einem monokristallinen Material mit einer Kristallstruktur K aufweist, wobei das Halbleitersubstrat einen oder mehrere Bereiche mit einer von außen aufgeprägten, permanenten Krümmung aufweist und die Kristallstruktur K in diesen Bereichen gestaucht und/oder geweitet und/oder verzerrt ist, wobei das Halbleiterbauteil ein Montagesubstrat zur Aufnahme des Halbleiterchips aufweist und der Halbleiterchip über Bonddrähte elektrisch mit dem Montagesubstrat verbunden ist.

In-situ cavity integrated circuit package

A flip chip semiconductor packaging device and method that incorporates in situ formation of cavities underneath selected portions of a die during a flip chip die bonding process. A method of flip chip semiconductor component packaging includes providing a die having a first surface, forming a barrier on first surface of the die, the barrier at least partially surrounding a designated location on the first surface of the die, bonding the die to a substrate in a flip chip configuration, and flowing molding compound over the die and over at least a portion of the substrate. Bonding the die to the substrate includes causing contact between the barrier and the substrate such that flow of the molding compound is blocked by the barrier to provide a cavity between the die and the substrate, the cavity being proximate the designated location on the first surface of the die.

Method of assembling a silicon stacked semiconductor package

Solder ball protection in packages

An integrated circuit structure includes a substrate, a metal pad over the substrate, a passivation layer having a portion over the metal pad, and a polymer layer over the passivation layer. A Post-Passivation Interconnect (PPI) has a portion over the polymer layer, wherein the PPI is electrically coupled to the metal pad. The integrated circuit structure further includes a first solder region over and electrically coupled to a portion of the PPI, a second solder region neighboring the first solder region, a first coating material on a surface of the first solder region, and a second coating material on a surface of the second solder region. The first coating material and the second coating material encircle the first solder region and the second solder region, respectively. The first coating material is spaced apart from the second coating material.

Stereolithographic method and apparatus for fabricating spacers for semiconductor devices and resulting structures

Insulative spacers to be disposed on a surface of a semiconductor device component and methods of fabricating and placing the insulative spacers on semiconductor device components. Upon assembly of the semiconductor device component face-down upon a higher level substrate and establishing electrical communication between the semiconductor device component and the higher level substrate, the insulative spacers define a minimum, substantially uniform distance between the semiconductor device component and the higher level substrate. The insulative spacers also prevent tilting or tipping of the semiconductor device component relative to the higher level substrate. The insulative spacers may be preformed or fabricated on a surface of the semiconductor device component. A stereolithographic method for fabricating the insulative spacers is disclosed, which may employ a machine vision system to recognize the position and orientation of a substrate to which material is to be applied and control ...

Magnetic contacts

Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with magnetic contacts, as well as corresponding fabrication methods and systems incorporating such magnetic contacts. A first IC substrate may have a first magnet coupled with a first electrical routing feature. A second IC substrate may have a second magnet coupled with a second electrical routing feature. The magnets may be embedded in the IC substrates and/or electrical routing features. The magnets may generate a magnetic field that extends across a gap between the first and second electrical routing features. Electrically conductive magnetic particles may be applied to one or both of the IC substrates to form a magnetic interconnect structure that extends across the gap. In some embodiments, magnetic contacts may be demagnetized by heating the magnets to a corresponding partial demagnetization temperature (PDT) or Curie temperature. Other embodiments may be described and/or claimed.

Semiconductor device

A semiconductor device includes a first semiconductor substrate, a second semiconductor substrate, a bonding electrode, and a dummy electrode. The first semiconductor substrate has a first surface and a first wiring, and contains a first semiconductor material. The second semiconductor substrate has a second surface and a second wiring, and contains a second semiconductor material, and the first surface and the second surface face each other. The bonding electrode is arranged between the first surface and the second surface, and is electrically connected to the first wiring and the second wiring. The dummy electrode is arranged between the first surface and the second surface, and is electrically insulated from at least one of the first wiring and the second wiring. The bonding electrode has a bonding bump and a first bonding pad. The dummy electrode has a dummy bump and a first dummy pad.

RAMP-STACK CHIP PACKAGE WITH STATIC BENDS

Ball grid array IC package and manufacturing method thereof

A kind of ball grid array package structure and its manufacturing method are disclosed in the present invention. According to the present invention, the conductive ball can be easily manufactured to have a rough-grain sandglass shape. The invented ball grid array package contains the followings: a semiconductor chip 210 formed with plural chip pads 212; rough-grain shaped conductive balls 215 connected electrically with each chip pad 212; the substrate 200 for mounting the conductive balls; and the separation maintaining member 230 for maintaining a constant separation between the semiconductor chip and the substrate.

SEMICONDUCTOR CHIP PACKAGE

A semiconductor chip package includes an integrated circuit chip (22) and a substrate (24). A chip contact pad (42) is formed on a first side (44) of the chip (22). A stud (46) is formed on the chip contact pad (42) from wire using a wire bonding machine. The stud (46) has a partially squashed ball portion (47) bonded to the chip contact pad (42). The stud (46) also has an elongated portion extending from the partially squashed ball portion. A first layer (48) of insulating material is on a first side (50) of the substrate (24). A bottomed well (54) is formed in the first layer (48) and opens to the first side (50) of the substrate (24). A first conductive material (60) at least partially fills the well (54). The first conductive material (60) is electrically connected to at least one trace line (64) in the substrate (24). The stud (46) is partially embedded in the first conductive material (60) to form an electrical connection between the chip (22) and the substrate (24).

Semiconductor device and manufacturing method of semiconductor device

A through electrode and a multilayer wiring are provided on a semiconductor substrate, and a bottom layer connection wiring, a lower layer connection wiring, an upper layer connection wiring, and a top layer connection wiring are provided in the multilayer wiring. The through electrode is connected to the bottom layer connection wiring, and a via is arranged at a position other than a position immediately above the through electrode.

Semiconductor chip having a supporting member, tape substrate, semiconductor package having the semiconductor chip and the tape substrate, and the method of manufacturing the same

A semiconductor chip includes a substrate having a main surface, the main surface including a flame-shaped first area, which is along sides of the main surface, and a second area encompassed by the first area, a pad formed in the first area and a bump electrode formed on the pad, and at least one supporting member formed in the second area.

Electric component with a flip-chip construction

A component includes a carrier substrate having a coefficient of thermal expansion alphap and a chip mounted on the carrier substrate by a plurality of bumps. The chip has a first coefficient of thermal expansion alpha1 in a first direction x1 and a first expansion difference, Deltaalpha1 equal to the absolute value of alphap-alpha1. The chip also has a second coefficient of thermal expansion alpha2 in a second direction x2 and a second expansion difference Deltaalpha2 is equal to the absolute value of alphap-alpha2,. The bumps are arranged such that a first distance, Deltax1, corresponding to a normal projection of a line between centers of terminally situated bumps in the first direction onto an axis running parallel to direction x1 is less than a second distance corresponding to a normal projection of a line between centers of terminally situated bumps in the second direction onto an axis parallel to direction x2.

METHOD AND APPARATUS FOR FACILITATING PROXIMITY COMMUNICATION AND POWER DELIVERY

The described embodiments provide a system that facilitates inter-chip alignment for proximity communication and power delivery. The system includes a first integrated circuit chip and a second integrated circuit chip, both of which whose surfaces have corresponding etch pit wells configured to align with each other. A shaped structure is placed in an etch pit well of the first integrated circuit chip such that when the corresponding etch pit well of the second integrated circuit chip is substantially aligned with the etch pit well of the first integrated circuit chip, the shaped structure mates with both the etch pit well of the first integrated circuit chip and with the corresponding etch pit well of the second integrated circuit chip, thereby aligning the first integrated circuit chip with the second integrated circuit chip. In some embodiments the etch pit wells include conductive structures for routing power through a conductive shaped structure.

METHOD OF CREATING ALIGNMENT/CENTERING GUIDES FOR SMALL DIAMETER, HIGH DENSITY THROUGH-WAFER VIA DIE STACKING

Semiconductor chip package

ball grid array package and method of fabricating the same

Semiconductor Structures and Method for Fabricating the Same

A semiconductor structure is provided. The semiconductor structure includes a first substrate, a second substrate opposite to the first substrate, a plurality of spacers disposed between the first substrate and the second substrate, and an adhesive material bonded with the first substrate and the second substrate within the two adjacent spacers. The invention also provides a method for fabricating the semiconductor structure.

Semiconductor device and method of fabricating the semiconductor device

A semiconductor device includes a first device including a first substrate and a first external connection terminal for connecting outside the first device; a second device stacked on the first device, the second device including a second substrate and a second external connection terminal for connecting outside the second device; an adhesive pattern disposed between the first device and second device, the adhesive pattern disposed in locations other than locations where the first external connection terminal and second external connection terminal are disposed, and the adhesive pattern causing the first device and second device, when stacked, to be spaced apart by a predetermined distance; and a plated layer disposed between and electrically and physically connecting the first external connection terminal and the second external connection terminal.

Semiconductor Device and Method of Forming a Metallurgical Interconnection Between a Chip and a Substrate in a Flip Chip Package

A method for forming metallurgical interconnections and polymer adhesion of a flip chip to a substrate includes providing a chip having a set of bumps formed on a bump side thereof and a substrate having a set of interconnect points on a metallization thereon, providing a measured quantity of a polymer adhesive in a middle region of the chip on the bump side, aligning the chip with the substrate so that the set of bumps aligns with the set of interconnect points, pressing the chip and the substrate toward one another so that a portion of the polymer adhesive contacts the substrate and the bumps contact the interconnect points, and heating the bumps to a temperature sufficiently high to form a metallurgical connection between the bumps and the interconnect points.

Substrate and semiconductor device

A substrate includes a base member having a predetermined thickness, and an electrode array provided in one surface in a thickness direction of the base member and having a plurality of electrodes arranged two-dimensionally in a plan view, and the electrode array includes a central portion and an incremental region provided around the central portion in the planar view and is formed so that a height of the electrodes in the incremental region gradually increase as approaching toward the central portion.

Semiconductor device, solid-state imaging device, and imaging device

A semiconductor device includes a first substrate, a second substrate, a connection part, and an alignment mark. The connection part includes a first electrode which is disposed on the first substrate, a second electrode which is disposed on the second substrate, and a connection bump which connects the first electrode and the second electrode. The alignment mark includes a first mark which is disposed on the first substrate and a second mark which is disposed on the second substrate. A sum of a height of the first mark and a height of the second mark is substantially equal to a sum of a height of the first electrode, a height of the second electrode, and a height of the connection bump.

Method and apparatus for manufacturing a semiconductor device including a plurality of semiconductor chips connected with bumps

A method for manufacturing a semiconductor device including a plurality of semiconductor chips includes steps of placing, on a first semiconductor chip, a second semiconductor chip, such that a plurality of bumps is located between the first semiconductor chip and the second semiconductor chip, determining a distance between the first semiconductor chip and the second semiconductor chip, and determining whether or not the distance is within a predetermined range and stopping placement of additional chips if the distance is determined to be outside the predetermined range.

CHIP ALIGNMENT UTILIZING SUPEROMNIPHOBIC SURFACE TREATMENT OF SILICON DIE

Certain embodiments of the present disclosure provide a method for soldering a chip onto a surface. The method generally includes forming a bonding pad on the surface on which the chip is to be soldered, wherein the bonding pad is surrounded, at least in part, by dielectric material. The method may also include treating the dielectric material to render the dielectric material superomniphobic, and soldering the chip onto the bonding pad. 1. An apparatus , comprising:a bonding pad formed on a surface, wherein the bonding pad is surrounded, at least in part, by dielectric material, and wherein the dielectric material is treated to render the dielectric material superomniphobic; anda chip soldered onto the bonding pad.2. The apparatus of claim 1 , wherein the chip comprises a bonding pad claim 1 , and wherein the bonding pad on the surface is aligned with the bonding pad of the chip.3. The apparatus of claim 1 , wherein the surface comprises a surface of another chip or a substrate.4. The apparatus of claim 1 , wherein the dielectric material comprises a different surface energy than the bonding pad.5. The apparatus of claim 1 , wherein the dielectric material comprises silicon dioxide.6. An apparatus for soldering a chip onto a surface claim 1 , comprising: form a bonding pad on the surface on which the chip is to be soldered, wherein the bonding pad is surrounded, at least in part, by dielectric material;', 'treat the dielectric material to render the dielectric material superomniphobic; and', 'solder the chip onto the bonding pad., 'a processing system configured to7. The apparatus of claim 6 , wherein the chip comprises a bonding pad claim 6 , and wherein the processing system is configured to solder the chip onto the bonding pad on the surface by:applying solder to the bonding pad of the chip;placing the chip on the bonding pad on the surface; andreflowing the solder to enable surface tension alignment of the bonding pad of the chip with the bonding pad on the ...

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

A semiconductor structure includes a semiconductor substrate; a first pad and a second pad on a first top surface of the semiconductor substrate; a circuit board including a second top surface, a recess indented from the second top surface into the circuit board, a polymeric pad disposed on the second top surface and corresponding to the first pad, and an active pad disposed within the recess and corresponding to the second pad; a first bump disposed between and contacting the polymeric pad and the first pad; and a second bump disposed between and contacting the active pad and the second pad, wherein a height of the first bump is substantially shorter than a height of the second bump. 2. The semiconductor structure of claim 1 , wherein the height of the second bump is substantially equal to a total of the height of the first bump and a thickness of the polymeric pad.3. The semiconductor structure of claim 1 , wherein a depth of the recess is substantially equal to a thickness of the active pad.4. The semiconductor structure of claim 1 , wherein a first angle between the first bump and the polymeric pad is substantially greater than a second angle between the second bump and the active pad.5. The semiconductor structure of claim 1 , wherein the second angle is about 10% to 30% smaller than the first angle.6. The semiconductor structure of claim 1 , wherein the second top surface of the circuit board is substantially coplanar with a third top surface of the active pad.7. The semiconductor structure of claim 1 , wherein an aspect ratio of the first bump is substantially less than an aspect ratio of the second bump.8. The semiconductor structure of claim 1 , wherein the first bump is electrically isolated from the circuit board by the polymeric pad.9. The semiconductor structure of claim 1 , wherein a width of the active pad is substantially equal to a width of the polymeric pad.10. The semiconductor structure of claim 1 , wherein a thickness of the active pad is ...

ALIGNING BUMPS IN FAN-OUT PACKAGING PROCESS

A method includes placing a first package component and a second package component over a carrier. The first conductive pillars of the first package component and second conductive pillars of the second package component face the carrier. The method further includes encapsulating the first package component and the second package component in an encapsulating material, de-bonding the first package component and the second package component from the carrier, planarizing the first conductive pillars, the second conductive pillars, and the encapsulating material, and forming redistribution lines to electrically couple to the first conductive pillars and the second conductive pillars. 1. A method comprising:placing a first package component and a second package component over a carrier, wherein first conductive pillars of the first package component and second conductive pillars of the second package component face the carrier;encapsulating the first package component and the second package component in an encapsulating material;de-bonding the first package component and the second package component from the carrier;planarizing the first conductive pillars, the second conductive pillars, and the encapsulating material; andforming redistribution lines to electrically couple to the first conductive pillars and the second conductive pillars.2. The method of claim 1 , wherein when the encapsulating is performed claim 1 , surfaces of the first conductive pillars and the second conductive pillars are aligned to substantially a same plane.3. The method of further comprising dispensing an underfill between the carrier and the first package component and between the carrier and the second package component claim 1 , wherein in the planarizing claim 1 , the underfill is also planarized.4. The method of further comprising:forming a plurality of metal pads over the carrier;bonding the first conductive pillars and the second conductive pillars to the plurality of metal pads; ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE

According to one embodiment, a first electrode is formed on a first face of a first semiconductor chip, and a second electrode and a protrusion are formed on a second face of a second semiconductor chip. The first semiconductor chip and the second semiconductor chip are spaced from one another by the protrusion in such a manner that the first face and the second face face each other. The first semiconductor chip and the second semiconductor chip are subject to reflow to be electrically connected to each other, and then the protrusion is cured at a temperature lower than a reflow temperature. 1. A method of manufacturing a semiconductor device , comprising:forming a first electrode comprising a metal on a first face of a first semiconductor chip;forming a second electrode comprising a metal, and a protrusion, on a second face of a second semiconductor chip;aligning the first semiconductor chip with the second semiconductor chip such that the first face and the second face face each other;electrically connecting the first semiconductor chip and the second semiconductor chip at a temperature that is higher than a melting point temperature of at least one metal contained in the first electrode and the second electrode; andcuring the protrusion at a temperature that is lower than the melting point temperature of the metals contained in the first electrode and the second electrode after electrically connecting the first semiconductor chip and the second semiconductor chip.2. The method according to claim 1 , further comprising:filling an underfill resin between the first face and the second face after curing the protrusion, and then curing the underfill resin.3. The method according to claim 1 ,wherein the protrusion comprises a plurality of columnar bodies extending from the second face.4. The method according to claim 3 ,wherein the plurality of columnar bodies are formed using a photolithographic process.5. The method according to claim 1 ,wherein the first ...

SOLDER IN CAVITY INTERCONNECTION STRUCTURES

The present disclosure relates to the field of fabricating microelectronic packages, wherein cavities are formed in a dielectric layer deposited on a first substrate to maintain separation between soldered interconnections. In one embodiment, the cavities may have sloped sidewalls. In another embodiment, a solder paste may be deposited in the cavities and upon heating solder structures may be formed. In other embodiments, the solder structures may be placed in the cavities or may be formed on a second substrate to which the first substrate may be connected. In still other embodiments, solder structures may be formed on both the first substrate and a second substrate. The solder structures may be used to form solder interconnects by contact and reflow with either contact lands or solder structures on a second substrate. 1. A microelectronic device , comprising:a first substrate having a plurality of bond pads proximate a first surface of the first substrate;a first dielectric layer disposed over the first substrate bond pads and the first substrate contact surface having a plurality of cavities extending therethrough to corresponding bond pads;a second substrate having a plurality of contact lands proximate a contact surface of the second substrate;a second dielectric layer on the second substrate surface adjacent the plurality of second substrate contact lands having a plurality of cavities extending therethrough to corresponding contact lands;a solder interconnection between the first substrate bond pads and the second substrate contact lands;an underfill material between the first dielectric layer and the second dielectric layer, wherein a portion of the underfill material extends into the plurality of cavities extending through the first dielectric layer and into the plurality of cavities extending through the second dielectric layer.2. The microelectronic device of claim 1 , wherein the plurality of cavities extending through the first dielectric layer each ...

Stacked device and method of manufacturing the same

A stacked device encompasses a lower chip including a plurality of wiring lands and a plurality of wall-block patterns, each of the wall-block patterns is allocated at a position except locations where the wiring lands are disposed, each of the wall-block patterns has a inclined plane, a height of each of the wall-block patterns measured from a reference plane of the array of the wiring lands is higher than the wiring lands, and an upper chip including a plurality of wiring bumps assigned correspondingly to the positions of the wiring lands, respectively, and a plurality of cone bumps assigned correspondingly to the positions of the wall-block patterns, respectively.

Chip package and method for forming the same

A chip package including a semiconductor substrate is provided. A recess is in the semiconductor substrate and adjoins a side edge of the semiconductor substrate, wherein the semiconductor substrate has at least one spacer protruding from the bottom of the recess. A conducting layer is disposed on the semiconductor substrate and extends into the recess.

LOW STRESS VIAS

A component can include a substrate having a front surface and a rear surface remote therefrom, an opening extending from the rear surface towards the front surface, and a conductive via extending within the opening. The substrate can have a CTE less than 10 ppm/° C. The opening can define an inner surface between the front and rear surfaces. The conductive via can include a first metal layer overlying the inner surface and a second metal region overlying the first metal layer and electrically coupled to the first metal layer. The second metal region can have a CTE greater than a CTE of the first metal layer. The conductive via can have an effective CTE across a diameter of the conductive via that is less than 80% of the CTE of the second metal region. 1. A method of fabricating a component , comprising:forming an opening extending from a rear surface of a substrate towards a front surface of the substrate remote therefrom, the opening defining an inner surface between the front and rear surfaces, the substrate consisting essentially of a material having a CTE less than 10 ppm/° C.; andforming a conductive via including forming a first metal layer overlying the inner surface of the opening and forming a second metal region overlying the first metal layer and electrically coupled to the first metal layer, the second metal region having a CTE greater than a CTE of the first metal layer,the conductive via having an effective CTE across a diameter of the conductive via that is less than 80% of the CTE of the second metal region.2. A method as claimed in claim 1 , wherein the step of forming the opening includes performing a first anisotropic etch process to produce an initial inner surface and a second process to smooth the initial inner surface to become the inner surface claim 1 , the first anisotropic etch process and the second process producing a transition surface between the opening and at least one of the front or rear surfaces claim 1 , wherein a radius of the ...

Semiconductor device and method of manufacturing semiconductor device

A semiconductor device including a semiconductor element; a pad electrode that is formed on the semiconductor element; an alignment mark that is formed on the semiconductor element; a connection electrode that is formed on the pad electrode; and an underfill resin that is formed to cover the connection electrode. The height of the alignment mark from the semiconductor element is greater than that of the connection electrode.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate and a metal holder. The substrate includes at least one bonding pad disposed adjacent to its surface and the metal holder is disposed adjacent to the bonding pad. 1. A semiconductor device , comprising:a substrate having a surface, the substrate including at least one bonding pad disposed adjacent to the surface; anda metal holder disposed adjacent to the bonding pad.2. The semiconductor device of claim 1 , wherein the metal holder comprises a cavity.3. The semiconductor device of claim 2 , wherein the cavity of the metal holder has a cup-like shape.4. The semiconductor device of claim 1 , wherein the metal holder has a sidewall claim 1 , wherein the sidewall slopes at one end.5. The semiconductor device of claim 1 , wherein the metal holder has a sidewall claim 1 , the sidewall has an inner surface and an outer surface opposite to the inner surface claim 1 , and the outer surface slopes down toward the surface of the substrate.6. The semiconductor device of claim 5 , wherein the inner surface is substantially perpendicular to a surface of the bonding pad.7. The semiconductor device of claim 1 , wherein the metal holder has a pincer-like shape.8. The semiconductor device of claim 1 , further comprising an insulation layer disposed adjacent to the surface of the substrate claim 1 , wherein the insulation layer defines an opening exposing a portion of the bonding pad claim 1 , and the metal holder is disposed in the opening of the insulation layer.9. A semiconductor device claim 1 , comprising:a first substrate having a surface, the first substrate including at least one bonding pad disposed adjacent to the surface; anda metal element disposed adjacent to the bonding pad, wherein the metal element is adapted to fit a metal holder disposed adjacent to a surface of a second substrate.10. The semiconductor device of claim 9 , wherein the metal holder ...

Die interconnect

One example embodiment discloses a chip having a chip area, wherein the chip area includes: an overhang area; a rigid coupling area, having a set of rigid coupling points, located on one side of the overhang area; and a flexible coupling area, having a set of flexible coupling points, located on a side of the overhang area opposite to the a rigid coupling area. Another example embodiment discloses a method for fabricating a die interconnect, comprising: fabricating a rigid coupler area, having a set of rigid coupler points, within a chip having a chip area; defining an overhang area within the chip area and abutted to the rigid coupler area; and fabricating a flexible coupler area, having a set of flexible coupler points, within the chip area abutted to a side of the overhang area opposite to the rigid coupler area.

Magnetic alignment for flip chip microelectronic devices

Incorporating at least one magnetic alignment structure on a microelectronic device and incorporating at least one alignment coil within a microelectronic substrate, wherein the alignment coil may be powered to form a magnetic field to attract the magnetic alignment structure, thereby aligning the microelectronic device to the microelectronic substrate. After alignment, the microelectronic device may be electrically attached to the substrate. Embodiments may include additionally incorporating an alignment detection coil within the microelectronic substrate, wherein the alignment detection coil may be powered to form a magnetic field to detect variations in the magnetic field generated by the alignment coil in order verify the alignment of the microelectronic device to the microelectronic substrate.

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

A semiconductor structure includes a semiconductor substrate; a first pad and a second pad on a top surface of the semiconductor substrate; a circuit board including a polymeric pad and an active pad corresponding to the first pad and the second pad on the top surface of the semiconductor substrate respectively; a first bump disposed between the polymeric pad and the first pad; and a second bump disposed between the active pad and the second pad; wherein a first thickness of the polymeric pad is greater than a second thickness of the active pad. 1. A semiconductor structure , comprising:a semiconductor substrate;a first pad and a second pad on a top surface of the semiconductor substrate;a circuit board including a polymeric pad and an active pad corresponding to the first pad and the second pad on the top surface of the semiconductor substrate respectively:a first bump disposed between the polymeric pad and the first pad; anda second bump disposed between the active pad and the second pad, wherein a first thickness of the polymeric pad is greater than a second thickness of the active pad.2. The semiconductor structure of claim 1 , wherein the circuit board comprises a first recess and a second recess claim 1 , and the polymeric pad and the active pad are disposed within the first recess and the second recess respectively.3. The semiconductor structure of claim 2 , wherein a width of the polymeric pad is substantially less than a width of the first recess.4. The semiconductor structure of claim 2 , wherein a width of the active pad is substantially less than a width of the second recess.5. The semiconductor structure of claim 1 , wherein the polymeric pad is protruded from a top surface of the circuit board.6. The semiconductor structure of claim 1 , wherein the polymeric pad is electrically insulative.7. The semiconductor structure of claim 1 , wherein the first bump and the second bump have a first height and a second height respectively claim 1 , and the second ...

MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE

A method for forming a semiconductor structure includes: providing a semiconductor substrate having a first pad and a second pad on a top surface of the semiconductor substrate; providing a circuit board having an active pad and a non-metallic surface; providing a first solder ball and a second solder ball on the active pad and the non-metallic surface respectively; attaching the first pad and the second pad on the first solder ball and the second solder ball respectively; and reflowing the first solder ball and the second solder ball to form a first bump wetted on the active pad and a second bump not wetted on the non-metallic surface. 1. A method for forming a semiconductor structure , comprising:providing a semiconductor substrate, having a first pad and a second pad on a top surface of the semiconductor substrate;providing a circuit board having an active pad and a non-metallic surface;providing a first solder ball and a second solder ball on the active pad and the non-metallic surface respectively;attaching the first pad and the second pad on the first solder ball and the second solder ball respectively; andreflowing the first solder ball and the second solder ball to form a first bump wetted on the active pad and a second bump not wetted on the non-metallic surface.2. The method of claim 1 , wherein reflowing the first solder ball and the second solder ball to form the first bump wetted on the active pad and the second bump not wetted on the non-metallic surface comprises:reflowing the first solder ball and the second solder ball to cause the second bump to elongate the first bump.3. The method of claim 1 , further comprising:providing a recessed portion on a surface of the circuit board for accommodating the active pad.4. The method of claim 1 , wherein a first contact angle is formed between a first contact surface of the first bump on the active pad and a surface of the active pad claim 1 , a second contact angle is formed between a second contact surface ...

Semiconductor device

本发明涉及半导体器件。所述半导体器件包括：半导体元件；位于所述半导体元件上的钝化层；位于所述半导体元件上的焊盘电极，其通过所述钝化层中的开口暴露；位于所述焊盘电极和所述钝化层上的阻挡层；位于所述焊盘电极上的连接电极；以及从所述半导体元件延伸的对准标记，其中，所述钝化层的一部分位于所述对准标记与所述半导体元件之间，且所述阻挡层的一部分位于所述对准标记与所述钝化层之间。根据本发明，能够提供能够容易辨认出对准标记并能够容易精确地对准位置的半导体器件。

Process for flip-chip connection of a semiconductor chip

A process for flip-chip connection comprises the steps of forming a plurality of spacer bumps 9 on the periphery of the semiconductor chip 6, forming a plurality of solder bumps 5 on the main chip surface, providing a cutting groove 10 between the solder bumps 5 and the spacer 9, aligning the solder bumps 5 on the semiconductor chip with the corresponding solder bumps on the circuit board 7, heating the assembly in order to merge the mating solder bumps 5 and thus to form the flip-chip connection, and breaking away the outer peripheral portion of the semiconductor chip 6 along the cutting groove 10 thereby removing the spacer bumps 9. <IMAGE>

Chip package and method for forming same

本发明提供一种晶片封装体及其制造方法，该晶片封装体包括：一半导体基底；一凹口，位于半导体基底内，其中半导体基底具有至少一间隔部，该至少一间隔部突出于凹口的一底部；以及一导线，设置于半导体基底上，且延伸至凹口内。本发明能够降低与导线电性连接的导电结构的高度，进而有效降低晶片封装体的整体尺寸，且可避免导线发生短路的问题，进而提升晶片封装体的可靠度。

Method for forming solder bump interconnections to a solder plated circuit trace

내용없음. None.

Wiring board, manufacture thereof, wiring board mounted with board, and manufacture thereof

(57)【要約】 【課題】 フリップチップ等の位置合わせやその接合な どを、精度良くしかも容易に行なうことができる配線基 板及びその製造方法、並びに被搭載基板を搭載した配線 基板及びその製造方法を提供すること。 【解決手段】 配線基板３の表面の（接続用パッド１７ も含めて）全てを覆うように、周知の感光性エポキシ樹 脂を厚み０．４ｍｍで塗布し、感光性エポキシ樹脂層２ １を形成する。次に、感光性エポキシ樹脂層２１上に、 突起形成部のみに孔２３が明けられた露光マスク２５を 載せ、感光性エポキシ樹脂層２１の突起形成部のみに紫 外線を当てて露光を行なう。その後、現像して余分な樹 脂を除去することによって、樹脂による位置決め用突起 ４を形成する。

Electronic component mounting method

Manufacture of semiconductor device

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Method of alinging integrated circuit package

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Packaging structure and method

A method for forming metallurgical interconnections and polymer adhesion of a flip chip to a substrate includes providing a chip having a set of bumps formed on a bump side thereof and a substrate having a set of interconnect points on a metallization thereon, providing a measured quantity of a polymer adhesive in a middle region of the chip on the bump side, aligning the chip with the substrate so that the set of bumps aligns with the set of interconnect points, pressing the chip and the substrate toward one another so that a portion of the polymer adhesive contacts the substrate and the bumps contact the interconnect points, and heating the bumps to a temperature sufficiently high to form a metallurgical connection between the bumps and the interconnect points. Also, a flip chip package is made by the method. In some embodiments the metallurgical connection includes an alloy of gold and tin at the interface between the bumps and the interconnect points.

Package and method of manufacturing the same

一種方法包括將第一封裝組件以及第二封裝組件置放在載體上。第一封裝組件的第一導電柱以及第二封裝組件的第二導電柱面向載體。所述方法更包括將第一封裝組件以及第二封裝組件包封在包封材料中，將第一封裝組件以及第二封裝組件自載體剝離，平坦化第一導電柱、第二導電柱以及包封材料，以及形成重佈線以電耦接至第一導電柱以及第二導電柱。

Packaging structure and method

기판(16)에 플립칩(12)을 폴리머 접착시키고 야금연결시키기 위한 방법은 범프 측면에 형성된 한쌍의 범프를 갖는 칩을 제공하고, 야금위에 한쌍의 연결지점을 갖는 기판을 제공하며, 범프 측면 위에 있는 칩의 중간영역에 일정량의 폴리머 접착제를 제공하며, 한 쌍의 연결지점과 범프과 정렬되도록 기판과 함께 칩을 정렬시키고, 폴리머 접착제가 기판과 범프가 연결지점을 접촉시키도록 서로를 향해 기판 및 칩을 누르며, 범프와 연결지점 사이에 야금을 형성하기에 충분히 높은 온도로 범프를 가열하는 것을 포함한다. 또한 플립칩(12) 패키지는 이러한 방법으로 만들어진다. 몇가지 실시예에서 야금 연결부는 범프(14) 및 연결지점(18) 사이의 경계부에 있는 금과 주석 합금을 포함한다.

Electronic device

반도체 장치와 기판의 접속부가 Cu 등의 금속 볼과 금속 볼과 Sn과의 화합물로 이루어지며, 금속 볼은 화합물에 의해 연결되어 있다. The connection part of a semiconductor device and a board | substrate consists of a compound of metal balls, such as Cu, a metal ball, and Sn, and the metal balls are connected by the compound.

Printed circuit board with improved positioning means

Semiconductor module

<P>PROBLEM TO BE SOLVED: To provide an electronic apparatus assembled by temperature-hierarchical bonding using a solder capable of maintaining a bonding strength at high temperature, a new solder paste, a method of solder bonding, and a soldered joint structure. <P>SOLUTION: A connection between a semiconductor device and a substrate is formed of metal balls made of Cu or the like and compounds formed of metal balls and Sn, and the metal balls are bonded together by the compounds. <P>COPYRIGHT: (C)2005,JPO&amp;NCIPI

Solder

온도 계층적 접합에서 고온측 땜납 접합을 실현하는 땜납에서, 반도체 장치와 기판 사이의 접합부는 Cu 등으로 이루어진 금속 볼과 금속 볼 및 Sn으로 형성된 화합물로 형성되며, 금속 볼은 화합물에 의해 서로 접합된다. Cu 합금 볼, Cu-Sn 합금 볼, Ni-Sn 합금 볼, Zn-Al계 합금 볼, Au-Sn계 합금 볼, 금속 볼, Cu3Sn 화합물, 땜납

Solder in cavity interconnection structures

The present disclosure relates to the field of fabricating microelectronic packages, wherein cavities are formed in a dielectric layer deposited on a first substrate to maintain separation between soldered interconnections. In one embodiment, the cavities may have sloped sidewalls. In another embodiment, a solder paste may be deposited in the cavities and upon heating solder structures may be formed. In other embodiments, the solder structures may be placed in the cavities or may be formed on a second substrate to which the first substrate may be connected. In still other embodiments, solder structures may be formed on both the first substrate and a second substrate. The solder structures may be used to form solder interconnects by contact and reflow with either contact lands or solder structures on a second substrate.

Solder composition for electronic devices

Each of junctions formed between a semiconductor device and a substrate comprises metal balls of Cu, or other materials and compounds of Sn and the metal balls, and the metal balls are bonded together by the compounds.

Alignment bumps in fan-out packaging process

一种方法包括将第一封装组件和第二封装组件放置在载体上方。第一封装组件的第一导电柱和第二封装组件的第二导电柱朝向载体。该方法还包括将第一封组件和第二封装组件密封在密封材料中；将第一封装组件和第二封装组件从载体脱粘；平坦化第一导电柱、第二导电柱和密封材料，以及形成再分布线以电连接至第一导电柱和第二导电柱。本发明实施例涉及一种封装件及其形成方法，更具体地，涉及扇出封装工艺中的对准凸块。

Electronic component, manufacturing method, and method for establishing an electrical connection between the component and a circuit board

Elektronisches Bauteil mit wenigstens einem Halbleiterchip (2) und mit einer auf dem Halbleiterchip (2) aufgebrachten Umverdrahtungsschicht, wobei die Umverdrahtungsschicht elastische Kontaktelemente (8) von geringer mechanischer Festigkeit in den Raumausrichtungen x, y und z aufweist, wobei der Halbleiterchip oder die Umverdrahtungsschicht wenigstens zwei Abstandshalter (6) zwecks stabiler mechanischer Verbindung mit einer Leiterplatte (4) aufweist, und wobei die elastischen Kontaktelemente (8) mit korrespondierenden Kontaktanschlußflächen (12) der Leiterplatte (9) elektrische Verbindungen herstellen. Electronic component with at least one semiconductor chip (2) and with a redistribution layer applied to the semiconductor chip (2), the redistribution layer having elastic contact elements (8) of low mechanical strength in the spatial orientations x, y and z, wherein the semiconductor chip or the redistribution layer at least has two spacers (6) for the purpose of a stable mechanical connection to a printed circuit board (4), and the elastic contact elements (8) with corresponding contact pads (12) of the printed circuit board (9) produce electrical connections.

Solder

本发明涉及一种焊料，在温度层级结合中实现高温端焊接结合，其中，半导体装置与衬底之间的连接部分通过由Cu之类构成的金属球以及由金属球和Sn构成的化合物而形成，并且金属球通过化合物而结合在一起。

Flip chip bonding method for semiconductor chips

A process for flip-chip connection comprises the steps of forming a plurality of spacer bumps 9 on the periphery of the semiconductor chip 6, forming a plurality of solder bumps 5 on the main chip surface, providing a cutting groove 10 between the solder bumps 5 and the spacer 9, aligning the solder bumps 5 on the semiconductor chip with the corresponding solder bumps on the circuit board 7, heating the assembly in order to merge the mating solder bumps 5 and thus to form the flip-chip connection, and breaking away the outer peripheral portion of the semiconductor chip 6 along the cutting groove 10 thereby removing the spacer bumps 9. <IMAGE>

Method for forming solder bump interconnections to a solder-plated circuit trace

Un procédé permettant de fixer un composant (10) de circuit intégré à une plaquette de circuits imprimés (12) par l'intermédiaire d'une multiplicité d'interconnexions par bosses de contact (40), consiste à utiliser une plaquette de circuits imprimés comprenant un ruban de circuit métallisé. Le ruban comporte des plages de connexion (20), dont chacune est pourvue d'une pastille (22) et d'une piste conductrice (24). Une couche métallisée (28) composée d'un premier alliage de soudure est appliquée sur la plage de connexion de façon à s'étendre sans interruption entre la pastille et la piste conductrice. Des bosses de contact (30, 32), composées d'un second alliage de soudure, de composition différente, et dont la température de fusion est supérieure à celle du premier alliage, sont fixées au composant. Celui-ci et la plaquette sont ensuite assemblés de façon que la bosse (30) prend appui sur les pastilles métallisées, et chauffés jusqu'à une température permettant de fondre la couche métallisée mais non l'alliage de la bosse. Lorsque la soudure se solidifie à nouveau en refroidissant, la couche métallisée se fusionne aux bosses pour produire les interconnexions. A method for attaching an integrated circuit component (10) to a printed circuit board (12) via a plurality of contact bump interconnections (40), includes using a printed circuit board comprising a metallic circuit tape. The ribbon has connection pads (20), each of which is provided with a pad (22) and a conductive track (24). A metallized layer (28) composed of a first solder alloy is applied to the connection pad so as to extend without interruption between the patch and the conductive track. Contact bumps (30, 32), composed of a second solder alloy, of different composition, and whose melting temperature is higher than that of the first alloy, are fixed to the component. The latter and the plate are then assembled so that the bump (30) bears on the metallized pellets, ...

Flexible stack packages, electronic systems including the same, and memory cards invluding the same

本发明提供柔性层叠封装体。柔性层叠封装体包括顺序层叠的第一单元封装体和第二单元封装体。第一单元封装体和第二单元封装体中的每个具有固定区和浮动区。第一单元封装体的固定区通过固定部而连接且固定至第二单元封装体的固定区。

Semiconductor device and method of manufacturing semiconductor device

A semiconductor device including a semiconductor element; a pad electrode that is formed on the semiconductor element; an alignment mark that is formed on the semiconductor element; a connection electrode that is formed on the pad electrode; and an underfill resin that is formed to cover the connection electrode. The height of the alignment mark from the semiconductor element is greater than that of the connection electrode.

Optical display package and the method thereof

The present invention includes a substrate with a glass plate, a plurality of oxide wires on the glass plate and a plurality of flip chip bumps on the oxide wires and an integrated circuit chip with a plurality of bump pads. The substrate and the integrated circuit chip are hot pressed with a predetermined bonding pressure and temperature to bond the bump pads to the flip chip bumps respectively by eutectic bonding.

Composite interconnect

A composite interconnect system includes a plurality of carbon nanotubes, a plurality of solder balls and standoff balls disposed on a first device to provide a connection to a second device. A die-attached substrate includes a substrate and one or more die disposed on the substrate by a die-attach composite interconnect. The die-attach composite interconnect includes a plurality of carbon nanotubes, solder bumps, and standoff balls disposed on the die to provide one or more connections to the substrate. A PCB-attached substrate package includes a substrate package and one or more die disposed on the substrate package. The substrate package is disposed on a PCB by a PCB-attach composite interconnect. The PCB-attach composite interconnect includes a plurality of carbon nanotubes, solder balls, and standoff balls disposed on the substrate package to provide one or more connections to the PCB.

Flip chip integrated circuit packages with spacers

In a described example, an apparatus includes a semiconductor substrate and at least two pillar bumps formed on an active surface of the semiconductor substrate, the at least two pillar bumps extending away from the active surface and having ends spaced from the semiconductor substrate with solder material at the ends of the at least two pillar bumps. At least one spacer is formed on the active surface of the semiconductor substrate, the at least one spacer extending a predetermined distance from the active surface of the semiconductor substrate. A package substrate has a die mount area on a first surface including portions receiving the ends of the at least two pillar bumps and receiving an end of the at least one spacer. Mold compound covers the semiconductor substrate, the at least two pillars, the at least one spacer, and at least a portion of the semiconductor substrate.

Flip-chip package and fabricating process thereof

A flip-chip package is described. The flip-chip package includes a chip, a substrate, supporters and electrically conductive adhesive bumps. The electrically conductive adhesive bumps are located between the chip and the substrate electrically connecting the bonding pads on the former and the bump pads on the latter, wherein each electrically conductive adhesive bump has a smaller diameter at the central portion thereof than at the end portions thereof. The supporters are also disposed between the chip and the substrate surrounding the active area of the chip, so that the chip can be supported on the substrate.

Method of fabricating integrated circuit chip package

Semiconductor device components with structures for stabilizing the semiconductor device components upon flip-chip arrangement with high-level substrates

Semiconductor device components include a substrate with contact pads and at least one stabilizer protruding from the contact pad-bearing surface of the substrate. The at least one stabilizer may include adjacent, mutually adhered regions. Each region includes dielectric material. The at least one stabilizer is configured to at least partially stabilize the semiconductor device component upon assembly of the semiconductor device component in flip-chip fashion relative to a higher level substrate, preventing tilting or tipping of the semiconductor device component relative to the higher level substrate. The at least one stabilizer may be configured and positioned to define a minimum, substantially uniform distance between the semiconductor device component and the higher level substrate.

Method for producing a flip-chip structure for assembling microelectronic devices comprising an insulating block for guiding a connecting element and corresponding device

The method involves forming stack and protective dielectric layer having first opening, on microelectronic device. An insulating block (120a,120b) comprising second opening is formed on peripheral region above upper surface of conductive pad. A conductive pillar (130a,130b) is formed in openings. The height of conductive pillar and insulating block are provided, such that void space is maintained between top of conductive pillar and mouth region of second opening. A protective dielectric layer and the conductive layer are etched using insulating block as protective mask. An independent claim is included for a connecting microelectronic device.

Method for connecting an integrated circuit to a substrate and corresponding circuit arrangement

Verfahren zur Verbindung einer integrierten Schaltung (1), insbesondere von einem Chip oder einem Wafer oder einem Hybrid, mit einem Substrat (30), welches folgende Schritte aufweist: Vorsehen einer ersten elektrischen Kontaktstruktur (3, 4) auf einer ersten Hauptfläche (HF1) der integrierten Schaltung (1); Vorsehen einer entsprechenden zweiten elektrischen Kontaktstruktur (33) auf einer Oberseite (OS) des Substrats (30); wobei mindestens eine der ersten und zweiten elektrischen Kontaktstrukturen (3, 4; 33) elastische Erhebungen (3) auf- weist; Anbringen einer zweiten Hauptfläche (HF2) der integrierten Schaltung (1) an einer Rahmenstruktur (20, 22), die die integrierte Schaltung (1) mit einem ringförmen Teilbereich (22) zumindest teilweise seitlich umgibt; Aufsetzen der ersten elektrischen Kontaktstruktur (3, 4) auf die zweite elektrische Kontaktstruktur (33), so dass beide in elektrischem Kontakt stehen, wobei ein Zwischenraum (G) zwischen dem unteren Ende des ringförmigen Teilbereichs (22) und der Oberseite (OS) des Substrats (30) bei Normaltemperatur, beispielsweise bei Raumtemperatur, vorhanden... Method for connecting an integrated circuit (1), in particular a chip or a wafer or a hybrid, with a substrate (30), which comprises the following steps: Providing a first electrical contact structure (3, 4) on a first main surface (HF1) of the integrated circuit (1); Providing a corresponding second electrical contact structure (33) on an upper side (OS) of the substrate (30); wherein at least one of the first and second electrical contact structures (3, 4, 33) has elastic elevations (3); Attaching a second main surface (HF2) of the integrated circuit (1) to a frame structure (20, 22) which at least partially laterally surrounds the integrated circuit (1) with a ring-shaped portion (22); Placing the first electrical contact structure (3, 4) on the second electrical contact structure (33), so that both are in electrical contact, wherein a gap (G) between the lower end ...

Semiconductor device and semiconductor module

Electronics

Method and apparatus for facilitating proximity communication and power delivery

The described embodiments provide a system that facilitates inter-chip alignment for proximity communication and power delivery. The system includes a first integrated circuit chip and a second integrated circuit chip, both of which whose surfaces have corresponding etch pit wells configured to align with each other. A shaped structure is placed in an etch pit well of the first integrated circuit chip such that when the corresponding etch pit well of the second integrated circuit chip is substantially aligned with the etch pit well of the first integrated circuit chip, the shaped structure mates with both the etch pit well of the first integrated circuit chip and with the corresponding etch pit well of the second integrated circuit chip, thereby aligning the first integrated circuit chip with the second integrated circuit chip. In some embodiments the etch pit wells include conductive structures for routing power through a conductive shaped structure.

Low-stress vias

A component can include a substrate having a front surface and a rear surface remote therefrom, an opening extending from the rear surface towards the front surface, and a conductive via extending within the opening. The substrate can have a CTE less than 10 ppm/° C. The opening can define an inner surface between the front and rear surfaces. The conductive via can include a first metal layer overlying the inner surface and a second metal region overlying the first metal layer and electrically coupled to the first metal layer. The second metal region can have a CTE greater than a CTE of the first metal layer. The conductive via can have an effective CTE across a diameter of the conductive via that is less than 80% of the CTE of the second metal region.

Low-stress vias

A component can include a substrate having a front surface and a rear surface remote therefrom, an opening extending from the rear surface towards the front surface, and a conductive via extending within the opening. The substrate can have a CTE less than 10 ppm/° C. The opening can define an inner surface between the front and rear surfaces. The conductive via can include a first metal layer overlying the inner surface and a second metal region overlying the first metal layer and electrically coupled to the first metal layer. The second metal region can have a CTE greater than a CTE of the first metal layer. The conductive via can have an effective CTE across a diameter of the conductive via that is less than 80% of the CTE of the second metal region.

Method of manufacturing an integrated circuit

A method of manufacturing an integrated circuit including a first isolated chip electrically and mechanically connected via wafer bonding to a second isolated chip, wherein the active faces of the chips face one another, includes: forming metallic contact zones on active faces of first and second wafers, positioning and fixing the wafers one above another at a predetermined distance such that the active faces of the wafers face one another and the contact zones are aligned, placing the fixed wafers in a bath for electroless metal deposition onto the contact zones; and removing the fixed wafers in the event that the metal layers growing on the aligned contact zones of the first and second wafers have grown together.

Integrated circuit with interface tile for coupling to a stacked-die second integrated circuit

A general purpose interface tile of a first integrated circuit includes a plurality of micropads. A second integrated circuit may be stacked on the first integrated circuit such that signals from the second integrated circuit are communicated through the micropads and the interface tile to other circuitry on the first integrated circuit. Similarly, signals from the first integrated circuit are communicated through the interface tile and the micropads to the second integrated circuit. In the event that the first integrated circuit is a programmable logic device having a programmable interconnect structure, the interface tile is part of and hooks into the programmable interconnect structure and provides a general purpose mechanism for coupling signals from the second integrated circuit to the programmable interconnect structure and/or for coupling signals from the programmable interconnect structure to the second integrated circuit.

Solder ball protection in packages

An integrated circuit structure includes a substrate, a metal pad over the substrate, a passivation layer having a portion over the metal pad, and a polymer layer over the passivation layer. A Post-Passivation Interconnect (PPI) has a portion over the polymer layer, wherein the PPI is electrically coupled to the metal pad. The integrated circuit structure further includes a first solder region over and electrically coupled to a portion of the PPI, a second solder region neighboring the first solder region, a first coating material on a surface of the first solder region, and a second coating material on a surface of the second solder region. The first coating material and the second coating material encircle the first solder region and the second solder region, respectively. The first coating material is spaced apart from the second coating material.

Manufacturing method of semiconductor device

Semiconductor device and method of manufacturing semiconductor device

【課題】接続電極を覆うアンダーフィル樹脂が形成されている場合にも、アライメントマークの認識が容易な半導体装置を提供する。 【解決手段】半導体素子１１と、半導体素子１１に形成されたパッド電極１２と、半導体素子１１に形成されたアライメントマーク１５と、パッド電極１２上に形成された接続電極と、接続電極を覆うように形成されたアンダーフィル樹脂１８とを備える半導体装置１０を構成する。そして、この半導体装置１０は、半導体素子１１からの高さが接続電極よりも大きいアライメントマーク１５を備える。 【選択図】図１

Wiring substrate and display device including the same

An active matrix substrate includes a first substrate and a driving integrated circuit chip mounted on the first substrate. A support member is provided between the active matrix substrate and the driving IC chip so as to be in contact with both the active matrix substrate and the driving IC chip.

Semiconductor device structure with air gap and method for forming the same

The present disclosure discloses a semiconductor device structure with an air gap for reducing capacitive coupling and a method for forming the semiconductor device structure. The semiconductor device structure includes a first conductive pad over a first semiconductor substrate, and a first conductive structure over the first conductive pad. The semiconductor device structure also includes a second conductive structure over the first conductive structure, and a second conductive pad over the second conductive structure. The second conductive pad is electrically connected to the first conductive pad through the first and the second conductive structures. The semiconductor device structure further includes a second semiconductor substrate over the second conductive pad, a first passivation layer between the first and the second semiconductor substrates and covering the first conductive structure, and a second passivation layer between the first passivation layer and the second semiconductor substrate. The first and the second passivation layers surround the second conductive structure, and a first air gap is enclosed by the first and the second passivation layers.

Structure for packaging and method for manufacturing the same

本發明關於一種封裝結構及其製造方法，其中封裝結構包含至少二金屬件設置於基板或半導體元件上，並在金屬件周圍設有圖案層與絕緣層，金屬件相對於圖案層與絕緣層具有一間隙，藉此避免金屬件於接合電路時溢出，進而避免短路或漏電流的情況發生。

Method for connecting an integrated circuit to a substrate and corresponding circuit arrangement

A process for connecting an integrated circuit (1), especially a chip, wafer or hybrid, with a substrate (30) provides corresponding electrical contacts on the IC (3,4) and substrate (33), at least one of which is elastically elevated and bringing the IC to a frame (22) and joining the electrical contacts together by compressing the elastic elevation. An Independent claim is also included for the device formed as above.

Electronic component with a semiconductor chip and method for producing the electronic component

An electronic component with at least one semiconductor chip and a wiring layer are described. The wiring layer has elastic contact elements of low mechanical strength in the spatial directions x, y and z, which can be electrically connected to corresponding contact terminal areas of a printed circuit board. The semiconductor chip or the wiring layer additionally has at least two spacers for the mechanical connection to a printed circuit board. A method for producing the electronic component is also described.

Electronic chip and substrate providing insulation protection between conducting nodes

RFID tag and method of manufacturing the same

The present invention provides a radio frequency identification (RFID) tag which exchanges information with an external device in a noncontact manner, in which a paste is used as a material for an antenna, and which is designed to prevent sinking of bumps. A stopper for limiting sinking of bumps of a circuit chip caused by a pressing force when the circuit chip is connected to an antenna is provided on the circuit chip or a base at a position adjacent to the bumps.

Package structure and method of optical display

Semiconductor device

Ramp-stack chip package with static bends

描述了一种斜坡堆栈芯片封装。此芯片封装包括在水平方向彼此偏移的半导体管芯或芯片的垂直堆栈，从而定义具有暴露的焊盘的阶地。大致平行于阶地放置的高带宽斜坡组件电学地并且机械地耦合到暴露的焊盘。例如，可以使用焊料、微弹簧和/或各向异性的导电膜将斜坡组件耦合到半导体管芯。此外，半导体管芯的每一个包括静态弯曲部，以使得半导体管芯的每一个的末端片段平行于所述方向并且机械地耦合到斜坡组件。这些末端片段可以例如经由接近通信来便于芯片和斜坡组件之间的信号的高带宽通信。

Semiconductor integrated circuit having standard and custom circuit regions

A semiconductor device includes a mother chip having a standard integrated circuit and electrodes pads, and an option chip having a custom integrated circuit, the option chip being provided over a part of the mother chip via connectors.

Optical connection through single assembly overhang flip chip optics die with micro structure alignment

시스템은 그것이 접속되는 기판 위로 돌출하는 광자 트랜시버를 갖는 반도체 다이의 플립 칩 접속을 포함하는 광학 트랜시버 어셈블리를 포함한다. 어셈블리는 반도체 다이에서의 마이크로-엔지니어드 구조에서 반도체 다이에 유지되는 정렬 핀을 더 포함한다. 정렬 핀은 하나 이상의 광학 채널들에 대해 광자 트랜시버를 인터페이스하는 광학 렌즈를 이용하여 광자 트랜시버의 수동 정렬을 제공한다. The system includes an optical transceiver assembly including a flip chip connection of a semiconductor die having a photonic transceiver protruding over a substrate to which it is connected. The assembly further includes an alignment pin held in the semiconductor die in a micro-engineered structure in the semiconductor die. The alignment pin provides for manual alignment of the photonic transceiver using an optical lens that interfaces the photonic transceiver to one or more optical channels.

Circuit and process for connecting an integrated circuit to a substrate in chip size and wafer level packages uses a frame and elastic contact between electrical contacts

A process for connecting an integrated circuit (1), especially a chip, wafer or hybrid, with a substrate (30) provides corresponding electrical contacts on the IC (3,4) and substrate (33), at least one of which is elastically elevated and bringing the IC to a frame (22) and joining the electrical contacts together by compressing the elastic elevation. An Independent claim is also included for the device formed as above.

The heap superimposition electronic installation of integrated circuit (IC) chip

本公开涉及集成电路芯片的堆叠和电子装置，该堆叠包括：第一集成电路芯片和第二集成电路芯片，具有彼此相距一定距离分别定位的相对的第一面和第二面；间隔物，介于第二集成电路芯片的第二面的外围区域的至少一部分和第一集成电路芯片的第一面之间；第一粘接剂，将间隔物仅附接至第一面和第二面中的一个面；以及第二粘接剂，介于第二集成电路芯片的第二面的中心区域与第一集成电路芯片的第一面之间，以便将第一集成电路芯片与第二集成电路芯片彼此固定。在本公开的各个实施方式中，芯片经受的机械应力可以非常受限或甚至不存在。

Semiconductor chip and production thereof, and semiconductor device having semiconductor chip bonded to solid device

A semiconductor chip having a functional bump provided on a surface of a semiconductor substrate thereof for electrical connection between an internal circuit thereof and a solid device, and a dummy bump not serving for the electrical connection between the internal circuit and the solid device. The dummy bump may be a stress relieving bump for relieving stresses exerted thereon. The dummy bump may be connected to a low impedance portion. The functional bump and the dummy bump may be provided on a surface protective film. In this case, the dummy bump is provided on a recess formed in the surface protective film.

Integrated mechanical aids for high accuracy alignable-electrical contacts

A method and apparatus for laterally urging two semiconductor chips, dies or wafers into an improved state of registration with each other, the method and apparatus employing microstructures comprising: a first microstructure disposed on a first major surface of a first one of said two semiconductor chips, dies or wafers, wherein the first microstructure includes a sidewall which is tapered thereby disposing it at an acute angle compared to a perpendicular of said first major surface, and a second microstructure disposed on a first surface of a second one of said two semiconductor chips, dies or wafers, wherein the shape of the second microstructure is complementary to, and mates with or contacts, in use, the first microstructure, the second microstructure including a surface which contacts said sidewall when the first and second microstructures are mated or being mated, the sidewall of the first microstructure and the surface of the second microstructure imparting a lateral force for urging the two semiconductor chips, dies or wafers into said improved state of registration.

Module and production method

본 발명은 전기적 배선을 구비한 캐리어 기판(6) 및 플립칩 기술로 캐리어 기판(6)상에 실장된 소자칩을 포함하는 모듈을 제공하고, 소자칩(1)은 캐리어 기판(6)을 향해있는 표면(2) 상에 소자 구조물(3), 지지 프레임(4) 및 지지 요소(5)를 포함하며, 지지 요소(5)는 소자 구조물(3)과 캐리어 기판(6)의 전기적 배선 사이의 전기적 연결을 구현하고, 지지 요소의 높이와 지지 프레임(4)의 높이는 일치한다. 또한 본 발명은 이러한 모듈을 위한 제조 방법을 제공한다.

Chip package, electronic computing device and method for communicating a signal

Semiconductor device and semiconductor fabrication process

本发明涉及一种半导体装置，其包含第一半导体管芯、第二半导体管芯以及多个支撐结构。所述第一半导体管芯包含邻近于其第一主动表面安置的多个第一凸块。所述第二半导体管芯包含邻近于其第二主动表面安置的多个第二凸块。所述第二凸块接合到所述第一凸块。所述支撐结构安置于所述第一半导体管芯的所述第一主动表面与所述第二半导体管芯的所述第二主动表面之间。所述支撐结构为电隔离且邻近于所述第二半导体管芯的所述第二主动表面的外围区安置。

3-D semiconductor die structure with containing feature and method

A die-on-die assembly has a first die ( 10 ) and a second die ( 50 ). The first die ( 10 ) has a first contact extension ( 28,42 ) and a peg ( 32,44,45 ) extending a first height above the first die. The second die ( 50 ) has a second contact extension ( 68 ) connected to the first contact extension and has a containing feature ( 62 ) extending a second height above the second die surrounding the peg. The peg extends past the containing feature. Because the peg extends past the containing feature, lateral movement between the first and second die can cause the peg to come in contact with and be constrained by the containing feature. The peg and containing feature are thus useful in constraining movement between the first and second die.

Technique for controlling positions of stacked dies

An assembly component and a technique for assembling a chip package using the assembly component are described. This chip package includes a set of semiconductor dies that are arranged in a stack in a vertical direction, which are offset from each other in a horizontal direction to define a stepped terrace at one side of the vertical stack. Moreover, the chip package may be assembled using the assembly component. In particular, the assembly component may include a pair of stepped terraces that approximately mirror the stepped terrace of the chip package and which provide vertical position references for an assembly tool that positions the set of semiconductor dies in the vertical stack during assembly of the chip package.

Semiconductor device and method of forming dummy pillars between semiconductor die and substrate for maintaining standoff distance

A semiconductor device has a semiconductor die with an insulation layer formed over an active surface of the semiconductor die. A conductive layer is formed over the first insulating layer electrically connected to the active surface. A plurality of conductive pillars is formed over the conductive layer. A plurality of dummy pillars is formed over the first insulating layer electrically isolated from the conductive layer and conductive pillars. The semiconductor die is mounted to a substrate. A height of the dummy pillars is greater than a height of the conductive pillars to maintain the standoff distance between the semiconductor die and substrate. The dummy pillars can be formed over the substrate. The dummy pillars are disposed at corners of the semiconductor die and a central region of the semiconductor die. A mold underfill material is deposited between the semiconductor die and substrate.

Process for sealing and connecting parts of electromechanical, fluid and optical microsystems and device obtained thereby

A process for connecting two bodies forming parts of an electromechanical, fluid and optical microsystem, wherein a welding region is formed on a first body; an electrically conductive region and a spacing region are formed on a second body; the spacing region extends near the electrically conductive region and has a height smaller than the electrically conductive region. One of the first and second bodies is turned upside down on the other, and the two bodies are welded together by causing the electrically conductive region to melt so that it adheres to the welding region and collapses until its height becomes equal to that of the spacing region. Thereby it is possible to seal active parts or micromechanical structures with respect to the outside world, self-align the two bodies during bonding, obtain an electrical connection between the two bodies, and optically align two optical structures formed on the two bodies.

Electrical component in flip-chip design

Elektrisches Bauelement mit einem Trägersubstrat (1), das einen thermischen Ausdehnungskoeffizient αp aufweist, mit einem Chip (2), der auf dem Trägersubstrat (1) in Flip-Chip-Bauweise mittels Bumps (31 bis 36) befestigt ist, wobei der Chip (2) in einer ersten Vorzugsrichtung x1 einen ersten thermischen Ausdehnungskoeffizient α1 aufweist, wobei Δα1 = |αp – α1| die erste Ausdehnungsdifferenz ist, wobei der Chip (2) in einer zweiten Vorzugsrichtung x2 einen zweiten thermischen Ausdehnungskoeffizient α2 aufweist, wobei Δα2 = |αp – α2| die zweite Ausdehnungsdifferenz ist, wobei das Bauelement in Richtung x1 die größte mögliche Ausdehnungsdifferenz Δα1 und in Richtung x2 die geringste mögliche Ausdehnungsdifferenz Δα2 aufweist, wobei Δx1 ein erster Abstand ist, der einer Normalprojektion der Verbindungslinie (41) zwischen den Mitten (310, 320) der in der ersten Vorzugsrichtung endständigen Bumps (31, 32) auf die parallel zur x1-Richtung verlaufende x1-Achse entspricht, wobei Δx2 ein zweiter Abstand ist, der einer Normalprojektion der Verbindungslinie (42) zwischen den Mitten (320, 340) der in der zweiten Vorzugsrichtung endständigen Bumps (32, 34) auf die parallel zur x2-Richtung verlaufende x2-Achse entspricht, wobei die Bumps so angeordnet sind, dass gilt Δx1 < Δx2, wobei das Material des Trägersubstrats (1) so gewählt ist, dass α1 > αp > α2 gilt, wobei die untere Fläche des Chips (2) in einen Mittelbereich (20) und einen umlaufenden breiten Randbereich (21) aufgeteilt ist, wobei der Chip im Randbereich keine Bumps aufweist, wobei die Breite des Randbereichs (21) in Richtung x1 größer ist als in Richtung x2, wobei auf der unteren Chipfläche fest mit den Bumps (31 bis 36) verbundene Kontaktflächen (91 bis 96) vorgesehen sind, wobei für die endständigen Bumps (31 bis 34) größere Kontaktflächen (91 bis 94) vorgesehen sind als für die übrigen Bumps (35, 36). Electrical component with a carrier substrate (1), which has a thermal expansion coefficient αp, with a ...

Method and structure for interfacing electronic devices

Method and structure for optimizing and controlling diffusional creep at metal contact interfaces are disclosed. Embodiments of the invention accommodate height variations in adjacent contacts, decrease planarization uniformity requirements, and facilitate contact bonding at lower temperatures and pressures by employing shapes and materials that respond predictably to compressive interfacing loads.

Method for producing an electronic component, wherein a semiconductor chip is positioned and placed on a connection carrier, corresponding electronic component, and corresponding semiconductor chip and method for producing a semiconductor chip

Ein Verfahren zur Herstellung eines elektronischen Bauelements (100) umfasst einen Schritt A), in dem ein Halbleiterchip (2) (z.B. ein pixelierter, optoelektronischer Halbleiterchip (2)) mit einer Unterseite (20), mit einer Mehrzahl von Kontaktstiften (21) und mit zumindest einem Justagestift (25) bereitgestellt wird, die von der Unterseite (20) hervorstehen. Die Kontaktstifte (21) sind zur elektrischen Kontaktierung des Halbleiterchips (2) eingerichtet. Der Justagestift (25) verschmälert sich in Richtung weg von der Unterseite (20) und steht weiter von der Unterseite (20) hervor als die Kontaktstifte (21). In einem Schritt B) wird ein Anschlussträger (I) mit einer Oberseite (10), in die mehrere Kontaktvertiefungen (II) und zumindest eine Justagevertiefung (15) eingebracht sind, bereitgestellt. Die Kontaktvertiefungen (11) sind jeweils mit einem Lötmaterial (12) zumindest teilweise gefüllt. In einem Schritt C) wird das Lötmaterial (12) in den Kontaktvertiefungen (11) auf eine Fügetemperatur erhitzt, bei der das Lötmaterial (12) zumindest teilweise schmilzt. In einem Schritt D) wird der Halbleiterchip (2) auf den Anschlussträger (1) aufgesetzt, wobei die Kontaktstifte (21) jeweils in eine Kontaktvertiefung (11) und der Justagestift (25) in die Justagevertiefung (15) eingeführt werden. Die Kontaktstifte (21) werden dabei in das aufgeschmolzene Lötmaterial (12) eingetaucht. D as Lötmaterial (12) und das Material der Kontaktstifte (21) können so gewählt sein, dass im Schritt D) und bei der Fügetemperatur das Lötmaterial (12) und die Kontaktstifte (21) durch isotherme Erstarrung stoffschlüssig miteinander verbunden werden. Ein Verfahren zur Herstellung eines Halbleiterchips (2) umfasst die Schritte: A) Bereitstellen eines Grundkörpers mit einem Halbleiterkörper (26) und einer Unterseite (20), wobei auf dem Halbleiterkörper (26) mehrere Kontaktstifte (21) und zumindest ein Justagestift (25) angeordnet sind, die jeweils von der Unterseite (20) hervorstehen, wobei die ...

Self alignment features for an electronic assembly

Some embodiments of the present invention relate to an electronic assembly that includes a substrate and a die. The electronic assembly further includes an alignment bump on one of the die and the substrate and a group of mating bumps on the other of the die and the substrate. The group of mating bumps is positioned such that if the alignment bump engages each of the mating bumps, the die is appropriately positioned relative to the substrate at that location where the alignment bump engages the group of mating bumps. In some embodiments, the alignment bump extends from the substrate while in other embodiments the alignment bump extends from the die. The alignment bump on the substrate (or die) may be part of a plurality of alignment bumps such that each alignment bump engages a different group of mating bumps on the die (or substrate).

Solder in cavity interconnection technology

一互連技術可使用模製焊料來界定焊球。一遮罩層可被圖案化以形成腔穴及積設於該等腔穴中的焊料糊料。加熱時焊球即可形成。腔穴由間隔壁來界定以阻止焊球在一結合過程中發生橋接。在某些實施例中，連接至該等焊球的焊球凸塊可能具有比焊球之接觸面更大的接觸面。

A structure of a flip-chip package and a process thereof