Metal Bump Joint Structure and Methods of Forming

A structure comprises a first semiconductor chip with a first metal bump and a second semiconductor chip with a second metal bump. The structure further comprises a solder joint structure electrically connecting the first semiconductor chip and the second semiconductor chip, wherein the solder joint structure comprises an intermetallic compound region between the first metal bump and the second metal bump, wherein the intermetallic compound region is with a first height dimension and a surrounding portion formed along exterior walls of the first metal bump and the second metal bump, wherein the surrounding portion is with a second height dimension, and wherein the second height dimension is greater than the first height dimension.

METAL BUMP JOINT STRUCTURE

Semiconductor package, interposer and semiconductor process for manufacturing the same

A semiconductor package includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes a first main body, at least one first columnar portion and at least one first conductive layer. The first columnar portion protrudes from a bottom surface of the first main body. The first conductive layer is disposed on a side surface of the first columnar portion. The second semiconductor device includes a second main body, at least one second columnar portion and at least one second conductive layer. The second columnar portion protrudes from a top surface of the second main body. The second conductive layer is disposed on a side surface of the second columnar portion. The first conductive layer is electrically coupled to the second conductive layer.

전자 디바이스

... 플립칩 실장된 복수의 전자부품을 포함하고, 표면의 평탄성이 뛰어난 CSP형 전자 디바이스를 제공한다. 전자 디바이스(1)는, 실장 기판(10)과, 실장 기판(10)의 표면에, 범프(21 및 22)를 통해 플립칩 실장되어 있는 전자부품(11 및 12)과, 전자부품(11 및 12)을 실장 기판(10) 상에 봉지하기 위한 봉지 부재(13)를 포함하고, 전자부품(11)의 두께(tx1)는, 전자부품(12)의 두께(tx2)보다도 두꺼우면서, 전자부품(11)에 접합된 범프(21)의 높이(ty1)는, 전자부품(12)에 접합된 범프(22)의 높이(ty2)보다도 낮다.

Metal Bump Joint Structure and Methods of Forming

A structure comprises a first semiconductor chip with a first metal bump and a second semiconductor chip with a second metal bump. The structure further comprises a solder joint structure electrically connecting the first semiconductor chip and the second semiconductor chip, wherein the solder joint structure comprises an intermetallic compound region between the first metal bump and the second metal bump, wherein the intermetallic compound region is with a first height dimension and a surrounding portion formed along exterior walls of the first metal bump and the second metal bump, wherein the surrounding portion is with a second height dimension, and wherein the second height dimension is greater than the first height dimension.

Electronic device

An electronic device includes a mount board, first and second electronic components flip-chip mounted on a surface of the mount board with bumps interposed therebetween, and a sealing member that seals the first and second electronic components on the mount board. A thickness of the first electronic component is larger than a thickness of the second electronic component, and a height of the bump bonded to the first electronic component is smaller than a height of the bump bonded to the second electronic component.

Semiconductor package structure and method of manufacturing the same

A semiconductor package structure includes a semiconductor die having an active surface, a conductive bump electrically coupled to the active surface, and a dielectric layer surrounding the conductive bump. The conductive bump and the dielectric layer form a planar surface at a distal end of the conductive bump with respect to the active surface. The distal end of the conductive bump is wider than a proximal end of the conductive bump with respect to the active surface.

SEMICONDUCTOR PACKAGES

Semiconductor packages include a first substrate including a central portion and a peripheral portion, at least one first central connection member attached to the central portion of the first substrate, and at least one first peripheral connection member attached to the peripheral portion of the first substrate. The first central connection member includes a first supporter and a first fusion conductive layer surrounding the first supporter.

SEMICONDUCTOR PACKAGE

A stacked semiconductor package in an embodiment includes a first semiconductor package including a first circuit board and a first semiconductor element mounted on the first circuit board; and a second semiconductor package including a second circuit board and a second semiconductor element mounted on the second circuit board, the second semiconductor package being stacked on the first semiconductor package. The first semiconductor package further includes a sealing resin sealing the first semiconductor element; a conductive layer located in contact with the sealing resin; and a thermal via connected to the conductive layer and located on the first circuit board.

Metal bump joint structure

A structure comprises a first semiconductor chip with a first metal bump and a second semiconductor chip with a second metal bump. The structure further comprises a solder joint structure electrically connecting the first semiconductor chip and the second semiconductor chip, wherein the solder joint structure comprises an intermetallic compound region between the first metal bump and the second metal bump, wherein the intermetallic compound region is with a first height dimension and a surrounding portion formed along exterior walls of the first metal bump and the second metal bump, wherein the surrounding portion is with a second height dimension, and wherein the second height dimension is greater than the first height dimension.

ELECTRONIC DEVICE

An electronic device includes a mount board, first and second electronic components flip-chip mounted on a surface of the mount board with bumps interposed therebetween, and a sealing member that seals the first and second electronic components on the mount board. A thickness of the first electronic component is larger than a thickness of the second electronic component, and a height of the bump bonded to the first electronic component is smaller than a height of the bump bonded to the second electronic component. 1. An electronic device comprising:a mount board;a first electronic component and a second electronic component flip-chip mounted on a surface of the mount board with bumps interposed therebetween; anda sealing member that seals the first electronic component and the second electronic component on the mount board; whereina thickness of the first electronic component is larger than a thickness of the second electronic component; anda height of the bump bonded to the first electronic component is smaller than a height of the bump bonded to the second electronic component.2. The electronic device according to claim 1 , wherein in plan view of the mount board claim 1 , an area of one electronic component of the first electronic component and the second electronic component with a large height from the surface of the mount board is larger than an area of the other electronic component with a small height from the surface of the mount board.3. The electronic device according to claim 1 , wherein claim 1 , a length claim 1 , in an arrangement direction in which the first electronic component and the second electronic component are arranged claim 1 , of one electronic component of the first electronic component and the second electronic component with a small height from the surface of the mount board is larger than a length in the arrangement direction of the other electronic component with a large height from the surface of the mount board.4. The electronic ...

전도성 언더필 물질을 포함하는 반도체 장치들과 패키지들, 및 관련 방법들

... 반도체 장치들 및 장치 패키지들은 복수의 전도성 구조물을 통해 기판에 전기적으로 연결된 적어도 하나의 반도체 다이를 포함한다. 적어도 하나의 반도체 다이는 복수의 메모리 다이일 수 있고, 기판은 논리 다이일 수 있다. 적어도 하나의 반도체 다이와 기판 사이에 배치된 언더필 물질은 열 전도성 물질을 포함할 수 있다. 복수의 전도성 구조물과 언더필 물질 사이에 전기 절연 물질이 배치될 수 있다. 반도체 장치 패키지들을 형성하기 위한 방법과 같은, 반도체 다이를 기판에 부착하는 방법들은, 전도성 구조물들의 적어도 외측 표면을 피복 또는 코팅하는 단계, 전기 절연 물질로 반도체 다이를 기판에 전기적으로 연결하는 단계, 및 반도체 다이와 기판 사이에 열 전도성 물질을 배치하는 단계를 포함한다.

Stretchable and self-healing solders for dies and components in manufacturing environments

A mechanism is described for facilitating stretchable and self-healing solders in microelectronics manufacturing environments. An apparatus of embodiments, as described herein, includes one or more solders associated with a microelectronics component, where the one or more solders contain a liquid metal and are wrapped in an encapsulation material. The apparatus further includes a substrate coupled to the one or more solders.

Metal bump joint structure

A structure comprises a first semiconductor chip with a first metal bump and a second semiconductor chip with a second metal bump. The structure further comprises a solder joint structure electrically connecting the first semiconductor chip and the second semiconductor chip, wherein the solder joint structure comprises an intermetallic compound region between the first metal bump and the second metal bump, wherein the intermetallic compound region is with a first height dimension and a surrounding portion formed along exterior walls of the first metal bump and the second metal bump, wherein the surrounding portion is with a second height dimension, and wherein the second height dimension is greater than the first height dimension.

Metal bump joint structure

A structure comprises a first semiconductor chip with a first metal bump and a second semiconductor chip with a second metal bump. The structure further comprises a solder joint structure electrically connecting the first semiconductor chip and the second semiconductor chip, wherein the solder joint structure comprises an intermetallic compound region between the first metal bump and the second metal bump, wherein the intermetallic compound region is with a first height dimension and a surrounding portion formed along exterior walls of the first metal bump and the second metal bump, wherein the surrounding portion is with a second height dimension, and wherein the second height dimension is greater than the first height dimension. The invention provides the metal bump joint structure.

반도체 패키지

... 본 발명은 반도체 패키지를 제공한다. 이 반도체 패키지는, 중심부와 주변부를 포함하는 제 1 기판; 상기 제 1 기판의 중심부에 부착되는 적어도 하나의 제 1 중심 연결부재; 및 상기 제 1 기판의 주변부에 부착되는 적어도 하나의 제 1 주변 연결부재를 포함하되, 상기 제 1 중심 연결부재는 제 1 지지체와 상기 제 1 지지체를 둘러싸는 제 1 융합도전층을 포함한다. 반도체 패키지에서는 고온 실장시 기판의 휨(warpage)을 방지하여, 이웃간의 솔더볼들이 서로 부착되는 불량을 방지할 수 있다. 이로써 반도체 패키지 불량률을 줄일 수 있어 생산 수율을 증대시킬 수 있다.

Bonding Through Multi-Shot Laser Reflow

A method includes performing a first laser shot on a first portion of a top surface of a first package component. The first package component is over a second package component, and a first solder region between the first package component and the second package component is reflowed by the first laser shot. After the first laser shot, a second laser shot is performed on a second portion of the top surface of the first package component. A second solder region between the first package component and the second package component is reflowed by the second laser shot. 1. A package comprising:a first package component comprising a first metallic feature and a second metallic feature at a surface of the first package component;a second package component comprising a third metallic feature and a fourth metallic feature at a surface of the second package component;a first solder region joining the first metallic feature to the third metallic feature;a first Inter-Metallic Compound (IMC) between and adjoining the first metallic feature and the first solder region, wherein the first IMC has a first thickness;a second solder region joining the second metallic feature to the fourth metallic feature; anda second IMC between and adjoining the second metallic feature and the second solder region, wherein the second IMC has a second thickness greater than the first thickness.2. The package of claim 1 , wherein a ratio of the second thickness to the first thickness is greater than about 1.2.3. The package of claim 2 , wherein the ratio is in a range between about 1.2 and about 2.4. The package of claim 1 , wherein the first thickness is in a first range between about 4 μm and about 6 μm claim 1 , and the second thickness is in a second range between about 7.2 μm and about 8 μm.5. The package of further comprising:a first column of metallic features comprised in the first package component, with the first metallic feature being in the first column of metallic features;a first column ...

CHIP ASSEMBLIES EMPLOYING SOLDER BONDS TO BACK-SIDE LANDS INCLUDING AN ELECTROLYTIC NICKEL LAYER

A stacked-chip assembly including a plurality of IC chips or die that are stacked, and electrically coupled by solder bonds. In accordance with some embodiments described further below, the solder bonds are to contact a back-side land that includes a diffusion barrier to reduce intermetallic formation and/or other solder-induced reliability issues. The back-side land may include an electrolytic nickel (Ni) barrier layer separating solder from a back-side redistribution layer trace. This electrolytic Ni may be of high purity, which at least in part, may enable the backside metallization stack to be of minimal thickness while still functioning as a diffusion barrier. In some embodiments, the back-side land composition and architecture is distinct from a front-side land composition and/or architecture.

Metal Bump Joint Structure

A structure comprises a first semiconductor chip with a first metal bump and a second semiconductor chip with a second metal bump. The structure further comprises a solder joint structure electrically connecting the first semiconductor chip and the second semiconductor chip, wherein the solder joint structure comprises an intermetallic compound region between the first metal bump and the second metal bump, wherein the intermetallic compound region is with a first height dimension and a surrounding portion formed along exterior walls of the first metal bump and the second metal bump, wherein the surrounding portion is with a second height dimension, and wherein the second height dimension is greater than the first height dimension.

METAL BUMP JOINT STRUCTURE

전도성 언더필 물질을 포함하는 반도체 장치들과 패키지들, 및 관련 방법들

... 반도체 장치들 및 장치 패키지들은 복수의 전도성 구조물을 통해 기판에 전기적으로 연결된 적어도 하나의 반도체 다이를 포함한다. 적어도 하나의 반도체 다이는 복수의 메모리 다이일 수 있고, 기판은 논리 다이일 수 있다. 적어도 하나의 반도체 다이와 기판 사이에 배치된 언더필 물질은 열 전도성 물질을 포함할 수 있다. 복수의 전도성 구조물과 언더필 물질 사이에 전기 절연 물질이 배치될 수 있다. 반도체 장치 패키지들을 형성하기 위한 방법과 같은, 반도체 다이를 기판에 부착하는 방법들은, 전도성 구조물들의 적어도 외측 표면을 피복 또는 코팅하는 단계, 전기 절연 물질로 반도체 다이를 기판에 전기적으로 연결하는 단계, 및 반도체 다이와 기판 사이에 열 전도성 물질을 배치하는 단계를 포함한다.

Semiconductor package and method of forming the same

Semiconductor devices and packages including conductive underfill material and related methods

Semiconductor devices and device packages include at least one semiconductor die electrically coupled to a substrate through a plurality of conductive structures. The at least one semiconductor die may be a plurality of memory dice, and the substrate may be a logic die. An underfill material disposed between the at least one semiconductor die and the substrate may include a thermally conductive material. An electrically insulating material is disposed between the plurality of conductive structures and the underfill material. Methods of attaching a semiconductor die to a substrate, such as for forming semiconductor device packages, include covering or coating at least an outer side surface of conductive structures, electrically coupling the semiconductor die to the substrate with an electrically insulating material, and disposing a thermally conductive material between the semiconductor die and the substrate.

SEMICONDUCTOR PACKAGE HAVING MAGNETIC INTERCONNECTS AND RELATED METHODS

Implementations of semiconductor packages may include a first die including a plurality of contact pads, a second die including a plurality of contact pads, a plurality of solder interconnects bonding the plurality of contact pads of the first die to the plurality of contact pads of the second die, and a plurality of magnetic particles each coated in an oxide included in each of the plurality of solder interconnects. 1. A semiconductor package comprising:a first die comprising a plurality of contact pads;a second die comprising a plurality of contact pads;a plurality of solder interconnects bonding the plurality of contact pads of the first die to the plurality of contact pads of the second die; anda plurality of magnetic particles each coated in an oxide comprised in each of the plurality of solder interconnects.2. The package of claim 1 , wherein the plurality of magnetic particles comprise Ni claim 1 , Co claim 1 , Fe claim 1 , FeO claim 1 , or any combination thereof.3. The package of claim 1 , wherein a pitch of the plurality of solder interconnects is less than 100 micrometers.4. The package of claim 1 , wherein the plurality of contact pads of the first die are bonded to the plurality of contact pads of the second die through an application of a magnetic field to the plurality of solder interconnects.5. The package of claim 1 , wherein the plurality of magnetic particles is more heavily concentrated near the second die than the first die.6. The package of claim 1 , wherein the oxide comprises silicon dioxide.7. A method of forming a semiconductor package comprising:forming a plurality of solder interconnects on a first die, wherein the plurality of solder interconnects comprise magnetic particles coated in an oxide;coupling a second die over the first die;reflowing the plurality of solder interconnects; andapplying a magnetic field to the plurality of solder interconnects to join the first die to the second die.8. The method of claim 7 , wherein the magnetic ...

Electronic device

STRETCHABLE AND SELF-HEALING SOLDERS FOR DIES AND COMPONENTS IN MANUFACTURING ENVIRONMENTS

A mechanism is described for facilitating stretchable and self-healing solders in microelectronics manufacturing environments. An apparatus of embodiments, as described herein, includes one or more solders associated with a microelectronics component, where the one or more solders contain a liquid metal and are wrapped in an encapsulation material. The apparatus further includes a substrate coupled to the one or more solders. 1. A microelectronics manufacturing apparatus comprising:one or more solders associated with a microelectronics component, wherein the one or more solders contain a liquid metal and are wrapped in an encapsulation material; anda substrate coupled to the one or more solders.2. The apparatus of claim 1 , wherein the one or more solders are stretchable and self-healing such that the liquid material offers stretchability and self-healing to the one or more solders.3. The apparatus of claim 1 , wherein the encapsulation material provides protection against potential leaks or overflows of the liquid material from the one or more solders.4. The apparatus of claim 3 , wherein the liquid material comprises one or more of Gallium claim 3 , Cesium claim 3 , Rubidium claim 3 , and Francium claim 3 , wherein the one or more solders further include a solder material combined with the liquid material claim 3 , wherein the solder material includes one or more of Indium claim 3 , Tin claim 3 , Bismuth claim 3 , Zinc claim 3 , Rhodium claim 3 , and Silver claim 3 , and wherein the encapsulation material refers to encapsulation epoxy.5. The apparatus of claim 1 , wherein the substrate comprises an FR4 based printed circuit board (PCB) substrate claim 1 , wherein the substrate to have metallization to engage with the one or solders wrapped in the encapsulated material claim 1 , wherein the metallization is based on Copper.6. The apparatus of claim 1 , wherein the microelectronics component comprises a semiconductor chip including an integrated circuit representing ...

The metal lug joining structure

Joint structure of semiconductor device and method of forming semiconductor device

A structure includes a first semiconductor chip with a first metal bump and a second semiconductor chip with a second metal bump. The structure further comprises a solder joint structure electrically connecting the first semiconductor chip and the second semiconductor chip, wherein the solder joint structure includes an intermetallic compound region between the first metal bump and the second metal bump, wherein the intermetallic compound region is with a first height dimension and a surrounding portion formed along exterior walls of the first metal bump and the second metal bump, wherein the surrounding portion is with a second height dimension, and wherein the second height dimension is greater than the first height dimension.

Bonding Through Multi-Shot Laser Reflow

A method includes performing a first laser shot on a first portion of a top surface of a first package component. The first package component is over a second package component, and a first solder region between the first package component and the second package component is reflowed by the first laser shot. After the first laser shot, a second laser shot is performed on a second portion of the top surface of the first package component. A second solder region between the first package component and the second package component is reflowed by the second laser shot.

Semiconductor device and package including conductive underfill material and related methods

Semiconductor package having magnetic interconnects and related methods

Implementations of semiconductor packages may include a first die including a plurality of contact pads, a second die including a plurality of contact pads, a plurality of solder interconnects bonding the plurality of contact pads of the first die to the plurality of contact pads of the second die, and a plurality of magnetic particles each coated in an oxide included in each of the plurality of solder interconnects.

REMOVABLE SACRIFICIAL CONNECTIONS FOR SEMICONDUCTOR DEVICES

Methods of fabricating semiconductor devices and Radio Frequency (RF) components are provided. The method includes providing a circuit layout on a semiconductor layer and providing one or more sacrificial connections to connect bump pads in the circuit layout. The method also includes testing the circuit layout using the one or more sacrificial connections and removing at least a portion of the one or more sacrificial connections. In this way, the performance of the semiconductor device is improved by reducing or avoiding capacitive or inductive leakage paths that can be caused by leftover materials.

Package on package configuration

A first integrated circuit (IC) package has a package substrate on bottom. The package substrate comprises a bottom redistribution circuitry configured according to printed circuit board (PCB) design rule and a top redistribution circuitry configured according to integrated circuit (IC) design rule. The first IC package has a plurality of top metal pads and a plurality of copper pillars configured on a top side according to IC design rule. A second IC package has a plurality of bottom metal pads configured according to IC design rule configured on a top side of the first IC package. The first IC package electrically couples to the second IC package through the plurality of copper pillars.

NO-REMELT SOLDER ENFORCEMENT JOINT

No-remelt solder joints can eliminate die or substrate movement in downstream reflow processes. In one example, one or more solder joints between two substrates can be formed as full IMC (intermetallic compound) solder joints. In one example, a full IMC solder joint includes a continuous layer (e.g., from the top pad to bottom pad) of intermetallic compounds. In one example, a full IMC joint can be formed by dispensing a no-remelt solder paste on some of the pads of one or both substrates to be bonded together.

Quilt packaging system with interdigitated interconnecting nodules for inter-chip alignment

First and second integrated devices each have an optical component and a plurality of interconnect structures disposed one edge thereon. The first edge surface of the second integrated device is positioned contiguous to the first edge surface of the first integrated device. The interconnect structures disposed on the first integrated device are in physical contact with the interconnect structures disposed on the edge surface of the second integrated device so as to provide alignment for conveying at least one signal between the optical components on the first and second integrated devices.

SEMICONDUCTOR DEVICES AND PACKAGES INCLUDING CONDUCTIVE UNDERFILL MATERIAL AND RELATED METHODS

Semiconductor devices and device packages include at least one semiconductor die electrically coupled to a substrate through a plurality of conductive structures. The at least one semiconductor die may be a plurality of memory dice, and the substrate may be a logic die. An underfill material disposed between the at least one semiconductor die and the substrate may include a thermally conductive material. An electrically insulating material is disposed between the plurality of conductive structures and the underfill material. Methods of attaching a semiconductor die to a substrate, such as for forming semiconductor device packages, include covering or coating at least an outer side surface of conductive structures, electrically coupling the semiconductor die to the substrate with an electrically insulating material, and disposing a thermally conductive material between the semiconductor die and the substrate.

Removable sacrificial connections for semiconductor devices

Methods of fabricating semiconductor devices and Radio Frequency (RF) components are provided. The method includes providing a circuit layout on a semiconductor layer and providing one or more sacrificial connections to connect bump pads in the circuit layout. The method also includes testing the circuit layout using the one or more sacrificial connections and removing at least a portion of the one or more sacrificial connections. In this way, the performance of the semiconductor device is improved by reducing or avoiding capacitive or inductive leakage paths that can be caused by leftover materials.

Stacked package and method of manufacturing the same

A stacked package includes a substrate, and a first structure bonded to the substrate. The first structure has a plurality of bumps, and a first hydrophilic coating is on sidewalls of the first structure. The stacked package further includes a second structure bonded to the plurality of bumps. The first hydrophilic coating is on sidewalls of the second structure. The first structure is between the second structure and the substrate. The stacked package further includes a housing, wherein the housing defines a volume enclosing the first structure and the second structure. A second hydrophilic coating is on sidewalls of an inner surface of the housing. The stacked package further includes a cooling fluid within the volume enclosing the first structure and the second structure. A top surface of the cooling fluid is above a top surface of the second structure.

MULTIPLE UNDERFILLS FOR FLIP CHIP PACKAGES

A method of assembling a flip chip IC package includes applying core underfill material to a surface of a package substrate in a pattern including an area corresponding to a core region of an IC die thereon that is to be attached, that excludes of an area corresponding to corners of the IC die. The IC die is bonded to the package substrate by pushing the IC die with a sufficient force for the core underfill material is displaced laterally by the bumps so that the bumps contact the land pads. After the pushing the corners of the IC die are not on the core underfill. Edge underfilling includes dispensing a second underfill material that is curable liquid to fill an area under the corners of the IC die. The second underfill material is cured resulting in it having a higher fracture strength as compared to the core underfill.

SEMICONDUCTOR DEVICES AND PACKAGES INCLUDING CONDUCTIVE UNDERFILL MATERIAL AND RELATED METHODS

Semiconductor devices and device packages include at least one semiconductor die electrically coupled to a substrate through a plurality of conductive structures. The at least one semiconductor die may be a plurality of memory dice, and the substrate may be a logic die. An underfill material disposed between the at least one semiconductor die and the substrate may include a thermally conductive material. An electrically insulating material is disposed between the plurality of conductive structures and the underfill material. Methods of attaching a semiconductor die to a substrate, such as for forming semiconductor device packages, include covering or coating at least an outer side surface of conductive structures, electrically coupling the semiconductor die to the substrate with an electrically insulating material, and disposing a thermally conductive material between the semiconductor die and the substrate.

SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF

A semiconductor device and a fabrication method thereof are disclosed, the semiconductor device including: a substrate having a substrate body and a plurality of conductive pads formed on the substrate body, wherein each of the conductive pads has at least an opening formed in a first surface thereof; a semiconductor component having a plurality of bonding pads; a plurality of conductive elements formed between the bonding pads and the conductive pads and in the openings of the conductive pads; and an encapsulant formed between the substrate and the semiconductor component for encapsulating the conductive elements, thereby strengthening the bonding between the conductive elements and the conductive pads and consequently increasing the product yield.

Quilt packaging system with mated metal interconnect nodules and voids

First and second integrated devices each have an optical component and a plurality of interconnect structures disposed one edge thereon. The first edge surface of the second integrated device is positioned contiguous to the first edge surface of the first integrated device. The interconnect structures disposed on the first integrated device are in physical contact with the interconnect structures disposed on the edge surface of the second integrated device so as to provide alignment for conveying at least one signal between the optical components on the first and second integrated devices.

Package and method of forming the same

A method includes performing a first laser shot on a first portion of a top surface of a first package component. The first package component is over a second package component, and a first solder region between the first package component and the second package component is reflowed by the first laser shot. After the first laser shot, a second laser shot is performed on a second portion of the top surface of the first package component. A second solder region between the first package component and the second package component is reflowed by the second laser shot.

Package and its forming method

REMOVABLE SACRIFICIAL CONNECTIONS FOR SEMICONDUCTOR DEVICES

Methods of fabricating semiconductor devices and Radio Frequency (RF) components are provided. The method includes providing a circuit layout on a semiconductor layer and providing one or more sacrificial connections to connect bump pads in the circuit layout. The method also includes testing the circuit layout using the one or more sacrificial connections and removing at least a portion of the one or more sacrificial connections. In this way, the performance of the semiconductor device is improved by reducing or avoiding capacitive or inductive leakage paths that can be caused by leftover materials.

Removable sacrificial connections for semiconductor devices

Methods of fabricating semiconductor devices and Radio Frequency (RF) components are provided. The method includes providing a circuit layout on a semiconductor layer and providing one or more sacrificial connections to connect bump pads in the circuit layout. The method also includes testing the circuit layout using the one or more sacrificial connections and removing at least a portion of the one or more sacrificial connections. In this way, the performance of the semiconductor device is improved by reducing or avoiding capacitive or inductive leakage paths that can be caused by leftover materials.

Bonding through multi-shot laser reflow

A method includes performing a first laser shot on a first portion of a top surface of a first package component. The first package component is over a second package component, and a first solder region between the first package component and the second package component is reflowed by the first laser shot. After the first laser shot, a second laser shot is performed on a second portion of the top surface of the first package component. A second solder region between the first package component and the second package component is reflowed by the second laser shot.

Joint structure of semiconductor device and method of forming semiconductor device

PACKAGE ON PACKAGE CONFIGURATION

A first integrated circuit (IC) package has a package substrate on bottom. The package substrate comprises a bottom redistribution circuitry configured according to printed circuit board (PCB) design rule and a top redistribution circuitry configured according to integrated circuit (IC) design rule. The first IC package has a plurality of top metal pads and a plurality of copper pillars configured on a top side according to IC design rule. A second IC package has a plurality of bottom metal pads configured according to IC design rule configured on a top side of the first IC package. The first IC package electrically couples to the second IC package through the plurality of copper pillars.

STACKED PACKAGE AND METHOD OF MANUFACTURING THE SAME

A stacked package includes a substrate, and a first structure bonded to the substrate. The first structure has a plurality of bumps, and a first hydrophilic coating is on sidewalls of the first structure. The stacked package further includes a second structure bonded to the plurality of bumps. The first hydrophilic coating is on sidewalls of the second structure. The first structure is between the second structure and the substrate. The stacked package further includes a housing, wherein the housing defines a volume enclosing the first structure and the second structure. A second hydrophilic coating is on sidewalls of an inner surface of the housing. The stacked package further includes a cooling fluid within the volume enclosing the first structure and the second structure. A top surface of the cooling fluid is above a top surface of the second structure.

Semiconductor package having a solder-on-pad structure

A semiconductor package and methods for producing the same are described. One example of the semiconductor package is described to include a substrate having a first face and an opposing second face. The package is further described to include a plurality of pads disposed on the first face of the substrate, each of the plurality of pads including a first face and an opposing second face that is in contact with the first face of the substrate. The semiconductor package is further described to include a plurality of solder-on-pad structures provided on a first of the plurality of pads.

Semiconductor devices and packages including conductive underfill material and related methods

Metal bump joint structure and methods of forming

A structure comprises a first semiconductor chip with a first metal bump and a second semiconductor chip with a second metal bump. The structure further comprises a solder joint structure electrically connecting the first semiconductor chip and the second semiconductor chip, wherein the solder joint structure comprises an intermetallic compound region between the first metal bump and the second metal bump, wherein the intermetallic compound region is with a first height dimension and a surrounding portion formed along exterior walls of the first metal bump and the second metal bump, wherein the surrounding portion is with a second height dimension, and wherein the second height dimension is greater than the first height dimension.

SEMICONDUCTOR PACKAGES

Semiconductor packages include a first substrate including a central portion and a peripheral portion, at least one first central connection member attached to the central portion of the first substrate, and at least one first peripheral connection member attached to the peripheral portion of the first substrate. The first central connection member includes a first supporter and a first fusion conductive layer surrounding the first supporter.

SEMICONDUCTOR PACKAGE HAVING A SOLDER-ON-PAD STRUCTURE

A semiconductor package and methods for producing the same are described. One example of the semiconductor package is described to include a substrate having a first face and an opposing second face. The package is further described to include a plurality of pads disposed on the first face of the substrate, each of the plurality of pads including a first face and an opposing second face that is in contact with the first face of the substrate. The semiconductor package is further described to include a plurality of solder-on-pad structures provided on a first of the plurality of pads. 1. A semiconductor device , comprising:a substrate comprising a first face and an opposing second face;a plurality of pads disposed on the first face of the substrate, each of the plurality of pads comprising a first face and an opposing second face that is in contact with the first face of the substrate; anda plurality of solder-on-pad structures provided on a first pad in the plurality of pads.2. The semiconductor device of claim 1 , further comprising:a circuit element mounted on the first pad via the plurality of solder-on-pad structures.3. The semiconductor device of claim 2 , wherein an edge of the circuit element is substantially aligned with an edge of the first pad.4. The semiconductor device of claim 3 , further comprising:a second circuit element mounted on a second pad in the plurality of pads.5. The semiconductor device of claim 4 , wherein a lateral distance between the circuit element and the second circuit element is substantially equal to a lateral distance between the first pad and the second pad.6. The semiconductor device of claim 5 , wherein an edge of the second circuit element is substantially aligned with an edge of the second pad.7. The semiconductor device of claim 1 , where the first face of the first pad is only partially covered by the plurality of solder-on-pad structures.8. A semiconductor package claim 1 , comprising:a substrate comprising a first face ...

SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME

A semiconductor package structure includes a semiconductor die having an active surface, a conductive bump electrically coupled to the active surface, and a dielectric layer surrounding the conductive bump. The conductive bump and the dielectric layer form a planar surface at a distal end of the conductive bump with respect to the active surface. The distal end of the conductive bump is wider than a proximal end of the conductive bump with respect to the active surface.

Inter-Chip Alignment

First and second integrated devices each have an optical component and a plurality of interconnect structures disposed one edge thereon. The first edge surface of the second integrated device is positioned contiguous to the first edge surface of the first integrated device. The interconnect structures disposed on the first integrated device are in physical contact with the interconnect structures disposed on the edge surface of the second integrated device so as to provide alignment for conveying at least one signal between the optical components on the first and second integrated devices.

Metal bump joint structure

A structure comprises a first semiconductor chip with a first metal bump and a second semiconductor chip with a second metal bump. The structure further comprises a solder joint structure electrically connecting the first semiconductor chip and the second semiconductor chip, wherein the solder joint structure comprises an intermetallic compound region between the first metal bump and the second metal bump, wherein the intermetallic compound region is with a first height dimension and a surrounding portion formed along exterior walls of the first metal bump and the second metal bump, wherein the surrounding portion is with a second height dimension, and wherein the second height dimension is greater than the first height dimension.

Bonding through multi-shot laser reflow

A method includes performing a first laser shot on a first portion of a top surface of a first package component. The first package component is over a second package component, and a first solder region between the first package component and the second package component is reflowed by the first laser shot. After the first laser shot, a second laser shot is performed on a second portion of the top surface of the first package component. A second solder region between the first package component and the second package component is reflowed by the second laser shot.

Bonding Through Multi-Shot Laser Reflow

A method includes performing a first laser shot on a first portion of a top surface of a first package component. The first package component is over a second package component, and a first solder region between the first package component and the second package component is reflowed by the first laser shot. After the first laser shot, a second laser shot is performed on a second portion of the top surface of the first package component. A second solder region between the first package component and the second package component is reflowed by the second laser shot.

Semiconductor devices and packages including conductive underfill material and related methods

Semiconductor packages

Semiconductor packages include a first substrate including a central portion and a peripheral portion, at least one first central connection member attached to the central portion of the first substrate, and at least one first peripheral connection member attached to the peripheral portion of the first substrate. The first central connection member includes a first supporter and a first fusion conductive layer surrounding the first supporter.

SEMICONDUCTOR PACKAGE, INTERPOSER AND SEMICONDUCTOR PROCESS FOR MANUFACTURING THE SAME

A semiconductor package includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes a first main body, at least one first columnar portion and at least one first conductive layer. The first columnar portion protrudes from a bottom surface of the first main body. The first conductive layer is disposed on a side surface of the first columnar portion. The second semiconductor device includes a second main body, at least one second columnar portion and at least one second conductive layer. The second columnar portion protrudes from a top surface of the second main body. The second conductive layer is disposed on a side surface of the second columnar portion. The first conductive layer is electrically coupled to the second conductive layer. 1. A semiconductor package , comprising: a first main body having a bottom surface;', 'at least one first columnar portion protruding from the bottom surface of the first main body; and', 'at least two first conductive layers disposed on side surfaces of the first columnar portion, wherein the first conductive layers do not physically contact each other; and, 'a first semiconductor device, comprising a second main body having a top surface facing the bottom surface of the first main body;', 'at least one second columnar portion protruding from the top surface of the second main body; and', 'at least two second conductive layers disposed on side surfaces of the second columnar portion, wherein the second conductive layers do not physically contact each other;, 'a second semiconductor device, comprisingwherein the first conductive layers are electrically coupled to the second conductive layers.2. The semiconductor package of claim 1 , wherein the first columnar portion has a first height claim 1 , the second columnar portion has a second height claim 1 , and a sum of the first height and the second height is greater than a distance between the bottom surface of the first main body and ...

Microelectronic packages with dual or multiple-etched flip-chip connectors

A packaged microelectronic element includes a microelectronic element having a front surface and a plurality of first solid metal posts extending away from the front surface. A substrate has a major surface and a plurality of conductive elements exposed at the major surface and joined to the first solid metal posts. In particular examples, the conductive elements can be bond pads or can be second posts having top surfaces and edge surfaces extending at substantial angles away therefrom. Each first solid metal post includes a base region adjacent the microelectronic element and a tip region remote from the microelectronic element, the base region and tip region having respective concave circumferential surfaces. Each first solid metal post has a horizontal dimension which is a first function of vertical location in the base region and which is a second function of vertical location in the tip region.

Semiconductor assembly and semiconductor package including a solder channel

Semiconductor packages connecting a semiconductor chip to an external device by bumps are provided. The semiconductor packages may include a connection pad on a semiconductor chip, a connecting bump on and configured to be electrically connected to the connection pad and a supporting bump on the semiconductor chip and configured to be electrically isolated from the connection pad. The connection bump may include a first pillar and a first solder ball and the supporting bump may include a second pillar and a second solder ball. The semiconductor packages may further include a solder channel in the second pillar configured to allow a portion of the second solder ball to extend into the solder channel along a predetermined direction.

Electronic element unit and reinforcing adhesive agent

It is an object of the present invention to provide an electronic element unit and a reinforcing adhesive agent in which a bonding strength can be improved between an electronic element and a circuit board and a repairing work can be carried out without giving a thermal damage to the electronic element or the circuit board. In an electronic element unit ( 1 ) including an electronic element ( 2 ) having a plurality of connecting terminals ( 12 ) on a lower surface thereof, a circuit board ( 3 ) having a plurality of electrodes ( 22 ) corresponding to the connecting terminals ( 12 ) on an upper surface thereof. The connecting terminals ( 12 ) and the electrodes ( 22 ) are connected by solder bumps ( 23 ), and the electronic element ( 2 ) and the circuit board ( 3 ) are partly bond by a resin bond part ( 24 ) made of a thermosetting material of a thermosetting resin, and a metal powder ( 25 ) is included in the resin bond parts ( 24 ) in a dispersed state. The metal powder ( 25 ) has a melting point lower than a temperature at which the resin bond parts ( 24 ) are heated when a work (a repairing work) is carried out for removing the electronic element ( 2 ) from the circuit board ( 3 ).

Semiconductor device and assembling method thereof

A semiconductor device and an assembling method thereof are provided. The semiconductor device includes a chip, a carrier, a plurality of first conductive elements and a plurality of second conductive elements. The chip has a plurality of first pads. The carrier has a plurality of second pads. The second pads correspond to the first pads. Each first conductive element is disposed between one of the first pads and one of the second pads. Each second conductive element is disposed between one of the first pads and one of the second pads. A volume ratio of intermetallic compound of the second conductive elements is greater than a volume ratio of intermetallic compound of the first conductive elements.

Semiconductor device

A semiconductor device which has a plurality of semiconductor chips stacked on a substrate. The semiconductor device includes semiconductor chip 2 , semiconductor chip 3 a stacked on substrate 4 together with semiconductor chip 2 , and having a foot print larger than semiconductor chip 2 , through electrode 22 extending through semiconductor chip 2 only in a central portion of semiconductor chip 2 , through electrode 32 extending through semiconductor chip 3 a at a position facing to through electrode 22 , and conduction bump 7 b arranged between through electrode 22 and through electrode 32 , and conductively connecting through electrode 22 with through electrode 32.

Electrical Contact Alignment Posts

An electronic apparatus and method of fabrication of the apparatus, the apparatus including a first electronic device having an interconnection surface with a first plurality of interconnection pads extending from the surface by a first distance and a second plurality of alignment posts extending from the surface by a second distance greater than the first distance, and a second electrical device having an interconnection surface with a first plurality of electrical interconnection pads, each pad arranged to contact a corresponding first electronic device interconnection surface pad upon assembly of the first electronic device interconnection surface upon the second electronic device interconnection surface, the second electronic device interconnection surface including a third plurality of alignment posts, each located to be adjacent to at least one of the first electronic device alignment posts upon assembly.

Reducing stress in multi-die integrated circuit structures

An integrated circuit structure can include a first interposer and a second interposer. The first interposer and the second interposer can be coplanar. The integrated circuit structure further can include at least a first die that is coupled to the first interposer and the second interposer.

Heterostructure containing ic and led and method for fabricating the same

A heterostructure containing IC and LED and a method of fabricating. An IC and an LED are established with the IC having a first electric-conduction block and a first connection block. The IC electrically connects to the first electric-conduction block. A first face of the LED has a second electric-conduction block and a second connection block. The LED is electrically connected to the second electric-conduction block. The first electric-conduction block and the first connection block are respectively joined to the second electric-conduction block and the second connection block, and the first electric-conduction block are electrically connected with the second electric-conduction block to form a heterostructure. The heterostructure provides functions of heat radiation and electric communication for IC and LED.

SEMICONDUCTOR ASSEMBLIES INCLUDING THERMAL CIRCUITS AND METHODS OF MANUFACTURING THE SAME

Semiconductor assemblies including thermal layers and associated systems and methods are disclosed herein. In some embodiments, the semiconductor assemblies comprise one or more semiconductor devices over a substrate. The substrate includes a thermal layer configured to transfer thermal energy along a lateral plane and across the substrate. The thermal energy is transferred along a non-lateral direction from the semiconductor device to the graphene layer using one or more thermal connectors. 1. A semiconductor assembly , comprising:a substrate;a semiconductor device over the substrate; anda thermal connector between and directly contacting opposing surfaces of the substrate and the semiconductor device, the thermal connector being configured to transfer thermal energy between the substrate and the semiconductor device;wherein:the substrate includes a graphene layer thermally coupled to the thermal connector and configured to transfer the thermal energy along a horizontal direction across the substrate.2. The semiconductor assembly of claim 1 , further comprising a heat spreader over the substrate and thermally coupled to the graphene thermal layer for receiving and dissipating the thermal energy from the semiconductor device.3. The semiconductor assembly of claim 2 , wherein the heat spreader and the semiconductor device are separated by a distance along the horizontal direction.4. The semiconductor assembly of claim 1 , wherein the substrate is a printed circuit board (PCB) including an external layer above or below the graphene layer.5. The semiconductor assembly of claim 4 , wherein the graphene layer is a core of the PCB.6. The semiconductor assembly of claim 4 , further comprising a core extending parallel to the graphene layer claim 4 , wherein the graphene layer is disposed between the core and the external layer.7. The semiconductor assembly of claim 1 , wherein:the substrate and the semiconductor device comprise a module; andfurther comprising:a second ...

INTEGRATED CIRCUIT DIE WITH IN-CHIP HEAT SINK

A method and apparatus are provided that includes an integrated circuit die having an in-chip heat sink, along with an electronic device and a chip package having the same, and methods for fabricating the same. In one example, an integrated circuit die has an in-chip heat sink that separates a high heat generating integrated circuit from another integrated circuit disposed within the die. The in-chip heat sink provides a highly conductive heat transfer path from interior portions of the die to at least one exposed die surface. 1. An integrated circuit die comprising:a die body having an upper surface and a lower surface, the bottom surfacing having a plurality of bond pad for establishing electrical connection with circuitry within the die body;a first circuit disposed in the die body and electrically coupled to at least one of the bond pads, the first circuit configured to operate at a first temperature;a second circuit disposed in the die body and electrically coupled to at least one of the bond pads, the second circuit configured to operate at a second temperature that is less than the first temperature; andan in-chip heat sink having a ring-shape and an orientation extending between the upper surface and the lower surface, the in-chip heat sink separating the first circuit from the second circuit.2. The integrated circuit die of claim 1 , wherein the in-chip heat sink comprises:vias and lines formed in metals layers of the die body.3. The integrated circuit die of claim 2 , wherein the in-chip heat sink comprises at least one metal layer that is also in the first circuit.4. The integrated circuit die of claim 1 , wherein the in-chip heat sink circumscribes the first circuit.5. The integrated circuit die of claim 1 , wherein interconnect circuitry coupled to the first circuit passes through the in-chip heat sink.6. The integrated circuit die of further comprising:a first dummy metal island disposed in the die body proximate the first circuit and separated from ...

Heat Spreading Device and Method

In an embodiment, a device includes: an integrated circuit die having a first side and a second side opposite the first side; a die stack on the first side of the integrated circuit die; a dummy semiconductor feature on the first side of the integrated circuit die, the dummy semiconductor feature laterally surrounding the die stack, the dummy semiconductor feature electrically isolated from the die stack and the integrated circuit die; a first adhesive disposed between the die stack and the dummy semiconductor feature; and a plurality of conductive connectors on the second side of the integrated circuit die.

THERMAL PADS BETWEEN STACKED SEMICONDUCTOR DIES AND ASSOCIATED SYSTEMS AND METHODS

Systems and methods are described for improved heat dissipation of the stacked semiconductor dies by including metallic thermal pads between the dies in the stack. In one embodiment, the thermal pads may be in direct contact with the semiconductor dies. Heat dissipation of the semiconductor die stack can be improved by a relatively high thermal conductivity of the thermal pads that directly contact the adjacent silicon dies in the stack without the intervening layers of the low thermal conductivity materials (e.g., passivation materials). In some embodiments, the manufacturing yield of the stack can be improved by having generally coplanar top surfaces of the thermal pads and under-bump metallization (UBM) structures. 1. A semiconductor die , comprising:a semiconductor substrate having a first surface and a second surface angled relative to the first surface, wherein the second surface at least partially defines an opening in the first surface;an interconnect extending at least partially through the semiconductor substrate, wherein the interconnect includes an end portion projecting from the opening, and wherein the end portion has a sidewall exposed from the semiconductor substrate in the opening;a metallization structure extending at least partially around the sidewall of the end portion of the interconnect, wherein the metallization structure is laterally spaced apart from the second surface of the semiconductor substrate; anda thermal pad on the first surface of the semiconductor substrate, wherein the thermal pad and the metallization structure project to generally the same vertical height above the first surface of the semiconductor substrate.2. The semiconductor die of claim 1 , further comprising a passivation material at least partially on the first surface of the semiconductor substrate.3. The semiconductor die of claim 1 , further comprising a passivation material in the opening between the metallization structure and the semiconductor substrate.4. The ...

SEMICONDUCTOR MODULE AND SEMICONDUCTOR DEVICE

Connection terminals of a semiconductor module are disposed appropriately in accordance with the connection destination of the semiconductor module. A semiconductor module which includes at least one semiconductor element is mounted on a first surface of a main substrate, which has the first surface on which a first circuit element is mounted and a second surface on which a second circuit element is mounted. A plurality of connection terminals include a first connection terminal group composed of a plurality of first connection terminals to be connected to the first circuit element via the main substrate, and a second connection terminal group composed of a plurality of second connection terminals to be connected to the second circuit element via the main substrate. The first connection terminal group is disposed on the outer peripheral side with respect to the second connection terminal group. 1. A semiconductor module mounted on a first surface of a main substrate and including at least one semiconductor element , with a first circuit element mounted on the first surface and with a second circuit element mounted on a second surface on an opposite side from the first surface , the semiconductor module comprising:a plurality of connection terminals disposed in a shape of a plurality of rectangular rings on a side of a facing surface that faces the main substrate to be connected to the main substrate, wherein:the plurality of connection terminals include a first connection terminal group composed of a plurality of first connection terminals to be connected to the first circuit element via the main substrate, and a second connection terminal group composed of a plurality of second connection terminals to be connected to the second circuit element via the main substrate; andthe first connection terminal group is disposed on an outer peripheral side with respect to the second connection terminal group.2. The semiconductor module according to claim 1 , wherein when ...

Semiconductor Devices, Methods of Manufacture Thereof, and Semiconductor Device Packages

Semiconductor devices, methods of manufacture thereof, and semiconductor device packages are disclosed. In one embodiment, a semiconductor device includes an insulating material layer having openings on a surface of a substrate. One or more insertion bumps are disposed over the insulating material layer. The semiconductor device includes signal bumps having portions that are not disposed over the insulating material layer. 1. A method of manufacturing a semiconductor device , the method comprising:forming a insulating material layer over a first substrate;removing a first portion of the insulating material layer to expose a contact pad at a top surface of the first substrate;forming one or more first insertion bumps over the insulating material layer; andwhile forming the one or more first insertion bumps, forming a first signal bump extending through the insulating material layer and electrically connected to the contact pad.2. The method according to claim 1 , wherein forming the one or more first insertion bumps and forming the first signal bump comprises:patterning a mask to form a first opening over the contact pad on the top surface of the first substrate, and to form one or more second openings over one or more areas of the insulating material layer over which the one or more first insertion bumps will be formed;performing a first plating process with a first conductive material to deposit the first conductive material in the first opening and the one or more second openings; andremoving the mask.3. The method according to claim 2 , further comprising:before removing the mask, performing a second plating process with a second conductive material to deposit the second conductive material in the first opening of the mask and the one or more second openings of the mask, wherein the second conductive material is different than the first conductive material.4. The method according to claim 2 , further comprising patterning the insulating material layer to remove ...

Semiconductor Device and Method of Forming PoP Semiconductor Device with RDL Over Top Package

A PoP semiconductor device has a top semiconductor package disposed over a bottom semiconductor package. The top semiconductor package has a substrate and a first semiconductor die disposed over the substrate. First and second encapsulants are deposited over the first semiconductor die and substrate. A first build-up interconnect structure is formed over the substrate after depositing the second encapsulant. The top package is disposed over the bottom package. The bottom package has a second semiconductor die and modular interconnect units disposed around the second semiconductor die. A second build-up interconnect structure is formed over the second semiconductor die and modular interconnect unit. The modular interconnect units include a plurality of conductive vias and a plurality of contact pads electrically connected to the conductive vias. The I/O pattern of the build-up interconnect structure on the top semiconductor package is designed to coincide with the I/O pattern of the modular interconnect units.

SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF

A semiconductor device is disclosed, which includes: a substrate having a substrate body and a plurality of conductive pads formed on the substrate body, wherein each of the conductive pads has at least an opening formed in a first surface thereof; a semiconductor component having a plurality of bonding pads; a plurality of conductive elements formed between the bonding pads and the conductive pads and in the openings of the conductive pads; and an encapsulant formed between the substrate and the semiconductor component for encapsulating the conductive elements, thereby strengthening the bonding between the conductive elements and the conductive pads and consequently increasing the product yield. 1. A semiconductor device , comprising:a substrate having a substrate body and a plurality of conductive pads formed on the substrate body, wherein each of the conductive pads has at least an opening formed in a first surface thereof;a semiconductor component having a plurality of bonding pads;a plurality of conductive elements formed between the bonding pads and the conductive pads and in the openings of the conductive pads so as to electrically connect the semiconductor component to the substrate via the conductive elements; andan encapsulant formed between the substrate and the semiconductor component and encapsulating the conductive elements.2. The semiconductor device of claim 1 , further comprising a solder mask layer formed on the substrate body and the conductive pads and having a plurality of openings for exposing the openings of the conductive pads.3. The semiconductor device of claim 1 , wherein each of the conductive pads further has a second surface opposite to the first surface claim 1 , and the opening of the conductive pad penetrates the first and second surfaces of the conductive pad for exposing a portion of the substrate body claim 1 , thus allowing the corresponding conductive element to be formed on side walls of the opening and on the exposed portion ...

Heat Spreading Device and Method

In an embodiment, a device includes: an integrated circuit die having a first side and a second side opposite the first side; a die stack on the first side of the integrated circuit die; a dummy semiconductor feature on the first side of the integrated circuit die, the dummy semiconductor feature laterally surrounding the die stack, the dummy semiconductor feature electrically isolated from the die stack and the integrated circuit die; a first adhesive disposed between the die stack and the dummy semiconductor feature; and a plurality of conductive connectors on the second side of the integrated circuit die. 1. A method comprising:providing a device wafer comprising an integrated circuit die, the integrated circuit die having a front side and a back side opposite the front side;bonding a die stack to the front side of the integrated circuit die;singulating the integrated circuit die from the device wafer;after singulating the integrated circuit die, bonding a dummy semiconductor feature to the front side of the integrated circuit die, the dummy semiconductor feature laterally surrounding the die stack, the dummy semiconductor feature contacting at least a majority of the front side of the integrated circuit die; andbonding a package substrate to the back side of the integrated circuit die.2. The method of claim 1 , wherein bonding the dummy semiconductor feature to the front side of the integrated circuit die comprises:placing the integrated circuit die on a carrier substrate;bonding a dummy wafer to the integrated circuit die, the dummy wafer comprising the dummy semiconductor feature, the dummy semiconductor feature having a recess, the die stack being disposed in the recess;debonding the integrated circuit die from the carrier substrate; andafter debonding the integrated circuit die, singulating the dummy semiconductor feature from the dummy wafer.3. The method of further comprising:thinning the dummy wafer until the recess is exposed, thereby forming an opening ...

Heat Spreading Device and Method

In an embodiment, a device includes: an integrated circuit die having a first side and a second side opposite the first side; a die stack on the first side of the integrated circuit die; a dummy semiconductor feature on the first side of the integrated circuit die, the dummy semiconductor feature laterally surrounding the die stack, the dummy semiconductor feature electrically isolated from the die stack and the integrated circuit die; a first adhesive disposed between the die stack and the dummy semiconductor feature; and a plurality of conductive connectors on the second side of the integrated circuit die. 1. A device comprising:an integrated circuit die having a first side and a second side opposite the first side;a die stack on the first side of the integrated circuit die;a dummy semiconductor feature on the first side of the integrated circuit die, the dummy semiconductor feature being bonded to the integrated circuit die by covalent bonds between a material of the dummy semiconductor feature and a material of the integrated circuit die, the dummy semiconductor feature laterally surrounding the die stack, the dummy semiconductor feature electrically isolated from the die stack and the integrated circuit die;a first adhesive disposed between the die stack and the dummy semiconductor feature; anda plurality of conductive connectors on the second side of the integrated circuit die.2. The device of claim 1 , wherein top surfaces of the dummy semiconductor feature claim 1 , the die stack claim 1 , and the first adhesive are level.3. The device of claim 2 , wherein the dummy semiconductor feature extends laterally past edges of the integrated circuit die.4. The device of claim 2 , wherein edges of the dummy semiconductor feature and the integrated circuit die are coterminous.5. The device of claim 1 , wherein the first adhesive is disposed on the die stack claim 1 , and the dummy semiconductor feature is disposed on the first adhesive.6. The device of claim 1 , ...

Leadframes in Semiconductor Devices

In one instance, a method of forming a semiconductor package with a leadframe includes cutting, such as with a laser, a first side of a metal strip to a depth D according to a cutting pattern to form a first plurality of openings, which may be curvilinear. The method further includes etching the second side of the metal strip to a depth D according to a photoresist pattern to form a second plurality of openings. At least some of the first plurality of openings are in fluid communication with at least some of the second plurality of openings to form a plurality of leadframe leads. The depth D is shallower than a height H of the metal strip, and the depth D is also shallower than the height H. Other embodiments are presented. 1. A method for forming a semiconductor package , the method comprising:cutting a first side of the metal strip to a first depth according to a cutting pattern to form a plurality of first channels, wherein the first depth is less than a height of the metal strip;etching a second side of the metal strip, opposing the first side to form a second plurality of channels including a second depth less than the height of the metal strip;coupling a plurality of bumps of a semiconductor die to the first side of the metal strip; andcovering at least a portion of the semiconductor die and at least a portion of the metal strip with a molding compound, wherein the cutting pattern is non-linear.2. The method of claim 1 , wherein the cutting is performed after etching.3. The method of claim 1 , wherein the height of the metal strip is between the first side and the second side of the metal strip.4. The method of claim 1 , wherein the plurality of bumps are aligned in multiple rows claim 1 , at least one of the plurality of bumps from at least two adjacent rows of the multiple rows overlap with each other from a side view of the semiconductor package.5. The method of claim 1 , wherein the second depth is more than the first depth.6. The method of claim 1 , ...

Semiconductor device

A semiconductor device includes an extended semiconductor chip including a first semiconductor chip and an extension outwardly extending from a side surface of the first semiconductor chip; and a second semiconductor chip connected to the extended semiconductor chip through a plurality of bumps and electrically connected to the first semiconductor chip. The first semiconductor chip is smaller than the second semiconductor chip. At least one external terminal is provided on the extension.

CONDUCTIVE CONNECTIONS, STRUCTURES WITH SUCH CONNECTIONS, AND METHODS OF MANUFACTURE

A solder connection may be surrounded by a solder locking layer () and may be recessed in a hole () in that layer. The recess may be obtained by evaporating a vaporizable portion () of the solder connection. Other features are also provided. 1. A manufacturing method comprising: one or more first components each of which comprises solder and a material sublimatable or vaporizable when the solder is melted; and', 'a first layer comprising a top surface and one or more holes in the top surface, each hole containing at least a segment of a corresponding first component;, 'obtaining a first structure comprisingheating each first component to sublimate or vaporize at least part of each sublimatable or vaporizable material and provide an electrically conductive connection at a location of each first component;wherein in the heating operation at least part of each first component recedes down from the top surface to provide or increase a recess in each hole at the top surface.2. The method of wherein each hole is a through-hole.3. The method of wherein each hole's sidewall is a dielectric sidewall.4. The method of wherein the first layer is dielectric.5. The method of wherein the first layer is formed by molding.6. The method of further comprising:obtaining a second structure with one or more protruding conductive posts; andinserting each conductive post into a corresponding recess provided or increased in the heating operation, and forming a solder bond in each recess between the corresponding conductive post and the corresponding electrically conductive connection.7. The method of wherein before the heating operation claim 1 , at least a segment of each first component either:comprises of a solder core coated with the sublimatable or vaporizable material; orconsists of the sublimatable or vaporizable material.8. The method of wherein in obtaining the first structure claim 7 , the one or more first components are formed before the first layer.9. The method of wherein in ...

Flexible circuit board for chip on film and chip package comprising the same, and electronic device comprising the same

A flexible circuit board for a chip on film according to an embodiment includes: a substrate including a first surface and a second surface opposite to the first surface and including a chip mounting region; a circuit pattern layer disposed on the first surface; and a heat dissipation part disposed in the chip mounting region, wherein the substrate is formed with at least two or more holes that are formed in a region overlapping the heat dissipation part, and the heat dissipation part includes: a heat dissipation pattern layer disposed on the first surface; a connection layer disposed inside the hole; and a heat dissipation layer disposed on the second surface.

Semiconductor device having planarized passivation layer and method of fabricating the same

A semiconductor device includes a semiconductor substrate divided into a pad region and a cell region and having an active surface and an inactive surface opposite to the active surface, a plurality of metal lines on the active surface of the semiconductor substrate, passivation layers on the active surface of the semiconductor substrate, and a plurality of bumps in the cell region. The passivation layers include a first passivation layer covering the plurality of metal lines and having a non-planarized top surface along an arrangement profile of the plurality of metal lines, and a second passivation layer on the non-planarized top surface of the first passivation layer and having a planarized top surface on which the plurality of bumps are disposed.

Semiconductor Die Package and Method of Manufacture

In an embodiment, an interposer has a first side, a first integrated circuit device attached to the first side of the interposer with a first set of conductive connectors, each of the first set of conductive connectors having a first height, a first die package attached to the first side of the interposer with a second set of conductive connectors, the second set of conductive connectors including a first conductive connector and a second conductive connector, the first conductive connector having a second height, the second conductive connector having a third height, the third height being different than the second height, a first dummy conductive connector being between the first side of the interposer and the first die package, an underfill disposed beneath the first integrated circuit device and the first die package, and an encapsulant disposed around the first integrated circuit device and the first die package.

Semicondcutor device and semicondcutor package

A semiconductor package includes a die, a passivation layer, a plurality of first electrical conductive vias, a plurality of second electrical conductive vias, a plurality of thermal conductive vias and a connecting pattern. The die includes a plurality of first pads and a plurality of second pads. The passivation layer is disposed on the die. The first electrical conductive vias and the second electrical conductive vias extend through the passivation layer and contact the first pads and the second pads respectively. The thermal conductive vias are disposed on the passivation layer. Each of the thermal conductive vias is spaced apart from the first and second electrical conductive vias. The connecting pattern is disposed on the passivation layer and connects the first electrical conductive vias and the thermal conductive vias. The thermal conductive vias are connected to the first pads through the connecting pattern and the first electrical conductive vias.

Die-on-Interposer Assembly with Dam Structure and Method of Manufacturing the Same

A semiconductor package includes an interposer chip having a frontside, a backside, and a corner area on the backside defined by a first corner edge and a second corner edge of the interposer chip. A die is bonded to the frontside of the interposer chip. At least one dam structure is formed on the corner area of the backside of the interposer chip. The dam structure includes an edge aligned to at least one the first corner edge and the second corner edge of the interposer chip. 1. A package comprising:a chip having a frontside and a backside, the chip comprising four corner areas;a die bonded to the frontside of the chip by a first set of conductive connectors;a molding layer on the frontside of the chip and surrounding sidewalls of the die;a dam structure in each of the four corner areas on the backside of the chip, each of the dam structures being disposed a distance from an edge of the chip, each of the dam structures being circular in a plane parallel to the backside of the chip; anda second set of conductive connectors on the backside of the chip.2. The package of claim 1 , wherein the dam structure is electrically isolated from the chip.3. The package of claim 1 , wherein a distance between the frontside of the chip and a surface of the molding layer distal the frontside of the chip is greater than a distance between the frontside of the chip and a surface of the die distal the frontside of the chip.4. The package of claim 1 , further comprising a through via extending through the chip.5. The package of claim 4 , wherein the through via comprises a metal via and a barrier layer lining sidewalls of the metal via.6. The package of claim 5 , further comprising an insulation layer between the chip and the through via claim 5 , the insulation layer comprising an oxide.7. The package of claim 1 , wherein the dam structure comprises a polymer material.8. The package of claim 1 , wherein a diameter of the dam structure is less than a diameter of each of the conductive ...

ELECTRONIC COMPONENT-MOUNTED BODY AND METHOD FOR MANUFACTURING SAME

An electronic component-mounted body () in accordance with an embodiment of the present invention is configured such that an IC chip () is fixed, with use of a post () having a thermosetting property, to a wiring substrate () having an anisotropic linear expansion coefficient. 1. An electronic component-mounted body comprising:a wiring substrate; andan electronic component including a terminal connected to wiring of the wiring substrate by soldering,the electronic component being fixed to the wiring substrate with use of a post which is made of a thermosetting resin and not in contact with the wiring and the terminal.2. The electronic component-mounted body as set forth in claim 1 , wherein:the electronic component is an IC chip including a plurality of the terminals arranged in a peripheral part of a back surface of the IC chip; andthe post is provided in a region surrounded by the plurality of the terminals.3. The electronic component-mounted body as set forth in claim 1 , wherein:a linear expansion coefficient of the wiring substrate with respect to a first direction parallel to a substrate surface of the wiring substrate is greater than a linear expansion coefficient of the wiring substrate with respect to a second direction which is parallel to the substrate surface and different from the first direction; anda width of a contact surface between the wiring substrate and the post as measured along the first direction is greater than a width of the contact surface as measured along the second direction.4. The electronic component-mounted body as set forth in claim 3 , wherein the contact surface between the wiring substrate and the post has a shape of an ellipse having a long axis parallel to the first direction and a short axis parallel to the second direction.5. The electronic component-mounted body as set forth in claim 3 , wherein the contact surface between the wiring substrate and the post has a shape of a cross which is a combination of (i) a first ...

IMAGE PICKUP APPARATUS

An image pickup apparatus includes: an image pickup device including a light receiving surface, an opposite surface, and an inclined surface, and provided with light receiving surface electrodes formed on the light receiving surface; cover glass joined so as to cover the light receiving surface; and a wiring board including second bond electrodes, wherein back surfaces of the light receiving surface electrodes being exposed to an opposite surface side, extended wiring patterns extended from the respective back surfaces of the light receiving surface electrodes through the inclined surface to the opposite surface, each of the extended wiring patterns including a first bond electrode, and the first bond electrode and the second bond electrode being bonded through a bump. 1. An image pickup apparatus comprising:an image pickup device including a light receiving surface where a light receiving portion is formed, an opposite surface opposing the light receiving surface, and an inclined surface inclined at an acute first angle to the light receiving surface, and provided with a plurality of light receiving surface electrodes electrically connected with the light receiving portion and formed on the light receiving surface;a transparent member joined so as to cover the light receiving surface; anda wiring board including a plurality of second bond electrodes on a main surface,wherein the transparent member and the plurality of light receiving surface electrodes are extended to an outside of an end side of the inclined surface, and back surfaces of the plurality of light receiving surface electrodes are exposed to a side of the opposite surface,the image pickup device includes a plurality of extended wiring patterns extended from the respective back surfaces of the plurality of light receiving surface electrodes through the inclined surface to the opposite surface, each of the extended wiring patterns including a first bond electrode on the opposite surface, andthe main ...

SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME

Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package comprises a redistribution substrate including dielectric and redistribution patterns, a first substrate pad on the redistribution substrate and penetrating the dielectric pattern to be coupled to the redistribution pattern, a second substrate pad the redistribution substrate and spaced apart from the first substrate pad, a semiconductor chip on the redistribution substrate, a first connection terminal connecting the first substrate pad to one of chip pads of the semiconductor chip, and a second connection terminal connecting the second substrate pad to another one of the chip pads of the semiconductor chip. A top surface of the second substrate pad is located at a higher level than that of a top surface of the first substrate pad. A width of the second substrate pad is less than that of the first substrate pad. 1. A semiconductor package , comprising:a redistribution substrate that includes a dielectric pattern and a redistribution pattern in the dielectric pattern;a first substrate pad on a top surface of the redistribution substrate, the first substrate pad penetrating the dielectric pattern and being coupled to the redistribution pattern;a second substrate pad on the top surface of the redistribution substrate and spaced apart from the first substrate pad;a semiconductor chip on the redistribution substrate;a first connection terminal that connects the first substrate pad to one of chip pads of the semiconductor chip; anda second connection terminal that connects the second substrate pad to another one of the chip pads of the semiconductor chip,wherein a top surface of the second substrate pad is located at a level higher than a level of a top surface of the first substrate pad, andwherein a width of the second substrate pad is less than a width of the first substrate pad.2. The semiconductor package of claim 1 , whereinthe width of the first substrate pad is ...

SEMICONDUCTOR ASSEMBLIES INCLUDING THERMAL CIRCUITS AND METHODS OF MANUFACTURING THE SAME

Semiconductor assemblies including thermal layers and associated systems and methods are disclosed herein. In some embodiments, the semiconductor assemblies comprise one or more semiconductor devices over a substrate. The substrate includes a thermal layer configured to transfer thermal energy across the substrate. The thermal energy is transferred from the semiconductor device to the graphene layer using one or more thermal connectors. 1. A semiconductor assembly , comprising:a substrate having a top surface and including a graphene layer below the top surface and configured to transfer thermal energy along a lateral direction across the substrate;a semiconductor device over the top surface of the substrate;a thermal connector between the substrate and the semiconductor device, the thermal connector being configured to transfer the thermal energy from the semiconductor device to the graphene layer; anda heat spreader over the top surface of the substrate and between opposing peripheral edges of the substrate, the heat spreader thermally coupled to the graphene layer2. The semiconductor assembly of claim 1 , wherein the heat spreader is directly connected to the substrate at a location laterally displaced from the thermal connector.3. The semiconductor assembly of claim 1 , wherein the thermal connector is electrically isolated from circuits within the semiconductor device.4. The semiconductor assembly of claim 1 , wherein thermal connector is electrically connected an electrical ground or a power input for one or more circuits within the semiconductor device.5. The semiconductor assembly of claim 1 , wherein:the thermal connector is directly attached to a bottom portion of the semiconductor device; andthe heat spreader is further thermally coupled to a top portion of the semiconductor device.6. The semiconductor assembly of claim 1 , wherein:the substrate is a printed circuit board (PCB),the graphene layer is a core of the PCB, andthe PCB includes thermal paths ...

INTEGRATED DEVICE COMPRISING A HEAT-DISSIPATION LAYER PROVIDING AN ELECTRICAL PATH FOR A GROUND SIGNAL

Provided herein is an integrated device that includes a substrate, a die, a heat-dissipation layer located between the substrate and the die, and a first interconnect configured to couple the die to the heat-dissipation layer. The heat-dissipation layer may be configured to provide an electrical path for a ground signal. The first interconnect may be further configured to conduct heat from the die to the heat-dissipation layer. The integrated device may also include a second interconnect configured to couple the die to the substrate. The second interconnect may be further configured to conduct a power signal between the die and the substrate. The integrated device may also include a dielectric layer located between the heat-dissipation layer and the substrate, and a solder-resist layer located between the die and the heat-dissipation layer. 1. An integrated device comprising:a substrate;a die;a heat-dissipation layer disposed on a surface of the substrate and located between the substrate and the die;a first interconnect configured to couple the die to the heat-dissipation layer, wherein the heat-dissipation layer is configured to provide an electrical path for a ground signal and the heat-dissipation layer is adjacent to the first interconnect; anda second interconnect configured to couple the die to the substrate, wherein the second interconnect is electrically isolated from the heat-dissipation layer by a solder-resist layer.2. The integrated device of claim 1 , wherein the first interconnect is further configured to conduct heat from the die to the heat-dissipation layer.3. (canceled)4. The integrated device of claim 1 , wherein the second interconnect is configured to conduct a power signal between the die and the substrate.5. The integrated device of claim 1 , wherein the second interconnect is configured to couple the die to the substrate through an opening in the heat-dissipation layer.6. The integrated device of claim 1 , further comprising:a dielectric ...

SEMICONDUCTOR PACKAGE

A semiconductor package includes a substrate comprising a top surface and a back surface, a semiconductor chip having a plurality of functions and mounted on the top surface of the substrate, and a plurality of balls formed on the back surface of the substrate to connect the substrate to an external substrate of the semiconductor package. The substrate further comprises a plurality of electrodes that correspond to the plurality of functions and are formed on the back surface of the substrate, and a subset of the plurality of electrodes corresponds to a subset of the plurality of functions, and each of the plurality of balls is respectively disposed on each of the electrodes in the subset. 1. A semiconductor package , comprising:a substrate comprising a top surface and a back surface;a semiconductor chip having a plurality of functions and mounted on the top surface of the substrate; anda plurality of balls formed on the back surface of the substrate to connect the substrate to an external substrate of the semiconductor package, wherein,the substrate further comprises a plurality of electrodes that correspond to the plurality of functions and are formed on the back surface of the substrate, anda subset of the plurality of electrodes corresponds to a subset of the plurality of functions, and each of the plurality of balls is respectively disposed on each of the electrodes in the subset.2. The semiconductor package according to claim 1 , whereinthe back surface of the substrate comprises a plurality of regions corresponding to the plurality of functions, andeach of the plurality of electrodes is respectively formed in the corresponding regions of the plurality of regions.3. The semiconductor package according to claim 1 , whereinthe electrodes in the subset that correspond to the subset of functions are disposed in a zigzag pattern, andthe electrodes not in the subset correspond to functions other than the functions in the subset and are disposed adjacent to the ...

Electronic device

An electronic device includes a surface-mounted component and a mounting component on which the surface-mounted component is mounted, the surface-mounted component includes a first bump and a second bump, a cross-sectional area of which in an in-plane direction of a surface facing the mounting component is larger than that of the first bump, on the surface facing the mounting component, the mounting component includes a first pad that is soldered to the first bump and a second pad soldered to the second bump on the surface facing the surface-mounted component, and a ratio of an area of the second pad to the cross-sectional area of the second bump is larger than a ratio of an area of the first pad to the cross-sectional area of the first bump.

SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor package includes a first die having a first surface, a first conductive bump over the first surface and having first height and a first width, a second conductive bump over the first surface and having a second height and a second width. The first width is greater than the second width and the first height is substantially identical to the second height. A method for manufacturing the semiconductor package is also provided.

Fabricating pillar solder bump

A substrate bonding method is able to reliably bond substrates while avoiding a reduction in yield made worse by finer pitches. The substrate bonding method can include: forming an adhesive resin layer on a surface of a first substrate on which a pad has been formed; forming an opening on the adhesive resin layer above the pad; filling the opening with molten solder to form a pillar-shaped solder bump; and applying heat and pressure to the first substrate and a second substrate while a terminal formed on the second substrate is aligned with the solder bump.

SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF

A semiconductor package includes an interconnect component surrounded by a molding compound. The interconnect component comprises a first RDL structure. A second RDL structure is disposed on the interconnect component. A plurality of first connecting elements is disposed on the second RDL structure. A polish stop layer covers a surface of the interconnect component. A plurality of second connecting elements is disposed on and in the polish stop layer. At least one semiconductor die is mounted on the second connecting elements. 1. A method for fabricating a semiconductor device , comprising:forming a first redistribution layer (RDL) structure on a polish stop material on a first carrier;subjecting the first RDL structure and the first carrier to a first singulation process to separate individual interconnect components from one another;rearranging and mounting the individual interconnect components onto a second carrier;forming a molding compound covering the individual interconnect components;removing the second carrier to expose a surface of the first RDL structure of each of the individual interconnect components;forming a second RDL structure on the exposed surface of the first RDL structure and on the molding compound;forming first connecting elements on the second RDL structure;bonding the first connecting elements to a third carrier;grinding the molding compound and the first carrier;completely removing a remaining portion of the first carrier to form a recess to expose the polish stop material;polishing the molding compound such that a top surface of the polish stop material is coplanar with a top surface of the molding compound;forming openings in the polish stop material; andforming second connecting elements in the openings respectively.2. The method of claim 1 , wherein after forming the second connecting elements in the openings claim 1 , respectively claim 1 , the method further comprises:mounting semiconductor dies on the second connecting elements; ...

Semiconductor package with air gap

The present application provides a semiconductor package with air gaps for reducing capacitive coupling between conductive features and a method for manufacturing the semiconductor package. The semiconductor package includes a first semiconductor structure and a second semiconductor structure bonded with the first semiconductor structure. The first semiconductor structure has a first bonding surface. The second semiconductor structure has a second bonding surface partially in contact with the first bonding surface. A portion of the first bonding surface is separated from a portion of the second bonding surface, a space between the portions of the first and second bonding surfaces is sealed and forms an air gap in the semiconductor package.

SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATING THE SAME

A semiconductor structure includes a semiconductor wafer, a first surface mount component, a second surface mount component and a first barrier structure. The first surface mount component is disposed on the semiconductor wafer, and electrically connected to the semiconductor wafer through a plurality of first electrical connectors. The second surface mount component is disposed on the semiconductor wafer, and electrically connected to the semiconductor wafer through a plurality of second electrical connectors, wherein an edge of the second surface mount component is overhanging a periphery of the semiconductor wafer. The first barrier structure is disposed on the semiconductor wafer in between the second electrical connectors and the edge of the second surface mount component, wherein a first surface of the first barrier structure is facing the second electrical connectors, and a second surface of the first barrier structure is facing away from the second electrical connectors. 1. A semiconductor structure , comprising:a semiconductor wafer;a first surface mount component disposed on the semiconductor wafer, and electrically connected to the semiconductor wafer through a plurality of first electrical connectors;a second surface mount component disposed on the semiconductor wafer, and electrically connected to the semiconductor wafer through a plurality of second electrical connectors, wherein an edge of the second surface mount component is overhanging a periphery of the semiconductor wafer; anda first barrier structure disposed on the semiconductor wafer in between the plurality of second electrical connectors and the edge of the second surface mount component, wherein a first surface of the first barrier structure is facing the plurality of second electrical connectors, and a second surface of the first barrier structure is facing away from the plurality of second electrical connectors.2. The semiconductor structure according to claim 1 , further comprising:a ...

Polymer Layers Embedded with Metal Pads for Heat Dissipation

An integrated circuit structure includes a metal pad, a passivation layer including a portion over the metal pad, a first polymer layer over the passivation layer, and a first Post-Passivation Interconnect (PPI) extending into to the first polymer layer. The first PPI is electrically connected to the metal pad. A dummy metal pad is located in the first polymer layer. A second polymer layer is overlying the first polymer layer, the dummy metal pad, and the first PPI. An Under-Bump-Metallurgy (UBM) extends into the second polymer layer to electrically couple to the dummy metal pad. 1. An integrated circuit structure comprising:a metal pad;a passivation layer comprising a portion over the metal pad;a first polymer layer comprising a portion over the passivation layer;a dummy metal pad in the first polymer layer, wherein the dummy metal pad is electrically floating;a second polymer layer over the first polymer layer and the dummy metal pad; anda first Under-Bump-Metallurgy (UBM) extending into the second polymer layer to electrically couple to the dummy metal pad.2. The integrated circuit structure of claim 1 , wherein a top surface and a bottom surface of the dummy metal pad are coplanar with a top surface and a bottom surface claim 1 , respectively claim 1 , of the first polymer layer.3. The integrated circuit structure of further comprising:a package component comprising a surface metallic feature; anda solder region bonding the surface metallic feature in the package component to the first UBM, wherein the dummy metal pad, the solder region, and the surface metallic feature in combination are electrically floating.4. The integrated circuit structure of further comprising:a third polymer layer between the first polymer layer and the second polymer layer; anda Post-Passivation Interconnect (PPI) extending into to the third polymer layer, wherein the PPI electrically couples the dummy metal pad to the first UBM.5. The integrated circuit structure of further comprising: ...

CHIP PACKAGE STRUCTURE

A chip package structure is provided. The chip package structure includes a substrate. The chip package structure includes a chip over the substrate. The chip package structure includes a first bump and a first dummy bump between the chip and the substrate. The first bump is electrically connected between the chip and the substrate, the first dummy bump is electrically insulated from the substrate, the first dummy bump is between the first bump and a corner of the chip, and the first dummy bump is wider than the first bump. 1. A chip package structure , comprising:a substrate;a chip over the substrate; anda first bump and a first dummy bump between the chip and the substrate, wherein the first bump is electrically connected between the chip and the substrate, the first dummy bump is electrically insulated from the substrate, the first dummy bump is between the first bump and a corner of the chip, and the first dummy bump is wider than the first bump.2. The chip package structure as claimed in claim 1 , wherein the first dummy bump has a first strip portion and a second strip portion claim 1 , and the first strip portion is not parallel to the second strip portion.3. The chip package structure as claimed in claim 2 , wherein the chip has a first edge and a second edge claim 2 , the first edge and the second edge meet at the corner of the chip claim 2 , and the first strip portion is substantially parallel to the first edge.4. The chip package structure as claimed in claim 3 , wherein the second strip portion is substantially parallel to the second edge.5. The chip package structure as claimed in claim 1 , further comprising:an underfill layer between the chip and the substrate and between the first dummy bump and the substrate.6. The chip package structure as claimed in claim 1 , further comprising:a second bump between the first bump and the substrate; anda second dummy bump between the chip and the substrate, wherein the second dummy bump is connected to the ...

Methods and Apparatus for Package on Package Devices

Package on package (PoP) devices and methods of packaging semiconductor dies are disclosed. A PoP device is formed by connecting a top package and a bottom package together using a plurality of PoP connectors on the bottom package connected to corresponding connectors of the top package. The PoP device further comprises a plurality of dummy connectors contained in the bottom package and not connected to any corresponding connector in the top package. 1. A device comprising:a first substrate;a first die attached to a first surface of the first substrate;a second substrate attached to the first substrate, the first die being interposed between the first substrate and the second substrate;one or more signaling connectors interposed between the first substrate and the second substrate; andone or more dummy connectors interposed between the first substrate and the second substrate, the one or more dummy connectors not passing electrical signals between the first substrate and the second substrate, the one or more dummy connectors being connected to only one of first substrate and the second substrate.2. The device of claim 1 , further comprising one or more intermediate connectors electrically coupling the one or more signaling connectors to the second substrate.3. The device of claim 2 , wherein the one or more intermediate connectors comprise solder balls.4. The device of claim 1 , further comprising an encapsulant claim 1 , wherein the first die is exposed through the encapsulant.5. The device of claim 4 , wherein the encapsulant encircles the one or more dummy connectors and the one or more signaling connectors.6. The device of claim 1 , further comprising an encapsulant claim 1 , wherein the encapsulant covers an upper surface of the first die.7. The device of claim 1 , wherein a first dummy connector of the one or more dummy connectors is of a different size from a first signaling connector of the one or more signaling connectors.8. The device of claim 1 , wherein ...

Semiconductor chip including through electrode, and semiconductor package including the same

A semiconductor chip includes a body portion with a front surface and a rear surface; a through electrode penetrating the body portion; a wiring portion that is disposed over the front surface of the body portion; a rear connection electrode that is disposed over the rear surface of the body portion; and a front connection electrode that s disposed over the wiring portion, wherein the rear connection electrode includes a power rear connection electrode that is simultaneously connected to two or more power through electrodes, and wherein a width of the power rear connection electrode is greater than a width of the front connection electrode.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device includes a substrate, a package, first conductors and second conductors. The substrate includes a first surface and a second surface opposite to the first surface. The package is disposed over the substrate. The first conductors are disposed over the substrate. The second conductors are disposed over the substrate, wherein the first conductors and the second conductors are substantially at a same tier, and a width of the second conductor is larger than a width of the first conductor. 1. A semiconductor device , comprising:a substrate including a first surface and a second surface opposite to the first surface;a package over the substrate;a plurality of first conductors over the substrate;a plurality of second conductors over the substrate, wherein the plurality of first conductors and the plurality of the second conductors are substantially at a same tier, and a width of a second conductor of the plurality of second conductors is larger than a width of a first conductor of the plurality of first conductors;a plurality of first bonding pads on the substrate and configured to receive and electrically connect to the plurality of first conductors, respectively;a plurality of second bonding pads on the substrate and configured to receive and electrically connect to the plurality of second conductors, respectively; anda passivation layer over the substrate, wherein the passivation layer includes a plurality of first recesses exposing the plurality of first bonding pads respectively, and a plurality of second recesses exposing the plurality of second bonding pads respectively, and a width of the first recess is wider than a width of the second recess, wherein the first conductor is apart from an edge of the respective first recess, and the second conductor is in contact with an edge of the respective second recess.2. The semiconductor device of claim 1 , wherein a volume of a second conductor of the plurality of second conductors is substantially ...

UNIFORM ELECTROCHEMICAL PLATING OF METAL ONTO ARRAYS OF PILLARS HAVING DIFFERENT LATERAL DENSITIES AND RELATED TECHNOLOGY

A semiconductor die assembly in accordance with an embodiment of the present technology includes first and second semiconductor dies spaced apart from one another. The first semiconductor die has a major surface with non-overlapping first and second regions. The semiconductor die assembly further includes an array of first pillars extending heightwise from the first region of the major surface of the first semiconductor die toward the second semiconductor die. Similarly, the semiconductor die assembly includes an array of second pillars extending heightwise from the second region of the major surface of the first semiconductor die toward the second semiconductor die. The first and second pillars have different lateral densities and different average widths. The latter difference at least partially offsets an effect of the former difference on relative metal deposition rates of an electrochemical plating process used to form the first and second pillars. 1. A method of forming pillars in a semiconductor die assembly , comprising:forming a first pattern of first and a second pattern of second holes in a material on a semiconductor die; anddepositing a conductive material into the first holes to a first elevation relative to the surface of the material and concurrently depositing the conductive material into the second holes to a second elevation relative to the surface of the material, wherein the first elevation is different than the second elevation;wherein the conductive material in the first holes define first pillars having a first height from a major surface of the semiconductor die and the conductive material in the second holes define second pillars having a second height from the major surface of the semiconductor die, wherein the first height is different than the second height.2. The method of wherein:the first holes have a first average width and the second holes have a second average width, and the first average width is greater than the second average ...

SEMICONDUCTOR METHOD FOR FORMING SEMICONDUCTOR STRUCTURE HAVING BUMP ON TILTING UPPER CORNER SURFACE

A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate and a first conductive bump. The semiconductor substrate has an integrated circuit and an interconnection metal layer, and a tilt surface is formed on an edge of the semiconductor substrate. The first conductive bump is electrically connected to the integrated circuit via the interconnection metal layer, and is disposed on the tilt surface, wherein a profile of the first conductive bump extends beyond a side surface of the edge of the semiconductor layer. 1. A method for forming a semiconductor device , the method comprising:forming a tilt surface on an edge each of at least one semiconductor substrate having an integrated circuit and an interconnection metal layer; andforming a first conductive bump on the tilt surface, wherein the first conductive bump is electrically connected to the integrated circuit via the interconnection metal layer, and a profile of the first conductive bump extends beyond a side surface of the edge.2. The method for forming a semiconductor device of claim 1 , wherein the at least one semiconductor substrate includes two semiconductor substrates claim 1 , the method further comprising:jointing the first conductive bumps of the two semiconductor substrates so as to connect the two semiconductor structures laterally.3. The method for forming a semiconductor device of claim 1 , wherein forming the tilt surface on the edge of the at least one semiconductor substrate comprises:providing a substrate;forming a passivation layer on the substrate;forming an inclined plane on an edge of the substrate;forming a metal layer on the passivation layer;patterning the metal layer to form a first conductor layer on the passivation layer, wherein an upper surface of a portion of the first conductor layer on the edge of the substrate is the tilt surface;forming a second conductor layer on the passivation layer and the first conductor layer, wherein the second ...

CHIP MOUNTING STRUCTURE

Highly reliable chip mounting is accomplished by using a substrate having such a shape that a stress exerted on a flip-chip-connected chip can be reduced, so that the stress exerted on the chip is reduced and separation of an interlayer insulating layer having a low dielectric constant (low-k) is minimized. Specifically, in a chip mounting structure, a chip including an interlayer insulating layer having a low dielectric constant (low-k) is flip-chip connected to a substrate via bumps is shown. In the chip mounting structure, the substrate has such a shape that a mechanical stress exerted on the interlayer insulating layer at corner portions of the chip due to a thermal stress is reduced, the thermal stress occurring due to a difference in coefficient of thermal expansion between the chip and the substrate. 1. A method for changing a shape of a substrate to reduce stress exerted on an interlayer insulating layer of a chip , the method comprising:providing the substrate;mounting the chip on the substrate such that a center of the chip corresponds to a center of the substrate and such that sides of the chip are parallel to sides of the substrate;measuring a distance B between a side of the chip and a nearest side of the substrate; andcutting off square portions of the substrate from each corner of the substrate such that a distance between a corner of the chip and a nearest corner of the substrate is less than the distance B.2. The method of claim 1 , wherein each square portion has sides of a length c.4. A method for mounting a chip on a substrate claim 1 , the method comprising:providing a chip having an interlayer insulating layer, the interlayer insulating layer having a low dielectric constant;mounting the chip to a substrate such that there is a distance B between a side of the chip and a nearest side of the substrate;connecting the chip to the substrate using flip-chip bumps; andcutting off right-angle isosceles triangle portions of the substrate from each ...

ANTENNA-IN-PACKAGE STRUCTURES WITH BROADSIDE AND END-FIRE RADIATIONS

Package structures are provided having antenna-in-packages that are integrated with semiconductor RFIC (radio frequency integrated circuit) chips to form compact integrated radio/wireless communications systems that operate in the millimeter wave (mmWave) frequency range with radiation in broadside and end-fire directions. 1. A package structure , comprising:an antenna package comprising a stack structure, wherein the stack structure comprises a plurality of substrates and metallization layers including a first metallization layer formed on a first surface of a first substrate, and a second metallization layer formed on first surface of a second substrate, wherein the first metallization layer comprises a first planar antenna and an ungrounded planar parasitic element disposed adjacent to the first planar antenna, and wherein the second metallization layer comprises a second planar antenna; andan RFIC (radio frequency integrated circuit) chip mounted to the second metallization layer of the antenna package, wherein the first planar antenna is connected to the RFIC chip by a first antenna feed line comprising a metalized via hole that is formed through the stack structure, and wherein the second planar antenna is connected to the RFIC chip by a second antenna feed line that is formed as part of the second metallization layer,wherein the first planar antenna is configured to receive or transmit broadside signals and the second planar antenna is configured to receive or transmit end-fire signals, and wherein the ungrounded planar parasitic element is configured to reduce surface waves on the surface of the first substrate.2. The package structure of claim 1 , wherein the ungrounded planar parasitic element comprises a parasitic patch element disposed adjacent to a critical edge of the first planar antenna.3. The package structure of claim 1 , wherein the ungrounded planar parasitic element comprises a parasitic ring element that surrounds the first planar antenna.4. ...

Package-integrated bistable switch for electrostatic discharge (esd) protection

A switch in a package substrate of a microelectronic package is provided, the switch comprising: an actuator plate; a strike plate; and a connecting element mechanically coupling the actuator plate and the strike plate. The switch is configured to move within a cavity inside the package substrate between an open position and a closed position, a conductive material is coupled to the switch and to a ground via in the package substrate, and the conductive material is configured to move with the switch, such that the switch is conductively coupled to the ground via in the open position and the closed position.

SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor package structure includes a semiconductor die surface having a narrower pitch region and a wider pitch region adjacent to the narrower pitch region, a plurality of first type conductive pillars in the narrower pith region, each of the first type conductive pillars having a copper-copper interface, and a plurality of second type conductive pillars in the wider pitch region, each of the second type conductive pillars having a copper-solder interface. A method for manufacturing the semiconductor package structure described herein is also disclosed. 1. A semiconductor package structure , comprising:a first carrier having a first surface, the first surface comprising a first region and a second region;a second carrier having a second surface opposing the first surface, the second surface comprising a third region corresponding to the first region and a fourth region corresponding to the second region;a plurality of first type conductive pillars between the first region of the first surface and the third region of the second surface; anda plurality of second type conductive pillars between the second region of the first surface and the fourth region of the second surface;wherein a contact resistance of each of the first type conductive pillars is lower than a contact resistance of each of the second type conductive pillars.2. The semiconductor package structure of claim 1 , wherein each of the plurality of first type conductive pillars comprises a copper-copper interface.3. The semiconductor package structure of claim 2 , wherein each of the plurality of second type conductive pillars comprises a copper-solder interface.4. The semiconductor package structure of claim 1 , wherein a pitch of the first type conductive pillars in the first region is smaller than a pitch of the second type conductive pillars in the second region.5. The semiconductor package structure of claim 4 , wherein the pitch of the first type conductive pillars in the first region is ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device according to an embodiment of the present invention comprises pads electrically connected to wires provided on an insulating substrate. A wiring substrate comprises a first insulant provided between the pads. A first semiconductor chip comprises metal bumps respectively connected to the pads on the wiring substrate on a first face facing the wiring substrate. A first adhesion layer is provided between the first insulant and the first semiconductor chip and adheres the wiring substrate and the first semiconductor chip to each other. An insulating resin is provided to cover peripheries of the first adhesion layer and the metal bumps between the wiring substrate and the first semiconductor chip, and a structure on the wiring substrate. 1. A semiconductor device comprising:a wiring substrate comprising pads electrically connected to wires provided on an insulating substrate, and a first insulant provided between the pads;a first semiconductor chip comprising metal bumps respectively connected to the pads on the wiring substrate on a first face facing the wiring substrate;a first adhesion layer provided between the first insulant and the first semiconductor chip and adhering the wiring substrate and the first semiconductor chip to each other; andan insulating resin covering peripheries of the first adhesion layer and the metal bumps between the wiring substrate and the first semiconductor chip, and a structure on the wiring substrate.2. The device of claim 1 , wherein the first adhesion layer has a thermal expansion coefficient larger than those of the wiring substrate and the first semiconductor chip.3. The device of claim 1 , wherein the first adhesion layer has an elastic modulus lower than those of the first insulant and the metal bumps.4. The device of claim 2 , wherein the first adhesion layer has an elastic modulus lower than those of the first insulant and the metal bumps.5. The device of claim 1 , wherein the first adhesion layer is placed ...

Stack-type semiconductor package

According to example embodiments, a stack-type semiconductor package includes a lower semiconductor package, an upper semiconductor package, connection pads, and a metal layer pattern. The lower semiconductor package includes a lower semiconductor chip on a top surface of a lower package substrate, lower lands on the lower package substrate, and an encapsulant on the top surface of the lower package substrate. The encapsulant defines via holes that expose the lower lands. The upper semiconductor package is on the encapsulant. Upper solder balls are connected to a bottom surface of the upper semiconductor package. The connection pads are on the via holes and the encapsulant. The connection pads electrically connect the lower semiconductor package to the upper semiconductor package. The metal layer pattern is between the lower package substrate and the upper semiconductor package. The metal layer pattern surrounds the connection pads and is isolated from the connection pads.

Die Features for Self-Alignment During Die Bonding

A semiconductor device assembly that includes a substrate having a first side and a second side, the first side having at least one dummy pad and at least one electrical pad. The semiconductor device assembly includes a first semiconductor device having a first side and a second side and at least one electrical pillar extending from the second side. The electrical pillar is connected to the electrical pad via solder to form an electrical interconnect. The semiconductor device assembly includes at least one dummy pillar extending from the second side of the first semiconductor device and a liquid positioned between an end of the dummy pillar and the dummy pad. The surface tension of the liquid pulls the dummy pillar towards the dummy pad. The surface tension may reduce or minimize a warpage of the semiconductor device assembly and/or align the dummy pillar and the dummy pad. 1. A semiconductor device assembly comprising:a substrate having a first side and a second side, the first side having at least one dummy pad and at least one electrical pad;a first semiconductor device having a first side and a second side;at least one electrical pillar extending from the second side of the first semiconductor device, the at least one electrical pillar connected to the at least one electrical pad via solder to form an electrical interconnect between the first semiconductor device and the substrate;at least one dummy pillar extending from the second side of the first semiconductor device;a first liquid positioned between an end of the at least one dummy pillar and the at least one dummy pad, wherein a surface tension of the first liquid pulls the at least one dummy pillar towards the at least one dummy pad.2. The semiconductor device assembly of claim 1 , wherein the surface tension of the first liquid reduces a warpage of the first semiconductor device.3. The semiconductor device assembly of claim 1 , wherein the surface tension of the first liquid aligns the at least one dummy ...

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

A semiconductor structure includes a semiconductor substrate; a first pad and a second pad on a first top surface of the semiconductor substrate; a circuit board including a second top surface, a recess indented from the second top surface into the circuit board, a polymeric pad disposed on the second top surface and corresponding to the first pad, and an active pad disposed within the recess and corresponding to the second pad; a first bump disposed between and contacting the polymeric pad and the first pad; and a second bump disposed between and contacting the active pad and the second pad, wherein a height of the first bump is substantially shorter than a height of the second bump. 2. The semiconductor structure of claim 1 , wherein the height of the second bump is substantially equal to a total of the height of the first bump and a thickness of the polymeric pad.3. The semiconductor structure of claim 1 , wherein a depth of the recess is substantially equal to a thickness of the active pad.4. The semiconductor structure of claim 1 , wherein a first angle between the first bump and the polymeric pad is substantially greater than a second angle between the second bump and the active pad.5. The semiconductor structure of claim 1 , wherein the second angle is about 10% to 30% smaller than the first angle.6. The semiconductor structure of claim 1 , wherein the second top surface of the circuit board is substantially coplanar with a third top surface of the active pad.7. The semiconductor structure of claim 1 , wherein an aspect ratio of the first bump is substantially less than an aspect ratio of the second bump.8. The semiconductor structure of claim 1 , wherein the first bump is electrically isolated from the circuit board by the polymeric pad.9. The semiconductor structure of claim 1 , wherein a width of the active pad is substantially equal to a width of the polymeric pad.10. The semiconductor structure of claim 1 , wherein a thickness of the active pad is ...

SYSTEMS AND METHODS FOR ASSEMBLING PROCESSOR SYSTEMS

This disclosure generally relates to processor systems comprising printed circuit boards, I/O chips and processor chips with mated contacts. Contacts are formed on an upper surface of a printed circuit board having a through-hole and on a processor chip inside the through-hole. The processor chip may be a superconducting quantum processor chip comprising qubits, couplers, Digital to Analog converters, QFP shift registers and analog lines. Contacts are formed on an upper surface on an I/O chip and mated with the contacts on the printed circuit board and the processor chip. Contacts may be Indium bump bonds or superconducting solder bonds. The processor chip and the I/O chip may include a shield layer, a substrate layer and a thermally conductive layer. 1. A processor system comprising:a processor chip, the processor chip having a major face, a perimeter which bounds the major face of the processor chip and that has a set of dimensions, and a plurality of contacts, the contacts of the processor chip distributed along the perimeter of the processor chip;a printed circuit board, the printed circuit board having a through-hole and a plurality of contacts, the through-hole having a perimeter with a set of dimensions, the dimensions of the through-hole larger than corresponding dimensions of the processor chip to receive the processor chip at least partially by the through-hole, the contacts of the printed circuit board distributed about the perimeter of the through-hole; andan input/output (I/O) chip, the I/O chip having a major face, a perimeter which bounds the major face of the I/O chip and that has a set of dimensions that are larger than corresponding dimensions of the through-hole of the printed circuit board, a first plurality of contacts, and a second plurality of contacts, the first plurality of contacts of the I/O chip distributed along the perimeter of the I/O chip, the second plurality of contacts distributed along the perimeter of the I/O chip spaced inwardly ...

Semiconductor device and method for manufacturing the same

A semiconductor device includes a dielectric interposer, a first interconnection layer, an electronic component, a plurality of electrical conductors and a plurality of conductive structures. The dielectric interposer has a first surface and a second surface opposite to the first surface. The first interconnection layer is over the first surface of the dielectric interposer. The electronic component is over and electrically connected to the first interconnection layer. The electrical conductors are over the second surface of the dielectric interposer. The conductive structures are through the dielectric interposer, wherein the conductive structures are electrically connected to the first interconnection layer and the electrical conductors.

ELECTRONIC DEVICE AND SEMICONDUCTOR DEVICE

The electronic device includes a first semiconductor device having a logic circuit, a second semiconductor device having a memory circuit, and a wiring substrate to which the first and second semiconductor devices are mounted. The first semiconductor device has a plurality of terminals arranged on a main surface. The plurality of terminals includes a plurality of differential pair terminals electrically connected to the second semiconductor device and to which differential signals are transmitted. The plurality of differential pair terminals is arranged along a side of the main surface, that is extending in an X direction, and includes a first differential pair terminal constituted by a pair of terminals arranged along a Y direction orthogonal to the X direction, and a second differential pair terminal constituted by a pair of terminals arranged along the Y direction. The first and second differential pair terminals are arranged along the Y direction.

Semiconductor package

A semiconductor package is provided comprising a package substrate having an opening located in a central region thereof and a circuit pattern provided adjacent to the opening. A first semiconductor chip is located on the package substrate and includes first bonding pads. A pair of second semiconductor chips are spaced apart from each other across the opening and mounted between the package substrate and the first semiconductor chip. Each of the second semiconductor chips includes a second bonding pad. A connection element is further provided to electrically connect the second bonding pad to a corresponding one of the first bonding pads.

Method and apparatus for die-to-die pad contact

A semiconductor device includes at least a first semiconductor die and a second semiconductor die. The first semiconductor dies comprises a first and second side, and includes at least a first contact pad located on the first side of the first semiconductor die. The second semiconductor die comprises a first and second side, and includes at least a second contact pad located on the first side of the second semiconductor die, wherein the first semiconductor die is stacked on the second semiconductor die and wherein the first side of the first semiconductor die faces the first side of the second semiconductor die. At least one voltage-guided conductive filament is created between the first contact pad and the second contact pad.

Semiconductor device and method for manufacturing semiconductor device

According to an aspect of the present disclosure, a semiconductor device includes a base plate, a first semiconductor chip provided above the base plate, a bonding wire joined with the first semiconductor chip at a first joint part and having a curved part above the first joint part, a first sealing member provided from an upper surface of the base plate up to a height higher than the first joint part and lower than the curved part, the first sealing member covering the first joint part and a second sealing member provided on the first sealing member, covering the curved part, and having an elastic modulus lower than an elastic modulus of the first sealing member.

Semiconductor Structure and Manufacturing Method Thereof

A semiconductor structure includes a three dimensional stack including a first semiconductor die and a second semiconductor die. The second semiconductor die is connected with the first semiconductor die with a bump between the first semiconductor die and the second semiconductor die. The semiconductor structure includes a molding compound between the first semiconductor die and the second semiconductor die. A first portion of a metal structure over a surface of the three dimensional stack and contacting a backside of the second semiconductor die and a second portion of the metal structure over the surface of the three dimensional stack and configured for electrically connecting the three dimensional stack with an external electronic device. 1. A method of manufacturing a semiconductor structure , comprising:bonding a semiconductor die to a substrate, the substrate having circuitry thereon;forming a conductive plug with a first end connected to the substrate;exposing a passive surface of the semiconductor die and a second end of the conductive plug; andforming a metal structure on the passive surface of the semiconductor die and the second end of the conductive plug, the metal structure comprising an active portion and a dummy portion, the active portion electrically coupled with the circuitry through the conductive plug, the dummy portion not being electrically coupled with any circuitry, the active portion and the dummy portion being on a same level of the metal structure.2. The method of claim 1 , further comprising disposing a molding compound on the substrate to surround the semiconductor die and the conductive plug.3. The method of claim 2 , further comprising performing a grinding operation to remove a portion of the molding compound to expose the passive surface of the semiconductor die and the second end of the conductive plug.4. The method of claim 1 , further comprising disposing a dummy bump on a portion of the metal structure.5. The method of claim 1 , ...

SEMICONDUCTOR PACKAGE INCLUDING TEST BUMPS

Disclosed is a semiconductor package comprising a first semiconductor chip and at least one second semiconductor chip on the first semiconductor chip. The second semiconductor chip includes first and second test bumps that are adjacent to an edge of the second semiconductor chip and are on a bottom surface of the second semiconductor chip. The first and second test bumps are adjacent to each other. The second semiconductor chip also includes a plurality of data bumps that are adjacent to a center of the second semiconductor chip and are on the bottom surface of the second semiconductor chip. A first interval between the second test bump and one of the data bumps is greater than a second interval between the first test bump and the second test bump. The one of the data bumps is most adjacent to the second test bump. 1. A semiconductor package , comprising:a first semiconductor chip;at least one second semiconductor chip stacked on the first semiconductor chip;a mold layer covering the first semiconductor chip and the second semiconductor chip,wherein the first semiconductor chip has a width greater than a width of the second semiconductor chip, a plurality of outer bumps on a bottom surface of the second semiconductor chip and being adjacent to an edge of the second semiconductor chip;', 'a plurality of inner bumps on the bottom surface of the second semiconductor chip and being adjacent to a center of the second semiconductor chip', 'a plurality of first through electrodes penetrating the second semiconductor chip and connected with the outer bumps; and', 'a plurality of second through electrodes penetrating the second semiconductor chin and connected with the inner bumps,, 'wherein the second semiconductor chip includeswherein a first interval between one of the outer bumps and one of the plurality of inner bumps that in moot adjacent to each other being greater than a second interval between the outer bumps, andwherein the outer bumps have a width equal to or ...

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

A semiconductor structure includes a semiconductor substrate and a pad. The pad is on a top surface of the semiconductor substrate. The semiconductor structure further includes a circuit board and a bump. The circuit board has a contact area corresponding to the pad on the top surface of the semiconductor substrate, and the bump is between the pad on the top surface of the semiconductor substrate and the contact area, wherein the contact area is a non-metallic surface. 1. A semiconductor structure , comprising:a semiconductor substrate;a pad on a top surface of the semiconductor substrate;a circuit board including a contact area corresponding to the pad on the top surface of the semiconductor substrate; anda bump between the pad on the top surface of the semiconductor substrate and the contact area, wherein the contact area is a non-metallic surface.2. The semiconductor structure of claim 1 , wherein the bump is in contact with the pad on the top surface of the semiconductor substrate in wetted manner.3. The semiconductor structure of claim 1 , wherein the contact area is a portion of a top electrically insulative surface of the circuit board.4. The semiconductor structure of claim 1 , wherein the contact area is an electrically insulative pad on a top surface of the circuit board.5. The semiconductor structure of claim 4 , wherein the electrically insulative pad is in a recess of the electrically insulative top surface of the circuit board.6. The semiconductor structure of claim 4 , wherein the electrically insulative pad is polymeric material.7. The semiconductor structure of claim 1 , further comprising a second bump adjacent the bump claim 1 , wherein the second bump is taller than the bump.8. The semiconductor structure of claim 7 , wherein the second bump is bonded with a conductive pad on the circuit board in wetted manner.9. The semiconductor structure of claim 7 , wherein the second bump includes an aspect ratio greater than an aspect ratio of the bump.10. ...

SEMICONDUCTOR DIE ASSEMBLIES WITH HEAT SINK AND ASSOCIATED SYSTEMS AND METHODS

Methods for forming semiconductor die assemblies with heat transfer features are disclosed herein. In some embodiments, the methods comprise providing a wafer having a first side and a second side opposite the first side, attaching a semiconductor die stack to the first side of the wafer, and forming a plurality of heat transfer features at the second side of the wafer. The heat transfer features can be defined by a plurality of grooves that define an exposed continuous surface of the wafer at the second side compared to a planar surface of the wafer. 1. A method of manufacturing a semiconductor die assembly , comprising:providing a wafer having a first side and a second side opposite the first side;attaching a semiconductor die stack to the first side of the wafer; andforming a plurality of heat transfer features at the second side of the wafer, wherein the heat transfer features are defined by a plurality of grooves that define an exposed continuous surface of the wafer at the second side compared to a planar surface of the wafer.2. The method of claim 1 , further comprising at least partially encapsulating the semiconductor die stack with a mold material.3. The method of claim 2 , further comprising cutting through the semiconductor wafer and the mold material to singulate the semiconductor die stack.4. The method of wherein the plurality of heat transfer features extend along a first width of the semiconductor wafer claim 1 , and wherein the semiconductor die stack includes a second width less than the first width.5. The method of claim 1 , further comprising claim 1 , before forming the plurality of heat transfer features claim 1 , disposing a mold material over the semiconductor die stack and the first side of the wafer.6. The method of wherein forming the plurality of heat transfer features includes removing material from the wafer at the second side.7. The method of claim 1 , further comprising claim 1 , before forming the plurality of heat transfer features ...

Pre-Molded Leadframes in Semiconductor Devices

In one instance, a semiconductor package includes a metal leadframe having a first plurality of openings extending partially into the leadframe from the first side and a second plurality of openings extending partially into the leadframe from the second side together forming a plurality of leads. A pre-mold compound is positioned in the second plurality of openings that at least partially supports the plurality of leads. The seminconductor package has a plurality of bumps extending from the landing sites to a semiconductor die and a molding compounding at least partially covering the plurality of bumps and the metal leadframe. Other packages and methods are disclosed.

Shaped Interconnect Bumps in Semiconductor Devices

In one instance, a semiconductor package includes a lead frame and a semiconductor die mounted to the lead frame via a plurality of bumps that are shaped or tapered. Each of the plurality of bumps includes a first end connected to the semiconductor die and an opposing, second end connected to the lead frame. The first end has an end surface area A. The second end has an end surface area A. The end surface area A of the first end is less than the end surface area A of the second end. Other aspects are disclosed. 1. A semiconductor package comprising:a leadframe;a semiconductor die mounted to the leadframe via a plurality of bumps; andwherein each of the plurality of bumps comprises:{'b': '1', 'a first end connected to the semiconductor die, the first end having an end surface area A, and'}{'b': 2', '1', '2, 'an opposing, second end connected to the leadframe, the second end having a end surface area A, wherein the end surface area A of the first end is less than the end surface area A of the second end.'}221. The package of claim 1 , wherein the end surface area A of the second end is at least 10 percent greater than the end surface area A of the first end.321. The package of claim 1 , wherein the surface area A of the second end is at least double the surface area A of the first end.421. The package of claim 1 , wherein each of the plurality of bumps is shaped as truncated cones with a large end of the truncated cone defining A and a narrow end of the truncated cone defining A.5. The package of claim 1 , wherein for each of the plurality of bumps a cross-section taken orthogonally to a line going from the first end to the second end is oval or circular.6. The package of claim 1 , wherein the leadframe is metallic claim 1 , and wherein the plurality of bumps is comprised of copper.7. The package of claim 1 , further comprising a solder material associated with each of the plurality of bumps and wherein the solder material is disposed between the second end of the ...

SEAL RING STRUCTURES AND METHODS OF FORMING SAME

Some embodiments relate to a three-dimensional (3D) integrated circuit (IC). The 3D IC includes a first IC die comprising a first semiconductor substrate, and a first interconnect structure over the first semiconductor substrate. The 3D IC also includes a second IC die comprising a second semiconductor substrate, and a second interconnect structure that separates the second semiconductor substrate from the first interconnect structure. A seal ring structure separates the first interconnect structure from the second interconnect structure and perimetrically surrounds a gas reservoir between the first IC die and second IC die. The seal ring structure includes a sidewall gas-vent opening structure configured to allow gas to pass between the gas reservoir and an ambient environment surrounding the 3D IC. 1. A semiconductor packaging device comprising:a first IC die comprising a first semiconductor substrate, and a first interconnect structure over the first semiconductor substrate;a second IC die comprising a second semiconductor substrate, and a second interconnect structure that separates the second semiconductor substrate from the first interconnect structure; anda seal ring structure that separates the first interconnect structure from the second interconnect structure and which perimetrically surrounds a gas reservoir between the first IC die and second IC die, wherein the seal ring structure includes a sidewall gas-vent opening structure configured to allow gas to pass between the gas reservoir and an ambient environment surrounding the 3D IC.2. The semiconductor packaging device according to claim 1 , wherein the seal ring structure is conductive but is electrically isolated from both the first interconnect structure and the second interconnect structure.3. The semiconductor packaging device according to claim 1 , wherein the first interconnect structure comprises a first interlayer dielectric (ILD) layer claim 1 , first wiring layers claim 1 , and first via ...

BUMP LAYOUT FOR COPLANARITY IMPROVEMENT

A method includes receiving a first design for conductive bumps on a first surface of an interposer, the conductive bumps in the first design having a same cross-section area; grouping the conductive bumps in the first design into a first group of conductive bumps in a first region of the first surface and a second group of conductive bumps in a second region of the first surface, where a bump pattern density of the second region is lower than that of the first region; forming a second design by modifying the first design, where modifying the first design includes modifying a cross-section area of the second group of conductive bumps in the second region; and forming the conductive bumps on the first surface of the interposer in accordance with the second design, where after being formed, the first group of conductive bumps and the second group of conductive bumps have different cross-section areas. 1. A method comprising:receiving a first design for conductive bumps on a first surface of an interposer, the conductive bumps in the first design having a same cross-section area;grouping the conductive bumps in the first design into a first group of conductive bumps in a first region of the first surface and a second group of conductive bumps in a second region of the first surface, wherein a bump pattern density of the second region is lower than that of the first region;forming a second design by modifying the first design, wherein modifying the first design comprises modifying a cross-section area of the second group of conductive bumps in the second region; andforming the conductive bumps on the first surface of the interposer in accordance with the second design, wherein after being formed, the first group of conductive bumps and the second group of conductive bumps have different cross-section areas.2. The method of claim 1 , wherein a size of the first group of conductive bumps remain unchanged in the first design and the second design.3. The method of claim 1 , ...

BUMP STRUCTURE AND FABRICATION METHOD THEREOF

Disclosed are bump structures and bump structure fabrication methods. A bump structure including a pad and a bump on a top surface of the pad may be provided. The bump may include an upper bump portion and the lower bump portion, and the lower bump portion may include a pedestal portion in contact with the top surface of the pad and a pillar portion upwardly extending from the pedestal portion. A cross-sectional area of at least a portion of the pedestal portion along a first direction may be greater than a cross-sectional area of the pillar portion along the first direction. 1. A bump structure , comprising:a pad; anda bump on a top surface of the pad, the bump including an upper bump portion and a lower bump portion, the lower bump portion including a pedestal portion in contact with the top surface of the pad and a pillar portion upwardly extending from the pedestal portion, a cross-sectional area of at least a portion of the pedestal portion along a first direction being greater than a cross-sectional area of the pillar portion along the first direction.2. The bump structure of claim 1 , wherein the pedestal portion and the pillar portion comprise a same material.3. The bump structure of claim 1 , wherein the cross-sectional area of the at least a portion of the pedestal portion is less than a cross-sectional area of the pad along the first direction.4. The bump structure of claim 1 , wherein the upper bump portion comprises solder and the lower bump portion comprises copper.5. The bump structure of claim 1 , wherein a cross-sectional area of the pedestal portion in the first direction is constant along a second direction perpendicular to the first direction.6. The bump structure of claim 1 , wherein a cross-sectional area of the pedestal portion in the first direction decreases as approaching the pillar portion from the pad.7. The bump structure of claim 1 , wherein a cross-sectional area of the pedestal portion in the first direction increases as approaching ...

THERMOCOMPRESSION FOR SEMICONDUCTOR CHIP ASSEMBLY

An assembly of a semiconductor chip having pads to a substrate having pads aligned to receive the semiconductor chip is provided, whereby at least one of the semiconductor chip pads and substrate pads include solder bumps. The solder bumps are deformed against the substrate pads and the semiconductor chip pads, whereby an underfill material is applied to fill the gap between the semiconductor chip and substrate such that the underfill material envelopes both the deformed solder bumps and the substrate pads. The underfill material does not penetrate between the deformed solder bumps, the semiconductor chip pads, and the substrate pads based on a compression force causing the solder bumps to be deformed against the substrate pads and the semiconductor chip pads. At least one of the solder bumps have not been melted or reflowed to make a metallurgical bond between the semiconductor chip pads and the substrate pads. 124.-. (canceled)25. An assembly of a semiconductor chip having pads to a substrate having pads aligned to receive the semiconductor chip , at least one of the semiconductor chip pads and substrate pads having solder bumps , the solder bumps being deformed against the substrate pads and the semiconductor chip pads , an underfill material applied to fill the gap between the semiconductor chip and substrate such that the underfill material envelopes both the deformed solder bumps and the substrate pads , the underfill material not penetrating between the deformed solder bumps , the semiconductor chip pads , and the substrate pads based on a compression force causing the solder bumps to be deformed against the substrate pads and the semiconductor chip pads , wherein at least one of the solder bumps have not been melted or reflowed to make a metallurgical bond between the semiconductor chip pads and the substrate pads.26. The assembly of claim 25 , wherein the semiconductor chip further comprises copper pillars extending from the semiconductor chip pads and the ...

SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor package includes a first die having a first surface, a first conductive bump over the first surface and having first height and a first width, a second conductive bump over the first surface and having a second height and a second width. The first width is greater than the second width and the first height is substantially identical to the second height. A method for manufacturing the semiconductor package is also provided. 1. A semiconductor package , comprising:a first die having a first surface;a first conductive bump over the first surface and having first height and a first width; anda second conductive bump over the first surface and having a second height and a second width,wherein the first width is greater than the second width and the first height is substantially identical to the second height.2. The semiconductor package of claim 1 , further comprising a second die having a second surface facing the first surface and bonded to the first die through the first conductive bump claim 1 , the first conductive bump and the second conductive bump projecting on the second die.3. The semiconductor package of claim 2 , further comprising a first solder bump between the first conductive bump and the second die.4. The semiconductor package of claim 3 , further comprising a second solder bump between the second conductive bump and the second die claim 3 , wherein the second solder bump is spaced from the second surface by a predetermined distance.5. The semiconductor package of claim 4 , further comprising a conductive terminal on the first surface of the first die claim 4 , the conductive terminal is configured to bond to a substrate.6. The semiconductor package of claim 1 , wherein the first width is 1.3 to 1.5 times greater than the second width.7. The semiconductor package of claim 1 , further comprising a first conductive pad on the first surface and in contact with the first conductive bump claim 1 , an edge of the first conductive pad is ...

SEMICONDUCTOR DEVICES WITH UNDERFILL CONTROL FEATURES, AND ASSOCIATED SYSTEMS AND METHODS

Semiconductor devices with underfill control features, and associated systems and methods. A representative system includes a substrate having a substrate surface and a cavity in the substrate surface, and a semiconductor device having a device surface facing toward the substrate surface. The semiconductor device further includes at least one circuit element electrically coupled to a conductive structure. The conductive structure is electrically connected to the substrate, and the semiconductor device further has a non-conductive material positioned adjacent the conductive structure and aligned with the cavity of the substrate. An underfill material is positioned between the substrate and the semiconductor device. In other embodiments, in addition to or in lieu of the con-conductive material, a first conductive structure is connected within the cavity, and a second conductive structure connected outside the cavity. The first conductive structure extends away from the device surface a greater distance than does the second conductive structure. 1. A semiconductor device assembly , comprisinga substrate having a substrate surface and a cavity in the substrate surface;a semiconductor device having a device surface facing toward the substrate surface, the semiconductor device further having at least one circuit element electrically coupled to a conductive structure, wherein the conductive structure is electrically connected to the substrate, the semiconductor device further having a non-conductive material positioned adjacent the conductive structure and aligned with the cavity of the substrate; andan underfill material positioned between the substrate and the semiconductor device.2. The system of wherein the non-conductive material does not extend laterally outwardly beyond the cavity.3. The system of wherein a thickness of the non-conductive material and a depth of the cavity are at least approximately the same.4. The system of wherein the non-conductive material ...

Mechanisms for Forming Hybrid Bonding Structures with Elongated Bumps

Embodiments of mechanisms for forming a package structure are provided. The package structure includes a semiconductor die and a substrate. The package structure includes a pillar bump and an elongated solder bump bonded to the semiconductor die and the substrate. A height of the elongated solder bump is substantially equal to a height of the pillar bump. The elongated solder bump has a first width, at a first horizontal plane passing through an upper end of a sidewall surface of the elongated solder bump, and a second width, at a second horizontal plane passing through a midpoint of the sidewall surface. A ratio of the second width to the first width is in a range from about 0.5 to about 1.1. 1. A package structure , comprising:a first substrate;a second substrate;a pillar bump bonded to the first substrate and the second substrate, the pillar bump being electrically coupled to the first substrate and the second substrate, wherein the pillar bump comprises a pillar and a bonding layer, the pillar is a non-solder material having a higher reflow temperature than the bonding layer, the bonding layer is between the pillar and the second substrate, and the pillar includes a linear sidewall profile; andan elongated solder bump bonded to the first substrate and the second substrate, wherein a height of the elongated solder bump is substantially equal to a height of the pillar bump, wherein the elongated solder bump and the bonding layer are formed of a solder.2. The package structure of claim 1 , wherein the first substrate comprises a semiconductor die.3. The package structure of claim 2 , wherein the bonding layer is interposed between the pillar and the second substrate.4. The package structure of claim 1 , wherein the elongated solder bump has convex sidewalls.5. The package structure of claim 1 , wherein the elongated solder bump has a solder portion having a first width at a first horizontal plane passing through an upper end of a sidewall surface of the elongated ...

Semiconductor Devices, Methods of Manufacture Thereof, and Semiconductor Device Packages

Semiconductor devices, methods of manufacture thereof, and semiconductor device packages are disclosed. In one embodiment, a semiconductor device includes an insulating material layer having openings on a surface of a substrate. One or more insertion bumps are disposed over the insulating material layer. The semiconductor device includes signal bumps having portions that are not disposed over the insulating material layer.

Method for bonding semiconductor components

A method of bonding semiconductor components is described. In one aspect a first component, for example a semiconductor die, is bonded to a second component, for example a semiconductor wafer or another die, by direct metal-metal bonds between metal bumps on one component and corresponding bumps or contact pads on the other component. In addition, a number of solder bumps are provided on one of the components, and corresponding contact areas on the other component, and fast solidified solder connections are established between the solder bumps and the corresponding contact areas, without realizing the metal-metal bonds. The latter metal-metal bonds are established in a heating step performed after the soldering step. This enables a fast bonding process applied to multiple dies bonded on different areas of the wafer and/or stacked one on top of the other, followed by a single heating step for realizing metal-metal bonds between the respective dies and the wafer or between multiple stacked dies. The method allows to improve the throughput of the bonding process, as the heating step takes place only once for a plurality of dies and/or wafers.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor device includes a dielectric interposer, a first interconnection layer, an electronic component, a plurality of electrical conductors and a plurality of conductive structures. The dielectric interposer has a first surface and a second surface opposite to the first surface. The first interconnection layer is over the first surface of the dielectric interposer. The electronic component is over and electrically connected to the first interconnection layer. The electrical conductors are over the second surface of the dielectric interposer. The conductive structures are through the dielectric interposer, wherein the conductive structures are electrically connected to the first interconnection layer and the electrical conductors. 1. A semiconductor device , comprising:a dielectric interposer having a first surface and a second surface opposite to the first surface;a first redistribution layer (RDL) over the first surface of the dielectric interposer;an electronic component over and electrically connected to the first RDL;a plurality of electrical connectors between and electrically connected to the RDL and the electronic component; anda plurality of electrical conductors over the second surface of the dielectric interposer.2. The semiconductor device of claim 1 , wherein a thickness of the dielectric interposer is in a range from about 5 micrometers to about 30 micrometers.3. The semiconductor device of claim 1 , wherein the dielectric interposer comprises an inorganic dielectric material.4. The semiconductor device of claim 3 , wherein the inorganic dielectric material comprises silicon oxide claim 3 , silicon nitride claim 3 , silicon oxynitride or a combination thereof.5. The semiconductor device of claim 1 , wherein the dielectric interposer comprises an organic dielectric material.6. The semiconductor device of claim 5 , wherein the organic dielectric material comprises polyimide claim 5 , polymethyl methacrylate (PMMA) claim 5 , polybenzoxazole (PBO) ...

SEMICONDUCTOR DEVICE ASSEMBLY WITH DIE SUPPORT STRUCTURES

A semiconductor device assembly is provided. The assembly includes a first semiconductor die and a second semiconductor die disposed over the first semiconductor die. The assembly further includes a plurality of die support structures between the first and second semiconductor dies and a plurality of interconnects between the first and second semiconductor dies. Each of the plurality of die support structures includes a stand-off pillar and a stand-off pad having a first bond material with a first solder joint thickness between them. Each of the plurality of interconnects includes a conductive pillar and a conductive pad having a second bond material with a second solder joint thickness between them. The first solder joint thickness is less than the second solder joint thickness. 1. A semiconductor package comprising a plurality of dies arranged in a stack ,wherein adjacent ones of the plurality of dies are separated by a plurality of interconnects and a plurality of die support structures,wherein each of the plurality of die support structures includes a stand-off pillar and a stand-off pad with a first distance between the stand-off pillar and the stand-off pad,wherein each of the plurality of interconnects includes a conductive pillar, a conductive pad, and a bond material with a solder joint thickness between the conductive pillar and the conductive pad, andwherein the first distance is less than the solder joint thickness.2. The semiconductor package of claim 1 , wherein the plurality of die support structures includes die support structures disposed about a periphery of the semiconductor package.3. The semiconductor package of claim 1 , wherein the plurality of die support structures includes die support structures disposed in a medial region of the semiconductor device assembly.4. The semiconductor package of claim 1 , wherein the plurality of dies includes more than two dies.5. The semiconductor package of claim 1 , wherein the plurality of dies includes at ...

Semiconductor structure and method of manufacturing the same

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes: a semiconductor chip; a substrate facing an active surface of the semiconductor chip; and a conductive bump extending from the active surface of the semiconductor chip toward the substrate, wherein the conductive bump comprises: a plurality of bump segments comprising a first group of bump segments and a second group of bump segments, wherein each bump segment comprises the same segment height in a direction orthogonal to the active surface of the semiconductor chip, and each bump segment comprises a volume defined by the multiplication of the segment height with the average cross-sectional area of the bump segment; wherein the ratio of the total volume of the first group of bump segments to the total volume of the second group of bump segments is between about 0.03 and about 0.8.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor chip includes a chip body and a plurality of solder-including electrodes provided on an element-formation surface of the chip body. A packaging substrate includes a substrate body, and one or more conductive layers and a solder resist layer that are provided on a front surface of the substrate body. The solder resist layer is provided as a continuous layer on the front surface of the substrate body and the one or more conductive layers, and has one or more apertures on each of the one or more conductive layers. The plurality of solder-including electrodes include two or more first electrodes having a same function other than a function of power supply. The one or more conductive layers include a continuous first conductive layer. The two or more first electrodes are connected to the continuous first conductive layer. The one or more apertures are confronted with the respective two or more first electrodes. 1. A semiconductor device , comprising:a semiconductor chip; anda packaging substrate on which the semiconductor chip is mounted,wherein the semiconductor chip includes a chip body and a plurality of solder-including electrodes provided on an element-formation surface of the chip body,the packaging substrate includes a substrate body, one or more conductive layers, and a solder resist layer, the one or more conductive layers and the solder resist layer being provided on a front surface of the substrate body,the solder resist layer is provided as a continuous layer on the front surface of the substrate body and the one or more conductive layers, and has one or more apertures on each of the one or more conductive layers,the plurality of solder-including electrodes include two or more first electrodes having a same function other than a function of power supply,the one or more conductive layers include a continuous first conductive layer,the two or more first electrodes are connected to the continuous first conductive layer, andthe one or more ...

Proximity coupling of interconnect packaging systems and methods

Proximity coupling interconnect packaging systems and methods. A semiconductor package assembly comprises a substrate, a first semiconductor die disposed adjacent the substrate, and a second semiconductor die stacked over the first semiconductor die. There is at least one proximity coupling interconnect between the first semiconductor die and the second semiconductor die, the proximity coupling interconnect comprising a first conductive pad on the first coupling face on the first semiconductor die and a second conductive pad on a second coupling face of the second semiconductor die, the second conductive pad spaced apart from the first conductive pad by a gap distance and aligned with the first conductive pad. An electrical connector is positioned laterally apart from the proximity coupling interconnect and extends between the second semiconductor die and the substrate, the position of the electrical connector defining the alignment of the first conductive pad and the second conductive pad.

Packaging Structures of Integrated Circuits

A chip includes a first group of dummy bumps disposed at a top surface of the chip in a first corner of the chip, a second group of dummy bumps disposed at the top surface of the chip in a second corner of the chip, and active bump connectors disposed at the top surface of the chip. The chip also includes an outer seal ring disposed around a periphery of the chip, a first seal ring arrangement disposed around the first group of dummy bumps, and a second seal ring arrangement disposed around the second group of dummy bumps. The first seal ring arrangement and second seal ring arrangement are disposed in dielectric layers underlying the first and second groups of dummy bumps. 1. A device comprising a chip , the chip comprising:a first group of dummy bumps comprising a plurality of dummy bump connectors, the first group of dummy bumps disposed at a top surface of the chip in a first corner of the chip, the first corner being disposed immediately adjacent two intersecting edges of the chip;a second group of dummy bumps comprising one or more dummy bump connectors, the second group of dummy bumps disposed at the top surface of the chip in a second corner of the chip, the second corner being disposed immediately adjacent two intersecting edges of the chip,wherein the first and second groups of dummy bumps are disposed in different corners of the chip;a plurality of active bump connectors disposed at the top surface of the chip, the plurality of active bump connectors and the first and second groups of dummy bumps arranged in a pattern in a top down view of the chip;an outer seal ring disposed around a periphery of the chip;a first seal ring arrangement disposed around the first group of dummy bumps;a second seal ring arrangement disposed around the second group of dummy bumps; anddielectric layers underlying the first and second groups of dummy bumps and the plurality of active bump connectors,wherein the first seal ring arrangement is disposed in the dielectric layers, ...

Underfill material flow control for reduced die-to-die spacing in semiconductor packages

Underfill material flow control for reduced die-to-die spacing in semiconductor packages and the resulting semiconductor packages are described. In an example, a semiconductor apparatus includes first and second semiconductor dies, each having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a common semiconductor package substrate by a plurality of conductive contacts, the first and second semiconductor dies separated by a spacing. A barrier structure is disposed between the first semiconductor die and the common semiconductor package substrate and at least partially underneath the first semiconductor die. An underfill material layer is in contact with the second semiconductor die and with the barrier structure, but not in contact with the first semiconductor die.

DRIVING CHIP, DISPLAY SUBSTRATE, DISPLAY DEVICE AND METHOD FOR MANUFACTURING DISPLAY DEVICE

The present disclosure provides a driving chip, a display substrate, a display device and a method for manufacturing a display device. The driving chip according to the present disclosure includes a substrate; and a plurality of connecting bumps and a plurality of supporting bumps disposed on the substrate. The plurality of connecting bumps include at least one set of connecting bumps arranged along a first direction, and the plurality of supporting bumps include the supporting bump that is located between the adjacent connecting bumps arranged along the first direction. 1. A driving chip , comprising:a substrate; anda plurality of connecting bumps and a plurality of supporting bumps disposed on the substrate;wherein the plurality of connecting bumps comprise at least one set of connecting bumps arranged along a first direction, and the plurality of supporting bumps comprise supporting bumps that are located between adjacent connecting bumps arranged along the first direction.2. The driving chip according to claim 1 , wherein the plurality of connecting bumps further comprise at least one set of connecting bumps arranged along a second direction that is distinct from the first direction claim 1 , and the plurality of supporting bumps comprise supporting bumps that are located between adjacent connecting bumps arranged along the second direction.3. The driving chip according to claim 1 , wherein the plurality of connecting bumps further comprise a set of connecting bumps arranged along a second direction that is distinct from the first direction claim 1 , and the plurality of supporting bumps comprise the supporting bumps that are arranged along the second direction and correspondingly disposed on at least one side of the set of connecting bumps arranged along the second direction.4. The driving chip according to claim 1 , wherein the plurality of supporting bumps further comprise supporting bumps that are located on at least one end of the connecting bump arranged ...

SEMICONDUCTOR DEVICE WITH A PROTECTION MECHANISM AND ASSOCIATED SYSTEMS, DEVICES, AND METHODS

A semiconductor device includes a substrate; a die attached over the substrate; and a metal enclosure continuously encircling a space and extending vertically between the substrate and the die. 1. A semiconductor device , comprising:a substrate;a die attached over the substrate, wherein the die includes a center portion surrounded by peripheral portions;interconnects extending vertically away from the die and electrically coupling the die to the substrate; anda metal enclosure located under or over the center portion, continuously encircling the interconnects, and extending vertically between the substrate and the die.2. The semiconductor device of claim 1 , wherein the metal enclosure is located halfway between the center portion and a peripheral edge of the substrate or closer to the center portion than the peripheral edge.3. The semiconductor device of claim 1 , wherein:the metal enclosure is an inner metal enclosure; andfurther comprising:an outer metal enclosure surrounding the inner enclosure.4. The semiconductor device of claim 3 , wherein the inner metal enclosure and the outer metal enclosure are concentrically arranged.5. The semiconductor device of claim 3 , wherein the inner metal enclosure and the outer metal enclosure have different shapes along a horizontal plane.6. The semiconductor device of claim 1 , wherein the metal enclosure has a circular or oval shape along a horizontal plane.7. The semiconductor device of claim 1 , wherein the metal enclosure has an asymmetrical shape along a horizontal plane.8. A semiconductor device claim 1 , comprising:a substrate;a die attached over the substrate, wherein the die includes a center portion surrounded by peripheral portions;interconnects extending vertically away from the die and electrically coupling the die to the substrate; anda metal enclosure continuously encircling the interconnects and extending vertically between the substrate and the die, wherein the metal enclosure includes at least one section ...

CHIP ON FILM PACKAGE

A chip on film package is disclosed, including a flexible film and a chip. The flexible film includes a film base, a patterned metal layer includes a plurality of pads and disposed on an upper surface of the film base, and a dummy metal layer covering a lower surface of the film base and capable of dissipating heat of the chip. The dummy metal layer comprises at least one opening exposing the second surface, and at least one of the plurality of pads is located within the at least one opening in a bottom view of the chip on film package. The chip is mounted on the plurality of pads of the patterned metal layer. 1. A chip on film package , comprising:a flexible film comprising a film base, a patterned metal layer comprising a plurality of pads and disposed on a first surface of the film base, and a dummy metal layer covering a second surface of the film base, wherein the dummy metal layer comprises at least one opening exposing the second surface, and at least one of the plurality of pads is located within the at least one opening in a bottom view of the chip on film package; anda chip mounted on the plurality of pads of the patterned metal layer.2. The chip on film package as claimed in claim 1 , wherein the dummy metal layer has a floating voltage.3. The chip on film package as claimed in claim 1 , wherein the dummy metal layer is connected to a reference voltage.4. The chip on film package as claimed in claim 3 , wherein the reference voltage is a ground voltage.5. The chip on film package as claimed in claim 1 , wherein the at least one of the plurality of pads located within the at least one opening is a plurality of dummy pads.6. The chip on film package as claimed in claim 5 , wherein the patterned metal layer comprises a plurality of dummy traces connected to the plurality of dummy pads claim 5 , and a part of the dummy traces are in the at least one opening in the bottom view of the chip on film package.7. The chip on film package as claimed in claim 1 , ...

Solderless interconnect for semiconductor device assembly

Semiconductor device assemblies with solderless interconnects, and associated systems and methods are disclosed. In one embodiment, a semiconductor device assembly includes a first conductive pillar extending from a semiconductor die and a second conductive pillar extending from a substrate. The first conductive pillar may be connected to the second conductive pillar via an intermediary conductive structure formed between the first and second conductive pillars using an electroless plating solution injected therebetween. The first and second conductive pillars and the intermediary conductive structure may include copper as a common primary component, exclusive of an intermetallic compound (IMC) of a soldering process. A first sidewall surface of the first conductive pillar may be misaligned with respect to a corresponding second sidewall surface of the second conductive pillar. Such interconnects formed without IMC may improve electrical and metallurgical characteristics of the interconnects for the semiconductor device assemblies.

STRUCTURES AND METHODS TO ENABLE A FULL INTERMETALLIC INTERCONNECT

A method forming an interconnect structure includes depositing a first solder bump on a chip; depositing a second solder bump on a laminate, the second solder bump including a nickel copper colloid surrounded by a nickel or copper shell and suspended in a tin-based solder; aligning the chip with the laminate; performing a first reflow process to join the chip to the laminate; depositing an underfill material around the first solder bump and the second solder bump; and performing a second reflow process at a temperature that is lower than the first reflow process to convert the first solder bump and the second solder bump to an all intermetallic interconnect; wherein depositing the underfill material is performed before or after performing the second reflow process. 1. A method forming an interconnect structure , the method comprising:depositing a first solder bump on a chip;depositing a second solder bump on a laminate, the second solder bump comprising a nickel copper colloid;joining the chip to the laminate;depositing an underfill material around the first solder bump and the second solder bump; andperforming a reflow process at a temperature that is lower than a temperature used to join the chip to the laminate to convert the first solder bump and the second solder bump to an all intermetallic interconnect.2. The method of claim 1 , wherein the nickel copper colloid is surrounded by a nickel shell.3. The method of claim 2 , wherein the nickel copper colloid surrounded by the nickel shell is suspended in a tin-based solder.4. The method of claim 3 , wherein the tin-based solder comprises a tin silver alloy.5. The method of claim 2 , wherein the nickel shell has a thickness of about 0.1 to 0.5 microns.6. The method of claim 1 , wherein the nickel copper colloid is surrounded by a copper shell.7. The method of claim 6 , wherein the nickel copper colloid surrounded by the copper shell is suspended in a tin-based solder.8. The method of claim 6 , wherein the copper ...

SEMICONDUCTOR PACKAGE

A semiconductor device including an integrated circuit, a dielectric layer, a plurality of connecting terminals and at least one dummy conductor is provided. The integrated circuit has a plurality of connecting pads, and the dielectric layer is disposed thereon and partially exposes the plurality of the connecting pads by a plurality of openings defined therein. The plurality of the connecting terminals is disposed on the plurality of the connecting pads exposed by the plurality of the openings. The at least one dummy conductor is disposed on the dielectric layer and electrically isolated from the integrated circuit. A substantial topology variation is between the plurality of the connecting terminals and the at least one dummy conductor. A semiconductor package having the semiconductor device is also provided. 1. A semiconductor package , comprising:a circuit substrate, comprising a plurality of first conductive pads, a plurality of second conductive pads each separated from the plurality of first conductive pads, and a solder mask layer with a plurality of first recesses and a plurality of second recesses defined therein; and an integrated circuit;', 'a plurality of connecting terminals, disposed over and electrically coupled to the integrated circuit; and', 'at least one dummy conductor, disposed over and electrically isolated from the integrated circuit, wherein the semiconductor device is bonded to the circuit substrate through connecting the plurality of connecting terminals to the plurality of first conductive pads and connecting the at least one dummy conductor to one of the plurality of second conductive pads, and there is a level difference between horizontal interfaces of the plurality of connecting terminals and the plurality of first conductive pads and a horizontal interface of the at least one dummy conductor and the one of the plurality of second conductive pads,', 'wherein the at least one dummy conductor is electrically floated or grounded., 'a ...

STACKED SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME

A stacked semiconductor device includes a plurality of semiconductor dies and a plurality of thermal-mechanical bumps. The semiconductor dies are stacked in a vertical direction. The thermal-mechanical bumps are disposed in bump layers between the semiconductor dies. Fewer thermal-mechanical bumps are disposed at a location near a heat source included in the semiconductor dies than at other locations, or a structure of the thermal-mechanical bumps at the location near the heat source is different from a structure of the thermal-mechanical bumps at other locations. 1. A stacked semiconductor device , comprising:a plurality of semiconductor dies stacked in a vertical direction; anda plurality of thermal-mechanical bumps disposed in bump layers between the semiconductor dies,wherein fewer thermal-mechanical bumps are disposed at a location near a heat source included in the semiconductor dies than at other locations, or a structure of the thermal-mechanical bumps at the location near the heat source is different from a structure of the thermal-mechanical bumps at other locations.2. The stacked semiconductor device of claim 1 , wherein the disposition or the structure of the thermal-mechanical bumps in a first bump layer is different from the disposition or the structure of the thermal-mechanical bumps in a second bump layer.3. The stacked semiconductor device of claim 1 , wherein the semiconductor dies include a first semiconductor die including the heat source and a second semiconductor die including a heat vulnerable region claim 1 , andwherein a number of the thermal-mechanical bumps in the bump layer between the first semiconductor die and the second semiconductor die is smaller than a number of the thermal-mechanical bumps in the other bump layers.4. The stacked semiconductor device of claim 1 , wherein the semiconductor dies include a first semiconductor die including the heat source and a second semiconductor die including a heat vulnerable region claim 1 , ...

ELECTRONIC DEVICE APPARATUS WITH MULTIPLE THERMALLY CONDUCTIVE PATHS FOR HEAT DISSIPATION

Examples described herein provide for an electronic device apparatus with multiple thermally conductive paths for heat dissipation. In an example, an electronic device apparatus includes a package comprising a die attached to a package substrate. The electronic device apparatus further includes a ring stiffener disposed around the die and on the package substrate, a heat sink disposed on the package, and a wedge disposed between the heat sink and the ring stiffener. 1. An electronic device apparatus comprising:a package comprising a die attached to a package substrate;a ring stiffener disposed around the die and on the package substrate;a heat sink disposed on the package; anda wedge disposed between the heat sink and the ring stiffener, wherein the wedge is expandable in a direction extending from the ring stiffener to the heat sink, the wedge contacting the ring stiffener and the heat sink.2. The electronic device apparatus of claim 1 , wherein a thermally conductive path of serially connected metal components is formed through the package substrate claim 1 , the ring stiffener claim 1 , and the wedge to the heat sink.3. The electronic device apparatus of claim 1 , wherein the die includes an in-chip heat sink claim 1 , the in-chip heat sink comprising a metal wall and a through substrate via (TSV) connected to the metal wall claim 1 , the metal wall comprising vias and lines claim 1 , the TSV being through a semiconductor substrate portion of the die.4. The electronic device apparatus of claim 1 , wherein:the die includes an in-chip heat sink;the die is attached to the package substrate by an external connector;the package substrate includes a metallization; anda thermally conductive path is through the in-chip heat sink, the external connector, the metallization of the package substrate, the ring stiffener, and the wedge to the heat sink.5. The electronic device apparatus of claim 1 , wherein the ring stiffener has a lateral portion that extends laterally beyond ...

Device conducive to reduction of parasitic inductance and method for circuit design and assembly

Disclosed are a device conducive to reduction of parasitic inductance and a method for circuit design and assembly; the device and method cause less parasitic inductance and are good for circuit performance. The device includes an integrated circuit of ball grid array packaging (BGA IC), a printed circuit board (PCB), and an electronic component. The BGA IC includes solder balls including at least one target ball. The PCB is electrically connected to the BGA IC via the solder balls. The electronic component is set between the BGA IC and the PCB and electrically connected to the at least one target ball, in which the height of the electronic component is lower than the stand-off height of each of the solder balls.

DIE-DIE STACKING STRUCTURE AND METHOD FOR MAKING THE SAME

The present invention relates to die-die stacking structure and the method for making the same. The die-die stacking structure comprises a top die having a bottom surface, a first insulation layer covering the bottom surface of the top die, a bottom die having a top surface, a second insulation layer covering the top surface of the bottom die, a plurality of connection members between the top die and the bottom die and a protection material between the first insulation layer and the second insulation layer. The plurality of connection members communicates the top die with the bottom die. The protection material bridges the plurality of connection members to form a mesh layout between the first insulation layer and the second insulation layer. The structure and method of present invention at least provide more strength and stress buffer to resist die warpage and absorb thermal cycling stress, and then prevents the bump and dielectric materials in the die-die stacking structure from cracking caused by thermal stress or external mechanical stress. 1. A die assembly , comprising:a die having an upper surface and a bottom surface;an insulation layer covering at least one of the upper surface and the bottom surface of the die;a plurality of connection members which pass through the insulation layer to connect with the die;a protection material on the surface of the insulation layer;wherein the protection material bridges the plurality of connection members to form a mesh layout on the insulation layer.2. The die assembly of claim 1 , wherein each of the plurality of connection members comprises a first connecting element claim 1 , wherein an end of the first connecting element passes through the insulation layer to connect with the die.3. The die assembly of claim 1 , wherein each of the plurality of connection members comprises a first connecting element and a second connecting element claim 1 , wherein an end of the first connecting element passes through the insulation ...

Stacked device and method of manufacturing the same

A stacked device encompasses a lower chip including a plurality of wiring lands and a plurality of wall-block patterns, each of the wall-block patterns is allocated at a position except locations where the wiring lands are disposed, each of the wall-block patterns has a inclined plane, a height of each of the wall-block patterns measured from a reference plane of the array of the wiring lands is higher than the wiring lands, and an upper chip including a plurality of wiring bumps assigned correspondingly to the positions of the wiring lands, respectively, and a plurality of cone bumps assigned correspondingly to the positions of the wall-block patterns, respectively.

Method for coupling circuit element and package structure

A method for coupling an circuit element onto a carrier element includes steps of providing the circuit element having a front side, a back side, and at least a sidewall formed between the front side and the back side, wherein the sidewall has a sloped portion inclined to the front side at an angle greater than zero degree; bring the circuit element on the carrier element with the front side facing the carrier element; and forming an underfilling structure so that the underfilling structure is disposed on the carrier element and below the circuit element, and covers at least a portion of the sidewall. A package structure constructed by the above-mentioned method is also provided.