Semiconductor device and method for manufacturing semiconductor device

A semiconductor device includes: a support base material, and a semiconductor element bonded to the support base material with a binder, the binder including: a porous metal material that contacts the support base material and the semiconductor element, and a solder that is filled in at least one part of pores of the porous metal material.

Chip package and manufacturing method thereof

An embodiment of the invention provides a manufacturing method of a chip package including: providing a semiconductor wafer having a plurality of device regions separated by a plurality of scribe lines; bonding a package substrate to the semiconductor wafer wherein a spacer layer is disposed therebetween and defines a plurality of cavities respectively exposing the device regions and the spacer layer has a plurality of through holes neighboring the edge of the semiconductor wafer; filling an adhesive material in the through holes wherein the material of the spacer layer is adhesive and different from the adhesive material; and dicing the semiconductor wafer, the package substrate and the spacer layer along the scribe lines to form a plurality of chip packages separated from each other.

Starting material for a sintered bond and process for producing the sintered bond

The invention relates to a starter material for a sintering compound, said starter material comprising particles which at least proportionally contain an organic metal compound and/or a precious metal oxide, the organic metal compound and/or the precious metal oxide being converted during heat treatment of the starter material into the elemental metal and/or precious metal. The invention is characterized in that the particles have a coating containing a reducing agent by means of which the organic metal compound and/or precious metal oxide is reduced to the elemental metal and/or precious metal at a temperature below the sintering temperature of the elemental metal and/or precious metal.

Submicron connection layer and method for using the same to connect wafers

A submicron connection layer and a method for using the same to connect wafers is disclosed. The connection layer comprises a bottom metal layer formed on a connection surface of a wafer, an intermediary diffusion-buffer metal layer formed on the bottom metal layer, and a top metal layer formed on the intermediary diffusion-buffer metal layer. The melting point of the intermediary diffusion-buffer metal layer is higher than the melting points of the top and bottom metal layers. The top and bottom metal layers may form a eutectic phase. During bonding wafers, two top metal layers are joined in a liquid state; next the intermediary diffusion-buffer metal layers are distributed uniformly in the molten top metal layers; then the top and bottom metal layers diffuse to each other to form a low-resistivity eutectic intermetallic compound until the top metal layers are completely exhausted by the bottom metal layers.

Die connections using different underfill types for different regions

Die connections are described using different underfill types for different regions. In one example, a first electrically-non-conductive underfill paste (NCP) type is applied to an I/O region of a first die. A second NCP type is applied outside the I/O region of the first die, the second NCP type having more filler than the first NCP type, and the second die is bonded to a first die using the NCP.

Method for producing a through semiconductor via connection

A method of producing a through semiconductor via (TSV) connection is disclosed. In one aspect, an opening of the TSV is produced for contacting a first semiconductor die bonded to a second die or to a temporary carrier. The first die includes fin-shaped devices in the front end of line of the die. Etching of the TSV opening does not end on a metal pad, but the opening is etched until reaching a well that is formed of material of a first doping type and formed in the first die amid semiconductor material of a second doping type opposite the first. After filling the TSV opening with a conductive material, the TSV connects to a conductor of an intermediate metallization (IM) of the first die through at least one fin extending from the well and connected to the conductor. A package of dies comprising at least one TSV produced by the above method is also disclosed.

PRINTED INTERCONNECTS FOR SEMICONDUCTOR PACKAGES

A method forming a packaged semiconductor device includes providing a first semiconductor die (first die) having bond pads thereon mounted face-up on a package substrate or on a die pad of a lead frame (substrate), wherein the substrate includes terminals or contact pads (substrate pads). A first dielectric layer is formed including printing a first dielectric precursor layer including a first ink having a first liquid carrier solvent extending from the substrate pads to the bond pads. A first interconnect precursor layer is printed including a second ink having a second liquid carrier over the first dielectric layer extending from the substrate pads to the bond pads. Sintering or curing the first interconnect precursor layer removes at least the second liquid carrier to form an electrically conductive interconnect including an ink residue which connects respective substrate pads to respective bond pads. 1. A method of forming packaged semiconductor devices , comprising:providing a first semiconductor die (first die) having bond pads thereon mounted face up on a package substrate or on a die pad of a lead frame (substrate), wherein said substrate includes terminals or contact pads (substrate pads);forming a first dielectric layer comprising printing a first dielectric precursor layer comprising a first ink including a first liquid carrier extending from said substrate pads to said bond pads;printing a first interconnect precursor layer comprising a second ink including a second liquid carrier over said first dielectric layer or said first dielectric precursor layer extending from said substrate pads to said bond pads, andsintering or curing said first interconnect precursor layer to remove at least said second liquid carrier to form a first electrically conductive interconnect comprising an ink residue which connects respective ones of said substrate pads to respective ones of said bond pads.2. The method of claim 1 , further comprising:forming a second dielectric ...

SOLDER PRINTING

A method includes performing a non-screen printing process that deposits solder on a lead frame or on conductive features of a semiconductor die or wafer, or on or in a conductive via of a laminate structure. The method further comprises engaging the semiconductor die to the lead frame, performing a thermal process that reflows the solder, performing a molding process that forms a package structure which encloses the semiconductor die and a portion of the lead frame, and separating a packaged electronic device from a remaining portion of the lead frame. 1. A method , comprising:performing a non-screen printing process that deposits solder on a lead frame or on conductive features of a semiconductor die or wafer;engaging the semiconductor die to the lead frame;performing a thermal process that reflows the solder;performing a molding process that forms a package structure, which encloses the semiconductor die and a portion of the lead frame; andseparating a packaged electronic device from a remaining portion of the lead frame.2. The method of claim 1 , further comprising:after performing the non-screen printing process and before engaging the semiconductor die to the lead frame, depositing flux on the solder.3. The method of claim 2 , wherein depositing the flux on the solder comprises performing a second non-screen printing process that deposits the flux on the solder.4. The method of claim 1 , wherein the non-screen printing process deposits the solder mixed with flux.5. The method of claim 1 , wherein the non-screen printing process deposits the solder as an alloy of tin (Sn) claim 1 , silver (Ag) claim 1 , and copper (Cu).6. The method of claim 1 , wherein the non-screen printing process deposits the solder as an alloy mixture of melted particles using a heated print head.7. The method of claim 1 , wherein the non-screen printing process deposits the solder as particles in a solvent.8. The method of claim 7 , wherein the non-screen printing process deposits the ...

Fabricating pillar solder bump

A substrate bonding method is able to reliably bond substrates while avoiding a reduction in yield made worse by finer pitches. The substrate bonding method can include: forming an adhesive resin layer on a surface of a first substrate on which a pad has been formed; forming an opening on the adhesive resin layer above the pad; filling the opening with molten solder to form a pillar-shaped solder bump; and applying heat and pressure to the first substrate and a second substrate while a terminal formed on the second substrate is aligned with the solder bump.

Anisotropic conductive film with carbon-based conductive regions and related semiconductor device assemblies and methods

An anisotropic conductive film (ACF) is formed with an ordered array of discrete regions that include a conductive carbon-based material. The discrete regions, which may be formed at small pitch, are embedded in at least one adhesive dielectric material. The ACF may be used to mechanically and electrically interconnect conductive elements of initially-separate semiconductor dice in semiconductor device assemblies. Methods of forming the ACF include forming a precursor structure with the conductive carbon-based material and then joining the precursor structure to a separately-formed structure that includes adhesive dielectric material to be included in the ACF. Sacrificial materials of the precursor structure may be removed and additional adhesive dielectric material formed to embed the discrete regions with the conductive carbon-based material in the adhesive dielectric material of the ACF.

MANUFACTURING METHOD OF SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR APPARATUS

A manufacturing method of a semiconductor apparatus includes preparing an intermediate member that includes a first member having a first substrate comprising a semiconductor element formed thereon, a second member having a second substrate, the second substrate including a part of a circuit electrically connected to the semiconductor element and having a linear expansion coefficient different from that of the first substrate, and a third member having a third substrate showing such a linear expansion coefficient that a difference between itself and the linear expansion coefficient of the first substrate is smaller than a difference between the linear expansion coefficients of the first substrate and the second substrate, and includes bonding the first member and the second member together. A first bonding electrode containing copper electrically connected to the semiconductor element and a second bonding electrode containing copper electrically connected to the circuit are bonded together. 1. A manufacturing method of a semiconductor apparatus , comprising: a first member including a first substrate a comprising semiconductor element formed thereon;', 'a second member including a second substrate, the second substrate including a part of a circuit electrically connected to the semiconductor element and having a linear expansion coefficient different from a linear expansion coefficient of the first substrate; and', 'a third member including a third substrate, a difference between a linear expansion coefficient of the third substrate and the linear expansion coefficient of the first substrate is smaller than a difference between the linear expansion coefficient of the first substrate and the linear expansion coefficient of the second substrate, wherein the second member is interposed between the first member and the third member; and, 'preparing an intermediate member that includesheating the intermediate member to bond the first member and the second member together ...

ANISOTROPIC CONDUCTIVE FILM AND MANUFACTURING METHOD THEREOF

An anisotropic conductive film A includes a conductive particle array layer in which a plurality of conductive particles are arrayed in a prescribed manner and held in an insulating resin layer The anisotropic conductive film A has a direction in which a thickness distribution, around the individual conductive particle, of the insulating resin layer holding the array of the conductive particles is asymmetric with respect to the conductive particle The direction in which the thickness distribution is asymmetric is aligned in the same direction in the plurality of conductive particles. When an electronic component is mounted using this anisotropic conductive film A, short circuits and conductive failure can be reduced. 1. An anisotropic conductive film comprising:a conductive particle array layer in which a plurality of conductive particles are arrayed in a prescribed manner and held in an insulating resin layer, the anisotropic conductive film having a direction in which a thickness distribution, around the individual conductive particle, of the insulating resin layer holding the array of the conductive particles is asymmetric with respect to the conductive particle.2. The anisotropic conductive film according to claim 1 , wherein the direction in which the thickness distribution is asymmetric is aligned in the same direction in the plurality of conductive particles.3. The anisotropic conductive film according to claim 1 , wherein in a cross section of the anisotropic conductive film when the anisotropic conductive film is cut in the direction in which the thickness distribution is asymmetric claim 1 , the direction passing through a center of the conductive particle claim 1 , an area of the insulating resin layer surrounding the conductive particle is configured such that an area on one side of the conductive particle is smaller than an area on the other side.4. The anisotropic conductive film according to claim 3 , wherein in the cross section of the anisotropic ...

CHIP MOUNTING STRUCTURE

Highly reliable chip mounting is accomplished by using a substrate having such a shape that a stress exerted on a flip-chip-connected chip can be reduced, so that the stress exerted on the chip is reduced and separation of an interlayer insulating layer having a low dielectric constant (low-k) is minimized. Specifically, in a chip mounting structure, a chip including an interlayer insulating layer having a low dielectric constant (low-k) is flip-chip connected to a substrate via bumps is shown. In the chip mounting structure, the substrate has such a shape that a mechanical stress exerted on the interlayer insulating layer at corner portions of the chip due to a thermal stress is reduced, the thermal stress occurring due to a difference in coefficient of thermal expansion between the chip and the substrate. 1. A method for changing a shape of a substrate to reduce stress exerted on an interlayer insulating layer of a chip , the method comprising:providing the substrate;mounting the chip on the substrate such that a center of the chip corresponds to a center of the substrate and such that sides of the chip are parallel to sides of the substrate;measuring a distance B between a side of the chip and a nearest side of the substrate; andcutting off square portions of the substrate from each corner of the substrate such that a distance between a corner of the chip and a nearest corner of the substrate is less than the distance B.2. The method of claim 1 , wherein each square portion has sides of a length c.4. A method for mounting a chip on a substrate claim 1 , the method comprising:providing a chip having an interlayer insulating layer, the interlayer insulating layer having a low dielectric constant;mounting the chip to a substrate such that there is a distance B between a side of the chip and a nearest side of the substrate;connecting the chip to the substrate using flip-chip bumps; andcutting off right-angle isosceles triangle portions of the substrate from each ...

DIELECTRIC AND METALLIC NANOWIRE BOND LAYERS

In some examples, an electronic device comprises a first component having a surface, a second component having a surface, and a bond layer positioned between the surfaces of the first and second components to couple the first and second components to each other. The bond layer includes a set of metallic nanowires and a dielectric portion. The dielectric portion comprises a polymer matrix and dielectric nanoparticles. 1. A method of forming an electronic device , the method comprising:providing a first die including a first surface and a second die including a second surface; andpositioning a bond layer positioned between the first surface and second surface the bond layer including a set of metallic wires and a dielectric portion, the dielectric portion comprising a polymer matrix and dielectric nanoparticles.2. The method of claim 1 , wherein the dielectric nanoparticles are selected from the group consisting of silicon nitride claim 1 , aluminum nitride claim 1 , boron nitride claim 1 , and aluminum oxide.3. The method of claim 1 , wherein the dielectric portion is porous.4. The method of claim 1 , wherein a the set of metallic wires is a set of metallic nanowires including a length-to-diameter ratio of at least 100:1.5. The method of claim 1 , wherein the bond layer further includes a metal layer coupled to the set of metallic wires.6. The method of claim 1 , wherein the bond layer further includes a metal layer and a set of metallic nanoparticles positioned on the metal layer claim 1 , the set of metallic nanoparticles coupled to the set of metallic wires.7. The method of claim 1 , wherein the set of metallic wires extend in a direction substantially orthogonal to the first surface or the second surface.8. The method of claim 1 , wherein a viscosity of the dielectric portion is sufficient to prevent flow of the dielectric portion into a pore of a nanowire in the set of metallic nanowires.9. The method of claim 1 , wherein a diameter of a wire in the set of ...

Printed interconnects for semiconductor packages

A method forming a packaged semiconductor device includes providing a first semiconductor die (first die) having bond pads thereon mounted face-up on a package substrate or on a die pad of a lead frame (substrate), wherein the substrate includes terminals or contact pads (substrate pads). A first dielectric layer is formed including printing a first dielectric precursor layer including a first ink having a first liquid carrier solvent extending from the substrate pads to the bond pads. A first interconnect precursor layer is printed including a second ink having a second liquid carrier over the first dielectric layer extending from the substrate pads to the bond pads. Sintering or curing the first interconnect precursor layer removes at least the second liquid carrier to form an electrically conductive interconnect including an ink residue which connects respective substrate pads to respective bond pads.

BOND MATERIALS WITH ENHANCED PLASMA RESISTANT CHARACTERISTICS AND ASSOCIATED METHODS

Several embodiments of the present technology are directed to bonding sheets having enhanced plasma resistant characteristics, and being used to bond to semiconductor devices. In some embodiments, a bonding sheet in accordance with the present technology comprises a base bond material having one or more thermal conductivity elements embedded therein, and one or more etched openings formed around particular regions or corresponding features of the adjacent semiconductor components. The bond material can include PDMS, FFKM, or a silicon-based polymer, and the etch resistant components can include PEEK, or PEEK-coated components. 1. A bonding sheet for use with semiconductor components , the bonding sheet comprising:a first side configured to be attached to a first semiconductor component;a second side configured to be attached to a second semiconductor component;an etch resistant material disposed in first regions of the bonding sheet;a bond material disposed in second regions of the bonding sheet; anda plurality of thermal conductive elements embedded within the bond material in the second regions,wherein individual first regions are distinct from and positioned proximate to individual second regions.2. The bonding sheet of wherein the thermal conductivity elements are configured to decompose into a gas when exposed to plasma processes.3. The bonding sheet of wherein:the bond material comprises at least one of polydimethylsiloxane (PDMS) and fluoroelastomers (FKM),the etch resistant material comprises polyetheretherketone (PEEK), andthe thermal conductivity elements comprise organic fillers configured to decompose into a gas when exposed to plasma processes.4. The bonding sheet of claim 1 , wherein the bonding sheet has:a thickness less than about 200 microns,a flatness across a length of the bonding sheet less than about 20 microns, andan elongation specification less than about 20%.5. The bonding sheet of claim 1 , further comprising:a thermal conductivity less ...

Selective micro device transfer to receiver substrate

A method of selectively transferring micro devices from a donor substrate to contact pads on a receiver substrate. Micro devices being attached to a donor substrate with a donor force. The donor substrate and receiver substrate are aligned and brought together so that selected micro devices meet corresponding contact pads. A receiver force is generated to hold selected micro devices to the contact pads on the receiver substrate. The donor force is weakened and the substrates are moved apart leaving selected micro devices on the receiver substrate. Several methods of generating the receiver force are disclosed, including adhesive, mechanical and electrostatic techniques.

SELECTIVE MICRO DEVICE TRANSFER TO RECEIVER SUBSTRATE

A method of selectively transferring micro devices from a donor substrate to contact pads on a receiver substrate. Micro devices being attached to a donor substrate with a donor force. The donor substrate and receiver substrate are aligned and brought together so that selected micro devices meet corresponding contact pads. A receiver force is generated to hold selected micro devices to the contact pads on the receiver substrate. The donor force is weakened and the substrates are moved apart leaving selected micro devices on the receiver substrate. Several methods of generating the receiver force are disclosed, including adhesive, mechanical and electrostatic techniques.

ANISOTROPIC CONDUCTIVE FILM AND MANUFACTURING METHOD THEREOF

An anisotropic conductive film 1A includes a conductive particle array layer 4 in which a plurality of conductive particles 2 are arrayed in a prescribed manner and held in an insulating resin layer The anisotropic conductive film 1A has a direction in which a thick distribution, around the individual conductive particle, of the insulating resin layer 3 holding the array of the conductive particles 2 is asymmetric with respect to the conductive particle 2. The direction in which the thickness distribution is asymmetric is aligned in the same direction in the plurality of conductive particles. When an electronic component is mounted using this anisotropic conductive film 1A, short circuits and conductive failure can be reduced. 1. An anisotropic conductive film comprising:a conductive particle array layer in which a plurality of conductive particles are arrayed in a prescribed manner and held in an insulating resin layer,wherein the anisotropic conductive film has a resin amount distribution, around the individual conductive particle, of the insulating resin layer holding the array of the conductive particles, and the resin amount distribution has a direction in which a resin amount decreases.2. The anisotropic conductive film according to claim 1 , wherein claim 1 , in a film surface direction claim 1 , the resin amount distribution claim 1 , around the individual conductive particle claim 1 , of the insulating resin layer holding the array of the conductive particles has a direction in which a resin amount decreases.3. The anisotropic conductive film according to claim 1 , wherein the direction in which the resin amount is less aligned in the same direction in the plurality of conductive particles.4. The anisotropic conductive film according to claim 1 , wherein in a cross section of the anisotropic conductive film when the anisotropic conductive film is cut in the direction in which the resin amount decreases claim 1 , the direction passing through a center of the ...

POWER SEMICONDUCTOR DEVICE

Provided is a technique of improving joint strength between a joining layer and a resin. A power semiconductor device includes a wiring member, a semiconductor element, a joining layer joining the wiring member and the semiconductor element to each other, and a resin covering the wiring member, the semiconductor element, and the joining layer. The joining layer includes a first joining layer provided to be adjacent to the resin and having a void filled with the resin. A filler contained in the resin has a maximum width greater than a minimum diameter of the void in the first joining layer. 1. A power semiconductor device comprising:a wiring member;a semiconductor element;a joining layer joining the wiring member and the semiconductor element to each other; anda resin covering the wiring member, the semiconductor element, and the joining layer,wherein the joining layer comprises a first joining layer provided to be adjacent to the resin and comprising a void filled with the resin, anda filler contained in the resin has a maximum width greater than a minimum diameter of the void in the first joining layer.2. The power semiconductor device according to claim 1 , wherein the joining layer further comprises a second joining layer provided to be surrounded by the wiring member claim 1 , the semiconductor element claim 1 , and the first joining layer claim 1 , and having a smaller void rate than the first joining layer.3. The power semiconductor device according to claim 1 , wherein the first joining layer is disposed between the wiring member and the semiconductor element claim 1 , and is disposed outside the semiconductor element in plan view.4. The power semiconductor device according to claim 1 , wherein the first joining layer has a void rate of 5% or greater and 20% or smaller.5. The power semiconductor device according to claim 1 , wherein the joining layer contains silver claim 1 , gold claim 1 , copper claim 1 , or nickel.6. The power semiconductor device ...

SEMICONDUCTOR DEVICE, DISPLAY PANEL, DISPLAY DEVICE, ELECTRONIC DEVICE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Void formation in a semiconductor device is to be prevented. The semiconductor device includes a semiconductor element, signal lines, and a protective layer. In the semiconductor device, the semiconductor element is mounted on a substrate. The signal lines in the semiconductor device are connected to the semiconductor element on the substrate. Further, the protective layer in the semiconductor device is provided in an inter-line region interposed between both edges of two adjacent signal lines among the signal lines on the substrate. 1. A semiconductor device comprising:a semiconductor element mounted on a substrate;a plurality of signal lines connected to the semiconductor element on the substrate; anda protective layer formed in an inter-line region interposed between both edges of two adjacent signal lines among the signal lines on the substrate.2. The semiconductor device according to claim 1 , wherein photosensitive resin is provided in the inter-line regions claim 1 , except for at least one of the inter-line regions.3. The semiconductor device according to claim 2 , wherein the photosensitive resin is provided preferentially in a region between signal lines with a small potential difference claim 2 , the region being of the inter-line regions.4. The semiconductor device according to claim 2 , wherein the photosensitive resin is provided in a region between signal lines having substantially the same potential claim 2 , the region being of the inter-line regions.5. The semiconductor device according to claim 2 , wherein at least one piece of the photosensitive resin is provided at each side of the semiconductor element.6. The semiconductor device according to claim 2 , wherein the photosensitive resin is not provided between terminals with a larger potential difference than a predetermined level.7. The semiconductor device according to claim 2 , whereinthe signal lines transmit a gradation signal indicating a gradation of a predetermined color, the gradation ...

METHOD AND APPARATUS FOR CREATING A BOND BETWEEN OBJECTS BASED ON FORMATION OF INTER-DIFFUSION LAYERS

The present disclosure provides a method of creating a bond between a first object and a second object. For example, at least one insert may be provided at a location in a space formed between the first object and the second object. In additional, a filler material may be provided proximal to the location. An inter-diffusion layer may be formed, wherein a first portion of the inter-diffusion layer is formed by diffusion between the filler material and the at least one insert, wherein a second portion of the inter-diffusion layer is formed between the filler material and the first object, wherein a third portion of the inter-diffusion layer is formed between the filler material and the second object, wherein the first portion is coadunate with each of the second portion and third portion. 1. An electronic module comprising:a substrate;at least one chip; a first set of inserts placed inside a space between the substrate and the at least one chip,', "wherein diffusion of the second set of inserts occurs into at least one of the following: the substrate's mating surface, the at least one chip's mating surface and the first set of inserts;", 'a second set of inserts placed inside a space formed by the substrate, the at least one chip and the first set of inserts,'}], 'a plurality of inserts comprisinga gap between the first set of the inserts and the substrate; and 'wherein the diffusion results in formation of at least one of the following: a coadunate inter-diffusion layer along at least one insert of the first set of inserts to the at least one chip and a coadunate inter-diffusion layer along at least one insert of the first set of the inserts to the substrate.', 'a gap between the first set of inserts and the at least one chip,'}21. The electronic module of lain , wherein the at least one insert of the first set of inserts is comprised in at least one of the substrate's mating surface and the chip's mating surface.3. The electronic module of claim 1 , wherein the at ...

Microelectronics h-frame device

A microelectronics H-frame device includes: a stack of two or more substrates wherein the substrate stack comprises a top substrate and a bottom substrate, wherein bonding of the top substrate to the bottom substrate creates a vertical electrical connection between the top substrate and the bottom substrate, wherein the top surface of the top substrate comprises top substrate top metallization, wherein the bottom surface of the bottom substrate comprises bottom substrate bottom metallization; mid-substrate metallization located between the top substrate and the bottom substrate; a micro-machined top cover bonded to a top side of the substrate stack; and a micro-machined bottom cover bonded to a bottom side of the substrate stack.

Method of applying conductive adhesive and manufacturing device using the same

An applying method includes the following steps. Firstly, a conductive adhesive including a plurality of conductive particles and an insulating binder is provided. Then, a carrier plate is provided. Then, a patterned adhesive is formed on the carrier plate by the conductive adhesive, wherein the patterned adhesive includes a first transferring portion. Then, a manufacturing device including a needle is provided. Then, the needle of the manufacturing device is moved to contact the first transferring portion. Then, the transferring portion is transferred to a board by the manufacturing device.

ANISOTROPIC CONDUCTIVE FILM

An anisotropic conductive film which can be used as a standard product as long as no problems arise in anisotropic conductive connections, even in a case where omissions are present in a prescribed disposition of conductive particles, includes a regular disposition region in which conductive particles are disposed regularly in an insulating resin binder, and has a length of 5 m or greater. A standard region including no sections with more than a prescribed number of consecutive omissions in conductive particles is present in the regular disposition region over a prescribed width in a short-side direction of the anisotropic conductive film and at least a prescribed length in a long-side direction of the anisotropic conductive film. 1. An anisotropic conductive film having a regular disposition region in which conductive particles are disposed regularly in an insulating resin binder ,wherein the anisotropic conductive film is formed on a release film, anda standard region including no sections with more than a prescribed number of consecutive omissions in conductive particles is present in the regular disposition region over a prescribed width in a short-side direction of the anisotropic conductive film and at least a prescribed length in a long-side direction of the anisotropic conductive film.2. The anisotropic conductive film according to claim 1 , wherein the anisotropic conductive film is formed long.3. The anisotropic conductive film according to claim 1 , wherein the prescribed width in a short-side direction of the anisotropic conductive film is not less than 10% and not greater than 95% of the entire width in a short-side direction of the anisotropic conductive film claim 1 , and the prescribed length in a long-side direction of the anisotropic conductive film is not less than 5 mm and not greater than 1000 m.4. The anisotropic conductive film according to claim 2 , wherein the prescribed width in a short-side direction of the anisotropic conductive film is ...

DISPLAY PANEL AND BONDING METHOD OF THE SAME

The present disclosure provides a display panel and a bonding method of the display panel. Signal lines of a display area of the display panel extend to a bonding area of the non-display area. A conductive adhesive layer is formed in the bonding area. A waterproof adhesive layer is formed in the non-display area of the bonding area near the display area. The conductive adhesive layer includes a conductive-particles doped region and a first insulating rubber material region formed in the conductive-particles doped region near the display area. 1. A display panel , wherein the display panel comprises a display area and a non-display area formed at a side of the display area , a plurality of signal lines is arranged in the non-display area , a bonding area is defined in the non-display area , ends of one side of the signal lines extend to the bonding area;an overlapping area and a non-overlapping area are defined in the non-display area and the bonding area, a first area is defined in the non-overlapping area and formed at a side of the bonding area, a second area is defined in the non-overlapping area and formed at another, opposite side of the bonding area; anda waterproof adhesive layer is formed in the first region, a conductive adhesive layer is formed in the bonding area; wherein the conductive adhesive layer comprises a conductive-particles doped region and a first insulating rubber material region formed at one side of the conductive-particles doped region, and the first insulating rubber material region is formed between the conductive-particles doped region and the second area.2. The display panel of the claim 1 , wherein a second insulating rubber material region is formed at another claim 1 , opposite side of the conductive-particles doped region claim 1 , the second insulating rubber material region extends toward the first area and ends at a side edge of the bonding area claim 1 , the first insulating rubber region extends toward the second area and ends ...

Solder Preform for Establishing a Diffusion Solder Connection and Method for Producing a Solder Preform

Various embodiments include a solder preform for establishing a diffusion solder connection comprising: a microstructure including a solder material and a metallic material; a first joining surface for a first joining partner and a second joining surface for a second joining partner; and a diffusion zone comprising an intermetallic compound of at least some of the solder material and at least some of the metallic material. The first joining surface and the second joining surface include at least some solder material.

System on Integrated Chips and Methods of Forming Same

An embodiment method for forming a semiconductor package includes attaching a first die to a first carrier, depositing a first isolation material around the first die, and after depositing the first isolation material, bonding a second die to the first die. Bonding the second die to the first die includes forming a dielectric-to-dielectric bond. The method further includes removing the first carrier and forming fan-out redistribution layers (RDLs) on an opposing side of the first die as the second die. The fan-out RDLs are electrically connected to the first die and the second die. 1. A package comprising:a first semiconductor die;a first isolation material around the first semiconductor die;a second semiconductor die over the first semiconductor die, the first semiconductor die and the second semiconductor die share a first insulator-to-insulator interface and a first metal-to-metal interface, the second semiconductor die and the first isolation material share a second insulator-to-insulator interface;a second isolation material around the second semiconductor die; andredistribution layers over the second semiconductor die, the redistribution layers are electrically connected to the first semiconductor die and the second semiconductor die.2. The package of further comprising:a third semiconductor die, the third semiconductor die and the second semiconductor die share a third insulator-to-insulator interface and a second metal-to-metal interface.3. The package of claim 2 , wherein the first isolation material is disposed around the third semiconductor die.4. The package of claim 1 , wherein the redistribution layers are electrically connected to the first semiconductor die by a conductive via claim 1 , the conductive via extends along a sidewall of the second semiconductor die claim 1 , and the second semiconductor die is physically separated from the conductive via by the second isolation material.5. The package of claim 4 , wherein the conductive via extends ...

SEMICONDUCTOR CHIP STACK ARRANGEMENT AND SEMICONDUCTOR CHIP FOR PRODUCING SUCH A SEMICONDUCTOR CHIP STACK ARRANGEMENT

A semiconductor-chip stack package includes a plurality of semiconductor chips disposed in a stack arrangement and at least one connecting substrate which connects the semiconductor chips. The semiconductor chips include a chip terminal face on a chip edge extending at least partially as a side terminal face in a side surface of the semiconductor chip. The side surfaces of the semiconductor chips provided with the side terminal face are arranged in a shared side surface plane S of the semiconductor-chip stack arrangement. The connecting substrate is arranged with a contact surface parallel to the side surface plane S of the semiconductor chips. Substrate terminal faces are formed on the contact surface for connecting a connection conductor structure formed in the connecting substrate and which are connected to the side terminal faces via a connecting material in a connection plane V parallel to the contact surface. 11. A semiconductor-chip stack package comprising a plurality of semiconductor chips disposed in a stack arrangement and at least one connecting substrate which connects the semiconductor chips , the semiconductor chips being equipped with at least one chip terminal face on at least one chip edge , said chip terminal face extending at least partially as a side terminal face in a side surface of the semiconductor chip formed on the chip edge , the side surfaces of the semiconductor chips provided with the side terminal face being arranged in a shared side surface plane S of the semiconductor-chip stack arrangement , the connecting substrate being arranged with a contact surface parallel to the side surface plane S of the semiconductor chips and comprising substrate terminal faces which are formed on the contact surface for connecting a connection conductor structure formed in the connecting substrate and which are connected to the side terminal faces in an electrically conductive manner via a connecting material in a connection plane V parallel to the ...

Methods for bonding substrates

Methods for fabricating and refurbishing an assembly are disclosed herein. The method begins by applying an adhesive layer onto a first substrate. A second substrate is placed onto the adhesive layer, thereby securing the two substrates together, the adhesive layer bounding at least one side of a channel that extends laterally between the substrates to an exterior of the assembly. And, the substrates and the adhesive layer are subjected to a bonding procedure and allowing outgassing of volatiles from the adhesive layer to escape from between the substrates through the channel, wherein the substrates bonded by the adhesive layer form a component for a semiconductor vacuum processing chamber.

Display apparatus and method of manufacturing the same

A display apparatus includes a display panel including a lower base substrate and a connecting portion disposed on the lower base substrate, a flexible circuit board attached on a side surface of the display panel, and including a base film and a conductive pattern disposed on the base film, a conductive paste part disposed between the side surface of the display panel and the flexible circuit board, a first anisotropic conductive film (ACF) film disposed between the side surface of the display panel and the conductive paste part, and a second ACF film disposed between the conductive paste part and the flexible circuit board. The connecting portion is exposed at the side surface of the display panel, and the first ACF film directly makes contact with the connecting portion.

SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME

A semiconductor device manufacturing technique which allows reduction of semiconductor chip size. First, a pad and other wires are formed over an insulating film. A surface protective film is formed over the insulating film including the pad and wires, and an opening is made in the surface protective film. The opening lies over the pad and exposes a surface of the pad. A bump electrode is formed over the surface protective film including the opening. Here, the pad is smaller than the bump electrode. Consequently, the wires are arranged just beneath the bump electrode in the same layer as the pad . In other words, the wires are arranged in space which becomes available because the pad is small enough. 1. A semiconductor device which includes a semiconductor chip comprising:(a) a pad formed over a semiconductor substrate;(b) an insulating film having an opening over the pad; and(c) a bump electrode formed over the insulating film including the opening,wherein the pad is smaller than the bump electrode, andwherein a wire different from the pad is formed in a layer under the bump electrode through the insulating film.2. The semiconductor device according to claim 1 , wherein the wire different from the pad includes a dummy wire.3. The semiconductor device according to claim 1 , wherein the wire different from the pad includes a signal wire or power wire.4. The semiconductor device according to claim 1 , wherein the wire different from the pad is formed in the same layer as the pad.5. The semiconductor device according to claim 1 , wherein a plurality of the wires different from the pad exist.6. The semiconductor device according to claim 1 , wherein the bump electrode extends in a prescribed direction.7. The semiconductor device according to claim 1 , wherein the bump electrodes are arranged in a zigzag pattern.8. The semiconductor device according to claim 5 , wherein the width of the pad is smaller than the width of a given wire included in the wires different from ...

Flexible device including conductive traces with enhanced stretchability

Flexible devices including conductive traces with enhanced stretchability, and methods of making and using the same are provided. The circuit die is disposed on a flexible substrate. Electrically conductive traces are formed in channels on the flexible substrate to electrically contact with contact pads of the circuit die. A first polymer liquid flows in the channels to cover a free surface of the traces. The circuit die can also be surrounded by a curing product of a second polymer liquid.

Anisotropic conductive film and method of making conductive connection

An anisotropic conductive film includes: an insulation region having a planer shape and containing an insulating filler at a first content rate; and a plurality of conductive particle holding regions arranged in the insulation region, the conductive particle holding regions holding conductive particles and containing the insulating filler at a second content rate lower than the first content rate, the conductive particle holding regions being arranged discretely in a planar direction of the insulation region. A method of making conductive connection between a first terminal arranged on a first member and a second terminal arranged on a second member includes: preliminarily tacking the anisotropic conductive film to the first member; holding the first and second members such that the first and second terminals face to each other across the preliminarily tacked anisotropic conductive film; pressing the first and second members to each other; and heating the anisotropic conductive film.

Composite and multilayered silver films for joining electrical and mechanical components

Materials for die attachment such as silver sintering films may include reinforcing, modifying particles for enhanced performance. Methods for die attachment may involve the of such materials.

Selective micro device transfer to receiver substrate

A method of selectively transferring micro devices from a donor substrate to contact pads on a receiver substrate. Micro devices being attached to a donor substrate with a donor force. The donor substrate and receiver substrate are aligned and brought together so that selected micro devices meet corresponding contact pads. A receiver force is generated to hold selected micro devices to the contact pads on the receiver substrate. The donor force is weakened and the substrates are moved apart leaving selected micro devices on the receiver substrate. Several methods of generating the receiver force are disclosed, including adhesive, mechanical and electrostatic techniques.

Hybrid thermal interface material for ic packages with integrated heat spreader

Flip chip packages are described that include two or more thermal interface materials (TIMs). A die is mounted to a substrate by solder bumps. A first TIM is applied to the die, and has a first thermal resistance. A second TIM is applied to the die and/or the substrate, and has a second thermal resistance that is greater than the first thermal resistance. An open end of a heat spreader lid is mounted to the substrate such that the die is positioned in an enclosure formed by the heat spreader lid and substrate. The first TIM and the second TIM are each in contact with an inner surface of the heat spreader lid. A ring-shaped stiffener may surround the die and be connected between the substrate and heat spreader lid by the second TIM.

ANISOTROPIC CONDUCTIVE FILM, METHOD FOR PRODUCING ANISOTROPIC CONDUCTIVE FILM, METHOD FOR PRODUCING CONNECTION BODY, AND CONNECTION METHOD

To reduce substrate warp occurring after connection an anisotropic conductive film is used. An anisotropic conductive film has: a first insulating adhesive layer; a second insulating adhesive layer; and a conductive particle-containing layer sandwiched by the first insulating adhesive layer and the second insulating adhesive layer and having conductive particles contained in an insulating adhesive, wherein air bubbles are contained between the conductive particle-containing layer and the first insulating adhesive layer, and, the conductive particle-containing layer, a portion thereof below the conductive particles and in contact with the second insulating adhesive layer has a lower degree of cure than other portions thereof. 1. A method for producing a connection body , the connection body being obtained by anisotropic conductive connection between a terminal of a first electronic component and a terminal of a second electronic component by using an anisotropic conductive film , the anisotropic conductive film comprising:a first insulating adhesive layer; anda conductive particle-containing layer laminated on the first insulating adhesive layer and having conductive particles each contained independently in an insulating adhesive;wherein air bubbles are contained between the conductive particle-containing layer and the first insulating adhesive layer, andwherein the air bubbles are contained in accordance with the conductive particles, the method comprising curing the anisotropic conductive film in a sandwiched state of sandwiching the anisotropic conductive film between the first electronic component and the second electronic component.2. A connection body obtained by anisotropic conductive connection between a first electronic component and a second electronic component by using an anisotropic conductive film , the anisotropic conductive film comprising:a first insulating adhesive layer; anda conductive particle-containing layer laminated on the first insulating ...

ANISOTROPIC CONDUCTIVE FILM WITH CARBON-BASED CONDUCTIVE REGIONS AND RELATED SEMICONDUCTOR ASSEMBLIES, SYSTEMS, AND METHODS

An anisotropic conductive film (ACF) is formed with an ordered array of discrete regions that include a conductive carbon-based material. The discrete regions, which may be formed at small pitch, are embedded in at least one adhesive dielectric material. The ACF may be used to mechanically and electrically interconnect conductive elements of initially-separate semiconductor dice in semiconductor device assemblies. Methods of forming the ACF include forming a precursor structure with the conductive carbon-based material and then joining the precursor structure to a separately-formed structure that includes adhesive dielectric material to be included in the ACF. Sacrificial materials of the precursor structure may be removed and additional adhesive dielectric material formed to embed the discrete regions with the conductive carbon-based material in the adhesive dielectric material of the ACF. 1. An anisotropic conductive film , comprising:a pattern of discrete regions mutually laterally spaced by at least one predetermined pitch, each discrete region comprising a conductive carbon-based material; anda dielectric material at least between the discrete regions.2. The anisotropic conductive film of claim 1 , wherein the conductive carbon-based material comprises graphene.3. The anisotropic conductive film of claim 1 , wherein the discrete regions further comprise a seed material on one or more surfaces of the conductive carbon-based material.4. The anisotropic conductive film of claim 3 , wherein the seed material comprises at least one of nickel or copper.5. The anisotropic conductive film of claim 3 , wherein the seed material is disposed on a sidewall of the conductive carbon-based material.6. The anisotropic conductive film of claim 5 , wherein the seed material is further disposed on at least one end surface of the conductive carbon-based material.7. The anisotropic conductive film of claim 1 , wherein the discrete regions consist of the conductive carbon-based ...

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING BASE AND SEMICONDUCTOR ELEMENT AND SEMICONDUCTOR DEVICE

In a method of manufacturing a semiconductor device of one embodiment, support members and a film which is formed of a paste containing metal particles and surrounds the support members are provided above a surface of a base. Then a semiconductor element is provided above the support members and the film. Subsequently, the film is sintered to join the base and the semiconductor element. The support members are formed of a metal which melts at a temperature equal to or below a sintering temperature of the metal particles contained in the paste. The support members support the semiconductor element after the semiconductor element is provided above the support members and the film. 1. A method of manufacturing a semiconductor device , comprising:providing support members, and a film which is formed of a paste containing metal particles and surrounds the support members, above a surface of a base;providing a semiconductor element above the support members and the film; andsintering the film to join the base and the semiconductor element, whereinthe support members are formed of a metal which melts at a temperature equal to or below a sintering temperature of the metal particles contained in the paste and support the semiconductor element after the semiconductor element is provided above the support members and the film.2. The method according to claim 1 , wherein the metal particles include at least one of silver claim 1 , copper or nickel claim 1 , and the diameters of the metal particles are 1 nm or more and 10000 nm or less.3. The method according to claim 1 , wherein the support members contain tin as a primary constituent and in addition at least one selected from a group of bismuth claim 1 , indium and gallium.4. The method according to claim 2 , wherein the support members contain tin as a primary constituent and in addition at least one selected from a group of bismuth claim 2 , indium and gallium.5. The method according to claim 2 , wherein claim 2 , in ...

Anisotropic conductive film, method for producing anisotropic conductive film, method for producing connection body, and connection method

To reduce substrate warp occurring after connection an anisotropic conductive film is used. An anisotropic conductive film has: a first insulating adhesive layer; a second insulating adhesive layer; and a conductive particle-containing layer sandwiched by the first insulating adhesive layer and the second insulating adhesive layer and having conductive particles contained in an insulating adhesive, wherein air bubbles are contained between the conductive particle-containing layer and the first insulating adhesive layer, and, the conductive particle-containing layer, a portion thereof below the conductive particles and in contact with the second insulating adhesive layer has a lower degree of cure than other portions thereof.

Lead frame for improving adhesive fillets on semiconductor die corners

The present disclosure is directed to a lead frame including a die pad with cavities, and methods for attaching a semiconductor die to the lead frame. The cavities allow for additional adhesive to be formed on the die pad at the corners of the semiconductor die, and prevent the additional adhesive from overflowing on to active areas of the semiconductor die.

ANISOTROPIC CONDUCTIVE FILM AND MANUFACTURING METHOD THEREOF

An anisotropic conductive film includes a conductive particle array layer in which a plurality of conductive particles are arrayed in a prescribed manner and held in an insulating resin layer. The anisotropic conductive film has a direction in which a thickness distribution, around the individual conductive particle, of the insulating resin layer holding the array of the conductive particles is asymmetric with respect to the conductive particle. The direction in which the thickness distribution is asymmetric is aligned in the same direction in the plurality of conductive particles. When an electronic component is mounted using this anisotropic conductive film, short circuits and conductive failure can be reduced. 1. An anisotropic conductive film for connecting electronic components via an anisotropic conductive connection , the anisotropic conductive film comprising:a conductive particle array layer in which a plurality of conductive particles are arrayed in a prescribed manner and held in an insulating resin layer, whereinthe insulating resin layer comprises a resin that is present around an individual conductive particle,the resin has a decreasing distribution in which a resin amount decreases in area, the area extending at an incline towards the conductive particle in a direction from a first plane at one end of the conductive particle to a second plane at an opposite end of the conductive particle,an amount of the resin present at the first plane is larger than an amount of resin present at the second plane, andthe anisotropic conductive film is formed before connecting the electronic components via the anisotropic conductive connection.2. The anisotropic conductive film according to claim 1 , wherein in a cross section of the anisotropic conductive film when the anisotropic conductive film is cut in a thickness direction thereof passing through a center of the conductive particle claim 1 , along the direction in which a resin amount decreases claim 1 , an area ...

Physical quantity sensor and semiconductor device

A device includes: a chip; a support member; an adhesive layer disposed on the support member; and a wire electrically connected to the sensor chip on a side face of the sensor chip. Herein the adhesive layer includes a material exhibiting a dilatancy property in which a shear stress increases in a multi-dimensional function as a shear rate increases.

Semiconductor device and method for manufacturing the same

A semiconductor device includes a wiring substrate, a first semiconductor chip provided on the wiring substrate, a supporting member provided on the wiring substrate in a region which does not overlap with the first semiconductor chip in a plan view when viewed from a direction perpendicular to the wiring substrate, a resin member provided on the first semiconductor chip, and a second semiconductor chip provided on the supporting member and the resin member. A method for manufacturing a semiconductor device includes providing a first semiconductor chip in a first region on a wiring substrate, providing a supporting member in a second region on the wiring substrate, providing a resin member in at least a portion on the first semiconductor chip, and providing a second semiconductor chip on the supporting member and the resin member.

Use of Pre-Channeled Materials for Anisotropic Conductors

A semiconductor device assembly has a first substrate, a second substrate, and an anisotropic conductive film. The first substrate includes a first plurality of connectors. The second substrate includes a second plurality of connectors. The anisotropic conductive film is positioned between the first plurality of connectors and the second plurality of connectors. The anisotropic conductive film has an electrically insulative material and a plurality of interconnects laterally separated by the electrically insulative material. The plurality of interconnects forms electrically conductive channels extending from the first plurality of connectors to the second plurality of connectors. A method includes connecting the plurality of interconnects to the first plurality of connectors and the second plurality of connectors, such that the electrically conductive channels are operable to conduct electricity from the first substrate to the second substrate. The method may include passing electrical current through the plurality of interconnects. 1. A semiconductor device assembly comprising:a first substrate having a first plurality of connectors;a second substrate having a second plurality of connectors; andan anisotropic conductive film positioned between the first plurality of connectors and the second plurality of connectors, the anisotropic conductive film having an electrically insulative material and a plurality of interconnects laterally separated by the electrically insulative material, the plurality of interconnects forming electrically conductive channels extending from the first plurality of connectors to the second plurality of connectors.2. The semiconductor device assembly of claim 1 , wherein the anisotropic conductive film is a microporous film and the plurality of interconnects are pores of the microporous film.3. The semiconductor device assembly of claim 2 , wherein the electrically insulative material is acrylic-based or epoxy-based.4. The semiconductor ...

Thermal management solutions for integrated circuit packages

A heat dissipation device may be formed having a planar structure with a first surface and a surface area enhancement structure projecting from or extending into the first surface of the planar structure. In one embodiment, an integrated circuit package may be formed with the heat dissipation device, wherein the heat dissipation device and at least one integrated circuit device are brought into thermal contact with a thermal interface material between the at least one integrated circuit device and the heat dissipation device and wherein the surface area enhancement structure of the heat dissipation device directly contacts the thermal interface material.

SEMICONDUCTOR DEVICE

A semiconductor device includes a semiconductor layer, an electrode layer arranged on the semiconductor layer, a crack starting point layer arranged above the semiconductor layer, and a solder layer being in contact with the electrode layer and the crack starting point layer. A joining force between the solder layer and the crack starting point layer is smaller than a joining force between the solder layer and the electrode layer. 1. A semiconductor device comprising:a semiconductor layer;an electrode layer arranged on the semiconductor layer;a crack starting point layer arranged above the semiconductor layer; anda solder layer being in contact with the electrode layer and the crack starting point layer;whereina joining force between the solder layer and the crack starting point layer is smaller than a joining force between the solder layer and the electrode layer,the crack starting point layer is arranged on the electrode layer, anda thickness of the crack starting point layer is smaller than a width of the crack starting point layer.2. (canceled)3. The semiconductor device according to claim 1 , whereinthe electrode layer is made of a material that forms an alloy more easily with the solder layer than the crack starting point layer.4. The semiconductor device according to claim 1 , whereinthe crack starting point layer is made of aluminum, aluminum silicon, carbon, or polyimide resin. The present teachings relate to a semiconductor device.In a general semiconductor device, due to a temperature cycle in which a temperature of the semiconductor device repeatedly rises and falls during its use, there may be a case where a stress is exerted on an inside of the semiconductor device and a crack (cracking) occurs. Patent Literature 1 (Japanese Patent Application Publication No. 2011-023631) discloses an art for improving resistance to cracks that occur in a semiconductor device. A configuration disclosed in Patent Literature 1 includes a semiconductor element, and an ...

Lead frame for improving adhesive fillets on semiconductor die corners

The present disclosure is directed to a lead frame including a die pad with cavities, and methods for attaching a semiconductor die to the lead frame. The cavities allow for additional adhesive to be formed on the die pad at the corners of the semiconductor die, and prevent the additional adhesive from overflowing on to active areas of the semiconductor die.

Semiconductor device with a layered protection mechanism and associated systems, devices, and methods

A semiconductor device includes a first die; a second die attached over the first die; a first metal enclosure and a second metal enclosure both directly contacting and vertically extending between the first die and the second die, wherein the first metal enclosure peripherally encircles a set of one or more internal interconnects and the second metal enclosure peripherally encircles the first metal enclosure without directly contacting the first metal enclosure; a first enclosure connector electrically connecting the first metal enclosure to a first voltage level; a second enclosure connector electrically connecting the second metal enclosure to a second voltage level; and wherein the first metal enclosure, the second metal enclosure, the first enclosure connector, and the second enclosure connector are configured to provide an enclosure capacitance.

ANISOTROPIC CONDUCTIVE FILM AND CONNECTION STRUCTURE

An anisotropic conductive film includes an insulating adhesive layer and conductive particles disposed thereon. Arrangement axes of the conductive particles having a particle pitch extend in a widthwise direction of the film, and the axes are sequentially arranged with an axis pitch in a lengthwise direction of the film. The particle pitch, axis pitch of the axes, and an angle θ of the axes relative the widthwise direction of the film are determined according to external shapes of terminals so 3 to 40 conductive particles are present on each terminal when a terminal arrangement region of an electronic component is superimposed on the film so a lengthwise direction of each terminal is aligned with the widthwise direction of the film. By using the film, stable connection reliability is obtained and an excessive increase in the density of the conductive particles is suppressed even in the connection of fine pitches. 1. An anisotropic conductive film comprising an insulating adhesive layer , and conductive particles disposed on the insulating adhesive layer , whereinarrangement axes of the conductive particles having a predetermined particle pitch extend in approximately a widthwise direction of the anisotropic conductive film, and the arrangement axes are sequentially arranged with a predetermined axis pitch in a lengthwise direction of the anisotropic conductive film, anda particle pitch in the arrangement axes, an axis pitch of the arrangement axes, and an angle of the arrangement axes relative to the widthwise direction of the film (hereinafter, referred to as an inclination angle of the arrangement axes) are determined according to external shapes of terminals such that 3 to 40 conductive particles are present on each of the terminals when a terminal arrangement region of an electronic component to be connected with the anisotropic conductive film is superimposed on the anisotropic conductive film such that a lengthwise direction of each of the terminals is aligned ...

HIGH DENSITY INTERCONNECTION OF MICROELECTRONIC DEVICES

A microelectronic package of the present description may comprises a first microelectronic device having at least one row of connection structures electrically connected thereto and a second microelectronic device having at least one row of connection structures electrically connected thereto, wherein the connection structures within the at least one first microelectronic device row are aligned with corresponding connection structures within the at least one second microelectronic device row in an x-direction. An interconnect comprising an interconnect substrate having a plurality of electrically isolated conductive traces extending in the x-direction on a first surface of the interconnect substrate may be attached to the at least one first microelectronic device connection structure row and the at least one second microelectronic device connection structure row, such that at least one interconnect conductive trace forms a connection between a first microelectronic device connection structure and its corresponding second microelectronic device connection structure. 1. A microelectronic package comprising:a first microelectronic device having an active surface, an opposing back surface, at least one side, and at least one row of connection structures formed on the active surface;a second microelectronic device having an active surface, an opposing back surface, at least one side, and at least one row of connection structures formed on the active surface;wherein the at least one side of the first microelectronic device abuts the at least one side of the second microelectronic device, and wherein at least one connection structure within the at least one first microelectronic device row is aligned with a corresponding connection structure within the at least one second microelectronic device row in an x-direction; andan interconnect comprising an interconnect substrate having a plurality of electrically isolated conductive traces extending in the x-direction on a first ...

Display apparatus and method of manufacturing the same

A display apparatus includes a display panel including a lower base substrate and a connecting portion disposed on the lower base substrate, a flexible circuit board attached on a side surface of the display panel, and including a base film and a conductive pattern disposed on the base film, a conductive paste part disposed between the side surface of the display panel and the flexible circuit board, a first anisotropic conductive film (ACF) film disposed between the side surface of the display panel and the conductive paste part, and a second ACF film disposed between the conductive paste part and the flexible circuit board. The connecting portion is exposed at the side surface of the display panel, and the first ACF film directly makes contact with the connecting portion.

Electromagnetic interference shield created on package using high throughput additive manufacturing

A device package and a method of forming the device package are described. The device package includes a substrate having a ground plane and dies disposed on the substrate. The dies are electrically coupled to the substrate with solder balls or bumps surrounded by an underfill layer. The device package has a mold layer disposed over and around the dies, the underfill layer, and the substrate. The device package further includes an additively manufactured electromagnetic interference (EMI) shield layer disposed on an outer surface of the mold layer. The additively manufactured EMI shield layer is electrically coupled to the ground plane of the substrate. The outer surface of the mold layer may include a topmost surface and one or more sidewalls that are covered with the additively manufactured EMI shield layer. The additively manufactured EMI shield may include a first and second additively manufactured EMI shield layers and an additively manufactured EMI shield frame.

Sealed semiconductor light emitting device

A light-emitting device is described herein. The device includes a semiconductor structure comprising a III-nitride light emitting layer disposed between an n-type region and a p-type region. The device also includes a metal layer with openings formed therein and filled with an insulating material. The openings separate the metal layer into a first portion that is electrically isolated from a second portion. The first portion is coupled to the n-type region and the second portion coupled to the p-type region. The device also includes conductive stacks. A first surface of each of the conductive stacks contacts a surface of the metal layer opposite the semiconductor structure. A respective gap is positioned between each of the conductive stacks. A body is in direct contact with a second surface of each of the conductive stacks that is opposite the first surface.

System and Method for Immersion Bonding

A representative system and method for manufacturing stacked semiconductor devices includes disposing an aqueous alkaline solution between a first semiconductor device and a second semiconductor device prior to bonding. In a representative implementation, first and second semiconductor devices may be hybrid bonded to one another, where dielectric features of the first semiconductor device are bonded to dielectric features of the second semiconductor device, and metal features of the first semiconductor device are bonded to metal features of the second semiconductor device. Immersion bonds so formed demonstrate a substantially lower incidence of delamination associated with bond defects. 1. A method of manufacturing a semiconductor device , the method comprising:submerge a first semiconductor die and a second semiconductor die in an aqueous solution; andwhile submerged, bonding the first semiconductor die to the second semiconductor die.2. The method of claim 1 , wherein the aqueous solution comprises deionized water.3. The method of claim 2 , wherein the aqueous solution has a pH of about 7.0.4. The method of claim 2 , wherein the aqueous solution has a pH greater than 7.0.5. The method of claim 4 , wherein the aqueous solution comprises hydroxide ion.6. The method of claim 1 , wherein:a first wafer comprises the first semiconductor die;immersing the first semiconductor die comprises immersing the first wafer in the aqueous solution; andbonding the first semiconductor die comprises bonding the first wafer to the second semiconductor die.7. The method of claim 6 , wherein:a second wafer comprises the second semiconductor die;immersing the second semiconductor die comprises immersing the second wafer in the aqueous solution; andbonding the first semiconductor die to the second semiconductor die comprises bonding the first wafer to the second wafer.8. The method of claim 1 , wherein the first semiconductor die and the second semiconductor die are immersed in one of a ...

Dielectric and metallic nanowire bond layers

In some examples, an electronic device comprises a first component having a surface, a second component having a surface, and a bond layer positioned between the surfaces of the first and second components to couple the first and second components to each other. The bond layer includes a set of metallic nanowires and a dielectric portion. The dielectric portion comprises a polymer matrix and dielectric nanoparticles.

HIGH-CONDUCTIVITY BONDING OF METAL NANOWIRE ARRAYS

A thermally-conductive and mechanically-robust bonding method for attaching a metal nanowire (MNW) array to an adjacent surface includes the steps of: removing a template membrane from the MNW; infiltrating the MNW with a bonding material; placing the bonding material on the adjacent surface; bringing an adjacent surface into contact with a top surface of the MNW while the bonding material is bondable; and allowing the bonding material to cool and form a solid bond between the MNW and the adjacent surface. A thermally-conductive and mechanically-robust bonding method for attaching a metal nanowire (MNW) array to an adjacent surface includes the steps of: choosing a bonding material based on a desired bonding process; and without removing the MNW from a template membrane that fills an interstitial volume of the MNW, depositing the bonding material onto a tip of the MNW. 1. A thermally-conductive and mechanically-robust bonding method for attaching a metal nanowire (MNW) array to an adjacent surface , comprising the steps of:removing a template membrane from the MNW;infiltrating the MNW with a bonding material;placing the bonding material on the adjacent surface;bringing an adjacent surface into contact with a top surface of the MNW while the bonding material is bondable; andallowing the bonding material to form a solid bond between the MNW and the adjacent surface.2. The method of claim 1 , further comprising an additional step claim 1 , performed after the placing step and before the bringing step claim 1 , of:wetting the bonding material to the adjacent surface.3. The method of claim 1 , wherein the step of infiltrating comprises heating the bonding material so that it becomes one or more of softened and molten.4. The method of claim 1 , wherein the step of infiltrating comprises chemically treating a composite material so as to create a bonding material.5. The method of claim 1 , wherein the step of bringing comprises bringing the adjacent surface into contact ...

SEMICONDUCTOR DEVICE

A semiconductor device includes an insulative substrate, a wiring pattern, a bonding portion, and a semiconductor element. The wiring pattern is formed on an upper surface of the insulative substrate. The bonding portion is formed on an upper surface of the wiring pattern. The semiconductor element includes an electrode pad connected to an upper surface of the bonding portion. The bonding portion includes first sintered layers distributed in the bonding portion and a second sintered layer having a density differing from each of the first sintered layers and surrounding the first sintered layer. 1. A semiconductor device , comprising:an insulative substrate;a wiring pattern formed on an upper surface of the insulative substrate;a bonding portion formed on an upper surface of the wiring pattern; anda semiconductor element that includes an electrode pad bonded to an upper surface of the bonding portion, wherein first sintered layers distributed in the bonding portion, and', 'a second sintered layer having a density differing from that of each of the first sintered layers and surrounding the first sintered layers., 'the bonding portion includes'}2. The semiconductor device according to claim 1 , whereinthe first sintered layers are formed on the upper surface of the wiring pattern, andthe second sintered layer is formed on the upper surface of the wiring pattern to cover an upper surface and a side surface of each of the first sintered layers.3. The semiconductor device according to claim 1 , wherein the bonding portion has a sea-island structure in which the second sintered layer forms a sea portion and the first sintered layers form island portions.4. The semiconductor device according to claim 1 , whereinthe first sintered layers and the second sintered layer are formed from the same material, andeach of the first sintered layers has a higher density than the second sintered layer.5. The semiconductor device according to claim 1 , wherein the first sintered layers ...

用于浸润接合的系统及方法

本发明实施例提供用于浸润接合的系统及方法。本发明实施例涉及一种用于制造堆叠半导体装置的代表性系统及方法，其包含在接合之前将水性碱溶液放置于第一半导体装置与第二半导体装置之间。在代表性实施方案中，第一半导体装置及第二半导体装置可彼此混合接合，其中所述第一半导体装置的电介质构件接合到所述第二半导体装置的电介质构件，且所述第一半导体装置的金属构件接合到所述第二半导体装置的金属构件。如此形成的浸润接合证实与接合缺陷相关联的大体上较低脱层发生率。

Anisotropic conductive film, method for producing anisotropic conductive film, method for producing connection body, and connection method

본 발명은 이방성 도전 필름을 사용한 접속에 있어서, 접속 후의 기판 휨의 저감을 도모하는 것을 목적으로 한다. 이방성 도전 필름(23)은 제1 절연성 접착제층(30)과, 제2 절연성 접착제층(31)과, 제1 절연성 접착제층(30) 및 제2 절연성 접착제층(31)에 끼움 지지되고, 도전성 입자(32)가 절연성 접착제(33)에 함유된 도전성 입자 함유층(34)을 갖고, 도전성 입자 함유층(34)과 제1 절연성 접착제층(30) 사이에 기포(41)가 함유되고, 도전성 입자 함유층(34)은 제2 절연성 접착제층(31)과 접하는, 도전성 입자(32)의 하부의 경화도가 다른 부위의 경화도보다도 낮은 것이다. This invention aims at reducing the board curvature after a connection in the connection using an anisotropic conductive film. The anisotropic conductive film 23 is sandwiched between the first insulating adhesive layer 30, the second insulating adhesive layer 31, the first insulating adhesive layer 30 and the second insulating adhesive layer 31, and is electrically conductive. The particle 32 has the electroconductive particle containing layer 34 contained in the insulating adhesive 33, the bubble 41 is contained between the electroconductive particle containing layer 34 and the 1st insulating adhesive layer 30, and an electroconductive particle containing layer Reference numeral 34 has a lower degree of curing of the lower portion of the conductive particles 32 in contact with the second insulating adhesive layer 31 than that of other portions.

Semiconductor device and fabrication method for semiconductor device

(과제) 반도체 장치에 있어서의 다이 본드의 신뢰성을 향상하는 것을 목적으로 하고 있다. (해결 수단) 이면측에 메탈리제이션층이 형성되어 있는 반도체 소자와, 반도체 소자와 간격을 두고 평행하게 배치된 금속제의 리드 프레임과, 반도체 소자와 리드 프레임의 사이에 마련되어, 메탈리제이션층에 접합되어 있는 제 1 접합층과, 반도체 소자와 리드 프레임의 사이에 마련되어, 제 1 접합층과 리드 프레임을 접합하는 제 2 접합층을 구비하고 있는 반도체 장치이다. 제 1 접합층은, 리드 프레임을 향해 중앙부가 부풀어져 있다. An object of the present invention is to improve the reliability of a die bond in a semiconductor device. A semiconductor device comprising: a semiconductor element having a metallization layer formed on its back side; a leadframe made of metal disposed in parallel with the semiconductor element so as to be spaced from the semiconductor element; And a second bonding layer provided between the semiconductor element and the lead frame to bond the first bonding layer and the lead frame. The first bonding layer is bulged at the center toward the lead frame.

Method and device for mounting electronic component on circuit board

IC칩(1)을 회로기판(4)에 구성요소를 배치하고 접속하는 경우에, IC칩상의 전극(2)에 범프(3)를 형성하고, 절연성의 도전입자가 없는 열경화성 수지(6)를 회로기판의 전극과 범프 사이에 개재시키면서 범프와 회로기판이 전극의 위치를 맞추어, 가열된 헤드(8)에 의하여 IC칩을 회로기판에 1 범프당 20gf 이상의 가압력으로 가압하여, IC칩 및 기판의 휨을 교정하면서, IC칩과 회로기판 사이에 개재하는 수지를 경화하여, IC칩과 회로기판을 접합한다. In the case where the IC chip 1 is disposed and connected to the circuit board 4, the bumps 3 are formed on the electrodes 2 on the IC chip, and the thermosetting resin 6 without insulating conductive particles is formed. The bumps and the circuit boards are positioned between the electrodes and the bumps of the circuit board while the electrodes are positioned so as to press the IC chip to a circuit board with a pressing force of 20 gf or more per bump by the heated head 8, thereby While correcting the warpage, the resin interposed between the IC chip and the circuit board is cured to join the IC chip and the circuit board.

電気部品および機械部品を接合するための複合物および複層銀膜

Semiconductor device

本发明的目的是提高半导体装置中的贴片的可靠性。本发明的半导体装置具有：在背面侧形成了金属镀层的半导体元件、与半导体元件隔开间隔并平行配置着的金属制的引线框架、设在半导体元件与引线框架之间并接合在金属镀层上的第1接合层、和设在半导体元件与引线框架之间并将第1接合层和引线框架接合的第2接合层。第1接合层的中央部朝着引线框架鼓出。

Anisotropic conductive film and method for manufacturing the same

본 발명의 일 실시예는 베이스 필름, 상기 베이스 필름상에 배치되며 개구부를 갖는 지지부, 상기 개구부에 배치된 적어도 하나의 도전 입자 및 상기 지지부 및 상기 도전 입자상에 배치된 점착층;을 포함하는 이방성 도전 필름(anisotropic conductive film, ACF)을 제공한다. One embodiment of the present invention is an anisotropic conductive comprising: a base film, a support portion disposed on the base film and having an opening, at least one conductive particle disposed in the opening, and an adhesive layer disposed on the support portion and the conductive particle Anisotropic conductive film (ACF) is provided.

C-SAM joint wafer seal composition and preparation method thereof

本发明涉及一种C-SAM中接合晶圆的密封结构及其制备方法，所述密封结构位于所述接合晶圆的边缘，将位于所述密封结构内侧的所述接合晶圆形成密封区域，以防止C-SAM检测中所述接合晶圆的间隙进水；其中，所述接合晶圆包括相互接合的上部接合晶圆和下部接合晶圆。本发明的优点在于：（1）所述接合晶圆边缘上设置的密封结构可以在C-SAM检测过程中将水封锁在晶圆之外。（2）可以根据预先设定的检测方法选用C-SAM对所述晶圆接合质量进行检测。（3）所述晶圆在C-SAM检测之后不会受到损坏。

Composite and multilayered silver films for joining electrical and mechanical components

향상된 성능을 위해, 본 발명의 실버 소결 필름 등의 다이 부착용 재료는 보강, 변형 입자를 포함할 수 있다. 다이 부착을 위한 방법은 이러한 재료를 포함할 수 있다. For improved performance, the die attach material, such as the silver sintered film of the present invention, may include reinforcing, deformable particles. Methods for die attach can include such materials.

Semiconductor device and manufacturing method

반도체 칩의 사이즈를 축소화하는 것이 가능한 기술을 제공한다. Provided is a technique capable of reducing the size of a semiconductor chip. 우선, 절연막(9)위로 패드(10) 및 패드이외의 배선(11a, 11b)을 실장한다. 이 패드(10) 및 배선(11a, 11b) 상을 포함하는 절연막(9)위로 표면보호막(12)을 형성하고, 표면보호막(12)에 개구부(13)를 실장한다. 개구부(13)는 패드(10)위로 형성되고 있어, 패드(10)의 표면을 노출한다. 이 개구부(13)를 포함하는 표면보호막(12)위로 범프전극(8)을 형성한다. 여기에서, 범프전극(8)의 크기와 비교해서 패드(10)의 크기를 충분히 작아지도록 구성한다. 이것에 의해, 범프전극(8)의 바로 밑이며, 패드(10)와 동일한 층에 배선(11a, 11b)이 배치되도록 한다. 즉, 패드(10)를 작게 하는 것에 의해 형성된 범프전극(8)하의 스페이스에 배선(11a, 11b)을 배치한다. First, the pad 10 and the wirings 11a and 11b other than the pad are mounted on the insulating film 9. The surface protection film 12 is formed on the insulating film 9 including the pad 10 and the wirings 11a and 11b, and the opening 13 is mounted in the surface protection film 12. The opening 13 is formed on the pad 10 to expose the surface of the pad 10. The bump electrode 8 is formed on the surface protective film 12 including the opening 13. Here, the size of the pad 10 is made sufficiently small as compared with the size of the bump electrode 8. As a result, the wirings 11a and 11b are arranged on the same layer as the pad 10 just under the bump electrode 8. That is, the wirings 11a and 11b are arranged in the space under the bump electrode 8 formed by reducing the pad 10. 범프전극, 표면보호막, 절연부 Bump electrode, surface protection film, insulation

Highly heat-conductive composite magnetic material

연자성 분말을 유기결합제중에 분산시켜 이루어지며 전자간섭억제효과를 가지는 복합자성체에 있어서, 유기결합제중에 열전도성이 양호한 분말을 분산하여, 열전도성이 우수한 복합자성체를 제공한다. 상기 복합자성체는, 전자기기의 방열용 시트로서 겸용할 수 있다. 또한, 전자간섭억제효과를 갖는 히트싱크를 구성할 수도 있다. 유기결합제로는, 열가소성 폴리이미드, 액정 폴리머를 들 수 있고, 열전도성이 양호한 분말로는, 알루미나(Al 2 O 3 ), 질화 알루미늄(AlN), 입방정(立方晶) 질화 붕소(BN), 절연성 탄화규소(SiC), 열 전도성 강화재(캡톤)를 들 수 있다. In a composite magnetic body obtained by dispersing a soft magnetic powder in an organic binder and having an electron interference inhibitory effect, a powder having good thermal conductivity is dispersed in the organic binder, thereby providing a composite magnetic body having excellent thermal conductivity. The composite magnetic body can be used as a heat dissipation sheet of an electronic device. Moreover, the heat sink which has an electron interference suppression effect can also be comprised. Examples of the organic binder include thermoplastic polyimide and liquid crystal polymer, and powders having good thermal conductivity include alumina (Al 2 O 3 ), aluminum nitride (AlN), cubic boron nitride (BN), and insulating properties. Silicon carbide (SiC) and a thermally conductive reinforcing material (kapton).

Thermal interface material and its forming method

여기에서는, 기재 상에 카본 나노 튜브들과 금속 나노 분말을 포함하는 예비 소결층을 형성하는 단계와, 상기 예비 소결층 상에 반도체칩을 배치하는 단계와, 카본 나노 튜브들과 금속 나노 분말로 된 열계면 재료를 얻도록, 상기 예비 소결층을 상기 금속 나노 분말의 소결 온도로 열처리하는 단계를 포함하는 반도체칩용 열계면 재료 형성방법이 개시된다. The method includes the steps of forming a pre-sintered layer containing carbon nanotubes and a metal nano powder on a substrate, disposing a semiconductor chip on the pre-sintered layer, and separating the carbon nanotubes and the metal nano- A method of forming a thermal interface material for a semiconductor chip comprising the step of heat treating the pre-sintered layer to a sintering temperature of the metal nano powder to obtain a thermal interface material. 기재, 카본 나노 튜브, 금속 나노 분말, 반도체칩, 발광다이오드칩, 기재 Substrate, carbon nanotube, metal nano powder, semiconductor chip, light emitting diode chip, substrate

Anisotropic conductive film and its preparation method, connector and its preparation method and connection method

本发明目的在于在利用各向异性导电膜的连接中，谋求降低连接后的基板翘曲。各向异性导电膜（23）包括：第1绝缘性粘接剂层（30）；第2绝缘性粘接剂层（31）；以及被第1绝缘性粘接剂层（30）及第2绝缘性粘接剂层（31）挟持并在绝缘性粘接剂（33）含有导电性粒子（32）的含导电性粒子层（34），在含导电性粒子层（34）与第1绝缘性粘接剂层（30）之间含有气泡（41），含导电性粒子层（34）中，与第2绝缘性粘接剂层（31）相接的导电性粒子（32）的下部的硬化度低于其他部位的硬化度。

A semiconductor device

반도체 칩의 사이즈를 축소화하는 것이 가능한 기술을 제공한다. 우선, 절연막(9)위로 패드(10) 및 패드이외의 배선(11a, 11b)을 실장한다. 이 패드(10) 및 배선(11a, 11b) 상을 포함하는 절연막(9)위로 표면보호막(12)을 형성하고, 표면보호막(12)에 개구부(13)를 실장한다. 개구부(13)는 패드(10)위로 형성되고 있어, 패드(10)의 표면을 노출한다. 이 개구부(13)를 포함하는 표면보호막(12)위로 범프전극(8)을 형성한다. 여기에서, 범프전극(8)의 크기와 비교해서 패드(10)의 크기를 충분히 작아지도록 구성한다. 이것에 의해, 범프전극(8)의 바로 밑이며, 패드(10)와 동일한 층에 배선(11a, 11b)이 배치되도록 한다. 즉, 패드(10)를 작게 하는 것에 의해 형성된 범프전극(8)하의 스페이스에 배선(11a, 11b)을 배치한다. 범프전극, 표면보호막, 절연부

Semiconductor package and method for manufacturing the same

본 발명은 반도체 장치 및 그 제조 방법에 관한 것으로서, 더욱 상세하게는 기판에 탑재된 반도체 칩과 그 위에 적층되는 열방출용 리드(lid) 간의 접착 고정력을 향상시켜 열방출 성능의 신뢰성을 향상시킬 수 있도록 한 반도체 장치 및 그 제조 방법에 관한 것이다. 즉, 본 발명은 기판에 탑재된 반도체 칩의 상면에 걸쳐 열전달 효과가 우수한 서멀 인터페이스 재료를 도포하되, 반도체 칩의 일부 영역에 접착력이 우수한 어드헤시브 인터페이스 재료를 도포하여 반도체 칩의 상면에 적층되는 열방출용 리드(lid)가 견고한 접착 고정상태를 유지할 수 있도록 함으로써, 열방출 성능의 신뢰성을 향상시킬 수 있도록 한 반도체 장치 및 그 제조 방법을 제공하고자 한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to improve adhesive fixation force between a semiconductor chip mounted on a substrate and a heat dissipation lid stacked thereon, thereby improving reliability of heat dissipation performance. The present invention relates to a semiconductor device and a method of manufacturing the same. That is, the present invention applies a thermal interface material having excellent heat transfer effect over the upper surface of the semiconductor chip mounted on the substrate, but is deposited on the upper surface of the semiconductor chip by applying an aggressive interface material having excellent adhesion to a portion of the semiconductor chip It is an object of the present invention to provide a semiconductor device and a method of manufacturing the same, which can improve the reliability of the heat dissipation performance by allowing the heat dissipation lid to maintain a firm adhesive fixing state.

Semiconductor device and method of manufacturing a semiconductor device

Halbleitervorrichtung, die Folgendes aufweist: – ein Halbleiterelement (1), bei dem eine Metallisierungsschicht (2) auf der Rückseite gebildet ist; – einen metallischen Leiterrahmen (4), der parallel zu dem Halbleiterelement (1) und in einem Abstand von diesem angeordnet ist; – eine erste Bondverbindungsschicht (3), die zwischen dem Halbleiterelement (1) und dem Leiterrahmen (4) vorgesehen ist und an die Metallisierungsschicht (2) gebondet ist; und – eine zweite Bondverbindungsschicht (6), die zwischen dem Halbleiterelement (1) und dem Leiterrahmen (4) vorgesehen ist und die erste Bondverbindungsschicht (3) an den Leiterrahmen (4) bondet, – wobei die erste Bondverbindungsschicht (3) in einem zentralen Bereich in Richtung auf den Leiterrahmen (4) erweitert ist und einen höheren Schmelzpunkt aufweist als die zweite Bondverbindungsschicht (6). A semiconductor device comprising: - a semiconductor element (1) in which a metallization layer (2) is formed on the back surface; - A metallic lead frame (4), which is arranged parallel to the semiconductor element (1) and at a distance from this; A first bonding layer (3) provided between the semiconductor element (1) and the lead frame (4) and bonded to the metallization layer (2); and a second bonding layer (6) provided between the semiconductor element (1) and the lead frame (4) and bonding the first bonding layer (3) to the lead frame (4), the first bonding layer (3) being in a central one Area is widened toward the lead frame (4) and has a higher melting point than the second bonding layer (6).

Establishing method of semiconductor device

내용 없음.

Composite and multilayered silver films for joining electrical and mechanical components

향상된 성능을 위해, 본 발명의 실버 소결 필름 등의 다이 부착용 재료는 보강, 변형 입자를 포함할 수 있다. 다이 부착을 위한 방법은 이러한 재료를 포함할 수 있다.

Mounting method and the device and anisotropic conductive sheet

(57)【要約】 【課題】本発明は、例えばフリップチップなどの半導体 装置を基板に実装する実装方法及びその装置及び異方性 導電材に関する。 【解決手段】本発明の実装方法は、複数のバンプ電極を 有する電子部品を基板上に形成された複数の配線端子に 接続する実装方法において、前記配線端子を包含する前 記基板上の領域に異方性導電膜を被着する異方性導電膜 被着工程と、前記異方性導電膜を囲繞する前記基板上の 領域及び前記異方性導電膜上の領域に導電性を有しない 絶縁性樹脂膜を被着する絶縁性樹脂膜被着工程と、ツー ルにより前記電子部品を前記基板に対して加熱加圧し前 記異方性導電膜を介して前記バンプ電極を前記配線端子 に接続する圧着工程とを具備する。

Composite connection of two components

The invention relates to a method for connecting a first component (2) to a second component (3), having the steps of: a) providing a plurality of nanowires (1) on a contact surface (4) of the first component (2), b) applying an adhesive (6) onto the contact surface (4) of the first component (2) and/or a contact surface (5) of the second component (3), and c) bringing together the first component (2) and the second component (3) such that the plurality of nanowires (1) are brought into contact with the contact surface (5) of the second component (3) and the contact surfaces (4, 5) are connected together by the adhesive (6). At least some of the nanowires (1) can be in contact with the adhesive (6) after forming the connection. Intermediate spaces between the nanowires (1) can be filled with the adhesive (6). Alternatively, the nanowires (1) are arranged in a first region, and the adhesive (6) can be arranged in a second region adjoining the first region or at a distance from the first region, wherein the second region can surround the first region. The adhesive (6) can be liquid upon being applied in step b). In step a), a plurality of nanowires (1) can additionally be provided on the contact surface (5) of the second component (3), said components (2, 3) being brought together in step c) such that the nanowires (1) on the contact surface (5) of the second component (3) are brought into contact with the contact surface (4) of the first component (2). In step c), at least the contact surface (5) of the second component (3) can be heated to a temperature of at least 90 °C and/or maximally 270 °C and/or the first component (2) and the second component (3) are pressed against each other with a pressure of at least 2 MPa and/or maximally 200 MPa. The contact surfaces (4, 5) can be connected together in an electrically and/or thermally conductive manner by means of the nanowires (1). The first component (2) and the second component (3) can be electronic components, such ...

ASSEMBLING A CHIP OF INTEGRATED CIRCUITS AND A PLATE

L'invention concerne un assemblage d'une puce (3) de circuits intégrés et d'une plaque (5), dans lequel au moins un canal (15) disposé entre la puce et la plaque s'étend d'un bord à un autre bord de la plus petite de la puce ou de la plaque, et est délimité par des parois latérales métalliques (17) s'étendant au moins partiellement d'une face de la puce à une face en regard de la plaque.

METHOD FOR CONNECTING PLANED SURFACES BY USING PASTY STATE ADHESIVE SUBSTANCES OR IN THE FORM OF NON-DRY FILM

CE PROCEDE POUR LIER DEUX SURFACES UTILISE UNE TOILE PREFORMEE 20 QUI PROCURE LA FORCE D'ADHERENCE TOUT EN ELIMINANT LES PROBLEMES QUE POSENT HABITUELLEMENT LES MANQUES ET LES EXCEDENTS DE SUBSTANCE ADHESIVE. ON PEUT REUNIR AINSI UNE TOILE PREFORMEE 20, UNSUBSTRAT MICROELECTRONIQUE 10 PORTEUR D'UN CIRCUIT ELECTRONIQUE ET UN BLOC CERAMIQUE OU METALLIQUE 40, GRACE A UNE COUCHE D'ADHESIF 14, EN SUPPRIMANT LES INCONVENIENTS DUS AUX EXCEDENTS ET AUX MANQUES D'ADHESIF QUI NUISENT A LA DISSIPATION DE LA CHALEUR PAR CONDUCTIBILITE THERMIQUE, AFIN D'OBTENIR UNE MEILLEURE STABILITE DES PARAMETRES ELECTRONIQUES. APPLICATION AUX CIRCUITS INTEGRES ET AUTRES COMPOSANTS ELECTRONIQUES EN GENERAL. THIS PROCESS FOR BINDING TWO SURFACES USES A PREFORMED CANVAS 20 WHICH PROVIDES THE STRENGTH OF ADHESION WHILE ELIMINING THE PROBLEMS USUALLY CAUSED BY LACKS AND EXCESSES OF ADHESIVE SUBSTANCE. A PREFORMED CANVAS 20, A MICROELECTRONIC SUBSTRATE 10 CARRYING AN ELECTRONIC CIRCUIT AND A CERAMIC OR METAL BLOCK 40, THANKS TO A LAYER OF ADHESIVE 14, REMOVING THE DISADVANTAGES DUE TO SURPLUS AND LACK OF ADHESIVE THAT HARMFUL TO THE DISSIPATION OF HEAT BY THERMAL CONDUCTIBILITY, IN ORDER TO OBTAIN BETTER STABILITY OF THE ELECTRONIC PARAMETERS. APPLICATION TO INTEGRATED CIRCUITS AND OTHER ELECTRONIC COMPONENTS IN GENERAL.

Semiconductor device

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Conductive connection material and connection method between terminals using the same

The present invention provides a conductive connecting material having a multilayered structure comprising a resin composition (A) and a metal foil (B) selected from a solder foil or a tin foil, wherein the volume ratio ((A)/(B)) of the resin composition (A) and the metal foil (B) selected from a solder foil or a tin foil in the conductive connecting material is 1-40 or 20-500, as well as a method for connecting terminals using the conductive connecting material. The conductive connecting material of the present invention is preferably used for electrically connecting electronic members in an electrical or electronic component.

The method for engaging substrate

披露了一种接合基板的方法、使用此方法形成组件的方法，以及整修这些组件的改良方法，这些方法利用在用于结合两个基板的粘结剂中形成的至少一个沟道来改良组件的制造、性能和整修。在一个实施方式中，组件包括通过粘结层固定至第二基板的第一基板。所述组件包括沟道，所述沟道具有由粘结层界定的至少一侧并且具有暴露于组件的外部的出口。

Electrically connected fields of active components in transfer printing technology

Ein aktives Bauteilfeld enthält ein Ziel-Substrat, welches ein oder mehrere Kontakte hat, welche auf einer Seite des Ziel-Substrats ausgebildet sind, und ein oder mehrere bedruckbare aktive Bauteile, welche über dem Ziel-Substrat verteilt sind. Jedes aktive Bauteil enthält eine aktive Schicht, welche eine Oberseite und eine gegenüberliegende Unterseite hat, und ein oder mehrere aktive Elemente, welche auf oder in der Oberseite der aktiven Schicht ausgebildet sind. Das aktive Element bzw. die aktiven Elemente sind elektrisch mit dem Kontakt bzw. den Kontakten verbunden, und die Unterseite ist am Ziel-Substrat angeklebt. Es sind ebenso zugehörige Herstellungsverfahren diskutiert. An active device array includes a target substrate having one or more contacts formed on one side of the target substrate and one or more printable active devices distributed over the target substrate. Each active device includes an active layer having a top and an opposite bottom, and one or more active elements formed on or in the top of the active layer. The active element (s) are electrically connected to the contact (s), and the bottom surface is adhered to the target substrate. There are also discussed related manufacturing methods.

Packaging structure and method for manufacturing packaging structure

Device mounting a semiconductor element on a wiring substrate including an adhesive material having first and second adhesive components with different cure characteristics

Two kinds of first and second adhesive components 8a, 8b are used to a joining treatment for connecting a protruded electrode 6 of a semiconductor element 5 and a substrate wiring 3 of a wiring substrate 1. The first adhesive component 8a is at a central portion on the surface of the semiconductor element 5 to be joined with the wiring substrate, in which the first adhesive component 8a is formed, and the second adhesive component 8b is disposed in a region at the periphery thereof having the protruded electrode 6. Further, the cure-shrinkage of the first adhesive component 8a is made greater than that of the second adhesive resin 8b and the modulus of elasticity of the second adhesive component 8b is made greater than that of the first adhesive component 8a such that the thermal expansion of the second adhesive component 8b in the high temperature circumference does not exceeds the cure-shrinkage during curing of the first adhesive 8a. Further, the curing temperature of the first adhesive component is made lower than that of the second adhesive component.

Sintered compound starting material and method for producing the sintered compound

Der erfindungsgemäße Ausgangswerkstoff einer Sinterverbindung umfasst Partikel, die zumindest anteilig eine organische Metallverbindung und/oder ein Edelmetalloxid enthalten, wobei die organische Metallverbindung und/oder das Edelmetalloxid bei einer Temperaturbehandlung des Ausgangswerkstoffes in das elementare Metall und/oder Edelmetall umgewandelt wird. Kennzeichnend für die Erfindung ist, dass die Partikel eine Beschichtung enthaltend ein Reduktionsmittel aufweisen, mittels welchem die Reduktion der organischen Metallverbindung und/oder des Edelmetalloxids zu dem elementaren Metall und/oder Edelmetall bei einer Temperatur unterhalb der Sintertemperatur des elementaren Metalls und/oder Edelmetalls erfolgt. The starting material of a sintered compound according to the invention comprises particles which at least partially contain an organic metal compound and / or a noble metal oxide, the organic metal compound and / or the noble metal oxide being converted into the elemental metal and / or noble metal during a temperature treatment of the starting material. It is characteristic of the invention that the particles have a coating containing a reducing agent, by means of which the reduction of the organic metal compound and / or the noble metal oxide to the elemental metal and / or noble metal takes place at a temperature below the sintering temperature of the elemental metal and / or noble metal .

Soldering system for heavy-duty semiconductor circuit uses spray of solder droplets in stream of hot gas to build up deposit of solder on area to be soldered

Verfahren zum Aufbringen eines Lotdepots für eine Lötverbindung an einem Leistungshalbleiter oder Leistungshalbleitersubstrat, mit einem Aufspritzen von Partikeln in einem Strom heißen Gases auf wenigstens Teilbereiche des zur Bildung des Lotdepots bestimmten Gebietes, wobei die Temperatur des Gases nicht mehr als die Schmelztemperatur der Partikel beträgt.

Process for connecting components in the manufacture of power electronic modules or assemblies

Bei einem Verfahren zur Verbindung von Komponenten bei der Herstellung leistungselektronischer Module oder Baugruppen werden zu verbindende Flächen der Komponenten mit einer metallischen Oberflächenschicht bereitgestellt oder versehen, die eine für direktes Bonden ausreichend glatte Oberfläche aufweist oder geglättet wird, um eine für direktes Bonden ausreichend glatte Oberfläche zu erhalten. Die Oberflächenschichten der zu verbindenden Flächen werden dann mit einem Druck von mindestens 5 MPa bei erhöhter Temperatur gegeneinander gepresst, so dass sie sich unter Bildung einer einzigen Schicht miteinander verbinden. Das Verfahren ermöglicht eine einfache und schnelle Verbindung auch von größeren Kontaktflächen, die den hohen Anforderungen leistungselektronischer Module genügt. In a method for connecting components in the manufacture of power electronic modules or assemblies, surfaces of the components to be connected are provided or provided with a metallic surface layer which has a surface that is sufficiently smooth for direct bonding or is smoothed to produce a surface that is sufficiently smooth for direct bonding obtain. The surface layers of the surfaces to be connected are then pressed against one another with a pressure of at least 5 MPa at an elevated temperature, so that they connect to one another to form a single layer. The process enables a simple and quick connection, even of larger contact areas, which meets the high requirements of power electronic modules.

Conductive connection material and terminal-to-terminal connection method using same

본 발명은, 수지 조성물과 땜납박 또는 주석박에서 선택되는 금속박으로 구성되는 적층 구조를 갖는 도전 접속 재료로서, 상기 도전 접속 재료에 있어서의 수지 조성물 (A) 와 땜납박 또는 주석박에서 선택되는 금속박 (B) 의 체적비 ((A)/(B)) 가 1 ∼ 40 또는 20 ∼ 500 인 것을 특징으로 하는 도전 접속 재료 및 그 도전 접속 재료를 사용한 단자 사이의 접속 방법을 제공한다. 본 발명의 도전 접속 재료는, 전기, 전자 부품 등에 있어서 전자 부재의 접속 단자 사이를 전기적으로 접속시키기 위해 바람직하게 사용된다.

Microstructure, and method for production thereof

本发明提供了一种微细结构体，所述微细结构体具有优异的长期稳定性，并且能够通过热压结合以高的接合强度简单接合。所述微细结构体包含绝缘基底，所述绝缘基底具有密度为1×10 6 至1×10 10 个微孔/mm 2 的各自具有10至500nm的孔径的贯通微孔。在每个贯通微孔内以30％以上的填充率填充金属。在所述绝缘基底材料的至少一个表面上设置了包含聚合物的层。

Insulating sheet and method for producing it, and power module comprising the insulating sheet

An insulating sheet includes an adhesive component of essentially a thermosetting resin and a filler member infiltrated into the component. Heat conductivity of an adhesive face region of the insulating sheet is smaller than heat conductivity of an inner region, other than the adhesive face region of the insulating sheet.

Sealed semiconductor light emitting device

A method according embodiments of the invention includes providing a wafer of semiconductor devices. The wafer of semiconductor devices includes a semiconductor structure comprising a light emitting layer sandwiched between an n-type region and a p-type region. The wafer of semiconductor devices further includes first and second metal contacts for each semiconductor device. Each first metal contact is in direct contact with the n-type region and each second metal contact is in direct contact with the p-type region. The method further includes forming a structure that seals the semiconductor structure of each semiconductor device. The wafer of semiconductor devices is attached to a wafer of support substrates.

Semiconductor package inhibiting viscous material spread

A semiconductor package includes spread inhibiting structure to constrain the movement of viscous material during fabrication. In some embodiments, the spread inhibiting structure comprises a recess in an underside of a package lid overlying the die. According to other embodiments, the spread inhibiting structure comprises polymer disposed on the lid underside proximate to a side of the packaged die. According to still other embodiments, the spread inhibiting structure comprises a polymer disposed around the top of the die to serve as a dam and contain spreading. In some embodiments, the viscous material may be a Thermal Integration Material (TIM) in an uncured state, and the polymer may be the TIM in a cured state.

Electrically bonded arrays of transfer printed active components

An active component array includes a target substrate having one or more contacts formed on a side of the target substrate, and one or more printable active components distributed over the target substrate. Each active component includes an active layer having a top side and an opposing bottom side and one or more active element(s) formed on or in the top side of the active layer. The active element(s) are electrically connected to the contact(s), and the bottom side is adhered to the target substrate. Related fabrication methods are also discussed.

Member connection method

Stacked structures and methods of fabricating stacked structures

A method includes: forming a transistor gate over a first substrate and at least one first dummy structure within the first substrate; forming an interlayer dielectric (ILD) layer over the gate transistor, the ILD layer including at least one contact structure formed therein and making electrical contact with the transistor gate and at least one first conductive structure formed therethrough at least partially over a surface of the dummy structure; forming a passivation layer over the ILD layer, the passivation layer comprising at least one first pad structure formed therein and making electrical contact with the conductive structure; bonding the first substrate with a second substrate; removing at least a portion of the first dummy structure, thereby forming a first opening; and forming a conductive material within the first opening for formation of a second conductive structure, the second conductive structure being electrically coupled to the first conductive structure.

Thermal interface material with support structure

Various semiconductor chip thermal interface material methods and apparatus are disclosed. In one aspect, a method of establishing thermal contact between a first semiconductor chip and a heat spreader is provided. The method includes placing a thermal interface material layer containing a support structure on the first semiconductor chip. The heat spreader is positioned proximate the thermal interface material layer. The thermal interface material layer is reflowed to establish thermal contact with both the first semiconductor chip and the heat spreader.

Electronic package and method of forming the same

一些實施例係關於一種電子封裝。該電子封裝包括一第一晶粒及堆疊至該第一晶粒上之一第二晶粒。一第一封裝物配置於該第一晶粒與該第二晶粒之間。該第一封裝物包括覆蓋該第一晶粒與該第二晶粒之間的一第一體積之一第一材料。一第二封裝物配置於該第一晶粒與該第二晶粒之間。該第二封裝物包括覆蓋該第一晶粒與該第二晶粒之間的一第二體積之一第二材料。該第一材料具有比該第二材料高之一熱導率，且與該第一材料相比，該第二材料更有效地促進該第一晶粒與該第二晶粒之間的電氣連接。