Method for making circuit board

A method for making the same is disclosed. First, a first substrate and a second substrate are provided. The first substrate includes a release film attached to a carrier. The second substrate includes a copper film covered with a solder mask. Second, the solder masked is patterned. Next, the release film and the patterned solder mask are pressed together so that the first substrate is attached to the second substrate. Then, the copper film is patterned to form a first pattern and a second pattern. The first pattern is in direct contact with the release film and the second pattern is in direct contact with the patterned solder mask. Later, a passivation is formed to cover the first pattern and the second pattern to form a circuit board structure. Afterwards, a package is formed on the carrier to form a packaging structure.

Alloy wire and methods for manufacturing the same

An alloy wire made of a material selected from one of a group consisting of a silver-gold alloy, a silver-palladium alloy and a silver-gold-palladium alloy is provided. The alloy wire is with a polycrystalline structure of a face-centered cubic lattice and includes a plurality of grains. A central part of the alloy wire includes slender grains or equi-axial grains, and the other parts of the alloy wire consist of equi-axial grains. A quantity of the grains having annealing twins was 20 percent or more of the total quantity of the grains of the alloy wire.

Method for fabricating a through wire interconnect (twi) on a semiconductor substrate having a bonded connection and an encapsulating polymer layer

A method for fabricating a through wire interconnect for a semiconductor substrate having a substrate contact includes the steps of: forming a via through the semiconductor substrate from a first side to a second side thereof; placing a wire in the via having a first end with a bonded connection to the substrate contact and a second end proximate to the second side; forming a first contact on the wire proximate to the first side; forming a second contact on the second end of the wire; and forming a polymer layer on the first side at least partially encapsulating the wire while leaving the first contact exposed.

WIRE BONDING SYSTEMS AND RELATED METHODS

A wire bond system. Implementations may include: a bond wire including copper (Cu), a bond pad including aluminum (Al) and a sacrificial anode electrically coupled with the bond pad, where the sacrificial anode includes one or more elements having a standard electrode potential below a standard electrode potential of Al. 1. A method for forming a wire bond comprising:bonding a wire comprising Cu with a bond pad comprising an aluminum alloy; andelectrically coupling a sacrificial anode with the bond pad;wherein the sacrificial anode does not physically contact the bond pad.2. The method of claim 1 , wherein the sacrificial anode comprises one of Mg claim 1 , Hf claim 1 , Be claim 1 , or any combination thereof.3. A method of forming a wire bond comprising:physically and electrically coupling a sacrificial anode over at least a portion of a bond pad, wherein the bond pad comprises an aluminum alloy; andforming one of an alloy stack or an intermetallic layer by bonding a wire comprising Cu through the sacrificial anode and to the bond pad.4. The method of claim 3 , wherein the sacrificial anode comprises one of Mg claim 3 , Hf claim 3 , Be claim 3 , and any combination thereof.5. The method of claim 3 , wherein the sacrificial anode comprises W.6. The method of claim 3 , wherein the sacrificial anode comprises Zn.7. The method of claim 3 , wherein the sacrificial anode comprises Cr.8. The method of claim 3 , wherein the sacrificial anode comprises Sn.9. The method of claim 3 , wherein the sacrificial anode comprises one of Mo claim 3 , Cd claim 3 , Ni claim 3 , Co claim 3 , Fe claim 3 , Cu claim 3 , or any combination thereof.10. The method of claim 3 , wherein the sacrificial anode is entirely over the bond pad.11. A wire bond system comprising:a bond wire comprising Cu; anda bond pad coupled to the bond wire, the bond pad comprising a sacrificial anode.12. The system of claim 11 , wherein the sacrificial anode comprises W.13. The system of claim 11 , wherein the ...

Cu ALLOY CORE BONDING WIRE WITH Pd COATING FOR SEMICONDUCTOR DEVICE

A bonding wire for a semiconductor device includes a Cu alloy core material and a Pd coating layer formed on a surface thereof, and the boding wire contains one or more elements of As, Te, Sn, Sb, Bi and Se in a total amount of 0.1 to 100 ppm by mass. The bonding longevity of a ball bonded part can increase in a high-temperature and high-humidity environment, improving the bonding reliability. When the Cu alloy core material further contains one or more of Ni, Zn, Rh, In, Ir, Pt, Ga and Ge in an amount, for each, of 0.011 to 1.2% by mass, it is able to increase the reliability of a ball bonded part in a high-temperature environment of 170° C. or more. When an alloy skin layer containing Au and Pd is further formed on a surface of the Pd coating layer, wedge bondability improves.

CHIP PACKAGE AND METHOD OF FORMING A CHIP PACKAGE WITH A METAL CONTACT STRUCTURE AND PROTECTIVE LAYER, AND METHOD OF FORMING AN ELECTRICAL CONTACT

In various embodiments, a chip package is provided. The chip package may include a chip, a metal contact structure including a non-noble metal and electrically contacting the chip, a packaging material, and a protective layer including or essentially consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material, wherein the protective layer may include a noble metal, wherein the portion of the protective layer may include a plurality of regions free from the noble metal, and wherein the regions free from the noble metal may provide an interface between the packaging material and the non-noble metal of the metal contact structure. 1. A method of forming an electrical contact , comprising:arranging an intermediate layer on the metal surface;arranging a metal contact structure over or on a metal surface; andplating a metal layer on the metal surface and on the metal contact structure, thereby fixing the metal contact structure to the metal surface and forming an electrical contact between the metal contact structure and the metal surface or strengthening or thickening an existing electrical contact between the metal contact structure and the metal surface.2. The method of claim 1 , further comprising:before plating the metal layer on the metal surface and on the metal contact structure, treating the metal surface and the metal contact structure by a process involving wet chemistry, dry chemistry, and/or a plasma in order to prepare a surface of the metal surface and of the metal contact structure for the plating.3. The method of claim 1 , wherein the metal contact structure claim 1 , the metal surface and/or a metallization material comprises or consists of copper.4. The method of claim 1 , wherein the metal contact structure may contain or consist of the same metal as the metal surface.5. The method of claim 3 , wherein the metallization comprises a galvanic deposit or an electroless deposit.6. The method of ...

PROCESS FOR ELECTRICALLY CONNECTING CONTACT SURFACES OF ELECTRONIC COMPONENTS

A process for electrically connecting contact surfaces of electronic components by capillary wedge bonding a round wire of 8 to 80 μm to the contact surface of a first electronic component, forming a wire loop, and stitch bonding the wire to the contact surface of a second electronic component, wherein the wire comprises a wire core having a silver or silver-based wire core with a double-layered coating comprised of a 1 to 50 nm thick inner layer of nickel or palladium and an adjacent 5 to 200 nm thick outer layer of gold. 1. A process for electrically connecting a contact surface of a first electronic component with a contact surface of a second electronic component comprising the subsequent steps:(1) capillary wedge bonding a wire having a circular cross-section with an average diameter in the range of 8 to 80 μm to the contact surface of the first electronic component,(2) raising the capillary wedge bonded wire to form a wire loop between the capillary wedge bond formed in step (1) and the contact surface of the second electronic component, and(3) stitch bonding the wire to the contact surface of the second electronic component,wherein the capillary wedge bonding of step (1) is carried out with a ceramic capillary having a lower face angle within the range of from zero to 4 degrees,wherein the wire comprises a wire core with a surface, the wire core having a double-layered coating superimposed on its surface,wherein the wire core consists of a material selected from the group consisting of pure silver, doped silver with a silver content of >99.5 wt.-% and silver alloys with a silver content of at least 89 wt.-%, andwherein the double-layered coating comprises a 1 to 50 nm thick inner layer of nickel or palladium and an adjacent 5 to 200 nm thick outer layer of gold.2. The process of claim 1 , (a′) an ultrasonic energy in a range of 50 to 100 mA,', '(b′) a force in a range of 10 to 30 g,', '(c′) a constant velocity in a range of 0.3 to 0.7 μm/s,', '(d′) a contact ...

Method for manufacturing bonding wire and manufacturing apparatus thereof

A method for manufacturing a bonding wire includes: putting a surface layer metal of a bonding wire in a crucible having a die cooler provided at the lower part thereof and melting the same; putting a main component metal core of the bonding wire in a core guide located at the upper part of the die cooler of the crucible and heating the core guide to the melting point or below of the metal core; transferring the metal core toward the die cooler so as to allow the molten surface layer metal to be injected to the surface of the metal core; and manufacturing a 50 □m to 350 □m bonding wire from the cast wire precursor by using a drawing die.

Light emitting apparatus

A light emitting apparatus includes a positive lead terminal and a negative lead terminal, each of which includes a first main surface, a second main surface, and an end surface including a first recessed surface area extending from a first point of the first main surface in cross section, and a second recessed surface area extending from a second point of the second main surface in cross section. A distance between a first part of the end surface of the positive lead terminal and a second part of the end surface of the negative lead terminal than a first distance between the first points of the positive lead terminal and the negative lead terminal and a second distance between the second points of the positive lead terminal and the negative lead terminal. The first part and the second part are separated from the first point and the second point.

BONDING WIRE FOR SEMICONDUCTOR DEVICE

There is provided a bonding wire that improves bonding reliability of a ball bonded part and ball formability and is suitable for on-vehicle devices. 1. A bonding wire for a semiconductor device comprising:a Cu alloy core material; anda Pd coating layer formed on a surface of the Cu alloy core material, whereinthe Cu alloy core material contains Ni,a concentration of Ni is 0.1 to 1.2 wt. % relative to the entire wire, anda thickness of the Pd coating layer is 0.015 to 0.150 □m.2. The bonding wire for a semiconductor device according to claim 1 , further comprising an Au skin layer on the Pd coating layer.3. The bonding wire for a semiconductor device according to claim 2 , wherein a thickness of the Au skin layer is 0.0005 to 0.050 □m.4. The bonding wire for a semiconductor device according to claim 1 , whereinthe Cu alloy core material further contains at least one element selected from B, In, Ca, P and Ti, anda concentration of the elements is 3 to 100 wt. ppm relative to the entire wire.5. The bonding wire for a semiconductor device according to claim 1 , whereinthe Cu alloy core material further contains Pt or Pd, anda concentration of Pt or Pd contained in the Cu alloy core material is 0.05 to 1.20 wt. %.6. The bonding wire for a semiconductor device according to claim 1 , wherein Cu is present at an outermost surface of the bonding wire. The present invention relates to a bonding wire for a semiconductor device used to connect electrodes on a semiconductor device and wiring of a circuit wiring board such as external leads.As a bonding wire for a semiconductor device which connects electrodes on a semiconductor device and external leads (hereinafter referred to as a “bonding wire”), a thin wire with a wire diameter of about 15 to 50 μm is mainly used today. For a bonding method with bonding wire, there is generally used a thermal compressive bonding technique with the aid of ultrasound, in which a general bonding device, a capillary tool used for bonding by ...

NOBLE METAL-COATED SILVER WIRE FOR BALL BONDING AND METHOD FOR PRODUCING THE SAME, AND SEMICONDUCTOR DEVICE USING NOBLE METAL-COATED SILVER WIRE FOR BALL BONDING AND METHOD FOR PRODUCING THE SAME

A noble metal-coated silver bonding wire suppresses corrosion at the bonding interface under severe conditions of high temperature and high humidity, and the noble metal-coated silver bonding wire can be ball-bonded in the air. The noble metal-coated silver wire for ball bonding is a noble metal-coated silver wire including a noble metal coating layer on a core material made of pure silver or a silver alloy, wherein the wire contains at least one sulfur group element, the noble metal coating layer includes a palladium intermediate layer and a gold skin layer, the palladium content relative to the entire wire is 0.01 mass % or more and 5.0 mass % or less, the gold content relative to the entire wire is 1.0 mass % or more and 6.0 mass % or less, and the sulfur group element content relative to the entire wire is 0.1 mass ppm or more and 100 mass ppm or less. 1. A noble metal-coated silver wire for ball bonding comprising a noble metal coating layer on a core material made of pure silver or a silver alloy ,wherein the wire contains at least one sulfur group element,the noble metal coating layer comprises a palladium intermediate layer and a gold skin layer,a palladium content relative to an entire wire is 0.01 mass % or more and 5.0 mass % or less,a gold content relative to the entire wire is 1.0 mass % or more and 6.0 mass % or less, anda content of the sulfur group element relative to the entire wire is 0.1 mass ppm or more and 100 mass ppm or less.2. The noble metal-coated silver wire for ball bonding according to claim 1 , wherein the noble metal coating layer further comprises a gold intermediate layer on a core material surface of the palladium intermediate layer.3. The noble metal-coated silver wire for ball bonding according to claim 1 , wherein the core material further contains copper claim 1 , and a copper content relative to the entire wire is 0.005 mass % or more and 2.0 mass % or less.46-. (canceled)7. A semiconductor device comprising at least one ...

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND CORRESPONDING SEMICONDUCTOR DEVICE

A method is for making a semiconductor device having an IC die on a substrate with electric contact formations for the IC die and the substrate. The method may include printing ink including electrically conductive nanoparticles, onto the electric contact formations. 110-. (canceled)11. A method of making a semiconductor device comprising at least one integrated circuit (IC) die on a substrate with a plurality of electric contact formations for the at least one IC die and the substrate , the method comprising:printing ink including electrically conductive nanoparticles onto the plurality of electric contact formations.12. The method of wherein the plurality of electric contact formations comprises contact formations adjacent the substrate claim 11 , a plurality of bond wires claim 11 , and contact formations adjacent the at least one IC die.13. The method of wherein the electrically conductive nanoparticles comprise metal nanoparticles.14. The method of wherein the electrically conductive nanoparticles comprise copper nanoparticles.15. The method of wherein the electrically conductive nanoparticles have a size in a range of 30-150 nanometers.16. The method of further comprising printing onto the plurality of electric contact formations a layer of the ink claim 11 , the layer having a thickness between 0.25-1 micrometers.17. The method of further comprising applying to the ink at least one of a heat treatment claim 11 , an ultraviolet curing claim 11 , an oven sintering claim 11 , and a laser sintering claim 11 ,18. The method of further comprising heating the ink to a temperature between 250-300° C.19. The method of wherein the plurality of electric contact formations comprises a bind wire lead claim 11 , a wire bonding joint claim 11 , and a pad/ball bond.20. The method of further comprising forming molding material onto the at least one IC die and the substrate with the ink.21. The method of further comprising printing the ink by at least one of inkjet printing ...

Palladium (pd)-coated copper wire for ball bonding

A palladium coated copper wire for ball bonding includes a core formed of pure copper or copper alloy having a purity of 98% by mass or more, and a palladium draw coated layer coated on the core. The copper wire has a diameter of 10 to 25 μm, and the palladium drawn layer contains sulfur, phosphorus, boron or carbon.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

To prevent cracks of an interlayer insulation film at the time of wire bonding while maintaining adhesion of an aluminum pad electrode and the interlayer insulation film in a semiconductor device in which the aluminum pad electrode and a lead frame are connected with bonding wire by a ball bonding technology. In a bonding pad that is configured to have multiple pad electrodes each with two or more layers, the pad electrodes being electrically connected with one another through vias, the vias are not arranged under an area to which a capillary end of a wire bonder contacts at the time of the wire boding. 1. A semiconductor device comprising:a first pad electrode formed in an interlayer insulation film;a second pad electrode formed in a layer higher than the first pad electrode; anda via that is provided between the first pad electrode and the second pad electrode and electrically connects the first pad electrode and the second pad electrode,wherein the via is not arranged under an area to which a capillary end of a wire bonder contacts.2. The semiconductor device according to claim 1 ,wherein the second pad electrode is covered with a surface protective film having a rectangular opening over the second pad electrode, and the via is not arranged in an area sandwiched by a virtual circle inscribed in the opening and a virtual circle derived on the basis of a dimension of a wire diameter of boding wire used in the wire boding.3. The semiconductor device according to claim 2 ,wherein the virtual circle derived on the basis of the dimension of the wire diameter is a circle of a diameter that is larger than the wire diameter by x μm, where x is in a range of 5≦x≦13.4. The semiconductor device according to claim 1 ,wherein the second pad electrode is covered with a surface protective film that has a rectangular opening over the second pad electrode, and the via is not arranged under an area in which a test needle contacts the second pad electrode at the time of a wafer ...

METALLIC RIBBON FOR POWER MODULE PACKAGING

A metallic ribbon for power module packaging is described. The metallic ribbon has a rectangular, oval or oblong cross section. The composition of the metallic ribbon is silver-palladium alloy containing 0.2 to 6 wt % Pd. The metallic ribbon has a thickness of 10 μm to 500 μm. The width of the metallic ribbon is 2 to 100 times its thickness. The metallic ribbon includes a plurality of grains. The average grain size of the grains observed in the transverse cross section is 2 μm to 10 μm. The metallic ribbon has a plurality of twin grains observed in the transverse cross section, and the number of twin grains observed in the transverse cross section accounts for at least 5% of the total number of grains observed in the transverse cross section. 1. A metallic ribbon for power module packaging , wherein:the metallic ribbon has a rectangular, oval or oblong cross section;a composition of the metallic ribbon is a silver-palladium alloy comprising 0.2 to 6 wt % palladium;the metallic ribbon has a thickness of 10 μm to 500 μm;a width of the metallic ribbon is 2 to 100 times the thickness;the metallic ribbon comprises a plurality of grains, an average grain size of grains observed in a transverse cross section of the metallic ribbon is 2 μm to 10 μm; andthe metallic ribbon has a plurality of twin grains observed in the transverse cross section of the metallic ribbon, and a number of the twin grains observed in the transverse cross section accounts for at least 5% of a total number of the grains observed in the transverse cross section.2. The metallic ribbon for power module packaging of claim 1 , wherein a hardness of the metallic ribbon is 40 Hv to 70 Hv.3. The metallic ribbon for power module packaging of claim 1 , wherein the width of the metallic ribbon is not greater than 5 mm.4. The metallic ribbon for power module packaging of claim 1 , wherein a surface of the metallic ribbon is covered by one or more metal layers claim 1 , wherein a composition of the one or more ...

Chip package, method of forming a chip package and method of forming an electrical contact

In various embodiments, a method of forming an electrical contact is provided. The method may include depositing, by atomic layer deposition, a passivation layer over at least a region of a metal surface, wherein the passivation layer may include aluminum oxide, and electrically contacting the region of the metal surface with a metal contact structure, wherein the metal contact structure may include copper.

Semiconductor die package and method for making the same

Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.

SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE

The present invention is directed to improve reliability of a semiconductor device. A semiconductor device manufacturing method includes: (a) a step of attaching a BGA having a solder ball to a socket for a burn-in test; and (b) a step of performing a burn-in test of the BGA by sandwiching the solder ball by conductive contact pins in the socket. The contact pin in the socket has a first projection part which is conductive and extends along an attachment direction of the BGA and a second projection part which is conductive, provided along a direction crossing the extension direction of the first projection part, and placed so as to face the surface on the attachment side of the BGA of the solder ball. In the step (b), a burn-in test of the BGA is performed in a state where the first projection parts in the contact pins are in contact with the solder ball. 1. A semiconductor device manufacturing method comprising the steps of:(a) attaching a semiconductor device having a ball electrode as an external terminal to a socket for a burn-in test; and wherein the contact part of the socket has a first projection part which is conductive and extends along an attachment direction of the semiconductor device and a second projection part which is conductive and placed so as to face the surface on the attachment side of the semiconductor device of the ball electrode, and', 'wherein in the step (b), the burn-in test of the semiconductor device is performed in a state where the first projection part of the contact part is in contact with the ball electrode., '(b) performing a burn-in test of the semiconductor device by sandwiching the ball electrode by a conductive contact part of the socket,'}2. The semiconductor device manufacturing method according to claim 1 ,wherein the semiconductor device has a substrate to which the plurality of ball electrodes are attached, andwherein the second projection part is arranged on the side of the substrate from a contact part between the first ...

TUNED SEMICONDUCTOR AMPLIFIER

Methods and structures for improving the performance of integrated semiconductor transistors operating at high frequency and/or high power are described. Two capacitors may be connected to an input of a semiconductor transistor and tuned to suppress second-harmonic generation and to transform and match the input impedance of the device. A two-stage tuning procedure is described. The transistor may comprise gallium nitride and may be configured as a power transistor capable of handling up to 1000 W of power. A tuned transistor may operate at frequencies up to 6 GHz with a peak drain efficiency greater than 60%. 1. A method for tuning a semiconductor transistor having a two-capacitor input network , the method comprising:{'sub': '11', 'altering a value of a first capacitor in a first capacitive shunt until a resonance loop of an Sscattering-parameter curve has a peak at a frequency that is approximately twice a target frequency for the semiconductor transistor, wherein the first capacitive shunt is connected to at least one gate contact of the semiconductor transistor;'}adding a second capacitive shunt to the first capacitive shunt; andaltering a value of a second capacitor in the second capacitive shunt until an input impedance at an input to the second capacitive shunt is approximately equal to a target impedance value.2. The method of claim 1 , wherein the semiconductor transistor comprises gallium nitride in an active region of the transistor.3. The method of claim 1 , wherein the target frequency is between approximately 1 GHz and approximately 6 GHz.4. The method of claim 1 , wherein altering the value of the first capacitor comprises selecting a value of the first capacitor in a range between approximately 5 pF and approximately 60 pF.5. The method of claim 1 , wherein altering the value of the second capacitor comprises selecting a value of the second capacitor in a range between approximately 5 pF and approximately 60 pF.6. The method of claim 1 , wherein the ...

BONDING WIRE FOR SEMICONDUCTOR DEVICE

A bonding wire for a semiconductor device includes a Cu alloy core material and a Pd coating layer formed on a surface thereof, and the boding wire contains one or more elements of As, Te, Sn, Sb, Bi and Se in a total amount of 0.1 to 100 ppm by mass. The bonding longevity of a ball bonded part can increase in a high-temperature and high-humidity environment, improving the bonding reliability. When the Cu alloy core material further contains one or more of Ni, Zn, Rh, In, Ir, Pt, Ga and Ge in an amount, for each, of 0.011 to 1.2% by mass, it is able to increase the reliability of a ball bonded part in a high-temperature environment of 170° C. or more. When an alloy skin layer containing Au and Pd is further formed on a surface of the Pd coating layer, wedge bondability improves. 1. A bonding wire for a semiconductor device comprising:a Cu alloy core material; anda Pd coating layer formed on a surface of the Cu alloy core material, whereinthe bonding wire contains at least one or more elements selected from As and Te, anda concentration of the elements in total is 0.1 ppm by mass or more and 100 ppm by mass or less relative to the entire wire.2. The bonding wire for a semiconductor device according to claim 1 , wherein the concentration of the at least one or more elements selected from As and Te in total is 1 ppm by mass or more and 100 ppm by mass or less relative to the entire wire.3. The bonding wire for a semiconductor device according to claim 1 , wherein a thickness of the Pd coating layer is 0.015 μm or more and 0.150 μm or less.4. The bonding wire for a semiconductor device according to claim 1 , further comprising an alloy skin layer containing Au and Pd on the Pd coating layer.5. The bonding wire for a semiconductor device according to claim 4 , wherein a thickness of the alloy skin layer containing Au and Pd is 0.0005 μm or more and 0.050 μm or less.6. The bonding wire for a semiconductor device according to claim 1 , whereinthe bonding wire further ...

Bonding wire for semiconductor device

A bonding wire for a semiconductor device includes a Cu alloy core material and a Pd coating layer on a surface of the Cu alloy core material, and contains Ga and Ge of 0.011 to 1.2% by mass in total, which is able to increase bonding longevity of the ball bonded part in the high-temperature, high-humidity environment, and thus to improve the bonding reliability. The thickness of the Pd coating layer is preferably 0.015 to 0.150 μm. When the bonding wire further contains one or more elements of Ni, Ir, and Pt in an amount, for each element, of 0.011 to 1.2% by mass, it is able to improve the reliability of the ball bonded part in a high-temperature environment at 175° C. or more. When an alloy skin layer containing Au and Pd is further formed on a surface of the Pd coating layer, wedge bondability improves.

COATED BOND WIRES FOR DIE PACKAGES AND METHODS OF MANUFACTURING SAID COATED BOND WIRES

A bond wire having a metal core, a dielectric layer, and a ground connectable metallization, wherein the bond wire has one or more vapor barrier coatings. Further, the present invention relates to a die package with at least one bond wire according to the invention. 1. A lead having a metal core , a dielectric layer at least partially surrounding the metal core , the dielectric in turn being at least partially surrounded by a ground connectable metal coating , wherein that the lead further has at least one vapor barrier coating for protecting areas that are not covered by metal.2. (canceled)3. The lead of claim 1 , wherein the metal coating surrounds the dielectric layer only partially.4. The lead of claim 1 , wherein the lead includes additional metal layers and/or additional dielectric layers.5. The lead of claim 1 , wherein the lead has multiple layers of dielectric of varying thickness claim 1 , which are separated by thin metal layers claim 1 , with the outermost layer being connected to ground.6. The lead of claim 1 , wherein a high performance dielectric providing a superior vapor barrier and/or oxygen degradation resistance is thinly deposited over a thick layer of another dielectric material.7. A die package comprisinga die having a plurality of connection pads;a die substrate supporting a plurality of connection elements; andone or more leads according to any of the preceding claims connected between the die and the die substrate.8. The die package of claim 7 , wherein the lead includes a first metal core with a defined core diameter claim 7 , a dielectric layer surrounding the first metal core having a first dielectric thickness claim 7 , an outer metal layer at least partially surrounding the dielectric layer claim 7 , and a vapor barrier overcoat.9. The die package of any of claim 7 , wherein the die is overmolded claim 7 , cured claim 7 , and/or singulated for use.10. A method of manufacturing the die package including a die having a plurality of ...

Aluminum coated copper ribbon

A ribbon, preferably a bonding ribbon for bonding in microelectronics, contains a first layer containing copper, a coating layer containing aluminum superimposed over the first layer, and an intermediate layer. In a cross-sectional view of the ribbon, the area share of the first layer is from 50 to 96% and the aspect ratio between the width and the height of the ribbon in a cross-sectional view is from 0.03 to less than 0.8. The ribbon has a cross-sectional area of 25,000 μm 2 to 800,000 μm 2 . The intermediate layer contains at least one intermetallic phase containing materials of the first and coating layers. The invention further relates to a process for making a wire, to a wire obtained by the process, to an electric device containing the wire, to a propelled device comprising said electric device and to a process of connecting two elements through the wire by wedge-bonding.

BONDING WIRE FOR SEMICONDUCTOR DEVICE

A bonding wire for a semiconductor device includes a Cu alloy core material and a Pd coating layer formed on a surface thereof. Containing an element that provides bonding reliability in a high-temperature environment improves the bonding reliability of the ball bonded part in high temperature. Furthermore, making an orientation proportion of a crystal orientation <100> angled at 15 degrees or less to a wire longitudinal direction among crystal orientations in the wire longitudinal direction 30% or more when measuring crystal orientations on a cross-section of the core material in a direction perpendicular to a wire axis of the bonding wire, and making an average crystal grain size in the cross-section of the core material in the direction perpendicular to the wire axis of the bonding wire 0.9 to 1.5 μm provides a strength ratio of 1.6 or less. 1. A bonding wire for a semiconductor device , the bonding wire comprising:a Cu alloy core material; anda Pd coating layer formed on a surface of the Cu alloy core material, whereinwhen measuring crystal orientations on a cross-section of the core material in a direction perpendicular to a wire axis of the bonding wire, a crystal orientation <100> angled at 15 degrees or less to a wire longitudinal direction has a proportion of 30% or more among crystal orientations in the wire longitudinal direction,an average crystal grain size in the cross-section of the core material in the direction perpendicular to the wire axis of the bonding wire is 0.9 μm or more and 1.5 μm or less, andthe bonding wire contains one or more elements selected from Co, Rh, Ir, Ni, Pd, Pt, Ag, Au, Zn, Al, In, Sn, P, As, Sb, Bi, Se and Te.2. The bonding wire for a semiconductor device according to claim 1 , wherein a strength ratio defined by the following Equation (1) is 1.1 or more and 1.6 or less:{'br': None, 'Strength ratio=ultimate strength/0.2% offset yield strength.\u2003\u2003(1)'}3. The bonding wire for a semiconductor device according to claim 1 ...

BONDING WIRE FOR SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE INCLUDING SAME

Provided is a bonding wire for a semiconductor package and a semiconductor package including the same. The bonding wire for the semiconductor package may include a core portion including silver (Ag), and a shell layer surrounding the core portion, having a thickness of 2 nm to 23 nm, and including gold (Au). The semiconductor package may include a package body having a first electrode structure and a second electrode structure, a semiconductor light emitting device comprising a first electrode portion and a second electrode portion electrically connected to the first electrode structure and the second electrode structure, and a bonding wire connecting at least one of the first electrode structure and the second electrode structure to the semiconductor light emitting device. 1. A bonding wire for a semiconductor package comprising:a core portion including silver (Ag); anda shell layer surrounding the core portion, having a thickness of 23 nm or less, and including gold (Au).2. The bonding wire for the semiconductor package of claim 1 , wherein the core portion includes Ag having a purity of 95% claim 1 , and the shell layer includes Au having a purity of 99% or more.3. The bonding wire for the semiconductor package of claim 1 , wherein the bonding wire has a reflectivity higher than a reflectivity of a wire including Au having a purity of 99.99% with regard to light having a wavelength of 420 nm.4. The bonding wire for the semiconductor package of claim 3 , wherein the reflectivity of the bonding wire ranges from 38% to 76%.5. The bonding wire for the semiconductor package of claim 1 , wherein the core portion has a thickness of 10 μm to 50 μm.6. The bonding wire for the semiconductor package of claim 5 , wherein the thickness of the shell layer ranges from about 0.0065% to 0.075% of the thickness of the core portion.7. The bonding wire for the semiconductor package of claim 1 , wherein the shell layer has a coating of Au having a thickness of 2 nm to 23 nm formed on ...

Cu ALLOY CORE BONDING WIRE WITH Pd COATING FOR SEMICONDUCTOR DEVICE

A bonding wire for a semiconductor device includes a Cu alloy core material and a Pd coating layer formed on a surface thereof, and the boding wire contains one or more elements of As, Te, Sn, Sb, Bi and Se in a total amount of 0.1 to 100 ppm by mass. The bonding longevity of a ball bonded part can increase in a high-temperature and high-humidity environment, improving the bonding reliability. When the Cu alloy core material further contains one or more of Ni, Zn, Rh, In, Ir, Pt, Ga and Ge in an amount, for each, of 0.011 to 1.2% by mass, it is able to increase the reliability of a ball bonded part in a high-temperature environment of 170° C. or more. When an alloy skin layer containing Au and Pd is further formed on a surface of the Pd coating layer, wedge bondability improves. 1. A bonding wire for a semiconductor device comprising:a Cu alloy core material; anda Pd coating layer formed on a surface of the Cu alloy core material, whereinthe bonding wire contains at least one or more first elements selected from Sb, Bi and Se,a concentration of the first elements in total is 0.1 ppm by mass or more and 100 ppm by mass or less relative to the entire wire, andSb≤10 ppm by mass; and Bi≤1 ppm by mass, andthe bonding wire contains at least one or more second elements selected from Ni, Zn, Rh, In, Ir, Pt, Ga and Ge, anda concentration of each of the second elements is 0.011% by mass or more and 1.2% by mass or less relative to the entire wire.2. The bonding wire for a semiconductor device according to claim 1 , wherein the concentration of the at least one or more first elements selected from Sb claim 1 , Bi and Se in total is 1 ppm by mass or more and 100 ppm by mass or less relative to the entire wire.3. The bonding wire for a semiconductor device according to claim 1 , wherein a thickness of the Pd coating layer is 0.015 μm or more and 0.150 μm or less.4. The bonding wire for a semiconductor device according to claim 1 , further comprising an alloy skin layer ...

Light emitting device mount, light emitting apparatus including the same, and leadframe

A mount includes a terminal, and a resin portion. The terminal includes a first surface, a second surface, and an end surface having first and second recessed areas that are extend from the first and second surfaces, respectively. The resin portion is integrally formed with the terminal, and at least partially covers the end surface so that the first and second surfaces are at least partially exposed. The resin portion forms a recessed part to accommodate the light emitting device. The second recessed area includes a closest point that is positioned closest to the first surface, and an extension part that extends outward of the closest point and toward the second surface side. The extension part is formed at least on opposing end surfaces of the pair of positive and negative lead terminal. The first recessed area is arranged on the exterior side relative to the closest point.

BONDING WIRE FOR SEMICONDUCTOR DEVICE

A bonding wire for a semiconductor device includes a Cu alloy core material and a Pd coating layer on a surface of the Cu alloy core material, and contains Ga and Ge of 0.011 to 1.2% by mass in total, which is able to increase bonding longevity of the ball bonded part in the high-temperature, high-humidity environment, and thus to improve the bonding reliability. The thickness of the Pd coating layer is preferably 0.015 to 0.150 μm. When the bonding wire further contains one or more elements of Ni, Ir, and Pt in an amount, for each element, of 0.011 to 1.2% by mass, it is able to improve the reliability of the ball bonded part in a high-temperature environment at 175° C. or more. When an alloy skin layer containing Au and Pd is further formed on a surface of the Pd coating layer, wedge bondability improves. 2. The bonding wire for a semiconductor device according to claim 1 , wherein a thickness of the Pd coating layer is 0.015 μm or more and 0.150 μm or less.3. The bonding wire for a semiconductor device according to claim 1 , further comprising an alloy skin layer containing Au and Pd on the Pd coating layer.4. The bonding wire for a semiconductor device according to claim 3 , wherein a thickness of the alloy skin layer containing Au and Pd is 0.0005 μm or more and 0.050 μm or less.5. The bonding wire for a semiconductor device according to claim 1 , whereinthe bonding wire further contains one or more elements selected from Ni, Ir, and Pt, anda concentration of each of the elements relative to the entire wire is 0.011% by mass or more and 1.2% by mass or less.6. The bonding wire for a semiconductor device according to claim 1 , whereinthe Cu alloy core material contains Pd, anda concentration of Pd contained in the Cu alloy core material is 0.05% by mass or more and 1.2% by mass or less.7. The bonding wire for a semiconductor device according to claim 1 , whereinthe bonding wire further contains at least one element selected from B, P, and Mg, anda concentration ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

According to one embodiment, semiconductor device includes a semiconductor layer, an electrode provided on the semiconductor layer, and a bonding wire connected to the electrode, wherein the electrode comprises a first metal layer containing copper, a second metal layer containing aluminum, provided between the first metal layer and the semiconductor layer, and a third metal layer provided between the first metal layer and the second metal layer, the third metal layer comprising a material different from those of the first metal layer and the second metal layer, and the thickness of the first metal layer is larger than the thickness of the second metal layer and larger than the thickness of the third metal layer. 1. A semiconductor device , comprising:a semiconductor layer;an electrode provided on the semiconductor layer; anda bonding wire connected to the electrode, whereinthe electrode comprises a first metal layer containing copper, a second metal layer containing aluminum and between the first metal layer and the semiconductor layer, and a third metal layer between the first metal layer and the second metal layer, the third metal layer comprising a material different from those of the first metal layer and the second metal layer, andthe thickness of the first metal layer is greater than the thickness of the second metal layer and greater than the thickness of the third metal layer.2. The semiconductor device according to claim 1 , wherein the third metal layer contains at least one metal element selected from the group consisting of titanium claim 1 , tungsten claim 1 , and tantalum.3. The semiconductor device according to claim 1 , wherein the third metal layer contains at least one material selected from the group consisting of titanium claim 1 , tungsten claim 1 , tantalum claim 1 , titanium nitride claim 1 , tungsten nitride claim 1 , tantalum nitride claim 1 , and a titanium/tungsten alloy.4. The semiconductor device according to claim 1 , wherein the ...

COATING LAYER FOR A CONDUCTIVE STRUCTURE

A coating layer for use in copper integrated circuit interconnect and other conductive structures hinders and decreases oxide growth on surfaces of such conductive structures. The coating layer includes an amorphous copper containing layer deposited on a crystalline copper substrate, such as utilized for a lead frame and a bonding wire. Additional amorphous layers may be interposed between the amorphous copper containing layer and the copper substrate, such as an amorphous tantalum nitride layer and an amorphous titanium nitride layer. 1. A conductive structure comprising:a crystalline copper substrate suitable for an electrically conductive structure; anda coating layer over the crystalline copper substrate, wherein the coating layer comprises acontinuous amorphous copper containing film.2. The conductive structure as recited in claim 1 , wherein the coating layer further comprises:an amorphous tantalum nitride layer between the crystalline copper substrate and an amorphous titanium nitride layer; andthe amorphous titanium nitride layer between, the amorphous tantalum, nitride layer and the amorphous copper containing film.3. The conductive structure as recited in claim 2 , wherein the amorphous copper containing film comprises an amorphous copper alloy.4. The conductive structure as recited in claim 3 , wherein the amorphous copper alloy is selected from the group consisting of an amorphous copper zirconium alloy and an amorphous copper hafnium alloy.5. The conductive structure as recited in claim 1 , wherein the amorphous copper containing film comprises an amorphous copper alloy.6. The conductive structure as recited in claim 1 , wherein the coating layer comprises an amorphous copper alloy layer interposed between the amorphous copper containing film and the crystalline copper substrate.7. The conductive structure as recited in claim 6 , wherein the amorphous copper alloy layer comprises an amorphous copper zirconium alloy.8. The conductive structure as recited ...

BONDING WIRE FOR SEMICONDUCTOR DEVICE

A bonding wire for a semiconductor device includes a Cu alloy core material and a Pd coating layer formed on a surface thereof. Containing an element that provides bonding reliability in a high-temperature environment improves the bonding reliability of the ball bonded part in high temperature. Furthermore, making an orientation proportion of a crystal orientation <100> angled at 15 degrees or less to a wire longitudinal direction among crystal orientations in the wire longitudinal direction 30% or more when measuring crystal orientations on a cross-section of the core material in a direction perpendicular to a wire axis of the bonding wire, and making an average crystal grain size in the cross-section of the core material in the direction perpendicular to the wire axis of the bonding wire 0.9 to 1.5 μm provides a strength ratio of 1.6 or less. 1. A bonding wire for a semiconductor device , the bonding wire comprising:a Cu alloy core material; anda Pd coating layer formed on a surface of the Cu alloy core material, whereinwhen measuring crystal orientations on a cross-section of the core material in a direction perpendicular to a wire axis of the bonding wire, a crystal orientation <100> angled at 15 degrees or less to a wire axis direction has a proportion of 30% or more among crystal orientations in the wire axis direction,an average crystal grain size in the cross-section of the core material in the direction perpendicular to the wire axis of the bonding wire is 0.9 μm or more and 1.5 μm or less, andthe bonding wire contains one or more elements selected from Ga and Ge, and a concentration of the elements in total is 0.011 to 1.5% by mass relative to the entire wire.2. The bonding wire for a semiconductor device according to claim 1 , wherein a strength ratio defined by the following Equation (1) is 1.1 or more and 1.6 or less:{'br': None, 'Strength ratio=ultimate strength/0.2% offset yield strength. \u2003\u2003(1)'}3. The bonding wire for a semiconductor device ...

WIRE BALL BONDING IN SEMICONDUCTOR DEVICES

A method of interconnecting components of a semiconductor device using wire bonding is presented. The method includes creating a free air ball at a first end of an aluminum wire that has a coating surrounding the aluminum wire, wherein the coating comprises palladium, and wherein the free air ball is substantially free of the coating. The method further includes the step of bonding the free air ball to a bond pad on a semiconductor chip, the bond pad having an aluminum surface layer, wherein the resultant ball bond and the bond pad form a substantially homogenous, aluminum-to-aluminum bond. The method may further include bonding a second, opposing end of the coated-aluminum wire to a bond site separate from the semiconductor chip, the bond site having a palladium surface layer, wherein the second end of the coated-aluminum wire and the bond site form a substantially homogenous, palladium-to-palladium bond. 1. A method of interconnecting components of a semiconductor device using wire bonding , the method comprising:providing a coated-aluminum wire, the coated-aluminum wire having a coating that comprises palladium;forming a free air ball from a first end of the coated-aluminum wire, wherein during the formation of the free air ball, the coating is removed from at least a portion of the free air ball;bonding the free air ball to a bond pad on a semiconductor chip, the bond pad having an aluminum surface layer, wherein the free air ball and the aluminum surface layer of the bond pad form a substantially homogenous, aluminum-to-aluminum ball bond; andbonding a second, opposing end of the coated-aluminum wire to a lead on a lead frame, the lead having a palladium surface layer, wherein the second end of the coated-aluminum wire and the lead form a substantially homogenous, palladium-to-palladium bond.2. The method of claim 1 , wherein the coating prevents oxidation of the free air ball during formation of the free air ball.3. The method of claim 1 , wherein the ...

PALLADIUM-COATED COPPER BONDING WIRE AND METHOD FOR MANUFACTURING SAME

There is provided a palladium-coated copper bonding wire that does not cause a shrinkage cavity during first bonding, has high bonding reliability, and is capable of maintaining excellent bonding reliability for a long period of time even in high-temperature and high-humidity environments. A palladium-coated copper bonding wire in which a concentration of palladium is 1.0 mass % or more and 4.0 mass % or less relative to the total of copper, palladium, and a sulfur group element, a total concentration of the sulfur group element is 50 mass ppm or less, and a concentration of sulfur is 5 mass ppm or more and 12 mass ppm or less, a concentration of selenium is 5 mass ppm or more and 20 mass ppm or less, or a concentration of tellurium is 15 mass ppm or more and 50 mass ppm or less, and the palladium-coated copper bonding wire including a palladium-concentrated region with the average concentration of palladium of 6.5 atom % or more and 30.0 atom % or less relative to the total of copper and palladium within a range from a surface of a tip portion of a free air ball formed at a tip of the wire to 5.0 nm or more and 100.0 nm or less. 1. A palladium-coated copper bonding wire containing 50 mass ppm or less of sulfur group element in total , the palladium-coated copper bonding wire comprising:a core material containing copper as a main component; anda palladium layer on the core material, wherein 5 mass ppm or more and 12 mass ppm or less of sulfur (S);', '5 mass ppm or more and 20 mass ppm or less of selenium (Se); and', '15 mass ppm or more and 50 mass ppm or less of tellurium (Te),, 'the sulfur group element includes at least one ofa concentration of palladium is 1.0 mass % or more and 4.0 mass % or less relative to the total of copper, palladium, and the sulfur group element of the palladium-coated copper bonding wire, and,the palladium-coated copper bonding wire includes a palladium-concentrated region with the average concentration of palladium of 6.5 atom % or more ...

Coated bond wires for die packages and methods of manufacturing said coated bond wires

A method of manufacturing a bond wire having a metal core, a dielectric layer, and a ground connectable metallization, wherein the bond wire has one or more vapor barrier coatings, and manufacturing a die package with at least one bond wire according to the invention.

Module Comprising a Semiconductor Chip

A module includes a semiconductor chip having at least a first terminal contact surface and a second terminal contact surface. A first bond element made of a material on the basis of Cu is attached to the first terminal contact surface, and a second bond element is attached to the second terminal contact surface. The second bond element is made of a material different from the material of the first bond element or is made of a type of bond element different from the type of the first bond element.

Half Bridge Circuit, Method of Operating a Half Bridge Circuit and a Half Bridge Circuit Package

A half bridge circuit includes an input connection configured to supply an electric input, an output connection configured to supply an electric output to a load to be connected to the output connection, a switch and a diode arranged between the input connection and the output connection and a voltage limiting inductance arranged in series between the switch and the diode. The voltage limiting inductance is configured to limit, upon switching the switch, a maximum voltage across the switch to below a breakdown voltage of the switch. A corresponding method of operating the half bridge circuit and package are also described. 120-. (canceled)21. A half bridge circuit , comprising:an input connection configured to supply an electric input;an output connection configured to supply an electric output to a load to be connected to the output connection;a switch and a diode arranged between the input connection and the output connection; anda voltage limiting inductance arranged in series between the switch and the diode, the voltage limiting inductance configured to limit, upon switching the switch, a maximum voltage across the switch to below a breakdown voltage of the switch.22. The half bridge circuit of claim 21 , wherein the switch is a field effect transistor switch claim 21 , wherein the diode is a field effect transistor diode claim 21 , and wherein the voltage limiting inductance is arranged in series between a source of the field effect transistor switch and a drain of the field effect transistor diode.23. The half bridge circuit of claim 21 , wherein both the switch and the diode are connected within a loop between the input connection and the output connection claim 21 , and wherein the voltage limiting inductance has an inductance value in a range between 20% and 70% of a loop inductance of the loop.24. The half bridge circuit of claim 23 , wherein the voltage limiting inductance is distributed over the entire loop.25. The half bridge circuit of claim 21 , ...

SEMICONDUCTOR APPARATUS INCLUDING A HEAT DISSIPATING MEMBER

A semiconductor apparatus is provided. The semiconductor apparatus includes: a base having a main surface on which a terminal is disposed; a first semiconductor device retained on the main surface of the base and having a top surface on which an electrode is disposed and a bottom surface facing the main surface of the base; a connection member connecting the terminal and the electrode; an encapsulant disposed on the main surface of the base and covering the terminal, the first semiconductor device and the connection member; and a heat dissipating member disposed on the encapsulant and having a space that opens in a direction extending perpendicular to the main surface of the base. The encapsulant is disposed in the space and, in a side view of the base, a peak of the connection member is located inside the space. 1. A semiconductor apparatus comprising:a base having a main surface on which a terminal is disposed;a first semiconductor device retained on the main surface of the base and having a top surface on which an electrode is disposed and a bottom surface facing the main surface of the base;a connection member connecting the terminal and the electrode;an encapsulant disposed on the main surface of the base and covering the terminal, the first semiconductor device and the connection member; anda heat dissipating member disposed on the encapsulant and having a space that opens in a direction extending perpendicular to the main surface of the base,wherein the encapsulant is disposed in the space, andin a side view of the base, a peak of the connection member is located inside the space.2. The semiconductor apparatus according to claim 1 , whereina side surface of the heat dissipating member, a side surface of the encapsulant, and a side surface of the base lie in a same plane.3. The semiconductor apparatus according to claim 2 , whereina top surface of the heat dissipating member and a top surface of the encapsulant lie in a same plane.4. The semiconductor ...

WIRE BONDING SYSTEMS AND RELATED METHODS

A wire bond system. Implementations may include: a bond wire including copper (Cu), a bond pad including aluminum (Al) and a sacrificial anode electrically coupled with the bond pad, where the sacrificial anode includes one or more elements having a standard electrode potential below a standard electrode potential of Al. 1. A wire bond system comprising:a bond wire comprising Cu;a bond pad comprising Al; anda sacrificial anode electrically coupled with the bond pad, the sacrificial anode comprising one or more elements having a standard electrode potential below a standard electrode potential of Al.2. The system of claim 1 , wherein the one or more elements is one of Mg claim 1 , Hf claim 1 , Be claim 1 , and any combination thereof.3. A wire bond system comprising:a bond wire comprising Cu;a bond pad comprising Al; anda sacrificial anode physically and electrically coupled over at least a portion of the bond pad, the sacrificial anode comprising one or more elements having a standard electrode potential below a standard electrode potential of Al.4. The system of claim 3 , wherein the one or more elements is one of Mg claim 3 , Hf claim 3 , Be claim 3 , and any combination thereof.5. A wire bond system comprising:a bond wire comprising Cu; anda bond pad coupled to the bond wire, the bond pad comprising a material comprising Al and one or more elements having a standard electrode potential between a standard electrode potential of Cu and a standard electrode potential of Al.6. The system of claim 5 , wherein the one or more elements is W.7. The system of claim 5 , wherein the one or more elements is Zn.8. The system of claim 5 , wherein the one or more elements is Cr.9. The system of claim 5 , wherein the one or more elements is Sn.10. The system of claim 5 , wherein the one or more elements is Fe.11. The system of claim 5 , wherein the one or more elements is selected from the group consisting of Mo claim 5 , Cd claim 5 , Co claim 5 , Ni claim 5 , Cu claim 5 , and ...

Binding wire and semiconductor package structure using the same

A semiconductor package structure includes a substrate, and a package preform. The substrate includes a plurality of conductive tracing wires. The package preform includes a semiconductor chip and a plurality of binding wires. The semiconductor chip includes a plurality of welding spots, and the welding spots are electrically connected with corresponding conductive tracing wires by the binding wires. Each binding wire comprises a carbon nanotube composite wire, the carbon nanotube composite wire includes a carbon nanotube wire and a metal layer. The carbon nanotube wire consists of a plurality of carbon nanotubes spirally arranged along an axial direction an axial direction of the carbon nanotube wire.

BONDING WIRE FOR SEMICONDUCTOR DEVICES

Provided is a bonding wire capable of reducing the occurrence of defective loops. The bonding wire includes: a core material which contains more than 50 mol % of a metal M; an intermediate layer which is formed over the surface of the core material and made of Ni, Pd, the metal M, and unavoidable impurities, and in which the concentration of the Ni is 15 to 80 mol %; and a coating layer formed over the intermediate layer and made of Ni, Pd and unavoidable impurities. The concentration of the Pd in the coating layer is 50 to 100 mol %. The metal M is Cu or Ag, and the concentration of Ni in the coating layer is lower than the concentration of Ni in the intermediate layer. 1. A bonding wire for a semiconductor device comprising:a core material containing more than 50 mol % of a metal M;an intermediate layer formed over a surface of the core material and made of Ni, Pd, the metal M, and unavoidable impurities, concentration of the Ni being 15 to 80 mol %; anda coating layer formed over the intermediate layer and made of Ni, Pd and unavoidable impurities, the concentration of the Pd being 50 to 100 mol %,wherein the metal M is Cu or Ag, and the concentration of the Ni in the coating layer is lower than the concentration of the Ni in the intermediate layer.2. The bonding wire according to claim 1 , wherein the thickness of the intermediate layer is 8 to 80 nm.3. The bonding wire according to claim 1 , whereinthe coating layer further contains Au, and the bonding wire further comprises a surface layer formed over the coating layer and made of an alloy containing Au and Pd, the concentration of the Au being 10 to 70 mol %, the sum total concentration of the Au and the Pd being 80 mol % or more,wherein the concentration of the Au in the coating layer is lower than the concentration of the Au in the surface layer.4. The bonding wire according to claim 3 , wherein the total thickness of the surface layer claim 3 , the coating layer claim 3 , and the intermediate layer is 25 ...

Semiconductor Device with Copper Structure

A semiconductor device includes a copper structure over a semiconductor body. In a copper oxide layer on a surface of the copper structure, a content of copper is between 60 at % and 75 at % and a content of oxygen is between 25 at % and 40 at %. 1. A semiconductor device , comprising:a semiconductor body;a copper structure comprising a wiring/pad structure formed on the semiconductor body, wherein the wiring/pad structure comprises a top surface and a side surface; anda copper oxide layer on the top surface and on the side surface of the wiring/pad structure, wherein, in the copper oxide layer, a content of copper is between 60 at % and 75 at %, and a content of oxygen is between 25 at % and 40 at %.2. The semiconductor device of claim 1 , wherein claim 1 , in the copper oxide layer claim 1 , a content of cuprous oxide is at least 90%.3. The semiconductor device of claim 1 , wherein a thickness of the copper oxide layer is at least 50 nm.4. The semiconductor device of claim 1 , further comprising:an interlayer dielectric between the wiring/pad structure and the semiconductor body.5. The semiconductor device of claim 1 , wherein the copper structure comprises a bond wire electrically connecting the wiring/pad structure with a lead claim 1 , and wherein the copper oxide layer is further formed on the bond wire.6. The semiconductor device of claim 5 , wherein the bond wire comprises a wire end in contact with the wiring/pad structure claim 5 , and wherein the copper oxide layer is formed in a bonding area of the wiring/pad structure around the wire end.7. The semiconductor device of claim 5 , wherein the lead comprises copper and the copper oxide layer is further formed on at least a first portion of the lead.8. The semiconductor device of claim 1 , further comprising:a dielectric structure directly on the copper oxide layer, the dielectric structure comprising at least one of a reducing agent and an agent capable of forming a hydrogen-complex.9. The semiconductor ...

BONDING WIRE FOR SEMICONDUCTOR DEVICE

There is provided a Cu bonding wire having a Pd coating layer on a surface thereof, that improves bonding reliability of a ball bonded part in a high-temperature and high-humidity environment and is suitable for on-vehicle devices. 1. A bonding wire for a semiconductor device comprising:a Cu alloy core material; anda Pd coating layer formed on a surface of the Cu alloy core material, wherein the bonding wire contains In,a concentration of In is 0.031% by mass or more and 1.2% by mass or less relative to the entire wire, anda thickness of the Pd coating layer is 0.015 μm or more and 0.150 μm or less.2. The bonding wire for a semiconductor device according to claim 1 , whereinthe Cu alloy core material contains at least one element selected from Pt, Pd, Rh and Ni, anda concentration of each of the elements contained in the Cu alloy core material is 0.05% by mass or more and 1.2% by mass or less.3. The bonding wire for a semiconductor device according to claim 1 , further comprising an Au skin layer on the Pd coating layer.4. The bonding wire for a semiconductor device according to claim 3 , wherein a thickness of the Au skin layer is 0.0005 μm or more and 0.050 μm or less.5. The bonding wire for a semiconductor device according to claim 1 , whereinthe bonding wire further contains at least one element selected from B, P, Mg, Ga and Ge, anda concentration of each of the elements is 1 ppm by mass or more and 100 ppm by mass or less relative to the entire wire.6. The bonding wire for a semiconductor device according to claim 1 , wherein claim 1 , in a measurement result when measuring crystal orientations on a surface of the bonding wire claim 1 , a crystal orientation <111> angled at 15 degrees or less to a longitudinal direction of the bonding wire has a proportion of 30% or more and 100% or less among crystal orientations in the wire longitudinal direction. The present invention relates to a bonding wire for a semiconductor device used to connect electrodes on a ...

CHIP PACKAGE, METHOD OF FORMING A CHIP PACKAGE AND METHOD OF FORMING AN ELECTRICAL CONTACT

In various embodiments, a chip package is provided. The chip package may include a chip, a metal contact structure including a non-noble metal and electrically contacting the chip, a packaging material, and a protective layer including or essentially consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material, wherein the protective layer may include a noble metal, wherein the portion of the protective layer may include a plurality of regions free from the noble metal, and wherein the regions free from the noble metal may provide an interface between the packaging material and the non-noble metal of the metal contact structure. 1. A chip package , comprising:a chip comprising a chip metal surface;a metal contact structure, the metal contact structure electrically contacting the chip metal surface;a packaging material; anda protective layer comprising or consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material; 'Ni, Co, Cr, Ti, V, Mn, Zn, Sn, Mo, Zr.', 'wherein the protective layer comprises or essentially consists of at least one material of a group of inorganic materials, the group consisting of'}2. A chip package , comprising:a chip comprising a chip metal surface;a metal contact structure, the metal contact structure electrically contacting the chip metal surface, wherein the metal contact structure comprises copper and/or silver;a packaging material; anda protective layer comprising or consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material;wherein the protective layer comprises or essentially consists of an azole and/or tetracyanoquinodimethane that is different from the packaging material.3. A leadframe based chip package , comprising:a chip;a metal contact structure comprising a non-noble metal and electrically contacting the chip;a packaging material; anda ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

A semiconductor device includes an insulation substrate including a circuit pattern, semiconductor chips mounted on the circuit pattern, a wire connecting between the semiconductor chips and between the semiconductor chip and the circuit pattern, and a conductive material serving as a conductor formed integrally with the wire. 1. A semiconductor device comprising:an insulation substrate including a circuit pattern;semiconductor chips mounted on the circuit pattern;a wire connecting between the semiconductor chips and between the semiconductor chip and the circuit pattern; anda conductor formed integrally with the wire.2. The semiconductor device according to claim 1 , whereinthe conductor is further formed near a connection portion where the semiconductor chip is connected to the wire.3. The semiconductor device according to claim 1 , whereinthe conductor is lower in linear expansion coefficient than the wire.4. The semiconductor device according to claim 1 , whereinthe wire includes a base made of Al and a coating made of Ni or Cu, the coating being put round the base.5. The semiconductor device according to claim 1 , whereinthe conductor is a conductive material.6. The semiconductor device according to claim 1 , whereinthe wire is a ribbon wire.7. The semiconductor device according to claim 1 , whereinthe conductor includes a conductive material formed on the wire and a plate-shaped conductive material fixed to the wire with the conductive material interposed between the plate-shaped conductive material and the wire.8. The semiconductor device according to claim 7 , whereina plurality of pairs of the semiconductor chips are connected in parallel, and one conductor connects the plurality of pairs of the semiconductor chips.9. The semiconductor device according to claim 1 , whereinthe conductor is formed integrally with the wire located on the other semiconductor chip side on one semiconductor chip and the wire located on the one semiconductor chip side on the other ...

COATED WIRE FOR BONDING APPLICATIONS

The invention is related to a bonding wire which contains a core having a surface and a coating layer which is at least partially superimposed over the surface of the core. The core contains a core main component selected from copper and silver. The coating layer contains a coating component selected from palladium, platinum, gold, rhodium, ruthenium, osmium and iridium in an amount of at least 10% and further contains the core main component in an amount of at least 10%. 121.-. (canceled)22. A bonding wire comprising a core having a surface and a coating layer which is at least partially superimposed over the surface of the core , wherein the core comprises a core main component selected from the group consisting of copper and silver; and wherein the coating layer comprises a coating component selected from the group consisting of palladium , platinum , gold , rhodium , ruthenium , osmium and iridium in an amount of at least 10% and further comprises the core main component in an amount of at least 10%.23. The wire according to claim 22 , wherein an outer range of the coating layer extends from a depth of 0.1% of a wire diameter to a depth of 0.25% of the wire diameter claim 22 , and wherein the amount of the core main component and the amount of the coating component are present in the outer range.24. The wire according to claim 23 , wherein the amount of the core main component in the outer range is between 30% and 70%.25. The wire according to claim 23 , wherein the amount of the coating component decreases within the outer range toward an inside of the wire.26. The wire according to claim 25 , wherein a difference of the amount of the coating component at a radially inner border of the outer range and the amount of the coating component at a radially outer border of the outer range is not more than 30%.27. The wire according to claim 22 , wherein a main component of the wire changes at least two times starting from an outside of the wire up to a depth of 0.25% ...

COATED WIRE

A wire comprising a wire core with a surface, the wire core having a coating layer superimposed on its surface, wherein the wire core includes: (a) pure silver consisting of silver and further components; or (b) doped silver consisting of silver, at least one doping element, and further components; or (c) a silver alloy consisting of silver, palladium and further components; or (d) a silver alloy consisting of silver, palladium, gold, and further components; or (e) a doped silver alloy consisting of silver, palladium, gold, at least one doping element, and further components, wherein the individual amount of any further component is less than 30 wt.-ppm and the individual amount of any doping element is at least 30 wt.-ppm, and the coating layer is a single-layer of gold or palladium or a double-layer comprised of an inner layer of nickel or palladium and an adjacent outer layer of gold. 1. A wire comprising a wire core with a surface , the wire core having a coating layer superimposed on its surface , wherein the wire core itself consists of:(a) pure silver consisting of (a1) silver in an amount in the range of from 99.99 to 100 wt.-% and (a2) further components in a total amount of from 0 to 100 wt.-ppm; or(b) doped silver consisting of (b1) silver in an amount in the range of from 99.69 to 99.987 wt.-%, (b2) at least one doping element selected from the group consisting of calcium, nickel, platinum, copper, rhodium and ruthenium, in a total amount of from 30 to 3000 wt.-ppm and (b3) further components in a total amount of from 0 to 100 wt.-ppm; or(c) a silver alloy consisting of (c1) silver in an amount in the range of from 95.99 to 99.49 wt.-%, (c2) palladium in an amount in the range of from 0.5 to 4 wt.-% and (c3) further components in a total amount of from 0 to 100 wt.-ppm; or(d) a silver alloy consisting of (d1) silver in an amount in the range of from 93.99 to 99.39 wt.-%, (d2) palladium in an amount in the range of from 0.5 to 4 wt.-%, (d3) gold in an ...

GOLD-COATED SILVER BONDING WIRE AND MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A gold-coated silver bonding wire includes: a core material containing silver as a main component; and a coating layer provided on a surface of the core material and containing gold as a main component. The gold-coated silver bonding wire contains gold in a range of not less than 2 mass % nor more than 7 mass %, and at least one sulfur group element selected from the group consisting of sulfur, selenium, and tellurium in a range of not less than 1 mass ppm nor more than 80 mass ppm, with respect to a total content of the bonding wire. 1. A gold-coated silver bonding wire comprising:a core material containing silver as a main component; anda coating layer provided on a surface of the core material and containing gold as a main component,wherein the gold-coated silver bonding wire contains gold in a range of not less than 2 mass % nor more than 7 mass %, and at least one sulfur group element selected from the group consisting of sulfur, selenium, and tellurium in a range of not less than 1 mass ppm nor more than 80 mass ppm, with respect to a total content of the bonding wire.2. A gold-coated silver bonding wire comprising:a core material containing silver as a main component; anda coating layer provided on a surface of the core material and containing gold as a main component,wherein the gold-coated silver bonding wire contains gold in a range of not less than 2 mass % nor more than 7 mass % with respect to a total content of the bonding wire, and at least one sulfur group element selected from the group consisting of sulfur, selenium, and tellurium, andwherein, when a free air ball is formed at one end of the gold-coated silver bonding wire, the free air ball has, in a cross-sectional view of the bonding wire and the free air ball, on a vertical line stretching from a midpoint of a line connecting neck portions between the wire and the ball to a position corresponding to a lowest point of the ball, a gold concentration region in a section corresponding to a position ...

Bonding wire for semiconductor device

The present invention provides a bonding wire capable of simultaneously satisfying ball bonding reliability and wedge bondability required of bonding wires for memories, the bonding wire including a core material containing one or more of Ga, In, and Sn for a total of 0.1 to 3.0 at % with a balance being made up of Ag and incidental impurities; and a coating layer formed over a surface of the core material, containing one or more of Pd and Pt, or Ag and one or more of Pd and Pt, with a balance being made up of incidental impurities, wherein the coating layer is 0.005 to 0.070 μm in thickness.

BONDING WIRE FOR SEMICONDUCTOR DEVICE

A bonding wire for a semiconductor device, which is suitable for on-vehicle devices bonding wire, has excellent capillary wear resistance and surface flaw resistance while ensuring high bonding reliability and further satisfies overall performance including ball formability and wedge bondability, the bonding wire including: a Cu alloy core material; a Pd coating layer formed on a surface of the Cu alloy core material; and a Cu surface layer formed on a surface of the Pd coating layer, in which the bonding wire for semiconductor device contains Ni, a concentration of the Ni in the bonding wire is 0.1 to 1.2 wt. %, the Pd coating layer is 0.015 to 0.150 μm in thickness, and the Cu surface layer is 0.0005 to 0.0070 μm in thickness. 1. A bonding wire for a semiconductor device comprising: a Cu alloy core material; a Pd coating layer formed on a surface of the Cu alloy core material; and a Cu surface layer formed on a surface of the Pd coating layer , wherein the bonding wire contains Ni , a concentration of the Ni in the bonding wire is 0.1 to 1.2 wt. % , the Pd coating layer is 0.015 to 0.150 μm in thickness , and the Cu surface layer is 0.0005 to 0.0070 μm in thickness.2. The bonding wire according to claim 1 , further comprising an alloy coating layer between the Pd coating layer and the Cu surface layer claim 1 , the alloy coating layer containing Au and Pd claim 1 , wherein the alloy coating layer is 0.0005 to 0.0500 μm in thickness.3. The bonding wire according to claim 1 , wherein the Cu alloy core material further contains at least one or more elements selected from among Zn claim 1 , In claim 1 , Pt claim 1 , and Pd; and a concentration of the one or more elements in the Cu alloy core material is 0.05 to 0.50 wt. %.4. The bonding wire according to claim 1 , wherein the bonding wire further contains at least one or more elements selected from among B claim 1 , P claim 1 , Mg claim 1 , and Sn; and a concentration of the one or more elements in the bonding wire is ...

SEGMENTED SHIELDING USING WIREBONDS

The present disclosure relates to segmented shielding using wirebonds. In an exemplary aspect, a shield is formed from a series of wires (e.g., wirebonds) to create a wall and/or shielded compartment in an integrated circuit (IC) module. The wires can be located in any area within the IC module. The IC module may be overmolded with an insulating mold compound, and a top surface of the insulating mold can be ground or otherwise removed to expose ends of the wires to a shield layer which surrounds the insulating mold. Some examples may further laser ablate or otherwise form cavities around the ends of the wires to create stronger bonding between the wires of the shield and the shield layer. 1. A method for forming a shielded compartment in an integrated circuit (IC) module , comprising:providing a module substrate; placing a first series of wires to form a first wall separating the shielded compartment from a portion of the module substrate; and', 'bonding the first series of wires to a conductive plate in the module substrate;, 'forming an electromagnetic shield, comprisingdepositing an insulating mold over the module substrate; anddepositing a shield layer over the insulating mold, the shield layer contacting an exposed end of each of the first series of wires.2. The method of claim 1 , wherein bonding the first series of wires to the conductive plate further comprises bonding ends of a plurality of wire loops to the conductive plate.3. The method of claim 2 , wherein the ends of the plurality of wire loops are separated from nearby ends of the plurality of wire loops.4. The method of claim 1 , wherein the insulating mold surrounds each of the first series of wires.5. The method of claim 1 , further comprising removing a portion of the insulating mold to expose the exposed end of each of the first series of wires.6. The method of claim 5 , further comprising laser ablating a cavity in the insulating mold about each of the exposed ends of the first series of wires to ...

Apparatus with a multi-layer coating and method of forming the same

In some embodiments, a printed circuit board (PCB) comprises a substrate comprising an insulating material. The PCB further comprises a plurality of conductive tracks attached to at least one surface of the substrate. The PCB further comprises a multi-layer coating deposited on the at least one surface of the substrate. The multi-layer coating (i) covers at least a portion of the plurality of conductive tracks and (ii) comprises at least one layer formed of a halo-hydrocarbon polymer. The PCB further comprises at least one electrical component connected by a solder joint to at least one conductive track, wherein the solder joint is soldered through the multi-layer coating such that the solder joint abuts the multi-layer coating.

Halogen-hydrocarbon polymer coating

FIELD: chemistry. SUBSTANCE: invention relates to polymer coatings, namely, to a halogen-hydrocarbon polymer coating for electric devices. A printed circuit board (PCB) includes a substrate, including an insulation material. The PCB additionally includes multitudes of electroconductive printing paths, connected to at least one substrate surface. The PCB additionally includes a multi-layered coating, precipitated on at least one substrate surface. The multilayered coating covers at least a part of a multitude of the electroconductive paths and includes at least one layer of the halogen-hydrocarbon polymer. The PCB additionally includes at least one electric component, connected by a solder connection to at least one electroconductive printing path, with the solder connection being soldered through the multilayered coating in such a way that the connection adjoins the multilayered coating. EFFECT: prevention of oxidation or corrosion of metal surfaces, capable of preventing the formation of strong solder connections or capable of reducing a service term of the said connections. 39 cl, 18 dwg РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) (51) МПК H05K 1/18 H05K 3/28 H05K 3/34 C09D 4/00 C09D 185/00 C09K 15/32 (13) 2 533 162 C2 (2006.01) (2006.01) (2006.01) (2006.01) (2006.01) (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ОПИСАНИЕ (21)(22) Заявка: ИЗОБРЕТЕНИЯ К ПАТЕНТУ 2011110260/07, 11.08.2009 (24) Дата начала отсчета срока действия патента: 11.08.2009 Приоритет(ы): (30) Конвенционный приоритет: (72) Автор(ы): ХАМФРИЗ Марк Робсон (GB), ФЕРДИНАНДИ Фрэнк (GB), СМИТ Родни Эдвард (GB) 18.08.2008 GB 0815094.8; 18.08.2008 GB 0815095.5; 18.08.2008 GB 0815096.3 R U (73) Патентообладатель(и): СЕМБЛАНТ ЛИМИТЕД (GB) (43) Дата публикации заявки: 20.10.2012 Бюл. № 29 (56) Список документов, цитированных в отчете о поиске: US 3931454 A, 06.01.1976. US 2004/ (85) Дата начала рассмотрения заявки PCT на национальной фазе: 18.03.2011 C 2 C 2 0026775 A1, 12.02.2004. US 4693799 A ...

Printed board and method for production thereof

FIELD: electrical engineering.SUBSTANCE: invention relates to a halocarbon polymer coating for electrical devices. It is achieved by the fact that the printed circuit board (PCB) includes a substrate including insulating material, and additionally includes multiple electroconductive printed paths connected to at least one surface of the substrate. PP further includes a multilayer coating deposited on at least one surface of the substrate. Multilayer coating (i) covers at least part of multiple electroconductive printed paths and (ii) includes at least one layer of halocarbon polymer. PP further includes at least one electrical component, connected by soldered joint to at least one electroconductive printed path, soldered connection is soldered through multilayer coating so that soldered joint is adjacent to multilayer coating.EFFECT: technical result is protection from environmental conditions.21 cl, 16 dwg РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) (13) 2 685 692 C2 (51) МПК H05K 1/18 (2006.01) H05K 3/28 (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ОПИСАНИЕ ИЗОБРЕТЕНИЯ К ПАТЕНТУ (52) СПК H05K 1/0353 (2019.02); H05K 3/282 (2019.02) (21) (22) Заявка: 2014121727, 28.05.2014 (24) Дата начала отсчета срока действия патента: 11.08.2009 (73) Патентообладатель(и): СЕМБЛАНТ ЛИМИТЕД (GB) 23.04.2019 18.08.2008 GB 0815094.8; 18.08.2008 GB 0815095.5; 18.08.2008 GB 0815096.3 Номер и дата приоритета первоначальной заявки, из которой данная заявка выделена: 2011110260 18.08.2008 (56) Список документов, цитированных в отчете о поиске: US 2004/0026775 A1, 12.02.2004. US 391453 A, 06.01.1976. US 2008/0176096 A1, 24.07.2008. RU 2032286 C1, 27.03.1995. (43) Дата публикации заявки: 10.12.2015 Бюл. № 2 6 8 5 6 9 2 Приоритет(ы): (30) Конвенционный приоритет: R U Дата регистрации: (72) Автор(ы): ХАМФРИЗ Марк Робсон (GB), ФЕРДИНАНДИ Фрэнк (GB), СМИТ Родни Эдвард (GB) 34 C 2 R U 2 6 8 5 6 9 2 C 2 (45) Опубликовано: 23.04.2019 Бюл. № 12 Адрес для переписки: 129090, Москва, ул. Б ...

Power semiconductor device

一种表面有镀金层的金银合金键合丝及其制备方法

<b>一种表面有镀金层的金银合金键合丝及其制备方法属于微电子封装用金属键合丝技术领域，尤其涉及一种表面有镀金层的金银合金键合丝及其制备方法。本发明提供一种推拉力、抗氧化性能、键合性能好且成本低的表面有镀金层的金银合金键合丝及其制备方法。本发明表面有镀金层的金银合金键合丝包括金银合金丝，其结构要点金银合金丝表面镀有金保护层。</b>

Halo-hydrocarbon polymer coating

일부 구체예에서, 인쇄 회로 보드(PCB)는 절연재를 포함하는 기판을 포함한다. 상기 PCB는 기판의 하나 이상의 표면에 결합된 복수의 도전성 트랙을 더 포함한다. 상기 PCB는 기판의 하나 이상의 표면상에 증착된 다중층 코팅을 더 포함한다. 상기 다중층 코팅은 (i) 복수의 도전성 트랙의 적어도 일부를 커버하고, (ii) 할로-하이드로카본 폴리머로 형성된 하나 이상의 층을 포함한다. 상기 PCB는 하나 이상의 도전성 트랙에 솔더 접합에 의해 연결된 하나 이상의 전기 소자를 더 포함하며, 상기 솔더 접합은 상기 솔더 접합이 상기 다중층 코팅에 인접하도록 상기 다중층을 통해 솔더된다. In some embodiments, the printed circuit board (PCB) comprises a substrate comprising an insulating material. The PCB further includes a plurality of conductive tracks coupled to at least one surface of the substrate. The PCB further comprises a multilayer coating deposited on at least one surface of the substrate. The multilayer coating includes (i) at least a portion of a plurality of conductive tracks, and (ii) at least one layer formed of a halo-hydrocarbon polymer. The PCB further comprises at least one electrical element connected by solder bonding to the at least one conductive track, wherein the solder joint is soldered through the multilayer so that the solder joint is adjacent the multilayer coating.

Bonding wire

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Optical transmitting set packaging part and device and correlation technique with improved wire bonding

本发明公开了具有改进的引线接合的光发射器封装件和装置及相关方法。在一个实施例中，光发射器封装件可包括通过焊线电连接至电元件的至少一个发光二极管（LED）芯片。所述焊线可通过改进的引线接合参数，诸如约150℃或更低的温度、约100ms或更少的接合时间、约1700mW或更小的功率以及约100克力（gf）或更小的力或其组合来提供。

Method for fabricating semiconductor components with through wire interconnects

A method for fabricating a semiconductor component with a through wire interconnect includes the step of providing a substrate having a circuit side, a back side, and a through via. The method also includes the steps of: threading a wire through the via, forming a contact on the wire on the back side, forming a bonded contact on the wire on the circuit side, and then severing the wire from the bonded contact. The through wire interconnect includes the wire in the via, the contact on the back side and the bonded contact on the circuit side. The contact on the back side, and the bonded contact on the circuit side, permit multiple components to be stacked with electrical connections between adjacent components. A system for performing the method includes the substrate with the via, and a wire bonder having a bonding capillary configured to thread the wire through the via, and form the contact and the bonded contact. The semiconductor component can be used to form chip scale components, wafer scale components, stacked components, or interconnect components for electrically engaging or testing other semiconductor components.

Semiconductor components having encapsulated through wire interconnects (TWI)

A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) attached to the substrate contact. The through wire interconnect provides a multi level interconnect having contacts on opposing first and second sides of the semiconductor substrate. The through wire interconnect (TWI) includes a via through the substrate contact and the substrate, a wire in the via having a bonded connection with the substrate contact, a first contact on the wire proximate to the first side, and a second contact on the wire proximate to the second side. The through wire interconnect (TWI) also includes a polymer layer which partially encapsulates the through wire interconnect (TWI) while leaving the first contact exposed. The semiconductor component can be used to fabricate stacked systems, module systems and test systems. A method for fabricating the semiconductor component can include a film assisted molding process for forming the polymer layer.

Resistance welding machine and resistance welding method

Method of mounting a spring element on a semiconductor device and testing at a wafer level

Resilient contact structures (430) are mounted directly to bond pads (410) on semiconductor dies (402a, 402b), prior to the dies (402a, 402b) being singulated (separated) from a semiconductor wafer. This enables the semiconductor dies (402a, 402b) to be exercised (e.g., tested and/or burned-in) by connecting to the semiconductor dies (702, 704) with a circuit board (710) or the like having a plurality of terminals (712) disposed on a surface thereof. Subsequently, the semiconductor dies (402a, 402b) may be singulated from the semiconductor wafer, whereupon the same resilient contact structures (430) can be used to effect interconnections between the semiconductor dies and other electronic components (such as wiring substrates, semiconductor packages, etc.). Using the all-metallic composite interconnection elements (430) of the present invention as the resilient contact structures, burn-in (792) can be performed at temperatures of at least 150 DEG C, and can be completed in less than 60 minutes.

Making method of chip size semicomductor package

본 발명의 칩 사이즈 반도체 패키지(Chip Size Semiconductor Package : CSP)의 제조 방법에 관한 것으로, 반도체 칩(41)의 상면에 형성되어 있는 본딩 패드(43)들 상에 도전선(45)을 본딩하는 공정과; 상기 도전선(45)의 단부는 전해액(50) 밖으로 나오도록, 상기 구조 전체를 전해액(50)이 담겨져 있는 전해조(55)내로 투입하는 공정과; 상기 전해액(50)이 담긴 전해조(55)의 내벽에 전해질(60)을 부착하는 공정과; 상기 전해액(50) 밖으로 노출된 도전선(45)의 단부에 공통 전극이 될 도전판(65)을 부착하는 공정과; 그리고, 상기 도전판(65)과 상기 전해조의 외벽 사이를 전극으로 연결하는 공정을 포함하여 구성되어, 저난도 및 저가의 전기 도금 공정을 구현할 수 있는 효과가 있다. The present invention relates to a method for manufacturing a chip size semiconductor package (CSP) of the present invention, and to bonding the conductive lines 45 on the bonding pads 43 formed on the upper surface of the semiconductor chip 41. and; Injecting the entire structure into the electrolytic cell 55 containing the electrolytic solution 50 so that the end portion of the conductive wire 45 comes out of the electrolytic solution 50; Attaching the electrolyte 60 to an inner wall of the electrolytic cell 55 containing the electrolyte 50; Attaching a conductive plate 65 to be a common electrode to an end portion of the conductive line 45 exposed outside the electrolyte solution 50; In addition, the conductive plate 65 may be configured to include a process of connecting the conductive plate 65 and the outer wall of the electrolytic cell to an electrode, thereby implementing a low plating and low cost electroplating process.

Bonding wires for semiconductor devices

An object of the present invention is to provide a high-performance bonding wire that is suitable for semiconductor mounting technology, such as stacked chip bonding, thinning, and fine pitch mounting, where wire lean (leaning) at an upright position of a ball and spring failure can be suppressed and loop linearity and loop height stability are excellent. This bonding wire for a semiconductor device includes a core material made of a conductive metal, and a skin layer formed on the core material and containing a metal different from the core material as a main component; wherein a relationship between an average size (a) of crystal grains in the skin layer on a wire surface along a wire circumferential direction and an average size (b) of crystal grains in the core material on a normal cross section, the normal cross section being a cross section normal to a wire axis, satisfies an inequality of a/b ‰¤ 0.7.

Ball bonding metal wire bond wires to metal pads

An apparatus, and methods therefor, relates generally to an integrated circuit package. In such an apparatus, a platform substrate has a copper pad. An integrated circuit die is coupled to the platform substrate. A wire bond wire couples a contact of the integrated circuit die and the copper pad. A first end of the wire bond wire is ball bonded with a ball bond for direct contact with an upper surface of the copper pad. A second end of the wire bond wire is stitch bonded with a stitch bond to the contact.

Method and apparatus for bonding components leads to pads located on a non-rigid substrate

Component leads are bonded to pads disposed on a non-rigid substrate by the application of a combination of laser energy and ultrasonic energy. The pads preferably are bare copper pads, without a noble metal coating or a chemical pretreatment, and the non-rigid substrate is preferably an epoxy printed circuit board.

Method of temporarily, then permanently, connecting to a semiconductor device

탄성 접촉 구조물(430)은 다이(402a, 402b)들이 반도체 웨이퍼로부터 개별화(분리)되기 전에 하나의 반도체 다이(402a, 402b) 상에 패드(410)들을 결합하도록 직접 장착된다. 이는 복수개의 단자(712)가 배치된 표면을 갖는 회로 기판(710) 등을 갖춘 반도체 다이(702, 704)에 연결함으로써 반도체 다이(402a, 402b)들을 실행(예를 들어, 시험 및/또는 번인 등)시킬 수 있게 해준다. 따라서, 반도체 다이(402a, 402b)들은 반도체 웨이퍼로부터 개별화될 수 있어서, 동일한 탄성 접촉 구조물(430)이 반도체 다이들과 (와이어링 구조, 반도체 패키지 등)의 다른 전자 부품들 사이의 상호 접속을 수행하는 데 사용될 수 있다. 탄성 접촉 구조물로서 본 발명의 모든 금속성 복합 상호 접속 요소(430)를 사용함으로써 번인을 적어도 150 ℃의 온도로 60분 미만 내에서 완료할 수 있다. The elastic contact structure 430 is mounted directly to couple the pads 410 on one semiconductor die 402a, 402b before the dies 402a, 402b are singulated (separated) from the semiconductor wafer. This executes (eg, tests and / or burns in) semiconductor dies 402a, 402b by connecting them to semiconductor dies 702, 704 with a circuit board 710, etc., having a surface on which a plurality of terminals 712 are disposed. Etc.). Thus, the semiconductor dies 402a and 402b can be individualized from the semiconductor wafer, such that the same elastic contact structure 430 performs the interconnection between the semiconductor dies and other electronic components of the wiring structure, semiconductor package, etc. Can be used to By using all metallic composite interconnect elements 430 of the present invention as elastic contact structures, burn-in can be completed in less than 60 minutes at a temperature of at least 150 ° C.

Manufacture of composite bonding wire

Circuit board structure, packaging structure and method for making the same

회로 기판 구조, 패키징 구조 및 이들의 제조 방법이 개시된다. 첫째로, 제 1 기판 및 제 2 기판이 제공된다. 상기 제 1 기판은 캐리어에 부탁된 릴리즈 필름을 포함한다. 상기 제 2 기판은 솔더 마스크로 덮인 구리 필름을 포함한다. 둘째로, 상기 솔더 마스크가 패터닝된다. 이후, 상기 릴리즈 필름과 패터닝된 상기 솔더 마스크가 서로 압착되어, 상기 제 1 기판이 상기 제 2 기판에 부착된다. 이후, 제 1 패턴 및 제 2 패턴을 형성하기 위해 상기 구리 필름이 패터닝된다. 상기 제 1 패턴은 상기 릴리즈 필름과 직접 접촉하고, 상기 제 2 패턴은 패터닝된 상기 솔더 마스크와 직접 접촉한다. 이후, 회로 기판 구조를 형성하기 위해, 상기 제 1 패턴 및 상기 제 2 패턴을 덮도록 패시베이션이 형성된다. 이후에, 패키징 구조를 형성하기 위해, 상기 캐리어 상에 패키지가 형성된다.

Mounting spring elements on semiconductor devices

탄성 접촉 구조물(430)은 다이(402a, 402b)들이 반도체 웨이퍼로부터 개별화(분리)되기 전에 하나의 반도체 다이(402a, 402b) 상에 패드(410)들을 결합하도록 직접 장착된다. 이는 복수개의 단자(712)가 배치된 표면을 갖는 회로 기판(710) 등을 갖춘 반도체 다이(702, 704)에 연결함으로써 반도체 다이(402a, 402b)들을 실행(예를 들어, 시험 및/또는 번인 등)시킬 수 있게 해준다. 따라서, 반도체 다이(402a, 402b)들은 반도체 웨이퍼로부터 개별화될 수 있어서, 동일한 탄성 접촉 구조물(430)이 반도체 다이들과 (와이어링 구조, 반도체 패키지 등)의 다른 전자 부품들 사이의 상호 접속을 수행하는 데 사용될 수 있다. 탄성 접촉 구조물로서 본 발명의 모든 금속성 복합 상호 접속 요소(430)를 사용함으로써 번인을 적어도 150 ℃의 온도로 60분 미만 내에서 완료할 수 있다. The elastic contact structure 430 is mounted directly to couple the pads 410 on one semiconductor die 402a, 402b before the dies 402a, 402b are singulated (separated) from the semiconductor wafer. This executes (eg, tests and / or burns in) semiconductor dies 402a, 402b by connecting them to semiconductor dies 702, 704 with a circuit board 710, etc., having a surface on which a plurality of terminals 712 are disposed. Etc.). Thus, the semiconductor dies 402a and 402b can be individualized from the semiconductor wafer, such that the same elastic contact structure 430 performs the interconnection between the semiconductor dies and other electronic components of the wiring structure, semiconductor package, etc. Can be used to By using all metallic composite interconnect elements 430 of the present invention as elastic contact structures, burn-in can be completed in less than 60 minutes at a temperature of at least 150 ° C.

Bonding Wires for Semiconductor Devices

본 발명은 볼 직상부의 와이어 무너짐(리닝) 및 스프링 불량을 억제할 수 있고, 루프의 직선성, 루프 높이의 안정성 등에도 우수하여, 적층 칩 접속, 세선화, 협피치 실장 등의 반도체 실장 기술에도 적응하는 고기능의 본딩 와이어를 제공하는 것을 목적으로 한다. 도전성 금속으로 이루어지는 심재와, 이 심재 위에 심재와는 다른 금속을 주성분으로 하는 표피층을 가진 본딩 와이어로서, 이 표피층의 표면에 있어서의 결정립의 원주 방향의 평균 사이즈 a와, 와이어 축의 수직 단면에 있어서의 이 심재의 결정립의 평균 사이즈 b와의 관계에 대하여, a≤0.7인 반도체 장치용 본딩 와이어이다. INDUSTRIAL APPLICABILITY The present invention can suppress wire collapse (lining) and spring failure in the upper portion of a ball, and is excellent in linearity of loops, stability of loop height, and the like. It is an object of the present invention to provide a high-performance bonding wire that is adapted to. Bonding wire which has a core material which consists of an electroconductive metal, and the skin layer which has a metal other than a core material as a main component on this core material, Comprising: The average size a of the circumferential direction of the crystal grain in the surface of this skin layer, and the vertical cross section of a wire axis It is a bonding wire for semiconductor devices whose a <= 0.7 is about the relationship with the average size b of the crystal grain of this core material. 본딩 와이어, 리닝, 스프링 불량, 루프의 직진성 Bonding wires, linings, bad springs, straightness of loop

method for improving mechanical strength of gold wire

본 발명은 반도체소자의 칩패드(chip pad)와 리드프레임(leadframe)을 전기적으로 연결시키는 역할을 하는 골드와이어(gold wire)의 인장강도를 향상시킬 수 있는 방법에 관해 개시한다. 칩패드와 리드프레임 간의 전기적인 연결을 제공하는 골드와이어의 강도를 향상시키는 방법에 있어서, 개시된 본 발명은 골드와이어에 1차로 무전해 금도금처리를 실시하여 표면거칠기를 증가시키는 공정과, 표면거칠기가 증가된 골드와이어에 2차로 무전해 도금처리를 실시하여 도금층을 피복하는 공정을 포함한다.

IC package and its mounting structure

Semiconductor device and manufacturing method thereof

A semiconductor device includes plural electrode pads arranged in an active region of a semiconductor chip, and wiring layers provided below the plural electrode pads wherein occupation rates of wirings arranged within the regions of the electrode pads are, respectively, made uniform for every wiring layer. To this end, in a region where an occupation rate of wiring is smaller than those in other regions, a dummy wiring is provided. On the contrary, when the occupation rate of wiring is larger than in other regions, slits are formed in the wiring to control the wiring occupation rate. In the respective wirings layers, the shapes, sizes and intervals of wirings below the respective electrode pads are made similar or equal to one another.

Gold wire for semiconductor device bonding

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Gold wire for bonding semiconductor element and semiconductor element

Semiconductor device

Bonding wire for semiconductor device

본 발명은, 볼부의 형성성, 접합성을 개선하고, 루프 제어성도 양호하고, 웨지 접속의 접합 강도를 높이고, 공업 생산성도 확보하고, 금 와이어보다도 저렴한 구리를 주체로 하는 본딩 와이어를 제공하는 것이며, 구리를 주성분으로 하는 코어재와, 상기 코어재 상에 코어재와 다른 조성의 도전성 금속의 표피층을 갖는 본딩 와이어이며, 상기 표피층의 주성분이 금, 팔라듐, 백금, 로듐, 은 또는 니켈로부터 선택되는 2종 이상이고, 상기 표피층 내에 와이어 직경 방향으로 주성분 금속 또는 구리의 한쪽 또는 양쪽의 농도 구배를 갖는 영역이 존재하는 것을 특징으로 하는 반도체 장치용 본딩 와이어이다. SUMMARY OF THE INVENTION The present invention improves the formability and bonding properties of a ball part, improves loop controllability, improves bonding strength of wedge connection, secures industrial productivity, and provides a bonding wire mainly composed of copper, which is cheaper than gold wire. A bonding wire having a core material mainly composed of copper and a skin layer of a conductive metal having a composition different from that of the core material on the core material, wherein the main component of the skin layer is selected from gold, palladium, platinum, rhodium, silver or nickel. It is a bond wire for semiconductor devices characterized by the above-mentioned, and the area | region which has the density | concentration gradient of one or both of main component metal or copper in a wire diameter direction exists in the said skin layer. 코어재, 본딩 와이어, 볼, 네크부, 피복층 Core material, bonding wire, ball, neck part, coating layer

Bonding wire for semiconductor package and semiconductor package including the same

본 발명의 실시예에 따른 반도체 패키지용 본딩 와이어는, 은을 포함하는 코어부, 2nm 내지 23nm 두께로 상기 코어부를 둘러싸며, 금을 포함하는 쉘층을 포함한다. 본 발명의 실시예에 따른 반도체 패키지는, 제1 및 제2 전극구조를 가지는 패키지 본체, 상기 제1 및 제2 전극구조와 각각 전기적으로 연결되는 제1 및 제2 전극부를 포함하는 반도체 소자, 및 상기 제1 및 제2 전극구조 중 적어도 하나와 상기 반도체 소자를 연결하는 본딩 와이어를 포함한다.

Bond wire for semiconductor device

Bonddraht für eine Halbleitervorrichtung, wobei der Bonddraht aufweist: ein Cu-Legierungskernmaterial; und eine Pd-Überzugschicht, die auf einer Oberfläche des Cu-Legierungskernmaterials ausgebildet ist, wobei der Bonddraht wenigstens ein Element enthält, das aus Ni, Zn, Rh, In, Ir und Pt ausgewählt ist, eine Konzentration der Elemente insgesamt relativ zu dem Gesamtdraht 0,03 Massen-% oder mehr und 2 Massen-% oder weniger beträgt, wenn Kristallorientierungen auf einem Querschnitt des Kernmaterials in einer Richtung senkrecht zu einer Drahtachse des Bonddrahts gemessen werden, eine Kristallorientierung <100> mit einem Winkel von 15 Grad oder weniger zu einer Drahtachsenrichtung einen Anteil von 50% oder mehr an Kristallorientierungen in der Drahtachsenrichtung hat, und eine mittlere Kristallkorngröße in dem Querschnitt des Kernmaterials in der Richtung senkrecht zu der Drahtachse des Bonddrahts 0,9 µm oder mehr und 1,3 µm oder weniger beträgt. Bond wire for a semiconductor device, the bond wire comprising: a Cu alloy core material; and a Pd plating layer formed on a surface of the Cu alloy core material, wherein the bonding wire contains at least one element selected from Ni, Zn, Rh, In, Ir and Pt, a total concentration of the elements relative to the total wire is 0.03 mass% or more and 2 mass% or less, when crystal orientations are measured on a cross section of the core material in a direction perpendicular to a wire axis of the bonding wire, a crystal orientation <100> at an angle of 15 degrees or less to a wire axis direction accounts for 50% or more of crystal orientations in the wire axis direction, and an average crystal grain size in the cross section of the core material in the direction perpendicular to the wire axis of the bonding wire is 0.9 µm or more and 1.3 µm or less.

Gold alloy wires for semiconductor devices

System for fabricating semiconductor components with through wire interconnects

A method for fabricating a semiconductor component with a through wire interconnect includes the step of providing a substrate having a circuit side, a back side, and a through via. The method also includes the steps of: threading a wire through the via, forming a contact on the wire on the back side, forming a bonded contact on the wire on the circuit side, and then severing the wire from the bonded contact. The through wire interconnect includes the wire in the via, the contact on the back side and the bonded contact on the circuit side. The contact on the back side, and the bonded contact on the circuit side, permit multiple components to be stacked with electrical connections between adjacent components. A system for performing the method includes the substrate with the via, and a wire bonder having a bonding capillary configured to thread the wire through the via, and form the contact and the bonded contact. The semiconductor component can be used to form chip scale components, wafer scale components, stacked components, or interconnect components for electrically engaging or testing other semiconductor components.

Power semiconductor device, method for manufacturing same, and bonding wire

The present invention addresses the issue of providing: a power semiconductor device, which can be used without a problem even if heat stress is generated, and which is capable of reducing heat generated by a wire, and is capable of ensuring reliability of a bonding section even under high-temperature environments, at the time when the current capacity of the power semiconductor device is increased and the power semiconductor device is used under high-temperature environments; a method for manufacturing the power semiconductor device; and a bonding wire. In a power semiconductor device (1), a metal electrode (element electrode (3)) and the other metal electrode (connecting electrode (4)), which are on a power semiconductor element (2), are both wedge-connected by means of a metal wire (5). The metal wire (5) is an Ag wire or an Ag alloy wire having a diameter larger than 50 μm but equal to or smaller than 2 mm, and the element electrode (3) has, on the surface thereof, one or more metal layers or alloy layers, each of which has a thickness of 50 Å or more, said metal layers being composed of a metal selected from among Ni, Cr, Cu, Pd, V, Ti, Pt, Zn, Ag, Au, W, and Al, and said alloy layers being composed of metals selected from among such metals. Consequently, irrespective of the fact that the Ag wire is used, reliability of a bonding section to the electrode can be ensured, heat generated by the metal wire can be reduced when a large current is used, and heat resistance at a high temperature is improved.

Method of bonding

1,035,595. Soldering. INTERNATIONAL BUSINESS MACHINES CORPORATION. June 15, 1965 [June 26, 1964], No. 25182/65. Heading B3R. [Also in Division H1] To bond a wire to a terminal (alloyed electrode) of a semi-conductor device, its end is positioned against the terminal with the aid of the pointed tip of a carbon rod and an electrical pulse is passed through the rod and wire to form the bond without adversely affecting the semi-conductor device. The semi-conductor device may have two or four zones of opposite conductivity type and may be made of silicon or of silicon-germanium alloy, but as described is a germanium PNP transistor. The collector region of the transistor is bonded to a header using a lead-gold alloy. The upper surface of the wafer bears a lead-indium emitter pellet surrounded by a lead-antimony base ring. Emitter and base contact posts pass through insulation in the header. The leads on the header are pushed into a hand-held holder which makes electrical contact to the emitter and base posts. Wires are attached to the upper parts of the posts and terminate close to the emitter and base electrodes. A hand-held pointed carbon rod is used to push a wire into contact with its associated electrode and a current pulse passed from a capacitor, one side of which is connected to the carbon rod by a foot-operated switch and the other side of which is connected to the wire through the transistor holder. The wires are of gold-plated copper, silver-plated copper, or solid gold.

Gold-plating gold and silver palladium alloy single-crystal bonding filament and manufacturing method thereof

本发明提供了一种镀金金银钯合金单晶键合丝及其制造方法，该键合丝是以高纯银为主体材料，包括金、钯、铕、镧等微量金属材料。其组成键合丝的材料各成分重量百分比为：银含量为：97.713%-98.157%、金含量为1.8%-2.2%、钯含量为0.04%-0.08%、铕含量为：0.002%-0.004%、镧含量为0.001%-0.003%；其制造方法包括：提取纯度大于99.9999%的高纯银，制备成银合金铸锭，再制成铸态金银钯合金单晶母线，将单晶母线拉制成1mm左右的单晶丝，经热处理后在其表面电镀纯金保护层，再经精密拉拔、热处理、清洗后制成不同规格的镀金金银钯合金单晶键合丝。

SEMICONDUCTOR DEVICE WITH COPPER STRUCTURE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Halbleitervorrichtung, umfassend:einen Halbleiterkörper (100);eine Kupferstruktur (300), wobei die Kupferstruktur (300) eine Verdrahtungs/Padstruktur (340) auf dem Halbleiterkörper (100) und die Verdrahtungs/Padstruktur (340) eine obere Oberfläche (341) und eine seitliche Oberfläche (343) aufweist;eine Kupferoxidschicht (400), die die obere Oberfläche (341) und die seitliche Oberfläche (343) der Verdrahtungs/Padstruktur (340) bedeckt, wobei in der Kupferoxidschicht (400) ein Kupfergehalt zwischen 60 At.-% und 75 At.-% liegt und ein Sauerstoffgehalt zwischen 25 At.-% und 40 At.-% liegt; und wobeidie Kupferstruktur (300) einen Bonddraht (360) umfasst, der die Verdrahtungs/Padstruktur (340) mit einem Kontakt (351, 352, 353) elektrisch verbindet, und wobei die Kupferoxidschicht (400) auf dem Bonddraht (360) ausgebildet ist. A semiconductor device comprising:a semiconductor body (100);a copper structure (300), the copper structure (300) having a wiring/pad structure (340) on the semiconductor body (100) and the wiring/pad structure (340) having a top surface (341) and a side surface (343);a copper oxide layer (400) covering the top surface (341) and the side surface (343) of the wiring/pad structure (340), the copper oxide layer (400) having a copper content between 60 at. -% and 75 at.% and an oxygen content between 25 at.% and 40 at.%; and wherein the copper structure (300) includes a bond wire (360) electrically connecting the wiring/pad structure (340) to a contact (351, 352, 353), and wherein the copper oxide layer (400) is formed on the bond wire (360).

Bonding wire for power module package and method of manufacturing the same

halo polymeric coating

Process for making composite conductors

Universal surface finish for DCA SMT, and pad on pad interconnections

A printed circuit connector terminal pad coating technique is disclosed which functions as a single universal pad surface which supports multiple electrical connection practices including wirebonding, soldering, and wear resistant, pad on pad mechanical connection. The tri-plate surface treatment includes an initial diffusion resistant coating (37) of nickel; an intermediate layer (39) of hard, wear resistant noble or semi-noble metal that provides pad on pad connector reliability and affords a metallurgically stable solder joints and wirebond interfaces; and a final coating (41) of soft gold. The intermediate layer (39) may be pure palladium having a nominal thickness of 35 microinches or a layer of gold, hardened by cobalt, nickel, iron or a combination of these dopants to effect a hardness of 200 to 250 (Knoop scale) . The use of a common surface treatment for the multiple attachment processes is implemented with a single masking step, rather than a sequence of selective masking, plating and stripping operations. In the printed circuit environment, the masking is provided by the final covering that encloses, seals, and electrically insulates the conductors in a circuit board application or in the instance of a flexcable, the adhesive coated flexible coverlay (34) covers and seals the copper conductor elements while exposing the conductor terminal pads (33).

Bonding wire for semiconductor device

표면에 Pd 피복층을 갖는 Cu 본딩 와이어에 있어서, 고온 고습 환경에서의 볼 접합부의 접합 신뢰성을 개선하고, 차량 탑재용 디바이스에 적합한 본딩 와이어를 제공한다. Cu 합금 코어재와, 상기 Cu 합금 코어재의 표면에 형성된 Pd 피복층을 갖는 반도체 장치용 본딩 와이어에 있어서, 본딩 와이어가 In을 0.011∼1.2질량％ 포함하고, Pd 피복층의 두께가 0.015∼0.150㎛이다. 이에 의해, 고온 고습 환경하에서의 볼 접합부의 접합 수명을 향상시키고, 접합 신뢰성을 개선할 수 있다. Cu 합금 코어재가 Pt, Pd, Rh, Ni의 1종 이상을 각각 0.05∼1.2질량％ 함유하면, 175℃ 이상의 고온 환경에서의 볼 접합부 신뢰성을 향상시킬 수 있다. 또한, Pd 피복층의 표면에 Au 표피층을 더 형성하면 웨지 접합성이 개선된다. A Cu bonding wire having a Pd coating layer on its surface improves bonding reliability of a ball joint in a high temperature and high humidity environment and provides a bonding wire suitable for a vehicle mounting device. Cu alloy core material and a Pd coating layer formed on the surface of the Cu alloy core material, wherein the bonding wire contains 0.011 to 1.2 mass% of In and the thickness of the Pd coating layer is 0.015 to 0.150 占 퐉. This improves the bonding life of the ball joint in a high temperature and high humidity environment and improves bonding reliability. When the Cu alloy core material contains 0.05 to 1.2 mass% of at least one of Pt, Pd, Rh, and Ni, the reliability of the ball joint in a high temperature environment of 175 캜 or more can be improved. Further, when an Au skin layer is further formed on the surface of the Pd coating layer, the wedge bonding property is improved.

Wire bonding structure and method for forming same

Provided is a bonding structure of a bonding wire and a method for forming the same which can solve problems of conventional technologies in practical application of a multilayer copper wire, improve the formability and bonding characteristic of a ball portion, improve the bonding strength of wedge connection, and have a superior industrial productivity. A bonding wire mainly composed of copper, and a concentrated layer where the concentration of a conductive metal other than copper is high is formed at a ball bonded portion. The concentrated layer is formed in the vicinity of the ball bonded portion or at the interface thereof. An area where the concentration of the conductive metal is 0.05 to 20 mol % has a thickness greater than or equal to 0.1 μm, and it is preferable that the concentration of the conductive metal in the concentrated layer should be five times as much as the average concentration of the conductive metal at the ball bonded portion other than the concentrated layer.

Halo-hydrocarbon polymer coating

Semiconductor die package and method for making the same

리드 프레임 구조물과 몰딩 물질을 포함하는 프리몰딩된 기판을 포함하는 반도체 다이 패키지가 제공된다. 상기 리드 프레임 구조물은 제 1 전도부, 제 2 전도부 및 패드 영역을 갖는다. 상기 제 1 전도부와 상기 제 2 전도부 사이에 공동이 위치한다. 봉지 물질이 상기 프리몰딩된 기판 위의 반도체 다이를 덮는다. 상기 패드 영역과 상기 몰딩 물질의 외측 표면은 실질적으로 동일 평면상에 있고 상기 프리몰딩된 기판의 표면과 일치한다. A semiconductor die package is provided that includes a lead frame structure and a premolded substrate comprising a molding material. The lead frame structure has a first conductive portion, a second conductive portion and a pad region. A cavity is located between the first conductive portion and the second conductive portion. An encapsulation material covers the semiconductor die over the premolded substrate. The pad region and the outer surface of the molding material are substantially coplanar and coincide with the surface of the premolded substrate.

Semiconductor die package and method for making the same

Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.

Semiconductor device

Bonding wires for semiconductor devices

Ｃｕ合金芯材と、前記Ｃｕ合金芯材の表面に形成されたＰｄ被覆層とを有する半導体装置用ボンディングワイヤにおいて、前記ボンディングワイヤが高温環境下における接続信頼性を付与する元素を含み、下記（１）式で定義する耐力比が１．１〜１．６であることを特徴とする。耐力比＝最大耐力／０．２％耐力 （１） In a bonding wire for a semiconductor device having a Cu alloy core material and a Pd coating layer formed on the surface of the Cu alloy core material, the bonding wire contains an element that provides connection reliability in a high temperature environment, 1) The yield strength ratio defined by the formula is 1.1 to 1.6. Strength ratio = Maximum strength / 0.2% strength (1)

Semiconductor die package and method for making the same

Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.

Halo-hydrocarbon polymer coating

In some embodiments, a printed circuit board (PCB) comprises a substrate comprising an insulating material. The PCB further comprises a plurality of conductive tracks attached to at least one surface of the substrate. The PCB further comprises a multi-layer coating deposited on the at least one surface of the substrate. The multi-layer coating (i) covers at least a portion of the plurality of conductive tracks and (ii) comprises at least one layer formed of a halo-hydrocarbon polymer. The PCB further comprises at least one electrical component connected by a solder joint to at least one conductive track, wherein the solder joint is soldered through the multi-layer coating such that the solder joint abuts the multilayer coating.

Gold-coated-sliver base bonding silk thread and manufacture method thereof

本发明公开了一种以银丝线为基材、表面覆有纯金防氧化保护层的键合丝线产品，按照重量百分比金占1.8％-10.0％，其余为银；其制造方法包括：提纯、制备单晶银棒、粗拔、热处理、表面镀金、精拔、热处理、表面清洗和分卷等步骤。本发明专利摒弃了传统思维方式电镀后直接应用的落后工艺，而是先制成直径小于1mm的银丝线后，先电镀一定厚度的纯金防氧化保护层，然后再经多道次工序精密拉拔成不同规格的银基覆金键合丝线成品。本产品镀金层材质致密、均匀，与基材结合强度大幅提高，有效延长了产品保质期限；丝线硬度适中、焊接成球性好；材料成本不到纯金键合丝线的1/3；本发明专利技术可以广泛应用于复合型结构的键合丝线产品制造。