SUBSTRATE BONDING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE BY USING THE SAME

A substrate bonding method and apparatus are described. The substrate bonding apparatus is used to bond a first substrate to a second substrate. The bonding apparatus includes a first bonding chuck configured to hold the first substrate on a first surface of the first bonding chuck; a second bonding chuck configured to hold the second substrate on a second surface of the second bonding chuck, the second surface facing the first surface of the first bonding chuck; a seal arranged between the first bonding chuck and the second bonding chuck and adjacent to at least one edge of the first substrate and at least one edge of the second substrate; and a process gas supply device configured to supply a process gas to a bonding space surrounded by the seal. 1. A substrate bonding apparatus for bonding a first substrate to a second substrate , a first bonding chuck configured to hold the first substrate on a first surface of the first bonding chuck;', 'a second bonding chuck configured to hold the second substrate on a second surface of the second bonding chuck, the second surface facing the first surface of the first bonding chuck;', 'a seal arranged between the first bonding chuck and the second bonding chuck and adjacent to at least one edge of the first substrate and at least one edge of the second substrate, and configured to enclose a bonding space; and', 'a process gas supply device configured to supply a process gas to the bonding space enclosed by the seal., 'the substrate bonding apparatus comprising2. The substrate bonding apparatus of claim 1 , whereina first portion of the seal is detachably coupled to the first bonding chuck, anda second portion of the seal is coupled to the second bonding chuck, the second portion of the seal being opposite the first portion of the seal.3. The substrate bonding apparatus of claim 2 , whereinthe first bonding chuck comprises a vacuum groove, andthe substrate bonding apparatus further comprises a vacuum pump configured to provide ...

Bonding alignment marks at bonding interface

Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a method for forming a semiconductor device is disclosed. A first device layer is formed on a first substrate. A first bonding layer including a first bonding contact and a first bonding alignment mark is formed above the first device layer. A second device layer is formed on a second substrate. A second bonding layer including a second bonding contact and a second bonding alignment mark is formed above the second device layer. The first bonding alignment mark is aligned with the second bonding alignment mark, such that the first bonding contact is aligned with the second bonding contact. The first substrate and the second substrate are bonded in a face-to-face manner, so that the first bonding contact is in contact with the second bonding contact at a bonding interface, and the first bonding alignment mark is in contact with the second bonding alignment mark at the bonding interface.

SEMICONDUCTOR STORAGE DEVICE

A semiconductor storage device includes first and second chips. The first chip includes memory cells provided on a first substrate in a memory cell region, a plurality of first pads provided on a first surface of the first substrate and disposed in an edge region of the first chip that surrounds the memory cell region, and a first conductive layer provided on the first substrate and electrically connected to the first pads. The second chip includes a first circuit provided on a second substrate in a circuit region, a plurality of second pads provided on the second substrate and disposed in an edge region of the second chip that surrounds the circuit region, and a second conductive layer provided on the second substrate and electrically connected to the second pads. The first pads of the first chip and the second pads of the second chip are bonded facing each other. 1. A semiconductor storage device comprising: a plurality of memory cells provided on a first substrate in a memory cell region,', 'a plurality of first pads provided on a first surface of the first substrate and disposed in an edge region of the first chip that surrounds the memory cell region, and', 'a first conductive layer provided on the first substrate and electrically connected to the first pads; and, 'a first chip including'} a first circuit provided on a second substrate in a circuit region,', 'a plurality of second pads provided on the second substrate and disposed in an edge region of the second chip that surrounds the circuit region, and', 'a second conductive layer provided on the second substrate and electrically connected to the second pads,, 'a second chip including'}wherein the first pads of the first chip and the second pads of the second chip are bonded facing each other.2. The semiconductor storage device according to claim 1 , wherein the first pads claim 1 , the first conductive layer claim 1 , the second pads claim 1 , and the second conductive layer are electrically insulated from ...

Bonding alignment marks at bonding interface

Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a bonded structure includes a first bonding layer including a first bonding contact and a first bonding alignment mark, a second bonding layer including a second bonding contact and a second bonding alignment mark, and a bonding interface between the first bonding layer and the second bonding layer. The first bonding alignment mark is aligned with the second bonding alignment mark at the bonding interface, such that the first bonding contact is aligned with the second bonding contact at the bonding interface. The first bonding alignment mark includes a plurality of first repetitive patterns. The second bonding alignment mark includes a plurality of second repetitive patterns different from the plurality of first repetitive patterns.

Electrical overlay measurement methods and structures for wafer-to-wafer bonding

Alignment of a first wafer bonded to a second wafer can be determined using electrical wafer alignment methods. A wafer stack can be formed by overlaying a second wafer over a first wafer such that second metal bonding pads of the second wafer contact first metal bonding pads of the first wafer. A leakage current or a capacitance measurement step is performed between first alignment diagnostic structures in the first wafer and second alignment diagnostic structures in the second wafer for multiple mating pairs of first semiconductor dies in the first wafer and second semiconductor dies in the second wafer to determine the alignment.

Electrical overlay measurement methods and structures for wafer-to-wafer bonding

A method includes providing a first wafer including a respective set of first metal bonding pads and at least one first alignment diagnostic structure, providing a second wafer including a respective set of second metal bonding pads and a respective set of second alignment diagnostic structures, overlaying the first wafer and the second wafer, measuring at least one of a current, voltage or contact resistance between the first alignment diagnostic structures and the second alignment diagnostic structures to determine an overlay offset, and bonding the second wafer to the first wafer.

SEMICONDUCTOR MANUFACTURING APPARATUSES AND METHODS THEREOF

A semiconductor manufacturing apparatus may include: a pickup unit configured to pick up a chip in a first region of the semiconductor manufacturing apparatus; a bonding head configured to receive the picked-up chip and configured to move from the first region to a top of a circuit board in a second region of the semiconductor manufacturing apparatus; and/or an optical unit configured to detect a bonding position on the circuit board while moving from the first region to the second region. A semiconductor manufacturing apparatus may include: a bonding head including a heater for heating a chip and bonding the chip onto a circuit board; and/or a cooling block, adjacent to the heater, through which cooling liquid flows. The cooling liquid may be removed from the cooling block while the heater generates heat. The cooling liquid may be supplied to the cooling block while the heater is cooled. 1. A semiconductor manufacturing apparatus , comprising:a pickup unit configured to pick up a chip in a first region of the semiconductor manufacturing apparatus;a bonding head configured to receive the picked-up chip and configured to move from the first region to a top of a circuit board in a second region of the semiconductor manufacturing apparatus; andan optical unit configured to detect a bonding position on the circuit board while moving from the first region to the second region.2. The semiconductor manufacturing apparatus of claim 1 , wherein the optical unit is on an upper portion of the circuit board while the bonding head moves from the first region to the second region.3. The semiconductor manufacturing apparatus of claim 1 , wherein the bonding head bonds the chip at the detected bonding position after the bonding head reaches the second region.4. The semiconductor manufacturing apparatus of claim 1 , further comprising:a gantry frame having a hollow therein;wherein the bonding head is configured to move in the hollow, andwherein the bonding head is configured to move ...

METHOD FOR BONDING WAFERS AND BONDING TOOL

A method is provided and includes the following steps. A first wafer is coupled to a first support of a bonding tool and a second wafer is coupled to a second support of the bonding tool. The second wafer is bonded to the first wafer with the first wafer coupled to the first support. Whether a bubble is between the bonded first and second wafers in the bonding tool is detected. 1. A method comprising:coupling a first wafer to a first support of a bonding tool and coupling a second wafer to a second support of the bonding tool;bonding the second wafer to the first wafer with the first wafer coupled to the first support; anddetecting whether a bubble is between the bonded first and second wafers in the bonding tool, wherein detecting whether a bubble is between the bonded first and second wafers is in a same chamber of the bonding tool as bonding the second wafer to the first wafer.2. The method of claim 1 , wherein the detecting comprises performing an optical detection.3. The method of claim 1 , wherein the detecting is performed by Fourier transform infrared microscopy (FTIR) claim 1 , xray reflection (XRR) claim 1 , nuclear reaction analysis (NRA) claim 1 , or combinations thereof.4. The method of claim 1 , further comprising:cleaning a chamber of the bonding tool accommodating the first and second supports when the bubble is detected between the bonded first and second wafers.5. The method of claim 4 , wherein loading of a third wafer is deferred until the cleaning completes.6. The method of claim 1 , wherein the detecting comprises capturing an image of the bonded first and second wafers by an infrared camera.7. The method of claim 1 , wherein the bonding comprises:releasing the second wafer from the second support such that the second wafer is bonded to the first wafer, wherein the detecting is performed after the releasing.8. The method of claim 1 , wherein the detecting is performed with the bonded first and second wafers coupled to the first support.9. The ...

CONNECTIVITY DETECTION FOR WAFER-TO-WAFER ALIGNMENT AND BONDING

A first workpiece includes first active pads, a first test pad, and a second test pad on a primary surface of the first workpiece, the first test pad electrically connected to the second test pad. A second workpiece includes second active pads, a third test pad, and a fourth test pad on a primary surface of the second workpiece. The first and second workpieces are bonded along an interface between the primary surface of the first workpiece and the primary surface of the second workpiece to bond the first active pads with the second active pads, bond the first test pad with the third test pad, and bond the second test pad with the fourth test pad. Connectivity detection circuits test electrical connectivity between the third test pad and the fourth test pad 1. An apparatus , comprising:a first workpiece including first active pads, a first test pad, and a second test pad on a primary surface of the first workpiece, the first test pad electrically connected to the second test pad;a second workpiece including second active pads, a third test pad, and a fourth test pad on a primary surface of the second workpiece, the first and second workpieces bonded along an interface between the primary surface of the first workpiece and the primary surface of the second workpiece to bond the first active pads with the second active pads, bond the first test pad with the third test pad, and bond the second test pad with the fourth test pad; andconnectivity detection circuits to test electrical connectivity between the third test pad and the fourth test pad.2. The apparatus of wherein the connectivity detection circuits are in the second workpiece.3. The apparatus of wherein the connectivity detection circuits include a comparator to compare a voltage at the fourth test pad with a reference voltage.4. The apparatus of wherein the connectivity detection circuits further include a multiplexer to selectively couple the third test pad and the fourth test pad to compare voltages at the ...

Bond enhancement structure in microelectronics for trapping contaminants during direct-bonding processes

Structures and techniques provide bond enhancement in microelectronics by trapping contaminants and byproducts during bonding processes, and arresting cracks. Example bonding surfaces are provided with recesses, sinks, traps, or cavities to capture small particles and gaseous byproducts of bonding that would otherwise create detrimental voids between microscale surfaces being joined, and to arrest cracks. Such random voids would compromise bond integrity and electrical conductivity of interconnects being bonded. In example systems, a predesigned recess space or predesigned pattern of recesses placed in the bonding interface captures particles and gases, reducing the formation of random voids, thereby improving and protecting the bond as it forms. The recess space or pattern of recesses may be placed where particles collect on the bonding surface, through example methods of determining where mobilized particles move during bond wave propagation. A recess may be repeated in a stepped reticule pattern at the wafer level, for example, or placed by an aligner or alignment process.

Method and measuring device for determining the path of a coupled wave

본 발명은 제1 기판(2)과 제2 기판(4) 사이의 갭(3)에서 결합파의 경로를 결정하기 위한 측정 장치에 관한 것이다. 또한, 본 발명은 그에 상응하는 방법에 관한 것이다.

Structure of semiconductor device and method for bonding two substrates

A structure of semiconductor device is provided, including a first circuit structure, formed on a first substrate. A first test pad is disposed on the first substrate. A second circuit structure is formed on a second substrate. A second test pad is disposed on the second substrate. A first bonding pad of the first circuit structure is bonded to a second bonding pad of the second circuit structure. One of the first test pad and the second test pad is an inner pad while another one of the first test pad and the second test pad is an outer pad, wherein the outer pad surrounds the inner pad.

Semiconductor storage device including first pads on a first chip that are bonded to second pads on a second chip

A semiconductor storage device includes first and second chips. The first chip includes memory cells provided on a first substrate in a memory cell region, a plurality of first pads provided on a first surface of the first substrate and disposed in an edge region of the first chip that surrounds the memory cell region, and a first conductive layer provided on the first substrate and electrically connected to the first pads. The second chip includes a first circuit provided on a second substrate in a circuit region, a plurality of second pads provided on the second substrate and disposed in an edge region of the second chip that surrounds the circuit region, and a second conductive layer provided on the second substrate and electrically connected to the second pads. The first pads of the first chip and the second pads of the second chip are bonded facing each other.

Enhancing bonding in microelectronic structures by trapping contaminants and preventing cracks during direct bonding processes

结构和技术可以通过在键合工艺期间捕获污染物和副产物并阻止裂纹来提供微电子结构中的键合增强。示例键合表面被提供有凹部、凹陷、阱或腔，以捕获键合的小颗粒和气态副产物并阻止裂纹，小颗粒和气态副产物将在被接合的微米级表面之间创建有害的空隙。这样的随机空隙将损害键合的完整性以及被键合互连件的电导率。在示例系统中，键合界面中放置的经预先设计的凹部空间或经预先设计的凹部图案捕获颗粒和气体，从而减少了随机空隙的形成，从而在键合形成时改进并保护键合。可以通过用于确定移动的颗粒在键合波传播期间移动的位置的示例方法，来将凹部空间或凹部图案放置在颗粒在键合表面上聚集的位置。例如，凹部可以以晶片级阶梯状的刻线图案来重复，或者通过对准器或对准工艺来放置。

Processes and applications for catalyst influenced chemical etching

A system for assembling fields from a source substrate onto a second substrate. The source substrate includes fields. The system further includes a transfer chuck that is used to pick at least four of the fields from the source substrate in parallel to be transferred to the second substrate, where the relative positions of the at least four of the fields is redetermined.

Joining method, item to be joined, and joining device

A joining device (1), on the basis of an amount of misalignment of a chip (CP) relative to a substrate (WT), adjusts the relative position of the chip (CP) to the substrate (WT) and then causes the chip (CP) to contact the substrate (WT). Thereafter, in a state in which the chip (CP) and the substrate (WT) are in contact with each other, the joining device (1) measures the amount of misalignment of the chip (CP) relative to the substrate (WT) and, on the basis of the measured amount of misalignment, causes the chip (CP) to be moved relative to the substrate (WT) for correction so as to reduce the amount of misalignment. Then, the joining device (1), if the amount of misalignment of the chip (CP) relative to the substrate (WT) is less than or equal to a misalignment amount threshold, irradiates a resin portion of the chip (CP) with ultraviolet radiation to cure the resin portion and to fix the chip (CP) onto the substrate (WT).

Semiconductor memory device with a plurality of memory cells

实施方式提供一种能够提高动作的可靠性的半导体存储装置。实施方式的半导体存储装置具备存储器阵列芯片(300)及周边电路芯片(200)，该存储器阵列芯片(300)包含：多个存储单元，设置在第1衬底；多个第1焊垫，设置在第1衬底上，且以包围多个存储单元的方式配置；及第1导电层，设置在第1衬底上，且电连接于第1焊垫；该周边电路芯片(200)包含：周边电路，设置在第2衬底；多个第2焊垫，设置在第2衬底上，且以包围周边电路的方式配置；及第2导电层，设置在第2衬底上，且电连接于第2焊垫。存储器阵列芯片(300)的第1焊垫与周边电路芯片的第2焊垫以对向的方式贴合。

Integrated circuit package and method

In an embodiment, a method includes: bonding a back side of a first memory device to a front side of a second memory device with dielectric-to-dielectric bonds and with metal-to-metal bonds; after the bonding, forming first conductive bumps through a first dielectric layer at a front side of the first memory device, the first conductive bumps raised from a major surface of the first dielectric layer; testing the first memory device and the second memory device using the first conductive bumps; and after the testing, attaching a logic device to the first conductive bumps with reflowable connectors.

Device and method for aligning substrates

Die Erfindung betrifft eine Vorrichtung und ein Verfahren zum Ausrichten von Substraten.

Method for bonding substrates together, and substrate bonding device

A production of voids between substrates is prevented when the substrates are bonded together, and the substrates are bonded together at a high positional precision while suppressing a strain. A method for bonding a first substrate and a second substrate includes a step of performing hydrophilization treatment to cause water or an OH containing substance to adhere to bonding surface of the first substrate and the bonding surface of the second substrate, a step of disposing the first substrate and the second substrate with the respective bonding surfaces facing each other, and bowing the first substrate in such a way that a central portion of the bonding surface protrudes toward the second substrate side relative to an outer circumferential portion of the bonding surface, a step of abutting the bonding surface of the first substrate with the bonding surface of the second substrate at the respective central portions, and a step of abutting the bonding surface of the first substrate with the bonding surface of the second substrate across the entirety of the bonding surfaces, decreasing a distance between the outer circumferential portion of the first substrate and an outer circumferential portion of the second substrate with the respective central portions abutting each other at a pressure that maintains a non-bonded condition,.

Measuring device and method for determining the course of joining waves

Distortion-compensated wafer bonding method and apparatus using a temperature-controlled backside thermal expansion layer

A bonded structure may be formed by measuring die areas of first semiconductor dies on a wafer at a measurement temperature, generating a two-dimensional map of local target temperatures that are estimated to thermally adjust a die area of each of the first semiconductor dies to a target die area, loading the wafer to a bonding apparatus comprising at least one temperature sensor, and iteratively bonding a plurality of second semiconductor dies to a respective one of the first semiconductor dies by sequentially adjusting a temperature of the wafer to a local target temperature of a respective first semiconductor die that is bonded to a respective one of the second semiconductor dies. An apparatus for forming such a bonded structure may include a computer, a chuck for holding the wafer, a die attachment unit, and a temperature control mechanism.

Substrate bonding apparatus

描述了一种基底键合设备。所述基底键合设备用于将第一基底键合到第二基底。所述基底键合设备包括：第一键合吸盘，被构造为将第一基底保持在第一键合吸盘的第一表面上；第二键合吸盘，被构造为将第二基底保持在第二键合吸盘的第二表面上，第二表面面对第一键合吸盘的第一表面；密封件，布置在第一键合吸盘与第二键合吸盘之间且与第一基底的至少一个边缘和第二基底的至少一个边缘相邻；以及处理气体供应装置，被构造为向被密封件围绕的键合空间供应处理气体。

Device and method for aligning substrates

The invention relates to a device and a method for aligning substrates.

Manufacturing apparatus, operation method thereof, and method for manufacturing semiconductor device

According to one embodiment, a manufacturing apparatus includes: a storage configured to store a work; a transfer arm configured to transfer the work; a hot bath configured to store a liquid; a mounting table configured to mount the work in the hot bath; and an upper arm configured to apply pressure to the work mounted on the mounting table.

Apparatus for bonding chip and method for bonding chip using the same

본 발명의 실시예에 따른 칩 본딩 장치는 바디와, 상기 바디에 설치되어 기판을 이송하는 기판 이송 유닛과, 상기 바디의 상면에 배치되는 본드 헤드 이송 유닛과, 상기 바디에 설치되며 상기 기판의 위치 및 칩의 위치를 확인하는 정렬 유닛 및 상기 본드 헤드 이송 유닛에 설치되어 이동되며 하부에 칩을 흡착하는 본드 헤드를 포함하며, 상기 본드 헤드는 하단부에 칩을 흡착하는 칩 본딩부를 구비하며, 상기 칩 본딩부는 설치홈이 형성되는 칩 본딩부 바디와, 상기 설치홈에 일단부가 삽입 배치되는 푸싱 모듈 및 상기 푸싱 모듈에 의해 변형되는 변형부재를 구비하는 부착 모듈을 포함하며, 상기 변형부재에는 상기 푸싱 모듈에 의해 가압되어 변형되며 저면에 칩이 흡착되는 변형부가 구비될 수 있다.

다이 본딩 방법 및 다이 본딩 장치

본 발명의 실시예는 각 다이의 품질을 고려한 본딩을 통해 칩의 품질을 일정하게 관리할 수 있는 다이 본딩 방법 및 다이 본딩 장치를 제공한다. 본 발명에 따른 다이 본딩 방법은, 웨이퍼에 위치하는 각 다이의 품질에 대한 등급 정보를 획득하는 단계와, 상기 웨이퍼에서 다이를 픽업하는 단계와, 기판에서 상기 픽업된 다이의 등급에 대응하는 본딩 위치를 확인하는 단계와, 상기 본딩 위치에 상기 다이를 본딩하는 단계를 포함한다.

裸片绑定方法以及裸片绑定装置

本发明的实施例提供通过考虑了各裸片质量的绑定能够恒定地管理芯片质量的裸片绑定方法以及裸片绑定装置。根据本发明的裸片绑定方法包括：获取位于晶圆的各裸片的质量的等级信息的步骤；从所述晶圆拾取裸片的步骤；在基板中确认与所述拾取的裸片的等级对应的绑定位置的步骤；以及在所述绑定位置绑定所述裸片的步骤。

접합 장치, 접합 시스템 및 접합 방법

본 개시에 따른 접합 장치(41, 41A, 41B)는, 기판끼리를 접합하는 접합 장치로서, 제 1 유지부(110)와, 제 2 유지부(120)와, 이동부(130)와, 하우징(100)과, 간섭계(160, 170)와, 제 1 가스 공급부(140, 140B)와, 제 2 가스 공급부(180, 180A)를 구비한다. 제 1 유지부(110)는, 제 1 기판(W1)을 상방으로부터 흡착 유지한다. 제 2 유지부(120)는, 제 2 기판(W2)을 하방으로부터 흡착 유지한다. 이동부(130)는, 제 1 유지부(110) 및 제 2 유지부(120)의 일방을 타방에 대하여 수평 방향으로 이동시킨다. 하우징(100)은, 제 1 유지부(110), 제 2 유지부(120) 및 이동부(130)를 수용한다. 간섭계(160, 170)는, 하우징(100)의 내부에 배치되어, 상기 일방 또는 상기 일방과 함께 이동하는 물체에 대하여 광을 조사함으로써 상기 일방 또는 물체까지의 수평 거리를 측정한다. 제 1 가스 공급부(140, 140B)는, 하우징(100)의 내부에 대하여, 청정화된 제 1 가스를 공급한다. 제 2 가스 공급부(180, 180A)는, 광이 조사되는 상기 일방 또는 상기 물체와 간섭계(160, 170)와의 사이의 공간에 대하여 제 2 가스를 공급한다.

半导体器件及其形成方法

在实施例中，一种器件包括：第一管芯阵列，包括第一集成电路管芯，第一集成电路管芯的取向沿着第一管芯阵列的行和列交替；第一介电层，围绕第一集成电路管芯，第一介电层和第一集成电路管芯的表面是平坦的；第二管芯阵列，包括位于第一介电层和第一集成电路管芯上的第二集成电路管芯，第二集成电路管芯的取向沿着第二管芯阵列的行和列交替，第二集成电路管芯的前侧通过金属对金属接合和通过电介质对电介质接合而接合至第一集成电路管芯的前侧；以及第二介电层，围绕第二集成电路管芯，第二介电层和第二集成电路管芯的表面是平坦的。本发明的实施例还涉及半导体器件及其形成方法。

촉매 영향 화학적 에칭을 위한 공정 및 응용

소스 기판의 필드를 제2 기판에 조립하기 위한 시스템이 제공된다. 소스 기판은 필드를 포함한다. 시스템은 상기 소스 기판의 상기 복수의 필드 중 적어도 4개를 선택하여 병렬로 상기 제2 기판으로 이송하는데 사용되는 이송 척을 더 포함하며, 상기 복수의 필드 중 상기 적어도 4개의 상대 위치는 미리 결정된다.

Bonding apparatus, bonding system, and bonding method

A bonding apparatus includes a first holder, a second holder, a moving unit, a housing, an interferometer, a first gas supply and a second gas supply. The first holder is configured to attract and hold a first substrate. The second holder is configured to attract and hold a second substrate. The moving unit is configured to move a first one of the first holder and the second holder in a horizontal direction with respect to a second one thereof. The interferometer is configured to radiate light to the first one or an object moved along with the first one to measure a horizontal distance thereto. The first gas supply is configured to supply a clean first gas to an inside of the housing. The second gas supply is configured to supply a second gas to a space between the interferometer and the first one or the object.

하이브리드 본딩 장치 및 이를 이용하는 하이브리드 본딩 방법

본 발명은 칩플라이를 방지하고 생산성을 높일 수 있는 하이브리드 본딩 장치 및 이를 이용하는 하이브리드 본딩 방법에 관한 발명이다. 본 발명의 일 실시예에 따른 하이브리드 본딩 장치는 복수 개의 챔버 및 상기 복수 개의 챔버 사이에서 웨이퍼를 이동시키고 본딩된 웨이퍼를 어닐링 챔버로 이동시키는 이동부를 포함하는 하이브리드 본딩 장치로서, 상기 복수 개의 챔버는 복수 개의 상기 웨이퍼를 보관하는 웨이퍼 공급부, 상기 웨이퍼를 본딩하는 본딩부 및 제어부를 포함하고, 상기 본딩부는 기판용 웨이퍼 상에 다이를 본딩하여 웨이퍼 레이어를 형성하는 본더 및 상기 웨이퍼 레이어를 1차 어닐링하는 프리 어닐링 오븐을 포함할 수 있다.

Bonding system and bonding method

Embodiments of the present disclosure provide a bonding system and a bonding method. The bonding system includes a bonding assembly, a wafer stage, a first alignment assembly and a second alignment assembly. The wafer stage is configured to drive, according to a first deviation value determined by the first alignment assembly and a second deviation value determined by the second alignment assembly, a carried wafer to move so as to align a second die with a first die. The bonding assembly is configured to bond the first die to the second die. The bonding system further includes a third alignment assembly located at a side of the wafer stage away from the bonding assembly, and configured to determine a third deviation value between positions of the first die and the second die which have been bonded. The bonding assembly is further configured to debond the first die from the second die, in response to that the third deviation value is greater than a preset threshold.

Semiconductor die, semiconductor wafer, semiconductor device including the semiconductor die and method of manufacturing the semiconductor device

A semiconductor die includes first pads, switches that are electrically connected with the first pads, respectively, a test signal generator that generates test signals and to transmit the test signals to the switches, internal circuits that receive first signals through the first pads and the switches, to perform operations based on the first signals, and to output second signals through the switches and the first pads based on a result of the operations, and a switch controller that controls the switches so that the first pads communicate with the test signal generator during a test operation and that the first pads communicate with the internal circuits after a completion of the test operation.

Bonding method, bonded article, and bonding device

System and Method for Bonding Semiconductor Devices

A method includes determining a first offset between a first alignment mark on a first side of a first wafer and a second alignment mark on a second side of the first wafer; aligning the first alignment mark of the first wafer to a third alignment mark on a first side of a second wafer, which includes detecting a location of the second alignment mark of the first wafer; determining a location of the first alignment mark of the first wafer based on the first offset and the location of the second alignment mark of the first wafer; and, based on the determined location of the first alignment mark, repositioning the first wafer to align the first alignment mark to the third alignment mark; and bonding the first side of the first wafer to the first side of the second wafer to form a bonded structure.

具有連續密封環的堆疊晶圓封裝結構及其形成方法

本發明提供一種封裝結構。該封裝結構包含一底部晶粒及一頂部晶粒。該底部晶粒包含：一第一主動區，其由一第一密封環區包圍；一第一密封環區，其包含一底部密封環；及一第一接合層，其經安置於該底部晶粒之一前側上。該頂部晶粒包含：一第二主動區，其由一第二密封環區包圍；一第二密封環區，其包含一頂部密封環；及一第二接合層，其安置於該頂部晶粒之一前側上。該底部晶粒及該頂部晶粒在其等之間之一界面處透過該第一接合層與該第二接合層之間的混合接合來接合，使得該底部密封環與該頂部密封環垂直對準且可操作以形成一連續密封環。

存储装置和制造存储装置的方法

一种存储装置包括：存储芯片，所述存储芯片包括连接到第一字线和第一位线的存储单元阵列、分别连接到所述第一字线的第一字线接合焊盘以及分别连接到所述第一位线的第一位线接合焊盘；以及外围电路芯片，其中，所述外围电路芯片包括连接到第二字线和第二位线的测试单元阵列、分别连接到所述第一字线接合焊盘的第二字线接合焊盘、分别连接到所述第一位线接合焊盘的第二位线接合焊盘以及外围电路，所述外围电路连接到所述第二字线接合焊盘和所述第二字线，或所述第二位线接合焊盘和所述第二位线。

Memory device including memory chip and peripheral memory chip and method of manufacturing the memory device

A memory device includes a memory chip including a memory cell array connected to first word lines and first bit lines, first word line bonding pads respectively connected to the first word lines, and first bit line bonding pads respectively connected to the first bit lines, and a peripheral circuit chip, wherein the peripheral circuit chip includes a test cell array connected to second word lines and second bit lines, second word line bonding pads respectively connected to the first word line bonding pads, second bit line bonding pads respectively connected to the first bit line bonding pads, and a peripheral circuit connected to the second word line bonding pads and the second word lines or the second bit line bonding pads and the second bit lines.

Bond enhancement structure in microelectronics for trapping contaminants during direct-bonding processes

Structures and techniques provide bond enhancement in microelectronics by trapping contaminants and byproducts during bonding processes, and arresting cracks. Example bonding surfaces are provided with recesses, sinks, traps, or cavities to capture small particles and gaseous byproducts of bonding that would otherwise create detrimental voids between microscale surfaces being joined, and to arrest cracks. Such random voids would compromise bond integrity and electrical conductivity of interconnects being bonded. In example systems, a predesigned recess space or predesigned pattern of recesses placed in the bonding interface captures particles and gases, reducing the formation of random voids, thereby improving and protecting the bond as it forms. The recess space or pattern of recesses may be placed where particles collect on the bonding surface, through example methods of determining where mobilized particles move during bond wave propagation. A recess may be repeated in a stepped reticule pattern at the wafer level, for example, or placed by an aligner or alignment process.

접합 장치, 접합 시스템, 접합 방법 및 컴퓨터 기억 매체

본 발명은, 기판의 접합 처리의 상태를 검사하여, 당해 접합 처리를 적절하게 행하는 것이다. 상부 웨이퍼(W U )와 하부 웨이퍼(W L )를 접합하는 접합 장치는, 하면에 상부 웨이퍼(W U )를 진공화해서 흡착 유지하는 상부 척(140)과, 상부 척(140)의 하방에 설치되고, 상면에 하부 웨이퍼(W L )를 진공화해서 흡착 유지하는 하부 척(141)과, 상부 척(140)에 설치되고, 상부 웨이퍼(W U )의 중심부를 가압하는 압동 부재(190)와, 상부 척(140)에 설치되고, 상부 척(140)으로부터 상부 웨이퍼(W U )의 이탈을 검출하는 복수의 센서(175)를 갖는다.

Flip-chip bonding apparatus and method of using the same

A flip-chip bonding method includes following operations. A wafer is provided with multiple semiconductor dies on an adhesive film held by a frame element. A semiconductor die is lifted up from the wafer by an ejector element. The semiconductor die is picked up with a collector element. The semiconductor die is flip-chipped with the collector element. An alignment check is performed to determine a position of the semiconductor die, so as to determine a process tolerance between a center of the collector element and a center of the semiconductor die. The semiconductor die with the collector element is transferred to a location underneath a bonder element based on the process tolerance of the alignment check. The semiconductor die is picked up from the collector element by the bonder element. The semiconductor die is bonded to a carrier by the bonder element.

Semiconductor device and manufacturing method thereof

A device includes a first semiconductor substrate and a second semiconductor substrate. A first insulating film is provided on a first face of the first semiconductor substrate. A first metal layer covers an inner surface of a first grove provided on the first insulating film. A first electrode is provided on the first metal layer and embedded in the first groove. The second semiconductor substrate has a second face facing the first face of the first semiconductor substrate. A second insulating film is provided on the second face of the second semiconductor substrate and is attached to the first insulating film. A second electrode is embedded in a second groove provided on the second insulating film and is connected to the first electrode. An end part of the first metal layer is recessed toward the first semiconductor substrate relative to a surface of the first insulating film.

晶片结合装置和包括晶片结合装置的晶片结合系统

本发明提供一种晶片结合装置，用于在晶片结合工艺和/或包括所述晶片结合装置的晶片结合系统中精确地检测晶片的结合状态。所述晶片结合装置包括：第一支撑板，包括第一表面和用于真空吸附在第一表面上设置的第一晶片的真空槽；第二支撑板，包括面对第一表面的第二表面。第二晶片在第二表面上。所述晶片结合装置和/或所述晶片结合系统包括位于第一支撑板的中心部分处的结合引发器和位于第一支撑板上的区域传感器，所述区域传感器被配置为检测第一晶片与第二晶片之间的结合的传播状态。

Bonding apparatus, bonding system, bonding method and storage medium

There is provided a bonding apparatus for bonding substrates together, which includes: a first holding part configured to adsorptively hold a first substrate by vacuum-drawing the first substrate on a lower surface of the first substrate; a second holding part provided below the first holding part and configured to adsorptively hold a second substrate by vacuum-drawing the second substrate on an upper surface of the second substrate; a pressing member provided in the first holding part and configured to press a central portion of the first substrate; and a plurality of substrate detection parts provided in the first holding part and configured to detect a detachment of the first substrate from the first holding part.

Bonding Apparatus, Bonding System, Bonding Method and Storage Medium

There is provided a bonding apparatus for bonding substrates together, which includes: a first holding part configured to adsorptively hold a first substrate by vacuum-drawing the first substrate on a lower surface of the first substrate; a second holding part provided below the first holding part and configured to adsorptively hold a second substrate by vacuum-drawing the second substrate on an upper surface of the second substrate; a pressing member provided in the first holding part and configured to press a central portion of the first substrate; and a plurality of substrate detection parts provided in the first holding part and configured to detect a detachment of the first substrate from the first holding part.

半導體結構的製造方法

一種半導體結構的製造方法，包括以下步驟。提供第一基底。在第一基底上形成第一介電結構。在第一介電結構中形成至少一個第一凹洞。在第一凹洞中形成第一應力調整層。第一應力調整層覆蓋第一介電結構。提供第二基底。在第二基底上形成第二介電結構。在第二介電結構中形成至少一個第二凹洞。在第二凹洞中形成第二應力調整層。第二應力調整層覆蓋第二介電結構。將第一應力調整層與第二應力調整層進行接合。

Apparatus for measuring an adhesion force

An apparatus for measuring an adhesion force, the apparatus comprising a stage configured to support a specimen, and a sensor adhered to the specimen, wherein the sensor detects the adhesion force of the specimen, the adhesion force of the specimen being a force for detaching the sensor from the specimen.

半导体存储装置

实施方式提供一种能够提高动作的可靠性的半导体存储装置。实施方式的半导体存储装置具备存储器阵列芯片(300)及周边电路芯片(200)，该存储器阵列芯片(300)包含：多个存储单元，设置在第1衬底；多个第1焊垫，设置在第1衬底上，且以包围多个存储单元的方式配置；及第1导电层，设置在第1衬底上，且电连接于第1焊垫；该周边电路芯片(200)包含：周边电路，设置在第2衬底；多个第2焊垫，设置在第2衬底上，且以包围周边电路的方式配置；及第2导电层，设置在第2衬底上，且电连接于第2焊垫。存储器阵列芯片(300)的第1焊垫与周边电路芯片的第2焊垫以对向的方式贴合。

Processes and applications for catalyst influenced chemical etching

A system for assembling fields from a source substrate onto a second substrate. The source substrate includes fields. The system further includes a transfer chuck that is used to pick at least four of the fields from the source substrate in parallel to be transferred to the second substrate, where the relative positions of the at least four of the fields is redetermined.

Bonding alignment marks at bonding interface

Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a method for forming a semiconductor device is disclosed. A first device layer is formed on a first substrate. A first bonding layer including a first bonding contact and a first bonding alignment mark is formed above the first device layer. A second device layer is formed on a second substrate. A second bonding layer including a second bonding contact and a second bonding alignment mark is formed above the second device layer. The first bonding alignment mark is aligned with the second bonding alignment mark, such that the first bonding contact is aligned with the second bonding contact. The first substrate and the second substrate are bonded in a face-to-face manner, so that the first bonding contact is in contact with the second bonding contact at a bonding interface, and the first bonding alignment mark is in contact with the second bonding alignment mark at the bonding interface.

接合方法

一種方法包含確定第一晶圓之第一面上之第一對準標記與第一晶圓之第二面上之第二對準標記之間之第一偏移；將第一晶圓之第一對準標記對準第二晶圓之第一面上之第三對準標記，包含檢測第一晶圓之第二對準標記之位置；根據第一偏移與第一晶圓之第二對準標記之位置，確定第一晶圓之第一對準標記之位置；以及根據第一對準標記之所確定之位置，重新定位第一晶圓，以將第一對準標記對準第三對準標記；以及將第一晶圓之第一面接合至第二晶圓之第一面，以形成接合結構。

System and method for bonding semiconductor devices

A method includes determining a first offset between a first alignment mark on a first side of a first wafer and a second alignment mark on a second side of the first wafer; aligning the first alignment mark of the first wafer to a third alignment mark on a first side of a second wafer, which includes detecting a location of the second alignment mark of the first wafer; determining a location of the first alignment mark of the first wafer based on the first offset and the location of the second alignment mark of the first wafer; and, based on the determined location of the first alignment mark, repositioning the first wafer to align the first alignment mark to the third alignment mark; and bonding the first side of the first wafer to the first side of the second wafer to form a bonded structure.

用于接合芯片的设备和使用该设备接合芯片的方法

一种芯片接合设备包括：主体；衬底传送件，其安装在主体上以转移衬底；接合头传送件，其设置在主体的上表面上；对齐单元，其安装在主体上，并且调整衬底的位置和芯片的位置；以及接合头，其安装在接合头传送件中，并且移动以及在其下方附着芯片，其中，接合头设有用于在其下端部中附着芯片的芯片接合单元，其中，芯片接合单元包括：芯片接合单元主体，其具有形成在其中的安装凹槽；推模块，其具有插入安装凹槽中的一个端部；以及附着模块，其具有通过推模块变形的可变形构件；其中，可变形构件设有可变形部分，可变形部分通过被推模块按压而变形，可变形部分的底表面接触芯片，并且对芯片施加力，以将芯片接合至衬底。

製造装置及びその動作方法、及び半導体装置の製造方法

【課題】貼合されたウェハに対してほとんど機械的な負荷をかけることなくお互いを剥離することが可能となる。【解決手段】実施の形態に係る製造装置は、ワークを収納する収納部と、ワークを移載する移載部と、移載部により移載されたワークを載置し、剥離処理を実施する処理部とを備える。処理部は、液体を収納する温浴槽と、温浴槽内においてワークを載置する載置部と、載置部に載置されたワークを加圧する上部アームとを備える。【選択図】図１

Manufacturing apparatus, operation method thereof, and method for manufacturing semiconductor device

According to one embodiment, a manufacturing apparatus includes: a storage configured to store a work; a transfer arm configured to transfer the work; a hot bath configured to store a liquid; a mounting table configured to mount the work in the hot bath; and an upper arm configured to apply pressure to the work mounted on the mounting table.

접합 장치, 접합 시스템, 접합 방법 및 컴퓨터 기억 매체

본 발명은, 기판의 접합 처리의 상태를 검사하여, 당해 접합 처리를 적절하게 행하는 것이다. 상부 웨이퍼(W U )와 하부 웨이퍼(W L )를 접합하는 접합 장치는, 하면에 상부 웨이퍼(W U )를 진공화해서 흡착 유지하는 상부 척(140)과, 상부 척(140)의 하방에 설치되고, 상면에 하부 웨이퍼(W L )를 진공화해서 흡착 유지하는 하부 척(141)과, 상부 척(140)에 설치되고, 상부 웨이퍼(W U )의 중심부를 가압하는 압동 부재(190)와, 상부 척(140)에 설치되고, 상부 척(140)으로부터 상부 웨이퍼(W U )의 이탈을 검출하는 복수의 센서(175)를 갖는다.

半導体製造装置およびその製造方法

【課題】基板同士を好適に貼り合わせることが可能な半導体製造装置およびその製造方法を提供する。 【解決手段】一の実施形態によれば、半導体製造装置は、第１基板と第２基板との倍率差の値を取得する倍率差取得部を備える。前記装置はさらに、前記倍率差の値に基づいて、前記第１または第２基板を保持するチャックの変形量の値を決定する変形量決定部を備える。前記装置はさらに、前記変形量の値に基づいて、前記第１基板と前記第２基板との間のギャップの値を決定するギャップ決定部を備える。前記装置はさらに、前記第１基板と前記第２基板とを貼り合わせる前に、前記変形量を前記決定された値に制御し、かつ前記ギャップを前記決定された値に制御する貼合制御部を備える。 【選択図】図６

基板貼り合わせ装置および基板貼り合わせ方法

第１の基板における表面の一部と第２の基板における表面の一部とを接触させて一部に接触領域を形成した後に、接触領域を拡大させて、第１の基板および第２の基板を貼り合わせる基板貼り合わせ装置であって、第１の基板および第２の基板の間の位置ずれが貼り合わせ後の位置ずれの許容値を超える前に、接触領域の拡大を開始させる。

Wafer bonding device and wafer bonding method

A wafer bonding device includes: a first fixing apparatus fixing a first wafer, on which a first alignment mark is disposed; a second fixing apparatus fixing a second wafer, on which a second alignment mark is disposed, the second fixing apparatus being disposed opposite to the first fixing apparatus; a reflection member between the first and second fixing apparatuses; a mark reader which reads position information about the first and second alignment marks by means of the reflection member, for aligning the first wafer with the second wafer; and a heating apparatus, configured to heat the first wafer or the second wafer to thermally expand the first wafer or the second wafer so that the first alignment mark or the second alignment mark is located at a central position of a field of view of the mark reader. A wafer bonding method also is involved.

Electrical overlay measurement methods and structures for wafer-to-wafer bonding

A method includes providing a first wafer including a respective set of first metal bonding pads and at least one first alignment diagnostic structure, providing a second wafer including a respective set of second metal bonding pads and a respective set of second alignment diagnostic structures, overlaying the first wafer and the second wafer, measuring at least one of a current, voltage or contact resistance between the first alignment diagnostic structures and the second alignment diagnostic structures to determine an overlay offset, and bonding the second wafer to the first wafer.

Manufacturing method of semiconductor structure

A manufacturing method of a semiconductor structure including the following steps is provided. A first substrate is provided. A first dielectric structure is formed on the first substrate. At least one first cavity is formed in the first dielectric structure. A first stress adjustment layer is formed in the first cavity. The first stress adjustment layer covers the first dielectric structure. A second substrate is provided. A second dielectric structure is formed on the second substrate. At least one second cavity is formed in the second dielectric structure. A second stress adjustment layer is formed in the second cavity. The second stress adjustment layer covers the second dielectric structure. The first stress adjustment layer and the second stress adjustment layer are bonded.

接合介面處的接合對準標記

公開了接合半導體結構及其製作方法的實施例。在示例中，一種半導體器件包括第一半導體結構、第二半導體結構以及處於第一半導體結構和第二半導體結構之間的接合介面。第一半導體結構包括基底、設置在基底上的第一器件層及設置在第一器件層上方並且包括第一接合觸點和第一接合對準標記的第一接合層。第二半導體結構包括第二器件層及設置在第二器件層下方並且包括第二接合觸點和第二接合對準標記的第二接合層。使第一接合對準標記與第二接合對準標記在接合介面處對準，以使得第一接合觸點與第二接合觸點在接合介面處對準。

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積體電路裝置及積體電路裝置的封裝方法

一種積體電路裝置包括：第一晶粒陣列，包括第一積體電路晶粒，第一積體電路晶粒的定向沿第一晶粒陣列的列及行交替改變；第一介電層，環繞第一積體電路晶粒，第一介電層的表面與第一積體電路晶粒的表面成平面；第二晶粒陣列，包括位於第一介電層及位於第一積體電路晶粒上的第二積體電路晶粒，第二積體電路晶粒的定向沿第二晶粒陣列的列及行交替改變，第二積體電路晶粒的前側藉由金屬-金屬鍵以及介電質-介電質鍵而結合至第一積體電路晶粒的前側；及第二介電層，環繞第二積體電路晶粒，第二介電層的表面與第二積體電路晶粒的表面成平面。

Integrated Circuit Package and Method

In an embodiment, a device includes: a first die array including first integrated circuit dies, orientations of the first integrated circuit dies alternating along rows and columns of the first die array; a first dielectric layer surrounding the first integrated circuit dies, surfaces of the first dielectric layer and the first integrated circuit dies being planar; a second die array including second integrated circuit dies on the first dielectric layer and the first integrated circuit dies, orientations of the second integrated circuit dies alternating along rows and columns of the second die array, front sides of the second integrated circuit dies being bonded to front sides of the first integrated circuit dies by metal-to-metal bonds and by dielectric-to-dielectric bonds; and a second dielectric layer surrounding the second integrated circuit dies, surfaces of the second dielectric layer and the second integrated circuit dies being planar.

Integriertes schaltungs-package und verfahren

Bei einer Ausführungsform weist eine Vorrichtung Folgendes auf: eine erste Die-Matrix mit ersten integrierten Schaltungs-Dies, wobei Orientierungen der ersten integrierten Schaltungs-Dies entlang Zeilen und Spalten der ersten Die-Matrix abwechseln; eine erste dielektrische Schicht, die die ersten integrierten Schaltungs-Dies umgibt, wobei Oberflächen der ersten dielektrischen Schicht und der ersten integrierten Schaltungs-Dies planar sind; eine zweite Die-Matrix mit zweiten integrierten Schaltungs-Dies auf der ersten dielektrischen Schicht und den ersten integrierten Schaltungs-Dies, wobei Orientierungen der zweiten integrierten Schaltungs-Dies entlang Zeilen und Spalten der zweiten Die-Matrix abwechseln und Vorderseiten der zweiten integrierten Schaltungs-Dies durch Metall-Metall-Bondverbindungen und durch Dielektrikum-Dielektrikum-Bondverbindungen an Vorderseiten der ersten integrierten Schaltungs-Dies gebondet sind; und eine zweite dielektrische Schicht, die die zweiten integrierten Schaltungs-Dies umgibt, wobei Oberflächen der zweiten dielektrischen Schicht und der zweiten integrierten Schaltungs-Dies planar sind.

집적 회로 패키지 및 방법

실시예에서, 디바이스는 제1 집적 회로 다이를 포함하는 제1 다이 어레이로서, 제1 집적 회로 다이의 배향은 제1 다이 어레이의 행과 열을 따라 교호하는 것인, 제1 다이 어레이; 제1 집적 회로 다이를 둘러싸는 제1 유전체층으로서, 제1 유전체층 및 제1 집적 회로 다이의 표면은 평면인 것인, 제1 유전체층; 제1 유전체층 및 제1 집적 회로 다이 상의 제2 집적 회로 다이를 포함하는 제2 다이 어레이로서, 제2 집적 회로 다이의 배향은 제2 다이 어레이의 행 및 열을 따라 교호하고, 제2 집적 회로 다이의 전측면은 금속 대 금속 본딩에 의해 그리고 유전체 대 유전체 본딩에 의해 제1 집적 회로 다이의 전측면에 본딩되는 것인, 제2 다이 어레이; 및 제2 집적 회로 다이를 둘러싸는 제2 유전체층으로서, 제2 유전체층 및 제2 집적 회로 다이의 표면은 평면인 것인, 제2 유전체층을 포함한다.

Memory device including memory chip and peripheral memory chip and method of manufacturing the memory device

A memory device includes a memory chip including a memory cell array connected to first word lines and first bit lines, first word line bonding pads respectively connected to the first word lines, and first bit line bonding pads respectively connected to the first bit lines, and a peripheral circuit chip, wherein the peripheral circuit chip includes a test cell array connected to second word lines and second bit lines, second word line bonding pads respectively connected to the first word line bonding pads, second bit line bonding pads respectively connected to the first bit line bonding pads, and a peripheral circuit connected to the second word line bonding pads and the second word lines or the second bit line bonding pads and the second bit lines.

Processes and applications for catalyst influenced chemical etching

触媒影響化学エッチングのためのプロセスおよび適用

ソース基板から第２の基板の上にフィールドを組み立てるためのシステム。ソース基板は、フィールドを含む。システムは、トランスファーチャックをさらに含み、トランスファーチャックは、第２の基板に転送されることとなるフィールドのうちの少なくとも４つをソース基板から並列にピッキングするために使用され、フィールドのうちの少なくとも４つの相対的位置は、事前に決定されている。

Pick and place method and apparatus thereof

A pick and place method and apparatus thereof are provided. The pick and place method includes: providing at least one semiconductor element disposed on a source storage location; picking up the at least one semiconductor element from the source storage location; transferring the at least one semiconductor element to a temporary storage device according to a signal; positioning the at least one semiconductor element through the temporary storage device; and picking up the positioned semiconductor element from the temporary storage device and placing the positioned semiconductor element on a destination storage location.

之複合結合方法

本發明提供一種複合結合裝置組，包括多數個腔室，以及被設置來在多數個腔室之間傳送多數個晶圓並將多數個已結合的晶圓傳送到退火室的傳送器，多數個晶圓包括多數個基板晶圓和多數個裸片供應晶圓，其中所述多數個腔室分別包括被設置來儲存所述多數個晶圓之晶圓供應器，被設置來結合所述多數個晶圓之結合裝置組，所述結合裝置組包括被設置來將裸片結合在所述來自多數個裸片供應晶圓的基板晶圓上之結合器，被設置來對多數個基板晶圓進行初級退火的預退火爐，以及一處理器。

Hybrid bonding apparatus and hybrid bonding method using the same

Provided is a hybrid bonding apparatus including a plurality of chambers, and a transferer configured to transfer a plurality of wafers between the plurality of chambers and transfer a plurality of bonded wafers to an annealing chamber, the plurality of wafers including a plurality of substrate wafers and a plurality of die supply wafers, wherein the plurality of chambers respectively includes a wafer supplier configured to store the plurality of wafers, a bonding device configured to bond the plurality of wafers, the bonding device including a bonder configured to bond dies on the plurality of substrate wafers from the plurality of die supply wafers, and a pre-annealing oven configured to primarily anneal the plurality of substrate wafers, and a processor.

用于晶圆对晶圆对准和接合的连接性检测

第一工件包括位于该第一工件的主表面上的第一有源焊盘、第一测试焊盘和第二测试焊盘，第一测试焊盘电连接到第二测试焊盘。第二工件包括位于该第二工件的主表面上的第二有源焊盘、第三测试焊盘和第四测试焊盘。第一工件和第二工件沿着第一工件的主表面与第二工件的主表面之间的界面接合，以将第一有源焊盘与第二有源焊盘接合，将第一测试焊盘与第三测试焊盘接合，并且将第二测试焊盘与第四测试焊盘接合。连接性检测电路测试第三测试焊盘与第四测试焊盘之间的电连接性。

Bonding system and bonding method

Embodiments of the present disclosure provide a bonding system and a bonding method. The bonding system includes a bonding assembly, a wafer stage, a first alignment assembly and a second alignment assembly. The wafer stage is configured to drive, according to a first deviation value determined by the first alignment assembly and a second deviation value determined by the second alignment assembly, a carried wafer to move so as to align a second die with a first die. The bonding assembly is configured to bond the first die to the second die. The bonding system further includes a third alignment assembly located at a side of the wafer stage away from the bonding assembly, and configured to determine a third deviation value between positions of the first die and the second die which have been bonded. The bonding assembly is further configured to debond the first die from the second die, in response to that the third deviation value is greater than a preset threshold.

Substrate bonding apparatus and method of manufacturing semiconductor device by using the same

A substrate bonding method and apparatus are described. The substrate bonding apparatus is used to bond a first substrate to a second substrate. The bonding apparatus includes a first bonding chuck configured to hold the first substrate on a first surface of the first bonding chuck; a second bonding chuck configured to hold the second substrate on a second surface of the second bonding chuck, the second surface facing the first surface of the first bonding chuck; a seal arranged between the first bonding chuck and the second bonding chuck and adjacent to at least one edge of the first substrate and at least one edge of the second substrate; and a process gas supply device configured to supply a process gas to a bonding space surrounded by the seal.

半导体裸片和半导体晶圆

公开了一种半导体裸片和一种半导体晶圆。所述半导体裸片包括：第一垫；开关，分别与第一垫电连接；测试信号产生器，产生测试信号并将测试信号发送到开关；内部电路，通过第一垫和开关接收第一信号，基于第一信号执行操作，并基于操作的结果通过开关和第一垫输出第二信号；以及开关控制器，控制开关，使得在测试操作期间第一垫与测试信号产生器连通，并且使得在完成测试操作之后第一垫与内部电路连通。

接合方法

一種方法包含確定第一晶圓之第一面上之第一對準標記與第一晶圓之第二面上之第二對準標記之間之第一偏移；將第一晶圓之第一對準標記對準第二晶圓之第一面上之第三對準標記，包含檢測第一晶圓之第二對準標記之位置；根據第一偏移與第一晶圓之第二對準標記之位置，確定第一晶圓之第一對準標記之位置；以及根據第一對準標記之所確定之位置，重新定位第一晶圓，以將第一對準標記對準第三對準標記；以及將第一晶圓之第一面接合至第二晶圓之第一面，以形成接合結構。

System und verfahren zum bonden von halbleitervorrichtungen

Ein Verfahren umfasst das Bestimmen eines ersten Versatzes zwischen einer ersten Ausrichtungsmarkierung auf einer ersten Seite eines ersten Wafers und einer zweiten Ausrichtungsmarkierung auf einer zweiten Seite des ersten Wafers; das Ausrichten der ersten Ausrichtungsmarkierung des ersten Wafers auf eine dritte Ausrichtungsmarkierung auf einer ersten Seite eines zweiten Wafers, umfassend Erfassen einer Position der zweiten Ausrichtungsmarkierung des ersten Wafers; Bestimmen einer Position der ersten Ausrichtungsmarkierung des ersten Wafers basierend auf dem ersten Versatz und der Position der zweiten Ausrichtungsmarkierung des ersten Wafers; und Neupositionieren des ersten Wafers basierend auf der bestimmten Position der ersten Ausrichtungsmarkierung, um die erste Ausrichtungsmarkierung auf die dritte Ausrichtungsmarkierung auszurichten; und Bonden der ersten Seite des ersten Wafers an die erste Seite des zweiten Wafers, um eine gebondete Struktur zu bilden.

Memory device including memory chip and peripheral memory chip and method of manufacturing the memory device

A memory device includes a memory chip including a memory cell array connected to first word lines and first bit lines, first word line bonding pads respectively connected to the first word lines, and first bit line bonding pads respectively connected to the first bit lines, and a peripheral circuit chip, wherein the peripheral circuit chip includes a test cell array connected to second word lines and second bit lines, second word line bonding pads respectively connected to the first word line bonding pads, second bit line bonding pads respectively connected to the first bit line bonding pads, and a peripheral circuit connected to the second word line bonding pads and the second word lines or the second bit line bonding pads and the second bit lines.

半導體裝置及其製造方法

實施形態提供一種可良好地貼合複數個半導體基板上之材料層之半導體裝置及其製造方法。 實施形態之半導體裝置具備第1半導體基板、第1絕緣膜、第1金屬層、第1電極部、第2半導體基板、第2絕緣膜、及第2電極部。第1絕緣膜設置於第1半導體基板之第1面，且形成有第1槽。第1金屬層被覆第1槽之內表面。第1電極部設置於第1金屬層上並嵌入至第1槽內。第2半導體基板具有與第1半導體基板之第1面對向之第2面。第2絕緣膜設置於第2半導體基板之第2面，與第1絕緣膜貼合，且形成有第2槽。第2電極部嵌入至第2槽內，並與第1電極部連接。第1金屬層之端部比第1絕緣膜之表面更向第1半導體基板側凹陷。

半导体装置及其制造方法

实施方式提供一种能够良好地贴合多个半导体衬底上的材料层的半导体装置及其制造方法。实施方式的半导体装置具备第1半导体衬底、第1绝缘膜、第1金属层、第1电极部、第2半导体衬底、第2绝缘膜、及第2电极部。第1绝缘膜设置在第1半导体衬底的第1面，且形成着第1槽。第1金属层被覆第1槽的内表面。第1电极部设置在第1金属层上并嵌入至第1槽内。第2半导体衬底具有与第1半导体衬底的第1面对向的第2面。第2绝缘膜设置在第2半导体衬底的第2面，与第1绝缘膜贴合，且形成着第2槽。第2电极部嵌入至第2槽内，并与第1电极部连接。第1金属层的端部比第1绝缘膜的表面更向第1半导体衬底侧凹陷。

Dimension compensation control for directly bonded structures

A method of direct hybrid bonding first and second semiconductor elements of differential thickness is disclosed. The method can include patterning a plurality of first contact features on the first semiconductor element. The method can include second a plurality of second contact features on the second semiconductor element corresponding to the first contact features for direct hybrid bonding. The method can include applying a lithographic magnification correction factor to one of the first patterning and second patterning without applying the lithographic magnification correction factor to the other of the first patterning and the second patterning. In various embodiments, a differential expansion compensation structure can be disposed on at least one of the first and the second semiconductor elements. The differential expansion compensation structure can be configured to compensate for differential expansion between the first and second semiconductor elements to reduce misalignment between at least the second and fourth contact features.

Bonding tool and bonding method thereof

A bonding tool and a bonding method are provided. The method includes attaching a semiconductor die to a bonding tool having a first surface, wherein the bonding tool comprises a bending member movably arranged in a trench of the bonding tool, and the bending member protrudes from the first surface and bends the semiconductor die; moving the semiconductor die toward a semiconductor wafer to cause a retraction of the bending member and a partial bonding at a portion of the semiconductor die and the semiconductor wafer; and causing a full bonding between the semiconductor die and the semiconductor wafer subsequent to the partial bonding.

接合裝置、接合系統、接合方法、接合程式及非暫時的電腦可讀取之記錄媒體

本發明提供一種接合裝置、接合系統、接合方法、接合程式及電腦記錄媒體，檢查基板的接合處理之狀態，適當地施行該接合處理。將上晶圓W U 與下晶圓W L 接合之接合裝置，包含：上吸盤140，抽真空而將上晶圓W U 吸附保持於底面；下吸盤141，設置於上吸盤140之下方，抽真空而將下晶圓W L 吸附保持於頂面；推動構件190，設置於上吸盤140，推壓上晶圓W U 之中心部；以及複數之感測器175，設置於上吸盤140，檢測上晶圓W U 從上吸盤140的脫離。

Bonding Apparatus, Bonding System, Bonding Method and Storage Medium

There is provided a bonding apparatus for bonding substrates together, which includes: a first holding part configured to adsorptively hold a first substrate by vacuum-drawing the first substrate on a lower surface of the first substrate; a second holding part provided below the first holding part and configured to adsorptively hold a second substrate by vacuum-drawing the second substrate on an upper surface of the second substrate; a pressing member provided in the first holding part and configured to press a central portion of the first substrate; and a plurality of substrate detection parts provided in the first holding part and configured to detect a detachment of the first substrate from the first holding part.

Wafer to wafer bonding methods and wafer to wafer bonding apparatuses

In a wafer to wafer bonding method, a first wafer is vacuum suctions on a first surface of a lower stage and a second wafer is vacuum suctioned on a second surface of an upper stage. Pressure is applied to a middle portion of the first wafer by a lower push rod and pressure is applied to a middle portion of the second wafer by an upper push rod. Bonding of the first and second wafers propagates radially outwards. A bonding propagation position of the first and second wafers is detected. A ratio of protruding lengths of the lower push rod and the upper push rod is changed according to the bonding propagation position.

웨이퍼 본딩 장치 및 그 장치를 포함한 웨이퍼 본딩 시스템

본 발명의 기술적 사상은 웨이퍼의 본딩 공정에서 웨이퍼의 본딩 상태를 정확하게 검출할 수 있는 웨이퍼 본딩 장치 및 그 장치를 포함한 웨이퍼 본딩 시스템을 제공한다. 그 웨이퍼 본딩 장치는 하방을 향하는 제1 면을 구비하고, 상기 제1 면 상에 배치되는 제1 웨이퍼를 진공 흡착하기 위한 진공 홈(vacuum groove)이 형성된 제1 지지판; 상기 제1 면에 대향하는 제2 면을 구비하고, 상기 제2 면 상에 제2 웨이퍼가 배치되는 제2 지지판; 상기 제1 지지판의 중심 부분에 배치된 본딩 개시 장치(bonding initiator); 및 상기 제1 지지판에 배치되고, 상기 제1 웨이퍼와 제2 웨이퍼의 본딩의 확산 상태를 검출하는 면적 센서;를 포함한다.

晶片结合装置和包括晶片结合装置的晶片结合系统

本发明提供一种晶片结合装置，用于在晶片结合工艺和/或包括所述晶片结合装置的晶片结合系统中精确地检测晶片的结合状态。所述晶片结合装置包括：第一支撑板，包括第一表面和用于真空吸附在第一表面上设置的第一晶片的真空槽；第二支撑板，包括面对第一表面的第二表面。第二晶片在第二表面上。所述晶片结合装置和/或所述晶片结合系统包括位于第一支撑板的中心部分处的结合引发器和位于第一支撑板上的区域传感器，所述区域传感器被配置为检测第一晶片与第二晶片之间的结合的传播状态。

Method And Apparatus For Determining Expansion Compensation In Photoetching Process, And Method For Manufacturing Device

A method and an apparatus for determining expansion compensation in a photoetching process, and a method for manufacturing a semiconductor device are provided. A relative vector misalignment value of a first wafer and a second wafer after being bonded is obtained based on a relative position relationship between a first alignment pattern of the first wafer and a second alignment pattern of the second wafer in a boding structure. A relative expansion value of the first wafer and the second wafer is obtained based on the relative vector misalignment value. A developing expansion compensation value in the photoetching process is obtained. The expansion compensation value is used to the photoetching process of a first conductor layer including the first alignment pattern of the first wafer and/or a second conductor layer including the second alignment pattern of the second wafer.

半導體結構的製造方法

一種半導體結構的製造方法，包括以下步驟。提供第一基底。在第一基底上形成第一介電結構。在第一介電結構中形成至少一個第一凹洞。在第一凹洞中形成第一應力調整層。第一應力調整層覆蓋第一介電結構。提供第二基底。在第二基底上形成第二介電結構。在第二介電結構中形成至少一個第二凹洞。在第二凹洞中形成第二應力調整層。第二應力調整層覆蓋第二介電結構。將第一應力調整層與第二應力調整層進行接合。

응착력 측정 장치 및 이를 포함하는 웨이퍼 본딩 시스템

응착력 측정 장치는 스테이지 및 센서 모듈을 포함할 수 있다. 시편은 상기 스테이지 상에 안치될 수 있다. 상기 센서 모듈은 상기 시편에 응착될 수 있다. 상기 센서 모듈은 상기 센서 모듈을 상기 시편으로부터 분리시킬 수 있는 힘을 상기 시편의 응착력으로서 감지할 수 있다. 따라서, 시편인 웨이퍼들을 본딩하기 전에, 웨이퍼의 응착력을 정확하게 측정할 수가 있다.

Die bonding tool with tiltable bond head for improved bonding and methods for performing the same

A die bonding tool includes a bond head that secures a semiconductor die against a planar surface of the bond head, an actuator system that moves the bond head and the semiconductor die towards a surface of a target substrate, and at least one contact sensor configured to detect an initial contact between a first region of the semiconductor die and the surface of the target substrate, where in response to detecting the initial contact between the semiconductor die and the target substrate, the actuator tilts the planar surface of the bond head and the semiconductor die to bring a second region of the semiconductor die into contact with the surface of the target substrate and thereby provide improved contact between the semiconductor die and the target substrate and more effective bonding including instances where the planar surface of the bond head and the target substrate surface are not parallel.

하이브리드 접합 시스템 및 그 클리닝 방법

몇몇 실시예에서, 하이브리드 접합 시스템은, 제1 디바이스, 제2 디바이스 및 제1 클리닝 모듈을 포함한다. 제1 디바이스는 제1 반도체 웨이퍼를 로딩하도록 구성된다. 제2 디바이스는 제1 디바이스에 관하여 제1 방향에서 이동 가능하도록 구성된다. 제2 디바이스는 제1 디바이스와 대면하는 제2 표면을 갖는다. 제2 표면은 제2 반도체 웨이퍼를 로딩하도록 구성된다. 제1 클리닝 모듈은 제2 디바이스에 관하여 제1 방향에서 제2 표면을 가로질러 이동하면서 제2 디바이스의 제2 표면을 클리닝하도록 구성된다.

半导体制造装置及其制造方法

实施方式提供能够将基板彼此适宜地贴合的半导体制造装置及其制造方法。实施方式的半导体制造装置具备取得第1基板与第2基板的倍率差的值的倍率差取得部。所述装置还具备基于所述倍率差的值来决定保持所述第1基板或所述第2基板的吸盘的变形量的值的变形量决定部。所述装置还具备基于所述变形量的值来决定所述第1基板与所述第2基板之间的间隙的值的间隙决定部。所述装置还具备在将所述第1基板和所述第2基板贴合前将所述变形量控制成决定的所述值且将所述间隙控制成决定的所述值的贴合控制部。