THREE-DIMENSIONAL ELECTRONIC PACKAGES UTILIZING UNPATTERNED ADHESIVE LAYER

An electronic package may be fabricated by forming a first layer of insulating material on a first substrate such that the first layer covers a contact pad; forming an opening through the first layer to expose the contact pad; forming an un-patterned second layer on the first layer, the second layer including an adhesive having a viscosity less than that of the first layer, wherein a region of the second layer obstructs the contact pad; removing the region to re-expose the contact pad; aligning a second substrate with the first substrate such that a via of the second substrate is aligned with the opening; bonding the first substrate and the second substrate together at the second layer; and forming an interconnect in contact with the contact pad by depositing a conductive material through the via and the opening.

Three-dimensional electronic packages utilizing unpatterned adhesive layer

An electronic package may be fabricated by forming a first layer of insulating material on a first substrate such that the first layer covers a contact pad; forming an opening through the first layer to expose the contact pad; forming an un-patterned second layer on the first layer, the second layer including an adhesive having a viscosity less than that of the first layer, wherein a region of the second layer obstructs the contact pad; removing the region to re-expose the contact pad; aligning a second substrate with the first substrate such that a via of the second substrate is aligned with the opening; bonding the first substrate and the second substrate together at the second layer; and forming an interconnect in contact with the contact pad by depositing a conductive material through the via and the opening.

Electronic component and method of manufacturing electronic component

A method of manufacturing an electronic component includes disposing a heat radiation material including a plurality of linear structures of carbon atoms and a filling layer of a thermoplastic resin provided among the plurality of linear structures above a first substrate, disposing a blotting paper above the heat radiation material, making a heat treatment at a temperature higher than a melting temperature of the thermoplastic resin and absorbing the thermoplastic resin above the plurality of linear structures with the absorption paper, removing the blotting paper, and adhering the heat radiation material to the first substrate by cooling to solidify the thermoplastic resin.

電子部品の製造方法

ELECTRONIC COMPONENT AND MANUFACTURING METHOD THEREOF

PROBLEM TO BE SOLVED: To provide an electronic component which is capable of radiating heat from a heat generating element with high efficiency, and a manufacturing method thereof. SOLUTION: On a substrate, a heat radiating material is disposed which has linear structures of carbon elements and a thermoplastic resin filling layer disposed between the linear structures. Next, blotting paper is disposed on the heat radiating material, thermal treatment is performed at a higher temperature than a melting temperature of the thermoplastic resin, and the thermoplastic resin on the linear structure is blotted by the blotting paper. Thereafter, the blotting paper is removed, the thermoplastic resin is then solidified by cooling and the heat radiating material is adhered onto the substrate. COPYRIGHT: (C)2012,JPO&INPIT ...

ELECTRONIC COMPONENT AND METHOD OF MANUFACTURING ELECTRONIC COMPONENT

A method of manufacturing an electronic component includes disposing a heat radiation material including a plurality of linear structures of carbon atoms and a filling layer of a thermoplastic resin provided among the plurality of linear structures above a first substrate, disposing a blotting paper above the heat radiation material, making a heat treatment at a temperature higher than a melting temperature of the thermoplastic resin and absorbing the thermoplastic resin above the plurality of linear structures with the absorption paper, removing the blotting paper, and adhering the heat radiation material to the first substrate by cooling to solidify the thermoplastic resin.

Method for Reducing Chip Warpage

A method of forming an integrated circuit structure including providing a wafer comprising a front surface and a back surface, wherein the wafer comprises a chip; forming an opening extending from the back surface into the chip; filling an organic material in the opening, wherein substantially no portion of the organic material is outside of the opening and on the back surface of the wafer; and baking the organic material to cause a contraction of the organic material.

Package systems and manufacturing methods thereof

A package system includes a first substrate and a second substrate. The second substrate is electrically coupled with the first substrate. The second substrate includes at least one first opening. At least one electrical bonding material is disposed between the first substrate and the second substrate. A first portion of the at least one electrical bonding material is at least partially filled in the at least one first opening.

Package systems and manufacturing methods thereof

A package system includes a first substrate. A second substrate is electrically coupled with the first substrate. At least one electrical bonding material is disposed between the first substrate and the second substrate. The at least one electrical bonding material includes a eutectic bonding material. The eutectic bonding material includes a metallic material and a semiconductor material. The metallic material is disposed adjacent to a surface of the first substrate. The metallic material includes a first pad and at least one first guard ring around the first pad.

Heat radiation material, electronic device and method of manufacturing electronic device

The electronic device includes a heat generator 54, a heat radiator 58, and a heat radiation material 56 disposed between the heat generator 54 and the heat radiator 58 and including a plurality of linear structures 12 of carbon atoms and a filling layer 14 formed of a thermoplastic resin and disposed between the plurality of linear structures 12.

Semiconductor chips including passivation layer trench structure

An integrated circuit including an active region a passive region and a cut line in the passive region includes a passivation layer that includes an outer nitride layer over an oxide layer. The integrated circuit also includes a crack stop below the passivation layer and in the passive region, and a solder ball in the active region. The passivation layer has a trench formed therein in a location that is further from the active region than the crack stop and closer to the active region than the cut line, the trench passing completely through the outer nitride layer and a least a portion of the way through the oxide layer.

Semiconductor Unit with Submount for Semiconductor Device

A semiconductor unit includes a submount and a chip coupled to the submount. The submount is configured with a base and a plurality of layers between the base and the chip. One of the layers, a heat-spreading electro-conducting sliver (“Ag”) layer, is deposited atop the base. The thickness of the Ag layer is selected so that a cumulative coefficient of thermal expansion of the submount substantially matches that one of the chip. Coupled to the active zone of the chip is a stress-dumping layer made from elastic malleable materials.

Bonding structure including metal nano particles and bonding method using metal nano particles

A bonding structure including metal nano particles includes a first member having a metal surface on at least one side, a second member having a metal surface on at least one side, the second member being disposed such that the metal surface of the second member faces the metal surface of the first member, and a bonding material bonding the first member and the second member by sinter-bonding the metal nano particles. At least one of the metal surfaces of the first member and the second member is formed to be a rough surface having a surface roughness within the range from 0.5 μm to 2.0 μm.

Solder fatigue arrest for wafer level package

A wafer level package includes a wafer, a lead disposed of the wafer for connecting the wafer to an electrical circuit, and a core disposed of the lead. In some embodiments, the lead disposed of the wafer is a copper pillar, and the core is plated onto the copper pillar. In some embodiments, the core is polymer screen-plated onto the lead. In some embodiments, the core extends between at least approximately thirty-five micrometers (35 μm) and fifty micrometers (50 μm) from the lead. In some embodiments, the core covers between at least approximately one-third (⅓) and one-half (½) of the surface area of the lead. In some embodiments, the core comprises a stud-shape extending from the lead. In some embodiments, the core extends perpendicularly across the lead. In some embodiments, the core extends longitudinally along the lead. Further, a portion of the core can extend perpendicularly from a longitudinal core.

Semiconductor package, method for forming semiconductor package, and method for forming semiconductor assembly

A semiconductor package includes a first package component include a first side, a second side opposite to the first side, and a plurality of recessed corners over the first side. The semiconductor package further includes a plurality of first stress buffer structures disposed at the recessed corners, and each of the first stress buffer structures has a curved surface. The semiconductor package further includes a second package component connected to the first package component and a plurality of connectors disposed between the first package component and the second package component. The connectors are electrically coupled the first package component and the second package component. The semiconductor package further includes an underfill material between the first package component and the second package component, and at least a portion of the curved surface of the first stress buffer structures is in contact with and embedded in the underfill material.

Semiconductor device and method of forming a semiconductor device

A semiconductor device and method is disclosed. The semiconductor device may include a semiconductor substrate including an active area, a metal layer structure over the active area, wherein the metal layer structure is configured to form an electrical contact, the metal layer structure including a solder area, a buffer area, and a barrier area between the solder area and the buffer area, wherein, in the barrier area, the metal layer structure is further away from the active area than in the solder area and in the buffer area, and wherein each of the solder area and the buffer area is in direct contact with the active area or with a wiring layer structure arranged between the active area and the metal layer structure.

METHOD AND APPARATUS FOR CREATING A BOND BETWEEN OBJECTS BASED ON FORMATION OF INTER-DIFFUSION LAYERS

The present disclosure provides a method of creating a bond between a first object and a second object. For example, at least one insert may be provided at a location in a space formed between the first object and the second object. In additional, a filler material may be provided proximal to the location. An inter-diffusion layer may be formed, wherein a first portion of the inter-diffusion layer is formed by diffusion between the filler material and the at least one insert, wherein a second portion of the inter-diffusion layer is formed between the filler material and the first object, wherein a third portion of the inter-diffusion layer is formed between the filler material and the second object, wherein the first portion is coadunate with each of the second portion and third portion. 1. An electronic module comprising:a substrate;at least one chip; a first set of inserts placed inside a space between the substrate and the at least one chip,', "wherein diffusion of the second set of inserts occurs into at least one of the following: the substrate's mating surface, the at least one chip's mating surface and the first set of inserts;", 'a second set of inserts placed inside a space formed by the substrate, the at least one chip and the first set of inserts,'}], 'a plurality of inserts comprisinga gap between the first set of the inserts and the substrate; and 'wherein the diffusion results in formation of at least one of the following: a coadunate inter-diffusion layer along at least one insert of the first set of inserts to the at least one chip and a coadunate inter-diffusion layer along at least one insert of the first set of the inserts to the substrate.', 'a gap between the first set of inserts and the at least one chip,'}21. The electronic module of lain , wherein the at least one insert of the first set of inserts is comprised in at least one of the substrate's mating surface and the chip's mating surface.3. The electronic module of claim 1 , wherein the at ...

METHOD FOR BONDING A HERMETIC MODULE TO AN ELECTRODE ARRAY

A method for bonding a hermetic module to an electrode array including the steps of: providing the electrode array having a flexible substrate with a top surface and a bottom surface and including a plurality of pads in the top surface of the substrate; attaching the hermetic module to the bottom surface of the electrode array, the hermetic module having a plurality of bond-pads wherein each bond-pad is adjacent to the bottom surface of the electrode array and aligns with a respective pad; drill holes through each pad to the corresponding bond-pad; filling each hole with biocompatible conductive ink; forming a rivet on the biocompatible conductive ink over each pad; and overmolding the electrode array with a moisture barrier material. 16-. (canceled)7. A method for attaching a lead wire to a module frame , the module frame including at least one module pad , the method comprising:drilling a hole adjacent the at least one module pad of the module frame;feeding an electrode wire through the drilled hole;securing the electrode wire in place within the drilled hole;connecting the at least one module pad to the drilled hole and the electrode wire; andovermolding the module frame.8. The method of claim 7 , further including securing the electrode wire by wrapping the electrode wire back onto itself and welding the electrode wire.9. The method of claim 7 , wherein the electrode wire is a Platinum wire.10. The method of claim 7 , further including connecting the at least one module pad to the drilled hole and the electrode wire done by applying a printed conductive ink trace.11. The method of claim 7 , further comprising filling the drilled hole with epoxy to obtain structural integrity.12. The method of claim 11 , further including applying the epoxy in a mushroom topology using an ink-jet or aerojet process.13. The method of claim 7 , wherein the module frame includes a plurality of module pads and a plurality of corresponding holes with a feedthrough density greater than ...

Semiconductor device and semiconductor apparatus

A semiconductor device that comprises a substrate with a primary surface and a secondary surface opposite to the primary surface. The primary surface provides a semiconductor active device. The semiconductor device includes a base metal layer deposited on the secondary surface and within the substrate via in which a vacancy is formed, and an additional metal layer on the base metal layer, the additional metal layer having different wettability against a solder as compared to the base metal layer whereby the solder is contactable by the base metal layer and repelled by the additional metal layer. The semiconductor device is die-bonded on the assembly substrate by interposing the solder between the secondary surface and the assembly substrate. The base metal layer in a portion that excepts the substrate via and a periphery of the substrate via by partly removing the additional metal layer is in contact with the solder.

Semiconductor device, method for manufacturing the same, and electronic device

Disclosed herein is a semiconductor device including: a first semiconductor chip having an electronic circuit section and a first connecting section formed on one surface thereof; a second semiconductor chip having a second connecting section formed on one surface thereof, the second semiconductor chip being mounted on the first semiconductor chip with the first and the second connecting sections connected to each other by a bump; a dam formed to fill a gap between the first and the second semiconductor chips on a part of an outer edge of the second semiconductor chip, the part of the outer edge being on a side of a region of formation of the electronic circuit section; and an underfill resin layer filled into the gap, protrusion of the resin layer from the outer edge of the second semiconductor chip to a side of the electronic circuit section being prevented by the dam.

Semiconductor device with frame having arms and related methods

A semiconductor device may include a circuit board having an opening, and a frame. The frame may have an IC die pad in the opening, and arms extending outwardly from the IC die pad and coupled to the circuit board. The semiconductor device may include an IC mounted on the IC die pad, bond wires coupling the circuit board with the IC, and encapsulation material surrounding the IC, the bond wires, and the arms.

Methods of forming 3-d circuits with integrated passive devices

Methods of forming 3-D ICs with integrated passive devices (IPDs) include stacking separately prefabricated substrates coupled by through-substrate-vias (TSVs). An active device (AD) substrate has contacts on its upper portion. An isolator substrate is bonded to the AD substrate so that TSVs in the isolator substrate are coupled to the contacts on the AD substrate. An IPD substrate is bonded to the isolator substrate so that TSVs therein are coupled to an interconnect zone on the isolator substrate and/or TSVs therein. The IPDs of the IPD substrate are coupled by TSVs in the IPD and isolator substrates to devices in the AD substrate. The isolator substrate provides superior IPD to AD cross-talk attenuation while permitting each substrate to have small high aspect ratio TSVs, thus facilitating high circuit packing density and efficient manufacturing.

Wafer level integration for embedded cooling

Techniques for wafer level integration of embedded cooling structures for integrated circuit devices are provided. In one embodiment, a method includes forming channel structures on a first surface of a silicon first wafer, wherein the channel structures respectively include radial channels that extend from central fluid distribution areas, and wherein integrated circuits are formed on a second surface of the silicon first wafer that opposes the first surface. The method can further include bonding a manifold wafer to the first surface of the silicon wafer such that inlet openings formed through the manifold wafer respectively connect to the central fluid distribution areas, thereby enclosing the radial channels and forming a bonded structure.

Wafer level integration for embedded cooling

Techniques for wafer level integration of embedded cooling structures for integrated circuit devices are provided. In one embodiment, a method includes forming channel structures on a first surface of a silicon first wafer, wherein the channel structures respectively comprise radial channels that extend from central fluid distribution areas, and wherein integrated circuits are formed on a second surface of the silicon first wafer that opposes the first surface. The method can further include bonding a manifold wafer to the first surface of the silicon wafer such that inlet openings formed through the manifold wafer respectively connect to the central fluid distribution areas, thereby enclosing the radial channels and forming a bonded structure.

MECHANISMS FOR FORMING PACKAGE STRUCTURE

A package structure is provided. The package structure includes a semiconductor die and a protection layer surrounding sidewalls of the semiconductor die. The package structure also includes a conductive structure penetrating through the protection layer. The package structure further includes an interfacial layer between the protection layer and the conductive structure. The interfacial layer is made of an insulating material, and the interfacial layer is in direct contact with the protection layer. The interfacial layer extends across a back side of the semiconductor die. 1. A package structure , comprising:a semiconductor die;a protection layer surrounding sidewalls of the semiconductor die;a conductive structure penetrating through the protection layer; andan interfacial layer between the protection layer and the conductive structure, wherein the interfacial layer is made of an insulating material, the interfacial layer is in direct contact with the protection layer, and the interfacial layer extends across a back side of the semiconductor die.2. The package structure as claimed in claim 1 , wherein the interfacial layer comprises polybenzoxazole (PBO) claim 1 , polyimide (PI) claim 1 , or a combination thereof.3. The package structure as claimed in claim 1 , further comprising a redistribution layer over the protection layer and a back side of the semiconductor die.4. The package structure as claimed in claim 3 , wherein the redistribution layer is electrically connected to the conductive structure.5. The package structure as claimed in claim 4 , further comprising a seed layer claim 4 , wherein the redistribution layer is between the seed layer and the conductive structure claim 4 , and a thickness ratio of the seed layer to the redistribution layer is in a range from about 0.8% to about 30%.6. The package structure as claimed in claim 3 , wherein the interfacial layer comprises a planar portion between the back side of the semiconductor die and the ...

Package structure and communications device

A package structure is disclosed, the package structure includes a substrate, a chip, a bonding layer, and a coating. A plurality of grooves are disposed on the substrate. Silver bonding materials are disposed in the grooves and on a surface of the substrate, to form the bonding layer. The chip is connected to the substrate by using the bonding layer. The grooves are symmetrically arranged along a first and a second axis that are perpendicular to each other, a vertical projection of the chip on the substrate is centrosymmetric about the first and the second axis, and the vertical projection of the chip on the substrate covers a partial area of an outer-ring groove which faces a periphery of the chip. The coating covers a surface that is of the bonding layer and not in contact with the substrate or the chip, used to prevent migration of silver ions.

THERMOCOMPRESSION BONDING WITH RAISED FEATURE

A method for bonding two substrates is described, comprising providing a first and a second silicon substrate, providing a raised feature on at least one of the first and the second silicon substrate, forming a layer of gold on the first and the second silicon substrates, and pressing the first substrate against the second substrate, to form a thermocompression bond around the raised feature. The high initial pressure caused by the raised feature on the opposing surface provides for a hermetic bond without fracture of the raised feature, while the complete embedding of the raised feature into the opposing surface allows for the two bonding planes to come into contact. This large contact area provides for high strength. 1. A bond between a first substrate and a second substrate , comprising:a first metal layer on the first substrate;a raised feature on the second substrate; anda second metal layer over the second substrate and the raised feature, wherein adhesive bonding strength between the first substrate and the second substrate is in the vicinity of the raised feature as a result of thermocompression bonding between the first metal layer and the second metal layer.2. The bond of claim 1 , wherein the second substrate and the raised feature are both silicon.3. The bond of claim 1 , wherein the first metal layer and the second metal layer are both gold claim 1 , with a thickness of about 0.5 to 6 microns.4. The bond of claim 1 , wherein the raised feature has a radius of curvature of less than about 3 microns.5. The bond of claim 1 , wherein the first substrate and the second substrate comprise at least one of glass claim 1 , metal claim 1 , semiconductor or ceramic.6. The bond of claim 1 , wherein the raised feature is completely embedded in the first metal layer.7. The bond of claim 1 , wherein a width of the raised feature is about 5 microns and a height of the raised feature above a plane of the substrate is about 1 micron.8. The bond of claim 1 , wherein a ...

Liquid ejection head and method of manufacturing the same

A recording element substrate is bonded to an FPC in at least a part of a region of a second face between a liquid supply port and an edge of the recording element substrate, and an electric connection part is provided in which a wiring conductor and a pad are electrically connected to each other by a bonding wire.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

Reliability of a semiconductor device is improved. A power device includes: a semiconductor chip; a chip mounting part; a solder material electrically coupling a back surface electrode of the semiconductor chip with an upper surface of the chip mounting part; a plurality of inner lead parts and a plurality of outer lead parts electrically coupled with an electrode pad of the semiconductor chip through wires; and a sealing body for sealing the semiconductor chip and the wires. Further, a recess is formed in a peripheral region of the back surface of the semiconductor chip. The recess has a first surface extending to join the back surface and a second surface extending to join the first surface. Also, a metal film is formed over the first surface and the second surface of the recess. 1. A method of manufacturing a semiconductor device , comprising the steps of:(a) forming a concave in a first back surface on the side opposite to a first main surface along dicing lines formed over the first main surface of a semiconductor wafer;(b) after the step (a), forming a metal film over the first back surface of the semiconductor wafer so as to enclose the concave;(c) after the step (b), dicing the semiconductor wafer along the dicing lines and forming a plurality of semiconductor chips each having a recess in a peripheral region of a second back surface located on the side opposite to a second main surface; and(d) after the step (c), mounting the semiconductor chip over a chip mounting part of a lead frame through a bonding material,wherein, in the step (d), the semiconductor chip is mounted over the chip mounting part through the bonding material such that the recess in the second back surface of the semiconductor chip comes in contact with the bonding material.2. The method of manufacturing a semiconductor device according to claim 1 , wherein a solder material is used as the bonding material.3. The method of manufacturing a semiconductor device according to claim 1 , wherein ...

Method and Structure for Supporting Thin Semiconductor Chips with a Metal Carrier

Disclosed is a method that includes: providing semiconductor dies, each of the semiconductor dies having a thinner active region surrounded by a thicker inactive region so that each of the semiconductor dies has a first cavity vertically aligned with the thinner active region and laterally surrounded by the thicker inactive region; providing a metal carrier having connection parts secured to the metal carrier, each of the connection parts dimensioned to fit within the first cavity of one of the semiconductor dies; inserting each of the connection parts of the metal carrier into the respective first cavity of the corresponding semiconductor die; after the inserting, attaching the metal carrier to the semiconductor dies; and after the attaching, singulating the metal carrier so that each of the connection parts of the metal carrier remains attached to the corresponding semiconductor die. 1. A method , comprising:providing a plurality of semiconductor dies, each of the semiconductor dies having a thinner active region surrounded by a thicker inactive region so that each of the semiconductor dies has a first cavity vertically aligned with the thinner active region and laterally surrounded by the thicker inactive region;providing a metal carrier having connection parts secured to the metal carrier, each of the connection parts dimensioned to fit within the first cavity of one of the semiconductor dies;inserting each of the connection parts of the metal carrier into the respective first cavity of the corresponding semiconductor die;after the inserting, attaching the metal carrier to the semiconductor dies; andafter the attaching, singulating the metal carrier so that each of the connection parts of the metal carrier remains attached to the corresponding semiconductor die.2. The method of claim 1 , wherein the metal carrier is a leadframe claim 1 , and wherein the connection parts of the metal carrier are raised parts of die pads of the leadframe.3. The method of claim 2 , ...

Interconnect structure for semiconductor package

A semiconductor device includes a semiconductor substrate having top and bottom surfaces, the top surface having at least one device region thereon. At least one trench opening is formed through the substrate from the bottom surface and connecting to the device region. A layer of conductive material is deposited in the at least one trench opening and partially fills the trench opening. A layer of conductive adhesive is deposited over the layer of conductive material and fills a remaining portion of the trench opening.

3-D circuits with integrated passive devices

3-D ICs ( 18, 18′, 90 ) with integrated passive devices (IPDs) ( 38 ) having reduced cross-talk and high packing density are provided by stacking separately prefabricated substrates ( 20, 30, 34 ) coupled by through-substrate-vias (TSVs) ( 40 ). An active device (AD) substrate ( 20 ) has contacts on its upper portion ( 26 ). An isolator substrate ( 30 ) is bonded to the AD substrate ( 20 ) so that TSVs ( 4030 ) in the isolator substrate ( 30 ) are coupled to the contacts ( 26 ) on the AD substrate ( 20 ), and desirably has an interconnect zone ( 44 ) on its upper surface. An IPD substrate ( 34 ) is bonded to the isolator substrate ( 30 ) so that TSVs ( 4034 ) therein are coupled to the interconnect zone ( 44 ) on the isolator substrate ( 30 ) and/or TSVs ( 4030 ) therein. The IPDs ( 38 ) are formed on its upper surface and coupled by TSVs ( 4034, 4030 ) in the IPD ( 34 ) and isolator ( 30 ) substrates to devices ( 26 ) in the AD substrate ( 20 ). The isolator substrate ( 30 ) provides superior IPD ( 38 ) to AD ( 26 ) cross-talk attenuation while permitting each substrate ( 20, 30, 34 ) to have small high aspect ratio TSVs ( 40 ), facilitating high circuit packing density and efficient manufacturing.

Semiconductor device

A semiconductor device has a resistance element including a metal block, a resin layer disposed on the metal block, and a resistance film disposed on the resin layer and an insulated circuit board including an insulating plate and a circuit pattern disposed on the insulating plate and having a bonding area on a front surface thereof to which a back surface of the metal block of the resistance element is bonded. The area of the circuit pattern is larger in plan view than that of a front surface of the resistance element. The metal block has a thickness greater than that of the circuit pattern in a direction orthogonal to the back surface of the metal block. As a result, the metal block properly conducts heat generated by the resistance film of the resistance element to the circuit pattern.

Integrated Electronic Chip and Interconnect Device and Process for Making the Same

반도체 디바이스와 마더보드에 접속시키기 위한 컨넥터를 포함하는 집적 구조물을 형성하는 방법이 설명된다. 제1층(26)은 제거 방사선에 투과성인 플레이트(23)상에 형성되고, 제2층(32)은 반도체 디바이스(31)상에 형성된다. 제1층은 결합 패드(27p)에 접속하는 제1 도체 세트(27)를 가지며, 상기 결합 패드는 마더보드에 접속하기 위해 요구되는 공간에 대응하는 제1 공간 거리의 간격을 둔다. 상기 제2 층은 상기 반도체 디바이스에 접속하는 제2 도체 세트를 갖는다. 제1층과 제2층은 상기 결합 패드의 공간보다 작은 공간을 갖는 스터드/비아 컨넥터(29,36)를 이용하여 접속된다. 상기 반도체 디바이스는 상기 제1층에 부착되고, 상기 제1 및 제2 도체 세트는 상기 스터드를 통해 접속된다. 상기 제1 층과 상기 플레이트사이의 인터페이스는 상기 플레이트를 통해 전송되는 제거 방사선(45)에 의해 제거되고, 이것에 의해 상기 플레이트를 분리한다. 컨넥터 구조물(48,48,49)이 상기 결합패드에 부착된다. 이러한 방법은 고밀도 패키징 디바이스를 절감된 비용으로 제작할 수 있게 한다. A method of forming an integrated structure comprising a connector for connecting to a semiconductor device and a motherboard is described. The first layer 26 is formed on the plate 23, which is transparent to the removal radiation, and the second layer 32 is formed on the semiconductor device 31. The first layer has a first set of conductors 27 that connect to the bond pads 27p, the bond pads being spaced at first space distances corresponding to the space required to connect to the motherboard. The second layer has a second set of conductors connecting to the semiconductor device. The first and second layers are connected using stud / via connectors 29 and 36 having a smaller space than that of the bond pad. The semiconductor device is attached to the first layer and the first and second conductor sets are connected through the stud. The interface between the first layer and the plate is removed by removal radiation 45 which is transmitted through the plate, thereby separating the plate. Connector structures 48, 48 and 49 are attached to the coupling pads. This approach enables the manufacture of high density packaging devices at reduced cost. 패키징, 컨넥터, 반도체 디바이스 Packaging, Connectors, Semiconductor Devices

Pad structure and display device having the same

본 발명에 따른 표시장치는, 기판의 표시영역에 배열된 다수의 신호라인 및 기판의 비표시영역에 위치하고, 신호라인과 연결되는 패드 구조를 포함할 수 있다. 여기서 패드 구조는, 복수의 금속층과, 각 금속층의 사이마다 위치하고, 복수의 금속층 중에서 인접한 두 금속층을 연결해주는 하나 이상의 컨택홀이 위치하는 절연막을 포함하고, 각 절연막마다의 컨택홀은 서로 중첩되지 않는다. The display device according to the present invention may include a plurality of signal lines arranged in a display area of a substrate and a pad structure positioned in a non-display area of the substrate and connected to the signal lines. Here, the pad structure includes a plurality of metal layers and an insulating film positioned between each metal layer, and one or more contact holes connecting two adjacent metal layers among the plurality of metal layers, and the contact holes for each insulating film do not overlap each other. .

Methods for bonding a hermetic module to an electrode array

A method for bonding a hermetic module to an electrode array including the steps of: providing the electrode array having a flexible substrate with a top surface and a bottom surface and including a plurality of pads in the top surface of the substrate; attaching the hermetic module to the bottom surface of the electrode array, the hermetic module having a plurality of bond-pads wherein each bond-pad is adjacent to the bottom surface of the electrode array and aligns with a respective pad; drill holes through each pad to the corresponding bond-pad; filling each hole with biocompatible conductive ink; forming a rivet on the biocompatible conductive ink over each pad; and overmolding the electrode array with a moisture barrier material.

Package structure and method for forming the same

提供一种封装结构及其形成方法。所述封装结构包括第一管芯、第二管芯、中介层、底部填充层、热界面材料及粘合剂图案。所述第一管芯及所述第二管芯并排设置在所述中介层上。所述底部填充层设置在所述第一管芯与所述第二管芯之间。所述热界面材料设置在所述第一管芯、所述第二管芯及所述底部填充层上。所述粘合剂图案设置在所述底部填充层与所述热界面材料之间，以将所述底部填充层与所述热界面材料分隔开。

Semiconductor device manufacturing method

본원의 발명과 관련되는 반도체 장치는, 실장 기판과, 상기 실장 기판에 도포된 접착제와, 상기 접착제에 의해 하면이 상기 실장 기판과 접착된 디바이스를 구비하고, 상기 디바이스의 측면 상부는 상기 디바이스의 측면 하부보다 표면 거칠기가 작은 것을 특징으로 한다.

Semiconductor device manufacturing method and semiconductor device

Interconnect structure for semiconductor package

本发明提供一种半导体装置，包括：半导体基板，具有上表面与下表面，该上表面包含至少一装置区；至少一沟槽，从该基板下表面穿过该基板，并连接至该装置区；导电层，填入部分该沟槽；以及粘着层，沉积于该导电层上，并填满该沟槽。根据本发明的封装技术可使用热分散层，使得装置有较佳的热分散效果。此外，封装过程中不会有任何焊盘污染的事情发生，同时其芯片尺寸也小于倒装提供的芯片尺寸。

Semiconductor device, method for manufacturing the same, and electronic device

[과제] 제 1 및 제 2 반도체 칩 사이의 언더필 수지층의 필릿으로부터 방출되는 반응 가스에 의한 전자 회로부의 오염을 방지할 수 있는 반도체 장치와 그 제조 방법 및 전자 기기를 제공한다. [해결 수단] 한쪽의 면에 전자 회로부(11, 12)와 제 1 접속부(언더 범프막(20))가 형성된 제 1 반도체 칩(10)상에, 한쪽의 면에 제 2 접속부(언더 범프막(32))가 형성된 제 2 반도체 칩(30)이 범프(24)에 의해 접속되어서 장착되고, 제 2 반도체 칩의 외연중의 전자 회로부의 형성 영역측의 적어도 일부에서 제 1 반도체 칩과 제 2 반도체 칩의 간극을 막는 댐(25)이 형성되고, 댐에 의해 제 2 반도체 칩의 외연으로부터 전자 회로부측으로의 돌출이 방지되도록 제 1 반도체 칩 및 제 2 반도체 칩의 간극에 언더필 수지층(26)이 충전된 구성으로 한다. [assignment] A semiconductor device capable of preventing contamination of an electronic circuit portion due to a reaction gas emitted from a fillet of an underfill resin layer between the first and second semiconductor chips, a manufacturing method thereof, and an electronic apparatus. [Solution] (The under bump film 32) is formed on one surface of the first semiconductor chip 10 on which the electronic circuit portions 11 and 12 and the first connection portion (under bump film 20) are formed on one surface, And a gap between the first semiconductor chip and the second semiconductor chip is formed in at least part of the formation region side of the electronic circuit portion of the outer periphery of the second semiconductor chip, And the underfill resin layer 26 is filled in the gap between the first semiconductor chip and the second semiconductor chip so that the dam is prevented from protruding from the outer edge of the second semiconductor chip toward the electronic circuit portion side by the dam .

METHOD FOR PRODUCING CHIP ELEMENTS WITH WIRE INSERTION GROOVES

The process comprises providing a conducting track (26) on an interconnecting substrate (22), where the conducting track is arranged to link a bonding pad of an active face of a chip (20) to an area corresponding to a first wall of grooves (14a, 14b), growing a contact pad (16) on the conducting track at the level of area corresponding to the first wall of the groove by electrodeposition, assembling the chip on the substrate by its active face so that a side wall of the chip forms a bottom of the grooves, and machining the chip by its rear surface parallel to the substrate. The process comprises providing a conducting track (26) on an interconnecting substrate (22), where the conducting track is arranged to link a bonding pad of an active face of a chip (20) to an area corresponding to a first wall of grooves (14a, 14b), growing a contact pad (16) on the conducting track at the level of area corresponding to the first wall of the groove by electrodeposition, assembling the chip on the substrate by its active face so that a side wall of the chip forms a bottom of the grooves, machining the chip by its rear surface parallel to the substrate by measuring the distance between the rear face of the chip and the contact pad, stopping the machining step when the measured distance reaches a desired value, assembling a plate (24) on the rear face of the chip by pasting to form a second wall of the groove, depositing a continuous conductor base overlying the substrate and the conductive track by electroplating, growing micro-inserts on the continuous conductor base at the conductive track contacting with the bonding pad of the active face of the chip by electrodeposition, growing the bonding pad on the continuous base, removing the excess continuous base, and assembling the chip on the substrate so its bonding pad bears on the micro-inserts. The step of assembling the chip on the substrate comprises applying a quantity of polymerizable adhesive on the rear face of the chip at ...

METHOD FOR PRODUCING CHIP ELEMENTS WITH WIRE INSERTION GROOVES

L'invention concerne un procédé de réalisation d'éléments à puce (10) munis d'une rainure (14), comprenant les étapes suivantes : prévoir, sur un substrat d'interconnexion (22), une piste conductrice (26) agencée pour relier une plage de contact d'une face active d'une puce (20) à une zone correspondant à une première paroi de la rainure ; faire croître par électrodéposition un plot de contact (16) sur la piste conductrice au niveau de la zone correspondant à la première paroi de la rainure ; assembler la puce (20) sur le substrat par sa face active de manière qu'une paroi latérale de la puce forme le fond de la rainure ; usiner la puce par sa face arrière parallèlement au substrat en mesurant la distance entre la face arrière de la puce et le plot de contact ; arrêter l'usinage lorsque la distance mesurée atteint une valeur souhaitée ; et assembler par collage une plaque (24) sur la face arrière de la puce de manière à former une deuxième paroi de la rainure. The invention relates to a method for producing chip elements (10) provided with a groove (14), comprising the following steps: providing, on an interconnection substrate (22), a conductive track (26) arranged to connecting a contact area of an active face of a chip (20) to an area corresponding to a first wall of the groove; electroplating a contact pad (16) on the conductive track at the region corresponding to the first wall of the groove; assembling the chip (20) on the substrate by its active side so that a side wall of the chip forms the bottom of the groove; machining the chip by its rear face parallel to the substrate by measuring the distance between the rear face of the chip and the contact pad; stop machining when the measured distance reaches a desired value; and bonding a plate (24) on the back side of the chip to form a second wall of the groove.

Thermal interface material and using method thereof

本发明涉及一种热界面材料，用于将一热源上的热量传递给一散热装置。所述热源具有一使所述热源不至于过热损坏的保护温度，所述热界面材料位于热源与散热装置之间。所述热界面材料包括一柔性基体及至少一填充在所述柔性基体中的第一导热颗粒。所述第一导热颗粒在熔融前的粒径小于100纳米，且该第一导热颗粒在熔融前的的熔点小于所述保护温度。所述第一导热颗粒在熔融后的粒径大于100纳米，且该第一导热颗粒在熔融后的的熔点大于所述保护温度。本发明还涉及一种该热界面材料的使用方法。

Semiconductor devices

本实用新型涉及一种半导体器件，可以包括具有开口的电路板、以及框架。该框架可以具有在该开口中的IC裸片焊盘、以及从该IC裸片焊盘向外延伸并且耦接至该电路板的多个臂。该半导体器件可以包括：安装在该IC裸片焊盘上的IC；将该电路板与该IC相耦接的多条键合接线；以及包围该IC、这些键合接线和这些臂的包封材料。

ELECTRONIC DEVICE COMPRISING A GROOVED CHIP

Dispositif électronique comprenant une plaque de support (2) qui présente une face de montage (3) et une puce électronique (8) qui présente une face avant (9) et une face arrière (10) opposée à sa face avant et qui est montée sur la plaque de support dans une position telle que la face avant de la puce est en regard de la face de montage de la plaque de support. La face arrière (10) de la puce est pourvue d'une pluralité de rainures arrière (14), de sorte que la face arrière (10) de la puce 8 présente, entre lesdites rainures (14), des zones arrière (15). Une couche arrière (16) en une matière conductrice de la chaleur est étalée sur la face arrière (10) de la puce de sorte à recouvrir au moins en partie lesdites zones arrière (15) et à remplir au moins partiellement lesdites rainures arrière (14). Electronic device comprising a support plate (2) which has a mounting face (3) and an electronic chip (8) which has a front face (9) and a rear face (10) opposite its front face and which is mounted on the support plate in a position such that the front face of the chip is opposite the mounting face of the support plate. The rear face (10) of the chip is provided with a plurality of rear grooves (14), so that the rear face (10) of the chip 8 has, between said grooves (14), rear zones (15) . A rear layer (16) of a heat conductive material is spread over the rear face (10) of the chip so as to cover at least in part said rear areas (15) and at least partially fill said rear grooves (14 ).

Semiconductor device and method for producing semiconductor device

本发明提供一种在两个半导体晶片的接合时使接合材料不易在水平方向上扩展的半导体装置的制造方法以及半导体装置。所述半导体装置具备互补型金属氧化膜半导体晶片与另外的半导体晶片，所述半导体装置的制作方法包括开口部形成工序、导通孔形成工序、配置工序、接合工序。在开口部形成工序中，在遍及作为互补型金属氧化膜半导体晶片的一部分的第一部分和作为半导体晶片的一部分的第二部分中的至少一个部分的内侧及外侧的范围内形成非贯穿的开口部。在导通孔形成工序中，在第一部分的内侧形成导通孔。在配置工序中，将第一接合材料配置在导通孔内及第一部分上，将第二接合材料配置在第二部分上。在接合工序中，将第一接合材料与第二接合材料接合。

Microelectronic packages and methods therefor

A microelectronic package includes a microelectronic element having a first face including contacts, and a flexible substrate having a first surface and a second surface, conductive posts projecting from the first surface and conductive terminals accessible at the second surface, at least some of the conductive terminals and the conductive posts being electrically interconnected and at least some of the conductive terminals being offset from the conductive posts. The first surface of the flexible substrate is juxtaposed with the first face of the microelectronic element so that the conductive posts project from the flexible substrate toward the first face of the microelectronic element. The conductive posts are electrically interconnected with the contacts of the microelectronic element and at least some of the conductive terminals are movable relative to the microelectronic element.

Light emitting device, method for fabricating the light emitting device and lighting unit

PURPOSE: A light emitting element, a method for manufacturing the same, and a light unit are provided to prevent the misalignment of a light emitting chip in a eutectic bonding process by forming a first pattern and a second pattern respectively on a package body and the light emitting chip. CONSTITUTION: A package body(10) includes a body part(11), a plurality of electrodes(31, 32), and a first pattern(35). A cavity(15) is formed in the body part. The electrodes are separated into cathodes and anodes and supply power to a light emitting chip(100). The light emitting chip is attached to the package body. A second pattern(181) is formed on the base side of the light emitting chip.

Semiconductor chip, method for mounting semiconductor chip, and module in which semiconductor chip is packaged

A semiconductor chip includes a single-crystal substrate and a metal electrode on the bottom surface of the substrate. The metal electrode has a region in which a first metal is exposed and a region in which a second metal is exposed, the second metal having a standard electrode potential different from that of the first metal.

Semiconductor module

A semiconductor module is disclosed. One embodiment provides a first semiconductor chip, a second semiconductor chip and a spacer. The first semiconductor chip has a depression at a first main surface. The spacer applied to the first main surface and at least partly fills the depression. The second semiconductor chip is applied to the spacer.

Module with semiconductor chip mounted thereon and semiconductor chip mounting method

本发明提供一种即使对于严酷的环境下的处理也能够确保充分的强度的粘接力的半导体芯片。半导体芯片具有单晶的基板和形成在基板的底面的金属电极。金属电极包含：露出了第一金属的区域；以及露出了具有与第一金属的标准电极电位不同的标准电极电位的第二金属的区域。

Semiconductor device having a frame with multiple arms and related methods

一种半导体器件可以包括具有开口的电路板、以及框架。该框架可以具有在该开口中的IC裸片焊盘、以及从该IC裸片焊盘向外延伸并且耦接至该电路板的多个臂。该半导体器件可以包括：安装在该IC裸片焊盘上的IC；将该电路板与该IC相耦接的多条键合接线；以及包围该IC、这些键合接线和这些臂的包封材料。

Method and apparatus for connecting printed wiring boards

Provided is a method for connecting printed wiring boards at least one of which is a flexible printed wiring board. A connecting terminal (4) of one printed wiring board (3) is placed over a connecting terminal (2) of the other printed wiring board (1) at a plurality of areas separated in a longitudinal direction by having an adhesive resin (6) in between. Pressure is applied to the both printed wiring boards while applying ultrasonic oscillation in a status where the adhesive resin is unhardened, and connecting terminals are bonded by solid phase intermetallic bonding at a plurality of areas. Since a time required for the solid phase intermetallic bonding (room temperature bonding) is extremely short, pressurization can be stopped without waiting for the resin to harden. Operating rate of the connecting apparatus is improved, and thus productivity is improved.

Light emitting device and light unit

本发明提供一种发光器件和灯单元。该发光器件包括：封装主体，该封装主体包括主体、凹陷部和多个电极，所述多个电极位于主体上，该凹陷部位于所述多个电极中的至少一个上；发光芯片，该发光芯片包括凸起部，该凸起部与所述凹陷部相对应，以将所述凹陷部联接并附接到所述凸起部，该发光芯片包括第一导电型半导体层、第二导电型半导体层以及有源层，该有源层位于第一导电型半导体层和第二导电型半导体层之间；以及附着层，该附着层位于发光芯片的底表面上。

Package systems having a eutectic bonding material and manufacturing methods thereof

A package system includes a first substrate. A second substrate is electrically coupled with the first substrate. At least one electrical bonding material is disposed between the first substrate and the second substrate. The at least one electrical bonding material includes a eutectic bonding material. The eutectic bonding material includes a metallic material and a semiconductor material. The metallic material is disposed adjacent to a surface of the first substrate. The metallic material includes a first pad and at least one first guard ring around the first pad.

Semiconductor device and method for forming the same

A method for forming a semiconductor device is provided. The method includes providing a substrate. The method includes forming a mask layer over a surface of the substrate. The mask layer has an opening over a portion of the surface. The method includes depositing a conductive layer over the surface and the mask layer. The method includes removing the mask layer and the conductive layer over the mask layer. The conductive layer remaining after the removal of the mask layer and the conductive layer over the mask layer forms a conductive pad. The method includes bonding a device to the conductive pad through a solder layer. The conductive pad is embedded in the solder layer.

Method for producing chip elements equipped with wire insertion grooves

本发明涉及一种装配有配线插入槽的芯片元件的制造方法。该方法包括以下步骤：在互连基板(22)上设置导电路(26)，该导电路(26)布置为将芯片(20)的有源表面的接触区域连接到与槽的第一壁对应的区域；在与槽的第一壁对应的区域处，通过电沉积在导电路上生长接触凸块(16)；将芯片(20)经由其有源表面组装到基板上，以使得芯片的侧壁形成槽的底部；经由芯片的与基板平行的背表面加工芯片，并同时测量芯片的该背表面与接触凸块之间的距离；当测量距离到达所要求的值时停止加工；以及通过接合将板(24)组装到芯片的背表面，以形成槽的第二壁。

Methods of forming 3-D circuits with integrated passive devices

Methods of forming 3-D ICs with integrated passive devices (IPDs) include stacking separately prefabricated substrates coupled by through-substrates-vias (TSVs). An active device (AD) substrate has contacts on its upper portion. An isolator substrate is bonded to the AD substrate so the TSVs in the isolator substrate are coupled to the contacts on the AD substrate. An IPD substrate is bonded to the isolator substrate so that TVs therein are coupled to an interconnect zone on the isolator substrate and/or TSVs therein. The IPDs of the IPD substrate are coupled by TSVs in the IPD and isolator substrates to devices in the AD substrate. The isolator substrate provides superior IPD to AD cross-talk attenuation while permitting each substrate to have small high aspect ratio TSVs, thus facilitating high circuit packing density and efficient manufacturing.

Semiconductor package

반도체 패키지의 부피를 최소화할 수 있는 고용량화된 반도체 패키지를 제공한다. 본 발명에 따른 반도체 패키지는 본딩 패드를 가지는 패키지 베이스 기판, 서로 반대되는 활성면 및 비활성면을 가지는 반도체 기판, 반도체 기판의 활성면에 형성되는 반도체 소자, 반도체 소자와 전기적으로 연결되는 제1 패드, 반도체 기판에 대하여 제1 패드와 동일 레벨을 가지며 제1 패드보다 반도체 기판의 가장자리에 인접하는 도전 패턴 및 제1 패드 상에 연결되고 도전 패턴과 이격되면서 도전 패턴 상으로 연장되는 제2 패드를 각각 포함하되, 제2 패드가 적어도 일부 노출되도록 제1 방향으로 소정거리만큼 쉬프트(shift)되며 패키지 베이스 기판 상에 적층되는 복수의 반도체 칩, 및 복수의 반도체 칩들 각각의 제2 패드와 본딩 패드를 연결하는 본딩 와이어를 포함한다.

Lead frame with notched lead ends

A lead frames has a forked top portion which has a recessed portion adjusted for receipt of a wire so that the wire is so caught by the forked top portion as to prevent the wire from being largely carried. Even if the density of the wires is high, the wires are not carried by the flow of the molten resin so that the wires are kept from contact with each other thereby avoiding short circuits. At the corners, the distance of the adjacent two wires is narrower than the other positions. Notwithstanding, the wires at the corners are also prevented by the forked top portion of the lead frame from being largely carried by the flow of the molten resin so that the wires are kept from contact with each other thereby avoiding short circuit.

Module having semiconductor chip mounted thereon, and semiconductor chip mounting method

Flip-chip semiconductor package structure and package substrate applicable thereto

Power module, preparation method thereof and electrical equipment

本发明提供了一种功率模块及其制备方法、电器设备，该功率模块包括：衬底，衬底的一侧为电路层；设置在电路层上的至少一个第一芯片，且每个第一芯片与电路层电连接；镶嵌在衬底上的印刷电路板，且印刷电路板外露在电路层一侧；且印刷电路板与至少一个第一芯片电连接；设置在印刷电路板的至少一个第二芯片，且每个第二芯片与所述印刷电路板电连接。在上述技术方案中，通过采用将印刷电路板镶嵌在衬底中承载芯片，方便了芯片的设置，并且通过芯片可以通过印刷电路板、衬底直接散热，提高了散热效果。

Vertical semiconductor arrangement e.g. semiconductor chip stack, for printed circuit board substrate, has auxiliary layer that is bounded on area of relevant main side or includes structure provided with recess, channel, wall and trench

The arrangement has a wafer (1), and a semiconductor chip (2) including main sides that are arranged opposite to each other and connected with each other. A filling material as underfill (3) is provided in an intermediate space between the wafer and the chip. A structured auxiliary layer (6) is provided on one of the main sides, where the layer is in contact with the underfill. The auxiliary layer is bounded on an area of the relevant main side or includes a structure formed from a group of structures and provided with a recess, channel, wall and a trench. An independent claim is also included for a method for manufacturing a vertical semiconductor arrangement.

Button rectifier package for non-planar die

Axial lead semiconductor device package (30) for use with non-planar semiconductor die (23). By using solders of predetermined strength, wetting and flow characteristics, melting temperature, shape, area, and thickness, reliable attachment of non-planar die (23) to planar mounting surfaces (36) is achieved.

Wafer level integrated interconnect decal and manufacturing method thereof

A wafer level integrated interconnect decal manufacturing method and wafer level integrated interconnect decal arrangement. In accordance with the technology concerning the soldering of integrated circuits and substrates, and particularly providing for solder decal methods forming and utilization, in the present instance there are employed underfills which consist of a solid film material and which are applied between a semiconductor chip and the substrate in order to enhance the reliability of a flip chip package. In particular, the underfill material increases the resistance to fatigue of controlled collapse chip connect (C4) bumps.

Semiconductor device and method for manufacturing same

This semiconductor device is provided with: a semiconductor chip (11, 11H, 11L) having an electrode (12) on one surface (11a); a first conductive member (23, 23H, 23L) on the one surface side of the semiconductor chip; a metal member (18, 18H, 18L), which has a base material (19a) and a film (19b), and is disposed between the semiconductor chip and the first conductive member; a first solder (17) between the metal member and the electrode of the semiconductor chip; and a second solder (22) between the metal member and the first conductive member. The film has, on the front surface of the base material, a metal thin film (20) and a recessed and protruding oxide film (21, 31, 32). The recessed and protruding oxide film is disposed on the metal thin film in a part of a connection region (18f) that connects to each other a first connection region (18d) having the first solder connected thereto, and a second connection region (18e) having the second solder connected thereto, said part being a part of the front surface of the metal member.

Semiconductor device with frame having arms and related methods

A semiconductor device may include a circuit board having an opening, and a frame. The frame may have an IC die pad in the opening, and arms extending outwardly from the IC die pad and coupled to the circuit board. The semiconductor device may include an IC mounted on the IC die pad, bond wires coupling the circuit board with the IC, and encapsulation material surrounding the IC, the bond wires, and the arms.

Method for low-temperature solid bonding of semiconductor device

本发明的半导体器件低温固态键合的方法，包括以下步骤：1）选择具有相互匹配的电互连焊盘的至少两个待键合元件；2）在一待键合元件的多个焊盘上形成铜微针锥群；3）在另一待键合元件的多个焊盘上形成至少表面设有低硬度第二金属层的凸点；4）使所述凸点与所述铜微针锥群接触，将所述凸点与所述铜微针锥群的接触部分加热到第一温度，施加键合压力使所述凸点与所述铜微针锥群电互连键合。与现有技术相比，本发明的工艺过程不需要将温度加热到焊料熔点以上以使焊料熔化，可避免对器件产生热损伤，且固态键合能够提高互连密度和产品可靠性，界面反应可控，无需助焊剂等有机物因而简化了工艺流程。

Circuit connection material, film-form circuit connecting material using the same, circuit member connecting structure, and method of manufacturing the same

The present invention is a circuit connecting material used for the mutual connection of a circuit member in which electrodes and insulating layers are formed adjacent to each other on the surface of a board, and a circuit member in which electrodes and insulating layers are formed adjacent to each other on the surface of a board, with the edge parts and of the insulating layers being formed with a greater thickness than the electrodes on the basis of the main surfaces, wherein this circuit connecting material contains a bonding agent composition and conductive particles that have a mean particle size of 1 μm or greater but less than 10 μm and a hardness of 1.961 to 6.865 GPa, and this circuit connecting material exhibits a storage elastic modulus of 0.5 to 3 GPa at 40° C. and a mean coefficient of thermal expansion of 30 to 200 ppm/° C. at from 25° C. to 100° C. when subjected to the curing treatment.

Micromechanical method and corresponding arrangement for bonding semiconductor substrates and corresponding bonded semiconductor chip

Die Erfindung schafft ein mikromechanisches Verfahren und eine entsprechende Anordnung zum Bonden von Halbleitersubstraten sowie einen entsprechenden gebondeten Halbleiterchip. Die Anordnung umfasst ein Halbleitersubstrat mit einem Chipmuster mit einer Vielzahl von Halbleiterchips (1), welche jeweils einen Funktionsbereich (4) und einen den Funktionsbereich (4) umgebenden Randbereich (4a) aufweisen, wobei im Randbereich (4a) beabstandet vom Funktionsbereich (4) ein Bondrahmen (2) aus einer Bondlegierung aus mindestens zwei Legierungskomponenten vorgesehen ist. Innerhalb des vom Bondrahmen (2) umgebenen Teils (4a2) des Randbereichs (4a) zwischen dem Bondrahmen (2) und dem Funktionsbereich (4) ist mindestens ein Stopprahmen (7; 7a, 7b; 7b'; 70) aus mindestens einer der Legierungskomponenten vorgesehen, der derart gestaltet ist, dass bei einem Auftreffen einer Schmelze der Bondlegierung beim Bonden auf den Stopprahmen (7; 7a, 7b; 7b'; 70) ein Erstarren der Bondlegierung auftritt. The invention creates a micromechanical method and a corresponding arrangement for bonding semiconductor substrates and a corresponding bonded semiconductor chip. The arrangement comprises a semiconductor substrate with a chip pattern with a plurality of semiconductor chips (1), each of which has a functional area (4) and an edge area (4a) surrounding the functional area (4), with the edge area (4a) spaced apart from the functional area (4) a bond frame (2) made of a bond alloy composed of at least two alloy components is provided. Within the part (4a2) of the edge area (4a) between the bond frame (2) and the functional area (4) surrounded by the bond frame (2) there is at least one stop frame (7; 7a, 7b; 7b '; 70) made of at least one of the alloy components provided, which is designed such that when a melt of the bonding alloy strikes the stop frame (7; 7a, 7b; 7b '; 70) during bonding, the bonding alloy solidifies.

Method for permanent bonding of wafers

本發明係關於一種將一第一固體基板(1)接合至包含一第一材料之一第二固體基板(2)的方法，該方法按照以下步驟，尤其是按照以下序列：-將包含一第二材料之一功能層(5)形成或施加至該第二固體基板(2)，-在該功能層(5)上使該第一固體基板(1)與該第二固體基板(2)接觸，-將該等固體基板(1、2)擠壓在一起以形成該等第一與第二固體基板(1、2)之間之一永久接合，該永久接合至少部分藉由引起該功能層上之一體積增加之該第一材料與該第二材料之固體擴散及/或相變而加強。

Solder fatigue arrest for wafer level package

A wafer level package includes a wafer, a lead disposed of the wafer for connecting the wafer to an electrical circuit, and a core disposed of the lead. In some embodiments, the lead disposed of the wafer is a copper pillar, and the core is plated onto the copper pillar. In some embodiments, the core is polymer screen-plated onto the lead. In some embodiments, the core extends between at least approximately thirty-five micrometers (35 μm) and fifty micrometers (50 μm) from the lead. In some embodiments, the core covers between at least approximately one-third (⅓) and one-half (½) of the surface area of the lead. In some embodiments, the core comprises a stud-shape extending from the lead. In some embodiments, the core extends perpendicularly across the lead. In some embodiments, the core extends longitudinally along the lead. Further, a portion of the core can extend perpendicularly from a longitudinal core.

Method of making a low-Rdson vertical power MOSFET device

The invention relates to a power semiconductor device and its preparation methods thereof. Particularly, the invention aims at providing a method for reducing substrate contribution to the Rdson (drain-source on resistance) of power MOSFETs, and a power MOSFET device made by the method. By forming one or more bottom grooves at the bottom of Si substrate, the on resistance of the power MOSFET device attributed to the substrate is effectively reduced. A matching lead frame base complementary to the substrate with bottom grooves further improves the package of the power MOSFET device.

Method and apparatus for connecting printed wiring board

Provided is a method for connecting printed wiring boards at least one of which is a flexible printed wiring board. A connecting terminal (4) of one printed wiring board (3) is placed over a connecting terminal (2) of the other printed wiring board (1) at a plurality of areas separated in a longitudinal direction by having an adhesive resin (6) in between. Pressure is applied to the both printed wiring boards while applying ultrasonic oscillation in a status where the adhesive resin is unhardened, and connecting terminals are bonded by solid phase intermetallic bonding at a plurality of areas. Since a time required for the solid phase intermetallic bonding (room temperature bonding) is extremely short, pressurization can be stopped without waiting for the resin to harden. Operating rate of the connecting apparatus is improved, and thus productivity is improved.

Semiconductor unit with submount for semiconductor device

Mechanisms for forming package structure

일부 실시예들에 따라서, 패키지 구조물 및 패키지 구조물을 형성하기 위한 방법이 제공된다. 패키지 구조물은, 반도체 다이 및 반도체 다이를 부분적으로 또는 완전히 캡슐화하는 몰딩 화합물을 포함한다. 패키지 구조물은 또한 상기 몰딩 화합물 내의 패키지 관통 비아를 포함한다. 상기 패키지 구조물은 상기 패키지 관통 비아와 상기 몰딩 화합물 사이의 계면 층을 더 포함한다. 상기 계면 층은 절연 재료를 포함하고 상기 몰딩 화합물과 직접적으로 접촉한다. According to some embodiments, a method is provided for forming a package structure and a package structure. The package structure includes a molding compound that partially or fully encapsulates the semiconductor die and the semiconductor die. The package structure also includes package through vias in the molding compound. The package structure further includes an interface layer between the package through vias and the molding compound. The interface layer comprises an insulating material and is in direct contact with the molding compound.

Electronic device comprising a nanotube-based interface connection layer, and manufacturing method thereof

An electronic device including a first region belonging to a semiconductor device having a first surface; a second region having a second surface; and an adhesion layer, set between the first and second regions, including first fibrils each having respective first and second ends. The first fibrils extend between the first and second surfaces and are fixed in a chemico-physical way to the first and second surfaces at the respective first and second ends.

Circuit connecting material, film-form circuit connecting material using the same, circuit member connecting structure and method of manufacturing the same

Semiconductor device, method for manufacturing the same, and electronic device

本发明涉及半导体器件、半导体器件制造方法以及电子装置。所述半导体器件包括：第一半导体芯片，在所述第一半导体芯片的一个表面上形成有电子电路部和第一连接部；第二半导体芯片，在所述第二半导体芯片的一个表面上形成有第二连接部，所述第二半导体芯片安装在所述第一半导体芯片上，且所述第一连接部与所述第二连接部通过凸块彼此连接；坝体，所述坝体形成在所述第二半导体芯片的外缘的一部分上并填充所述第一半导体芯片与所述第二半导体芯片间的间隔，所述外缘的所述一部分位于形成有所述电子电路部的区域侧；以及底部填充树脂层，它填充在所述间隔中，所述坝体防止所述底部填充树脂层从所述第二半导体芯片的所述外缘向所述电子电路部侧突出。

Method for junction of semiconductor substrate

본 발명의 일 실시예에 따른 반도체 기판의 접합 방법은 제1 반도체 기판 위에 정렬 키를 형성하는 단계, 상기 제1 반도체 기판 및 상기 정렬 키 위에 절연막을 형성하는 단계, 상기 절연막 위에 제1 금속층 패턴 및 제2 금속층 패턴을 형성하는 단계, 제2 반도체 기판 위에 제1 돌출부, 제2 돌출부 및 상기 제1 돌출부와 상기 제2 돌출부 사이에 위치하는 정렬 홈을 형성하는 단계, 상기 제1 돌출부 및 상기 제2 돌출부 위에 각각 제3 금속층 패턴 및 제4 금속층 패턴을 형성하는 단계, 그리고 상기 제1 반도체 기판 및 상기 제2 반도체 기판을 접합하는 단계를 포함하고, 상기 제1 반도체 기판 및 상기 제2 반도체 기판의 접합 시, 상기 정렬 키는 상기 정렬 홈에 위치한다. A method of bonding a semiconductor substrate according to an embodiment of the present invention includes forming an alignment key on a first semiconductor substrate, forming an insulating film on the first semiconductor substrate and the alignment key, Forming a second metal layer pattern on the second semiconductor substrate, forming a first protrusion, a second protrusion, and an alignment groove located between the first protrusion and the second protrusion on the second semiconductor substrate, Forming a third metal layer pattern and a fourth metal layer pattern on the protrusions, and bonding the first semiconductor substrate and the second semiconductor substrate, wherein the bonding of the first semiconductor substrate and the second semiconductor substrate , The alignment key is located in the alignment groove.

IMPROVEMENT IN SEMICONDUCTOR DIODE PACKAGES, IN PARTICULAR PAD DIODES

Semiconductor integrated circuit having standard and custom circuit regions

A semiconductor device includes a mother chip having a standard integrated circuit and electrodes pads, and an option chip having a custom integrated circuit, the option chip being provided over a part of the mother chip via connectors.

Semiconductor chip module and method of manufacturing the same

Abstract of the Disclosure The semiconductor chip module comprises a substrate on which a wiring portion is formed, a semiconductor chip mounted so as to face a circuit side down to the wiring portion, a heat sink with one end in contact with a side opposite to the circuit side of the semiconductor chip, and a cap enclosing the semiconductor chip and having an opening exposing externally the other end of the heat sink. A metal film is formed at least on the inner wall of the opening and on the surface of the heat sink which is inserted into the cap. An adhesive material is filled between the tip portion of the heat sink and the semiconductor chip, while an adhesive material is filled between the metal films.

Fastening device

本发明涉及一种固定装置，其包括：一具有集成电路的半导体本体；一构造在所述半导体本体的表面上的介电钝化层；一构造在所述钝化层下方的带状导体；一构造在所述带状导体下方的氧化物层；一连接介质，所述连接介质在一构造在所述钝化层上方的构件与所述半导体本体之间形成力锁合的连接，其中，一透穿所述钝化层和所述氧化物层的成型部具有一底部面并且在所述底部面上构造一导电层并且所述连接介质在所述导电层与所述构件之间构造电连接。

ARRANGEMENT WITH SEMICONDUCTOR DEVICE INCLUDING CHIP CARRIER, SEMICONDUCTOR WAFER AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Anordnung mit Halbleitervorrichtung, umfassend:einen Chipträger (300),eine Halbleiter-Die (100) mit einem Halbleiterteil (110) und einer leitenden Struktur (120),eine Lötschicht (200), die mechanisch und elektrisch den Chipträger (300) und die leitende Struktur (120) an einer Lötseite der Halbleiter-Die (100) verbindet,wobei an der Lötseite ein äußerster Oberflächenteil (112c) einer Rückseitenoberfläche (112) des Halbleiterteils (110) längs eines Randes der Halbleiter-Die (100) einen größeren Abstand zu dem Chipträger (300) aufweist als ein zentraler Oberflächenteil (112a) der Rückseitenoberfläche (112),wobei die leitende Struktur (120) den zentralen Oberflächenteil (112a) und wenigstens einen Abschnitt eines Zwischenoberflächenteiles (112b) bedeckt, der zu dem zentralen Oberflächenteil (112a) geneigt ist und die zentralen und äußersten Oberflächenteile (112a, 112c) verbindet,wobei die leitende Struktur (120) eine erste Unterschicht (122) eines ersten Materials, das eine Barriereschicht bildet, die für Kupferionen und -atome undurchdringbar ist, und zwischen der ersten Unterschicht (122) und der Lötschicht (200) wenigstens eine weitere Unterschicht (124) aus einem leitenden zweiten Material aufweist, das von dem ersten Material verschieden ist, undwobei die erste Unterschicht (122) den zentralen Oberflächenteil (112a), den Zwischenoberflächenteil (112b) und den äußersten Oberflächenteil (112c) bedeckt, undwobei die wenigstens eine weitere Unterschicht (124, 126) den zentralen Oberflächenteil (112a) und mindestens einen Abschnitt des Zwischenoberflächenteils (112b) bedeckt und entlang des äußersten Oberflächenteils (112c) fehlt. A semiconductor device assembly comprising: a chip carrier (300), a semiconductor die (100) having a semiconductor portion (110) and a conductive structure (120), a solder layer (200) mechanically and electrically connecting the chip carrier (300) and the conductive structure (120) at a soldering side of the semiconductor die (100), wherein ...

Semiconductor device and its manufacturing method and connection structure

(57)【要約】 【課題】 突起電極と回路電極の間の導電材料が接続時 の加熱、加圧の時に流れだしを防止し、充分な接続抵抗 値と信頼性を確保する。 【解決手段】 突起電極２２頂部の中央部が周縁部より も低くし、突起電極２２と回路電極間の導電性材料３２ が接続加圧されたときに、異方性導電接着剤３４の流動 とともに流れ出すのを抑え、突起電極２２と回路電極２ ６との間の導電性材料を充分な数が確保できる半導体装 置とその製造方法およびその接続構造。

Semiconductor package, method for forming semiconductor package, and method for forming semiconductor assembly

一種半導體封裝結構包含一第一封裝結構組件，該第一封裝結構組件包含一第一側、與該第一側相對之一第二側及位於該第一側上方之複數個凹陷拐角。該半導體封裝結構包含置於該等凹陷拐角處之複數個第一應力緩衝結構，且各該等第一應力緩衝結構具有一彎曲表面。該半導體封裝結構包含連接至該第一封裝結構組件之一第二封裝結構組件及放置於之間的複數個連接件。該半導體封裝結構包含位於該第一封裝結構組件與該第二封裝結構組件之間的一底膠材料，且該等第一應力緩衝結構之該彎曲表面之至少一部分與該底膠材料接觸且嵌入於該底膠材料中。

Semiconductor chip, method for mounting semiconductor chip, and module in which semiconductor chip is packaged

本發明提供一種即使對於嚴酷的環境下的處理也能夠確保充分的強度的黏接力的半導體晶片。半導體晶片具有單晶的基板和形成在基板的底面的金屬電極。金屬電極包含：露出第一金屬的區域；以及露出具有與第一金屬的標準電極電位不同的標準電極電位的第二金屬的區域。

Semiconductor component with metallized sidewalls on silicon wafer power components has a metal edging surrounding the components on an underside and on partially covered metal sidewalls and deep troughs etched on silicon wafers.

An electronic power component (1) with a metal layer (2) on a silicon substrate has a metal edging (3) surrounding it on an underside (5) and on sidewalls (4) partially covered with metal edging. Deep troughs are etched on a silicon wafer's rear side. The troughs and the rear side are metallized. The power components with partial sidewall metallizing (3.1) fit on a metal heat sink (7) by means of a soldered joint (6).

3-D semiconductor die structure with containing feature and method

A die-on-die assembly has a first die ( 10 ) and a second die ( 50 ). The first die ( 10 ) has a first contact extension ( 28,42 ) and a peg ( 32,44,45 ) extending a first height above the first die. The second die ( 50 ) has a second contact extension ( 68 ) connected to the first contact extension and has a containing feature ( 62 ) extending a second height above the second die surrounding the peg. The peg extends past the containing feature. Because the peg extends past the containing feature, lateral movement between the first and second die can cause the peg to come in contact with and be constrained by the containing feature. The peg and containing feature are thus useful in constraining movement between the first and second die.

A method of attaching a metal surface to a carrier and method of attaching a chip to a chip carrier

Verfahren zum Befestigen einer Metallfläche an einen Träger, wobei das Verfahren folgendes aufweist:• Aufbringen einer porösen Schicht über der Metallfläche; und• Aufbringen eines Materials über einer Seite des Trägers; und• Inkontaktbringen des Materials mit der porösen Schicht mittels Zusammenführens der Metallfläche, auf welcher die poröse Schicht aufgebracht ist, und des Trägers, auf welchem das Material aufgebracht ist, wobei das Material in Poren der porösen Schicht eingebracht wird, so dass das Material eine Verbindung zwischen der Metallfläche und dem Träger bildet. A method of attaching a metal surface to a support, the method comprising: depositing a porous layer over the metal surface; and • applying a material over one side of the carrier; and contacting the material with the porous layer by bringing together the metal surface on which the porous layer is applied and the support on which the material is applied, the material being introduced into pores of the porous layer so that the material forms a bond forms between the metal surface and the carrier.

Semiconductor device manufacturing method

本发明提供半导体装置的制造方法，其目的是提高半导体装置的可靠性和制造成品率。准备第一电极和第二电极通过绝缘层被分离的半导体元件，在金属箔上配置焊接材料，在焊接材料上以第三电极与其接触的方式载置半导体元件。此外，使片状的焊接材料与半导体元件的第一电极和第二电极相对，使柱电极的下端隔着焊接材料与第一电极上表面和第二电极上表面相对。而且，使焊接材料隔着绝缘层分离，通过焊接材料使第一电极与柱电极接合，并且通过焊接材料使第二电极与柱电极接合。此外，通过焊接材料使第三电极与金属箔接合。由此，能够提高半导体装置的可靠性和制造成品率。

Microstructures and method for wafer to wafer bonding

Wafer-to-wafer bonding using, e.g., solder metal bonding, glass bonding or polymer (adhesive) bonding is improved by profiling one or both of the wafer surfaces (22, 20) being bonded to define microstructures therein. Profiling means providing other than the conventional planar bonding surface to define cavities therein. The bonding material (24) fills the cavities in the microstructures (26). For instance, a system of ridges and trenches (e.g. in cross-section vertical, slanted, key-holed shaped, or diamond-shaped) are microstructures that increase the surface area of the wafers to which the bonding material can adhere. Use of the key-hole shaped or diamond-shaped profile having a negative slope at the trench interior substantially increases the bonding force.

Semiconductor device manufacturing method

　半導体チップにシート状樹脂組成物が貼り付けられたシート状樹脂組成物付きチップを準備する工程Ａと、被着体を準備する工程Ｂと、被着体に、シート状樹脂組成物付きチップを、シート状樹脂組成物を貼り合わせ面にして貼り付ける工程Ｃと、工程Ｃの後に、シート状樹脂組成物を加熱して半硬化させる工程Ｄと、工程Ｄの後に、工程Ｄにおける加熱よりも高温でシート状樹脂組成物を加熱して硬化させる工程Ｅとを含む半導体装置の製造方法。

Semiconductor device and semiconductor device manufacturing method

A semiconductor device according to the present invention includes a mount substrate, an adhesive applied to the mount substrate, and a device having its lower surface bonded to the mount substrate with the adhesive. The surface roughness of a side surface upper portion of the device is lower than that of a side surface lower portion of the device.

Semiconductor device pepackage

반도체 소자 패키지 및 개선된 땜납 접합부 구조를 사용하여 이 패키지를 제조하는 방법이 개시되어 있다. 상기 패키지는 상부 부분보다 얇은 저부 부분을 갖는 땜납 접합부를 포함한다. 저부 부분은 몰딩 화합물에 의해 둘러싸이고, 상부 부분은 몰딩 화합물에 의해 둘러싸이지 않는다. 상기 방법은 이형 필름을 사용하여 중간 땜납 접합부 주위에 액체 몰딩 화합물을 증착 및 형성하는 것과, 그 다음에 몰딩 화합물을 감소된 높이로 에칭하는 것을 포함한다. 결과적인 땜납 접합부는 몰딩 화합물과 땜납 접합부의 인터페이스에서 웨이스트(waist)를 갖지 않는다. 몰딩 화합물을 에칭 후에, 형성 직후의 몰딩 화합물보다 약 3 미크론 더 큰 거칠기를 갖는다. A method of fabricating the package using a semiconductor device package and an improved solder joint structure is disclosed. The package includes a solder joint having a bottom portion that is thinner than the top portion. The bottom portion is surrounded by the molding compound and the top portion is not surrounded by the molding compound. The method includes depositing and forming a liquid molding compound around the intermediate solder joint using a release film, and then etching the molding compound to a reduced height. The resulting solder joint does not have a waist at the interface of the molding compound and the solder joint. After etching the molding compound, it has a roughness of about 3 microns greater than the molding compound immediately after formation.

Semiconductor package, method for forming semiconductor package, and method for forming semiconductor assembly

一種半導體封裝結構包含一第一封裝結構組件，該第一封裝結構組件包含一第一側、與該第一側相對之一第二側及位於該第一側上方之複數個凹陷拐角。該半導體封裝結構包含置於該等凹陷拐角處之複數個第一應力緩衝結構，且各該等第一應力緩衝結構具有一彎曲表面。該半導體封裝結構包含連接至該第一封裝結構組件之一第二封裝結構組件及放置於之間的複數個連接件。該半導體封裝結構包含位於該第一封裝結構組件與該第二封裝結構組件之間的一底膠材料，且該等第一應力緩衝結構之該彎曲表面之至少一部分與該底膠材料接觸且嵌入於該底膠材料中。

Semiconductor device assembly including a chip carrier, semiconductor wafer and method of manufacturing a semiconductor device

本发明涉及包括芯片载体的半导体器件组件、半导体晶片和制造半导体器件的方法。一种半导体器件包括芯片载体以及具有半导体部分和传导结构半导体管芯。焊接层在半导体管芯的焊接侧机械连接和电连接芯片载体和传导结构。在焊接侧，沿半导体管芯的边缘的最外侧表面部分到芯片载体的距离大于中央表面部分到芯片载体的距离。传导结构覆盖中央表面部分以及中间表面部分的至少区段，所述中间表面部分相对于中央表面部分倾斜。焊接材料被有效地防止以免于涂覆易受损坏的这样的半导体表面，并且焊接引起的污染被显著地减少。

SEMI-CONDUCTOR COMPONENT

Ein Halbleiterbauteil beinhaltet einen Chip, der eine Montagefläche, eine Nicht-Montagefläche und eine Seitenwand aufweist, die die Montagefläche und die Nicht-Montagefläche verbindet, und der einen Überhangabschnitt aufweist, der an der Seitenwand weiter nach außen vorsteht als die Montagefläche, und mit einer Metallschicht, die die Montagefläche bedeckt. A semiconductor device includes a chip that has a mounting surface, a non-mounting surface, and a side wall connecting the mounting surface and the non-mounting surface, and which has an overhang portion that protrudes further outward on the side wall than the mounting surface, and with a Metal layer that covers the mounting surface.

Integrated electronic chip and interconnect device and process for making the same

A method is described for forming an integrated structure, including a semiconductor device and connectors for connecting to a motherboard. A first layer is formed on a plate transparent to ablating radiation, and a second layer on the semiconductor device. The first layer has a first set of conductors connecting to bonding pads, which are spaced with a first spacing distance in accordance with a required spacing of connections to the motherboard. The second layer has a second set of conductors connecting to the semiconductor device. The first layer and second layer are connected using a stud/via connectors having spacing less than that of the bonding pads. The semiconductor device is thus attached to the first layer, and the first set and second set of conductors are connected through the studs. The interface between the first layer and the plate is ablated by ablating radiation transmitted through the plate, thereby detaching the plate. The connector structures are then attached to the bonding pads. This method permits fabrication of a high-density packaged device with reduced cost.

Method for permanently bonding wafers by a connecting layer by means of solid-state diffusion or phase transformation

본 발명은 제1 고체 기판(1)을 제1 물질을 포함하는 제2 고체 기판(2)에 접착하기 위한 방법이며, - 제2 물질을 포함하는 기능 층(5)을 제2 고체 기판(2)에 적용 또는 형성하고; - 상기 기능 층(5) 상의 제2 고체 기판(2)과 제1 고체 기판(1)을 접촉시키며; -고체 기판(1, 2)을 함께 프레스하여 제1 및 제2 고체 기판(1, 2) 사이의 영구 접착을 형성하도록 하는 순차적인 단계를 포함하고, 상기 영구 접착이 제1 물질과 제2 물질의 고체 확산 및/또는 상 변환에 의해 적어도 부분적으로 보강되고, 상기 기능 층 상의 볼륨 증가가 발생되도록 하는 방법에 대한 것이다. The present invention relates to a method for bonding a first solid substrate (1) to a second solid substrate (2) comprising a first material, characterized in that - the functional layer (5) ); - contacting the first solid substrate (1) with the second solid substrate (2) on the functional layer (5); - pressing the solid substrates (1, 2) together to form a permanent bond between the first and second solid substrates (1, 2), wherein the permanent adhesion comprises a first and a second material At least in part, by solid diffusivity and / or phase transformation of the active layer, resulting in an increase in volume on the functional layer.

Circuit member connecting structure

Protection of integrated circuits

A first integrated circuit chip is assembled to a second integrated circuit chip with a back-to-back surface relationship. The back surfaces of the integrated circuit chips are attached to each other using one or more of an adhesive, solder or molecular bonding. The back surface of at least one the integrated circuit chips is processed to include at least one of a trench, a cavity or a saw cut.