СПОСОБ ФОРМИРОВАНИЯ СОЕДИНЕНИЯ В БИНАРНОЙ СИСТЕМЕ И СОЕДИНЕНИЕ, ПОЛУЧЕННОЕ ТАКИМ СПОСОБОМ

Ein Schaltkreisgehäuse, ein elektronisches Schaltkreisgehäuse und Verfahren zum Verkapseln eines elektronischen Schaltkreises

Ein Schaltkreisgehäuse wird bereitgestellt, das Schaltkreisgehäuse aufweisend: einen elektronischen Schaltkreis; einen Metallblock neben dem elektronischen Schaltkreis; eine erste Metallschichtstruktur elektrisch kontaktiert mit mindestens einem ersten Kontakt auf einer ersten Seite des elektronischen Schaltkreises; eine zweite Metallschichtstruktur elektrisch kontaktiert mit mindestens einem zweiten Kontakt auf einer zweiten Seite des elektronischen Schaltkreises, wobei die zweite Seite gegenüberliegend der ersten Seite ist; wobei der Metallblock elektrisch kontaktiert ist mit der ersten Metallschichtstruktur und der zweiten Metallschichtstruktur mittels eines elektrisch leitfähigen Mediums; und wobei das elektrisch leitfähige Medium ein Material verschieden von dem Material der ersten und der zweiten Metallschichtstruktur oder eine Materialstruktur verschieden von dem Material der ersten und der zweiten Metallschichtstruktur aufweist.

Anordnung mit drei Halbleiterchips und Herstellung einer solchen Anordnung

Anordnung, umfassend:einen ersten Halbleiterchip, der eine erste Kontaktstelle auf einer ersten Seite umfasst;einen zweiten Halbleiterchip, der eine erste Kontaktstelle auf einer ersten Seite umfasst, wobei der zweite Halbleiterchip über dem ersten Halbleiterchip platziert ist und die erste Seite des ersten Halbleiterchips der ersten Seite des zweiten Halbleiterchips zugewandt ist; genau eine Schicht aus einem elektrisch leitfähigen Material, die zwischen dem ersten Halbleiterchip und dem zweiten Halbleiterchip angeordnet ist, wobei die genau eine Schicht aus einem elektrisch leitfähigen Material die erste Kontaktstelle des ersten Halbleiterchips elektrisch mit der ersten Kontaktstelle des zweiten Halbleiterchips koppelt;eine Passivierungsschicht, die einen Teil der ersten Seite des ersten Halbleiterchips außerhalb der ersten Kontaktstelle überdeckt; undeinen auf der Passivierungsschicht angebrachten dritten Halbleiterchip,wobei der erste und der zweite Halbleiterchip jeweils Leistungs-Halbleiterchips ...

Sinterwerkstoff, Sinterverbindung sowie Verfahren zum Herstellen eines Sinterverbindung

Die Erfindung betrifft einen Sinterwerkstoff mit metallischen, mit einer organischen Beschichtung versehenen Strukturpartikeln. Erfindungsgemäß ist vorgesehen, dass nicht-organisch beschichtete, metallische und/oder keramische, beim Sinterprozess nicht ausgasende Hilfspartikel (7) vorgesehen sind. Ferner betrifft die Erfindung eine Sinterverbindung (1) sowie ein Verfahren zum Herstellen einer Sinterverbindung (1).

Semiconductor device and method for manufacturing method of semiconductor device

The semiconductor device comprises a base

SEMICONDUCTOR PACKAGE SUBSTRATE

Improved method of making a chip device

A method and arrangement for packaging a plurality of chip devices. The method includes providing a plurality of bottom leadframes coupled together with rails to form a bottom leadframe assembly and providing a plurality of top leadframes coupled together with rails to form a top leadframe assembly. Dies are placed between the top and bottom leadframes and the top and bottom leadframe assemblies are coupled to one another. The dies are attached to die attach pads of the bottom leadframes and are coupled to the top leadframes with solder bumps. A molded body is placed around the top and bottom leadframes with the dies there between and the rails are removed from the top and bottom leadframes, thus providing a plurality of chip devices.

MICROCIRCUIT PACKAGE HAVING DUCTILE LAYER

A microcircuit package having a ductile layer between a copper flange and die attach. The ductile layer absorbs the stress between the flange and semiconductor device mounted on the flange, and can substantially reduce the stress applied to the semiconductor device. In addition, the package provides the combination of copper flange and polymeric dielectric with a TCE close to copper, which results in a low stress structure of improved reliability and conductivity.

Method for soldering surface-mount component and surface-mount component

A method for soldering a surface-mount component onto a circuit board. The melting of die-bonding solder material is prevented by using a mounting solder material when soldering a surface-mount component formed using the die-bonding solder material onto a printed circuit board. The surface-mount component, formed using (Sn—Sb)-based solder material having high melting point, the (Sn—Sb)-based solder material containing Cu but not more than a predetermined quantity of Cu constituent and a main ingredient thereof being Sn, is soldered on a board terminal portion of a circuit board using (Sn—Ag—Cu—Bi)-based solder material or (Sn—Ag—Cu—Bi—In)-based solder material as the mounting solder material and with the solder material being applied on the terminal portion. Since solidus temperature of the die-bonding solder material is 243 degrees C. and liquidus temperature of the mounting solder material is about 215 through 220 degrees C., the melting of die-bonding solder material is prevented even ...

Method for Fabricating an Electronic Component

A carrier and a semiconductor chip are provided. A connection layer is applied to a first main face of the semiconductor chip. The connection layer includes a plurality of depressions. A filler is applied to the connection layer or to the carrier. The semiconductor chip is attached to the carrier so that the connection layer is disposed between the semiconductor chip and the carrier. The semiconductor chip is affixed to the carrier.

Interconnect structure with redundant electrical connectors and associated systems and methods

Semiconductor die assemblies having interconnect structures with redundant electrical connectors are disclosed herein. In one embodiment, a semiconductor die assembly includes a first semiconductor die, a second semiconductor die, and an interconnect structure between the first and the second semiconductor dies. The interconnect structure includes a first conductive film coupled to the first semiconductor die and a second conductive film coupled to the second semiconductor die. The interconnect structure further includes a plurality of redundant electrical connectors extending between the first and second conductive films and electrically coupled to one another via the first conductive film.

Electronic devices with semiconductor die attached with sintered metallic layers, and methods of formation of such devices

An electronic device includes a semiconductor die having a lower surface, a sintered metallic layer underlying the lower surface of the semiconductor die, a conductive layer underlying the sintered metallic layer, and a conductive substrate underlying the conductive layer.

Power semiconductor element bonded to a substrate by a Sn-Sb-Cu solder and manufacturing method therefor

A power semiconductor device includes a substrate (14), an element circuit pattern (16) formed on the substrate (14) and made of Cu optionally covered with an electroless-plated Ni-P layer, and a power semiconductor element (40,42) bonded to the element circuit pattern (16) by a solder (30,32), wherein the solder (30,32) is an alloy of Sn, Sb, and Cu, the Sb content being in the range of 6.5 to 8 weight % and the Cu content being in the range of 0.5 to 1 weight %. A terminal (52) is bonded to a terminal circuit pattern (18, 20) formed on the substrate (14) by a terminal solder (50) made of a Sn-Ag-based or Sn-Ag-Cu-based unleaded solder. A heat sink (46) is bonded to a surface pattern (22) formed on the bottom surface the substrate (14) by a solder (34) having the same composition as the Sn-Sb-Cu solder (30, 32).

Semiconductor device and on-vehicle AC generator

An object of the present invention is to provide, at low costs, an environmental friendly bonding material for a semiconductor, having sustained bonding reliability even when used at a temperature as high as 200°C or higher for a long period of time, the semiconductor device having a semiconductor element (1), a supporting electrode body (3) bonded to a first face of the semiconductor element (1) via a first bonding member (4), and a lead electrode body (7) bonded to a second face of the semiconductor element (1) supported by the supporting electrode body (3) via a second bonding member (2), the semiconductor device having a Ni-based plating layer and an intermetallic compound layer containing at least one of Cu6Sn5 and (Cu,Ni)6Sn5 compounds at an interface between the supporting electrode body (3) and the first bonding member (4), and having a Ni-based plating layer and an intermetallic compound layer containing at least one of Cu6Sn5 and (Cu,Ni)6Sn5 compounds at an interface between the ...

HIGH TEMPERATURE SOLDER, HIGH TEMPERATURE SOLDER PASTE MATERIAL AND POWER SEMICONDUCTOR EQUIPMENT USING THE SAME

PROBLEM TO BE SOLVED: To provide power semiconductor equipment using a high temperature lead-free solder material having excellent heat resistance at ≥280°C, joinability at ≤400°C, solder feedability and wettability, high temperature holding reliability and temperature cycle reliability. SOLUTION: The power semiconductor equipment is obtained by joining a semiconductor device and a metal electrode member with a high temperature solder material having a composition comprising Sn, Sb, Ag and Cu as the main constituting elements and satisfying 42 wt.%≤Sb/(Sn+Sb)≤48 wt.%, 5 wt.%≤Ag<20 wt.%, 3 wt.%≤Cu<10 wt.% and 5 wt.%≤Ag+Cu≤25 wt.%, and the balance other inevitable impurity elements. COPYRIGHT: (C)2007,JPO&INPIT ...

SEMICONDUCTOR DEVICE, AND ON-VEHICLE AC GENERATOR

PROBLEM TO BE SOLVED: To provide a connection material for a semiconductor element that is small in environmental load and inexpensive, and can maintain connection reliability even when used at a high temperature of ≥200°C for a long time. SOLUTION: A semiconductor device includes the semiconductor element, a support electrode body connected to a first surface of the semiconductor element through a first connection member, and a lead electrode body connected to a second surface of the semiconductor element supported by the support electrode body through a second connection member, and has an Ni-based plating layer and an inter-metal compound layer containing at least one of a Cu6Sn5 compound and a (Cu, Ni) 6Sn5 compound, on an interface between the support electrode body and the first connection member, and an Ni-based plating layer and an inter-metal compound layer containing at least one of a Cu6Sn5 compound and a (Cu, Ni) 6Sn5 compound, on an interface between the lead electrode body ...

Verfahren zur Herstellung eines elektronischen Bauteils

Es werden ein Träger und ein Halbleiterchip bereitgestellt. Eine Verbindungsschicht wird auf eine erste Hauptfläche des Halbleiterchips aufgetragen. Die Verbindungsschicht umfasst eine Mehrzahl von Vertiefungen. Ein Füllmaterial wird auf die Verbindungsschicht oder den Träger aufgetragen. Der Halbleiterchip wird so am Träger befestigt, dass die Verbindungsschicht zwischen dem Halbleiterchip und dem Träger angeordnet ist. Der Halbleiterchip wird am Träger fixiert.

Halbleitervorrichtung mit Grundplatte

Eine Halbleitervorrichtung umfasst einen Halbleiterchip (136) und eine Grundplatte (102), die mit dem Halbleiterchip (136) gekoppelt ist. Die Grundplatte (102) umfasst einen oberen und einen unteren Abschnitt (112, 114). Der obere Abschnitt (112) weist eine Bodenfläche (106) auf, die sich mit einer Seitenwand (108) des unteren Abschnitts (114) trifft. Die Halbleitervorrichtung umfasst ein Kühlelement (160), das mit der Grundplatte (102) gekoppelt ist. Das Kühlelement (160) weist eine erste Fläche (166) auf, die direkt mit der Bodenfläche (106) des oberen Abschnitts (112) der Grundplatte (102) in Berührung ist, eine zweite Fläche (170), die die Seitenwand (108) des unteren Abschnitts (114) der Grundplatte (102) direkt berührt, und eine dritte Fläche (168), die parallel zu der ersten Fläche (166) verläuft und die bündig zu einer Bodenfläche (110) des unteren Abschnitts (114) der Grundplatte (102) angeordnet ist.

HALBLEITERVORRICHTUNG

Die Entstehung thermischer Spannungen und eine Verschlechterung der Qualität werden unterdrückt.In einer Halbleitervorrichtung (10) ist in einer seitlichen Querschnittsansicht eine erste Stirnfläche (15a1) einer leitfähigen Struktur (15a) zwischen dem äußersten Rand (16a1) einer Vertiefung (16a) und dem innersten Rand (16b2) einer Vertiefung (16b) angeordnet. Wenn eine thermische Spannung aufgrund von Temperaturänderungen in der Halbleitervorrichtung (10) auf die keramische Leiterplatte (13) einwirkt, unterdrückt die Mehrzahl von Vertiefungen (16a und 16b) eine durch die Temperaturänderungen verursachte Verformung der keramischen Leiterplatte (13). Folglich werden Risse in der keramischen Leiterplatte (13) und eine Abtrennung der Metallplatte (16) und der leitfähigen Struktur (15a) verhindert.

CONTACT STRUCTURE FOR SECURING A SEMICONDUCTOR SUBSTRATE TO A MOUNTING BODY

A B S T R A C T A contact structure for securing a semiconductor substrate to a mounting body in a semiconductor device. A multi-layered electrode formed on a surface of the semiconductor substrate, the multi-layered electrode comprising a chromium-nickel alloy layer formed on the surface, a nickel layer formed thereon and a noble metal layer selected from the group consisting of gold, silver, palladium and platinum formed further thereon, a solder layer, and a mounting means for holding the semiconductor substrate thereon, the solder layer soldering the multi-layered electrode to the mounting means, thereby bonding the semiconductor substrate to the mounting means. The foregoing construction has the features that there are substantially no voids at the solder layer as a result of good wetting of the noble metal to the solder layer; that the effective bonding area increases as a result of decrease of voids, resulting in decrease of thermal resistance by 10 to 20%; that secondary breakdown voltage increases by about 10%, thereby increasing reliability; that the bonding force is drastically increased; that process control in the soldering step becomes easier; that undesirable Sn-Ni formation is suppressed, thereby improving resistivity to thermal fatigue; and that oxidation of the surface of the multi-layered electrode is eliminated, thereby eliminating the necessity for preliminary treatment before soldering.

Solder, contact structure and method of fabricating contact structure

Provided is a solder and a contact structure formed by the solder. The solder includes a zinc-based metal layer, a copper film, and a precious metal film. The copper film completely covers the surface of the zinc-based metal layer, and the precious metal film completely covers the copper film. The contact structure includes a zinc-based metal layer and an intermetallic layer. The intermetallic layer consists of zinc and a precious metal and completely covers the surface of the zinc-based metal layer.

SINTERED MATERIAL, SINTERED BOND AND PROCESS FOR PRODUCING A SINTERED BOND

The invention relates to a sintered material comprising metallic structure particles provided with an organic coating. It is envisaged in accordance with the invention that metallic and/or ceramic auxiliary particles (7) with a non-organic coating, which do not outgas in the course of the sintering process, are provided. The invention further relates to a sintered bond (1) and to a process for producing a sintered bond (1).

Semiconductor device and method of forming PIP with inner known good die interconnected with conductive bumps

A PiP semiconductor device has an inner known good semiconductor package. In the semiconductor package, a first via is formed in a temporary carrier. A first conductive layer is formed over the carrier and into the first via. The first conductive layer in the first via forms a conductive bump. A first semiconductor die is mounted to the first conductive layer. A first encapsulant is deposited over the first die and carrier. The semiconductor package is mounted to a substrate. A second semiconductor die is mounted to the first conductive layer opposite the first die. A second encapsulant is deposited over the second die and semiconductor package. A second via is formed in the second encapsulant to expose the conductive bump. A second conductive layer is formed over the second encapsulant and into the second via. The second conductive layer is electrically connected to the second die.

Strong, heat stable junction

Provided among other things is an electrical device comprising: a first component that is a semiconductor or an electrical conductor; a second component that is an electrical conductor; and a strong, heat stable junction there between including an intermetallic bond formed of: substantially (a) indium (In), tin (Sn) or a mixture thereof, and (b) substantially nickel (Ni). The junction can have an electrical contact resistance that is small compared to the resistance of the electrical device.

Semiconductor device

A semiconductor device comprises a first metal lead frame portion with a chip mounting surface, a second metal lead frame portion, and a semiconductor chip with a first surface facing and attached to the chip mounting surface of the first metal lead frame part and a second surface facing away from the chip mounting surface of the first metal lead frame part. A connector portion is electrical connected to the second metal lead frame portion and is attached to the second surface of the semiconductor chip. The connector portion covers the entirety of a planar area of the semiconductor chip when viewed along a direction orthogonal to second surface of the semiconductor chip.

CHIP PACKAGE AND A METHOD FOR MANUFACTURING A CHIP PACKAGE

A chip package is provided, the chip package including: a carrier including at least one cavity; a chip disposed at least partially within the at least one cavity; at least one intermediate layer disposed over at least one side wall of the chip; wherein the at least one intermediate layer is configured to thermally conduct heat from the chip to the carrier.

Transient liquid phase sinter pastes and application and processing methods relating thereto

The present invention relates to transient liquid phase sinter pastes for electronic interconnects, and sinter paste application and processing methods.

3DIC Package and Method Forming the Same

A method includes bonding a first device die to a second device die through face-to-face bonding, wherein the second device die is in a device wafer, forming a gap-filling region to encircle the first device die, performing a backside-grinding process on the device wafer to reveal a through-via in the second device die, and forming a redistribution structure on the backside of the device wafer. The redistribution structure is electrically connected to the first device die through the through-via in the second device die. A supporting substrate is bonded to the first device die.

Semiconductor device and on-vehicle AC generator

An object of the present invention is to provide, at low costs, an environmental friendly bonding material for a semiconductor, having sustained bonding reliability even when used at a temperature as high as 200°C or higher for a long period of time, the semiconductor device having a semiconductor element (1), a supporting electrode body (3) bonded to a first face of the semiconductor element (1) via a first bonding member (4), and a lead electrode body (7) bonded to a second face of the semiconductor element (1) supported by the supporting electrode body (3) via a second bonding member (2), the semiconductor device having a Ni-based plating layer and an intermetallic compound layer containing at least one of Cu6Sn5 and (Cu,Ni)6Sn5 compounds at an interface between the supporting electrode body (3) and the first bonding member (4), and having a Ni-based plating layer and an intermetallic compound layer containing at least one of Cu6Sn5 and (Cu,Ni)6Sn5 compounds at an interface between the ...

Solder material and electronic part using the same

This invention provides a lead-free high temperature solder material comprising 0.005-3.0 wt % of palladium (Pd) and 97.0-99.995 wt % of tin (Sn) whose liquidus temperature is 200-350°C. The solder material is environmentally-friendly, improved in thermal fatigue property, and it can improve the reliability of electronic apparatuses. A predetermined amount of Sn material and Pd is mixed, vacuum-melted and cast to prepare an ingot. The ingot is rolled to be a tape that is later pressed to obtain a solder pellet. In a preferable composition, at least 95 wt % of Sn and 0.005-3.0 wt 5 of Pd are contained, and 0.1-5.0 wt % of metallic (e.g. Cu, Ni) or alloy particles are added. The average particle diameter is about 40 µm. A substrate and an IC chip (5) (electronic element) are die-bonded substantially in parallel by a solder material (3) provided between an Ni plating (4) on the lower side of an IC chip (semiconductor) (5) and an Ni plating (2) on a die (1). ...

パッケージキャリアの製造方法

半導体装置接合材

КОМПОЗИТНЫЙ МАТЕРИАЛ, СПОСОБ ЕГО ПОЛУЧЕНИЯ, ИЗЛУЧАЮЩАЯ ТЕПЛО ПАНЕЛЬ ДЛЯ ПОЛУПРОВОДНИКОВОГО ПРИБОРА, ПОЛУПРОВОДНИКОВЫЙ ПРИБОР (ВАРИАНТЫ), ДИЭЛЕКТРИЧЕСКАЯ ПАНЕЛЬ И ЭЛЕКТРОСТАТИЧЕСКОЕ ПОГЛОЩАЮЩЕЕ УСТРОЙСТВО

FIELD: power electronics, polycrystalline modules. SUBSTANCE: proposed composite material includes metal and inorganic compound so formed that it has dendrite or rod shape. Specifically this material presents copper composite material that contains from 10 to 55 volume per cent of copper oxide Cu 2 O and Cu and random impurities and coefficient of thermal expansion in temperature range from room temperature to + 300 C of 5•10 -6 / ° C to 17•10 -6 / ° C and thermal conductivity from 100 to 380 W/(m•k). Given composite material can be produced by process which includes stages of melting, molding and treatment, it is good for panel of semiconductor device emitting heat. EFFECT: increased plasticity and strength of composite material, prevention of deterioration of properties of semiconductor device caused by heat generation, raised functional reliability of it. 20 cl, 20 dwg бубзегс пы сэ (19) РОССИЙСКОЕ АГЕНТСТВО ПО ПАТЕНТАМ И ТОВАРНЫМ ЗНАКАМ ВО 2 198 949 7 МК С 22С 1/05, 9/00, 29/12, (13) С2 32/00, НОЕ 23/373 12) ОПИСАНИЕ ИЗОБРЕТЕНИЯ К ПАТЕНТУ РОССИЙСКОЙ ФЕДЕРАЦИИ (21), (22) Заявка: 2000106644/28, 15.03.2000 (24) Дата начала действия патента: 15.03.2000 (30) Приоритет: 16.03.1999 УР 11-069540 (46) Дата публикации: 20.02.2003 (56) Ссылки: УР 9-209058 А, 12.08.1997. 4Р 1-106451 А, 24.04.1989. УР 10-163307 А, 19.06.1998. КЦ 2047952 СЛ, 10.11.1995. (98) Адрес для переписки: 129010, Москва, ул. Б. Спасская, 25, стр.3, ООО "Юридическая фирма Городисский и Партнеры", Ю.Д.Кузнецову, рег.№ 595 (71) Заявитель: ХИТАЧИ, ЛТД. (УР) (72) Изобретатель: ОКАМОТО Казутака (4+Р), КОНДО Йасуо (/Р), АБЕ Теруйоси (.Р), АОНО Йасухиса (/Р), КАНЕДА Дзунйа (.Р), САИТО Риуити (/Р), КОИКЕ Йосихико (/Р) (73) Патентообладатель: ХИТАЧИ, ЛТД. (4Р) (74) Патентный поверенный: Кузнецов Юрий Дмитриевич (54) КОМПОЗИТНЫЙ МАТЕРИАЛ, СПОСОБ ЕГО ПОЛУЧЕНИЯ, ИЗЛУЧАЮЩАЯ ТЕПЛО ПАНЕЛЬ ДЛЯ ПОЛУПРОВОДНИКОВОГО ПРИБОРА, ПОЛУПРОВОДНИКОВЫЙ ПРИБОР (ВАРИАНТЫ), ДИЭЛЕКТРИЧЕСКАЯ ПАНЕЛЬ И ЭЛЕКТРОСТАТИЧЕСКОЕ ПОГЛОЩАЮЩЕЕ ...

ПОЛУПРОВОДНИКОВОЕ УСТРОЙСТВО И СПОСОБ ИЗГОТОВЛЕНИЯ ПОЛУПРОВОДНИКОВОГО УСТРОЙСТВА

Полупроводниковое устройство (2) содержит первый и второй полупроводниковые элементы (3, 5) и первый и второй токопроводящие элементы (10, 29). Первый электрод (3а) на первом полупроводниковом элементе крепится к первому столбиковому элементу (12) первого токопроводящего элемента посредством первого связующего слоя (8а). Второй электрод (5b) на втором полупроводниковом элементе крепится к второму столбиковому элементу (25) второго токопроводящего элемента посредством второго связующего слоя (8f). Первый соединяющий элемент (13) первого токопроводящего элемента крепится к второму соединяющему элементу (26) второго токопроводящего элемента посредством промежуточного связующего слоя (8g). Первая поверхность первого соединяющего элемента, обращенная к второму соединяющему элементу, боковая поверхность первого соединяющего элемента, являющаяся продолжением упомянутой первой поверхности, вторая поверхность второго соединяющего элемента, обращенная к первому соединяющему элементу, и боковая поверхность ...

Metallteil, Metallteiloberflächenbearbeitungsverfahren, Halbleitervorrichtung, Halbleitervorrichtungsherstellungsverfahren und Verbundformkörper

Die Aufgabe der vorliegenden Erfindung ist die Ausbildung einer rauen Oberfläche zum Zweck der Sicherstellung einer Haftung zwischen einem Metallteil und anderen Teilen oder einer rauen Oberfläche zum Unterdrücken einer Ausdehnung eines Lots in dem Metallteil unter Verwendung eines Energiestrahls mit einer Energiedichte, die geringer ist als die im Stand der Technik. Ein Oberflächenbearbeitungsverfahren eines Metallteils (2), in welchem ein Metalldünnfilm (22) auf einer Oberfläche (21a) einer Basis (21) angeordnet ist, gemäß der vorliegenden Erfindung umfasst: Schmelzen oder Verdampfen eines Oberflächenbereichs des Metalldünnfilms durch Bestrahlen der Oberfläche (22a) des Metalldünnfilms mit einem pulsoszillierten Laserstrahl mit einer Energiedichte von 100 J/cm2 oder weniger und einer Pulsdauer von 1 μs oder weniger; und Aufrauen der Oberfläche des Metalldünnfilms durch Verfestigen des Oberflächenbereichs des Metalldünnfilms nach dem Schmelzen oder Verdampfen. Der Metalldünnfilm ist aus ...

Verfahren und System zum Ausbilden eines dünnen Halbleiterbauelements

Es werden ein Verfahren und ein System zum Ausbilden eines dünnen Halbleiterbauelements offenbart. Bei einer Ausführungsform wird ein Systemträger (102) über einem Träger (100) bereitgestellt. Mindestens ein Halbleiterchip (108) wird auf dem Systemträger (102) bereitgestellt, und der mindestens eine Halbleiterchip (108) wird mit einem Kapselungsmaterial (120) gekapselt. Die Dicke des mindestens einen Halbleiterchips (108) und des Kapselungsmaterials (120) werden reduziert. Mindestens eine Durchverbindung (128, 130, 132) wird in dem Kapselungsmaterial (120) ausgebildet, und mindestens ein elektrisches Kontaktelement (134, 136, 138) wird über dem mindestens einen Halbleiterchip (108) und der mindestens einen Durchverbindung (128, 130, 132) ausgebildet.

SINTERABLE BONDING MATERIAL AND SEMICONDUCTOR DEVICE USING THE SAME

METHOD OF PERMANENT JOINING OF TWO ELEMENTS BY INTERDIFFUSION TRANSIENT LIQUID PHASE

SEMICONDUCTOR DEVICE, A CONNECTION STRUCTURE, AND A MANUFACTURING METHOD THEREOF, CAPABLE OF IMPROVING CONNECTION RELIABILITY AGAINST THERMAL STRESS

PURPOSE: A semiconductor device, a connection structure, and a manufacturing method thereof are provided to obtain suitable humidity of a connection material using the connection material which forms a Zn based alloy layer on the outermost of an AL based alloy layer. CONSTITUTION: A semiconductor device includes a semiconductor device, a frame, and a connection unit. The connection unit connects the semiconductor device with the frame and includes an Al layer(102), a first Zn layer(101), and a second Zn layer. The first Zn layer is formed on the semiconductor device of the Al layer. The first Zn layer is connected to the semiconductor device. The second Zn layer is formed on the frame of the Al layer and is connected to the frame. COPYRIGHT KIPO 2010 ...

SEMICONDUCTOR DEVICE, CONTACT STRUCTURE AND MANUFACTURING METHOD THEREOF

Soldered joint and method for forming soldered joint

Provided are: a soldered joint which suppresses detachment between a back metal and a solder alloy during formation of the soldered joint, and which offers higher reliability by suppressing non-wetting of the solder alloy, splashing of molten solder, and breakage of an electronic component due to chip cracking; and a method for forming such a soldered joint. In this soldered joint, an electronic component equipped with a back metal is bonded to a substrate via a solder alloy. The solder alloy has: a solder alloy layer having an alloy composition comprising, in mass%, 2-4% of Ag, 0.6-2% of Cu, 9.0-12% of Sb, 0.005-1% of Ni with the remainder being Sn; a Sn-Sb intermetallic compound phase; a back metal-side intermetallic compound layer; and a substrate-side intermetallic compound layer. The solder alloy layer is interposed between the Sn-Sb intermetallic compound phase and the back metal-side intermetallic compound layer and/or between the Sn-Sb intermetallic compound phase and the substrate-side ...

Power electronic module and method for producing a power electronic module

The invention relates to a power electronic module comprising at least one semiconductor element, in particular a power semiconductor element, and a carrier with at least one function surface for the indirect connecting with the semiconductor element. According to the invention, a barrier layer of palladium is directly or indirectly formed on the function surface of the carrier at least in sections, wherein the semiconductor element is directly or indirectly connected with the side of the barrier layer facing away from the function surface of the carrier by means of a layer of a silver sinter paste.

Bonding method and bonding material using metal particle

It is an object of this invention to provide a bonding material capable of realizing bonding by metallic bonding at a bonding interface at a lower temperature compared to a bonding material using a metal particle having an average particle diameter of not more than 100 nm and a bonding method. There is provided a bonding material including a metal particle precursor being at least one selected from the group consisting of a particle of a metal oxide, a particle of a metal carbonate, and a particle of a metal carboxylate and having an average particle diameter of 1 nm to 50 μm and a reducing agent composed of an organic substance, wherein the content of the metal particle precursor is more than 50 parts by mass and not more than 99 parts by mass per 100 parts by mass of the bonding material.

Contact structure for a semiconductor substrate on a mounting body

In bonding a semiconductor substrate onto a mounting means, a multiple layer metal electrode is formed on the surface, the multiple layer comprising at least a chromium-nickel alloy layer, nickel layer and a noble metal layer of a noble metal selected from a group consisting of gold, silver or platinum, which is bonded to a solder layer of Pb-Sn-alloy or Ag-Sb-Sn-alloy of the mounting means.

THERMAL MATCHED COMPOSITE DIE

A thermal matched composite material, suitable for use as a die is described. In one example, the material includes a metal plate and a substrate having a coefficient of thermal expansion (CTE) lower than the metal plate to carry microelectronic circuits. An adhesive layer between the substrate and the metal plate physically attaches the metal plate to the substrate so that the combined metal plate and substrate have a higher CTE than the substrate alone.

Method and system for forming a thin semiconductor device

A method and system for forming a thin semiconductor device are disclosed. In one embodiment, a lead frame is provided over a carrier. At least one semiconductor chip is provided on the lead frame and the at least one semiconductor chip is enclosed with an encapsulating material. The thickness of the at least one semiconductor chip and the encapsulating material are reduced. At least one through connection is formed in the encapsulating material and at least one electrical contact element is formed over the at least one semiconductor chip and the at least one through connection.

Semiconductor package substrate

Disclosed herein is a semiconductor package substrate including a base substrate, a mounting member mounted on an upper portion of the base substrate, and an adhesive layer formed between the base substrate and the mounting member, wherein the adhesive layer includes a thermally conductive adhesive and a ductile adhesive formed at the outer circumference of the thermally conductive adhesive.

Silicon nitride circuit board

This invention provides a silicon nitride circuit board in which a metal circuit plate is bonded to a high thermal conductive silicon nitride substrate having a thermal conductivity of not less than 60 W/m K, wherein a thickness DS of the high thermal conductive silicon nitride substrate and a thickness DM of the metal circuit plate satisfy a relational formula DS ≦ 2DM. The silicon nitride circuit board is characterized in that, when a load acts on the central portion of the circuit board which is held at a support interval of 50 mm, a maximum deflection is not less than 0.6 mm until the silicon nitride substrate is broken. The silicon nitride circuit board is characterized in that, when an anti-breaking test is performed to the circuit board which is held at a support interval of 50 mm, an anti-breaking strength is not less than 500 MPa. The metal circuit plate or a circuit layer are integrally bonded on the silicon nitride substrate by a direct bonding method, an active metal brazing ...

Lötmetalllegierung und Halbleiterbauteil

Eine Lötmetalllegierung (3) enthält 5 bis 15 Masse-% Sb, 3 bis 8 Masse-% Cu, 0,01 bis 0,15 Masse-% Ni und 0,5 bis 5 Masse-% In. Deren Rest enthält Sn und unvermeidbare Fremdstoffe. Dadurch können eine hochzuverlässige Lötmetalllegierung (3) und ein Halbleiterbauteil (1) erzielt werden, bei denen ein Bruch in einem Halbleiterelement (2) unterbunden und die Rissbildungsresistenz eines Lötmaterials verbessert ist.

Bauelement mit einem Halbleiterchip und einem Träger und Fabrikationsverfahren

Verfahren, umfassend: Bereitstellen eines Halbleiterchips (10), wobei Halbleitermaterial an einer ersten Oberfläche (11) des Halbleiterchips (10) exponiert ist; Platzieren des Halbleiterchips (10) über einem Träger (12), wobei die erste Oberfläche (11) dem Träger (12) zugewandt ist und elektrisch leitendes Material (13) zwischen dem Halbleiterchip (10) und dem Träger (12) angeordnet ist; und Zuführen von Wärme, um den Halbleiterchip (10) an dem Träger (12) anzubringen, wobei das elektrisch leitende Material (13) beim Zuführen der Wärme gesintert wird.

Vorrichtung und Verfahren mit einem Lötprozess

Verfahren, umfassend: Bereitstellen eines Substrats (11); Bereitstellen eines Halbleiterchips (10), der eine erste Fläche (12) mit einer Rauheit von mehr als 500 nm besitzt; Aufbringen einer Metalllage (14) auf die erste Fläche (12) des Halbleiterchips (10), wobei eine Oberfläche der Metalllage (14) eine Rauheit von mehr als 500 nm aufweist; und Ausführen eines Diffusionslötprozesses, um die erste Fläche (12) des Halbleiterchips (10) unter Bildung mindestens einer intermetallischen Phase (16) mit dem Substrat (11) zu verbinden.

Microcircuit package having ductile layer

A microcircuit package having a ductile layer between a copper flange and die attach. The ductile layer absorbs the stress between the flange and semiconductor device mounted on the flange, and can substantially reduce the stress applied to the semiconductor device. In addition, the package provides the combination of copper flange and polymeric dielectric with a TCE close to copper, which results in a low stress structure of improved reliability and conductivity.

면 실장 부품의 솔더링 방법 및 면 실장 부품

... 다이본드용 땜납 재료를 사용하여 형성된 면 실장 부품을, 실장용 땜납 재료를 사용하여 프린트 기판에 솔더링할 때라도, 다이본드용 땜납 재료의 용해가 일어나지 않도록 하였다. 다이패드용 땜납 재료(30)로서, Cu의 함유량이 소정값 이하인 Sn을 주성분으로 하는 (Sn-Sb)계의 고융점 땜납 재료를 사용하여 형성된 면 실장 부품을, 회로 기판의 기판 단자부에 도포된 실장용 땜납 재료(70)로서, (Sn-Ag-Cu-Bi)계 땜납 재료를 사용하여 솔더링한다. 다이본드용 땜납 재료(30)의 고상선 온도는 243℃이고, 실장용 땜납 재료(70)의 액상선 온도는 215 내지 220℃ 정도이므로, 리플로우 노의 가열 온도(240℃ 이하)에 의해서도 다이본드용 땜납 재료(30)는 용해되지 않는다.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

The present invention relates to a semiconductor device and a manufacturing method of a semiconductor device. The semiconductor device includes: a semiconductor element; a member to be joined which is joined to the semiconductor element and on which a nickel film is formed; and a junction layer jointing the member to be joined and containing a copper element at the rate of greater than or equal to 2.0 wt%. The junction layer includes; a solder unit in which at least tin is included in an element of a basic material and confraternal copper is included inside the base material; and a Cu_6Sn_5 unit in contact with the nickel film. COPYRIGHT KIPO 2016 ...

Semiconductor device and method of forming embedded die substrate, and system-in-package modules with the same

A semiconductor device has a first substrate. A first semiconductor component is disposed on a first surface of the first substrate. A second substrate includes a vertical interconnect structure on a first surface of the second substrate. A second semiconductor component is disposed on the first surface of the second substrate. The first semiconductor component or second semiconductor component is a semiconductor package. The first substrate is disposed over the second substrate with the first semiconductor component and second semiconductor component between the first substrate and second substrate. A first encapsulant is deposited between the first substrate and second substrate. A SiP submodule is disposed over the first substrate or second substrate opposite theencapsulant. A shielding layer is formed over the SiP submodule.

Semiconductor device and method of manufacturing semiconductor device

A semiconductor device (100) includes: a semiconductor element (6); a joined member (2) that is joined to the semiconductor element and includes a nickel film (2a); and a joining layer (4) that is joined to the joined member and contains 2.0 wt% or higher of copper, in which the joining layer includes a solder portion (4a) and a Cu6Sn5 portion, base metal of the solder portion contains at least tin as a constituent element and contains elemental copper, and the Cu6Sn5 portion is in contact with the nickel film.

Die Attach Methods and Semiconductor Devices Manufactured based on Such Methods

A method includes providing a carrier, depositing a die attach material on the carrier, and arranging a semiconductor die on the die attach material, wherein a main surface of the semiconductor die facing the die attach material at least partly contacts the die attach material, wherein immediately after arranging the semiconductor die on the die attach material, a first maximum extension of the die attach material over edges of the main surface is less than about 100 micrometers. 1. A method , comprising:providing a carrier;depositing a die attach material on the carrier; andarranging a semiconductor die on the die attach material,wherein a main surface of the semiconductor die facing the die attach material at least partly contacts the die attach material,wherein immediately after arranging the semiconductor die on the die attach material, a first maximum extension of the die attach material over edges of the main surface is less than about 100 micrometers.2. The method of claim 1 , further comprising:forming a fillet of the die attach material at a side surface of the semiconductor die, wherein forming the fillet is based on a creeping of the die attach material along the side surface of the semiconductor die.3. The method of claim 2 , wherein the creeping of the die attach material is based on an adhesive force between the die attach material and the semiconductor die.4. The method of one of claim 1 , further comprising:after arranging the semiconductor die on the die attach material, further extending the die attach material over the edges of the main surface,wherein a second maximum extension of the die attach material over the edges of the main surface is less than about 200 micrometers.5. The method of claim 1 , further comprising:curing the die attach material at a curing time in a range from about 10 minutes to about 3 hours and a curing temperature in a range from about 100 degrees Celsius to about 300 degrees Celsius.6. The method of claim 1 , wherein a ...

Bonding structure on gold thin film

The present invention provides a bonding method (S1) which is capable of achieving a high adhesive force without carrying out any special treatment on the second member (14), even in a case where the first member (11) has a surface on which a gold thin film (12) is formed. The first member (11) is made of a material other than gold and has a surface on which the gold thin film (12) is formed. The bonding method (S1) includes the steps of: (S11) irradiating, with laser light, at least part of a specific region (12a) of the surface of the first member (11), so that a base of the thin film (12) is exposed in the at least part of the specific region (12a); and (S12) bonding the second member (14) to the specific region (12a) by use of an adhesive (13).

COPPER PASTE FOR PRESSURELESS BONDING, BONDED BODY AND SEMICONDUCTOR DEVICE

A copper paste for pressureless bonding is a copper paste for pressureless bonding, containing: metal particles; and a dispersion medium, in which the metal particles include sub-micro copper particles having a volume average particle diameter of greater than or equal to 0.01 μm and less than or equal to 0.8 μm, and micro copper particles having a volume average particle diameter of greater than or equal to 2.0 μm and less than or equal to 50 μm, and the dispersion medium contains a solvent having a boiling point of higher than or equal to 300° C., and a content of the solvent having a boiling point of higher than or equal to 300° C. is greater than or equal to 2 mass % on the basis of a total mass of the copper paste for pressureless bonding.

Semiconductor Device Assembly Including a Chip Carrier, Semiconductor Wafer and Method of Manufacturing a Semiconductor Device

A semiconductor device includes a chip carrier and a semiconductor die with a semiconductor portion and a conductive structure. A soldered layer mechanically and electrically connects the chip carrier and the conductive structure at a soldering side of the semiconductor die. At the soldering side an outermost surface portion along an edge of the semiconductor die has a greater distance to the chip carrier than a central surface portion. The conductive structure covers the central surface portion and at least a section of an intermediate surface portion tilted to the central surface portion. Solder material is effectively prevented from coating such semiconductor surfaces that are prone to damages and solder-induced contamination is significantly reduced.

SEMICONDUCTOR DEVICE INCLUDING A HEAT SPREADER

A semiconductor device includes a semiconductor chip including back side metal, a substrate, and an electrically conductive heat spreader directly contacting the back side metal. The semiconductor chip includes a sintered joint directly contacting the heat spreader and electrically coupling the heat spreader to the substrate.

Electronic device, and manufacturing method of electronic device

An electronic device includes a drive substrate (a pressure chamber substrate and a vibration plate) including a piezoelectric element and electrode wirings related to driving of the piezoelectric element formed thereon, and a sealing plate bonded thereto, the electrode wirings are made of wiring metal containing gold (Au) on the drive substrate through an adhesion layer which is a base layer, and has a removed portion in which a portion of the wiring metal in a region containing a part bonded to a bonding resin is removed and the adhesion layer is exposed.

Semiconductor device

A semiconductor device has a semiconductor element provided with a functional surface on which a functional circuit is formed and with a back surface facing in the opposite direction to the functional surface, while also having a lead supporting the semiconductor element and electrically connected to the semiconductor element, and a resin package covering at least a portion of the semiconductor element and the lead. The semiconductor element has a functional surface side electrode formed on the functional surface and equipped with a functional surface side raised part that projects in the direction in which the functional surface faces. The functional surface side raised part of the functional surface side electrode is joined to the lead by solid state bonding.

Method for preventing die pad delamination

The invention is directed to a method for inhibiting or preventing delamination at the interface of the die attach/mold compound and the die pad of a semiconductor device and a semiconductor device formed by such method. The method includes providing a leadframe having a top surface; coating the top surface of the leadframe with first and second silane coating; heating the silane coatings to form a porous layer having a porosity of at least 10%; applying a die to the porous layer; securing the die to the porous layer by a die attaching compound; and after the curing of die attach material and wire bonding, a mold compound is applied through molding.

LID BODY, ELECTRONIC COMPONENT ACCOMMODATION PACKAGE, AND ELECTRONIC DEVICE

A lid body includes a base containing an alloy of iron and nickel, a first film positioned on a lower surface of the base and containing nickel, and a second film positioned on a lower surface of the first film and containing copper. During welding of the lid body, penetration of crystal grain boundaries of the base by Cu of the second film is reduced by the first film. Therefore, occurrence of cracks in the base is reduced and thus a package with high airtightness can be formed.

Metallmatrix-verbundmaterial, Verfahren zu seiner Herstellung und seine Verwendung

VERFAHREN ZUM VERLÖTEN EINES SCHALTUNGSTRÄGERS MIT EINER TRÄGERPLATTE

Ein Aspekt der Erfindung betrifft ein Verfahren zum Verlöten eines Schaltungsträgers (2) mit einer Trägerplatte (3). Hierzu werden eine Trägerplatte (3), ein Schaltungsträger (2) und ein Lot (5) bereitgestellt. Die Trägerplatte (3) weist eine Oberseite (2t) auf, sowie eine erste Justiereinrichtung (41). Der Schaltungsträger (2) weist eine Unterseite (2b) auf, sowie eine zweite Justiereinrichtung (42). Der Schaltungsträger (2) wird so auf die Trägerplatte (3) aufgelegt, dass die Unterseite (2b) des Schaltungsträgers (2) der Oberseite (3t) der Trägerplatte (3) zugewandt ist, das Lot (5) zwischen der Trägerplatte (3) und dem Schaltungsträger (2) angeordnet ist, und die erste Justiereinrichtung (41) für die zweite Justiereinrichtung (42) einen Anschlag bildet, der eine Verschiebung des auf die Trägerplatte (3) aufgelegten Schaltungsträgers (2) entlang der Oberseite der Trägerplatte (3) begrenzt. Danach wird das Lot (5) aufgeschmolzen und nachfolgend abgekühlt, bis es erstarrt und den Schaltungsträger ...

Semiconductor device and manufacturing method for the semiconductor device

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SEMICONDUCTOR DEVICE A semiconductor device (2) comprising: a first semiconductor element (3); and a second semiconductor element (5) electrically connected to the first semiconductor element (3) by a first conductive member (10) and a second conductive member (29), wherein a first electrode (3a) is arranged on a surface of the first semiconductor element (3), a second electrode (5b) is arranged on a surface of the second semiconductor element (5), the first conductive member (10) has a first stack part (12) stacked to the first semiconductor element (3) to face the first electrode (3a), and a first copper joint part (13) extending from the first stack part (12), the second conductive member (29) has a second stack part (25) stacked to the second semiconductor element (5) to face the second electrode (5b), and a second copper joint part (26), the second copper joint part (26) extending from the second stack part (25) and facing the first ...

Module including a sintered joint

METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING GANG BONDING AND SEMICONDUCTOR DEVICE FABRICATED BY THE SAME

집단 본딩을 이용한 반도체 디바이스 제조 방법 및 반도체 디바이스가 개시된다. 본 발명의 일 태양에 따른 반도체 디바이스 제조 방법은, 정렬된 복수의 반도체 적층 구조체를 갖는 지지기판을 준비하는 것을 포함한다. 각 반도체 적층 구조체는 제1 도전형 반도체층, 제2 도전형 반도체층, 및 제1 도전형 반도체층과 제2 도전형 반도체층 사이에 개재된 활성 영역을 포함한다. 한편, 복수의 반도체 적층 구조체에 대응하도록 정렬된 제1 리드 전극들 및 제2 리드 전극들을 갖는 멤버가 준비된다. 그 후, 지지기판 상에서 상기 복수의 반도체 적층 구조체를 유지하면서, 복수의 반도체 적층 구조체가 멤버에 본딩된다. 복수의 반도체 적층 구조체가 본딩된 후, 멤버가 분할된다. 이에 따라, 칩 본딩 공정을 단순화할 수 있으며 작업시간을 크게 줄일 수 있다. Disclosed are a semiconductor device manufacturing method and a semiconductor device using collective bonding. A semiconductor device manufacturing method according to one aspect of the present invention includes preparing a support substrate having a plurality of aligned semiconductor laminate structures. Each semiconductor stacked structure includes a first conductive semiconductor layer, a second conductive semiconductor layer, and an active region interposed between the first conductive semiconductor layer and the second conductive semiconductor layer. Meanwhile, a member having first lead electrodes and second lead electrodes aligned to correspond to the plurality of semiconductor stacked structures is prepared. Thereafter, the plurality of semiconductor laminates are bonded to the members while maintaining the plurality of semiconductor laminates on the support substrate. After the plurality of semiconductor laminates are bonded, the members are divided. Accordingly, the chip bonding process can be simplified and the working time can be greatly reduced.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

METHOD FOR SOLDERING SURFACE-MOUNT COMPONENT AND SURFACE-MOUNT COMPONENT

HIGH TEMPERATURE, STABLE SiC DEVICE INTERCONNECTS AND PACKAGES HAVING LOW THERMAL RESISTANCE

A method of forming packages containing SiC or other semiconductor devices bonded to other components or conductive surfaces utilizing transient liquid phase (TLP) bonding to create high temperature melting point bonds using in situ formed ternary or quaternary mixtures of conductive metals and the devices created using TLP bonds of ternary or quaternary materials. The compositions meet the conflicting requirements of an interconnect or joint that can be exposed to high temperature, and is thermally and electrically conductive, void and creep resistant, corrosion resistant, and reliable upon temperature and power cycling.

METHOD FOR MANUFACTURING ELECTRONIC DEVICE BY USING FLIP-CHIP BONDING

An electronic device is manufactured by providing a substrate on which a pad including an organic solderability preservative (OSP) film is formed, mounting a die on the substrate such that the die is electrically connected to the pad, performing a molding process on the die mounted on the substrate, and thereafter, forming an oxide film on the substrate by using an oxidation process on the substrate.

Semiconductor device and manufacturing method for the semiconductor device

A semiconductor device includes first and second semiconductor elements and first and second conductive members. A first electrode on the first semiconductor element is bonded to a first stack part of the first conductive member by a first bonding layer. A second electrode on the second semiconductor element is bonded to a second stack part of the second conductive member by a second bonding layer. A first joint part of the first conductive member is bonded to a second joint part of the second conductive member by an intermediate bonding layer. A first surface of the first joint part facing the second joint part, a side surface of the first joint part continuous from the first surface, a second surface of the second joint part facing the first joint part, and a side surface of the second joint part continuous from the second surface are covered by nickel layers.

Circuit package, an electronic circuit package, and methods for encapsulating an electronic circuit

A circuit package is provided, the circuit package including: an electronic circuit; a metal block next to the electronic circuit; encapsulation material between the electronic circuit and the metal block; a first metal layer structure electrically contacted to at least one first contact on a first side of the electronic circuit; a second metal layer structure electrically contacted to at least one second contact on a second side of the electronic circuit, wherein the second side is opposite to the first side; wherein the metal block is electrically contacted to the first metal layer structure and to the second metal layer structure by means of an electrically conductive medium; and wherein the electrically conductive medium includes a material different from the material of the first and second metal layer structures or has a material structure different from the material of the first and second metal layer structures.

AU-BASED SOLDER DIE ATTACHMENT SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor device according to the present invention, having an Au-based solder layer (3) sandwiched between a semiconductor element (1) and a Cu substrate (2) made mainly of Cu, in which the semiconductor device includes: a dense metal film (23) which is arranged between the Cu substrate (2) and the Au-based solder layer (3), and has fine slits (24) patterned to have a predetermined shape in a plan view; and fine structures (4) with dumbbell-like cross section, which have Cu and Au as main elements, and are each buried in the Cu substrate (2), the Au-based solder layer (3), and the fine slits (24) of the dense metal film (23).

Electronic assemblies having a mesh bond material and methods of forming thereof

Embodiments of the present disclosure include a method of forming an electronic assembly with a mesh bond layer. The method may include forming a mesh bond material comprising a first surface spaced apart from a second surface by a thickness of the mesh bond material and one or more openings extending from the first surface through the thickness of the mesh bond material to the second surface. The method may further include adjusting at least one of: the thickness of the mesh bond material, a geometry of the one or more openings, or a size of the one or more openings of the mesh bond material, where the adjusting modifies a Young's modulus of the mesh bond material, and bonding the first surface of the mesh bond material to a surface of a semiconductor device.

Strain-tolerant die attach with improved thermal conductivity, and method of fabrication

A mechanically-stable and thermally-conductive interface device between a semiconductor die and a package for the die, and related method of fabrication, comprising: a semiconductor die; a package for the die; a surface area-enhancing pattern on the package and/or the die; and die attach materials between the die and the package, the die attach materials attaching the die to the package through an interface provided by the die attach materials; wherein: an effective bonding area between the die attach materials and the package and/or the die is greater with the pattern than without the pattern; and the increase of the effective bonding area simultaneously increases the surface area for thermal transport between the package and/or the die, and the die attach materials; and increases the surface area for stably attaching the at least one of the package and the die to the die attach materials.

Solder material and electronic part using the same

This invention provides a lead-free high temperature solder material comprising 0.005-3.0 wt % of palladium (Pd) and 97.0-99.995 wt % of tin (Sn) whose liquidus temperature is 200-350° C. The solder material is environmentally-friendly, improved in thermal fatigue property, and it can improve the reliability of electronic apparatuses. A predetermined amount of Sn material and Pd is mixed, vacuum-melted and cast to prepare an ingot. The ingot is rolled to be a tape that is later pressed to obtain a solder pellet. In a preferable composition, at least 95 wt % of Sn and 0.005-3.0 wt 5 of Pd are contained, and 0.1-5.0 wt % of metallic (e.g. Cu, Ni) or alloy particles are added. The average particle diameter is about 40 mum. A substrate and an IC chip (electronic element) are die-bonded substantially in parallel by a solder material provided between an Ni plating on the lower side of an IC chip (semiconductor) and an Ni plating on a die.

SEMICONDUCTOR ELEMENT BONDING SUBSTRATE, SEMICONDUCTOR DEVICE, AND POWER CONVERSION DEVICE

A semiconductor element bonding substrate according to the present invention includes an insulating plate, and a metal pattern bonded to a main surface of the insulating plate. A main surface of the metal pattern on an opposite side of the insulating plate includes a bonding region to which a semiconductor element is bonded by a solder. The metal pattern includes at least one concave part located in the main surface. The at least one concave part is located closer to an edge of the bonding region in relation to a center part of the bonding region in the bonding region.

METHOD OF FORMING A CHIP ASSEMBLY AND CHIP ASSEMBLY

A method of forming a chip assembly may include forming a plurality of cavities in a carrier; The method may further include arranging a die attach liquid in each of the cavities; arranging a plurality of chips on the die attach liquid, each chip comprising a rear side metallization and a rear side interconnect material disposed over the rear side metallization, wherein the rear side interconnect material faces the carrier; evaporating the die attach liquid; and after the evaporating the die attach liquid, fixing the plurality of chips to the carrier. 1. A chip assembly , comprising:a carrier with a top side comprising a cavity formed in the top side of the carrier, the cavity configured to receive a chip;a chip, arranged in the cavity, and comprising a chip contact fixed to the bottom of the cavity; andan interconnect material, between the chip contact and the bottom of the cavity;wherein the top side of the carrier outside the cavity is not flush with the chip; andwherein the chip is diffusion-soldered to the bottom of the cavity.2. The chip assembly of claim 1 ,wherein side walls of the cavity are inclined away from the cavity in a direction from a bottom of the cavity to a top of the cavity.3. The chip assembly of claim 1 ,wherein the cavity is formed with a channel at a bottom of the cavity.4. The chip assembly of claim 1 ,the chip has a thickness that is smaller than a depth of the cavity.5. The chip assembly of claim 1 ,wherein the chip protrudes from the cavity.6. The chip assembly of claim 1 ,wherein the cavity has a convex-shaped bottom that is configured to self-center the chip in the associated cavity.7. The chip assembly of claim 1 ,wherein the cavity has side walls that are convex that are configured to self-center the chip in the cavity.8. The chip assembly of claim 1 ,wherein the cavity has side walls that have a non-constant distance between opposite sides of the cavity along a length of a side.9. The chip assembly of claim 1 ,wherein the chip is ...

Silicon nitride circuit board

This invention provides a silicon nitride circuit board in which a metal circuit plate is bonded to a high thermal conductive silicon nitride substrate having a thermal conductivity of not less than 60 W/m K, wherein a thickness DS of the high thermal conductive silicon nitride substrate and a thickness DM of the metal circuit plate satisfy a relational formula . The silicon nitride circuit board is characterized in that, when a load acts on the central portion of the circuit board which is held at a support interval of 50 mm, a maximum deflection is not less than 0.6 mm until the silicon nitride substrate is broken. The silicon nitride circuit board is characterized in that, when an anti-breaking test is performed to the circuit board which is held at a support interval of 50 mm, an anti-breaking strength is not less than 500 MPa. The metal circuit plate or a circuit layer are integrally bonded on the silicon nitride substrate by a direct bonding method, an active metal brazing method, ...

Ａｕ系はんだダイアタッチメント半導体装置及びその製造方法

Elektronisches Bauelement und ein Verfahren zur Herstellung eines elektronischen Bauelements

Das elektronische Bauelement enthält einen Träger, ein an dem Träger angebrachtes Halbleiter-Substrat und ein zwischen dem Halbleiter-Substrat und dem Träger angeordnetes Schichtsystem. Das Schichtsystem enthält eine auf dem Halbleiter-Substrat angeordnete elektrische Kontaktschicht. Eine Funktionsschicht ist auf der elektrischen Kontaktschicht angeordnet. Eine Klebeschicht ist auf der Funktionsschicht angeordnet. Eine Lötschicht ist zwischen der Klebeschicht und dem Träger angeordnet.

Halbleitermodule mit an eine Metallfolie gebondeten Halbleiterchips

Ein Verfahren zur Herstellung von Halbleitermodulen weist folgende Schritte auf: Bereitstellen eines Metallverbundsubstrats mit einer an einer Metallschicht befestigten Metallfolie, wobei die Metallfolie dünner als die Metallschicht ist und ein anderes Material als diese umfasst, Befestigen einer ersten Fläche von mehreren Halbleiterchips an der Metallfolie vor dem Strukturieren der Metallfolie und Einschließen der an der Metallfolie befestigten Halbleiterchips in ein elektrisch isolierendes Material. Die Metallschicht und die Metallfolie werden strukturiert, nachdem die Halbleiterchips mit dem elektrisch isolierenden Material eingeschlossen wurden, so dass Oberflächengebiete des elektrisch isolierenden Materials von der Metallfolie und der Metallschicht frei sind. Das elektrisch isolierende Material wird entlang den Oberflächengebieten, die von der Metallfolie und der Metallschicht frei sind, geteilt, um einzelne Module zu bilden.

CHIPBAUGRUPPE UND VERFAHREN ZUM HERSTELLEN EINER CHIPBAUGRUPPE

Chipbaugruppe (310), aufweisend: eine erste Verkapselungsstruktur (202); eine über der ersten Verkapselungsstruktur (202) gebildete erste Passivierungsschicht (224) und eine über der ersten Passivierungsschicht (224) gebildete erste elektrisch leitende Schicht (234); mindestens einen über der ersten elektrisch leitenden Schicht (234) und der ersten Passivierungsschicht (224) angeordneten Chip (242), wobei mindestens eine Chipkontaktstelle (243) die erste elektrisch leitende Schicht (234) kontaktiert; mindestens einen in der ersten Verkapselungsstruktur (202) gebildeten Hohlraum (2112), wobei der mindestens eine Hohlraum (2112) einen Abschnitt der die mindestens eine Chipkontaktstelle (243) bedeckenden ersten Passivierungsschicht (224) exponiert; eine auf der ersten Verkapselungsstruktur (202) aufgebrachte und den mindestens einen Hohlraum (2112) bedeckende zweite Verkapselungsstruktur (2116), wobei eine Kammerzone (2118) über der mindestens einen Chipkontaktstelle (243) durch den mindestens ...

HALBLEITERVORRICHTUNGEN MIT EINER METALLSILICIDSCHICHT UND VERFAHREN ZU IHRER HERSTELLUNG

Eine Halbleitervorrichtung enthält eine Siliciumschicht, eine Metallsilicidschicht, die direkt auf der Siliciumschicht angeordnet ist, und eine Lotschicht, die direkt auf der Metallsilicidschicht angeordnet ist.

Multiple chip component with wireless packing has dies or chip elements with bumps on lower line frames, upper line frames coupled to dies, connecting rails interconnected in pairs

The component has lower line frames (11), dies or chip elements with bumps on lower line frames with source and gate solder bump arrays, upper line frames (13), each coupled to a die with bumps and containing lines and four rails interconnected in pairs with sides connected to the frames. Each lower frame has lines with drain connections coupled to dies with bumps. Each upper frame has lines coupled to gate and source connections on a die. Independent claims are also included for the following: a method of manufacturing a chip component, especially an improved method of packing several DMOS components.

Composite substrate with alternating pattern of diamond and metal or metal alloy

Semiconductor device and manufacturing method for the semiconductor device

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SEMICONDUCTOR DEVICE A semiconductor device (2) includes first and second semiconductor elements (3, 5) and first and second conductive members (10, 29). A first electrode (3a) on the first semiconductor element is bonded to a first stack part (12) of the first conductive member by a first bonding layer (8a). A second electrode (5b) on the second semiconductor element is bonded to a second stack part (25) of the second conductive member by a second bonding layer (8f). A first joint part (13) of the first conductive member is bonded to a second joint part (26) of the second conductive member by an intermediate bonding layer (8g). A first surface of the first joint part facing the second joint part, a side surface of the first joint part continuous from the first surface, a second surface of the second joint part facing the first joint part, and a side surface of the second joint part continuous from the second surface are covered by nickel ...

SEMICONDUCTOR DEVICE MANUFACTURE

PASTE AND METHOD FOR CONNECTING ELECTRONIC COMPONENTS TO A SUBSTRATE CAPABLE OF FORMING A STABLE AND STRONG COUPLING

PURPOSE: A paste is provided to form a coupling between an electronic component and substrate with high reliability at a high temperature. CONSTITUTION: A paste contains a metal particle; one or more activators with two or more carboxylic acid units; and a dispersion medium. A method for connecting an electronic device to a substrate through a contact region comprises a step of providing a substrate with a first contact region and an electronic component with a second contact region; a step of providing the paste; a step of generating a structure where the first contact region and the second contact region are contacted to each other through the paste; and a step of sintering the paste and manufacturing a module which comprises the substrate and the electronic component connected to each other through the sintered paste. COPYRIGHT KIPO 2013 ...

SOLDER ALLOY AND SEMICONDUCTOR DEVICE

SEMICONDUCTOR DEVICE AND THE MANUFACTURING METHOD THEREOF MAKING SURE THE WIRE BONDING BETWEEN THE ELECTRODE OF THE SEMICONDUCTOR DEVICE AND THE ELECTRODE ON THE SUPPORTING BODY

PURPOSE: A semiconductor device and manufacturing method thereof are provided to suppress the warpage caused by the wire bonding. CONSTITUTION: The electrode terminal(106) is arranged in the supporting body(101). The intermediate member is mounted on the supporting body. A part of the semiconductor device is supported by the intermediate member. The semiconductor device is arranged on the supporting body. The block shaped member is arranged on the supporting body or the intermediate member. The electrode terminal on the electrode terminal of the semiconductor device and the supporting body are connected to the bonding wire(109). © KIPO 2009 ...

dispositivo semicondutor e método para fabricação do dispositivo semicondutor

Substrate bonding with metal germanium silicon material

In one embodiment, a semiconductor structure including a first substrate, a semiconductor device on the first substrate, a second substrate, and a conductive bond between the first substrate and the second substrate that surrounds the semiconductor device to seal the semiconductor device between the first substrate and the second substrate. The conductive bond comprises metal, silicon, and germanium. A percentage by atomic weight of silicon in the conductive bond is greater than 5%.

Solar cell assembly ii

The present invention relates to a solar cell assembly that includes a solar cell attached to a bonding pad and a cooling substrate, wherein the bonding pad is attached to a surface of the cooling substrate by a thermally conductive adhesive and electrically contacted to the bonding pad and cooling substrate by a bonding wire. Alternatively, the bonding pad is attached to a surface of the cooling substrate by a thermally and electrically conductive adhesive.

Paste and method for connecting electronic component to substrate

A paste may be used to connect at least one electronic component to at least one substrate through contact regions, wherein at least one of the contact regions contains a non-noble metal. The paste contains (a) metal particles, (b) at least one activator that bears at least two carboxylic acid units in the molecule, and (c) a dispersion medium. A method for connecting at least one electronic component to at least one substrate through the contact regions includes steps of providing a substrate having a first contact region and an electronic component having a second contact region; providing the above paste; generating a structure, wherein the first contact region of the substrate contacts the second contact region of the electronic component through the paste; and sintering the structure while producing a module including at least the substrate and the electronic component connected to each other through the sintered paste.

Connecting material, method for manufacturing connecting material and semiconductor device

In a connecting material of the present invention, a Zn series alloy layer is formed on an outermost surface of an Al series alloy layer. In particular, in the connecting material, an Al content of the Al series alloy layer is 99 to 100 wt.% or a Zn content of the Zn series alloy layer is 90 to 100 wt.%. By using this connecting material, the formation of an Al oxide film on the surface of the connecting material at the time of the connection can be suppressed, and preferable wetness that cannot be obtained with the Zn—Al alloy can be obtained. Further, a high connection reliability can be achieved when an Al series alloy layer is left after the connection, since the soft Al thereof functions as a stress buffer material.

Electronic Device and a Method for Fabricating an Electronic Device

The electronic device includes a carrier, a semiconductor substrate attached to the carrier, and a layer system disposed between the semiconductor substrate and the carrier. The layer system includes an electrical contact layer disposed on the semiconductor substrate. A functional layer is disposed on the electrical contact layer. An adhesion layer is disposed on the functional layer. A solder layer is disposed between the adhesion layer and the carrier.

Package carrier and manufacturing method thereof

A manufacturing method of a package carrier is provided. A supporting board having an upper surface which a patterned circuit layer formed thereon is provided. A portion of the upper surface is exposed by the patterned circuit layer. An insulating layer and a conducting layer located at a first surface of the insulating layer are laminated onto the patterned circuit layer. The patterned circuit layer and the exposed portion of the upper surface are covered by the insulating layer. Plural conductive connection structures are formed on the patterned circuit layer. Plural of pads respectively connecting the conductive connection structures and exposing a portion of the first surface of the insulating layer is defined by patterning the conductive layer. The supporting board is removed so as to expose a second surface of the insulating layer. The second surface and a bonding surface of the patterned circuit layer are coplanar.

Circuit package, an electronic circuit package, and methods for encapsulating an electronic circuit

A circuit package is provided, the circuit package including: an electronic circuit; a metal block next to the electronic circuit; encapsulation material between the electronic circuit and the metal block; a first metal layer structure electrically contacted to at least one first contact on a first side of the electronic circuit; a second metal layer structure electrically contacted to at least one second contact on a second side of the electronic circuit, wherein the second side is opposite to the first side; wherein the metal block is electrically contacted to the first metal layer structure and to the second metal layer structure by means of an electrically conductive medium; and wherein the electrically conductive medium includes a material different from the material of the first and second metal layer structures or has a material structure different from the material of the first and second metal layer structures.

Semiconductor device, and method of manufacturing semiconductor device

A semiconductor device which can reduce a heat stress to a solder layer while suppressing an increase of thermal resistance is provided. A semiconductor device includes a semiconductor element, a solder layer which is arranged on at least one surface of the semiconductor element and a lead frame which is arranged on the solder layer so that a porous nickel plating part is sandwiched between the lead frame and the solder layer. Compared with a case that the semiconductor element and the lead frame are jointed by a solder directly, an increased part of a thermal resistance of the solder junction is held down only to a part of the porous nickel plating part and a thermal resistance applied to the solder layer can be reduced.

Method for Producing Electronic Device With Multi-Layer Contact

A method for producing an electric device with a multi-layer contact is disclosed. In an embodiment, a method includes providing a carrier, the carrier having a metallic layer disposed on its surface, providing a semiconductor substrate, forming a layer stack on the semiconductor substrate and attaching the layer stack of the semiconductor substrate to the metallic layer of the carrier so that an intermetallic phase is formed between the metallic layer and the solder layer. 1. A method for fabricating an electronic device , the method comprising:providing a carrier, the carrier having a metallic layer disposed on its surface, wherein the metallic layer comprises Ni or NiNiP;providing a semiconductor substrate; directly depositing an electrical contact layer on the semiconductor substrate, the electrical contact layer being a single elemental Al layer;', 'directly depositing a functional layer on the electrical contact layer, the functional layer comprising Ti or an alloy containing Ti;', 'directly depositing an adhesion layer on the functional layer, the adhesion layer comprising Ni or NiV;', 'directly depositing a solder layer on the adhesion layer, the solder layer being a single element Sn layer or a noble metal free alloy layer containing Sn; and', 'directly depositing a protective layer on the solder layer, the protection layer being an Ag layer; and, 'forming a layer stack on the semiconductor substrate bybonding the layer stack of the semiconductor substrate to the metallic layer of the carrier so that an intermetallic phase is formed between the metallic layer and the solder layer, the intermetallic phase comprising a binary alloy of Ni/Sn.2. The method according to claim 1 , wherein the electrical contact layer has a thickness in a range from 100 nm to 1 μm.3.The method according to claim 2 , wherein the functional layer has a thickness in a range from 50 nm to 200 nm.4382. The method according to claim claim 2 , wherein the solder layer has a thickness in ...

DIE BONDING TO A BOARD

An apparatus for bonding die to a board includes a circuit board having a solderable layer and a plurality of die bonded to the circuit board using at least three respective layers. Each of the at least three respective layers includes an inner layer, a first alloy of material from an outer layer and the solderable layer of the circuit board, and a second alloy of material from the outer layer and the solderable layer of the circuit board. Melting temperatures of the first alloy and the second alloy are higher than reflow temperatures of the outer layer and the solderable layer of the circuit board. 1. An apparatus , comprising:a first solderable layer on a surface of a ceramic or substrate board or a metal lead frame; a first solderable die surface on a first die comprising a first plurality of metal layers wherein an outer layer comprises a silver and tin first alloy having a silver composition that is less than 7 percent by weight and wherein an inner layer next to the outer layer comprises one of titanium, nickel or silver; and', 'a second alloy having a subsequent melting temperature that is higher than a first reflow temperature required to adhere the first die to the first solderable layer of the board, wherein the second alloy bonds the first alloy to the first solderable layer of the surface of the board to hold the first die to the board, and, 'first circuitry comprising 'a second solderable die surface on a second die comprising a third alloy,', 'second circuitry comprisingwherein the first and second circuitry are configured to control operations of the apparatus.2. The apparatus of claim 1 , wherein the second alloy has a melting temperature that will not completely melt during subsequent reflow process at the first reflow temperature used to add the second circuitry.3. The apparatus of claim 1 , wherein the first solderable layer of the ceramic or substrate board or metal lead frame comprises at least one of copper claim 1 , silver and tin.4. The ...

Electronic Device with Multi-Layer Contact

An electric device with a multi-layer contact is disclosed. In an embodiment, the electronic device includes a carrier, a semiconductor substrate attached to the carrier, and a layer system disposed between the semiconductor substrate and the carrier. The layer system includes an electrical contact layer disposed on the semiconductor substrate. A functional layer is disposed on the electrical contact layer. An adhesion layer is disposed on the functional layer. A solder layer is disposed between the adhesion layer and the carrier.

Semiconductor device

A semiconductor device includes a semiconductor element having a rectangular shape in a plan view, and a fixed member to which the semiconductor element is fixed. The semiconductor element is disposed so that a rectangular face of the semiconductor element is faced toward a surface of the fixed member. A part of the rectangular face of the semiconductor element is fixed to the surface of the fixed member. At least corner parts of the rectangular face of the semiconductor element are not fixed to the surface of the fixed member.

Strong, heat stable junction

Provided among other things is an electrical device comprising: a first component that is a semiconductor or an electrical conductor; a second component that is an electrical conductor; and a strong, heat stable junction there between including an intermetallic bond formed of: substantially (a) indium (In), tin (Sn) or a mixture thereof, and (b) substantially nickel (Ni). The junction can have an electrical contact resistance that is small compared to the resistance of the electrical device.

INTERCONNECT STRUCTURE WITH REDUNDANT ELECTRICAL CONNECTORS AND ASSOCIATED SYSTEMS AND METHODS

Semiconductor die assemblies having interconnect structures with redundant electrical connectors are disclosed herein. In one embodiment, a semiconductor die assembly includes a first semiconductor die, a second semiconductor die, and an interconnect structure between the first and the second semiconductor dies. The interconnect structure includes a first conductive film coupled to the first semiconductor die and a second conductive film coupled to the second semiconductor die. The interconnect structure further includes a plurality of redundant electrical connectors extending between the first and second conductive films and electrically coupled to one another via the first conductive film. 1. A semiconductor device , comprising:a semiconductor substrate;a dielectric material over the substrate;a conductive trace extending at least partially through the dielectric material; and a conductive member coupled to the conductive trace, and', 'a conductive bond material bonded to the conductive member,, 'a plurality of redundant electrical connectors extending from the conductive trace and through at least a portion of the dielectric material, wherein each of the redundant electrical connectors includes—'}wherein all of the redundant electrical connectors are coupled to the conductive trace.2. The semiconductor device of wherein the dielectric includes a plurality of openings exposing portions of the conductive trace claim 1 , wherein the redundant electrical connectors are formed in the openings.3. The semiconductor device of wherein the conductive member comprises copper and the bond material comprises a solder material.4. The semiconductor device of wherein the conductive member includes an end portion claim 1 , and wherein the conductive bond material and conductive member form a conductive joint at the end portion.5. The semiconductor device of claim 1 , further comprising a through-substrate via (TSV) extending at least partially through the substrate claim 1 , ...

Pre-Plating of Solder Layer on Solderable Elements for Diffusion Soldering

A pre-soldered circuit carrier includes a carrier having a metal die attach surface, a plated solder region on the metal die attach surface, wherein a maximum thickness of the plated solder region is at most 50 μm, the plated solder region has a lower melting point than the first bond pad, and the plated solder region forms one or more intermetallic phases with the die attach surface at a soldering temperature that is above the melting point of the plated solder region.

POWER ELECTRONICS MODULE WITH A SUPPORT WITH A PALLADIUM/OXYGEN DIFFUSION BARRIER LAYER AND A SEMICONDUCTOR ELEMENT CONNECTED THERETO BY MEANS OF SINTERING, AND METHOD FOR PRODUCING SAME

A power electronics module includes a semiconductor element and a support with a functional surface for indirectly connecting to the semiconductor element. A palladium barrier layer is formed directly or indirectly on the functional surface, and the semiconductor element is directly or indirectly connected to the barrier layer face facing away from the functional surface by a layer of sintering silver paste. A silver layer is can be formed on the barrier layer, and a nickel layer can be formed between the functional surface and the barrier layer. 1. A power electronics module comprising:a semiconductor element;s support comprising a functional surface for indirect connection to the semiconductor element;a barrier layer comprising palladium; anda second layer comprising a silver sintering paste;wherein the barrier layer being formed on the functional surface directly or indirectly at least in sections of the functional surface;wherein the semiconductor element is connected by the second layer directly or indirectly to a first side of the harder layer, the first side facing away from the functional surface.2. The power electronics module as claimed in claim 1 , wherein the barrier layer comprises a layer thickness of 0.1 μm-1.0 μm claim 1 , 0.3 μm-0.7 μm claim 1 , or 0.4 μm-0.6 μm.3. The power electronics module as claimed in claim 1 ,further comprising a third layer consisting of silver,wherein the third layer is electrolytically applied at least in sections between the barrier layer and the second layer.4. The power electronics module as claimed in claim 3 , wherein the third layer comprises a layer thickness of 0.1 μm-5.0 μm or 0.5 μm-2.0 μm.5. The power electronics module as claimed in claim 1 , further comprising a nickel layer is formed at least in sections between the functional surface and the barrier layer.6. The power electronics module as claimed in claim 5 , the nickel layer comprises a layer thickness of 0.025 μm-3.0 μm or 0.1 μm-2.0 μm.7. The power ...

Semiconductor device

A semiconductor device according to an embodiment includes a base frame, a semiconductor element provided on the base frame, a connector provided on the semiconductor element, the connector having an upper surface, a side surface, and a porous body having a plurality of pores provided on at least the side surface, and a molded resin provided in a periphery of the semiconductor element and at least the side surface of the connector. The upper surface of the connector is exposed.

Semiconductor device and manufacturing method thereof

A semiconductor device according to an embodiment includes a lead frame, a semiconductor chip provided above the lead frame, and a bonding material including a sintered material containing a predetermined metal material and a predetermined resin, where the bonding material includes a first portion provided between the lead frame and the semiconductor chip, and a second portion provided on the lead frame around the semiconductor chip, where the bonding material bonds the lead frame and the semiconductor chip, wherein an angle formed by a lower face of the semiconductor chip and an upper face of the second portion adjacent to the lower face is 80 degrees or less.

Method of forming a chip assembly and chip assembly

A method of forming a chip assembly may include forming a plurality of cavities in a carrier; The method may further include arranging a die attach liquid in each of the cavities; arranging a plurality of chips on the die attach liquid, each chip comprising a rear side metallization and a rear side interconnect material disposed over the rear side metallization, wherein the rear side interconnect material faces the carrier; evaporating the die attach liquid; and after the evaporating the die attach liquid, fixing the plurality of chips to the carrier.

Electronic Device with Multi-Layer Contact and System

An electronic device with a multi-layer contact and a system is disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate having a first electrode terminal located on a first surface and a second surface electrode terminal located on a second surface, the first surface being opposite to the second surface, an electrical contact layer disposed directly on the first electrode terminal, a functional layer directly disposed on the electrical contact layer, an adhesion layer directly disposed on the functional layer, a solder layer directly disposed on the adhesion layer; and a protection layer directly disposed on the solder layer, wherein the semiconductor device is a power semiconductor device configured to provide a vertical current flow. 1. A semiconductor device comprising:a semiconductor substrate having a first electrode terminal located on a first surface and a second surface electrode terminal located on a second surface, the first surface being opposite to the second surface;an electrical contact layer disposed directly on the first electrode terminal, the electrical contact layer consisting essentially of Al;a functional layer directly disposed on the electrical contact layer, the functional layer consisting essentially of Ti or an alloy containing Ti;an adhesion layer directly disposed on the functional layer, the adhesion layer consisting essentially of Ni or NiV;a solder layer directly disposed on the adhesion layer, the solder layer consisting essentially of Sn; anda protection layer directly disposed on the solder layer,wherein the semiconductor device is a power semiconductor device configured to provide a vertical current flow.2. The device according to claim 1 , wherein the electrical contact layer has a thickness in a range from 100 nm to 1 μm claim 1 , wherein the functional layer has a thickness in a range from 50 nm to 200 nm claim 1 , wherein the adhesion layer has a thickness in a range from 200 nm to 2 μm claim 1 , ...

SEMICONDUCTOR DEVICE

A semiconductor device, having a substrate including an insulating plate and a circuit board provided on a front surface of the insulating plate. The circuit board has a first disposition area and a second disposition area with a gap therebetween, and a groove portion, of which a longitudinal direction is parallel to the gap, formed in the gap. The semiconductor device further includes a first semiconductor chip and a second semiconductor chip located on the circuit board in the first disposition area and the second disposition area, respectively, and a blocking member located in the gap across the groove portion in parallel to the longitudinal direction in a plan view of the semiconductor device. 1. A semiconductor device , comprising: an insulating plate having a front surface, and', a first disposition area and a second disposition area with a gap therebetween, and', 'a groove portion, of which a longitudinal direction is parallel to the gap, formed in the gap;, 'a circuit board provided on the front surface of the insulating plate, the circuit board having'}], 'a substrate including'}a first semiconductor chip located on the circuit board in the first disposition area;a second semiconductor chip located on the circuit board in the second disposition area; anda blocking member located in the gap across the groove portion in parallel to the longitudinal direction in a plan view of the semiconductor device.2. The semiconductor device according to claim 1 , wherein the blocking member is of a linear shape.3. The semiconductor device according to claim 2 , wherein the blocking member is longer than the groove portion in the longitudinal direction.4. The semiconductor device according to claim 3 , wherein a width of the blocking member is narrower than a width of the groove portion.5. The semiconductor device according to claim 2 , wherein the blocking member is made of a metal.6. The semiconductor device according to claim 2 , wherein the blocking member is bonded to ...

Electronic part mounting substrate and method for producing same

An electronic part mounting substrate includes: a metal plate 10 (for mounting thereon electronic parts) of aluminum or an aluminum alloy having a substantially rectangular planar shape, one major surface of the metal plate 10 being surface-processed so as to have a surface roughness of not less than 0.2 micrometers; a plating film 20 of nickel or a nickel alloy formed on the one major surface of the metal plate 10; an electronic part 14 bonded to the plating film 20 by a silver bonding layer 12 (containing a sintered body of silver); a ceramic substrate having a substantially rectangular planar shape, one major surface of the ceramic substrate 16 being bonded to the other major surface of the metal plate 10; and a radiating metal plate (metal base plate) 18 bonded to the other major surface of the ceramic substrate 16.

Micro-transfer printing with volatile adhesive layer

A method of making a micro-transfer printed structure includes providing a destination substrate and a source substrate having one or more micro-transfer printable components. A layer of volatile adhesive is formed over the destination substrate and one or more components are micro-transfer printed from the source substrate onto the volatile adhesive layer at a non-evaporable temperature of the volatile adhesive layer. The volatile adhesive layer is then heated to an evaporation temperature to evaporate at least a portion of the volatile adhesive after micro-transfer printing. In certain embodiments, a micro-transfer printed structure includes a destination substrate having one or more metal contacts and one or more micro-transfer printable components having one or more component contacts disposed on the destination substrate with the metal contact aligned with the component contact. The metal contact can form an intermetallic bond with the component contact.

Bonding method, method for manufacturing structure, and structure

The present invention provides a bonding method (S 1 ) which is capable of achieving a high adhesive force without carrying out any special treatment on the second member ( 14 ), even in a case where the first member ( 11 ) has a surface on which a gold thin film ( 12 ) is formed. The first member ( 11 ) is made of a material other than gold and has a surface on which the gold thin film ( 12 ) is formed. The bonding method (S 1 ) includes the steps of: (S 11 ) irradiating, with laser light, at least part of a specific region ( 12 a ) of the surface of the first member ( 11 ), so that a base of the thin film ( 12 ) is exposed in the at least part of the specific region ( 12 a ); and (S 12 ) bonding the second member ( 14 ) to the specific region ( 12 a ) by use of an adhesive ( 13 ).

Solder alloy and junction structure using same

A solder alloy, includes: about 3 wt % to about 15 wt % of Sb; about 0.01 wt % to about 1.5 wt % of Te; and about 0.005 wt % to about 1 wt % of at least one element selected from the group consisting of Zn, Co, and Cr; and a balance of Sn.

Conductive Paste For Bonding

The present invention relates to a conductive paste for bonding that comprises a metal powder and a solvent, wherein the metal powder comprises a first metal powder having a particle diameter (D50) of 10 to 150 nm and a second metal powder having a particle diameter (D50) of 151 to 500 nm. The paste is useful for manufacturing an electronic device comprising a substrate with an electrically conductive layer and an electrical or electronic component, which are reliably bonded together using the paste. 1. A conductive paste for bonding comprising a metal powder and a solvent , wherein the metal powder comprises a first metal powder and a second metal powder , wherein the particle diameter (D50) of the first metal powder is 10 to 150 nm , and the particle diameter (D50) of the second metal powder is 151 to 500 nm.2. The conductive paste of claim 1 , wherein the total content of the first metal powder and the second metal powder is 80 to 95 weight % (wt. %) claim 1 , and the solvent is 5 to 20 wt. % claim 1 , wherein the weight % is based on the total weight of the conductive paste.3. The conductive paste of claim 1 , wherein each of the first metal powder and the second metal powder is selected from the group consisting of silver claim 1 , copper claim 1 , gold claim 1 , palladium claim 1 , platinum claim 1 , rhodium claim 1 , nickel claim 1 , aluminum claim 1 , an alloy thereof and a combination thereof.4. The conductive paste of claim 1 , wherein the mixing weight ratio of the first metal powder and the second metal powder (first metal powder:second metal powder) is 1:10 to 30:10.5. The conductive paste of claim 1 , wherein the conductive paste further comprises 0.05 to 5 wt. % of a polymer claim 1 , wherein the weight % is based on the total weight of the conductive paste.6. The conductive paste of claim 1 , wherein the particle diameter of the second metal powder is at least 50 nm larger than the particle diameter of the first metal powder.7. The conductive paste ...

Power module substrate, power module substrate with heat sink, power module, and method of manufacturing power module substrate

A power module substrate includes an insulating substrate, and a circuit layer that is formed on one surface of the insulating substrate. The circuit layer is formed by bonding a first copper plate onto one surface of the insulating substrate. Prior to bonding, the first copper plate has a composition containing at least either a total of 1 to 100 mol ppm of one or more kinds among an alkaline-earth element, a transition metal element, and a rare-earth element, or 100 to 1000 mol ppm of boron, the remainder being copper and unavoidable impurities.

SEMICONDUCTOR DEVICE INCLUDING A SOLDER COMPOUND CONTAINING A COMPOUND SN/SB

A semiconductor device and method is disclosed. In one embodiment, the semiconductor device comprises a semiconductor die comprising a first surface and a second surface opposite to the first surface, a first metallization layer disposed on the first surface of the semiconductor die, a first solder layer disposed on the first metallization layer, wherein the first solder layer contains the compound Sn/Sb, and a first contact member comprising a Cu-based base body and a Ni-based layer disposed on a main surface of the Cu-based base body, wherein the first contact member is connected with the Ni-based layer to the first solder layer. 1. A semiconductor device , comprising:a semiconductor die comprising a first surface and a second surface opposite to the first surface;a first metallization layer disposed on the first surface of the semiconductor die;a first solder layer disposed on the first metallization layer, wherein the first solder layer contains the compound Sn/Sb; anda first contact member comprising a Cu-based base body and a Ni-based layer disposed on a main surface of the Cu-based base body;wherein the first contact member is connected with the Ni-based layer to the first solder layer.2. The semiconductor device according to claim 1 , whereinthe solder layer further comprises an Ni/Sb phase.3. The semiconductor device according to claim 1 , whereinthe compound Sn/Sb of the solder layer is Pb free.4. The semiconductor device according to claim 1 , whereinthe material composition of the compound Sn/Sb is such that the ratio of Sb in the compound is in a range from 17% to 90%.5. The semiconductor device according to claim 4 , whereinbesides the ratio of Sb, the material composition is comprised of Sn or Sn with other materials, wherein Sn is predominant.6. The semiconductor device according to claim 5 , whereinthe other materials comprise one or more Ag, Au, Pt, Cu, Ni, and Pd.7. The semiconductor device according to claim 1 , whereinthe material composition of ...

Gallium arsenide devices with copper backside for direct die solder attach

Systems, apparatuses, and methods related to the design, fabrication, and manufacture of gallium arsenide (GaAs) integrated circuits are disclosed. Copper can be used as the contact material for a GaAs integrated circuit. Metallization of the wafer and through-wafer vias can be achieved through copper plating processes disclosed herein. Direct die solder (DDS) attach can be achieved by use of electroless nickel plating of the copper contact layer followed by a palladium flash. GaAs integrated circuits can be singulated, packaged, and incorporated into various electronic devices.

Nano copper paste and film for sintered die attach and similar applications

A sintering powder comprising copper particles, wherein: the particles are at least partially coated with a capping agent, and the particles exhibit a D10 of greater than or equal to 100 nm and a D90 of less than or equal to 2000 nm.

METHOD AND APPARATUS FOR CREATING A BOND BETWEEN OBJECTS BASED ON FORMATION OF INTER-DIFFUSION LAYERS

The present disclosure provides a method of creating a bond between a first object and a second object. For example, at least one insert may be provided at a location in a space formed between the first object and the second object. In additional, a filler material may be provided proximal to the location. An inter-diffusion layer may be formed, wherein a first portion of the inter-diffusion layer is formed by diffusion between the filler material and the at least one insert, wherein a second portion of the inter-diffusion layer is formed between the filler material and the first object, wherein a third portion of the inter-diffusion layer is formed between the filler material and the second object, wherein the first portion is coadunate with each of the second portion and third portion. 1. An electronic module comprising:a substrate;at least one chip; a first set of inserts placed inside a space between the substrate and the at least one chip,', "wherein diffusion of the second set of inserts occurs into at least one of the following: the substrate's mating surface, the at least one chip's mating surface and the first set of inserts;", 'a second set of inserts placed inside a space formed by the substrate, the at least one chip and the first set of inserts,'}], 'a plurality of inserts comprisinga gap between the first set of the inserts and the substrate; and 'wherein the diffusion results in formation of at least one of the following: a coadunate inter-diffusion layer along at least one insert of the first set of inserts to the at least one chip and a coadunate inter-diffusion layer along at least one insert of the first set of the inserts to the substrate.', 'a gap between the first set of inserts and the at least one chip,'}21. The electronic module of lain , wherein the at least one insert of the first set of inserts is comprised in at least one of the substrate's mating surface and the chip's mating surface.3. The electronic module of claim 1 , wherein the at ...

SEMICONDUCTOR PACKAGES HAVING SEMICONDUCTOR CHIPS DISPOSED IN OPENING IN SHIELDING CORE PLATE

A semiconductor package includes a first plate having a through hole therein, at least one interconnection layer disposed on a first surface of the first plate, and at least one semiconductor chip disposed on the at least one interconnection layer in a space defined by the through hole and electrically connected to the least one interconnection layer. The package further includes a second plate disposed on the at least one semiconductor chip and a second surface of the first plate on a side of the first plate opposite the first surface, and at least one conductive pad disposed on the second surface of the first plate and electrically connected to the at least one interconnection layer. 1. A semiconductor package comprising:an interconnection layer;a semiconductor chip disposed on the interconnection layer;a first vertical interconnection structure disposed on the interconnection layer and insulated from the semiconductor chip;an insulative layer on the semiconductor chip, the insulative layer being in direct physical contact with the semiconductor chip; anda conductive layer disposed on the insulative layer and extending continuously across an entire length of the semiconductor chip.2. The semiconductor package of claim 1 , wherein the insulative layer is in direct physical contact with the conductive layer.3. The semiconductor package of claim 1 , wherein a planer extent of the conductive layer is greater than a planar extent of the semiconductor chip.4. The semiconductor package of claim 1 , wherein the insulative layer extends continuously across the entire length of the semiconductor chip.5. The semiconductor package of claim 1 , wherein the insulative layer comprises an epoxy material.6. The semiconductor package of claim 1 , wherein the semiconductor chip has bonding pads on a bottom surface thereof claim 1 , andwherein the bonding pads are electrically connected to the interconnection layer.7. The semiconductor package of claim 1 , wherein the first vertical ...

Method for connecting components by means of a metal paste

The invention relates to a method for connecting components, comprising the following steps: (1) applying a metal paste containing an organic solvent to the contact surface of a first component; (2) optionally applying the metal paste to the contact surface of a second component to be connected to the first component; (3) producing a sandwich arrangement with the two components and a layer of the metal paste in-between; (4) drying the layer of metal paste between the components; and (5) pressureless sintering of the sandwich arrangement comprising the layer of dried metal paste, the drying and the pressureless sintering being performed by irradiation with IR radiation with a peak wavelength in the wavelength range of between 750 and 1500 nm. The components can be selected from the group consisting of substrates, active components and passive components. One or both of the components can be permeable to IR radiation. Step (4) and/or step (5) can be carried out in an atmosphere containing oxygen or an oxygen-free atmosphere. In both cases, at least one of the components can have an oxidation-sensitive contact surface.

Semiconductor device

A semiconductor device includes: a first lead; a first semiconductor element mounted on the first lead; and a sealing resin that covers the first semiconductor element, wherein the first lead includes: a first die pad having a first main surface and a first back surface; a second die pad arranged side by side with the first die pad and located on a side of the first main surface with respect to the first die pad; and a connecting portion connected to the first die pad and the second die pad, wherein the second die pad has a second main surface and a second back surface, and wherein the connecting portion has a connecting portion main surface connected to the first main surface and the second main surface, and an inhibiting portion arranged on the connecting portion main surface and configured to inhibit a flow of a fluid.

Semiconductor device

A semiconductor device includes a semiconductor element and an electrically conductive member. The semiconductor element is configured to allow an electric current to flow from a first electrode to a second electrode and prevent an electric current flowing from the second electrode to the first electrode. The electrically conductive member is joined with the second electrode via a solder joint layer. Surface of the second electrode in contact with the solder joint layer mainly comprises nickel, and surface of the electrically conductive member in contact with the solder joint layer mainly comprises copper. The solder joint layer comprises first and second compound layers. The first compound layer is located at an interface with, the second electrode and comprises nickel-tin based intermetallic compound. The second compound layer is located at an interface with the electrically conductive member and comprises copper-tin based intermetallic compound.

Power semiconductor device fabrication method, power semiconductor device

A method for fabricating a power semiconductor device that comprises a base substrate with a conductive layer on a surface of the base substrate and semiconductor components mounted on the base substrate includes forming a hardened layer on the surface of the conductive layer before mounting a semiconductor component on the base substrate. The forming of the hardened layer may optionally be performed using a peening process, for example, a shot peening process, a laser peening process, or an ultrasonic peening process. The conductive layer may comprise a metal such as, for example, aluminum or copper.

Power Semiconductor Device and Method for Fabricating a Power Semiconductor Device

A SiC power semiconductor device includes: a power semiconductor die including SiC and a metallization layer, wherein the metallization layer includes a first metal; a die carrier, wherein the power semiconductor die is arranged over the die carrier such that the metallization layer faces the die carrier, the die carrier being at least partially covered by a plating that includes Ni; and a first intermetallic compound arranged between the power semiconductor die and the plating and including NiSn. 1. A SiC power semiconductor device , comprising:a power semiconductor die comprising SiC and a metallization layer, wherein the metallization layer comprises a first metal;a die carrier, wherein the power semiconductor die is arranged over the die carrier such that the metallization layer faces the die carrier, the die carrier being at least partially covered by a plating that comprises Ni; and{'sub': 3', '4, 'a first intermetallic compound arranged between the power semiconductor die and the plating and comprising NiSn.'}2. The SiC power semiconductor device of claim 1 , wherein the first metal is Ni claim 1 , Ag claim 1 , Au claim 1 , or Pt.3. The SiC power semiconductor device of claim 1 , further comprising:precipitates of a second intermetallic compound arranged within the first intermetallic compound, the second intermetallic compound comprising a different material composition than the first intermetallic compound.4. The SiC power semiconductor device of claim 3 , wherein the second intermetallic compound comprises AgSn.5. The SiC power semiconductor device of claim 3 , wherein the precipitates are essentially arranged in a plane parallel to the die carrier.6. The SiC power semiconductor device of claim 3 , wherein the precipitates are essentially arranged halfway between the metallization layer and the plating.7. The SiC power semiconductor device of claim 1 , wherein the plating comprises NiP claim 1 , or NiPd claim 1 , or NiPdAu claim 1 , or NiPdAuAg.8. The SiC ...

Solder material

A solder material having a good thermal-cycle fatigue property and wettability. The solder material contains not less than 5.0% by mass and not more than 8.0% by mass Sb, not less than 3.0% by mass and not more than 5.0% by mass Ag, and the balance of Sn and incidental impurities. Also, a semiconductor device may include a joining layer between a semiconductor element and a substrate electrode or a lead frame, the joining layer being obtained by melting this solder material.

Manufacturing method for semiconductor device

A semiconductor device manufacturing method includes a preparation step and a sinter bonding step. In the preparation step, a sinter-bonding work having a multilayer structure including a substrate, semiconductor chips, and sinter-bonding material layers is prepared. The semiconductor chips are disposed on, and will bond to, one side of the substrate. Each sinter-bonding material layer contains sinterable particles and is disposed between each semiconductor chip and the substrate. In the sinter bonding step, a cushioning sheet having a thickness of 5 to 5000 μm and a tensile elastic modulus of 2 to 150 MPa is placed on the sinter-bonding work, the resulting stack is held between a pair of pressing faces, and, in this state, the sinter-bonding work between the pressing faces undergoes a heating process while being pressurized in its lamination direction, to form a sintered layer from each sinter-bonding material layer.

Electrode connection structure and electrode connection method

An electrode connection structure includes: a first electrode of an electrical circuit; and a second electrode of the electrical circuit that is electrically connected to the first electrode. The first and second electrodes are oppositely disposed in direct or indirect contact with each other. A plated lamination is substantially uniformly formed by plating process from a surface of a contact region and opposed surfaces of the first and second electrodes. A void near the surface of the contact region is filled by formation of the plated lamination. Portions of the plated lamination formed from the opposed surfaces of the first and second electrodes in a region other than the contact region are not joined together.

Bi-BASED SOLDER ALLOY, METHOD OF BONDING ELECTRONIC COMPONENT USING THE SAME, AND ELECTRONIC COMPONENT-MOUNTED BOARD

Provided is a Bi-based solder alloy containing a specific amount of Al in Bi—Ag and having particles including a Ag—Al intermetallic compound dispersed therein, a method of bonding a Ag-plated electronic component, a bare Cu frame electronic component, an Ni-plated electronic component, or the like using the same, and an electronic component-mounted board. A Bi-based solder alloy includes Ag and Al, is substantially free of Pb, and has a Bi content of 80 mass % or more, a solidus of a melting point of 265° C. or more, and a liquidus of 390° C. or less. A content of Ag is 0.6 to 18 mass %, a content of Al is 0.1 to 3 mass %, the content of Al is 1/20 to 1/2 of the content of Ag, and particles including a Ag—Al intermetallic compound are dispersed in the solder alloy.

Electronic device and method for manufacturing same

An electronic device includes: a support member that has a metallic placement surface joined to the conductive bonding layer, and a metallic sealing surface provided on an outer side of the placement surface in an in-plane direction of the placement surface to adjoin the placement surface and to surround the placement surface; and a resin member, which is a synthetic resin molded article, joined to the sealing surface and covering the electronic component. The sealing surface includes a rough surface having a plurality of laser irradiation marks having a substantially circular shape. The rough surface includes a first region and a second region. The second region has a higher density of the laser irradiation marks in the in-plane direction than the first region.

Semiconductor device

A semiconductor device and a method of making the same. The device includes an electrically conductive heat sink having a first surface. The device also includes a semiconductor substrate. The device further includes a first contact located on a first surface of the substrate. The device also includes a second contact located on a second surface of the substrate. The first surface of the substrate is mounted on the first surface of the heat sink for electrical and thermal conduction between the heat sink and the substrate via the first contact. The second surface of the substrate is mountable on a surface of a carrier.

Semiconductor device

A semiconductor device includes: a semiconductor chip; a case having a frame portion that has an inner wall portion surrounding an housing area in which the semiconductor chip is disposed; a buffer member provided on at last part of the inner wall portion of the case on a side of the housing area; a low expansion member provided on said at least part of the inner wall portion with the buffer member interposed therebetween on the side of the housing area; and a sealing member that seals the housing area, wherein the buffer member has a smaller elastic modulus than the case and the sealing member, and wherein the low expansion member has a smaller linear expansion coefficient than the case and the sealing member.

Light emitting diode module and manufacturing method thereof

A light emitting diode module includes a first conductive device, a second conductive device, an insulating structure and a plating layer. The first conductive device includes a first metal layer and a first protecting layer covering the first metal layer. The second conductive device includes a second metal layer and a second protecting layer covering the second metal layer. The insulating structure covers around the first and the second conductive devices. The plating layer is disposed on the first and the second protecting layers in a first and a second openings of the insulating structure. The insulating structure covers portions of upper surfaces of the first and the second conductive devices. The plating layer covers remaining portions of the upper surfaces of the first and the second conductive devices. Lower surfaces of the first and the second conductive devices are located in the second opening.

Power electronics assemblies and vehicles incorporating the same

A power electronics assembly includes a semiconductor device, a metal substrate, and a cooling structure. The metal substrate includes a plurality of stress-relief features that extend at least partially through a thickness of the metal substrate. The plurality of stress-relief features are at least partially filled with a transient liquid phase (TLP) bonding material. The semiconductor device is positioned over the plurality of stress-relief features and thermally bonded to the metal substrate via TLP bonding material. Vehicles having power electronics assemblies with stress-relief through-features are also disclosed.

Bonded body, circuit board, and semiconductor device

A bonded body according to an embodiment includes a substrate, a metal member, and a bonding layer. The bonding layer is provided between the substrate and the metal member. The bonding layer includes a first particle including carbon, a first region including a metal, and a second region including titanium. The second region is provided between the first particle and the first region. A concentration of titanium in the second region is greater than a concentration of titanium in the first region.

Semiconductor device

According to one embodiment, a semiconductor device includes a first semiconductor chip, a heat dissipation member provided on one surface of the first semiconductor chip and connected to the first semiconductor chip, and a sealing resin sealing the first semiconductor chip and the heat dissipation member. The heat dissipation member includes mutually interlaced metal fibers and a thermosetting resin.

Sheet for sintering bonding and sheet for sintering bonding with base material

To provide a sheet for sintering bonding and a sheet for sintering bonding with a base material that are suited for properly supplying a material for sintering bonding to a face planned to be bonded of a bonding object. A sheet for sintering bonding 10 according to the present invention comprises an electrically conductive metal containing sinterable particle and a binder component. In the sheet for sintering bonding 10 , the shear strength at 23° C., F (MPa), measured in accordance with a SAICAS method and the minimum load, f (μN), which is reached during an unloading process in load-displacement measurement in accordance with a nanoindentation method, satisfy 0.1≤F/f≤1. A sheet body X, which is a sheet for sintering bonding with a base material according to the present invention, has a laminated structure comprising a base material B and the sheet for sintering bonding 10.

Sheet for sintering bonding, sheet for sintering bonding with base material, and semiconductor chip with layer of material for sintering bonding

A sheet for sintering bonding 10 of the present invention comprises an electrically conductive metal containing sinterable particle and a binder component, and upon subjecting the sheet to a pressurization treatment onto a silver plane of a 5 mm square Si chip under predetermined conditions, the ratio of the area of a layer of a material for sintering bonding transferred onto the silver plane to the silver plane area is 0.75 to 1. A sheet body X of the present invention has a laminated structure comprising a base material B and the sheet 10 . A semiconductor chip with a layer of a material for sintering bonding of the present invention comprises a semiconductor chip and a material layer derived from the sheet 10 on one face of the chip, and the ratio of the area of the material layer to the area of that face is 0.75 to 1.

Lead frame

A lead frame includes, as an outermost plating layer, a roughened silver plating layer having acicular projections and covering the entire surface of a lead frame substrate made of a copper-based material. The roughened silver plating layer has a crystal structure in which the crystal direction <101> occupies a largest proportion among the crystal directions <001>, <111>, and <101>. The lead frame can be manufactured with improved productivity owing to reduction in cost and operation time, and achieves remarkably high adhesion to sealing resin while keeping the total thickness of plating layers including the silver plating layer to be thin.

METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING GANG BONDING AND SEMICONDUCTOR DEVICE FABRICATED BY THE SAME

A semiconductor device including a first lead electrode and a second lead electrode; a semiconductor stack structure disposed on the member, the semiconductor stack structure including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active region interposed between the first and second conductive semiconductor layers; a first electrode electrically connected to the first conductive semiconductor layer; a second electrode electrically connected to the second conductive semiconductor layer; a plating layer configured to bond the semiconductor stack structure to the member; and a first wavelength converter that covers at least side surfaces of the semiconductor stack structure. 1a member comprising a first lead electrode and a second lead electrode;a semiconductor stack structure disposed on the member, the semiconductor stack structure comprising a first conductive semiconductor layer, a second conductive semiconductor layer, and an active region interposed between the first and second conductive semiconductor layers;a first electrode electrically connected to the first conductive semiconductor layer;a second electrode electrically connected to the second conductive semiconductor layer;a plating layer configured to bond the semiconductor stack structure to the member;spacer electrodes respectively disposed on the first and second lead electrodes; anda first wavelength converter that covers at least side surfaces of the semiconductor stack structure,wherein the first electrode comprises a first electrode pad and a first additional electrode disposed on the first electrode pad,wherein the second electrode comprises a second electrode pad and a second additional electrode disposed on the second electrode pad,wherein the plating layer comprises a first plating layer configured to bond the first additional electrode to the spacer electrode on the first lead electrode, and a second plating layer configured to bond the second ...

SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME

In a semiconductor device, a first semiconductor chip and a second semiconductor chip are disposed between a first support member and a second support member. A first underlayer bonding material is disposed between the first semiconductor chip and the first support member. A second underlayer bonding material is disposed between the second semiconductor chip and the first support member. A first upper layer bonding material is disposed between the first semiconductor chip and the second support member. A second upper layer bonding material is disposed between the second semiconductor chip and the second support member. 1. A semiconductor device comprising:a first support member;a second support member facing the first support member;a first semiconductor chip disposed between the first support member and the second support member;a second semiconductor chip disposed between the first support member and the second support member;a first underlayer bonding member disposed between the first support member and the first semiconductor chip;a second underlayer bonding member disposed between the first support member and the second semiconductor chip;a first upper layer bonding member disposed between the second support member and the first semiconductor chip; anda second upper layer bonding member disposed between the second support member and the second semiconductor chip, whereinthe first underlayer bonding member, the second underlayer bonding member, the first upper layer bonding member and the second upper layer bonding member are, respectively, provided by silver sintered bodies, andthe silver sintered bodies of the first and second underlayer bonding members have gaps between adjacent particles, and the gaps of the silver sintered bodies of the first and second underlayer bonding members are smaller in size than those of the silver sintered bodies of the first and second upper layer bonding members,the first and second underlayer bonding members are bonded with the ...

Solder alloy and bonded structure using the same

A solder alloy of the disclosure includes Sb of which a content is in a range of 3 wt % to 30 wt %, Te of which a content is in a range of 0.01 wt % to 1.5 wt %, Au of which a content is in a range of 0.005 wt % to 1 wt %, at least one of Ag and Cu, wherein a content rate of at least one of Ag and Cu in the solder alloy is in a range of 0.1 wt % to 20 wt %; and a content rate of a sum of Ag and Cu in the solder alloy is in a range of 0.1 wt % to 20 wt %; and a balance of Sn.

METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING CONDUCTIVE ADHESIVE AND SEMICONDUCTOR DEVICE FABRICATED BY THE SAME

A semiconductor device including a first lead electrode and a second lead electrode on a lead frame; a semiconductor stack structure disposed on the lead frame, the semiconductor stack structure including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active region interposed between the first and second conductive semiconductor layers; a first electrode electrically connected to the first conductive semiconductor layer; a second electrode electrically connected to the second conductive semiconductor layer; a conductive adhesive configured to bond the semiconductor stack structure to the lead frame; and a first wavelength converter that covers at least side surfaces of the semiconductor stack structure. 1. A semiconductor device , comprising:a lead frame, the lead frame comprising a housing forming a recess dimensioned to accommodate a light emitting diode (LED) and a first lead electrode and a second lead electrode disposed in the recess;the LED comprising a semiconductor stack structure disposed on the lead frame, the semiconductor stack structure comprising a first conductive semiconductor layer, a second conductive semiconductor layer, and an active region interposed between the first and second conductive semiconductor layers;a first electrode electrically connected to the first conductive semiconductor layer;a second electrode electrically connected to the second conductive semiconductor layer;a conductive adhesive configured to bond the semiconductor stack structure to the lead frame; anda first wavelength converter that covers at least side surfaces of the semiconductor stack structure,wherein the conductive adhesive comprises a first conductive adhesive configured to bond the first electrode to the first lead electrode, and a second conductive adhesive configured to bond the second electrode to second lead electrode, andwherein the first wavelength converter extends to a space between the semiconductor stack ...

Die Features for Self-Alignment During Die Bonding

A semiconductor device assembly that includes a substrate having a first side and a second side, the first side having at least one dummy pad and at least one electrical pad. The semiconductor device assembly includes a first semiconductor device having a first side and a second side and at least one electrical pillar extending from the second side. The electrical pillar is connected to the electrical pad via solder to form an electrical interconnect. The semiconductor device assembly includes at least one dummy pillar extending from the second side of the first semiconductor device and a liquid positioned between an end of the dummy pillar and the dummy pad. The surface tension of the liquid pulls the dummy pillar towards the dummy pad. The surface tension may reduce or minimize a warpage of the semiconductor device assembly and/or align the dummy pillar and the dummy pad.

Electrode connection method and electrode connection structure

Provided is an electrode connection method and the like which make it possible to connect tightly without leaving a gap, by connecting by plating while electrodes in an electrical circuit contact one another in a dot or linear pattern. Contact is made directly or indirectly in at least part of the interval between a plurality of electrically connected electrodes in an electrical circuit, and the interval between electrodes is plated and connected while a plating fluid flows around the periphery of the contact section. In addition, the contact section maintains a linear or dot pattern. Furthermore, nickel or a nickel alloy or copper or a copper alloy is used as the material for performing the plating, while the material for the surface of the electrodes to be connected is nickel or a nickel alloy, copper or a copper alloy, gold or a gold alloy, silver or a silver alloy, or palladium or a palladium alloy.

Semiconductor device

A semiconductor device has a resistance element including a metal block, a resin layer disposed on the metal block, and a resistance film disposed on the resin layer and an insulated circuit board including an insulating plate and a circuit pattern disposed on the insulating plate and having a bonding area on a front surface thereof to which a back surface of the metal block of the resistance element is bonded. The area of the circuit pattern is larger in plan view than that of a front surface of the resistance element. The metal block has a thickness greater than that of the circuit pattern in a direction orthogonal to the back surface of the metal block. As a result, the metal block properly conducts heat generated by the resistance film of the resistance element to the circuit pattern.

Semiconductor packages having semiconductor chips disposed in opening in shielding core plate

A semiconductor package includes a first plate having a through hole therein, at least one interconnection layer disposed on a first surface of the first plate, and at least one semiconductor chip disposed on the at least one interconnection layer in a space defined by the through hole and electrically connected to the least one interconnection layer. The package further includes a second plate disposed on the at least one semiconductor chip and a second surface of the first plate on a side of the first plate opposite the first surface, and at least one conductive pad disposed on the second surface of the first plate and electrically connected to the at least one interconnection layer.

Semiconductor packages having semiconductor chips disposed in opening in shielding core plate

A semiconductor package includes a first plate having a through hole therein, at least one interconnection layer disposed on a first surface of the first plate, and at least one semiconductor chip disposed on the at least one interconnection layer in a space defined by the through hole and electrically connected to the least one interconnection layer. The package further includes a second plate disposed on the at least one semiconductor chip and a second surface of the first plate on a side of the first plate opposite the first surface, and at least one conductive pad disposed on the second surface of the first plate and electrically connected to the at least one interconnection layer.

電子デバイス、および、電子デバイスの製造方法

Semiconductor package and method of fabricating the same

According to the present invention, a semiconductor package comprises: at least one first substrate (110) on which at least one first substrate terminal (111) extends; at least one second substrate (120) bonded to a top surface of the first substrate (110) by ultrasonic welding; at least one semiconductor chip (130) bonded to a top surface of the second substrate (120); a package housing (140) covering the at least one semiconductor chip (130) and an ultrasonically welded region of the second substrate (120); and a terminal (150) formed separately from the first substrate (110), and electrically connected to the at least one semiconductor chip (130) through an electrical signal line (151), in which at least one terminal (150) is exposed to the outside of the package housing (140), wherein a thickness of the terminal (150) formed inside the package housing (140) is less than or equal to a thickness of the first substrate (110), and at least one embossing groove (122) is formed on the top surface of the second substrate (120). Accordingly, the first substrate (110) and the second substrate (120), which are separated from each other, are formed of a material that can be ultrasonically welded and bonded to each other so as to reduce a weight, a size of the first substrate (110) is increased to improve a heat dissipation effect, and bonding strength with the semiconductor chip (130) is increased by the embossing groove (122).

包括散热器的半导体器件

本发明涉及包括散热器的半导体器件。半导体器件包括：包括背面金属的半导体芯片；衬底；以及直接接触背面金属的导电散热器。所述半导体芯片包括直接接触散热器且将散热器与衬底电耦合的烧结接头。

金属粒子膏糊、使用了其的固化物及半导体装置

根据本发明，可提供含有极性溶剂、和分散在上述极性溶剂中且包含第一金属的粒子的金属粒子膏糊。在上述极性溶剂中，溶解有与上述第一金属不同的第二金属。本发明还提供了使用了该金属粒子膏糊的固化物及半导体装置。

도전 재료, 접속 구조체 및 접속 구조체의 제조 방법

도전 재료가 일정 기간 방치된 경우에도, 전극 상에 도전성 입자에 있어서의 땜납을 효율적으로 배치할 수 있고, 또한 가열 시에 도전 재료의 황변을 충분히 억제할 수 있는 도전 재료를 제공한다. 본 발명에 따른 도전 재료는, 도전부의 외표면 부분에 땜납을 갖는 복수의 도전성 입자와, 경화성 화합물과, 3불화붕소 착체를 포함한다.

Electronic part mounting substrate and method for producing same

본 발명에 따르면, 실질적으로 직사각형의 평면 형상을 갖는 알루미늄 또는 알루미늄 합금의 (전자 부품을 그 상에 장착하는) 금속 판(10)으로서, 금속 판(10)의 하나의 주요 표면이 0.2 ㎛ 이상의 표면 거칠기를 갖도록 표면-가공되는, 금속 판(10)과; 금속 판(10)의 하나의 주요 표면 상에 형성되는 니켈 또는 니켈 합금의 도금 필름(20)과; (은의 소결체를 함유하는) 은 접합 층(12)에 의해 도금 필름(20)에 접합되는 전자 부품(14)과; 실질적으로 직사각형의 평면 형상을 갖는 세라믹 기판(16)으로서, 세라믹 기판(16)의 하나의 주요 표면이 금속 판(10)의 다른 주요 표면에 접합되는, 세라믹 기판(16)과; 세라믹 기판(16)의 다른 주요 표면에 접합되는 방열 금속 판(금속 기부 판)(18)을 포함하는, 전자 부품 장착 기판이 제공된다.

Electronic part mounting substrate and method for producing same

본 발명에 따르면, 실질적으로 직사각형의 평면 형상을 갖는 알루미늄 또는 알루미늄 합금의 (전자 부품을 그 상에 장착하는) 금속 판(10)으로서, 금속 판(10)의 하나의 주요 표면이 0.2 ㎛ 이상의 표면 거칠기를 갖도록 표면-가공되는, 금속 판(10)과; 금속 판(10)의 하나의 주요 표면 상에 형성되는 니켈 또는 니켈 합금의 도금 필름(20)과; (은의 소결체를 함유하는) 은 접합 층(12)에 의해 도금 필름(20)에 접합되는 전자 부품(14)과; 실질적으로 직사각형의 평면 형상을 갖는 세라믹 기판(16)으로서, 세라믹 기판(16)의 하나의 주요 표면이 금속 판(10)의 다른 주요 표면에 접합되는, 세라믹 기판(16)과; 세라믹 기판(16)의 다른 주요 표면에 접합되는 방열 금속 판(금속 기부 판)(18)을 포함하는, 전자 부품 장착 기판이 제공된다.

Sinterable bonding material and semiconductor device using the same

본 발명의 목적은 소결성이 우수한 소결성 접합재를 제공하는 것이다. 본 발명은 은 충전제 및 소결 촉진제로서 유기 염기 화합물을 포함하는 소결성 접합재에 관한 것이다. An object of the present invention is to provide a sinterable bonding material excellent in sinterability. The present invention relates to a sinterable bonding material comprising an organic basic compound as a silver filler and a sintering accelerator.

Semiconductor equipment and power conversion equipment

Junction structure and manufacturing method thereof

Pb를 포함한 땜납을 대체하여 고온 환경 하에서 고신뢰 접합을 유지할 수 있는 접합 재료로서, 접합부가 고온 환경에 견딜 수 있고, 고신뢰 접합을 유지할 수 있는 접합 구조를 제공하는 데에 있다. 본 발명은, 제1 부재(5)와 제2 부재(1)의 접합 구조에서, 땜납(3)과 글래스(4)에 의해서, 제1 부재(5)와 제2 부재(1)를 접합하고, 글래스(4)가 땜납(3)을 밀봉하고 있음으로써, 도전성을 확보함과 함께, 고온 시에 땜납 용융에 의한 유출을 억제하여, 내구성을 향상시킬 수 있다.

Semiconductor device and method of forming embedded die substrate, and system-in-package modules with the same

반도체 디바이스는 제1 기판을 가진다. 제1 반도체 부품은 제1 기판의 제1 표면 상에 배치된다. 제2 기판은 제2 기판의 제1 표면 상에 수직 상호연결 구조물을 포함한다. 제2 반도체 부품은 제2 기판의 제1 표면 상에 배치된다. 제1 반도체 부품 또는 제2 반도체 부품은 반도체 패키지이다. 제1 반도체 부품과 제2 반도체 부품은 제1 기판과 제2 기판 사이에 있도록 제1 기판은 제2 기판 위에 배치된다. 제1 인캡슐란트는 제1 기판과 제2 기판 사이에 증착된다. SiP 서브모듈은 인캡슐란트 반대편의 제1 기판 또는 제2 기판 위에 배치된다. 쉴딩층은 SiP 서브모듈 위에 형성된다. The semiconductor device has a first substrate. A first semiconductor component is disposed on a first surface of a first substrate. The second substrate includes a vertical interconnect structure on a first surface of the second substrate. A second semiconductor component is disposed on the first surface of the second substrate. The first semiconductor component or the second semiconductor component is a semiconductor package. The first substrate is disposed over the second substrate such that the first semiconductor component and the second semiconductor component are between the first substrate and the second substrate. A first encapsulant is deposited between the first and second substrates. The SiP submodule is disposed on the first or second substrate opposite the encapsulant. A shielding layer is formed over the SiP submodule.

Semiconductor device

Electrode connection method and electrode connection structure

Semiconductor device

A semiconductor device and a method of making the same. The device includes an electrically conductive heat sink having a first surface. The device also includes a semiconductor substrate. The device further includes a first contact located on a first surface of the substrate. The device also includes a second contact located on a second surface of the substrate. The first surface of the substrate is mounted on the first surface of the heat sink for electrical and thermal conduction between the heat sink and the substrate via the first contact. The second surface of the substrate is mountable on a surface of a carrier.

Manufacture of semiconductor device

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Package structure and method for forming the same

提供一种封装结构及其形成方法。所述封装结构包括第一管芯、第二管芯、中介层、底部填充层、热界面材料及粘合剂图案。所述第一管芯及所述第二管芯并排设置在所述中介层上。所述底部填充层设置在所述第一管芯与所述第二管芯之间。所述热界面材料设置在所述第一管芯、所述第二管芯及所述底部填充层上。所述粘合剂图案设置在所述底部填充层与所述热界面材料之间，以将所述底部填充层与所述热界面材料分隔开。

Semiconductor device and manufacturing method thereof

본 발명은 전극 단자가 배열 설치된 지지 기체(基體)와, 상기 지지 기체 상에 탑재된 중간 부재와, 일부가 상기 중간 부재에 의해 지지되어, 상기 지지 기체 상에 배열 설치된 반도체 소자와, 상기 반도체 소자의 전극 단자에 대응하여, 상기 지지 기체 상 또는 상기 중간 부재 상에 배열 설치된 볼록 형상 부재를 구비하고, 상기 반도체 소자의 전극 단자와 상기 지지 기체 상의 전극 단자가 본딩 와이어(bonding wire)에 의해 접속되어 이루어지는 것을 특징으로 하는 반도체 장치를 제공하는 것을 과제로 한다. 지지 기체, 중간 부재, 반도체 소자, 전극 단자

Silicon nitride circuit board

본 발명은 열전도율이 60W/m·K이상인 고열전도성 질화규소기판(2)상에 금속회로판(4)을 일체로 접합한 회로기판(1)이고, 상기 고열전도성 질화규소기판(2)의 두께를 D S , 금속회로판(4)의 두께를 D M 으로 한 때에 관계식 D S ≤2D M 을 만족하는 것을 특징으로 한다. 또한, 회로기판(1)을 50㎜이 지지간격으로 유지한 상태에서 중앙부에 하중을 부가한 때에 질화규소기판(2)이 파단(破斷)에 이르기 까지의 최대 편향량이 0.6㎜이상인 것을 특징으로 한다. 또한, 회로기판을 50㎜의 지지간격으로 유지한 상태에서 항절시험을 실시한 때에 항절강도가 500㎫ 이상인 것을 특징으로 한다. 상기 금속회로판(4)이나 회로층은 직접접합법, 활성금속법 또는 메탈라이즈법에 의해 질화규소기판(2) 상에 일체로 접합 형성된다. 상기 구성에 의한 질화규소 회로기판에 의하면, 열전도율이 높고 방열성이 우수함과 더불어, 내열사이클 특성을 큰폭으로 개선할 수 있다. The present invention is a circuit board (1) in which a metal circuit board (4) is integrally bonded to a high thermal conductivity silicon nitride substrate (2) having a thermal conductivity of 60 W / m · K or more, and the thickness of the high thermal conductivity silicon nitride substrate (2) is D S. When the thickness of the metal circuit board 4 is D M , the relation D S ≤ 2 D M is satisfied. In addition, when the load is applied to the center in a state where the circuit board 1 is held at a supporting interval of 50 mm, the maximum deflection amount until the silicon nitride substrate 2 breaks is 0.6 mm or more. . In addition, when the section test is carried out while maintaining the circuit board at a supporting interval of 50 mm, the section strength is 500 MPa or more. The metal circuit board 4 and the circuit layer are integrally formed on the silicon nitride substrate 2 by a direct bonding method, an active metal method or a metallization method. According to the silicon nitride circuit board having the above structure, the thermal conductivity is high, the heat dissipation is excellent, and the heat cycle characteristics can be greatly improved.

Batch diffusion soldering and electronic devices produced by batch diffusion soldering

A method of batch soldering includes: forming a soldered joint between a metal region of a first semiconductor die and a metal region of a substrate using a solder preform via a soldering process which does not apply pressure directly to the first semiconductor die, the solder preform having a maximum thickness of 30 μm and a lower melting point than the metal regions; setting a soldering temperature of the soldering process so that the solder preform melts and fully reacts with the metal region of the first semiconductor die and the metal region of the substrate to form one or more intermetallic phases throughout the entire soldered joint, each intermetallic phase having a melting point above the preform melting point and the soldering temperature; and soldering a second semiconductor die to the same or different metal region of the substrate, without applying pressure directly to the second semiconductor die.

Semiconductor apparatus, manufacturing method of semiconductor apparatus, and joint material

A die bonding portion is metallically bonded by well-conductive Cu metal powders with a maximum particle diameter of about 15 μm to 200 μm and adhesive layers of Ag, and minute holes are evenly dispersed in a joint layer. With this structure, the reflow resistance of about 260° C. and reliability under thermal cycle test can be ensured without using lead.

Semiconductor apparatus, manufacturing method of semiconductor apparatus, and joint material

A die bonding portion is metallically bonded by well-conductive Cu metal powders with a maximum particle diameter of about 15 μm to 200 μm and adhesive layers of Ag, and minute holes are evenly dispersed in a joint layer. With this structure, the reflow resistance of about 260° C. and reliability under thermal cycle test can be ensured without using lead.

Semiconductor device

半导体装置具备：层叠基板，具有电路板；半导体芯片，固定于电路板；端子，具有筒状的前端部、和非筒状的布线部，且前端部和布线部由一个导电部件构成；以及接合材料，对电路板和前端部进行电连接和机械连接。

Silicon nitride circuit board

This invention provides a silicon nitride circuit board in which a metal circuit plate is bonded to a high thermal conductive silicon nitride substrate having a thermal conductivity of not less than 60 W/m K, wherein a thickness D s of the high thermal conductive silicon nitride substrate and a thickness D M of the metal circuit plate satisfy a relational formula D s ≦2D M . The silicon nitride circuit board is characterized in that, when a load acts on the central portion of the circuit board which is held at a support interval of 50 mm, a maximum deflection is not less than 0.6 mm until the silicon nitride substrate is broken. The silicon nitride circuit board is characterized in that, when an anti-breaking test is performed to the circuit board which is held at a support interval of 50 mm, an anti-breaking strength is not less than 500 MPa. The metal circuit plate or a circuit layer are integrally bonded on the silicon nitride substrate by a direct bonding method, an active metal brazing method, or an metalize method. According to the silicon nitride circuit board with the above arrangement, high thermal conductivity and excellent heat radiation characteristics can be obtained, and heat cycle resistance characteristics can be considerably improved.

Method for producing bonded object and semiconductor device and copper bonding paste

本発明の一態様は、第一の部材、接合用銅ペースト、及び第二の部材がこの順に積層されている積層体を用意する工程と、接合用銅ペーストを、０．１～１ＭＰａの圧力を受けた状態で焼結する工程と、を備え、接合用銅ペーストは、金属粒子及び分散媒を含有し、金属粒子の含有量が、接合用銅ペーストの全質量を基準として、５０質量％以上であり、金属粒子が、前記金属粒子の全質量を基準として、９５質量％以上のサブマイクロ銅粒子を含有する、接合体の製造方法を提供する。

Solder alloy and semiconductor device

本发明的钎料合金(3)含有：5质量％以上15质量％以下的Sb、3质量％以上8质量％以下的Cu、0.01质量％以上0.15质量％以下的Ni、0.5质量％以上5质量％以下的In，其余部分包括Sn及不可避免的杂质。由此，可得到抑制半导体元件(2)的破裂，而且提高钎料材料的耐裂性的可靠性高的钎料合金(3)及半导体装置(1)。

Direct die solder of gallium arsenide integrated circuit dies and methods of manufacturing gallium arsenide wafers

Electronic devices, and methods of manufacturing the electronic devices, utilizing direct die soldering of GaAs integrated circuit dies. In some embodiments, the GaAs integrated circuit die can have a footprint approximately the same size as a die attach pad. Further, the GaAs integrated circuit die can self-align with the die attach pad after reflow of any solder layer used to attach the die.

Surface acoustic wave filter package structure and method of manufacturing the same

一種表面聲波濾波器封裝結構，其包括一介電基板，具有一介電層、一第一圖案化導電層、一第二圖案化導電層及一導電連接層，其中導電連接層係設於介電層內，並且電性連接分設於介電層二側之第一圖案化導電層及第二圖案化導電層，且第二圖案化導電層至少具有一指叉電極部；一晶片，係以主動面面對於指叉電極部而設置；一高分子密封框體，係設置於晶片與介電基板之間，並圍設於晶片周緣，以與晶片及介電基板共同形成一密閉腔體；模封層係設置於介電基板之上，並且覆蓋晶片及高分子密封框體。本發明復提供表面聲波濾波器封裝結構之製法。

Semiconductor device bonding structure, method for producing semiconductor device bonding structure, and conductive bonding agent

Solar cell assembly Ⅱ

본 발명은 태양 전지 조립체에 관한 것으로서, 본딩 패드에 부착된 태양 전지 및 냉각 기판을 포함하며, 상기 본딩 패드는 열적으로 전도성 있는 접착 수단에 의해 상기 냉각 기판의 표면에 부착되고, 본딩 패드는 본딩 와이어에 의해 냉각 기판에 전기적으로 접촉되고, 열적 및 전기적으로 전도성 있는 접착 수단에 의해 냉각 기판의 표면에 부착된다. The present invention relates to a solar cell assembly comprising a solar cell and a cooling substrate attached to a bonding pad, wherein the bonding pad is attached to the surface of the cooling substrate by thermally conductive bonding means, To the cooling substrate and attached to the surface of the cooling substrate by thermal and electrically conductive bonding means.

Multi-layer die attachment

A packaged electrical device that includes a cured adhesive layer and a cured layer of die attach material coupled between a semiconductor die and a substrate. The packaged electrical device may also include wire bonds coupled between the substrate and leads of the semiconductor die. In addition, the packaged electrical device may be encapsulated in molding compound. A method for fabricating a packaged electrical device. The method includes printing a layer of die attach material over a semiconductor wafer and applying a layer of 2-in-1 die attach film over the layer of die attach material. The method also includes singulating the semiconductor wafer to create a semiconductor die and placing the semiconductor die onto a substrate. In addition the method includes wire bonding the substrate to leads of the semiconductor die and encapsulating the device in molding compound.

Interconnect structure with redundant electrical connectors and associated systems and methods

Microcircuit package having ductile layer