Halbleitergehäuse und Verfahren zu ihrer Herstellung

Verfahren zum Herstellen eines Halbleitergehäuses, wobei das Verfahren umfasst:Ausbilden mehrerer erster Chipöffnungen (20) auf einem Laminatsubstrat (10), wobei das Laminatsubstrat (10) eine Vorderseite (11) und eine gegenüberliegende Rückseite (12) aufweist;Anordnen mehrerer erster Chips (110) in den mehreren ersten Chipöffnungen (20);Ausbilden eines integrierten Abstandshalters (220) um jeden Chip der mehreren ersten Chips (110), wobei der integrierte Abstandshalter (220) die Querschnittsform eines gedrehten „H“ aufweist und in Lücken (Wg) zwischen dem Laminatsubstrat (10) und einer äußeren Seitenwand jedes Chips der mehreren ersten Chips (110) angeordnet wird, wobei der integrierte Abstandshalter (220) den Chip innerhalb des Laminatsubstrats (10) hält, indem er sich teilweise über einen Teil einer Oberseite jedes Chips der mehreren ersten Chips (110) erstreckt; undAusbilden vorderseitiger Kontakte (125) über der Vorderseite (11) des Laminatsubstrats (10).

Leistungshalbleitervorrichtung und Verfahren zum Herstellen einer Leistungshalbleitervorrichtung

Die Erfindung betrifft eine Leistungshalbleitervorrichtung, die ein Substrat (12) mit einer ersten Seite (14) und einer zweiten Seite (16) umfasst, wobei sich die erste Seite (14) und die zweite Seite (16) einander gegenüberliegend befinden, wobei die erste Seite (14) eine Kathode (18) umfasst und wobei die zweite Seite (14) eine Anode (20) umfasst, wobei ein Übergangsabschluss eines p/n-Übergangs bei wenigstens einer Oberfläche des Substrats bereitgestellt ist, bevorzugt bei wenigstens einer der ersten Seite (14) und der zweiten Seite, dadurch gekennzeichnet, dass der Übergangsabschluss durch eine Passivierungsbeschichtung (26) beschichtet ist, wobei die Passivierungsbeschichtung (26) wenigstens ein Material umfasst, das aus der Gruppe ausgewählt ist, die aus einem Anorganisch-Organisch-Verbundmaterial, Parylen und einem Phenolharz, das Polymerpartikel umfasst, besteht. Eine Vorrichtung (10), wie oben beschrieben, behandelt dementsprechend Probleme einer Passivierung von Übergangsabschlüssen ...

Packung mit aufgerauter verkapselter Oberfläche zur Förderung einer Haftung

Eine Packung (100), die mindestens einen elektronischen Chip (102), einen ersten wärmeabführenden Körper (104), der thermisch mit einer Hauptoberfläche des mindestens einen elektronischen Chips (102) gekoppelt ist und dafür ausgelegt ist, Wärmeenergie von dem mindestens einen elektronischen Chip (102) abzuführen, ein Kapselungsmittel (108), das mindestens einen Teil des mindestens einen elektronischen Chips (102) und einen Teil des ersten wärmeabführenden Körpers (104) verkapselt, wobei mindestens ein Teil einer Oberfläche des ersten wärmeabführenden Körpers (104) aufgeraut ist.

Leistungsmodul

Das Leistungsmodul weist mindestens ein elektrisches Bauteil mit einer Kontaktfläche auf, wobei welchem das elektrische Bauteil mittels der Kontaktfläche an mindestens ein mit offenporigem Material gebildetes Kontaktstück des Leistungsmoduls elektrisch kontaktiert ist und das zumindest eine elektrische Bauteil und das zumindest eine Kontaktstück, zumindest in Richtungen der flächigen Erstreckungen der mindestens einen Kontaktfläche, relativ zueinander zumindest formschlüssig festgelegt sind.

HALBLEITERBAUELEMENT MIT PASSIVIERTEM HALBLEITERKOERPER

Semiconductor chip arrangement for flip chip; has base plate metallized rear surface and source and gate contacts connected to contacts of connection frame and has casing with window near rear surface

The arrangement (10) has a connection frame with a number of contacts (20). A base plate with a metallized rear surface (14) and source and gate connectors is connected to the connection frame, so that the contacts are connected directly to the connectors. A casing with windows surrounds at least part of the connection frame and the base plate. The base plate is positioned with respect to the casing, so that the rear surface is near a window. An Independent claim is included for a method for manufacturing the arrangement.

VERKAPSELTES SEMICONDUCTOR PRODUCT AND PROCEDURE FOR ITS PRODUCTION

Verfahren zum Herstellen einer Leiterplatte sowie Leiterplatte

A method for producing a printed circuit board (10) with at least one embedded sensor chip (3), in which at least one sensor face (5) and connectors (4) are arranged on a face of the chip, comprising the following steps: a) providing an adhesive film (1), b) printing a conductor structure (2) made of a conductive paste onto a surface of the adhesive film, c) placing the at least one sensor chip (3) with the face having the at least one sensor face (5) and the connectors (4) onto the conductor structure (2) made of a conductive paste in a registered manner, d) curing the conductive paste, e) applying an insulation layer (6) with a conductor layer (7) lying thereabove onto the surface having the chip (3) of the structure created in the preceding steps, f) laminating the structure created in the preceding steps, g) structuring the conductor layer (7) and forming vias (9) from the conductor layer to the printed conductors (7b, 7c) of the conductor structure on the surface of the adhesive film ...

Method for protecting integrated card chips by deposit of an electrically insulating layer by vacuum suction

EDGELESS TRANSISTOR

EDGELESS TRANSISTOR An MOS mesa transistor wherein the sidewalls of the mesa are electrically isolated from a device formed on the principal surface of the mesa, is provided. The mesa is comprised of a source and a drain which do not extend to a sidewall of the mesa. The source and the drain are surrounded by a band of semiconductor material which is a portion of the mesa and which electrically isolates the source and the drain from the sidewalls of the mesa.

Halbleiterbauelement

Chipmodul, Verwendung des Chipmoduls, Prüfanordnung sowie Prüfverfahren.

Die vorliegende Anmeldung betrifft ein Chipmodul, umfassend einen Chip (1), aufweisend eine Vorder- und eine Rückseite, einen Chipträger, aufweisend eine dem Chip (1) zugewandte Oberseite, eine auf der Oberseite des Chipträgers und zwischen der Rückseite des Chips und der Oberseite des Chipträgers angeordnete leitfähige Kontaktschicht, ein auf einer dem Chip zugewandten Oberseite der Kontaktschicht zumindest bereichsweise angeordneter, elektrisch leitfähiger Klebstoff, der die Oberseite der Kontaktschicht und eine Rückseite des Chips miteinander verbindet Die Kontaktschicht weist zumindest zwei voneinander elektrisch isolierte Bereiche auf, die jeweils über den im jeweiligen isolierten Bereich auf der Oberseite der Kontaktschicht angeordneten leitfähigen Klebstoff mit dem Chip elektrisch verbunden sind Ein leitfähiger Klebstoff kann in der vorliegenden Anmeldung sowohl ein leitfähiger Klebstoff im engeren Sinne als auch eine geeignete leitfähige Verbindung sein, z B Lot Die Erfindung betrifft ...

Chipmodul, Verwendung des Chipmoduls, Prüfanordnung sowie Prüfverfahren.

Die vorliegende Anmeldung betrifft ein Chipmodul, umfassend einen Chip (1), aufweisend eine Vorder- und eine Rückseite; einen Chipträger, aufweisend eine dem Chip (1) zugewandte Oberseite; eine auf der Oberseite des Chipträgers und zwischen der Rückseite des Chips und der Oberseite des Chipträgers angeordnete leitfähige Kontaktschicht, ein auf einer dem Chip zugewandten Oberseite der Kontaktschicht zumindest bereichsweise angeordneter, elektrisch leitfähiger Klebstoff, der die Oberseite der Kontaktschicht und eine Rückseite des Chips miteinander verbindet. Die Kontaktschicht weist zumindest zwei voneinander elektrisch isolierte Bereiche auf, die jeweils über den im jeweiligen isolierten Bereich auf der Oberseite der Kontaktschicht angeordneten leitfähigen Klebstoff mit dem Chip elektrisch verbunden sind. Ein leitfähiger Klebstoff kann in der vorliegenden Anmeldung sowohl ein leitfähiger Klebstoff im engeren Sinne als auch eine geeignete leitfähige Verbindung sein, z.B. Lot. Die Erfindung ...

MULTI-FACED MOLDED SEMICONDUCTOR PACKAGE AND RELATED METHODS

PROCESS OF PROTECTION OF CHIPS OF INTEGRATED CIRCUIT BY DEPOSIT OF LAYER MINCEISOLANTE

Electronic device including electrical connections on an encapsulation block

IC chip, especially having conductive side faces, is insulated by depositing a low viscosity insulating material on an active face surface portion between connection bumps

L'invention concerne un procédé pour l'isolation électrique d'une puce de circuit intégré (200), comportant des flancs et une face active munie de plots de connexion saillants. Il est caractérisé en ce qu'il comprend l'étape suivante consistant à déposer de la matière isolante (207) de faible viscosité sur une portion de surface de ladite face active (203) entre lesdits plots (204). L'application de la matière isolante est notamment effectuée par jet de matière. L'invention concerne également la puce isolée selon l'invention et un dispositif support à puce de circuit intégré utilisant ladite puce isolée.

Protection procedure for Integrated circuit chip, uses vacuum suction to spread insulating material between supporting layers holding chips

L'invention concerne un procédé de protection de puces de circuit intégré (100) disposées sur une plaquette de silicium (10), caractérisé en ce que le procédé comprend les étapes consistant à : - découper des chemins de découpe dans la plaquette de silicium de manière à désolidariser les puces de circuit intégré (100) et à faire apparaître leurs flancs; - disposer les puces de circuit intégré (100) entre deux feuilles support (110, 120); - faire pénétrer un matériau électriquement isolant (150) entre les deux feuilles support (110, 120) de manière à couvrir les flancs de chaque puce de circuit intégré (100). Le matériau électriquement isolant (150), constitué d'une résine ou d'un vernis fluide et adhésif, pénètre entre les feuilles support (110, 120) par aspiration sous vide.

Semiconductor wiring spacers for Schottky double diode

L'invention concerne un composant semiconducteur de type mésa comprenant sur l'une au moins de ses faces, en plus d'un anneau périphérique (9) constitué d'une portion d'une couche de verre de passivation, au moins un plot (30) constitué d'une portion de cette couche et ayant une fonction d'espaceur.

HYBRID ELECTRONIC DEVICE PROTECTED AGAINST MOISTURE AND METHOD FOR MOISTURE PROOFING OF A HYBRID ELECTRONIC DEVICE

적층된 다이 어셈블리들을 위한 Ｚ-상호연결와 다이 패드 간의 전기 커넥터

... 프로세싱의 웨이퍼 레벨에서 다이 패드들 상에 커넥터들을 형성하는 방법들은, 다이 패드들 위에 경화가능한 전기 전도성 물질의 스팟들을 형성하고 이를 상호연결 다이 에지로 또는 그 위로 연장하는 단계; 상기 전도성 물질을 경화시키는 단계; 및 그 후에 웨이퍼 절단 단계에서 그 스팟들을 절단하는 단계를 포함한다. 또한, 그러한 방법들에 의해 z-상호연결 커넥터들로의 다이패드들이 형성되며, 따라서 형태가 이루어지고 크기가 결정된다. 또한, 적층된 다이 어셈블리들 및 적층된 다이 패키지들은 그러한 방법들에 따라 준비되는 다이를 포함하고, 그러한 방법들에 의해 형성되고 그에따라 형태가 이루어지고 디멘젼이 결정되는 z-상호연결 커넥터들로의 다이 패드를 갖는다.

THREE-DIMENSIONAL CHIP STACK AND METHOD OF FORMING THE SAME

MULTI-CHIP SEMICONDUCTOR PACKAGE AND A METHOD FOR FORMING THE SAME CAPABLE OF IMPROVING PRODUCTION EFFICIENCY

PURPOSE: A multi-chip semiconductor package and a method for forming the same are provided to reduce a chip crack by using an insulating layer, a protrusion electrode, and an interconnection. CONSTITUTION: A first semiconductor chip(11) having a first protrusion electrode(17) is formed on the upper surface. A second semiconductor chip(21) having a second protrusion electrode(27) is formed on the first semiconductor chip. An insulating layer(8) is formed between the first protrusion electrode and the second protrusion electrode. A groove is formed on the insulating layer. The first protrusion electrode is interconnected with the second protrusion electrode by filling the groove. COPYRIGHT KIPO 2013 ...

Semiconductor devices, methods of manufacture thereof, and methods of singulating semiconductor devices

Integrated circuit package and method of forming the same

In an embodiment, a device includes: a processor die including circuit blocks, the circuit blocks including active devices of a first technology node; a power gating die including power semiconductor devices of a second technology node, the second technology node larger than the first technology node; and a first redistribution structure including first metallization patterns, the first metallization patterns including power supply source lines and power supply ground lines, where a first subset of the circuit blocks is electrically coupled to the power supply source lines and the power supply ground lines through the power semiconductor devices, and a second subset of the circuit blocks is permanently electrically coupled to the power supply source lines and the power supply ground lines.

Package structure and manufacture method thereof

A package structure including a semiconductor die, an insulating encapsulant, a dielectric layer, and a redistribution layer is provided. The semiconductor die has an active surface, a back surface opposite to the active surface, and a plurality of conductive bumps disposed on the active surface. The insulating encapsulant is encapsulating the semiconductor die. The redistribution layer is disposed on the he insulating encapsulant and electrically connected to the plurality of conductive bumps. The dielectric layer is disposed between the insulating encapsulant and the redistribution layer, wherein the dielectric layer encapsulates at least a portion of each of the plurality of conductive bumps. A manufacturing method of the package structure is also provided.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME, AND RINSING FLUID

Semiconductor device and method of manufacture

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Semiconductor border protection sealant

Semiconductor package and manufacturing method thereof

Resin-encapsulated semiconductor device and method of manufacturing the same

The resin-encapsulated semiconductor device includes a bump electrode (2) formed on an element surface side of a semiconductor chip (1), a conductive layer (3) electrically connected to the bump electrode (2), and a resin encapsulation body (6) covering the semiconductor chip (1), the bump electrode (2), and the conductive layer (3). On a back surface of the semiconductor chip (1) that is flush with a back surface of the resin encapsulation body (6), a metal layer (4) and a laminated film (5) are formed. The laminated film (5) is formed on a front surface of the conductive layer (3). The external terminal (9) is arranged on an inner side of an outer edge of the semiconductor chip (1).

Die protection process

A method of protecting a microelectronic chip contained in a microelectronic assembly, including the steps of depositing a protective coating across the exposed faces of the chip. The coating, having a low modulus of elasticity, is applied across the chip so as to reduce the overall height of the assembly while still protecting the exposed face and corners of the chip from damage.

Semiconductor package with supported overhanging upper die

A circuit assembly is provided with a lower die and an upper die offset and stacked on the lower die. A supporting material, such as a dielectric molding compound or epoxy resin, is dispensed along the side surfaces of the lower die under the overhanging parts of the upper die to provide support for the upper die, thereby preventing cracking of the upper die during wire bonding.

MOUNTING STRUCTURE OF SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor-device mounting structure includes a first semiconductor device and a plate-shaped second semiconductor device connected to the first semiconductor device. The first semiconductor device includes a flexible board, an electronic component, and a sealing resin. The flexible board includes a bendable flexible portion and a hard portion. The flexible portion is bent at a boundary with the hard portion, along a shape of the electronic component such that the flexible board covers the electronic component. The flexible board and the electronic component are sealed with the sealing resin. The first semiconductor device is provided vertical to the second semiconductor device such that the hard portion is provided parallel to the second semiconductor device, and a length of the hard portion in a direction perpendicular to a bend line of the flexible portion is equal to a thickness of a bottom surface of the electronic component in the direction.

SGS or GSGSG pattern for signal transmitting channel, and PCB assembly, chip package using such SGS or GSGSG pattern

A substrate having multiple metal layers is disclosed. The substrate includes a plurality of metal layers disposed in different levels. The plurality of metal layers includes a lower metal layer, a middle metal layer situated overlying the lower layer, and an upper metal layer situated overlying the middle metal layer. A solder mask covers the upper metal layer. A reference plane is arranged in the lower metal layer. A trio of signal traces is arranged in the middle metal layer. The trio of signal traces comprises at least a pair of differential signal traces. A plurality of reference nets is arranged in the middle metal layer.

Micro or below scale multi-layered heterostructure

A heteostructure having a first and a second layer, in micrometer or smaller (e.g. nanometer) scale, arranged in a configuration defining at least one undercut at one side of the second layer, underneath the first layer, is described herein. In various embodiments, the undercut is filled with passivation materials to protect the layers underneath the first layer. Further, in various embodiments, a large metal contact layer including coverage of the first layer sidewall may be employed to provide significant increase in contact area, and to reduce the device contact resist value.

Method for producing miniature amplifier and signal processing unit

A method for producing miniature amplifier and signal processing unit includes the steps of: producing arrays of individual integrated circuits on a side of a wafer, where each circuit has a number of I/O connection points; providing a number of solder connection pads at each integrated circuit for redistribution of the I/O connection points of the integrated circuit; coating the side of the wafer having the solder connection pads-with a protection coating and ensuing through going apertures in the coating to provide electrical contact with the solder connection pads; applying electrical components onto the coating and gaining electrical contact with the solder connection pads through the apertures of the coating material; and singulating the individual amplifiers from the wafer and ensuring light protection of the edges and possible unprotected side of the amplifiers.

HETERO-INTEGRATED STRUCTURE AND MEHOD OF FABRICATING THE SAME

A hetero-integrated structure includes a substrate, a die, a passivation layer, a first redistribution layer, a second redistribution layer, and connecting portions. The die is attached on the substrate. The die has an active surface and a non-active surface. The active surface has pads. The passivation layer covers sidewalls and a surface of the die to expose a surface of the pads. The first redistribution layer is located on the passivation layer and electrically connected to the pads. The second redistribution layer is located on the substrate and adjacent to the die. The connecting portions are connected to the first redistribution layer and the second redistribution layer.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device structure and a method for manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a method for manufacturing a semiconductor device that comprises ordering and performing processing steps in a manner that prevents warpage deformation from occurring to a wafer and/or die due to mismatching thermal coefficients.

PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME

A package structure including an interposer, at least one semiconductor die and an insulating encapsulation is provided. The interposer includes a semiconductor substrate and an interconnect structure disposed on the semiconductor substrate, the interconnect structure includes interlayer dielectric films and interconnect wirings embedded in the interlayer dielectric films, the semiconductor substrate includes a first portion and a second portion disposed on the first portion, the first interconnect structure is disposed on the second portion, and a first maximum lateral dimension of the first portion is greater than a second maximum lateral dimension of the second portion. The at least one semiconductor die is disposed over and electrically connected to the interconnect structure. The insulating encapsulation is disposed on the first portion, wherein the insulating encapsulation laterally encapsulates the least one semiconductor die and the second portion.

Filp chip in leaded molded package and method of manufacture thereof

A chip device that includes a leadframe, a die and a mold compound. The backside of the die is metallized and exposed through a window defined within a mold compound that encapsulates the die when it is coupled to the leadframe. Leads on the leadframe are coupled to source and gate terminals on the die while the metallized backside of the die serves as the drain terminals.

MOISTUREPROOFING CHIP ON FILM PACKAGE

The present disclosure discloses a moistureproofing chip on film (COF) package for protecting the conductive pattern of the COF package against moisture. The moistureproofing COF package includes a base film having a conductive pattern formed on one surface thereof and having a solder resist formed on the conductive pattern and a moistureproofing tape attached to the top of the solder resist and configured to block moisture from being delivered to the conductive pattern through the solder resist.

SEMICONDUCTOR DEVICES

A semiconductor device comprises a substrate, a semiconductor chip on the substrate, and first and second leads between the substrate and the semiconductor chip. The first and second leads extend from an edge of the substrate toward below the semiconductor chip along a first direction parallel to a top surface of the substrate. The first lead includes a first bump connector and a first segment. The second lead includes a second bump connector. The first bump connector is spaced apart in the first direction from the second bump connector. The first segment of the first lead is spaced apart in a second direction from the second bump connector. The second direction is parallel to the top surface of the substrate and perpendicular to the first direction. A thickness of the first segment of the first lead is less than that of the second bump connector. 1. A semiconductor device , comprising:a substrate;a semiconductor chip on the substrate; anda first lead and a second lead between the substrate and the semiconductor chip,wherein the first lead and the second lead extend on the substrate to below the semiconductor chip along a first direction parallel to a top surface of the substrate,wherein the first lead comprises a first bump connector and a first segment connected to the first bump connector,wherein the second lead comprises a second bump connector,wherein the first bump connector is spaced apart in the first direction from the second bump connector,wherein the first segment of the first lead is spaced apart in a second direction from the second bump connector, the second direction being parallel to the top surface of the substrate and perpendicular to the first direction, andwherein a thickness of the first segment of the first lead is less than a thickness of the second bump connector.2. The semiconductor device of claim 1 , wherein the thickness of the first segment of the first lead is less than a thickness of the first bump connector.3. The semiconductor device ...

Semiconductor Devices Having Insulating Substrates and Methods of Formation Thereof

In one embodiment, a method of forming a current sensor device includes forming a device region comprising a magnetic sensor within and/or over a semiconductor substrate. The device region is formed adjacent a front side of the semiconductor substrate. The back side of the semiconductor substrate is attached over an insulating substrate, where the back side is opposite the front side. Sidewalls of the semiconductor substrate are exposed by dicing the semiconductor substrate from the front side without completely dicing the insulating substrate. An isolation liner is formed over all of the exposed sidewalls of the semiconductor substrate. The isolation liner and the insulating substrate include a different material. The method further includes separating the insulating substrate to form diced chips, removing at least a portion of the isolation liner from over a top surface of the device region, and forming contacts over the top surface of the device region.

STRUCTURE AND FORMATION METHOD OF CHIP PACKAGE WITH FAN-OUT FEATURE

A package structure and a formation method of a package structure are provided. The method includes disposing a semiconductor die over a first surface of a redistribution structure. The method also includes forming a first protective layer to surround a portion of the semiconductor die. The method further includes disposing a device element over a second surface of the redistribution structure. The redistribution structure is between the device element and the semiconductor die. In addition, the method includes forming a second protective layer to surround a portion of the device element. The second protective layer is thicker than the first protective layer, and the second protective layer and the first protective layer have different coefficients of thermal expansion.

SEMICONDUCTOR DEVICE

A semiconductor device configures one arm of an upper-lower arm circuit, and includes: a semiconductor element that includes a first main electrode and a second main electrode, wherein a main current between the first main electrode and the second main electrode; and multiple main terminals that include a first main terminal connected to the first main electrode and a second main terminal connected to the second main electrode. The first main terminal and the second main terminal are placed adjacent to each other; A lateral surface of the first main terminal and a lateral surface of the second main terminal face each other in one direction orthogonal to a thickness direction of the semiconductor element.

Micro-trenching mold interface in a pop package

Embodiments disclosed herein include an electronics package. In an embodiment, the electronics package comprises a package substrate and a die on the package substrate. In an embodiment, a mold layer is positioned over the package substrate. In an embodiment, the electronics package further comprises through-mold interconnects through the mold layer, and a trench that extends at least partially into the mold layer.

Fabrication process and structure of fine pitch traces for a solid state diffusion bond on flip chip interconnect

A method to produce a semiconductor package or system-on-flex package comprising bonding structures for connecting IC/chips to fine pitch circuitry using a solid state diffusion bonding is disclosed. A plurality of traces is formed on a substrate, each respective trace comprising at least four different conductive materials having different melting points and plastic deformation properties, which are optimized for both diffusion bonding of chips and soldering of passives components.

DIE STACKING STRUCTURE, SEMICONDUCTOR PACKAGE AND FORMATION METHOD OF THE DIE STACKING STRUCTURE

A die stacking structure, a semiconductor package and a method for forming the die stacking structure are provided. The die stacking structure includes a first device die; second device dies, bonded onto the first device die, and arranged side-by-side; and a stack of dielectric layers, extending in between the second device dies, and laterally enclosing each of the second device dies. The dielectric layers are respectively formed of a spin-on-glass (SOG) or a polymer, and a lower one of the dielectric layers has a thickness greater than a thickness of another one of the dielectric layers at a higher level.

Semiconductor power component

Power semiconductor element The semiconductor element has an angled peripheral edge, with a cathode electrode (2) and an anode electrode (3), at least the anode electrode bonded to the semiconductor body (1) via a metal layer (5,7). The anode electrode has a dia. which is greater than the cathode electrode dia. but less than the dia. of the semiconductor body at the anode side, so that the edge of the semiconductor body projects beyond the anode electrode. Pref. the peripheral edge of the semiconductor body has a surface (9) which extends at an angle between 0 and 10 degrees to the surface of the cathode electrode at the cathode side, with the edge of the anode electrode lying opposite this surface.

SEMICONDUCTOR DEVICE

PURPOSE: To obtain the semiconductor device having the high withstand voltage by a method wherein an insulating member to wrap the surface of a protective film formed on the circumferential face of a semiconductor element is interposed between a package of enlarge the creeping distance between the circumferential face of the element and the air wrapping the element thereof. CONSTITUTION: The semiconductor element 20 having the electrode parts 22 on the surface and on the back is fixed on a holding plate 21 consisting of Mo, etc., and the element is made to be in the electrically conducting condition with the holding plate 21. Moreover a pair of electrodes 23a, 23b for leading out are provided by adhesion by pressure on the electrode part 22 on the surface and on the lower face of the holding plate 21, and a bevel face 20a is formed on the circumferential face of the element 20. Then the protective film 20b consisting of PSG or silicon rubber, etc., is provided on the bevel face 20a, and ...

SEMICONDUCTOR PACKAGE

PURPOSE: To disperse the stress resulting from the contraction due to the hardening of sealing resin and the drop in temperature, to reduce the fluctuations in characteristics of a semiconductor device, and to prevent the protective film on the surface from breakdown by a method wherein the surface and the side face of the semiconductor device adhered to a die-pad are coated with the elastic material such as silicon resin, and resin is sealed thereon. CONSTITUTION: After silver or gold-plated layer 6 has been formed on the bottom face 5 of a die-pad 3 and on the part corresponding to the tip part of an inner lead 4, a press working is performed. Then, the semiconductor device 7, consisting of silicon and other compound, is adhered to the bottom face 5 of the die-pad 3 with silver paste and by performing a gold-silicon eutectic method. Then, the terminal 8 formed on the surface of the semiconductor device 7 and the metal-plated layer 6 of the inner lead 4 are connected using the metal fine ...

Halbleiterbauelement und Verfahren zum Vereinzeln eines Halbleiterbauelements mit einem pn-Übergang

Die Erfindung betrifft ein Halbleiterbauelement (1a, 1b) miteiner Vorder- und einer gegenüberliegenden Rückseite sowie Seitenflächen, sowie zumindest ein Emitter (2a, 2b) und zumindest einer Basis (3a, 3b), wobei zwischen Emitter (2a, 2b) und Basis (3a, 3b) ein pn-Übergang (4a, 4b) ausgebildet ist und der Emitter (2a, 2b) sich parallel zu der Vorder- und/oder Rückseite erstreckt. Wesentlich ist, dass zumindest eine Seitenfläche eine passivierte Trennfläche (T) ist, an der eine Trennflächenpassivierungsschicht (6a, 6b) angeordnet ist, welche ortsfeste Ladungen mit einer Flächenladungsdichte an der Trennfläche (T) im Betrag größer gleich 10cmaufweist. Die Erfindung betrifft weiterhin ein Verfahren zum Vereinzeln eines Halbleiterbauelementes (1a, 1b) mit einem pn-Übergang.

Elektronik-Modul, insbesondere für eine Armbanduhrenschaltung

Struktur und Bildungsverfahren für Chippaket

Strukturen und Bildungsverfahren eines Chippakets werden bereitgestellt. Das Chippaket umfasst einen Chipstapel, der eine Anzahl von Halbleiter-Dies umfasst. Das Chippaket umfasst auch einen Halbleiterchip und der Halbleiterchip ist höher als der Chipstapel. Das Chippaket umfasst weiter eine Paketschicht, die eine Oberseite und Seitenwände des Chipstapels und Seitenwände des Halbleiterchips abdeckt.

VERFAHREN ZUR HERSTELLUNG EINER HALBLEITERVORRICHTUNG

Elektromagnetischer Strahlungsdetektor und Herstellungsverfahren

Halbleitervorrichtung und Verfahren zu ihrer Herstellung

Eine Vielzahl von Halbleitereinrichtungen, die auf einem Siliciumcarbid-Substrat angeordnet sind, ist jeweils mit Elektrodenschichten versehen. Das Siliciumcarbid-Substrat ist in einem Bereich einer freiliegenden Oberfläche des Siliciumcarbid-Substrats geschnitten, welcher die Elektrodenschichten (1) trennt, so dass die Halbleitereinrichtungen individuell getrennt sind. Ein Spannungsabbauharz (7) ist jeweils auf die einzelnen getrennten Halbleitereinrichtungen aufgebracht, um die freiliegende Oberfläche in einem Umfangs-Endbereich der Oberfläche der Halbleitereinrichtung zu bedecken, auf der die Elektrodenschicht angeordnet ist. Somit kann eine Halbleitervorrichtung (PM) erhalten werden, die es ermöglicht, dass eine Halbleitereinrichtung mit einem Siliciumcarbid-Substrat oder einem Halbleitersubstrat aus einer ähnlichen Substanz an einem Einkapselungsharz (R) mit einer großen Haftfestigkeit haftet. Auf diese Weise ist das Einkapselungsharz (R) weniger anfällig gegenüber Rissen, Brüchen, ...

Halbleiterstruktur und Verfahren zur Herstellung mit einer Herangehensweise zum Verhindern von Dünnwaferriss

Verfahren zum Bilden eines Halbleiterbauelements, wobei das Verfahren umfasst:Bereitstellen einer ersten Chiplage (1041) und einer zweiten Chiplage (1042), die auf einer ersten Seite eines Substrats (104) angebracht sind, wobei das Substrat (104) eine Aussparung (220) zwischen der ersten Chiplage (1041) und der zweiten Chiplage (1042) aufweist;Füllen der Aussparung (220) mit einer ersten Formstoffschicht (3301); undBilden einer zweiten Formstoffschicht (3302) über der ersten Formstoffschicht (3301), wobei mindestens eine von den Formstoffschichten (3301, 3302) sich entlang von Seitenwänden der ersten Chiplage (1041) und der zweiten Chiplage (1042) erstreckt;Vereinzeln des Substrats (104) in der Aussparung (220), um eine vereinzelte Struktur zu bilden.

Verfahren zum Herstellen einer Halbleitervorrichtung

Ein Verfahren zum Herstellen einer Halbleitervorrichtung umfasst Prozesse eines: Aufbringens einer Vorläuferlösung eines Schutzfilms über einem Ende jeder einer Vielzahl von Halbleiterelementstrukturen und einer seitlichen Oberfläche und einer Bodenfläche einer Vertiefung; unvollkommenen Trocknens eines Lösungsmittels in der Vorläuferlösung eines Schutzfilms, um einen Schutzfilm auszubilden; und Durchführens einer vollständigen Aushärtung, um ein Lösungsmittel im Schutzfilm nach einem Prozess eines Schneidens zwischen der Vielzahl von Halbleiterelementstrukturen oder einem Prozess eines Ablösens einer Vielzahl von Halbleiterelementen von einem Zerteilungsband zu verdampfen.

Method for packaging using resin

Pressure-connection type semiconductor device and method of fabricating the same

Insulated gate bipolar transistors

A method of manufacturing a printed circuit board and a printed circuit board

Ein Verfahren zum Herstellen einer Leiterplatte (10) mit zumindest einem eingebetteten Sensorchip (3), bei welchem zumindest eine Sensorfläche (5) und Anschlüsse (4) auf einer Fläche des Chips angeordnet sind, die folgenden Schritte aufweisend: a) Bereitstellen einer Klebefolie (1), b) Aufdrucken einer Leiterstruktur (2) aus einer leitfähigen Paste auf eine Oberfläche der Klebefolie, c) registriertes Aufsetzen des zumindest einen Sensorchips (3) mit der die zumindest eine Sensorfläche (5) und die Anschlüsse (4) aufweisenden Fläche auf die Leiterstruktur (2) aus einer leitfähigen Paste, d) Aushärten der leitfähigen Paste, e) Aufbringen einer Isolierschicht (6) mit einer darüber liegenden Leiterschicht (7) auf die den Chip (3) aufweisende Oberfläche des in den vorgehenden Schritten geschaffenen Aufbaus, f) Laminieren des in den vorgehenden Schritten geschaffenen Aufbaus, g) Strukturieren der Leiterschicht (7) und Bilden von Durchkontaktierungen (9) von der Leiterschicht zu Leiterbahnen (7b ...

ELEMENT ARRANGEMENT AND PROCEDURE FOR THE PRODUCTION OF AN ELEMENT ARRANGEMENT

PROTECTIVE LAYER FOR A SEMICONDUCTOR DEVICE

A semiconductor device comprises at least one first semiconductor layer (1-4) and a second layer (8) applied on at least a surface portion of the first layer for protecting the device. The protecting layer is of a second material having a larger energy gap between the valence band and the conduction band than a first material forming said first layer. The second material has at least in one portion of said protecting layer a nano-crystalline and amorphous structure by being composed of crystalline grains with a size less than 100 nm and a resistivity at room temperature exceeding 1x1010 .OMEGA.cm.

POWER ELECTRONIC DEVICE WITH EDGE PASSIVATION

The present invention relates to a semiconductor device or power electronic device. The device includes a pair of pole pieces (36, 38), each having a profiled surface (40, 42). A semiconductor body or wafer (30), preferably of wide bandgap electronic material, is located between the pole pieces (36, 38) and includes contact metallisation regions (32, 34). The semiconductor body (30) produces an electric field that emerges from an edge region. Passivation means includes a first or radially inner part (44) in contact with the edge region of the semiconductor body (30) and which diffuses the electric field as it emerges from the edge region and a second or radially outer part (46). The second part (46) is in contact with the first part (44) and provides a substantially void-free interface with the profiled surface (40, 42) of each pole piece (36, 38). The device may be immersed in a dielectric liquid (50).

Power management applications of interconnect substrates

Various applications of interconnect substrates in power management systems are described.

半导体器件的制造方法

... 本发明提供提高具有球状导电端子的BGA型半导体器件成品率和可靠性的制造方法。该方法在形成了第一配线(3)的半导体晶片(1a)表面通过树脂(5a)粘接第一玻璃衬底(4)。在半导体晶片(1a)的背面通过树脂(5b)粘接第二玻璃衬底(6)。对第一玻璃衬底(4)的一部分进行刻蚀，形成V字形槽(VG)。之后，形成与第一配线(3)连接并在第二玻璃衬底(6)的表面上延伸的第二配线(8)。再通过喷涂在第二配线8上形成由有机树脂构成的保护膜(9)、以及形成用于在保护膜(9)上设置开口部(K)的抗蚀剂层R)。之后使用保护膜(9)作为焊料掩模、通过丝网印刷形成导电端子(10)。此外，也可以在第二玻璃衬底(6)上通过喷涂形成缓冲部件(7)。 ...

Semiconductor device

Semiconductor joint and protect the glass composite, method for manufacturing semiconductor device and semiconductor device

Semiconductor device and semiconductor die around the method of forming the insulating layer

COMPONENT SEMICONDUCTOR HAS ASSEMBLY BY BRAZING

Electromagnetic radiation detector and method of manufacturing the same.

Electrical insulation of chip wafers involves liquid phase deposition of an insulating silica layer

L'invention concerne un procédé d'isolation électrique par le dépôt d'une couche isolante de silice sur les faces latérales de puces comportant circuit (s) intégré (s), faces latérales générées par leur découpe dans une plaque de silicium, elle-même associée à un support adhésif en plastique, qui maintient lesdites puces en position après cette découpe, qui se caractérise en ce que : a - on prépare une phase liquide de traitement formée d'une solution d'acide fluosilicique saturée en silice à e température comprise entre 15 °C et 35 °C. b - on immerge les puces disposées sur leur support plastique adhésif dans la phase liquide de traitement. c - on ajoute un agent de provocation de la sursaturation en silice de la phase liquide de traitement. d - on maintient les dites puces dans le milieu de traitement au plus pendant 10 heures à une température comprise entre environ 15 °C et environ 50 °C.

PACKAGE STRUCTURE AND FORMING METHOD THEREOF

Provided are a package structure and a forming method thereof. The method comprises a step of arranging a first package within a concave part of a first substrate. The first package includes a first die. The method additionally includes a step of attaching a first sensor to the first package and the first substrate. The first sensor is electrically connected to the first package and the first substrate. COPYRIGHT KIPO 2017 ...

MODULE PACKAGE AND PRODUCTION METHOD

광전자 반도체 소자를 제조하기 위한 방법 그리고 광전자 반도체 소자

... 본 발명은 광전자 반도체 소자를 제조하기 위한 방법에 관한 것이며, 상기 방법은 하기의 단계들을 포함한다: 캐리어(1)를 제공하는 단계, 적어도 하나의 광전자 반도체 칩(2)을 상기 캐리어(1)의 상부면(1a)에 배치하는 단계, 상기 적어도 하나의 광전자 반도체 칩(2)을 성형 바디(3)에 의하여 변형하는 단계 － 상기 성형 바디(3)는 상기 적어도 하나의 광전자 반도체 칩(2)의 모든 측면들(2c)을 덮고, 상기 캐리어(1)로부터 떨어져서 마주하는 표면은 상기 적어도 하나의 반도체 칩(2)의 상부면(2a)에서 또는 상기 캐리어 쪽을 향하는 캐리어의 표면은 상기 적어도 하나의 반도체 칩(2)의 하부면(2b)에서 성형 바디(3)를 갖지 않거나 또는 노출되어 있음 －, 상기 캐리어(1)를 제거하는 단계.

A packaging method and structure for an image sensing chip

A packaging method and structure for an image sensing chip is provided. The packaging method includes: providing a wafer having a first surface and a second surface opposite to the first surface, the wafer including multiple image sensing chips arranged in a grid, and the image sensing chip including an image sensing region and a pad which are located at the side of the first surface; forming a cutting groove and a hole corresponding to the pad on the second surface of the wafer, the pad being exposed through the hole; filling the cutting groove with a first photosensitive ink; coating the second surface of the wafer with a second photosensitive ink to cause the second photosensitive ink to cover the hole with a cavity being formed in the hole. The packaging structure of the image sensing chip formed by the method can effectively avoid contact of the second photosensitive ink with the bottom of the hole, which improves the yield of packaging the image sensing chip and improves the reliability ...

Semiconductor device and manufacturing method thereof

A semiconductor device structure and a method for manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a method for manufacturing a semiconductor device that comprises ordering and performing processing steps in a manner that prevents warpage deformation from occurring to a wafer and/or die due to mismatching thermal coefficients.

Semiconductor device tape carrier, manufacturing method for semiconductor device, semiconductor device, and semiconductor module device

The present invention provides a semiconductor device tape carrier formed of an insulative tape 1 of a thin film, which becomes a semiconductor device by conducting a plurality of wire patterns 11 on its surface to a bump 23 of a semiconductor element 21 and being sealed by an insulative resin 22, wherein: an outer dimension of the semiconductor device in a carriage direction of the insulative tape 1 is greater than an integral multiple X (X=1, 2, 3, 4, 5,) of a pitch interval of sprocket holes 2, which are openings formed to carry the insulative tape 1, and not more than: the integral multiple X+ a decimal Y (0 < Y < 1), and the tape pitch for a single semiconductor device is set to the integral multiple X + a decimal Y (0 < Y < 1). In this way, the manufacturing method for semiconductor device, the semiconductor device, and the semiconductor module device for a tape carrier type semiconductor device according to the present invention reduces an unformed region of the insulative tape 1 ...

Methods to planarize semiconductor device and passivation layer

Embodiments of methods in accordance with the present invention provide a planarized surface between a semiconductor device and a portion of surrounding passivation material. The methods involve the use of a hard mask that defines the planarized surface as the interface between the hard mask and both the passivation layer and the device, after a passivation layer etching process. The resulting planarized surface has a small to zero step height, is insensitive to passivation layer non-uniformity and etch non-uniformity, provides full passivation of the device side wall, provides protection for the device against etch-induced damage, and prevents the detrimental effects of passivation layer voids. The methods are applicable to semiconductor device fabrication for electronic and photonic systems such as, but not limited to, cell phones, networking systems, high brightness (HB) light emitting diodes (LEDs), laser diodes (LDs), and multijunction solar cells.

Package structure and methods for forming the same

A structure and a formation method of a package structure are provided. The method includes forming one or more solder elements over a substrate. The one or more solder elements surround a region of the substrate. The method also includes disposing a semiconductor die structure over the region of the substrate. The method further includes dispensing a polymer-containing liquid onto the region of the substrate. The one or more solder elements confine the polymer-containing liquid to being substantially inside the region. In addition, the method includes curing the polymer-containing liquid to form an underfill material.

MICROELECTRONIC ASSEMBLY WITH THERMALLY AND ELECTRICALLY CONDUCTIVE UNDERFILL

A microelectronic assembly may include a microelectronic element having a surface and a plurality of contacts at the surface; a first element consisting essentially of at least one of semiconductor or dielectric material, the first element having a surface facing the surface of the microelectronic element and a plurality of first element contacts at the surface of the first element; electrically conductive masses each joining a contact of the plurality of contacts of the microelectronic element with a respective first element contact of the plurality of first element contacts; a thermally and electrically conductive material layer between the surface of the microelectronic element and the surface of the first element and adjacent conductive masses of the conductive masses; and an electrically insulating coating electrically insulating the conductive masses and the surfaces of the microelectronic element and the first element from the thermally and electrically conductive material layer.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor device includes a semiconductor constituent provided with a semiconductor substrate and a plurality of electrodes for external connection (13) provided under the semiconductor substrate. A lower-layer insulating film (1) is provided under and around the semiconductor constituent. A plurality of lower-layer wirings (22, 22A) are electrically connected to the electrodes for external connection of the semiconductor constituent, and provided under the lower-layer insulating film. An insulation layer (31) is provided on the lower-layer insulating film in the periphery of the semiconductor constituent. An upper-layer insulating film (32) is provided on the semiconductor constituent and the insulation layer. A plurality of upper-layer wirings (33, 33A) are provided on the upper-layer insulating film. A base plate (51) on which the semiconductor constituent and the insulation layer are mounted is removed.

SEMICONDUCTOR MODULE

Disclosed is a semiconductor module comprising a semiconductor element (1) and two terminal electrodes (3a, 3b, 3c) between which the semiconductor element (1) is disposed and with which the semiconductor element (1) is contacted in an electrically conducting manner. The semiconductor element (1) is surrounded by an at least partly electrically insulating housing (5, 7, 11, 12). In order to protect the housing from the effect of electric arcs occurring in the event of an overload, a high temperature-resistant insulator which is arranged at least at some points between a housing wall and the semiconductor element is provided inside the module. The insulator can surround the semiconductor element as a hollow cylinder.

PASSIVATION LAYER FOR POWER SEMICONDUCTORS WITH PN JUNCTIONS APPEARING ON THE SURFACE

L'invention vise à appliquer sur des semiconducteurs de puissance, au niveau de zone de charges d'espace apparaissant à la surface, une couche de passivation (8, 10) possédant une densité de charge la plus faible possible et ne présentant surtout aucun état de charge instable à l'intérieur d'elle-même ni au niveau des surfaces limites. A cet effet, on applique comme couche de passivation une couche d'oxyde (8) sur Si et une couche de nitrure d'oxyde de silicium (9) sur la couche d'oxyde (8).

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DUAL SIDED CONNECTION AND METHOD OF MANUFACTURE THEREOF

A method of manufacture of an integrated circuit packaging system includes: attaching an integrated circuit having a through via over a substrate with the through via coupled to the substrate; attaching a conductive support over the substrate and adjacent to the integrated circuit; forming an encapsulation over the substrate with the conductive support exposed from the encapsulation; and attaching an external interconnect under the substrate.

Packaging structure for gallium nitride devices

Implementations of semiconductor packages may include: a substrate having one or more traces on a first side and one or more traces on a second side of the substrate. The substrate may be rigid. The packages may include at least one die mechanically and electrically coupled to the first side of the substrate. The die may be a high voltage die. The package may include one or more traces along one or more edges of the substrate. The one or more traces along the one or more edges of the substrate provide electrical connectivity between the one or more traces on the first side of the substrate and the one or more traces on the second side of the substrate. The package may also include a molding compound encapsulating at least the first and the one or more edges of the ceramic substrate.

High electron mobility transistor

A method of fabricating a semiconductor device includes forming a first mixed crystal semiconductor layer of AlAs and InAs; applying a solution containing a material easily combining with fluorine to the surface of the first mixed crystal semiconductor layer exposed to the atmosphere so that the material combines with fluorine that sticks to the surface of the first mixed crystal semiconductor layer; and annealing the first mixed crystal semiconductor layer in a vacuum. In this method, since the fluorine on the surface of the first mixed crystal semiconductor layer exposed to the atmosphere combines with the material included in the solution and is removed together with the material, a first mixed crystal semiconductor layer having no fluorine is produced. Therefore, unwanted infiltration of fluorine into the first mixed crystal semiconductor layer is avoided, resulting in a highly reliable semiconductor device with desired characteristics.

Semiconductor Devices, Methods of Manufacture Thereof, and Methods of Singulating Semiconductor Devices

Semiconductor devices, methods of manufacture thereof, and methods of singulating semiconductor devices are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes forming a trench in a substrate, the trench being formed within a first side of the substrate and disposed around a portion of the substrate. A first insulating material is formed over the first side of the substrate and the trench, and a second insulating material is formed over the first insulating material. Apertures are formed in the second insulating material and the first insulating material over the portion of the substrate. Features are formed in the apertures, and a carrier is coupled to the features and the second insulating material. A second side of the substrate is planarized, the second side of the substrate being opposite the first side of the substrate. The second insulating material is removed, and the carrier is removed.

Semiconductor packages and methods of manufacturing the same

Provided are semiconductor devices and methods of manufacturing the same. The semiconductor package includes a substrate, a first semiconductor chip mounted on the circuit substrate and having a first width, a second semiconductor chip overlying the first semiconductor chip and having a second width greater than the first width, and a first under filler disposed between the first and second semiconductor chips, covering a side surface of the first semiconductor chip and having an inclined side surface.

Three dimensional six surface conformal die coating

Semiconductor die are typically manufactured as a large group of integrated circuit die imaged through photolithographic means on a semiconductor wafer or slice made of silicon. After manufacture, the silicon wafer is thinned, usually by mechanical means, and the wafer is cut, usually with a diamond saw, to singulate the individual die. The resulting individual integrated circuit has six exposed surfaces. The top surface of the die includes the circuitry images and any passivation layers that have been added to the top layer during wafer fabrication. The present invention describes a method for protecting and insulating all six surfaces of the die to reduce breakage, provide electrical insulation for these layers, and to provide physical surfaces that can be used for bonding one semiconductor die to another for the purpose of stacking die in an interconnected module or component.

Molded die last chip combination

Various multi-die arrangements and methods of manufacturing the same are disclosed. In one aspect, a method of manufacturing a semiconductor chip device is provided. A redistribution layer (RDL) structure is fabricated with a first side and second side opposite to the first side. An interconnect chip is mounted on the first side of the RDL structure. A first semiconductor chip and a second semiconductor chip are mounted on the second side of the RDL structure after mounting the interconnect chip. The RDL structure and the interconnect chip electrically connect the first semiconductor chip to the second semiconductor chip.

Three dimensional six surface conformal die coating

Semiconductor die are typically manufactured as a large group of integrated circuit die imaged through photolithographic means on a semiconductor wafer or slice made of silicon. After manufacture, the silicon wafer is thinned, usually by mechanical means, and the wafer is cut, usually with a diamond saw, to singulate the individual die. The resulting individual integrated circuit has six exposed surfaces. The top surface of the die includes the circuitry images and any passivation layers that have been added to the top layer during wafer fabrication. The present invention describes a method for protecting and insulating all six surfaces of the die to reduce breakage, provide electrical insulation for these layers, and to provide physical surfaces that can be used for bonding one semiconductor die to another for the purpose of stacking die in an interconnected module or component.

Semiconductor device and method for fabricating the same

A semiconductor device includes two or more semiconductor elements provided on a semi-insulating substrate with a buffer layer and an interlevel film being interposed therebetween, an element isolating portion provided as a result of forming a groove between the two or more semiconductor elements through the buffer layer and the interlevel film so as to reach the semi-insulating substrate, and a protective film for protecting at least ends of the buffer layer in the vicinity of the element isolating portion.

Semiconductor apparatus and semiconductor apparatus manufacturing method

The sealing resin of a semiconductor device is prevented from being peeled off from the substrate of the semiconductor device. A semiconductor device according to the present invention has a semiconductor substrate containing a central portion having a first thickness and a peripheral portion having a second thickness that is smaller than the first thickness, an electrode pad formed on the semiconductor substrate, a sealing resin for sealing the semiconductor substrate, a protruded electrode formed on the sealing resin, and a wire which electrically connects the electrode pad to the protruded electrode.

Sealed rectifier

A sealed rectifier used in a vehicle alternator is composed of a semiconductor diode chip, a base electrode having a disk plate which has a central mount for supporting the chip and an annular wall extending higher than the central mount, a pole electrode having a flange connected to the other side of the chip and an insulating member covering the chip, base electrode and pole electrode. The thickness of the annular wall is smaller than the thickness of the central mount, the outer periphery of the disk plate has a serrated surface for mechanical connection with an cooling fin of the alternator, and the insulating member is composed of resinous material and inorganic filler material to provide residual internal pressure higher than the atmospheric pressure.

Atomic layer deposition encapsulation for power amplifiers in rf circuits

Power amplifiers and methods of coating a protective film of alumina (Al 2 O 3 ) on the power amplifiers are disclosed herein. The protective film is applied through an atomic layer deposition (ALD) process. The ALD process can deposit very thin layers of alumina on the surface of the power amplifier in a precisely controlled manner. Thus, the ALD process can form a uniform film that is substantially free of free of pin-holes and voids.

Semiconductor Device and Method of Forming Bond Wires and Stud Bumps in Recessed Region of Peripheral Area around the Device for Electrical Interconnection to Other Devices

A semiconductor wafer contains a plurality of semiconductor die each having a peripheral area around the die. A recessed region with angled or vertical sidewall is formed in the peripheral area. A conductive layer is formed in the recessed region. A first stud bump is formed over a contact pad of the semiconductor die. A second stud bump is formed over the first conductive layer within the recessed region. A bond wire is formed between the first and second stud bumps. A third stud bump is formed over the bond wire and first stud bump. A dicing channel partially formed through the peripheral area. The semiconductor wafer undergoes backgrinding to the dicing channel to singulate the semiconductor wafer and separate the semiconductor die. The semiconductor die can be disposed in a semiconductor package with other components and electrically interconnected through the bond wire and stud bumps.

Apparatus for restricting moisture ingress

Apparatus and methods to protect circuitry from moisture ingress, e.g., using a metallic structure as part of a moisture ingress barrier.

Semiconductor packages and methods of forming the same

A semiconductor package may include a substrate including a substrate connection terminal, at least one semiconductor chip stacked on the substrate and having a chip connection terminal, a first insulating layer covering at least portions of the substrate and the at least one semiconductor chip, and/or an interconnection penetrating the first insulating layer to connect the substrate connection terminal to the chip connection terminal. A semiconductor package may include stacked semiconductor chips, edge portions of the semiconductor chips constituting a stepped structure, and each of the semiconductor chips including a chip connection terminal; at least one insulating layer covering at least the edge portions of the semiconductor chips; and/or an interconnection penetrating the at least one insulating layer to connect to the chip connection terminal of each of the semiconductor chips.

Semiconductor Device and Method of Manufacturing a Semiconductor Device Including Grinding Steps

A method of manufacturing a device includes providing a semiconductor chip having a first face and a second face opposite to the first face with a contact pad arranged on the first face. The semiconductor chip is placed on a carrier with the first face facing the carrier. The semiconductor chip is encapsulated with an encapsulation material. The carrier is removed and the semiconductor material is removed from the second face of the first semiconductor chip without removing encapsulation material at the same time.

Substrate Dicing

A method and apparatus for separating a substrate into individual dies and the resulting structure is provided. A modification layer, such as an amorphous layer, is formed within the substrate. A laser focused within the substrate may be used to create the modification layer. The modification layer creates a relatively weaker region that is more prone to cracking than the surrounding substrate material. As a result, the substrate may be pulled apart into separate sections, causing cracks the substrate along the modification layers. Dice or other components may be attached to the substrate before or after separation.

Multi-chip semiconductor package and method of fabricating the same

A first semiconductor chip having a first projection electrode formed on an upper surface thereof is prepared. A second semiconductor chip having a second projection electrode is mounted on the first semiconductor chip to expose the first projection electrode. An insulating film is formed between the first projection electrode and the second projection electrode. A groove is formed in the insulating film. An interconnection configured to fill an inside of the groove and connected to the first projection electrode and the second projection electrode is formed.

Power management applications of interconnect substrates

Various applications of interconnect substrates in power management systems are described.

Packages and Method of Forming the Same

A method includes forming a dielectric layer over a substrate, forming an interconnect structure over the dielectric layer, and bonding a die to the interconnect structure. The substrate is then removed, and the dielectric layer is patterned. Connectors are formed at a surface of the dielectric layer, wherein the connectors are electrically coupled to the die.

Semiconductor Packages and Methods of Forming The Same

In one embodiment, a method of fabricating a semiconductor package includes forming a first plurality of die openings on a laminate substrate. The laminate substrate has a front side and an opposite back side. A plurality of first dies is placed within the first plurality of die openings. An integrated spacer is formed around each die of the plurality of first dies. The integrated spacer is disposed in gaps between the laminate substrate and an outer sidewall of each die of the plurality of first dies. The integrated spacer holds the die within the laminate substrate by partially extending over a portion of a top surface of each die of the plurality of first dies. Front side contacts are formed over the front side of the laminate substrate.

Semiconductor Die Connection System and Method

A system and method for connecting semiconductor dies is provided. An embodiment comprises connecting a first semiconductor die with a first width to a second semiconductor die with a larger second width and that is still connected to a semiconductor wafer. The first semiconductor die is encapsulated after it is connected, and the encapsulant and first semiconductor die are thinned to expose a through substrate via within the first semiconductor die. The second semiconductor die is singulated from the semiconductor wafer, and the combined first semiconductor die and second semiconductor die are then connected to another substrate.

Sgs or gsgsg pattern for signal transmitting channel, and pcb assembly, chip package using such sgs or gsgsg pattern

A printed circuit board (PCB) assembly includes a PCB having a core substrate, a plurality of conductive traces on a first surface of the PCB, and a ground layer on the second surface of the PCB. The conductive traces comprise a pair of differential signal traces. An intervening reference trace is disposed between the differential signal traces. A connector is disposed at one end of the plurality of conductive traces. A semiconductor package is mounted on the first surface at the other end of the plurality of conductive traces.

Methods for manufacturing a chip arrangement, methods for manufacturing a chip package, a chip package and chip arrangements

A method for manufacturing a chip arrangement is provided, the method including: forming a hole in a carrier including at least one chip, wherein forming a hole in the carrier includes: selectively removing carrier material, thereby forming a cavity in the carrier, forming passivation material over one or more cavity walls exposed by the selective removal of the carrier material; selectively removing a portion of the passivation material and further carrier material exposed by the selective removal of the passivation material, wherein a further portion of the passivation material remains over at least one cavity side wall; the method further including subsequently forming a layer over the further portion of passivation material remaining over the at least one cavity side wall.

SEMINCONDUCTOR COMPONENT AND METHOD FOR SINGULATING A SEMICONDUCTOR COMPONENT HAVING A PN JUNCTION

A a semiconductor component () having a front side and an opposite rear side and also side surfaces, and also at least one emitter () and at least one base (), wherein a pn junction () is formed between emitter () and base () and the emitter () extends parallel to the front and/or rear side. At least one side surface is a passivated separating surface (T), at which a separating surface passivation layer () is arranged, which has stationary charges having a surface charge density at the separating surface (T) with a magnitude of greater than or equal to 10cm-2. A method for singulating a semiconductor component () having a pn junction is also provided. 111ab. A semiconductor component ( , ) comprising:a front side and an opposite back side and side faces;{'b': 2', '2', '3', '3, 'i': a', 'b', 'a', 'b, 'at least one emitter (, ) and at least one base (, );'}{'b': 4', '4', '2', '2', '3', '3, 'i': a', 'b', 'a', 'b', 'a', 'b, 'a pn junction (, ) formed between the at least one emitter (, ) and the at least one base (, );'}{'b': 2', '2, 'i': a', 'b, 'the emitter (, ) extends parallel to at least one of the front side or back side;'}{'b': 6', '6, 'i': a', 'b, 'at least one of the side faces comprises a passivated separating surface (T) on which a separating surface passivation layer (, ) is arranged; and'}{'b': 6', '6, 'i': a', 'b, 'sup': 12', '−2, 'the separating surface passivation layer (, ) has stationary charges with a surface charge density at the separating surface (T) with an absolute value of greater than or equal to 10cm.'}21166abab. The semiconductor component ( claim 1 , ) as claimed in claim 1 , wherein the separating surface passivation layer ( claim 1 , ) extends over the entire separating surface (T).31144abab. The semiconductor component ( claim 1 , ) as claimed in claim 1 , wherein the pn junction ( claim 1 , ) has a distance of less than 50 μm from the separating surface (T).41166abab. The semiconductor component ( claim 1 , ) as claimed in claim 1 , ...

Stacked Semiconductor Devices and Methods of Forming Same

Stacked semiconductor devices and methods of forming the same are provided. Contact pads are formed on a die. A passivation layer is blanket deposited over the contact pads. The passivation layer is subsequently patterned to form first openings, the first openings exposing the contact pads. A buffer layer is blanket deposited over the passivation layer and the contact pads. The buffer layer is subsequently patterned to form second openings, the second opening exposing a first set of the contact pads. First conductive pillars are formed in the second openings. Conductive lines are formed over the buffer layer simultaneously with the first conductive pillars, ends of the conductive lines terminating with the first conductive pillars. An external connector structure is formed over the first conductive pillars and the conductive lines, the first conductive pillars electrically coupling the contact pads to the external connector structure. 113-. (canceled)14. A method comprising:forming contact pads on a die;blanket depositing a passivation layer over the contact pads;patterning the passivation layer to form first openings, the first openings exposing the contact pads;blanket depositing a buffer layer over the passivation layer and the contact pads;patterning the buffer layer to form second openings, the second openings exposing a first set of the contact pads;forming first conductive pillars in the second openings, topmost surfaces of the first conductive pillars being above a topmost surface of the buffer layer;simultaneously with forming the first conductive pillars, forming conductive lines over the buffer layer, ends of the conductive lines terminating with the first conductive pillars; andforming an external connector structure over the first conductive pillars and the conductive lines, the first conductive pillars electrically coupling the contact pads to the external connector structure.15. The method of claim 14 , wherein forming the external connector structure ...

STRUCTURE AND FORMATION METHOD FOR CHIP PACKAGE

Structures and formation methods of a chip package are provided. The chip package includes a chip stack including a number of semiconductor dies. The chip package also includes a semiconductor chip, and the semiconductor chip is higher than the chip stack. The chip package further includes a package layer covering a top and sidewalls of the chip stack and sidewalls of the semiconductor chip. 1. A chip package , comprising:a chip stack including a plurality of semiconductor dies;a semiconductor chip, wherein the semiconductor chip is higher than the chip stack; anda package layer covering a top and sidewalls of the chip stack and sidewalls of the semiconductor chip.2. The chip package as claimed in claim 1 , wherein a top surface of the semiconductor chip is not covered by the package layer.3. The chip package as claimed in claim 1 , further comprising a substrate claim 1 , wherein the chip stack and the semiconductor chip are bonded on the substrate through conductive bonding structures.4. The chip package as claimed in claim 3 , wherein the substrate is a semiconductor substrate.5. The chip package as claimed in claim 4 , further comprising a conductive feature penetrating through the substrate and electrically connected to one of the conductive bonding structures.6. The chip package as claimed in claim 3 , wherein the package layer surrounds and is in direct contact with the conductive bonding structures.7. The chip package as claimed in claim 3 , further comprising an underfill layer surrounding and in direct contact with the conductive bonding structures claim 3 , wherein the underfill layer is between the substrate and the package layer.8. The chip package as claimed in claim 7 , wherein the underfill layer is in direct contact with the package layer.9. The chip package as claimed in claim 1 , wherein the chip stack comprises a plurality of memory dies.10. The chip package as claimed in claim 1 , wherein a top surface of the package layer is substantially ...

SEMICONDUCTOR PACKAGE

Disclosed is a semiconductor package including a base film that has a first surface and a second surface opposite to the first surface, a plurality of input/output lines on the first surface of the base film, a semiconductor chip disposed on the first surface of the base film and connected to the input/output lines and including a central portion and end portions on opposite sides of the central portion, and a heat radiation pattern on the second surface of the base film The heat radiation pattern corresponds to the semiconductor chip and has a plurality of openings that correspond to the end portions of the semiconductor chip and that vertically overlap the end portions of the semiconductor chip. 1. A semiconductor package , comprising:a base film having a first surface and a second surface opposite to the first surface;a plurality of input/output lines on the first surface of the base film;a semiconductor chip disposed on the first surface of the base film and connected to the input/output lines, the semiconductor chip including a central portion and end portions on opposite sides of the central portion; anda heat radiation pattern on the second surface of the base film, the heat radiation pattern corresponding to the semiconductor chip and having a plurality of openings that correspond to the end portions of the semiconductor chip and that vertically overlap the end portions of the semiconductor chip.2. The semiconductor package of claim 1 , wherein the semiconductor chip includes a plurality of first chip pads on the central portion and a plurality of second chip pads on the end portions claim 1 ,wherein the second chip pads of the semiconductor chip vertically overlap the openings of the heat radiation pattern.3. The semiconductor package of claim 2 , further comprising a plurality of connection terminals between the input/output lines and the first and second chip pads.4. The semiconductor package of claim 1 , first and second edges opposite to each other; and ...

ELECTRONIC PACKAGE AND METHOD OF CONNECTING A FIRST DIE TO A SECOND DIE TO FORM AN ELECTRONIC PACKAGE

Some embodiments relate to an electronic package. The electronic package includes a substrate and a die attached to the substrate. The electronic package further includes an underfill positioned between the die and the substrate due to capillary action. A support surrounds the die. The support provides the same beneficial fillet geometry on all die edges. Therefore, the support provides similar stress reduction on all die edges. Other embodiments relate to method of fabricating an electronic package. The method includes attaching a die to a substrate and inserting an underfill between the die and the substrate using capillary action. The method further includes placing a support around the die such that the support surrounds the die. 1. An electronic package comprising:a substrate;a die attached to the substrate;an underfill positioned between the die and the substrate due to capillary action; anda support surrounding the die.2. The electronic package of claim 1 , wherein the die is flip chip bonded to the substrate.3. The electronic package of claim 1 , wherein the underfill secures the support to the substrate.4. The electronic package of claim 1 , wherein the underfill secures the support to the die.5. The electronic package of claim 1 , wherein the support has a substantially uniform cross-section.6. The electronic package of claim 1 , wherein the support has an inner bottom edge and an outer bottom edge claim 1 , the inner bottom edge being chamfered to receive underfill when the support is mounted around the die.7. The electronic package of claim 6 , wherein the support has an inner upper edge and an inner outer upper edge claim 6 , the inner upper edge including a channel to receive excess underfill that flows upward between the die and the support when the support is mounted around the die.8. The electronic package of claim 1 , wherein the cross-section of the support changes such that the cross-section is larger in areas of relatively higher stress on the ...

Integrated circuit packages and methods of forming same

An integrated circuit package and a method of forming the same are provided. A method includes forming a conductive column over a carrier. An integrated circuit die is attached to the carrier, the integrated circuit die being disposed adjacent the conductive column. An encapsulant is formed around the conductive column and the integrated circuit die. The carrier is removed to expose a first surface of the conductive column and a second surface of the encapsulant. A polymer material is formed over the first surface and the second surface. The polymer material is cured to form an annular-shaped structure. An inner edge of the annular-shaped structure overlaps the first surface in a plan view. An outer edge of the annular-shaped structure overlaps the second surface in the plan view.

Structure of Power Devices and Method of Manufacturing Thereof

The present invention relates to a method of manufacturing a power device and a structure of the power device, which is used to solve the problem that conventional power device needs to be independently packaged and requires a welding process. The method includes: forming a plurality of semiconductor device layers spaced in intervals on a front of a silicon wafer; excavating a plurality of grooves on the front of the silicon wafer to separate the plurality of semiconductor device layers; filling each of the plurality of grooves with each of a plurality of first spacer materials; grinding a back of the silicon wafer until the first spacer materials being exposed; attaching a plurality of metal layers to a region of the back of the silicon wafer opposite to the plurality of semiconductor device layers; and electrically connecting each of independent plurality of lead frames to the plurality of metal layers respectively. The present invention further includes the structure of the power device. 1. A method of manufacturing a power device , comprising:forming a plurality of semiconductor device layers spaced in intervals on a front of a silicon wafer;excavating a plurality of grooves on the front of the silicon wafer to separate the plurality of semiconductor device layers;filling each of the plurality of grooves with each of a plurality of first spacer materials;grinding a back of the silicon wafer until the first spacer materials being exposed;attaching a plurality of metal layers to a region on the back of the silicon wafer opposite to the plurality of semiconductor device layers; andelectrically connecting each of independent plurality of lead frames to the plurality of metal layers respectively.2. The method according to claim 1 , wherein the plurality of grooves are excavated on the front of the silicon wafer claim 1 , allowing the silicon wafer to form a structure from which a plurality of silicon layers staggers and protrudes out of the front of the silicon wafer ...

SEMICONDUCTOR PACKAGE STRUCTURE

A semiconductor package structure and a method for forming the same are disclosed. The semiconductor package structure includes a semiconductor die, a molding layer and an inductor. The semiconductor die includes an active surface, a back surface and a sidewall surface between the active surface and the back surface. The molding layer covers the back surface and the sidewall surface of the semiconductor die. The inductor is in the molding layer. The sidewall surface of the semiconductor die faces toward the inductor. 1. A semiconductor package structure , comprising:a molding layer having a first molding surface and a second molding surface opposing to the first molding surface;a semiconductor die having an active surface and being embedded in the molding layer, wherein the active surface of the semiconductor die has a contact pad therein;an inductor extending through the molding layer from the first molding surface to the second molding surface of the molding layer, wherein a lower surface of the molding layer is coplanar with a lower surface of the inductor, and wherein an upper surface of the contact pad is coplanar with an upper surface of the inductor; anda redistribution layer extending from the active surface of the semiconductor die and the second molding surface of the molding layer in a direction away from the first molding surface of the molding layer,wherein a layout region of the redistribution layer and a layout region of the inductor are overlapping, andwherein a layout pattern of the inductor and a layout pattern of the semiconductor die are non-overlapping.2. The semiconductor package structure of claim 1 , wherein a pattern of the inductor surrounds the semiconductor die.3. The semiconductor package structure of claim 1 , wherein a pattern of the inductor is disposed outside of the semiconductor die.4. The semiconductor package structure of claim 1 , wherein the layout region of the redistribution layer is larger than a layout region of the ...

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

A method of manufacturing a semiconductor package includes forming at least two partial package chip stacks, each partial package chip stack including at least two semiconductor chips each including a plurality of through substrate vias (TSVs), and including a first mold layer surrounding side surfaces of the at least two semiconductor chips, and sequentially mounting the at least two partial package chip stacks on a package substrate in a direction vertical to a top surface of the package substrate, such that the at least two partial package chip stacks include a first partial package chip stack and a second partial package chip stack directly connected to the first partial package chip stack. 1. A method comprising:providing a first sub-package unit including at least two first semiconductor chips, which are vertically stacked, and a first mold layer surrounding side surfaces of the at least two first semiconductor chips; andproviding a second sub-package unit including at least two second semiconductor chips, which are vertically stacked, and a second mold layer that surrounds side surfaces of the at least two second semiconductor chips and is vertically spaced apart from the first mold layer, the second sub-package unit being disposed on the first sub-package unit,wherein the at least two first semiconductor chips and the at least two second semiconductor chips each include a through substrate via (TSV), andwherein a top-most semiconductor chip of the at least two first semiconductor chips is electrically connected to the bottom-most semiconductor chip of the at least two second semiconductor chips, without a package substrate therebetween; andproviding a package substrate on which the at least two first semiconductor chips and the at least two second semiconductor chips are vertically stacked to form a semiconductor package.2. The method claim 1 , further comprising:providing an upper connection pad on a top surface of a second semiconductor chip disposed in an ...

VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME

Vertical memory devices, and methods of manufacturing the same, include providing a substrate including a cell array region and a peripheral circuit region, forming a mold structure in the cell array region, forming an opening for a common source line passing through the mold structure and extending in a first direction perpendicular to a top surface of the substrate, forming a first contact plug having an inner sidewall delimiting a recessed region in the opening for the common source line, and forming a common source bit line contact electrically connected to the inner sidewall of the first contact plug. 1. A vertical memory device comprising:a cell gate stack structure on a substrate, the cell gate stack structure comprising a plurality of cell gate lines spaced apart from one another in a vertical direction, and an opening adjacent to the plurality of cell gate lines, the opening passing through the cell gate stack structure;a contact plug in the opening, the contact plug comprising an inner sidewall delimiting a recessed region in the opening;a buried film pattern in a portion of the recessed region, the buried film pattern being formed of a Si-containing material having a resistance greater than a resistance of the contact plug; anda separation film pattern interposed between the plurality of cell gate lines and the contact plug.2. The vertical memory device of claim 1 , wherein the contact plug comprises a conductive metal nitride.3. The vertical memory device of claim 1 , wherein the contact plug comprises a first top surface farthest from the substrate claim 1 , andwherein the buried film pattern comprises a second top surface farthest from the substrate, the second top surface being closer to the substrate than the first top surface.4. The vertical memory device of claim 1 , wherein the contact plug has an inner top surface delimiting a lowermost portion of the recessed region claim 1 , the inner top surface being higher than a top surface of the substrate ...

Method of Manufacture of a Semiconductor Device

In order to prevent cracks from occurring at the corners of semiconductor dies after the semiconductor dies have been bonded to other substrates, an opening is formed adjacent to the corners of the semiconductor dies, and the openings are filled and overfilled with a buffer material that has physical properties that are between the physical properties of the semiconductor die and an underfill material that is placed adjacent to the buffer material. 1. A device comprising:a semiconductor device with an opening located at a corner of the semiconductor device;a buffer material located at least partially within the opening, wherein the buffer material does not extend across the semiconductor device;a substrate bonded to the semiconductor device; andan underfill material located between the semiconductor device and the substrate, wherein the buffer material has a first property with a value located between a value of the semiconductor device and a value of the underfill material.2. The device of claim 1 , wherein the buffer material has a first sidewall that is aligned with a second sidewall of the semiconductor device.3. The device of claim 1 , wherein the buffer material has a rounded surface facing away from the semiconductor device.4. The device of claim 1 , wherein the value is a coefficient of thermal expansion.5. The device of claim 1 , wherein the value is a Young's modulus.6. The device of claim 1 , wherein the buffer material comprises epoxy.7. A device comprising:a first semiconductor device comprising a top surface and a sidewall, wherein the top surface and the sidewall are connected by a first surface that is misaligned from the top surface and the sidewall;a buffer material in physical contact with the top surface and covering the first surface, wherein a second surface of the buffer material is aligned with the sidewall; andan underfill material in physical contact with the top surface and the buffer material.8. The device of claim 7 , wherein the buffer ...

Underfill Control Structures and Method

A semiconductor device and method of reducing the risk of underbump metallization poisoning from the application of underfill material is provided. In an embodiment a spacer is located between a first underbump metallization and a second underbump metallization. When an underfill material is dispensed between the first underbump metallization and the second underbump metallization, the spacer prevents the underfill material from creeping towards the second underbump metallization. In another embodiment a passivation layer is used to inhibit the flow of underfill material as the underfill material is being dispensed.

Method of packaging chip and chip package structure

A method of packaging a chip includes laminating a first substrate with a second substrate, the first substrate being capable of withstanding a greater stress than the second substrate; applying an adhesive layer on the second substrate; bonding the chip on the adhesive layer; and forming an encapsulation layer that covers at least the chip.

Integrated circuit system and packaging method therefor

An integrated circuit system and a packaging method therefor are disclosed. The method includes providing a first carrier and a second carrier oppositely, with a first device set of the first carrier and a second device set of the second carrier both located between the first and second carriers, providing a molding material between the first and second carriers to make the first and second device sets respectively in contact with the molding material, curing the material to make the first and second device sets respectively mounted at two sides of the molding material, making the first and second carriers detached from the first device set and the molding material and from the second device set and the molding material respectively; and forming connection holes in the molding material and fabricating a conductive layer which extend into the connection holes to electrically connect the first and second device sets. 1. An integrated circuit system packaging method , comprising steps of: providing a first carrier and a second carrier opposite to each other, wherein a first device set of the first carrier and a second device set of the second carrier are both located between the first carrier and the second carrier,', 'providing a molding material between the first carrier and the second carrier, wherein the first device set and the second device set are respectively in contact with the molding material, and', 'curing the molding material, so that the first device set and the second device set are respectively mounted at two sides of the molding material;, 'curing, comprising 'detaching the first carrier from the first device set and the molding material, and detaching the second carrier detached from the second device set and the molding material; and', 'detaching, comprising forming connection holes in the molding material, and', 'forming a conductive layer in such a way that the conductive layer extends into the connection holes, wherein the conductive layer enables ...

Semiconductor Device and Method of Manufacture

In order to prevent cracks from occurring at the corners of semiconductor dies after the semiconductor dies have been bonded to other substrates, an opening is formed adjacent to the corners of the semiconductor dies, and the openings are filled and overfilled with a buffer material that has physical properties that are between the physical properties of the semiconductor die and an underfill material that is placed adjacent to the buffer material. 1. A method of manufacturing a device , the method comprising:forming an opening along an outside edge of a semiconductor die;overfilling at least a portion of the opening with a buffer material; andplacing an underfill material adjacent to the buffer material.2. The method of claim 1 , further comprising singulating the semiconductor die from a semiconductor wafer after the overfilling the opening and before the placing the underfill material.3. The method of claim 2 , wherein the singulating the semiconductor die is performed by slicing through the buffer material and the semiconductor wafer with a saw.4. The method of claim 1 , further comprising bonding the semiconductor die to a first substrate prior to the placing the underfill material adjacent to the buffer material.5. The method of claim 4 , wherein the underfill material flows between the first substrate and the buffer material during the placing the underfill material.6. The method of claim 5 , further comprising bonding the first substrate to a second substrate.7. The method of claim 1 , wherein the overfilling at least the portion of the opening with the buffer material leaves the buffer material along an entire perimeter of the semiconductor die.8. A method of manufacturing a device claim 1 , the method comprising:partially singulating a first wafer to form a first opening within the first wafer, the first wafer comprising a semiconductor substrate of a first material, the first material having a first property with a first value, wherein the first opening ...

Insulated die

An insulated chip comprising a semiconductor chip comprising at least one chip pad and an electrically insulating layer surrounding at least part of the semiconductor chip. 1. An insulated chip , comprising:a semiconductor chip comprising at least one chip pad;an electrically insulating layer surrounding at least part of the semiconductor chip.2. The chip according to claim 1 , wherein an entire surrounding surface of the semiconductor chip and the at least one pad is covered with the electrically insulating layer.3. The chip according to claim 1 , wherein a surrounding surface of the semiconductor chip excluding only at least one surface portion around the at least one pad is covered with the electrically insulating layer.4. The chip according to claim 1 , wherein five side surfaces of the semiconductor chip are covered with the electrically insulating layer claim 1 , and a sixth side surface of the semiconductor chip is free of the electrically insulating layer.5. The chip according to claim 1 , wherein the electrically insulating layer is made of a polymer material claim 1 , in particular parylene.6. The chip according to claim 1 , wherein the electrically insulating layer is made of a material being removable by laser drilling.7. A method of manufacturing an insulated chip claim 1 , the method comprising:providing a semiconductor chip comprising at least one chip pad;surrounding at least part of the semiconductor chip with an electrically insulating layer.8. The method according to claim 7 , wherein the surrounding comprises:placing the semiconductor chip on an auxiliary carrier, and;depositing a first part of electrically insulating material of the electrically insulating layer on an exposed surface of the semiconductor chip placed on the auxiliary carrier.9. The method according to claim 8 , wherein the surrounding further comprises:placing a surface portion of the semiconductor chip covered with the deposited electrically insulating material on a further ...

THREE-DIMENSIONAL STACKING STRUCTURE

A three-dimensional stacking structure is described. The stacking structure includes at least a bottom die, a top die and a spacer protective structure. The bottom die includes contact pads in the non-bonding region. The top die is stacked on the bottom die without covering the contact pads of the bottom die and the bottom die is bonded with the top die through bonding structures there-between. The spacer protective structure is disposed on the bottom die and covers the top die to protect the top die. By forming an anti-bonding layer before stacking the top dies to the bottom dies, the top die can be partially removed to expose the contact pads of the bottom die for further connection. 1. A stacking structure , comprising:a first die, having a first bonding structure, wherein the first bonding structure comprises contact pads;a second die, having a second bonding structure, wherein the second die is stacked on the first die, and the second bonding structure is bonded with the first bonding structure;a spacer protective structure, disposed over the first die and surrounding the second die, wherein the spacer protective structure covers sidewalls of the second die; andan anti-bonding layer, disposed over the first die and located between the spacer protective structure and the first die.2. The structure of claim 1 , wherein the first bonding structure further comprises first bonding elements embedded in a first dielectric material claim 1 , and the second bonding structure comprises second bonding elements embedded in a second dielectric material.3. The structure of claim 2 , wherein the second bonding structure is bonded with the first bonding structure through the bonding of the first and second bonding elements and the bonding of the first and second dielectric materials.4. The structure of claim 2 , wherein the second bonding structure further comprises at least one seal ring structure embedded within the second dielectric material claim 2 , arranged along a ...

SEMICONDUCTOR DEVICE WITH A SEMICONDUCTOR CHIP CONNECTED IN A FLIP CHIP MANNER

A semiconductor device includes a wiring board, a semiconductor chip, and a connecting member provided between a surface of the wiring board and a functional surface of the semiconductor chip. The connecting member extends a distance between the wiring board surface and the functional surface. A sealing material seals a gap space between the wiring board and the semiconductor chip. An electrode is formed at the wiring board surface and arranged outside of an outer periphery of the sealing material. A lateral distance between an outer periphery of the semiconductor chip and the outer periphery of the sealing material is between 0.1 mm and a lateral distance from the outer periphery of the semiconductor chip to the electrode. 1. A semiconductor device comprising:a wiring board having a surface,a semiconductor chip having a functional surface,a connecting member provided between the surface of the wiring board and the functional surface of the semiconductor chip, the connecting member extending a distance between the surface of the wiring board and the functional surface of the semiconductor chip,a sealing material that seals a gap space between the wiring board and the semiconductor chip, andan electrode formed at the surface of the wiring board and arranged outside of an outer periphery of the sealing material,wherein a lateral distance between an outer periphery of the semiconductor chip and the outer periphery of the sealing material is between 0.1 mm and a lateral distance from the outer periphery of the semiconductor chip to the electrode,wherein the wiring board includes an insulating pattern provided on the surface thereof, the insulating pattern not overlapping with the semiconductor chip when viewed in a plan view, andwherein the sealing material extends to an upper surface of the insulating pattern such that the sealing material covers at least a portion of the upper surface of the insulating pattern.2. The semiconductor device according to claim 1 , wherein ...

SEMICONDUCTOR PACKAGE HAVING A PLURALITY OF SEMICONDUCTOR CHIPS STACKED THEREIN

A semiconductor package may include a first semiconductor chip having a plurality of first bonding pads arranged at a first pitch on a first active surface. The semiconductor package may include one or more reconfigurable package units each including a second semiconductor chip having a plurality of second bonding pads arranged at a second pitch on a second active surface; a semiconductor chip connector arranged spaced apart from the second semiconductor chip and having a plurality of through vias arranged at the first pitch; a molding layer surrounding side surfaces of the second semiconductor chip and the semiconductor chip connector; and redistribution lines formed over the second semiconductor chip, the semiconductor chip connector, and the molding layer. The semiconductor package may include coupling members interposed between the first bonding pads of the first semiconductor chip and the through vias of the reconfigurable package unit and between the respective through vias of the stacked reconfigurable package units. 1. A semiconductor package , comprising:a first semiconductor chip having a plurality of first bonding pads arranged at a first pitch on a first active surface; a second semiconductor chip having a plurality of second bonding pads arranged at a second pitch different from the first pitch on a second active surface;', 'a semiconductor chip connector arranged spaced apart from the second semiconductor chip and having a plurality of through vias arranged at the first pitch;', 'a molding layer surrounding at least side surfaces of the second semiconductor chip and the semiconductor chip connector; and', 'redistribution lines formed over the second semiconductor chip, the semiconductor chip connector, and the molding layer so as to electrically couple the second bonding pads and the through vias; and, 'one or more reconfigurable package units stacked over the first semiconductor chip, each comprisingcoupling members interposed between the first ...

METHOD FOR PRODUCING SEMICONDUCTOR DEVICE, SEMICONDUCTOR PACKAGE, AND METHOD FOR PRODUCING SEMICONDUCTOR PACKAGE

A method for producing a semiconductor device includes dicing, at a scribe area of a semiconductor wafer, the semiconductor wafer into semiconductor chips including respective circuit areas formed on the semiconductor wafer, the scribe area being provided between the circuit areas and extending in a first direction in a plan view, wherein the scribe area includes a first area extending in the first direction and second areas including monitor pads and extending in the first direction and located on both sides of the first area, wherein the method includes removing at least portions of the monitor pads by emitting laser beam to the second areas before the dicing, and wherein, in the dicing, the semiconductor wafer is diced at the first area. 1. A method for producing a semiconductor device , the method comprising:dicing, at a scribe area, a semiconductor wafer into a plurality of semiconductor chips each including at least one of a plurality of circuit areas, the semiconductor wafer including the plurality of circuit areas and the scribe area provided between neighboring circuit areas of the plurality of circuit areas, the scribe area extending in a first direction in a plan view, a first area extending in the first direction; and', 'second areas located on both sides of the first area in a second direction perpendicular to the first direction in the plan view, the second areas extending in the first direction, monitor pads being provided in the second areas,, 'wherein the scribe area includeswherein the method comprises:before the dicing of the semiconductor wafer into the plurality of semiconductor chips, removing at least portions of the monitor pads by emitting laser beam to the second areas, andwherein, in the dicing of the semiconductor wafer into the plurality of semiconductor chips, the semiconductor wafer is diced at the first area.2. The method for producing the semiconductor device according to claim 1 , wherein in the scribe area claim 1 , the ...

AN ADHESIVE AND THERMAL INTERFACE MATERIAL ON A PLURALITY OF DIES COVERED BY A LID

Provided are a package structure and a method of forming the same. The package structure includes a first die, a second die, an interposer, an underfill layer, a thermal interface material (TIM), and an adhesive pattern. The first die and the second die are disposed side by side on the interposer. The underfill layer is disposed between the first die and the second die. The TIM is disposed on the first die, the second die, and the underfill layer. The adhesive pattern is disposed between the underfill layer and the TIM to separate the underfill layer from the TIM. 1. A package structure , comprising:a first die and a second die group, disposed side by side on an interposer;an underfill layer, disposed between the first die and the second die group;a thermal interface material (TIM), disposed on the first die, the second die group, and the underfill layer;an adhesive pattern, disposed between the underfill layer and the TIM to separate the underfill layer from the TIM; andan encapsulant laterally encapsulating the first die, the second die group, and the underfill layer, wherein a sidewall of the encapsulant is substantially aligned with a sidewall of the interposer.2. The package structure of claim 1 , wherein the second die group comprises at least one second die or a plurality of second dies claim 1 , the plurality of second dies are respectively disposed at both sides of the first die claim 1 , and the adhesive pattern comprises a plurality of adhesive layers discretely distributed on the underfill layer between the first die and the plurality of second dies.3. The package structure of claim 2 , wherein a portion of the plurality of adhesive layers is disposed between the encapsulant and the TIM to separate the encapsulant from the TIM.4. (canceled)5. The package structure of claim 2 , wherein one of the plurality of adhesive layers has a curved top surface and has a thickness decreasing along a direction from center to edge.6. The package structure of claim 1 , ...

Stacked package and method of manufacturing the same

A stacked package includes a substrate, and a first structure bonded to the substrate. The first structure has a plurality of bumps, and a first hydrophilic coating is on sidewalls of the first structure. The stacked package further includes a second structure bonded to the plurality of bumps. The first hydrophilic coating is on sidewalls of the second structure. The first structure is between the second structure and the substrate. The stacked package further includes a housing, wherein the housing defines a volume enclosing the first structure and the second structure. A second hydrophilic coating is on sidewalls of an inner surface of the housing. The stacked package further includes a cooling fluid within the volume enclosing the first structure and the second structure. A top surface of the cooling fluid is above a top surface of the second structure.

Method for fabricating laterally insulated integrated circuit chips

Laterally insulated integrated circuit chips are fabricated from a semiconductor wafer. Peripheral trenches are formed in the wafer which laterally delimit integrated circuit chips to be formed. A depth of the peripheral trenches is greater than or equal to a desired final thickness of the integrated circuit chips. The peripheral trenches are formed by a process which repeats successive steps of a) ion etching using a sulfur hexafluoride plasma, and b) passivating using an octafluorocyclobutane plasma. Upon completion of the step of forming the peripheral trenches, lateral walls of the peripheral trenches are covered by an insulating layer of a polyfluoroethene. A thinning step is performed on the lower surface of the wafer until a bottom of the peripheral trenches is reached. The insulating layer is not removed.

SEMICONDUCTOR PACKAGES AND METHODS OF MANUFACTURING SAME

A semiconductor package and a method manufacturing the same are disclosed. At least one semiconductor chip is mounted on a package substrate. An insulative mold layer is formed at sides of the semiconductor chip having at least one recess in a region in which conductive connection members are formed, the recess defining one or more protrusions within the mold layer. An interposer is positioned on the protrusions with the conductive connection members connecting and providing electrical connections between conductive pads on the upper surface of the package and conductive pads on the lower surface of the package substrate. The protrusions may position the interposer in the vertical direction by defining the vertical spacing between the lower surface of the interposer and the upper surface of the package substrate. The protrusions may also position the interposer in one or more horizontal directions and/or prevent substantial movement during connecting of the interposer to the package substrate. An under-fill resin layer may be injected into remaining space between the interposer and the package substrate. 1. A method of manufacturing a semiconductor package comprising:attaching a plurality of first conductive bumps to respective first conductive pads provided on an upper surface of a first substrate;providing an interposer with a plurality of second conductive bumps attached to respective second conductive pads on a bottom surface of the interposer;flip chip mounting a first semiconductor chip to the first substrate including electrically connecting the first semiconductor chip to third conductive pads provided on the upper surface of the first substrate;forming an insulative mold layer on the upper surface of the first substrate to cover and surround the first conductive bumps, the insulative mold layer extending along sidewalls of the first semiconductor chip and having an upper surface at least as high as an upper surface of the first semiconductor chip;etching ...

ELECTRONIC DEVICE AND MANUFACTURING METHOD OF ELECTRONIC DEVICE

An electronic device includes a semiconductor device including a semiconductor chip, a first grounded layer formed on a surface of the semiconductor chip, a mold resin arranged on a side of the semiconductor device, an insulating layer arranged over the semiconductor device and the mold resin, a second grounded layer formed between the semiconductor device and the insulating layer, and the resin mold and the insulating layer, a second wiring layer formed over the insulating layer and includes a first area disposed at a part overlapping with the second grounded layer and a second area disposed on a side of an end part of the second grounded layer, a via that couples the first wiring layer and the second area of the second wiring layer, and a grounded conductor formed inside the insulating layer at a position overlapping with the second area of the second wiring layer. 1. An electronic device comprising:a semiconductor device including a semiconductor chip, a first grounded layer formed on a surface of the semiconductor chip, and a first wiring layer that constitutes a first transmission line that has a predetermined characteristic impedance with the first grounded layer;a mold resin arranged on a side of the semiconductor device;an insulating layer arranged over the semiconductor device and the mold resin;a second grounded layer formed between the semiconductor device and the insulating layer, and the resin mold and the insulating layer;a second wiring layer formed over the insulating layer and includesa first area disposed at a part overlapping with the second grounded layer anda second area disposed on a side of an end part of the second grounded layer, the first area including a first line width and constituting a second transmission line including a predetermined characteristic impedance equal to the characteristic impedance of the first transmission line with the second grounded layer, the second area including a second line width smaller than the first line ...

SEMICONDUCTOR PACKAGE

Disclosed is a semiconductor package comprising first and second semiconductor structures spaced apart on a first substrate, a heat sink covering the first and second semiconductor structure and the first substrate, and a thermal interface material layer between the heat sink and the first and second semiconductor structures. The first semiconductor structure includes a first sidewall adjacent to the second semiconductor structure and a second sidewall opposite the first sidewall. The thermal interface material layer includes a first segment between the first and second semiconductor structures and a second segment protruding beyond the second sidewall. A first distance from a top surface of the first substrate to a lowest point of a bottom surface of the first segment is less than a second distance from the top surface of the first substrate to a lowest point of a bottom surface of the second segment. 1. A semiconductor package , comprising:a first substrate;a first semiconductor structure mounted on the first substrate, the first semiconductor structure including a first sidewall and a second sidewall opposite to the first sidewall;a second semiconductor structure mounted on the first substrate and spaced apart from the first semiconductor structure, the second semiconductor structure being adjacent to the first sidewall of the first semiconductor structure;a heat sink covering at least portions of the first semiconductor structure, the second semiconductor structure, and the first substrate; anda thermal interface material layer between the first semiconductor structure and the heat sink and between the second semiconductor structure and the heat sink, the thermal interface material layer including a first thermal interface material segment between the first and second semiconductor structures and a second thermal interface material segment that protrudes beyond the second sidewall, a first distance from a top surface of the first substrate to a lowest point of a ...

INTEGRATED CIRCUIT PACKAGE ELECTRONIC DEVICE

A surface mount electronic device providing an electrical connection between an integrated circuit (IC) and a printed circuit board (PCB) is provided and includes a die and a dielectric material formed to cover portions of the die. Pillar contacts are electrically coupled to electronic components in the die and the pillar contacts extend from the die beyond an outer surface of the die. A conductive ink is printed on portions of a contact surface of the electronic device package and forms electrical terminations on portions of the dielectric material and electrical connector elements that connect an exposed end surface of the pillar contacts to the electrical terminations. 1. A method comprising:placing a die in a carrier, the die having pillar contacts electrically coupled to components in the die where the pillar contacts extend beyond an outer surface of the die;forming a dielectric material in the carrier to cover portions of the die and between the pillar contacts to form an electronic device package;polishing an exposed surface of the pillar contacts to ensure that the pillar contacts are coplanar with the dielectric material and to form contact surface of the electronic device package having exposed pillar contact ends; andprinting conductive ink on portions of the contact surface of the electronic device package to form electrical connector elements connected to the exposed pillar contact ends.2. The method of claim 1 , wherein printing the conductive ink on portions of the contact surface of the electronic device package includes printing electrical terminations on portions of the dielectric material and printing electrical connections from the exposed pillar contact ends to the electrical terminations.3. The method of claim 2 , further comprising printing a passivation layer over the exposed pillar contact ends.4. The method of claim 3 , further comprising applying a finishing conductive material on the electrical terminations of the dielectric material.5. ...

PACKAGE AND METHOD OF MANUFACTURING THE SAME

A package and a method of manufacturing the same are provided. The package includes a first die, a second die, a third die, an encapsulant, and a redistribution layer (RDL) structure. The first die and the second die are disposed side by side. The third die is disposed on the first die and the second die to electrically connect the first die and the second die. The encapsulant laterally encapsulates the first die, the second die, and the third die and fills in a gap between the first die, the second die, and the third die. The RDL structure is disposed on the third die and the encapsulant. 1. A package , comprising:a first die and a second die disposed side by side;a third die disposed on the first die and the second die to electrically connect the first die and the second die;an encapsulant, laterally encapsulating the first die, the second die, and the third die and filling in a gap between the first die, the second die, and the third die; anda redistribution layer (RDL) structure disposed on the third die and the encapsulant.2. The package of claim 1 , further comprising a plurality of first through insulating vias (TIVs) disposed between the first die and the third die claim 1 , and between the second die and the third die claim 1 , wherein the first die and the second die are electrically connected to the third die by the plurality of the first TIVs.3. The package of claim 2 , further comprising a plurality of second TIVs disposed on the first die and the second die and aside the third die claim 2 , wherein the first die and the second die are electrically connected to the RDL structure by the plurality of second TIVs.4. The package of claim 3 , wherein a height of the plurality of first TIVs is less than a height of the plurality of second TIVs.5. The package of claim 1 , wherein the third die comprises a plurality of through semiconductor vias (TSVs) to electrically connect the first die and the RDL structure and electrically connect the second die and the ...

PROTRUDING SN SUBSTRATE FEATURES FOR EPOXY FLOW CONTROL

Embodiments disclosed herein include electronic packages with underfill flow control features. In an embodiment, an electronic package comprises a package substrate and a plurality of interconnects on the package substrate. In an embodiment, a die is coupled to the package substrate by the plurality of interconnects and a flow control feature is adjacent on the package substrate. In an embodiment, the flow control feature is electrically isolated from circuitry of the electronic package. In an embodiment, the electronic package further comprises an underfill surrounding the plurality of interconnects and in contact with the flow control feature. 1. An electronic package , comprising:a package substrate;a plurality of interconnects on the package substrate;a die coupled to the package substrate by the plurality of interconnects;a flow control feature adjacent on the package substrate, wherein the flow control feature is electrically isolated from circuitry of the electronic package; andan underfill surrounding the plurality of interconnects and in contact with the flow control feature.2. The electronic package of claim 1 , wherein the flow control feature comprises:a plurality of substantially parallel lines.3. The electronic package of claim 2 , wherein the plurality of substantially parallel lines run in a direction substantially parallel to a direction of flow of the underfill.4. The electronic package of claim 2 , wherein the plurality of substantially parallel lines run in a direction substantially orthogonal to a direction of flow of the underfill.5. The electronic package of claim 1 , wherein the flow control feature comprises first lines and second lines claim 1 , wherein the first lines are substantially orthogonal to the second lines.6. The electronic package of claim 1 , wherein a first flow control feature is adjacent to a first edge of the die and a second flow control feature is adjacent to a second edge of the die claim 1 , wherein the first edge is ...

Wafer-level stack chip package and method of manufacturing the same

A semiconductor product in the form of a stack chip package and a method of manufacturing the same, where a plurality of semiconductor chips are stacked one on another so as to enable the exchange of electrical signals between the semiconductor chips, and where a conductive layer is included for inputting and outputting signals to and from individual chips. A stack chip package having a compact size may, for example, be manufactured by stacking, on a first semiconductor chip, a second semiconductor chip having a smaller surface area by means of interconnection structures so as to enable the exchange of electrical signals between the first and second semiconductor chips, and by using a conductive layer for inputting and outputting signals to and from individual semiconductor chips, in lieu of a thick substrate. Furthermore, heat dissipation effects can be enhanced by the addition of a heat dissipation unit.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device including a relatively thin interposer excluding a through silicon hole and a manufacturing method thereof are provided. The method includes forming an interposer on a dummy substrate. The forming of the interposer includes, forming a dielectric layer on the dummy substrate, forming a pattern and a via on the dielectric layer, and forming a seed layer at the pattern and the via of the dielectric layer and forming a redistribution layer and a conductive via on the seed layer. A semiconductor die is connected with the conductive via facing an upper portion of the interposer, and the semiconductor die is encapsulated with an encapsulant. The dummy substrate is removed from the interposer. A bump is connected with the conductive via facing a lower portion of the interposer. 120-. (canceled)21. A semiconductor device comprising: a first interposer side;', 'a second interposer side opposite the first interposer side;', 'a first dielectric layer at the first interposer side;', 'a first conductive via that extends through at least the first dielectric layer;', 'a second conductive via at the second interposer side; and', 'a redistribution structure in contact with the first dielectric layer and electrically connected to the first conductive via and the second conductive via;, 'an interposer comprising a first die side that faces away from the first interposer side;', 'a second die side that faces toward the first interposer side and comprises a die connection terminal that is coupled to the first conductive via; and', 'a lateral die side that extends between the first die side and the second die side;, 'a semiconductor die comprising the encapsulating material comprises an uppermost surface facing away from the interposer, a lowermost surface facing the interposer, and a lateral surface that extends entirely between the uppermost surface and the lowermost surface;', 'no portion of the encapsulating material is substantially vertically higher than the ...

THREE-DIMENSIONAL INTEGRATED CIRCUIT STRUCTURES AND METHODS OF MANUFACTURING THE SAME

Three-dimensional integrated circuit structures and methods of forming the same are disclosed. One of the three-dimensional integrated circuit structures includes a first die, a plurality of second dies and a dielectric structure. The second dies are bonded to the first die. The dielectric structure is disposed between the second dies. The dielectric structure includes a first dielectric layer and a second dielectric layer. The first dielectric layer has a sidewall and a bottom, a first surface of the sidewall and a first surface of the bottom are in contact with the second dielectric layer and form a first angle. A second angle smaller than the first angle is formed by a second surface of the sidewall and a second surface of the bottom. 1. A three-dimensional integrated circuit structure , comprising:a first die;a plurality of second dies, bonded to the first die; anda dielectric structure, disposed between the plurality of second dies, comprising a first dielectric layer and a second dielectric layer, wherein the first dielectric layer has a sidewall and a bottom, a first surface of the sidewall and a first surface of the bottom are in contact with the second dielectric layer and form a first angle, and a second angle smaller than the first angle is formed by a second surface of the sidewall and a second surface of the bottom.2. The three-dimensional integrated circuit structure according to claim 1 , wherein a distance between the first surface of the sidewall and one of the second dies increases as the first surface becomes closer to the bottom.3. The three-dimensional integrated circuit structure according to claim 1 , wherein a thickness between the first and second surfaces of the sidewall increases as the first and second surfaces become closer to the bottom.4. The three-dimensional integrated circuit structure according to claim 1 , wherein the first dielectric layer is disposed between the second dielectric layer and the plurality of second dies.5. The ...

SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF

A semiconductor package structure and a method for making a semiconductor package. As non-limiting examples, various aspects of this disclosure provide various semiconductor package structures, and methods for making thereof, that comprise a connect die that routes electrical signals between a plurality of other semiconductor die. 1. An electronic device comprising:a signal redistribution structure (SRS) comprising a top SRS side, a bottom SRS side, and a plurality of lateral SRS sides, where the signal redistribution structure is coreless;a lower electronic component (LEC) comprising a top LEC side, a bottom LEC side, and a plurality of lateral LEC sides, where the top LEC side is coupled to the bottom SRS side;a vertical interconnect structure coupled to the bottom SRS side at a position that is laterally offset from the lower electronic component;an LEC interconnect structure that is coupled to the top LEC side and to the bottom SRS side, such that the lower electronic component is electrically coupled to the signal redistribution structure through at least the LEC interconnect structure;a semiconductor die comprising a top die side, a bottom die side, and a plurality of lateral die sides;a first die interconnect structure coupled to the top SRS side and to the bottom die side, such that the semiconductor die is electrically coupled to the vertical interconnect structure; anda second die interconnect structure coupled to the top SRS side and to the bottom die side, such that the semiconductor die is electrically coupled to the lower electronic component.2. The electronic device of claim 1 , wherein:the semiconductor die is electrically coupled to the vertical interconnect structure through at least the first die interconnect structure and the signal redistribution structure; andthe semiconductor die is electrically coupled to the lower electronic component through at least the second die interconnect structure, the signal redistribution structure, and the LEC ...

CIRCUIT SUBSTRATE, SEMICONDUCTOR PACKAGE AND PROCESS FOR FABRICATING THE SAME

A circuit substrate has the following elements. A stacked circuit structure has a first surface and a second surface opposite thereto surface. A first patterned inner conductive layer is disposed on the first surface and has multiple pads. A first patterned outer conductive layer is disposed on the patterned inner conductive layer and has multiple conductive pillars, wherein each of the first conductive pillar is located on the corresponding first pad. The first dielectric layer covers the first surface, the first patterned inner conductive layer and the first patterned outer conductive layer, and has multiple first concaves, wherein the first concave exposes the top and side of the corresponding first conductive pillar. A semiconductor package structure applied the above circuit substrate and a process for fabricating the same are also provided here. 1. A circuit substrate , comprising:a stacked circuit structure having a first surface and a second surface opposite to the first surface;a first patterned inner conductive layer disposed on the first surface and having a plurality of first pads;a first patterned outer conductive layer disposed on the first patterned inner conductive layer and having a plurality of first conductive pillars, wherein each of the first conductive pillars is located on the corresponding first pad;a first dielectric layer covering the first surface, the first patterned inner conductive layer and the first patterned outer conductive layer and having a plurality of first concaves, wherein each of the first concaves exposes a top and a side of the corresponding first conductive pillar, and the top and the side of the first conductive pillar are exposed for directly soldering a chip;a second patterned inner conductive layer disposed on the second surface and having a plurality of second pads;a second patterned outer conductive layer disposed on the second patterned inner conductive layer and having a plurality of second conductive pillars, ...

CIRCUIT PACKAGE

A circuit package panel containing a packaging of epoxy mold compounds and a circuit device in the packaging, wherein the packaging comprises, at least one hybrid layer of a first epoxy mold compound and a second epoxy mold compound of a different composition. 1. A circuit package panel comprisinga front and back face,a packaging of epoxy mold compounds, anda circuit device in the packaging, whereinthe packaging comprises, parallel to the front face, at least one hybrid layer of a first epoxy mold compound and next to it a second epoxy mold compound of a different composition.2. The circuit package of comprising an array of circuit devices.3. The circuit package of whereinthe circuit device extends in the first compound, and,the second compound surrounds the first compound.54. The circuit package of claim wherein the first compound extends under the circuit device and under the second compound.6. The circuit package of wherein the second compound has a higher CTE than the first compound.7. The circuit package of wherein the first and second compounds have a different CTE (Coefficient of Thermal Expansion) and the circuit device has a lower CTE than the compounds8. The circuit package of wherein the second compound has a lower weight percentage of fillers than the first compound.9. The circuit package of wherein the second compound has finer fillers claim 1 , on average claim 1 , than the first compound.10. The circuit package of whereinthe circuit device is a fluidic device comprising a fluid channel array, andthe second compound comprises fluid holes to deliver fluid to the circuit device.11. The circuit package of wherein the circuit devices each comprise relatively thin slivers having nozzle arrays of at least 300 nozzles per inch and having a width:length ration of at least 1:25.12. A method of compression molding a circuit package claim 10 , comprisingdepositing on a carrier a first epoxy mold compound and a second epoxy mold compound each of a different ...

FAN-OUT PACKAGE STRUCTURE

A semiconductor package structure including a redistribution layer (RDL) structure having a first surface and a second surface opposite thereto is provided. The RDL structure includes an inter-metal dielectric (IMD) layer and a first conductive layer disposed at a first layer-level of the IMD layer. A molding compound covers the first surface of the RDL structure. A first semiconductor die is disposed over the second surface of the RDL structure and electrically coupled to the RDL structure. A plurality of bump structures is disposed over the second surface of the RDL structure and electrically coupled to the RDL structure. 1. A semiconductor package structure , comprising:a redistribution layer (RDL) structure having a first surface and a second surface opposite thereto, wherein the RDL structure comprises an inter-metal dielectric (IMD) layer and a first conductive layer disposed at a first layer-level of the IMD layer;a molding compound covering the first surface of the RDL structure;a first semiconductor die disposed over the second surface of the RDL structure and electrically coupled to the RDL structure; anda plurality of bump structures disposed over the second surface of the RDL structure and electrically coupled to the RDL structure.2. The semiconductor package structure as claimed in claim 1 , further comprising an underfill layer interposed between the second surface of the RDL structure and the first semiconductor die.3. The semiconductor package structure as claimed in claim 1 , further comprising a second semiconductor die and an electronic component disposed within the molding compound claim 1 , arranged side-by-side claim 1 , and electrically coupled to the RDL structure.4. The semiconductor package structure as claimed in claim 3 , wherein the electronic component comprises a capacitor claim 3 , an inductor claim 3 , a resistor claim 3 , or a combination thereof.5. The semiconductor package structure as claimed in claim 3 , wherein the second ...

SEMICONDCUTOR STRUCTURE AND SEMICONDUCTOR MANUFACTURING PROCESS THEREOF

A semiconductor structure has an integrated circuit component, a conductive contact pad, a seal ring structure, a conductive via, a ring barrier, and a mold material. The conductive contact pad is disposed on and electrically connected with the integrated circuit component. The seal ring structure is disposed on the integrated circuit component and surrounding the conductive contact pad. The conductive via is disposed on and electrically connected with the conductive contact pad. The ring barrier is disposed on the seal ring structure. The ring barrier surrounds the conductive via. The mold material covers side surfaces of the integrated circuit component. A semiconductor manufacturing process is also provided. 1. A semiconductor structure comprising:an integrated circuit;a conductive contact pad, disposed on and electrically connected with the integrated circuit;a seal ring structure, disposed on the integrated circuit and surrounding the conductive contact pad;a conductive via, disposed on and electrically connected with the conductive contact pad;a ring barrier, disposed on top of the seal ring structure, wherein the seal ring structure and the ring barrier are distributed within a first side and second side of the integrated circuit, and the ring barrier surrounds the conductive via; anda mold material covering side surfaces of the integrated circuit.2. The semiconductor structure as claimed in claim 1 , wherein a height of the conductive via is substantially the same as a height of the ring barrier.3. The semiconductor structure as claimed in claim 1 , further comprising:a first passivation layer, disposed on the integrated circuit, wherein the conductive contact pad and seal ring structure are disposed on the first passivation layer, and the first passivation layer comprises at least one opening exposing the integrated circuit; anda second passivation layer, disposed on the first passivation layer and covering a portion of the seal ring structure and a portion ...

Vertical Memory Devices and Methods of Manufacturing the Same

Vertical memory devices, and methods of manufacturing the same, include providing a substrate including a cell array region and a peripheral circuit region, forming a mold structure in the cell array region, forming an opening for a common source line passing through the mold structure and extending in a first direction perpendicular to a top surface of the substrate, forming a first contact plug having an inner sidewall delimiting a recessed region in the opening for the common source line, and forming a common source bit line contact electrically connected to the inner sidewall of the first contact plug. 1. A method of manufacturing a vertical memory device , the method comprising:providing a substrate comprising a cell array region and a peripheral circuit region;forming a mold structure in the cell array region;forming an opening for a common source line passing through the mold structure and extending in a first direction perpendicular to a top surface of the substrate;forming a first contact plug having an inner sidewall delimiting a recessed region in the opening for the common source line; andforming a common source bit line contact electrically connected to the inner sidewall of the first contact plug.2. The method of claim 1 , wherein the forming the first contact plug comprises forming an open passage of the recessed region in the vicinity of an entrance of the opening for the common source line claim 1 , andwherein the method further comprises after forming the first contact plug, exhausting a gas in the recessed region outside the recessed region through the open passage.3. The method of claim 2 , wherein the forming the opening for the common source line comprises forming the opening for the common source line so as to extend in a second direction perpendicular to the first direction claim 2 , andwherein the forming the first contact plug comprises forming the first contact plug such that the first contact plug extends in the second direction.4. The ...

Method for preparing semiconductor package structure

The present disclosure provides a method for preparing a semiconductor package structure. The method includes the following steps. A first die is provided. A second die including a plurality of first conductors is bonded to the first die. A plurality of second conductors are disposed on the first die. A molding is disposed to encapsulate the first die, the second die and the plurality of second conductors. An RDL is disposed on the second die and the molding. A plurality of connecting structures are disposed on the RDL.

PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

A package structure including a first die, an encapsulant, a first circuit structure, a second circuit structure, a conductive connector, a second die, and a filler is provided. The encapsulant covers the first die and has a first surface and a second surface opposite to each other. The first circuit structure is disposed on the first surface. The second circuit structure is disposed on the second surface. The conductive connector penetrates the encapsulant. The second die is disposed on the second circuit structure. The second die has an optical signal transmission area. The filler is disposed between the second die and the second circuit structure. An upper surface of the second circuit structure has a groove. The upper surface includes a first area and a second area disposed on opposite sides of the groove. The filler directly contacts the first area. The filler is disposed away from the second area. 1. A package structure , comprising:a first die;an encapsulant, covering the first die, and having a first molding surface and a second molding surface opposite to the first molding surface;a first redistributed circuit structure, disposed on the first molding surface of the encapsulant;a second redistributed circuit structure, disposed on the second molding surface of the encapsulant and electrically connected to the first die;a conductive connector, penetrating through the encapsulant and electrically connected to the first redistributed circuit structure and the second redistributed circuit structure;a second die, disposed on the second redistributed circuit structure and electrically connected to the second redistributed circuit structure, wherein the second die has an optical signal transmission area; and an upper surface of the second redistributed circuit structure has a groove, and the upper surface comprises a first area and a second area disposed on two opposite sides of the groove;', 'the filler directly contacts the first area; and', 'the filler is ...

POLYMER RESIN AND COMPRESSION MOLD CHIP SCALE PACKAGE

A method for fabricating a chip scale package, comprising: providing a wafer; applying a polymer resin on at least part of a first surface of the wafer and to one or more sides of the wafer; and applying a compression mold on at least part of a second surface of the wafer and to one or more sides of the wafer, said first and second surfaces opposing each other. 1. A chip scale package , comprising:a semiconductor die having a top surface, a bottom surface, and side surfaces;a metallization layer coupled on the top surface of the semiconductor die; anda compression mold coupled on the bottom surface of the die, on the side surfaces of the die, and on a portion of the top surface of the die,wherein a portion of the compression mold of the die forms a strip along at least part of the perimeter of the top surface; andwherein a portion of the compression mold covering the portion of the top surface of the die is over-mold.2. The chip scale package of claim 1 , wherein the strip has an average width between 40 and 60 micrometers claim 1 , inclusive.3. The chip scale package of claim 1 , wherein the strip occupies between 20 percent and 40 percent claim 1 , inclusive claim 1 , of a total area of the top surface excluding metallization.4. The chip scale package of claim 1 , wherein the compression mold is made of a material selected from the group consisting of: polyamides claim 1 , polyimides claim 1 , polyamide-imides claim 1 , polyphenylene sulfide (PPS) claim 1 , polyether ether ketone (PEEK) claim 1 , and polyester fiberglass resin.5. The chip scale package of claim 1 , wherein the top and bottom surfaces oppose each other.6. A chip scale package claim 1 , comprising:a semiconductor die having a first largest planar surface, a second largest planar surface, and side surfaces across a thickness between the first largest planar surface and the second largest planar surface;a metallization layer coupled on the first largest planar surface of the semiconductor die; anda ...

BONDING STRUCTURE FOR SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

A method of manufacturing a bonding structure includes (a) providing a substrate, wherein the substrate includes a top surface and at least one bonding pad disposed adjacent to the top surface of the substrate, at least one bonding pad having a sloped surface with a first slope; (b) providing a semiconductor element, wherein the semiconductor element includes at least one pillar, and at least one pillar has a sidewall with a second slope, wherein the absolute value of the first slope is smaller than the absolute value of the second slope; and (c) bonding at least one pillar to a portion of the sloped surface of corresponding ones of the at least one bonding pad. 1. A method of manufacturing a bonding structure , comprising:(a) providing a substrate, wherein the substrate includes a top surface and at least one bonding pad disposed adjacent to the top surface of the substrate, at least one bonding pad having a sloped surface with a first slope;(b) providing a semiconductor element, wherein the semiconductor element includes at least one pillar, and at least one pillar has a sidewall with a second slope, wherein the absolute value of the first slope is smaller than the absolute value of the second slope; and(c) bonding at least one pillar to a portion of the sloped surface of corresponding ones of the at least one bonding pad.2. The method of claim 1 , wherein in (a) claim 1 , a space defined by the sloped surface of at least one bonding pad has a maximum width and a minimum width claim 1 , and in (b) claim 1 , a width of a corresponding one of the at least one pillar is greater than the minimum width of the space and less than the maximum width of the space.3. The method of claim 1 , wherein in (c) claim 1 , a gap is formed between the sidewall of the at least one pillar and the sloped surface of a corresponding bonding pad.4. The method of claim 1 , wherein in (b) claim 1 , at least one pillar further has a top surface and an edge portion claim 1 , wherein the edge ...

TURN-OFF POWER SEMICONDUCTOR DEVICE WITH IMPROVED CENTERING AND FIXING OF A GATE RING, AND METHOD FOR MANUFACTURING THE SAME

The present application relates to a turn-off power semiconductor device having a wafer with an active region and a termination region surrounding the active region, a rubber ring as an edge passivation for the wafer and a gate ring placed on a ring-shaped gate contact on the termination region for contacting the gate electrodes of a thyristor cell formed in the active region of the wafer. In the turn-off power semiconductor device, the outer circumferential surface of the gate ring is in contact with the rubber ring to define the inner border of the rubber ring. The area consumed by the ring-shaped gate contact on the termination or edge region can be minimized. The upper surface of the gate ring and the upper surface of the rubber ring form a continuous surface extending in a plane parallel to the first main side of the wafer. 1. Turn-off power semiconductor device comprising:a wafer having a first main side, a second main side parallel to the first main side and extending in a lateral direction, an active region and a termination region laterally surrounding the active region;at least one thyristor cell in the active region between the first main side and the second main side, the at least one thyristor cell comprising in the order from the first main side to the second main side:(a) a first cathode electrode;(b) a cathode semiconductor layer of a first conductivity type;(c) a base semiconductor layer of a second conductivity type different from the first conductivity type;(d) a drift semiconductor layer of the first conductivity type;(e) an anode semiconductor layer of the second conductivity type;(f) a first anode electrode,wherein the at least one thyristor cell further comprises a gate electrode which is arranged lateral to the cathode semiconductor layer and contacting the base semiconductor layer, andwherein the at least one gate electrode of the at least one thyristor cell is electrically connected to a ring-shaped contact for contacting the at least one ...

SHIELDED FAN-OUT PACKAGED SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING

Several aspects of the present technology are directed toward fan-out packaged semiconductor devices having an integrated shield to protect against electromagnetic interference and methods of manufacturing such devices. The shield can be constructed by forming a conductive wall on a redistribution structure and disposing a conductive cap on an upper surface of an encapsulant. The conductive wall and the conductive cap are electrically connected to each other. By forming the conductive wall directly on the redistribution structure and separately disposing the conductive cap onto an upper surface of the encapsulant, an electromagnetic shield can be readily formed using wafer-level or panel-level processing techniques that are efficient and cost-effective. Several embodiments of semiconductor devices in accordance with the present technology accordingly shield the integrated circuitry of semiconductor dies from electromagnetic interference. 1. A packaged semiconductor device , comprising:a redistribution structure having first side, a second side, a dielectric formation having a thickness from the first side to the second side, die contacts at the first side of the redistribution structure, at least one shield contact at the first side of the redistribution structure, and ball pads at the second side of the redistribution structure;a semiconductor die mounted on the first side of the redistribution structure, wherein the semiconductor die has an outer perimeter;a conductive wall on the first side of the redistribution structure spaced laterally apart from the outer perimeter of the semiconductor die and comprising a printed conductive material or reflowed conductive paste, wherein the conductive wall is electrically coupled to the shield contact, extends around at least a portion of the outer perimeter of the semiconductor die, and has a planar top surface spaced apart from the first side of the redistribution structure;an encapsulant covering at least a portion of the ...

Fabrication Process and Structure of Fine Pitch Traces for a Solid State Diffusion Bond on Flip Chip Interconnect

A method to produce a semiconductor package or system-on-flex package comprising bonding structures for connecting IC/chips to fine pitch circuitry using a solid state diffusion bonding is disclosed. A plurality of traces is formed on a substrate, each respective trace comprising at least four different conductive materials having different melting points and plastic deformation properties, which are optimized for both diffusion bonding of chips and soldering of passives components. 1. A semiconductor package comprising:a flexible substrate;a plurality of traces formed on said flexible substrate, each respective trace comprising at least four different conductive materials having different melting points and plastic deformation properties constructed in four layers, which are optimized for both diffusion bonding and soldering of passive components wherein a topmost layer of each said trace comprises tin; andat least one die mounted on said substrate wherein there is a diffusion bond between at least one of said plurality of traces and said at least one die.2. The semiconductor package according to claim 1 , wherein said diffusion bond is via a gold plated bump or a gold stud bump on said die.3. The package according to claim 1 , wherein said topmost layer of each said trace comprises tin having a purity above 99% claim 1 , a hardness of below 10 HV claim 1 , and minimum thickness of 0.01 preferably at 0.1 μm.4. The semiconductor package according to claim 3 , wherein a second layer of each of said traces next closest to said diffusion bond comprises Cu—Sn intermetallic layer and a minimum thickness of 0.01 μm claim 3 , preferably at 0.35 μm.5. The semiconductor package according to claim 4 , wherein a third layer of each of said traces comprises copper having a purity of more than 99.9% claim 4 , a hardness of about 100 HV claim 4 , and a thickness of between about 2 μm and 25 μm.6. The semiconductor package according to claim 5 , wherein an underlying layer of each ...

MICRO-TRENCHING MOLD INTERFACE IN A POP PACKAGE

Embodiments disclosed herein include an electronics package. In an embodiment, the electronics package comprises a package substrate and a die on the package substrate. In an embodiment, a mold layer is positioned over the package substrate. In an embodiment, the electronics package further comprises through-mold interconnects through the mold layer, and a trench that extends at least partially into the mold layer. 1. An electronics package , comprising:a package substrate;a die on the package substrate;a mold layer over the package substrate;through-mold interconnects through the mold layer; anda trench into the mold layer, wherein the trench extends at least partially into the mold layer.2. The electronics package of claim 1 , further comprising:a fiducial on the package substrate.3. The electronics package of claim 2 , wherein the trench extends from the fiducial to one of the through-mold interconnects.4. The electronics package of claim 3 , further comprising a second trench that extends from the fiducial to a second one of the through-mold interconnects.5. The electronics package of claim 1 , wherein the trench extends from an edge of the mold layer towards the die.6. The electronics package of claim 5 , wherein the trench extends from the edge of the mold layer past a plurality of rows of through-mold interconnects.7. The electronics package of claim 1 , wherein the trench is positioned between the die and a plurality of through-mold interconnects.8. The electronics package of claim 8 , further comprising a second trench positioned between the through-mold interconnects and an edge of the electronics package.9. The electronics package of claim 1 , wherein the trench has non-vertical sidewalls.10. The electronics package of claim 1 , wherein the trench intersects with a through-mold interconnect opening.11. The electronics package of claim 1 , further comprising:an interposer over the mold layer, wherein the interposer is electrically coupled to the through- ...

Encapsulated Emissive Element for Fluidic Assembly

A method is provided for fabricating an encapsulated emissive element. Beginning with a growth substrate, a plurality of emissive elements is formed. The growth substrate top surface is conformally coated with an encapsulation material. The encapsulation material may be photoresist, a polymer, a light reflective material, or a light absorbing material. The encapsulant is patterned to form fluidic assembly keys having a profile differing from the emissive element profiles. In one aspect, prior to separating the emissive elements from the handling substrate, a fluidic assembly keel or post is formed on each emissive element bottom surface. In one variation, the emissive elements have a horizontal profile. The fluidic assembly key has horizontal profile differing from the emissive element horizontal profile useful in selectively depositing different types of emissive elements during fluidic assembly. In another aspect, the emissive elements and fluidic assembly keys have differing vertical profiles useful in preventing detrapment. 1. An encapsulated emissive element comprising:an emissive element having a profile and comprising a top surface, a bottom surface, sidewall surfaces between the top and bottom surfaces, and a pair of electrical contacts; and,a fluidic assembly key at least partially encapsulating the emissive element to form a profile, different than the emissive element profile, made from a material selected from the group consisting of photoresist, light reflective, magnetic, and light absorbing materials.2. The encapsulated emissive element of wherein the emissive element top surface is substantially planar in a horizontal orientation; and claim 1 ,wherein the emissive element has a horizontal profile and the fluidic assembly key has a differing horizontal profile, as defined from a plan view vantage orthogonal to the emissive element top surface and sidewall surfaces.3. The encapsulated emissive element of wherein the emissive element is capable of ...

SEMICONDUCTOR PACKAGE STRESS BALANCE STRUCTURES AND RELATED METHODS

Implementations of a semiconductor package may include a semiconductor die including a first side and a second side where the first side of the semiconductor die includes one or more electrical contacts; a layer of metal coupled to the second side of the semiconductor; and a stress balance structure coupled to one of the layer of metal or around the one or more electrical contacts. 1. A semiconductor package , comprising:a semiconductor die comprising a first side and a second side, the first side of the semiconductor die comprising one or more electrical contacts;a layer of metal coupled to the second side of the semiconductor; anda stress balance structure coupled to one of the layer of metal or around the one or more electrical contacts.2. The package of claim 1 , wherein the stress balance structure coupled around the one or more electrical contacts comprises an organic material covering at least the first side of the semiconductor die wherein the one or more electrical contacts extend through one or more openings in the organic material.3. The package of claim 2 , wherein the one or more electrical contacts comprise at least two metal-containing layers coupled to the one or more electrical contacts.4. The package of claim 2 , wherein the organic material is a mold compound.5. The package of claim 1 , wherein the semiconductor die comprises a thickness between 0.1 microns and 125 microns.6. The package of claim 1 , wherein the stress balance structure coupled to the layer of metal comprises one of silicon claim 1 , a ceramic claim 1 , a polymer material claim 1 , or any combination thereof.7. The package of claim 6 , wherein a thickness of the stress balance structure is between 1 micron to 600 microns.8. A method of forming semiconductor packages claim 6 , comprising:providing a semiconductor substrate comprising a plurality of semiconductor die, the semiconductor substrate comprising a first side and a second side;forming one or more electrical contacts on the ...

Integrated Circuit Package Pad and Methods of Forming

A semiconductor device and method for forming the semiconductor device is provided. The semiconductor device includes an integrated circuit having through vias adjacent to the integrated circuit die, wherein a molding compound is interposed between the integrated circuit die and the through vias. The through vias have a projection extending through a patterned layer, and the through vias may be offset from a surface of the patterned layer. The recess may be formed by selectively removing a seed layer used to form the through vias. 1. A method of manufacturing a semiconductor device , the method comprising:forming a first insulating layer over a carrier substrate;forming a second insulating layer over the first insulating layer;forming an opening through the second insulating layer;forming a conductive structure directly on an upper surface of the second insulating layer, the conductive structure extending through the opening;placing an integrated circuit die over the second insulating layer, the integrated circuit die having contact pads facing away from the carrier substrate; andforming a molding compound over the second insulating layer, the molding compound extending along sidewalls of the integrated circuit die and the conductive structure.2. The method of claim 1 , wherein a smallest width of the conductive structure in the molding compound is greater than a largest width of the conductive structure in the second insulating layer.3. The method of further comprising:removing the carrier substrate, exposing the first insulating layer; andremoving the first insulating layer, exposing the second insulating layer and the conductive structure.4. The method of further comprising claim 3 , after removing the first insulating layer claim 3 , recessing the second insulating layer claim 3 , wherein after recessing the second insulating layer the conductive structure protrudes from a recessed surface of the second insulating layer.5. The method of claim 4 , wherein the ...

ENCAPSULATED PACKAGE WITH CARRIER, LAMINATE BODY AND COMPONENT IN BETWEEN

A package and method of manufacturing a package is disclosed. In one example, the method comprises mounting at least one electronic component on a carrier, attaching a laminate body to the mounted at least one electronic component, and filling at least part of spaces between the laminate body and the carrier with mounted at least one electronic component with an encapsulant. 1. A package , comprising:a carrier;at least one electronic component mounted on the carrier;a laminate body attached to the at least one electronic component; andan encapsulant filling at least part of spaces between the laminate body and the carrier with the mounted at least one electronic component in between.2. The package according to claim 1 , wherein the carrier is a structured plate-shaped carrier claim 1 , in particular comprises a leadframe or a patterned printed circuit board.3. The package according to claim 1 , wherein the laminate body comprises a sheet comprising a dielectric material claim 1 , in particular comprises or consists of at least one of the group consisting of a prepreg layer claim 1 , and a Resin Coated Copper sheet.4. The package according to claim 1 , comprising one of the following features:the at least one electronic component comprises at least one pad exclusively on a main surface facing the carrier;the at least one electronic component comprises at least one pad exclusively on a main surface facing the laminate body;the at least one electronic component comprises at least one pad on a main surface facing the carrier and comprises at least one further pad on another main surface facing the laminate body;the at least one electronic component comprises at least one pad arranged face-up;the at least one electronic component comprises at least one pad arranged face-down.5. The package according to claim 1 , comprising one of the following features:wherein the encapsulant extends vertically beyond, in particular completely covers, a main surface of the carrier ...

PACKAGE STRUCTURE

A package structure includes a redistribution layer having an upper surface and a lower surface opposite to each other, in which the redistribution layer has at least one recess on its lower surface, an electronic element disposed on the upper surface of the redistribution layer, at least one first conductive ball disposed on the at least one recess of the redistribution layer, in which a portion of the at least one first conductive ball is filled into the at least one recess, and a plurality of second conductive balls disposed on the lower surface of the redistribution layer. The height of the first conductive ball is larger than the height of each of the second conductive balls in a direction perpendicular to the lower surface of the redistribution layer. 1. A package structure , comprising:a redistribution layer comprising an upper surface and a lower surface opposite to each other, wherein the lower surface of the redistribution layer has at least one first recess;an electronic element disposed on the upper surface of the redistribution layer;at least one first conductive ball disposed on the at least one first recess of the redistribution layer, wherein a part of the at least one first conductive ball is filled into the at least one first recess; anda plurality of second conductive balls disposed on the lower surface of the redistribution layer;wherein in a direction perpendicular to the lower surface of the redistribution layer, a height of the at least one first conductive ball is larger than a height of each of the second conductive balls.2. The package structure of claim 1 , wherein the electronic element comprises a chip.3. The package structure of claim 1 , wherein the at least one first recess is disposed along an edge of the electronic element in the direction.4. The package structure of claim 3 , wherein the at least one first recess is overlapped with the edge of the electronic element in the direction.5. The package structure of claim 3 , wherein the ...

PRINTED CIRCUIT BOARD AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME

A printed circuit board (PCB) includes a substrate base including at least two chip attach regions spaced apart from one another, a plurality of upper pads disposed in the at least two chip attach regions of the substrate base, an accommodation cavity overlapping a part of each of the at least two chip attach regions and recessed in an upper surface of the substrate base, and at least one spacing groove recessed in the upper surface of the substrate base. The at least one spacing groove is connected to the accommodation cavity, and extends in a region between the at least two chip attach regions. 1. A printed circuit board (PCB) , comprising:a substrate base comprising at least two chip attach regions spaced apart from one another,a plurality of upper pads disposed in the at least two chip attach regions of the substrate base;an accommodation cavity overlapping a part of each of the at least two chip attach regions, wherein the accommodation cavity is recessed in an upper surface of the substrate base; andat least one spacing groove recessed in the upper surface of the substrate base, wherein the at least one spacing groove is connected to the accommodation cavity, and extends in a region between the at least two chip attach regions.2. The PCB of claim 1 , wherein the at least two chip attach regions are spaced apart from one another in a first direction claim 1 , and the at least one spacing groove extends in a second direction substantially perpendicular to the first direction.3. The PCB of claim 2 , wherein the at least one spacing groove comprises a first spacing groove and a second spacing groove that respectively extend from opposite sides of the accommodation cavity in the second direction.4. The PCB of claim 3 , wherein a length of the first spacing groove is about equal to a length of the second spacing groove.5. The PCB of claim 3 , wherein a length of the first spacing groove is different from a length of the second spacing groove.6. The PCB of claim 1 , ...

Semiconductor Structure and Method of Forming

A device package and methods of forming are provided. The device package includes a logic die and a first passivation layer over the logic die. The device package also includes a memory die and a molding compound extending along sidewalls of the logic die and the memory die. The device package also includes a conductive via extending through the molding compound, and a first redistribution layer (RDL) structure over the molding compound. The molding compound extends between a top surface of the memory die and a bottom surface of the first RDL structure. A top surface of the first passivation layer contacts the bottom surface of the first RDL structure. 1. A device package comprising:a logic die, a first passivation layer over the logic die;a memory die,a molding compound extending along sidewalls of the logic die and the memory die;a conductive via extending through the molding compound; anda first redistribution layer (RDL) structure over the molding compound, wherein the molding compound extends between a top surface of the memory die and a bottom surface of the first RDL structure along a line that intersects the memory die and that is parallel to a sidewall of the memory die, and wherein a top surface of the first passivation layer contacts the bottom surface of the first RDL structure.2. The device package of claim 1 , wherein the memory die is a dynamic random access memory (DRAM) die.3. The device package of claim 1 , wherein the first passivation layer comprises polybenzoxazole (PBO).4. The device package of claim 1 , wherein a second passivation layer is disposed along a surface of the memory die claim 1 , the surface of the second passivation layer contacting the molding compound.5. The device package of claim 4 , wherein the first passivation layer comprises a first material claim 4 , the second passivation layer comprises a second material claim 4 , and wherein the first material and the second material are different.6. The device package of claim 1 , ...

SEMICONDUCTOR PACKAGES INCLUDING A PLURALITY OF STACKED DIES

A semiconductor package includes core dies and an encapsulant layer. The core dies are stacked on a base die to leave edge regions of the base die exposed. The encapsulant layer is disposed to cover side surfaces of the core dies and a surface of the exposed edge regions of the base die. The surface of the edge regions of the base die includes a concave/convex-shaped structure which is at least partially filled by the encapsulant layer. 1. A semiconductor package comprising:core dies stacked on a base die to leave edge regions of the base die exposed; andan encapsulant layer disposed to cover side surfaces of the core dies as well as a surface of the exposed edge regions of the base die,wherein the surface of the edge regions of the base die includes a concave/convex-shaped structure which is at least partially filled by the encapsulant layer.2. The semiconductor package of claim 1 , wherein the concave/convex-shaped structure includes concave portions recessed from the surface of the edge regions of the base die and convex portions located between the concave portions to protrude from bottom surfaces of the concave portions.3. The semiconductor package of claim 2 , wherein the concave portions are trenches that extend in a direction parallel to the side surfaces of the core dies in a plan view.4. The semiconductor package of claim 3 , wherein each of the trenches has a straight line shape extending to be parallel to the side surfaces of the core dies in a plan view.5. The semiconductor package of claim 3 , wherein the trenches are parallel with each other.6. The semiconductor package of claim 2 , wherein the encapsulant layer extends into empty spaces of the concave portions to provide protrusions of the encapsulant layer.7. The semiconductor package of claim 1 , wherein the concave/convex-shaped structure includes grid-shaped concave portions which are respectively located at corner portions of the base die claim 1 , in a plan view.8. The semiconductor package of ...

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

A semiconductor package and a manufacturing method are provided. The semiconductor package includes a die, a dummy cube, a stress relaxation layer, an encapsulant and a redistribution structure. The dummy cube is disposed beside the die. The stress relaxation layer covers a top surface of the dummy cube. The encapsulant encapsulates the die and the dummy cube. The redistribution structure is disposed over the encapsulant and is electrically connected to the die. The stress relaxation layer is interposed between the dummy cube and the redistribution structure. 1. A semiconductor package , comprising:a die;a dummy cube, disposed beside the die;a stress relaxation layer, covering a top surface of the dummy cube;an encapsulant encapsulating the die and the dummy cube; anda redistribution structure disposed over the encapsulant and electrically connected to the die,wherein the stress relaxation layer is interposed between the dummy cube and the redistribution structure.2. The semiconductor package of claim 1 , wherein the dummy cube is electrically isolated from the redistribution structure.3. The semiconductor package of claim 1 , wherein the stress relaxation layer comprises a portion of the encapsulant.4. The semiconductor package of claim 1 , wherein the stress relaxation layer comprises a polymeric layer claim 1 , and the polymeric layer is not in physical contact with the redistribution structure.5. The semiconductor package of claim 1 , wherein the stress relaxation layer comprises a first polymeric layer and a second polymeric layer claim 1 , and a material of the first polymeric layer is different from a material of the second polymeric layer.6. The semiconductor package of claim 1 , wherein the stress relaxation layer comprises a polymeric layer extending from the top surface of the dummy cube to the redistribution structure.7. The semiconductor package of claim 6 , wherein a material of the polymeric layer comprises polyimide claim 6 , polybenzooxazole claim 6 ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

An electronic device and a method of making an electronic device. As non-limiting examples, various aspects of this disclosure provide various methods of manufacturing electronic devices, and electronic devices manufactured thereby, that comprise utilizing an adhesive layer to attach an upper electronic package to a lower die and/or utilizing metal pillars for electrically connecting the upper electronic package to a lower substrate, wherein the metal pillars have a smaller height above the lower substrate than the lower die. 120-. (canceled)21. An electronic device comprising:a lower substrate (LS) comprising a top LS side, a bottom LS side, and a lateral LS side between the top LS side and the bottom LS side;a semiconductor die comprising a top die side, a bottom die side coupled to the top LS side, and a lateral die side between the top die side and the bottom die side;a first conductive interconnection structure between the semiconductor die and the lower substrate and electrically connecting the semiconductor die to the lower substrate;an adhesive comprising a top adhesive side, a bottom adhesive side adhered to the top die side, and a lateral adhesive side between the top adhesive side and the bottom adhesive side;an upper substrate (US) comprising a top US side, a bottom US side adhered to the top adhesive side, and a lateral US side between the top US side and the bottom US side;a substrate-to-substrate (S2S) interconnection structure that extends between the top LS side and the bottom US side, where the S2S interconnection structure comprises a solder portion and a non-solder metal portion; anda first encapsulating material of a single continuous material that covers the top LS side, the lateral die side, and the lateral adhesive side, where the first encapsulating material comprises a first top planar surface that is generally coplanar with the top adhesive side.22. The electronic device of claim 21 , wherein the non-solder metal portion of the S2S ...

Method of forming a packaged semiconductor device having enhanced wettable flank and structure

A packaged electronic device includes a substrate having a lead. The lead includes an outward facing side surface having a first height, and an inward facing side surface having a second height that is less than the first height. An electronic device is electrically connected to the lead. A package body encapsulates the electronic device and portions of the lead. The outward facing side surface is exposed through a side surface of the package body, and the inward facing side surface is encapsulated by the package body. A conductive layer is disposed on the outward facing side surface to provide the packaged electronic device with an enhanced wettable flank. In one embodiment, the electronic device is electrically connected to a thick terminal portion having the outward facing side surface. In another embodiment, the electronic device is electrically connected to a thin terminal portion having the inward facing side surface.

INTEGRATED CIRCUIT PACKAGE AND METHOD

A package structure and a method of forming the same are provided. A method includes forming first electrical connectors and second electrical connectors on a first side of an interposer wafer. An integrated circuit die is bonded to the first side of the interposer wafer using the first electrical connectors. A stiffener structure is attached to the first side of the interposer wafer adjacent the integrated circuit die. The stiffener structure covers the second electrical connectors in a plan view. The integrated circuit die and the stiffener structure are encapsulated with a first encapsulant. The interposer wafer and the stiffener structure are singulated to form a stacked structure.

COATED SEMICONDUCTOR DIES

In examples, a chip scale package (CSP) comprises a semiconductor die; a conductive terminal coupled to the semiconductor die; and a non-conductive coat covering a backside of the semiconductor die and a sidewall of the semiconductor die. The non-conductive coat has a thickness of less than 45 microns.

TRIM WALL PROTECTION METHOD FOR MULTI-WAFER STACKING

The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a first substrate having an upper surface and a recessed surface extending in a closed loop around the upper surface. The recessed surface is vertically between the upper surface and a lower surface of the first substrate opposing the upper surface. A first plurality of interconnects are disposed within a first dielectric structure on the upper surface. A dielectric protection layer is over the recessed surface, along a sidewall of the first dielectric structure, and along a sidewall of the first substrate. The first substrate extends from directly below the dielectric protection layer to laterally outside of the dielectric protection layer. 1. An integrated chip structure , comprising:a first substrate having an upper surface and a recessed surface extending in a closed loop around the upper surface, wherein the recessed surface is vertically between the upper surface and a lower surface of the first substrate opposing the upper surface;a first plurality of interconnects disposed within a first dielectric structure on the upper surface; anda dielectric protection layer over the recessed surface, along a sidewall of the first dielectric structure, and along a sidewall of the first substrate, wherein the first substrate extends from directly below the dielectric protection layer to laterally outside of the dielectric protection layer.2. The integrated chip structure of claim 1 , wherein a bottommost surface of the dielectric protection layer rests on the recessed surface of the first substrate.3. The integrated chip structure of claim 1 , wherein the dielectric protection layer continuously extends from along a first outermost sidewall of the first dielectric structure to along an opposing second outermost sidewall of the first dielectric structure.4. The integrated chip structure of claim 1 , wherein the first substrate has a greater maximum ...

SEMICONDUCTOR PACKAGE INCLUDING STACKED SEMICONDUCTOR CHIPS

A semiconductor package may include a base layer; a first semiconductor chip disposed over and spaced apart from the base layer; a second semiconductor chip stack disposed between the base layer and the first semiconductor chip, the second semiconductor chip stack including a plurality of second semiconductor chips that are stacked in a vertical direction; a bridge die stack disposed between the base layer and the first semiconductor chip and disposed to be spaced apart from the second semiconductor chip stack, the bridge die stack including a plurality of bridge dies that are stacked in the vertical direction and electrically connecting the first semiconductor chip and the base layer to supply power; and a vertical interconnector disposed between the base layer and the first semiconductor chip and disposed to be spaced apart from the second semiconductor chip stack and the bridge die stack, the vertical interconnector electrically connecting the first semiconductor chip and the base layer to transmit a signal.

Chip Package Structure, Terminal Device, and Method

A chip package apparatus includes a substrate, a chip on the substrate, and a filling layer on the substrate and surrounding a portion of the chip. The filling layer is made of epoxy molding compound (EMC) and the EMC is white. An electronic device with the chip package apparatus and a method for manufacturing the chip apparatus structure are provided. 1. A chip package apparatus , comprising:a substrate;a chip on the substrate; anda filling layer on the substrate and surrounding a portion of the chip, and the filling layer being made of epoxy molding compound and the epoxy molding compound being white.2. The chip package apparatus of claim 1 , wherein the chip is coupled with the substrate through solder balls claim 1 , and the solder balls are disposed on the substrate in array.3. The chip package apparatus of claim 1 , wherein the chip is coupled with the substrate through conductive wires.4. The chip package apparatus of claim 3 , wherein the chip and the substrate are adhesively coupled through transparent optical adhesive.5. The chip package apparatus of claim 2 , wherein each solder ball has a diameter ranging from 0.22 mm to 0.3 mm or a distance between neighbor solder balls ranges from 0.46 mm to 0.55 mm.6. The chip package apparatus of claim 1 , wherein the chip package apparatus further comprises a reinforcement member disposed on the substrate to avoid the warpage of the substrate.7. The chip package apparatus of claim 6 , wherein the thermal conductivity of the reinforcement member is greater than that of the substrate.8. The chip package apparatus of claim 6 , wherein the substrate and the reinforcement member are adhesively coupled through transparent optical adhesive.9. An electronic device claim 6 , comprising:a white panel glass; anda chip package apparatus attached to the white panel glass, the chip package apparatus comprising:a substrate;a chip on the substrate; anda filling layer on the substrate and surrounding a portion of the chip, and the ...

PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME

A method for forming a package structure is provided. The method for forming a package structure includes bonding a package component to a first surface of a substrate through a plurality of first connectors. The package component includes an interposer, a first semiconductor die and a second semiconductor die over the interposer. The method for forming a package structure also includes forming a dam structure over the first surface of the substrate. The dam structure is around and separated from the package component. The method for forming a package structure further includes forming an underfill layer between the dam structure and the package component, and removing the dam structure after the underfill layer is formed. 1. A method for forming a package structure , comprising:bonding a package component to a first surface of a substrate through a plurality of first connectors, wherein the package component comprises an interposer, a first semiconductor die and a second semiconductor die over the interposer;forming a dam structure over the first surface of the substrate, wherein the dam structure is around and separated from the package component;forming an underfill layer between the dam structure and the package component; andremoving the dam structure after the underfill layer is formed.2. The method for forming the package structure as claimed in claim 1 , wherein forming the package component further comprises:bonding the first semiconductor die and the second semiconductor die to an interposer wafer through a plurality of second connectors;forming a molding compound layer over the interposer wafer and laterally surrounding the first semiconductor die and the second semiconductor die; anddicing the molding compound layer and the interposer wafer to form the package component.3. The method for forming the package structure as claimed in claim 1 , wherein the dam structure comprises a lower portion that adjoins the substrate claim 1 , a middle portion over the ...

SEMICONDUCTOR CHIP INCLUDING LOW-K DIELECTRIC LAYER

A semiconductor chip includes a device layer on a substrate, the device layer including a plurality of semiconductor devices; a wiring structure and a lower inter-wiring dielectric layer each on the device layer, the lower inter-wiring dielectric layer surrounding the wiring structure and having a lower permittivity than silicon oxide; an upper inter-wiring dielectric layer arranged on the lower inter-wiring dielectric layer; an isolation recess arranged along an edge of the substrate, the isolation recess formed on side surfaces of the lower and upper inter-wiring dielectric layers and having a bottom surface at a level equal to or lower than that of a bottom surface of the lower inter-wiring dielectric layer; and a cover dielectric layer covering the side surfaces of the lower and upper inter-wiring dielectric layers and the bottom surface of the isolation recess. 1. A semiconductor chip comprising:a device layer on a substrate, the device layer including a plurality of semiconductor devices;a wiring structure and a lower inter-wiring dielectric layer each on the device layer, the lower inter-wiring dielectric layer surrounding the wiring structure and having a lower permittivity than silicon oxide;an upper inter-wiring dielectric layer on the lower inter-wiring dielectric layer, the upper inter-wiring dielectric layer having a permittivity that is equal to or higher than a permittivity of silicon oxide;an isolation recess along an edge of the substrate, the isolation recess formed on a side surface of the lower inter-wiring dielectric layer and a side surface of the upper inter-wiring dielectric layer, the isolation recess having a bottom surface at a level that is equal to or lower than a level of a bottom surface of the lower inter-wiring dielectric layer; anda cover dielectric layer covering the side surfaces of the lower inter-wiring dielectric layer and the upper inter-wiring dielectric layer and the bottom surface of the isolation recess.2. The ...

Semiconductor Device and Method of Forming Insulating Layers Around Semiconductor Die

A semiconductor device has a semiconductor wafer including a plurality of semiconductor die and a plurality of contact pads formed over a first surface of the semiconductor wafer. A trench is formed partially through the first surface of the semiconductor wafer. An insulating material is disposed over the first surface of the semiconductor wafer and into the trench. A conductive layer is formed over the contact pads. The conductive layer can be printed to extend over the insulating material in the trench between adjacent contact pads. A portion of the semiconductor wafer opposite the first surface of the semiconductor wafer is removed to the insulating material in the trench. An insulating layer is formed over a second surface of the semiconductor wafer and side surfaces of the semiconductor wafer. The semiconductor wafer is singulated through the insulating material in the first trench to separate the semiconductor die. 1. A method of making a semiconductor device , comprising:providing a semiconductor wafer including a contact pad formed over a first surface of the semiconductor wafer;forming a trench into the first surface of the semiconductor wafer;disposing an insulating material over the first surface of the semiconductor wafer and into the trench, wherein the insulating material covers the contact pad;grinding the insulating material over the first surface of the semiconductor wafer to expose the contact pad;backgrinding a second surface of the semiconductor wafer opposite the first surface to expose the insulating material in the trench;forming an insulating layer over the second surface of the semiconductor wafer after backgrinding; anddicing the semiconductor wafer through the trench.2. The method of claim 1 , further including forming a nickel plating over the contact pad prior to disposing the insulating material.3. The method of claim 2 , wherein grinding the insulating material exposes the nickel plating.4. The method of claim 1 , further including ...

Sawing Underfill in Packaging Processes

A method includes bonding a first and a second package component on a top surface of a third package component, and dispensing a polymer. The polymer includes a first portion in a space between the first and the third package components, a second portion in a space between the second and the third package components, and a third portion in a gap between the first and the second package components. A curing step is then performed on the polymer. After the curing step, the third portion of the polymer is sawed to form a trench between the first and the second package components.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

A semiconductor device includes a support body including a mount region, a semiconductor chip disposed on the mount region with a predetermined distance therebetween, a bump disposed between the support body and the semiconductor chip, a wall portion disposed between the support body and the semiconductor chip along a part of an outer edge of the semiconductor chip, and an underfill resin layer disposed between the support body and the semiconductor chip. The underfill resin layer covers an outer side surface of the wall portion. 1. A semiconductor device comprising:a support body including a mount region;a semiconductor chip disposed on the mount region with a predetermined distance therebetween;a bump disposed between the support body and the semiconductor chip;a wall portion disposed between the support body and the semiconductor chip along a part of an outer edge of the semiconductor chip; andan underfill resin layer disposed between the support body and the semiconductor chip,wherein the underfill resin layer covers an outer side surface of the wall portion.2. The semiconductor device according to claim 1 ,wherein the underfill resin layer covers the entire outer side surface of the wall portion.3. The semiconductor device according to claim 1 ,wherein a material of the wall portion is the same as a material of the bump.4. The semiconductor device according to claim 1 ,wherein the outer side surface of the wall portion is positioned on an inward side of the part of the outer edge of the semiconductor chip when viewed in a direction in which the support body and the semiconductor chip face each other.5. The semiconductor device according to claim 1 , a first fillet portion disposed on the mount region along the part of the outer edge of the semiconductor chip, the first fillet portion being positioned on an outward side of the part, and', 'a second fillet portion disposed on the mount region along a remaining part of the outer edge of the semiconductor chip ...

SEMICONDUCTOR DEVICE

A semiconductor device includes a memory component, which is a semiconductor component (a semiconductor chip or a semiconductor package), to be mounted over an upper surface of a wiring substrate. In addition, in the upper surface, a distance between the memory component and a first substrate side of the upper surface is smaller than a distance between the memory component and a second substrate side of the upper surface. In addition, in the upper surface, a dam portion is formed between the memory component and the first substrate side. 1. A semiconductor device comprising:a wiring substrate including a first surface, a first insulating film formed on the first surface, and a dam portion formed on the first insulating film;a first semiconductor component mounted over the first surface of the wiring substrate; anda first resin located between the first insulating film and the first semiconductor component,wherein the first surface includes a first side, and a second side opposite to the first side,wherein a distance between the first semiconductor component and the first side is smaller than a distance between the first semiconductor component and the second side, andwherein the dam portion is formed between the first semiconductor component and the first side, but is not formed between the first semiconductor component and the second side.2. The semiconductor device according to claim 1 ,wherein a plane shape of the first surface has a quadrangle including the first side, the second side, a third side intersecting with each of the first side and the second side, and a fourth side opposite to the third side and intersecting with each of the first side and the second side,wherein a distance between the first semiconductor component and the third side is smaller than a distance between the first semiconductor component and the second side,wherein the wiring substrate includes a first dam portion formed on the first insulating film and formed between the first ...

SHIELDED FAN-OUT PACKAGED SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING

Several aspects of the present technology are directed toward fan-out packaged semiconductor devices having an integrated shield to protect against electromagnetic interference and methods of manufacturing such devices. The shield can be constructed by forming a conductive wall on a redistribution structure and disposing a conductive cap on an upper surface of an encapsulant. The conductive wall and the conductive cap are electrically connected to each other. By forming the conductive wall directly on the redistribution structure and separately disposing the conductive cap onto an upper surface of the encapsulant, an electromagnetic shield can be readily formed using wafer-level or panel-level processing techniques that are efficient and cost-effective. Several embodiments of semiconductor devices in accordance with the present technology accordingly shield the integrated circuitry of semiconductor dies from electromagnetic interference. 1. A method of packaging a semiconductor device , comprising:electrically coupling a semiconductor die to die contacts at a first side of a redistribution structure, wherein the die contacts are electrically coupled to ball pads at a second side of the redistribution structure;forming a contiguous conductive wall around the semiconductor die by depositing a conductive material onto the redistribution structure such that the conductive wall is formed progressively with increasing height, wherein the conductive wall is electrically coupled to at least one shield contact at the first side of the redistribution structure, and wherein the shield contact is electrically coupled to a ball pad at the second side of the redistribution structure;depositing an encapsulant over the semiconductor die, wherein the encapsulant has an upper surface;removing a portion of the encapsulant and a portion of the conductive wall to form the upper surface on the encapsulant over the semiconductor die and a top surface on the conductive wall, wherein the ...

Contact Pad for Semiconductor Device

A device and method of manufacture is provided that utilize a dummy pad feature adjacent contact pads. The contact pads may be contact pads in an integrated fan-out package in which a molding compound is placed along sidewalls of a die and the contact pads extend over the die and the molding compound. The contact pads are electrically coupled to the die using one or more redistribution layers. The dummy pad features are electrically isolated from the contact pads. In some embodiments, the dummy pad features partially encircle the contact pads and are located in a corner region of the molding compound, a corner region of the die, and/or an interface region between an edge of the die and the molding compound. 1. A device comprising:a first redistribution structure, the first redistribution structure comprising a plurality of first conductive features and a plurality of first dielectric layers, wherein the plurality of first conductive features comprises a first contact pad and a first dummy feature formed on a first dielectric layer of the plurality of first dielectric layers, wherein the first dummy feature is electrically decoupled from the first contact pad;a second redistribution structure, the second redistribution structure comprising a plurality of second conductive features and a plurality of second dielectric layers;a die interposed between the first redistribution structure and the second redistribution structure;a molding compound interposed between the first redistribution structure and the second redistribution structure, the molding compound extending along sidewalls of the die;through vias interposed between the first redistribution structure and the second redistribution structure, the through vias electrically coupling the first redistribution structure to the second redistribution structure;a first protective layer over the first dummy feature; andan under bump metallization extending through the first protective layer to the first contact pad, ...

Semiconductor Device and Method of Forming Protective Layer Around Cavity of Semiconductor Die

A semiconductor device has a semiconductor die with a sensor and a cavity formed into a first surface of the semiconductor die to provide access to the sensor. A protective layer is formed on the first surface of the semiconductor die around the cavity. An encapsulant is deposited around the semiconductor die. The protective layer blocks the encapsulant from entering the cavity. With the cavity clear of encapsulant, liquid or gas has unobstructed entry into cavity during operation of the semiconductor die. The clear entry for the cavity provides reliable sensor detection and measurement. The semiconductor die is disposed over a leadframe. The semiconductor die has a sensor. The protective layer can be a film. The protective layer can have a beveled surface. A surface of the leadframe can be exposed from the encapsulant. A second surface of the semiconductor die can be exposed from the encapsulant. 1. A method of making a semiconductor device , comprising:providing a semiconductor die;forming a cavity into a first surface of the semiconductor die;forming a protective layer on the first surface of the semiconductor die around the cavity; anddepositing an encapsulant around the semiconductor die, wherein the protective layer blocks the encapsulant from entering the cavity.2. The method of claim 1 , further including:providing a leadframe; anddisposing the semiconductor die over the leadframe.3. The method of claim 2 , wherein the semiconductor die includes a sensor.4. The method of claim 1 , wherein the protective layer includes a film.5. The method of claim 1 , wherein the protective layer includes a beveled surface.6. The method of claim 1 , wherein a second surface of the semiconductor die is exposed from the encapsulant.7. A method of making a semiconductor device claim 1 , comprising:providing a semiconductor die including a cavity;forming a protective layer around the cavity; anddepositing an encapsulant around the semiconductor die, wherein the protective layer ...

MULTI-FACED MOLDED SEMICONDUCTOR PACKAGE AND RELATED METHODS

Implementations of a method of forming a semiconductor package may include forming electrical contacts on a first side of a wafer, applying a photoresist layer to the first side of the wafer, patterning the photoresist layer, and etching notches into the first side of the wafer using the photoresist layer. The method may include applying a first mold compound into the notches and over the first side of the wafer, grinding a second side of the wafer opposite the first side of the wafer to the notches formed in the first side of the wafer, applying one of a second mold compound and a laminate resin to a second side of the wafer, and singulating the wafer into semiconductor packages. Six sides of each semiconductor package may be covered by one of the first mold compound, the second mold compound, and the laminate resin. 1. A method of forming a semiconductor package comprising:forming a plurality of electrical contacts on a first side of a wafer;applying a photoresist layer to the first side of the wafer;patterning the photoresist layer;etching a plurality of notches into the first side of the wafer using the photoresist layer;applying a first mold compound into the plurality of notches and over the first side of the wafer;grinding a second side of the wafer opposite the first side of the wafer to the plurality of notches formed in the first side of the wafer;applying one of a second mold compound and a laminate resin to a second side of the wafer; andsingulating the wafer into a plurality of semiconductor packages, wherein six sides of each semiconductor package are covered by one of the first mold compound, the second mold compound, and the laminate resin.2. The method of claim 1 , wherein the first mold compound is applied using one of a printer molding technique and a compression molding technique.3. The method of claim 1 , wherein a perimeter of a first side of a die within the package is substantially one of an octagon and a rectangle with rounded corners.4. The ...

INTEGRATED FAN-OUT PACKAGE AND LAYOUT METHOD THEREOF

An integrated fan-out package and a layout method thereof are provided. One integrated fan-out package includes a die and a fan-out substrate. The die has an interconnect structure therein. The fan-out substrate has a redistribution layer structure therein and a plurality of first conductive bumps on a first surface thereof. The first conductive bumps are in physical contact with an interconnect layer of the interconnect structure and a redistribution layer of the redistribution layer structure, and an aspect ratio of the first conductive bumps ranges from about 1/3 to 1/10. 1. An integrated fan-out package , comprising:a die having an interconnect structure therein; anda fan-out substrate having a conductive redistribution layer structure therein and a plurality of first conductive bumps on a first surface thereof,wherein the first conductive bumps are in physical contact with an interconnect layer of the interconnect structure and a conductive redistribution layer of the conductive redistribution layer structure,wherein the fan-out substrate further has a plurality of second conductive bumps on the first surface thereof and aside the first conductive bumps, and the second conductive bumps are not in physical contact with the interconnect layer but in physical contact with the conductive redistribution layer, andwherein the first and second conductive bumps are overlapped with each of the fan-out substrate and the die, and an underfill layer encapsulates the first and second conductive bumps.2. The integrated fan-out package of claim 1 , wherein an aspect ratio of the first conductive bumps ranges from about 1/5 to 1/8.3. The integrated fan-out package of claim 1 , wherein a width of the first conductive bumps is about 5 μm to 10 μm.4. The integrated fan-out package of claim 1 , further comprising a dielectric layer encapsulating the first conductive bumps claim 1 , wherein a dielectric constant of the dielectric layer is equal to or less than about 3.5. The ...

Integrated Circuit Package Pad and Methods of Forming

A semiconductor device and method for forming the semiconductor device is provided. The semiconductor device includes an integrated circuit having through vias adjacent to the integrated circuit die, wherein a molding compound is interposed between the integrated circuit die and the through vias. The through vias have a projection extending through a patterned layer, and the through vias may be offset from a surface of the patterned layer. The recess may be formed by selectively removing a seed layer used to form the through vias. 1. A semiconductor device comprising:an integrated circuit die, the integrated circuit die having a front-side and a backside;molding compound adjacent sidewalls of the integrated circuit die;a through-via extending through the molding compound; anda first layer extending over the molding compound, the through via having a through via projection extending through the first layer.2. The semiconductor device of claim 1 , wherein the through via projection has a width less than a width of the through via extending through the molding compound.3. The semiconductor device of claim 2 , wherein the through via projection protrudes from the first layer.4. The semiconductor device of claim 3 , wherein the through via projection protrudes from the first layer by a distance equal to or greater than 2 μm.5. The semiconductor device of claim 1 , wherein sidewalls of the through via projection are tapered.6. The semiconductor device of claim 1 , further comprising a redistribution structure over a front-side of the integrated circuit die.7. The semiconductor device of claim 6 , wherein the through via projection extends beyond the backside of the integrated circuit die.8. A semiconductor device comprising:an integrated circuit die;molding compound encapsulating the integrated circuit die;a redistribution layer on a first side of the molding compound;a dielectric layer on a second side of the molding compound opposite the first side;an electrical ...

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

A semiconductor package includes a first chip, a second chip, a plurality of first conductive bumps, a plurality of second conductive bumps and an underfill. The first chip includes a first active surface having a chip bonding zone, a plurality of first inner pads in the chip bonding zone and a plurality of first outer pads out of the chip bonding zone. The second chip is flipped on the chip bonding zone. The first conductive bumps are disposed on the first outer pads. The second conductive bumps are disposed between the first inner pads of the first chip and a plurality of second pads of the second chip. The underfill is disposed on the first active surface and covers the second conductive bumps, at least a part of each second chip lateral and at least a part of each first conductive bump. Multiple semiconductor package manufacturing methods are further provided. 1. A semiconductor package , comprising:a first chip, comprising a first active surface, wherein the first active surface comprises a chip bonding zone, a plurality of first inner pads in the chip bonding zone and a plurality of first outer pads out of the chip bonding zone;a second chip, flipping on the chip bonding zone of the first chip, and comprising a second active surface and a plurality of second chip side faces connected to the second active surface, wherein the second active surface comprises a plurality of second pads;a plurality of first conductive bumps, disposed on the first outer pads;a plurality of second conductive bumps, located between the first inner pads and the second pads, each of the first inner pads being electrically connected with the corresponding second pad via the correspondingly second conductive bump;an underfill, disposed on the first active surface, and covering the second conductive bumps, at least a part of each of the second chip side faces and at least a part of each of the first conductive bumps, wherein the underfill comprises a molded underfill (MUF), and the molded ...

Chip carrier, a device and a method

According to various embodiments, a chip carrier may include: a chip supporting region configured to support a chip; a chip contacting region including at least one contact pad for electrically contacting the chip; wherein the chip carrier is thinned in the chip contacting region such that a first thickness of the chip carrier at the at least one contact pad is smaller than a second thickness of the chip carrier in the chip supporting region.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device includes a semiconductor die. A dielectric material surrounds the semiconductor die to form an integrated semiconductor package. There is a contact coupling to the integrated semiconductor package and configured as a ground terminal for the semiconductor package. The semiconductor device further has an EMI (Electric Magnetic Interference) shield substantially enclosing the integrated semiconductor package, wherein the EMI shield is coupled with the contact through a path disposed in the integrated semiconductor package. 1. A semiconductor device , comprising:a semiconductor die;a dielectric material surrounding the semiconductor die to form an integrated semiconductor package;a contact coupling to the integrated semiconductor package and configured as a ground terminal for the semiconductor package; andan EMI (Electric Magnetic Interference) shield substantially enclosing the integrated semiconductor package, wherein the EMI shield is coupled with the contact through a path disposed in the integrated semiconductor package.2. The semiconductor device of claim 1 , wherein the path includes a conductive trace connected to the EMI shield at one end claim 1 , and the conductive trace is a portion of a seal ring of the integrated semiconductor package.3. The semiconductor device of claim 1 , wherein the path includes a conductive through isolation via (TIV) claim 1 , wherein the TIV is extended upwardly from the contact and through the dielectric material.4. The semiconductor device of claim 1 , wherein the path includes a conductive trace embedded in the dielectric material claim 1 , and the conductive trace is connected to the EMI shield at one end and connected to a conductive through isolation via (TIV) at the other end claim 1 , wherein the TIV is connected to the contact.5. The semiconductor device of claim 1 , wherein the path includes a conductive retainer in the dielectric material and coupled to the EMI shield claim 1 , wherein the ...

FLIP CHIP BACKSIDE DIE GROUNDING TECHNIQUES

An integrated circuit is attached to a chip carrier in a flip chip configuration. An electrically conductive conformal layer is disposed on a back surface of the substrate of the integrated circuit. The electrically conductive conformal layer contacts the semiconductor material in the substrate and extending onto, and contacting, a substrate lead of the chip carrier. The substrate lead of the chip carrier is electrically coupled to a substrate bond pad of the integrated circuit. The substrate bond pad is electrically coupled through an interconnect region of the integrated circuit to the substrate of the integrated circuit. A component is attached to the chip carrier and covered with an electrically insulating material. The electrically conductive conformal layer also extends at least partially over the electrically insulating material on the component. The electrically conductive conformal layer is electrically isolated from the component by the electrically insulating material on the component. 1. A semiconductor device , comprising:a chip carrier including a substrate lead located at a front surface of the chip carrier;a component attached to the front surface of the chip carrier;an electrically insulating material disposed on the component; a substrate including semiconductor material, the semiconductor material extending to a back surface of the integrated circuit;', 'an interconnect region on the substrate, the interconnect region extending to a front surface of the integrated circuit;', 'a plurality of n-channel metal oxide semiconductor (NMOS) transistors located within the integrated circuit and a plurality of p-channel metal oxide semiconductor (PMOS) transistors located within the integrated circuit; and', 'a substrate bond pad located at the front surface of the integrated circuit, wherein the front surface of the integrated circuit is facing the front surface of the chip carrier, wherein the substrate bond pad is electrically coupled through the ...

Flip chip backside mechanical die grounding techniques

A semiconductor device includes an integrated circuit attached to a chip carrier in a flip chip configuration. A substrate extends to a back surface of the integrated circuit, and an interconnect region extends to a front surface of the integrated circuit. A substrate bond pad is disposed at the front surface, and is electrically coupled through the interconnect region to the semiconductor material. The chip carrier includes a substrate lead at a front surface of the chip carrier. The substrate lead is electrically coupled to the substrate bond pad. An electrically conductive compression sheet is disposed on the back surface of the integrated circuit, with lower compression tips making electrical contact with the semiconductor material in the substrate. The electrically conductive compression sheet is electrically coupled to the substrate lead of the chip carrier by a back surface shunt disposed outside of the integrated circuit.

Semiconductor package

A semiconductor package including a package substrate, a semiconductor chip on a top surface of the package substrate, a connection terminal between the package substrate and the semiconductor chip, the connection terminal connecting the package substrate to the semiconductor chip, a non-conductive film (NCF) between the package substrate and semiconductor chip, the NCF surrounding the connection terminal and bonding the semiconductor chip to the package substrate, and a side encapsulation material covering a side surface of the semiconductor chip, contacting the package substrate, and including a first portion between a bottom surface of the semiconductor chip and the top surface of the package substrate may be provided. At least a portion of the NCF includes a second portion that horizontally protrudes from the semiconductor chip when viewed, and a portion of the side encapsulation material is in contact with the bottom surface of the semiconductor chip.

Package structure of fingerprint identification chip

The present invention provides a package structure of a fingerprint identification chip, including: a substrate, having a first surface, a second surface and a penetrating opening, the second surface including a groove extending from the penetrating opening and a second metal contact, and the groove being used for accommodating a first metal contact; a fingerprint identification chip having an upper surface and a lower surface, the fingerprint identification being disposed in the penetrating opening and having a bonding pad on the lower surface; a cover plate, fixedly disposed on the first surface of the substrate and covering the upper surface of the fingerprint identification chip; and a flexible print circuit (FPC), disposed on the second surface of the substrate, a surface of the FPC having a third metal contact that corresponds to and is electrically connected to the second metal contact, where bonding pad is electrically connected to the first metal contact through a wire.

INTEGRATED FAN-OUT PACKAGE

An integrated fan-out package includes a first redistribution structure, a die, an insulation encapsulation, and a second redistribution structure. The die is disposed on the first redistribution structure. The insulation encapsulation encapsulates the die. The second redistribution structure is disposed on the die and the insulation encapsulation. At least one of the first redistribution structure and the second redistribution structure includes a dielectric layer, a feed line, and a signal enhancement layer. The feed line is at least partially disposed on the dielectric layer. The signal enhancement layer covers the feed line. The signal enhancement layer has a lower dissipation factor (Df) and/or a lower permittivity (Dk) than the dielectric layer. 1. An integrated fan-out package , comprising:a first redistribution structure;a die, disposed on the first redistribution structure, wherein the die has an active surface and a rear surface opposite to the active surface, and the rear surface of the die is coplanar with the first redistribution structure;an insulation encapsulation encapsulating the die; and a dielectric layer;', 'a feed line, at least partially disposed on the dielectric layer; and', 'a signal enhancement layer covering the feed line, wherein the signal enhancement layer has a lower dissipation factor (Df) and/or a lower permittivity (Dk) than the dielectric layer., 'a second redistribution structure, disposed on the die and the insulation encapsulation, wherein at least one of the first redistribution structure and the second redistribution structure comprises2. The integrated fan-out package according to claim 1 , wherein the signal enhancement layer has the Df ranges between 0.001 and 0.02.3. The integrated fan-out package according to claim 1 , wherein the signal enhancement layer has the Dk ranges between 3 and 4.4. The integrated fan-out package according to claim 1 , wherein the signal enhancement layer and the insulation encapsulation are ...

WAFER EDGE PROTECTION FOR CRACK-FREE MATERIAL GROWTH

A method of fabricating a wafer is disclosed. The method includes forming a protective layer on a device side and a non-device side of a substrate of the wafer. The method further includes removing the protective layer from a center portion of the device side of the substrate while retaining the protective layer in an edge portion of the substrate. The method also includes forming semiconductor layer in the center portion of the device side of the substrate while the protective layer is in the edge portion of the substrate. 1. A method of fabricating a wafer comprising:forming a protective layer on a device side and a non-device side of a substrate of the wafer;removing the protective layer from a center portion of the device side of the substrate while retaining the protective layer in an edge portion of the substrate; andforming a semiconductor layer in the center portion of the device side of the substrate while the protective layer is in the edge portion of the substrate.2. The method of fabricating the wafer of claim 1 , wherein forming the semiconductor layer in the center portion of the device side of the substrate while the protective layer is in the edge portion of the substrate comprises:growing the semiconductor layer in the center portion of the device side of the substrate and on at least part of the protective layer in the edge portion of the substrate, wherein the semiconductor layer in the center portion is crystalline and the semiconductor layer on the at least part of the protective layer in the edge portion is non-crystalline; andetching the semiconductor layer to remove the non-crystalline semiconductor layer while retaining the crystalline semiconductor layer.3. The method of fabricating the wafer of claim 1 , wherein a mismatch of a coefficient of thermal expansion (CTE) between the semiconductor layer and the substrate is greater than 75 percent.4. The method of fabricating the wafer of claim 1 , wherein the semiconductor layer comprises a III ...

Semiconductor Device and Method of Forming Insulating Layers Around Semiconductor Die

A semiconductor device has a semiconductor wafer including a plurality of semiconductor die and a plurality of contact pads formed over a first surface of the semiconductor wafer. A trench is formed partially through the first surface of the semiconductor wafer. An insulating material is disposed over the first surface of the semiconductor wafer and into the trench. A conductive layer is formed over the contact pads. The conductive layer can be printed to extend over the insulating material in the trench between adjacent contact pads. A portion of the semiconductor wafer opposite the first surface of the semiconductor wafer is removed to the insulating material in the trench. An insulating layer is formed over a second surface of the semiconductor wafer and side surfaces of the semiconductor wafer. The semiconductor wafer is singulated through the insulating material in the first trench to separate the semiconductor die. 1. A method of making a semiconductor device , comprising:providing a semiconductor wafer including a contact pad formed over a first surface of the semiconductor wafer;forming a first trench into the first surface of the semiconductor wafer;disposing an insulating material over the first surface of the semiconductor wafer and into the first trench, wherein the contact pad is exposed from the insulating material and the insulating material includes a planar section extending from the contact pad to over the first trench;forming a conductive layer over the contact pad;backgrinding a second surface of the semiconductor wafer to expose the insulating material in the first trench;forming an insulating layer over the second surface of the semiconductor wafer; andsingulating the semiconductor wafer through the first trench.2. The method of claim 1 , wherein a portion of the conductive layer includes a footprint that is coextensive with a footprint of the contact pad.3. The method of claim 1 , wherein the insulating material and insulating layer enclose a ...

SEMICONDUCTOR DEVICE AND OPTICAL COUPLING DEVICE

According to one embodiment, a semiconductor device includes a first semiconductor element having a first surface, a second semiconductor element having a lower surface bonded to the first surface of the first semiconductor element, a gel-like silicone that covers an upper surface of the second semiconductor element, and a resin portion that covers the gel-like silicone and the first surface of the first semiconductor element. 1. A semiconductor device , comprising:a first semiconductor element having a first surface;a second semiconductor element having a lower surface bonded to the first surface of the first semiconductor element;a gel-like silicone covering an upper surface of the second semiconductor element; anda resin portion covering the gel-like silicone and the first semiconductor element.2. The semiconductor device according to claim 1 , wherein the gel-like silicone has a hardness value of 10 to 24 as determined according to at least one of JIS K 6253 and JIS K 7215.3. The semiconductor device according to claim 2 , wherein the resin portion has a hardness value greater than or equal to 30 as determined according to at least one of JIS K 6253 and JIS K 7215.4. The semiconductor device according to claim 1 , wherein the resin portion is an epoxy resin.5. The semiconductor device according to claim 1 , wherein the first semiconductor element is a light receiving chip and the second semiconductor element is a light emitting chip claim 1 , and the first semiconductor element is bonded to the second semiconductor with a transparent silicone material.6. The semiconductor device according to claim 1 , wherein a bonding wire extends through the resin portion and the gel-like silicone to contact the upper surface of the second semiconductor element.7. The semiconductor device according to claim 1 , wherein the second semiconductor element includes a light emitting element and the resin portion is opaque at a wavelength of light emitted by the light emitting ...

Stacked Semiconductor Devices and Methods of Forming Same

Stacked semiconductor devices and methods of forming the same are provided. Contact pads are formed on a die. A passivation layer is blanket deposited over the contact pads. The passivation layer is subsequently patterned to form first openings, the first openings exposing the contact pads. A buffer layer is blanket deposited over the passivation layer and the contact pads. The buffer layer is subsequently patterned to form second openings, the second opening exposing a first set of the contact pads. First conductive pillars are formed in the second openings. Conductive lines are formed over the buffer layer simultaneously with the first conductive pillars, ends of the conductive lines terminating with the first conductive pillars. An external connector structure is formed over the first conductive pillars and the conductive lines, the first conductive pillars electrically coupling the contact pads to the external connector structure. 1. A method of forming a semiconductor device , the method comprising:forming a first contact pad and a second contact pad over a substrate;depositing a passivation layer over the first contact pad and the second contact pad;patterning the passivation layer to expose a first opening over the first contact pad, the first opening having a first width;depositing a buffer layer over the passivation layer;patterning the buffer layer to expose a second opening over the first contact pad and a third opening over the passivation layer, the second opening having a second width less than the first width; and forming a first conductive pillar over the first contact pad, a topmost portion of the first conductive pillar having a third width greater than the second width;', 'forming a conductive line over the passivation layer, the conductive line electrically coupled to the first conductive pillar; and', 'forming a second conductive pillar over the second contact pad, the third opening being interposed between the second conductive pillar and the ...