Chip-size package production

Production of a semiconductor chip-size housing (CSP) involves (a) bonding conductive wires (45) onto bond pads on a chip (41); (b) placing the chip in an electrolysis cell (55) such that the wire ends are outside the electrolyte solution (50) of the cell; (c) fitting an electroplating electrode (60) on an inner wall of the cell; (d) placing a conductive plate (65) as common electrode on the exposed wire ends; and (e) connecting the conductive plate (65) and the outer wall of the cell (55) to a current source (70). Preferably, the wires (45) consist of gold, the conductive plate (65) consists of copper and the electroplating electrode (60) consists of nickel or gold.

Integriertes Passivvorrichtungs-Package und Verfahren zum Ausbilden von diesem

Ein Vorrichtungs-Package umfasst einen ersten Die, einen zweiten Die und eine Moldmasse, die sich entlang von Seitenwänden des ersten Die und des zweiten Die erstreckt. Das Package umfasst ferner Umverteilungsschichten (RDLs), die sich seitlich über Kanten des ersten Die und des zweiten Die hinaus erstrecken. Die RDLs umfassen einen Eingabe-/Ausgabekontakt (I/O-Kontakt), der mit dem ersten Die und dem zweiten Die elektrisch verbunden ist, und der I/O-Kontakt ist an einer Seitenwand des Vorrichtungs-Package freigelegt, die im Wesentlichen senkrecht zu einer den RDLs entgegengesetzten Fläche der Moldmasse ist.

Halbleiterbauelement mit Verbindungselementen und Verfahren zur Herstellung desselben

Halbleiterbauelement mit Verbindungselementen (6) zur Herstellung einer Verbindung zwischen einem Halbleiterchip (7) aus einem Halbleiterwafer (8) mit diskreten Halbleiterbauelementen (1 bis 5) und einem übergeordneten Schaltungsträger, wobei das Halbleiterbauelement (1 bis 5) eine koplanare Fläche (9) aus Oberseiten (10) der Verbindungselemente (6) und einer Kunststoffmasse (11) aufweist, und wobei das Verbindungselement (6) eine Mesastruktur (12) oder eine Pilzform (13) für eine Oberflächenmontage aufweist und ein Lotdepot in Form einer strukturierten bleifreien Kontaktbeschichtung (14) umfasst, wobei die Verbindungselemente (6) auf Kontaktflächen (15) der Halbleiterchips (7) angeordnet sind, die flächige Erstreckung der Verbindungselemente (6) den Kontaktflächen (15) des Halbleiterchips (7) entsprechen und alle Verbindungselemente (6) auf einer aktiven Oberseite des Halbleiterchips (7) angeordnet sind.

Protecting wiring on wafers/chips comprises covering wafer with wiring on its whole surface with organic layer to protect wiring from corrosion and oxidation and form sealed coating

Protecting the wiring on wafers/chips comprises covering the wafer (1) with the wiring on its whole surface with an organic layer (12) to protect the wiring from corrosion and oxidation and form a sealed coating of the metal surface of the wiring.

Verfahren zum Schutz einer Umverdrahtung auf Wafern/Chips

Verfahren zum Schutz der Seitenkanten einer Umverdrahtung auf Wafern oder Chips, die aus einer Seed-Layer, einer auf dieser befindlichen Kupferschicht, einer darauf angeordneten Nickel-Schicht, und einer diese abdeckenden Goldschicht besteht, wobei der mit der Umverdrahtung (1) versehene Wafer (4) leicht angeätzt wird, dass der Wafer (4) oder ein Flüssigkeitsvorrat eines organischen Materials zunächst auf eine Temperatur von ca. 30 °C erwärmt wird und dass der Wafer (4) anschließend auf seiner gesamten Oberfläche mit einer organischen Schutzschicht (12) dieses organischen Materials versehen wird und dass durch chemische Bindung eine dichte Belegung der Metalloberfläche der Umverdrahtung (1) erzeugt wird.

Lötverfahren und Schaltung

Vorgeschlagen wird ein Lötverfahren zum Verbinden eines Halbleiterchips (1) mit einer Leiterplatte (2) über wenigstens einen Lötkontakt (7) und zum Herstellen einer Schaltung (14), wobei der Halbleiterchip wenigstens ein elektrisch leitendes Pad (5) aufweist und die Leiterplatte wenigstens einen Leiterbahnabschnitt (9) zur Kontaktierung mit wenigstens einem der Pads des Halbleiterchips umfasst, umfassend: eine Auftragung von Lötpaste (10) auf den wenigstens einen Leiterbahnabschnitt, einen Bondingprozess, bei dem ein Höcker (7) auf wenigstens einem Materialabschnitt (6) auf wenigstens eines der Pads gebondet wird, einen Bestückungsvorgang, bei dem die Leiterplatte so mit wenigstens einem der Halbleiterchips bestückt wird, dass wenigstens einer der Lötkontakte mit der Lötpaste in Berührung kommt, einen Heizprozess, bei dem eine elektrisch leitende Verbindung zwischen dem Leiterbahnabschnitt und dem Pad hergestellt wird. Zur Verbesserung des Lötverfahrens wird als Lötkontakt ausschließlich ...

TIN SILVER BRAZING DENTS DURING THE ELECTRONICS PRODUCTION

PHOTO-SENSITIVE RESIN COMPOSITION, ISOLATION FOIL, PROTECTIVE PLASTIC FILM AND ELECTRONIC EQUIPMENT FOR IT

PROCEDURE FOR THE PRODUCTION OF SEMICONDUCTOR MICROCHIP

SEMICONDUCTOR ARRANGEMENT WITH SWITCHES ELECTRICAL CONNECTIONS, CONSTRUCTION UNIT THEREBY AND ITS MANUFACTURING PROCESSES

HIGH-DENSITY INTERCONNECTION OF TEMPERATURE SENSITIVE ELECTRONIC DEVICES

Electrical contact structures from flexible wire

SEMICONDUCTOR PACKAGE, SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE AND PRODUCTION METHOD FOR SEMICONDUCTOR PACKAGE

An insulation layer (3) is formed on an Si wafer (1), and a rewiring layer (2) is formed after an opening is formed in the insulation layer (3). Then, a resin layer (4) is formed on the rewiring layer (2), and it is cured and used to bond the rewiring layer (2) with Cu foils (5). Then, an annular opening (4a) is formed in the resin layer (4), and a Cu plated layer (8) is formed in the opening (4a).

METHOD OF PROVIDING RAISED CONTACT PORTIONS ON CONTACT AREAS OF AN ELECTRONIC MICROCIRCUIT

... : "Method of providing raised contact portions on contact areas of an electronic microcircuit". A method of providing raised contact portions on contact areas of an electronic microcircuit in which a ball is formed at one end of a metal wire by means of thermal energy, the ball is pressed against a contact area of the electronic microcircuit and is connected to said contact area, a weakening being provided in the wire near the ball and the wire being severed at the area of the weakening.

SEMICONDUCTOR DEVICE WITH COMPLIANT ELECTRICAL TERMINALS, APPARATUS INCLUDING THE SEMICONDUCTOR DEVICE, AND METHODS FOR FORMING SAME

A semiconductor device (e.g., a chip scale package or CSP) is described including multiple input/output (I/O) pads arranged on a surface of a semiconductor substrate, a compliant dielectric layer, an outer dielectric layer, and multiple electrically conductive, compliant interconnect bumps (i.e., compliant bumps). The compliant bumps may form electrical terminals of the semiconductor device. The compliant dielectric layer is positioned between the outer dielectric layer and the surface of the semiconductor substrate. The outer dielectric layer and the compliant dielectric both have multiple openings (i.e., holes) extending therethrough. Each of the compliant bumps is formed upon a different one of the I/O pads, and extends through a different one of the openings in the first compliant dielectric layer and the outer dielectric layer. Each of the compliant bumps includes an electrically conductive, compliant body, and an electrically conductive, solderable conductor element. The compliant ...

Halbleiterbauelement und Verfahren zu dessen Herstellung

PROCEDURE FOR THE ATTACHMENT OF CONTACT CONTACTS TO CONTACT POINTS OF AN ELECTRONIC MICROCIRCUIT.

ELECTRONIC PACKAGE AND MANUFACTURE MEHTOD THEREOF

Semiconductor device free from short-circuit between bump electrodes and separation from circuit board and process of fabrication thereof

Method for forming bump of semiconductor device

Method for making electronic element with lugs and method for making said electronic element

Method of manufacturing a semiconductor device

The present invention discloses a method for manufacturing semiconductor device, wherein, an internal connecting terminal 12 is formed on electrode pads 23 of a plurality of semiconductor chips 11 formed on a semiconductor substrate 35, and there is formed a resin member 13 having a resin member body 13-1 and a protruded portion 13-2 and covering the semiconductor chips 11 on which the internal connecting terminal 12 is formed, a metal layer 39 is formed on the resin member body 13-1 and the protruded portion 13-2 is used as an alignment mark to form a resist film 48 covering the metal layer 39 in a part corresponding to a region in which a wiring pattern 14 is formed and to then carry out etching over the metal layer 39 by using the resist layer 48 as a mask, thereby forming the wiring pattern 14 which is electrically connected to the internal connecting terminal 12.

Semiconductor device having align mark layer and method of fabricating the same

Semiconductor device and a method of manufacturing the semiconductor device

A semiconductor device having redistribution interconnects in the WPP technology and improved reliability, wherein the redistribution interconnects have first patterns and second patterns which are electrically separated from each other within the plane of the semiconductor substrate, the first patterns electrically coupled to the multi-layer interconnects and the floating second patterns are coexistent within the plane of the semiconductor substrate, and the occupation ratio of the total of the first patterns and the second patterns within the plane of the semiconductor substrate, that is, the occupation ratio of the redistribution interconnects is 35 to 60%.

Semiconductor device

Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion (2) formed on the upper surface of a semiconductor substrate (1), a passivation layer (3) so formed on the upper surface of the semiconductor substrate (1) as to overlap a part of the electrode pad portion (2) and having a first opening portion (3a) where the upper surface of the electrode pad portion (2) is exposed, a barrier metal layer (5) formed on the electrode pad portion (2), and a solder bump (6) formed on the barrier metal layer (5). The barrier metallayer (5) is formed such that an outer peripheral end (5b) lies within the first opening portion (3a) of the passivation layer (3) when viewed in plan.

Adhesive composition, electronic component-mounted substrate using the adhesive composition, and semiconductor device

METHOD FOR REALIZATION OF STUDS OF CONNECTION ON A CIRCUIT PRINTS

Wafer level chip scale package manufacture comprises use of mold or complex stencil to make stress relaxing insulation layer for front face of wafer

L'invention concerne un procédé de réalisation d'un boîtier à la taille d'une puce électronique et réalisé à l'échelle du substrat, le substrat comportant au moins une puce et ladite au moins une puce possédant des plots d'entrée-sortie sur une face du substrat dite face avant, le procédé comprenant les étapes suivantes : a) formation, au moyen d'un moule ou d'un pochoir complexe, d'une couche isolante de relaxation de contraintes sur ladite face avant, ladite couche de relaxation recouvrant la face avant du substrat avec un relief présentant des puits d'accès au niveau des plots d'entrée-sortie, et ailleurs, des parties en saillie destinées à relaxer les contraintes, chaque partie en saillie ayant une forme étagée comprenant au moins une zone proéminente et au moins une zone, en retrait par rapport à ladite zone proéminente, destinée à supporter un plot de connection électrique, b) formation de pistes électriquement conductrices sur la couche de relaxation pour connecter les plots d'entrée ...

SUPPORT WITH SOLDER GLOBULE ELEMENTS AND A METHOD FOR ASSEMBLY OF SUBSTRATES WITH GLOBULE CONTACTS

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

MEMORY ELEMENT AND SEMICONDUCTOR DEVICE

AN ELECTRONIC DEVICE AND A METHOD OF MANUFACTURING THE SAME

CHIP SCALE SURFACE MOUNT PACKAGES FOR SEMICONDUCTOR DEVICE AND PROCESS OF FABRICATING THE SAME

PURPOSE: A chip scale surface-mounting semiconductor device package is provided to have a footprint of the same side as a semiconductor die. CONSTITUTION: The method for fabricating a package for a semiconductor device comprises the steps of bringing dies into contact with connecting pads on a surface of the dies while the dies are parts of a wafer, forming a first metal layer extended into a scribe line between the die and its adjacent die, forming a nonconductive layer on a lower surface of the water, and covering the nonconductive layer with a second metal layer. In this case, the second layer is extended into the scribe line brought into contact with the first metal layer through an opening of the nonconductive layer. © KIPO 2002 ...

FLIP CHIP

The present invention provides a flip chip not causing a crack even at ultrasonic bonding. According to an embodiment of the present invention, the flip chip comprises: a substrate; an electrode pad layer laminated on the substrate; a passivation layer laminated on both ends of the electrode pad layer; an under bump metallurgy (UBM) layer laminated on the electrode pad layer and the passivation layer; and a bump formed on the UBM layer. An opening on which the passivation layer is not laminated on the electrode pad layer is wider than the width of the bump. COPYRIGHT KIPO 2018 ...

SEMICONDUCTOR APPARATUS AND A METHOD FOR MANUFACTURING THE SAME CAPABLE OF PREVENTING THE PEELING OF A PHOTORESIST RESIN LAYER OR AN INTERLAYER FROM A SEMICONDUCTOR SUBSTRATE

PURPOSE: A semiconductor apparatus and a method for manufacturing the same are provided to prevent the peeling of a photoresist resin layer or an interlayer from a semiconductor substrate. CONSTITUTION: An electrode for outside connection is formed on a semiconductor chip(10') having an interlayer(11). A rewire(12) is electrically connected to the electrode. The rewire is prepared on the interlayer. The rewire is coated by an insulation layer(13). A pad(15) is electrically connected to the rewire through an opening formed on the insulation layer. A solder terminal(19) is prepared on the pad. A photoresist resin layer(17) is prepared on the insulation layer. An outer circumference of the interlayer is coated by the photoresist resin layer. A step unit is prepared at the outer circumference of the semiconductor chip. The step unit protrudes an outer circumference opposite to the interlayer toward the outside more than the outer circumference of the interlayer. The outer circumference of the ...

SHEET-LIKE UNDERFILL MATERIAL AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD

A sheet-like underfill material to be adhered on a circuit plane of a semiconductor wafer (6) whereupon bumps (5) are formed. The underfill material is composed of a base material (1) and an adhesive layer (2) peelably formed on the base material, and is adhered so that the bumps (5) penetrate the adhesive layer (2) and the bump top sections intrude into the base material (1). The base material (1) has a storage elastic modulus of 1.0x10^6-4.0x10^9Pa, a rupture stress of 1.0x10^5-2.0x10^8Pa, and a Yong's modulus of 1.0x10^7-1.1x10^10Pa, and the adhesive layer (2) has a storage elastic modulus of 1.0x10^4-1.0x10^7Pa, and a rupture stress of 1.0x10^3-3.0x10^7Pa. © KIPO & WIPO 2008 ...

JUNCTION STRUCTURE OF TERMINAL PAD AND SOLDER, SEMICONDUCTOR DEVICE HAVING THE SAME STRUCTURE, AND METHOD FOR MANUFACTURING THE SAME SEMICONDUCTOR DEVICE HAVING REACTIVE PRODUCT LAYER BETWEEN TERMINAL PAD AND SOLDER

PURPOSE: A junction structure of a terminal pad and solder, a semiconductor device having the same structure, and a method for manufacturing the same semiconductor device are provided to reduce resistance to thermal stress by forming a reactive product layer between the terminal pad and the solder. CONSTITUTION: A junction structure of a terminal pad and solder includes a terminal pad(120) formed on a base(105), solder, and a reactive product layer(250). The reactive product layer includes a component of the terminal pad and a reactive product layer of a Zn-based material which are provided between the terminal pad and the solder. The terminal pad and the solder are formed at a semiconductor device. The reactive product layer is formed between the terminal pad of the inside of the semiconductor device and the solder. © KIPO 2007 ...

SEMICONDUCTOR COMPONENT AND METHOD, STRUCTURE FOR MOUNTING SEMICONDUCTOR COMPONENT AND METHOD

PURPOSE: A semiconductor component and fabricating method therefor, a structure for mounting the semiconductor component and mounting method therefor are provided to improve the contact strength of a land terminal at a time of semiconductor component mounting and to provide a sufficient margin to arrangement pitch of a wire passing the land terminal. CONSTITUTION: A semiconductor component comprises land terminals(22a,22b,22c) for bump arranged as a grid pattern and connected to the electrode pad surface through re-arrangement wires on a substrate. The land terminals for bump is divided into external land terminals(22a) arranged at the circumference of the substrate and internal land terminals(22c) arranged at inner side of the external land terminals. Each external land terminal has a diameter larger than that of each internal land terminal. COPYRIGHT 2000 KIPO ...

ELECTRONIC SUBSTRATE, A SEMICONDUCTOR DEVICE AND AN ELECTRONIC INSTRUMENT TO SIMPLIFY THE MOUNTING PROCESS OF AN ELECTRONIC SUBSTRATE

PURPOSE: An electronic substrate is provided to decrease the number of connection terminals of an electronic substrate by enabling transmission and reception of signals while using a plurality of inductor devices formed on an electronic substrate. CONSTITUTION: A base member(10) has an active surface and a back surface. A plurality of inductor devices are formed on the active surface or the back surface. The plurality of inductor devices can include a first inductor device(80) and a second inductor device(40) that has a different inductance value from that of the first inductor device and an adaptable frequency. © KIPO 2007 ...

SEMICONDUCTOR DEVICE FORMING SMALL Z-SIZED PACKAGE, AND METHOD THEREOF

A semiconductor device includes a plurality of first semiconductor dies. A plurality of first bumps is formed on the first semiconductor dies. A first protecting layer is formed on the first bumps. A part of the first semiconductor dies is removed during rear side polishing work. A rear protecting layer is formed on the first semiconductor dies. A sealant is deposited on the first semiconductor dies and first bumps. A part of the sealant is removed to expose the first bumps. A conductive layer is formed on the first bumps and sealant. An insulating layer and a plurality of second bumps are formed on the conductive layer. A plurality of conductive vias is formed through the sealant. A plurality of semiconductor devices is stacked and, at the same time, the conductive vias electrically connect the semiconductor devices. Second semiconductor dies with through silicon are placed on the first semiconductor dies. COPYRIGHT KIPO 2017 ...

BALL GRID ARRAY PACKAGING METHOD AND BALL GRID ARRAY PACKAGE

PURPOSE: A ball grid array(BGA) packaging method is provided to reduce process time and cost by eliminating the necessity of a back-end rerouting step used in a conventional BGA chip scale packaging technology. CONSTITUTION: A semiconductor die having metal conductors thereon is provided. The metal conductors are covered with an insulation layer. An etch process is performed through the insulation layer so as to provide one or more openings to the metal conductors. A compliant material layer is deposited. An etch process is performed through the compliant material layer so as to provide on or more openings to the metal conductors. The conductive layer is patterned so as to bring at least one of the metal conductors in electrical contact with one or more pads, each pad comprising a portion of the conductive layer disposed upon the compliant material. Solder balls(2) are disposed upon the pads. © KIPO 2004 ...

SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD

PURPOSE: To prevent a α-ray soft error of a semiconductor device wherein a solder bump is connected to a Cu wiring formed on an Al wiring. CONSTITUTION: A bump-land 6 connecting with the solder bump 10A and the Cu wiring 10 formed together with it in one-piece, consists of a stacked-layer film of a Cu film and a Ni film formed on its upper portion. The film thickness of the stacked-layer film is larger than film thickness of each of a photosensitive polyimide resin film 11 formed on the lower layers of the Cu wiring 10 and the bump-land 10A, an inorganic passivation film 26, a third Al wiring 25, the bump-pad BP, and a second inter-layer insulating film 24. That is, the bump-land 10A is constructed by film thickness larger than those of an insulating component and wiring component which are interposed between a MISFET (n- channel-type MISFETQn and p-channel-type MISFETQp) and the bump-land 10A. © KIPO & JPO 2003 ...

팬 아웃 패널 레벨 패키지 및 그의 제조 방법

... 본 발명은 팬 아웃 패널 레벨 패키지 및 그의 제조방법을 개시한다. 그의 제조방법은, 팬 아웃 기판의 캐버티들 내에 다이들을 고정하는 몰드 기판을 제공하는 단계와, 팬 아웃 기판에 대한 다이들 각각의 위치를 검출하는 단계와, 팬 아웃 기판과 다이들 사이의 캐버티들 상에 팬 아웃 기판으로부터 미리 설정된 위치들의 다이들로 연장하는 제 1 부분과, 미리 설정된 위치들과 다른 검출된 위치의 적어도 하나의 상기 다이들로부터 팬 아웃 기판으로 연장하는 제 2 부분을 포함하는 배선들을 형성하는 단계를 포함한다.

Semiconductor element and a producing method for the same, and a semiconductor device and a producing method for the same

A columnar bump formed of copper etc. is formed on a wiring film of a semiconductor chip through an interconnected film and an adhesive film in a wafer unit by electrolytic plating in which package formation is possible. An oxidation prevention film is formed of such as gold on an upper surface or a part of the upper surface and side surface. A wet prevention film of such as an oxide film is formed on the columnar bump side as needed. If this bump is soldered to the pad on a packaging substrate, solder gets wet in the whole region of the columnar bump upper surface and only a part of the side surface. Stabilized and reliable junction form can be thus formed. Moreover, since the columnar bump does not fuse, the distance between a semiconductor board and a packaging board is not be narrowed by solder.

Semiconductor device, method for manufacturing semiconductor device, circuit board, and electronic instrument

A semiconductor device includes: a semiconductor substrate having an active surface and a back surface; an integrated circuit formed on the active surface; a feedthrough electrode penetrating the semiconductor substrate, and projecting from the active surface and the back surface; a first resin layer formed on the active surface, having a thickness greater than a height of a portion of the feedthrough electrode that projects from the active surface, and having an opening portion for exposing at least a portion of the feedthrough electrode; a wiring layer which is formed on the first resin layer, and which is connected to the feedthrough electrode through the opening portion; and an external connecting terminal connected to the wiring layer.

Semiconductor device, manufacturing method for semiconductor device, electronic component, circuit substrate, and electronic apparatus

A semiconductor device includes: a semiconductor substrate including a first face and a second face on a side opposite to the first face; an external connection terminal formed on the first face of the semiconductor substrate; a first electrode formed on the first face of the semiconductor substrate and electrically connected to the external connection terminal; an electronic element formed on or above the second face of the semiconductor substrate; a second electrode electrically connected to the electronic element and having a top face and a rear face; a groove portion formed on the second face of the semiconductor substrate and having a bottom face including at least part of the rear face of the second electrode; and a conductive portion formed in the groove portion and electrically connected to the rear face of the second electrode.

Method and system for packing optimization of semiconductor devices

Provided is a disclosure for optimizing the number of semiconductor devices on a wafer/substrate. The optimization comprises laying out, cutting, and packaging the devices efficiently.

SEMICONDUCTOR DEVICE AND METHOD OF FORMING ATHIN WAFER WITHOUT A CARRIER

Abstract SEMICONDUCTOR DEVICE AND METHOD OFFORMING A THIN WAFER WITHOUT A CARRIERA semiconductor device has a conductive via in a first surface of a substrate. A first interconnect structure is formed over the first surface of the substrate. A first bump is formed over the first interconnect structure. The first bump is formed over or offset from the conductive via. An encapsulant is deposited over the first bump and first interconnect structure. A portion of the encapsulant is removed to expose the first bump. A portion of a second surface of the substrate is removed to expose theconductive via. The encapsulant provides structural support and eliminates the need for a separate carrier wafer when thinning the substrate. A second interconnect structure is formed over the second surface of the substrate. A second bump is formed over the first bump. A plurality of semiconductor devices can be stacked and electrically connected through the conductive via.(Figure 5) ...

Press-fit power module and related methods

Semiconductor package

Electronic substrate, semiconductor device, and electronic device

Semiconductor devices and fabrication method thereof

Dip formation of flip-chip solder bumps

A process for fabricating a solder bump (113) includes providing an inorganic de-wetting substrate (102). In order to form a composite substrate (20), having the desired wetting/de-wetting composition, a wetting metal is first applied on the inorganic de-wetting substrate to create at least one wetting metal pad (52). The composite substrate (20) is then dipped or otherwise immersed into a reservoir of liquid solder (106). Next, the composite substrate (20) is redraw (116), or otherwise removed, from the liquid solder to form solder bumps (113) on the at least one metal wetting pad (52).

Solder ball structure of circuit board and method for fabricating same

BUMP STRESS MITIGATION LAYER FOR INTEGRATED CIRCUITS

An apparatus comprises a semiconductor substrate having a device layer, a plurality of metallization layers, a passivation layer, and a metal bump formed on the passivation layer that is electrically coupled to at least one of the metallization layers. The apparatus further includes a solder limiting layer formed on the passivation layer that masks an outer edge of the top surface of the metal bump, thereby making the outer edge of the top surface non-wettable to a solder material.

UNDER BUMP METALLIZATION STRUCTURE HAVING A SEED LAYER FOR ELECTROLESS NICKEL DEPOSITION

Structures and methods for fabrication of an under bump metallization (UBM) structure having a metal seed layer and electroless nickel deposition layer are disclosed involving a UBM structure comprising a semiconductor substrate, at least one final metal layer, a passivation layer, a metal seed layer, and a metallization layer. The at least one final metal layer is formed over at least a portion of the semiconductor substrate. Also, the passivation layer is formed over at least a portion of the semiconductor substrate. In addition, the passivation layer includes a plurality of openings. Additionally, the passivation layer is formed of a non-conductive material. The at least one final metal layer is exposed through the plurality of openings. The metal seed layer is formed over the passivation layer and covers the plurality of openings. The metallization layer is formed over the metal seed layer. The metallization layer is formed from electroless deposition.

ADHESIVE COMPOSITION, ELECTRONIC COMPONENT-MOUNTED SUBSTRATE USING THE ADHESIVE COMPOSITION, AND SEMICONDUCTOR DEVICE

This invention provides an adhesive composition which, while maintaining storage stability, can form a metallic bond in such a state that the cured product wets components and is spread well between components, and is excellent in adhesion, electroconductivity, TCT resistance, and mounting reliability such as high-temperature standing resistance, and an electronic component-mounted substrate using the adhesive composition and a semiconductor device.The adhesive composition comprises electroconductive particles (A) and a binder component (B). The adhesive composition is characterized in that the electroconductive particles (A) comprise a metal (a1), which has a melting point equal to or above the reflow temperature and is free form lead, and a metal (a2), which has a melting point below the reflow temperature and is free from lead, and the binder component (B) comprises a heat curable resin composition (b1) and an aliphatic dihydroxycarboxylic acid (b2).

WAFER-LEVEL FABRICATION OF LIDDED CHIPS WITH ELECTRODEPOSITED DIELECTRIC COATING

A unit including a semiconductor element, e.g., a chip-scale package (350, 1350) or an optical sensor unit (10) is fabricated. A semiconductor element (300) has semiconductive or conductive material (316) exposed at at least one of the front (302) and rear surfaces (114) and conductive features (310) exposed thereat which are insulated from the semiconductive or conductive material. By electrodeposition, an insulative layer (304) is formed to overlie the at least one of exposed semiconductive material or conductive material. Subsequently, a plurality of conductive contacts (308) and a plurality of conductive traces (306) are formed overlying the electrodeposited insulative layer (304) which connect the conductive features (310) to the conductive contacts (308). An optical sensor unit (10) can be incorporated in a camera module (1030) having an optical element (1058) in registration with an imaging area (1026) of the semiconductor element (1000).

STABLE GOLD BUMP SOLDER CONNECTIONS

A metallic interconnect structure (200) for connecting a gold bump (205) and a copper pad (212), as used for example in semiconductor flip-chip assembly. A first region (207) of binary AuSn2 intermetallic is adjacent to the gold bump. A region (208) of binary AuSn4 intermetallic is adjacent to the first AuSn2 region. Then, a region (209) of binary gold-tin solid solution is adjacent to the AuSn4 region, and a second region (210) of binary AuSn2 intermetallic is adjacent to the solid solution region. The second AuSn2 region is adjacent to a nickel layer (213) (preferred thickness about 0.08 μm), which covers the copper pad. The nickel layer insures that the gold/tin intermetallic s and solutions remain substantially free of copper and thus avoid ternary compounds, providing stabilized gold bump/solder connections.

Semiconductor device and manufacturing method therefor

A semiconductor device is obtained, in which excellent characteristics are achieved, the reliability is improved, and an SiC wafer can also be used for the fabrication. A plurality of Schottky-barrier-diode units 10 is formed on an SiC chip 9, and each of the units 10 has an external output electrode 4 independently of each other. Bumps 11 (the diameter is from several tens to several hundreds of m) are formed only on the external output electrodes 4 of non-defective units among the units 10 formed on the SiC chip 9, meanwhile bumps are not formed on the external output electrodes 4 of defective units in which the withstand voltage is too low, or the leakage current is too much. Because the bumps are not formed on the defective units, Schottky-barrier-side electrodes 3 are connected in parallel to the exterior of the device through the bumps 11, and a wiring layer 13 and an external lead 13a of a wiring substrate 12; thus, only the external output electrodes 4 of the non-defective units ...

Semiconductor packaging process using through silicon vias

A microelectronic unit can include a semiconductor element having a front surface, a microelectronic semiconductor device adjacent to the front surface, contacts at the front surface and a rear surface remote from the front surface. The semiconductor element can have through holes extending from the rear surface through the semiconductor element and through the contacts. A dielectric layer can line the through holes. A conductive layer may overlie the dielectric layer within the through holes. The conductive layer can conductively interconnect the contacts with unit contacts.

FABRICATING PROCESS OF A CHIP PACKAGE STRUCTURE

A fabricating process of a chip package structure is provided. First, a first substrate having a plurality of first bonding pads and a second substrate having a plurality of second bonding pads are provided, wherein bumps are formed on the first bonding pads of the first substrate. A first two-stage adhesive layer is formed on the first substrate and is B-stagized to form a first B-staged adhesive layer. A second two-stage adhesive layer is formed on the second substrate and is B-stagized to form a second B-staged adhesive layer. Then, the first substrate and the second substrate are bonded via the first and second B-staged adhesive layer such that the bumps pierce through the second B-staged adhesive layer and are electrically connected to the second bonding pads, wherein each of the first bonding pads is respectively electrically connected to one of the second bonding pads via one of the bumps.

Microelectronic packages with solder interconnections

A soldered assembly for a microelectronic element includes a microelectronic element, solder columns extending from a surface of the microelectronic element and terminals connected to distal ends of the columns. The assembly can be handled and mounted using conventional surface-mount techniques, but provides thermal fatigue resistance. The solder columns may be inclined relative to the chip surface, and may contain long, columnar inclusions preferentially oriented along the lengthwise axes of the columns.

TIN-SILVER SOLDER BUMPING IN ELECTRONICS MANUFACTURE

A process for forming a solder bump on an under bump metal structure in the manufacture of a microelectronic device comprising exposing the under bump metal structure to an electrolytic bath comprising a source of Sn2+ ions, a source of Ag+ ions, a thiourea compound and/or a quaternary ammonium surfactant; and supplying an external source of electrons to the electrolytic bath to deposit a Sn—Ag alloy onto the under bump metal structure.

SEMICONDUCTOR CHIP AND METHOD FOR FABRICATING THE SAME

A semiconductor chip includes a silicon substrate, a first dielectric layer over said silicon substrate, a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, a second dielectric layer between said first and second metal layers, a passivation layer over said metallization structure and over said first and second dielectric layers, an opening in said passivation layer exposing a pad of said metallization structure, a polymer bump over said passivation layer, wherein said polymer bump has a thickness of between 5 and 25 micrometers, an adhesion/barrier layer on said pad exposed by said opening, over said passivation layer and on a top surface and a portion of sidewall(s) of said polymer bump, a seed layer on said adhesion/barrier layer; and a third metal layer on said seed layer.

Multi-component integrated circuit contacts

An integrated circuit connection is describe that includes a first, securing member and a second, connection member. The first member, in an embodiment, is a spike that has a portion of its body fixed in a layer of an integrated circuit structure and extends outwardly from the integrated circuit structure. The second material is adapted to form a mechanical connection to a further electrical device. The second material (e.g., solder), is held by the first member to the integrated circuit structure. The first member increases the strength of the connection and assists in controlling the collapse of second member to form the mechanical connection to another circuit. The connection is formed by coating the integrated circuit structure with a patterned resist and etching the layer beneath the resist. A first member material (e.g.,metal) is deposited. The resist is removed. The collapsible material is fixed to the first member.

Semiconductor device with intermediate connector

A semiconductor element and a circuit substrate each having electrodes disposed at narrow pitch are electrically connected with high reliability by conductive paste. A semiconductor device with a semiconductor section and a circuit substrate electrically connected and a method for manufacturing such semiconductor device are provided. The manufacturing method includes processes of: forming semiconductor electrodes at the semiconductor section; forming substrate electrodes at the circuit substrate; firstly affixing one part of the semiconductor section and circuit substrate to an intermediate connector made of insulating material; forming via holes at intermediate connector according to positions of the semiconductor electrodes and positions of the substrate electrodes; electrically connecting each semiconductor electrode and each substrate electrode via each via hole; and secondly affixing the other part of the semiconductor section and circuit substrate to the intermediate connector.

Integrated circuit chip to substrate interconnection and method

An interconnection between bonding pads on an integrated circuit chip and corresponding bonding contacts on a substrate are formed. To form the interconnection, a metallization is formed on each of the substrate bonding contacts. Metal ball bond bumps are formed on selective ones of the bonding pads and then coined. The substrate and integrated circuit chip are heated. The coined ball bond bumps are then placed into contact with the corresponding metallizations, pressure and ultrasonic energy are applied, and a metal-to-metal bond is formed between each coined ball bond bump and the corresponding metallization.

Method for bumping and packaging semiconductor die

An electrical interconnect structure, including a first component (300), a second component (320), and an electrical interconnect electrically and mechanically interconnecting the first component to the second component, the electrical interconnect including a first solder sphere (314) and a second solder sphere (318) stacked on each other. A semiconductor die (200, 100) that is bumped and packaged utilizing the electrical interconnect structure is also disclosed.

Flip chip technology using electrically conductive polymers and dielectrics

A method is presented for interconnecting bond pads of a flip chip with bond pads of a substrate by an electrically conductive polymer. An organic protective layer is selectively formed over a surface of a flip chip to thereby leave exposed bond pads on the flip chip. Electrically conductive polymerizable precursor is formed on the bond pads extending to a level beyond the organic protective layer to form bumps. The bumps are aligned with bond pads of a substrate and then contacted to those bond pads. The bumps can be polymerized either before or after contacting the bumps to the bond pads of the substrate to form electrically conductive interconnections between the bond pads of the flip chip and the bond pads of the substrate.

Collar positionable about a periphery of a contact pad and around a conductive structure secured to the contact pads, semiconductor device components including same, and methods for fabricating same

Dielectric collars to be disposed around contact pads on a surface of a semiconductor device or another substrate and methods of fabricating and disposing the collars on semiconductor devices and other substrates are disclosed. Semiconductor devices including the collars and having contact pads exposed through the collars are also disclosed. One or more of the collars are disposed around the contact pads of a semiconductor device or other substrate before or after conductive structures are secured to the contact pads. Upon connecting the semiconductor device face down to a higher level substrate and establishing electrical communication between contact pads of the semiconductor device and contacts pads of the substrate, the collars prevent the material of conductive structures protruding from the semiconductor device from contacting regions of the surface of the semiconductor device that surround the contact pads thereof. The collars may be preformed structures which are attached to a surface ...

Method of locating conductive spheres utilizing screen and hopper of solder balls

Apparatus and methods for placing conductive spheres on prefluxed bond pads of a substrate using a stencil plate with a pattern of through-holes positioned over the bond pads. Conductive spheres are placed in the through-holes by a moving feed mechanism and the spheres drop through the through-holes onto the bond pads. In one embodiment, the feed mechanism is a sphere hopper which crosses the entire through-hole pattern. In another embodiment, a shuttle plate fed spheres from a reservoir and reversibly moves about one-half of the pitch, moving from a non-discharge position to a discharge position.

Stereolithographically fabricated conductive elements, semiconductor device components and assemblies including such conductive elements, and methods

Stereolithographically fabricated conductive elements and semiconductor device components and assemblies including these conductive elements. The conductive elements may include multiple superimposed, contiguous, mutually adhered layers of a conductive material, such as a thermoplastic conductive elastomer or a metal. In semiconductor device assemblies, the stereolithographically fabricated conductive elements may electrically connect semiconductor device components to one another. The conductive elements may alternatively comprise conductive traces or vias of circuit boards or interposers. A stereolithographic method for fabricating the conductive elements may include use of a machine vision system with at least one camera operably associated with a computer controlling a stereolithographic application of material so that the system may recognize the position, orientation, and features of a semiconductor device assembly, semiconductor die, or other substrate on which the conductive element ...

Low fabrication cost, fine pitch and high reliability solder bump

A barrier layer is deposited over a layer of passivation including in an opening to a contact pad created in the layer of passivation. A column of three layers of metal is formed overlying the barrier layer and aligned with the contact pad and having a diameter that is about equal to the surface of the contact pad. The three metal layers of the column comprise, in succession when proceeding from the layer that is in contact with the barrier layer, a layer of pillar metal, a layer of under bump metal and a layer of solder metal. The layer of pillar metal is reduced in diameter, the barrier layer is selectively removed from the surface of the layer of passivation after which reflowing of the solder metal completes the solder bump of the invention.

Method for fabricating semiconductor package with circuit side polymer layer

A semiconductor package includes a substrate, a die attached and wire bonded to the substrate, and a die encapsulant encapsulating the die. The die includes a circuit side having a pattern of die contacts, planarized wire bonding contacts bonded to the die contacts, and a planarized polymer layer on the circuit side configured as stress defect barrier. A method for fabricating the package includes the steps of forming bumps on the die, encapsulating the bumps in a polymer layer, and then planarizing the polymer layer and the bumps to form the planarized wire bonding contacts. The method also includes the steps of attaching and wire bonding the die to the substrate, and then forming the die encapsulant on the die.

Structure for preventing burnt fuse pad from further electrical connection

A semiconductor device with a capability can prevent a burnt fuse pad from re-electrical connection, wherein the semiconductor device includes a bump pad and a fuse pad over a wafer. The fuse pad includes the burnt fuse pad having a gap for electrical isolation. The semiconductor device comprises a dielectric layer, disposed substantially above the burnt fuse pad and filling the gap, and a bump structure, disposed on the bump pad. The foregoing semiconductor device can further comprise a passivation layer, which exposes the bump pad and a portion of the burnt fuse pad. Wherein, the dielectric layer is over the passivation layer, covers the exposed portion of the burnt fuse pad and fills the gap.

Bonding IC die to TSV wafers

A method for bonding IC die to TSV wafers includes bonding at least one singulated IC die to respective ones of a plurality of IC die on a TSV wafer that includes a top semiconductor surface and TSV precursors including embedded TSV tips to form a die-wafer stack. The die-wafer stack is thinned beginning from the bottom surface of the TSV wafer to form a thinned die-wafer stack. The thinning includes exposing the embedded TSV tips to provide electrical access thereto from the bottom surface of the TSV wafer. The thinned die-wafer stack can be singulated to form a plurality of thinned die stacks.

Probe card assembly and kit, and methods of using same

A probe card assembly includes a probe card, a space transformer having resilient contact structures (probe elements) mounted directly thereto (i.e., without the need for additional connecting wires or the like) and extending from terminals on a surface thereof, and an interposer disposed between the space transformer and the probe card. The space transformer and interposer are "stacked up" so that the orientation of the space transformer, hence the orientation of the tips of the probe elements, can be adjusted without changing the orientation of the probe card. Suitable mechanisms for adjusting the orientation of the space transformer, and for determining what adjustments to make, are disclosed. The interposer has resilient contact structures extending from both the top and bottom surfaces thereof, and ensures that electrical connections are maintained between the space transformer and the probe card throughout the space transformer's range of adjustment, by virtue of the interposer's ...

Structure of a ball bump for wire bonding and the formation thereof

The ball bump mainly includes a body and a protrusion. The protrusion is located at the upper of the body and essentially consists of a flat upper surface with an annular inclination. The flat upper surface and the annular inclination together define the area for wire bonding. The method of the formation of the ball bump of wire bonding mainly comprises steps of: an end of a wire held by a bonding machine is melted to form a ball; the bonding machine bonds the ball onto the bonding pad to form a ball bump; the bonding tool moves upward a predetermined vertical distance and the clamp of the bonding tool is then opened; the bonding tool is moved a predetermined horizontal distance to reduce the connection part of wire connecting to the upper of the ball bump for the convenience of wire cutting, and this forms a protrusion on the ball bump consisting of a flat upper surface with an annular inclination; the bonding tool is again moved upward a predetermined vertical distance, and the clamp ...

Fine pitch bumping with improved device standoff and bump volume

Embodiments of the present invention relate generally to solder bump formation and semiconductor device assemblies. One embodiment related to a method for forming a bump structure includes providing a semiconductor device (10) having a bond pad (12), and forming a first masking layer (20) overlying the bond pad (12). The first masking layer (20) is patterned to form a first opening (22) overlying at least a portion of the bond pad (12). A second masking layer (40) is formed overlying the first masking layer (20), and the second masking layer (40) is patterned to form a second opening (42) overlying at least a portion of the first opening (22). The method further includes forming a stud (30) at least within the first opening (22) and a solder bump (60) at least within the second opening (42).

Methods for making z-axis electrical connections

The present invention relates to a method for connecting an integrated circuit chip to a circuit substrate. The method includes the step of the steps pre-applying adhesive directly to a bumped side of integrated circuit chip. The method also includes the step of pressing the bumped side of the integrated circuit chip, which has previously been coated with adhesive, against the circuit substrate such that the bumps provide an electrical connection between the integrated circuit chip and the circuit substrate. The pre-applied adhesive on the chip forms a bond between the integrated circuit chip and the circuit substrate.

Method and apparatus for extending fatigue life of solder joints in a semiconductor device

A ball grid array (BGA) or chips scale package (CSP) integrated circuit (IC) (20) is manufactured by first identifying the most unreliable solder ball joints in the IC. These worst case joints, or joints in the vicinity of the worst case joints, are changed in pad dimension and exposed to more ball/bump conductive material than the other more robust joints (14) in the IC (20) to create a ball (24) on a larger pad (22) that is larger than the normal sized ball (14). The larger balls (24) are formed by placing multiple smaller balls (14) together on a single pad (22) to form one larger ball (24) during a reflow operation. The larger ball (24) improves the overall IC reliability by improving the reliability of the weakest joints in the IC design. In addition, the standoff of both the larger balls (24) and the smaller balls (14) are engineered to be substantially equal.

Thin metal barrier for electrical interconnections

An interconnect structure and barrier layer for electrical interconnections is described incorporating a layer of TaN in the hexagonal phase between a first material such as Cu and a second material such as Al, W, and PbSn. A multilayer of TaN in the hexagonal phase and Ta in the alpha phase is also described as a barrier layer. The invention overcomes the problem of Cu diffusion into materials desired to be isolated during temperature anneal at 500° C.

Circuit board and process for producing the same

The invention includes: applying an anisotropic conductive resin including conductive particles only to a plurality of bumps of an electronic component; placing the electronic component above a main surface of a flexible wiring board via the anisotropic conductive resin; and pressurizing the electronic component to the wiring board and curing the anisotropic conductive resin applied to the plurality of bumps to join the plurality of bumps to the electrodes of the wiring board. This can prevent a defective mounting of the electronic component.

Thermo-compression bonded electrical interconnect structure and method

An electrical structure and method for forming electrical interconnects. The method includes positioning a sacrificial carrier substrate such that a first surface of a non-solder metallic core structure within the sacrificial carrier substrate is in contact with a first electrically conductive pad. The first surface is thermo-compression bonded to the first electrically conductive pad. The sacrificial carrier substrate is removed from the non-solder metallic core structure. A solder structure is formed on a second electrically conductive pad. The first substrate comprising the non-solder metallic core structure is positioned such that a second surface of the non-solder metallic core structure is in contact with the solder structure. The solder structure is heated to a temperature sufficient to cause the solder structure to melt and form an electrical and mechanical connection between the second surface of the non-solder metallic core structure and the second electrically conductive pad.

Method of manufacturing a semiconductor device using electrical contacts formed in an isolation layer

Disclosed are techniques for constructing a novel solder bump layout on substrates for bonding using flip-chip, wafer-level, or other similar techniques. In one embodiment, a method of manufacturing a semiconductor device provides for forming contact pads on a first substrate, and forming an isolation layer over the contact pads and the substrate. In addition the method includes forming openings in the isolation layer over the contact pads, and depositing metal in the openings and in electrical contact with the contact pads to form electrical contacts in the openings. Also in such embodiments, the method includes bonding exposed surfaces of the electrical contacts to corresponding bonding pads formed on an external surface of a second substrate. In these embodiments, the bonding is done such that the isolation layer is in contact with the external surface to provide electrical isolation between the first and second substrates and between the electrical contacts.

Semiconductor device and manufacturing method thereof

A semiconductor device and manufacturing method thereof improving moisture resistance of a FeRAM. After a probe test using a pad, a metal film is formed to cover the pad in an opening of a protective film and a region from the pad to an opening outer periphery of the protective film. On the metal film, a metal bump is formed. The metal film is formed to have a two-layer structure of the first and second metal films. Materials of the lower and upper layers are selected mainly in consideration of adhesion to the protective film and adhesion to the metal bump, respectively. Film formation conditions thereof are set to provide metal films with a desired quality and thickness. Thus, penetration of moisture from the pad or the periphery into a ferroelectric capacitor can be prevented and therefore, occurrence of potential inversion abnormalities due to penetrated moisture can be effectively suppressed.

Through wafer vias and method of making same

A method of forming and structure for through wafer vias and signal transmission lines formed of through wafer vias. The method of forming through wafer vias includes forming an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via through a semiconductor substrate having a top surface and an opposite bottom surface, each through wafer via of the array of through wafer vias extending from the top surface of the substrate to the bottom surface of the substrate.

Autoclave capable chip-scale package

A power semiconductor package that includes a power semiconductor device having a threshold voltage that does not vary when subjected to an autoclave test.

Semiconductor device

For preventing alpha-rays induced soft errors in a semiconductor device in which solder bumps are connected with Cu wirings formed on Al wirings, bump lands connected with solder bumps and Cu wirings connected integrally therewith are constituted of a stacked film of a Cu film and an Ni film formed thereon, the thickness of the stacked film is larger than the thickness of the photosensitive polyimide resin film, the thickness of the inorganic passivation film, the thickness of the third Al wiring layer and the bonding pad and the thickness of the second interlayer insulative film formed below the Cu wirings and the bump land, that is, the bump land being constituted with such a thickness as larger than any of the thickness for the insulation material and the wiring material interposed between the MISFET (n-channel MISFET and p-channel MISFET) constituting the memory cell and the bump land.

Semiconductor integrated circuit device

In semiconductor integrated circuit devices for vehicle use, an aluminum pad on a semiconductor chip and an external device are coupled to each other by wire bonding using a gold wire for the convenience of mounting. Such a semiconductor integrated circuit device, however, causes a connection failure due to the interaction between aluminum and gold in use for a long time at a relatively high temperature (about 150 degrees C.). A semiconductor integrated circuit device can include a semiconductor chip as a part of the device, an electrolytic gold plated surface film (gold-based metal plated film) provided over an aluminum-based bonding pad on a semiconductor chip via a barrier metal film, and a gold bonding wire (gold-based bonding wire) for interconnection between the plated surface film and an external lead provided over a wiring board (wiring substrate).

Use of palladium in IC manufacturing with conductive polymer bump

An apparatus and a method for forming a substrate having a palladium metal layer over at least one contact point of the substrate and having a flexible conductive polymer bump, preferably a two-stage epoxy, on the palladium plated contact point, are provided. The present invention also relates to assemblies comprising one or more of these substrates.

Thin film metal barrier for electrical interconnections

An interconnect structure and barrier layer for electrical interconnections is described incorporating a layer of TaN in the hexagonal phase between a first material such as Cu and a second material such as Al, W, and PbSn. A multilayer of TaN in the hexagonal phase and Ta in the alpha phase is also described as a barrier layer. The invention overcomes the problem of Cu diffusion into materials desired to be isolated during temperature anneal at 500° C.

Semiconductor device having low dielectric insulating film and manufacturing method of the same

A semiconductor device includes a semiconductor substrate on which a structure portion is provided except a peripheral portion thereof, and has a laminated structure including low dielectric films and wiring lines, the low dielectric films having a relative dielectric constant of 3.0 or lower and a glass transition temperature of 400° C. or higher. An insulating film is formed on the structure portion. A connection pad portion is arranged on the insulating film and connected to an uppermost wiring line of the laminated structure portion. A bump electrode is provided on the connection pad portion. A sealing film made of an organic resin is provided on a part of the insulating film which surrounds the pump electrode. Side surfaces of the laminated structure portion are covered with the insulating film and/or the sealing film.

Method for fabricating a chip scale package using wafer level processing

Channels are formed that pass through an active surface of a semiconductor substrate to provide isolation between adjacent active surface regions defining individual die locations. Bond pads on the substrate are bumped with intermediate conductive elements, after which a material used to encapsulate the active surface is applied, filling the channels and covering exposed peripheral edges of the active surface integrated circuitry. The encapsulant is then planarized to expose the ends of the bumps. External conductive elements such as solder balls are then formed on the exposed bump ends. The semiconductor wafer is diced in alignment with the channels to singulate the semiconductor devices, the encapsulant in the channels keeping the edges of the integrated circuitry substantially hermetically sealed.

Semiconductor device with intermediate connector

A semiconductor element and a circuit substrate each having electrodes disposed at narrow pitch are electrically connected with high reliability by conductive paste. A semiconductor device with a semiconductor section and a circuit substrate electrically connected and a method for manufacturing such semiconductor device are provided. The manufacturing method includes processes of: forming semiconductor electrodes at the semiconductor section; forming substrate electrodes at the circuit substrate; firstly affixing one part of the semiconductor section and circuit substrate to an intermediate connector made of insulating material; forming via holes at intermediate connector according to positions of the semiconductor electrodes and positions of the substrate electrodes; electrically connecting each semiconductor electrode and each substrate electrode via each via hole; and secondly affixing the other part of the semiconductor section and circuit substrate to the intermediate connector.

SEMICONDUCTOR DEVICES

A semiconductor device comprises a substrate, a semiconductor chip on the substrate, and first and second leads between the substrate and the semiconductor chip. The first and second leads extend from an edge of the substrate toward below the semiconductor chip along a first direction parallel to a top surface of the substrate. The first lead includes a first bump connector and a first segment. The second lead includes a second bump connector. The first bump connector is spaced apart in the first direction from the second bump connector. The first segment of the first lead is spaced apart in a second direction from the second bump connector. The second direction is parallel to the top surface of the substrate and perpendicular to the first direction. A thickness of the first segment of the first lead is less than that of the second bump connector.

Method for manufacture of integrated circuit package system with protected conductive layers for pads

A method for manufacture of an integrated circuit package system includes: providing an integrated circuit die having a contact pad; forming a protection cover over the contact pad; forming a passivation layer having a first opening over the protection cover with the first opening exposing the protection cover; developing a conductive layer over the passivation layer; forming a pad opening in the protection cover for exposing the contact pad having the conductive layer partially removed; and an interconnect directly on the contact pad and only adjacent to the protection cover and the passivation layer.

Interconnections for flip-chip using lead-free solders and having reaction barrier layers

An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting composition including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components. With a two-layer ball-limiting composition comprising an adhesion/reaction barrier layer, wherein the adhesion/reaction barrier layer serves both as an adhesion layer and a reaction barrier layer, the adhesion/reaction barrier layer can be comprised of a material selected from the group consisting of Zr and ZrN

Semiconductor device

There is provided a semiconductor device with which stress can be prevented from locally concentrating on an external connecting terminal on a post and thus damages of the external connecting terminal can be prevented. The semiconductor device includes a semiconductor chip, a sealing resin layer stacked on a surface of the semiconductor chip, and the post which penetrates the sealing resin layer in a stacking direction of the semiconductor chip and the sealing resin layer, protrudes from the sealing resin layer, and has a periphery of the protruding portion opposedly in contact with a surface of the sealing resin layer in the stacking direction.

Microelectronic assemblies having compliancy and methods therefor

A microelectronic assembly is disclosed that includes a semiconductor wafer with contacts, compliant bumps of dielectric material overlying the first surface of the semiconductor wafer, and a dielectric layer overlying the first surface of the semiconductor wafer and edges of the compliant bumps. The compliant bumps have planar top surfaces which are accessible through the dielectric layer. Conductive traces may be electrically connected with contacts and extend therefrom to overlie the planar top surfaces of the compliant bumps. Conductive elements may overlie the planar top surfaces in contact with the conductive traces.

Ohmic connection using widened connection zones in a portable electronic object

The invention relates to portable electronic objects comprising an integrated circuit chip, and a mounting having two connection terminals for a circuit, as well as to a method for manufacturing such objects. The invention is characterized in that the chip is provided, on the active surface thereof, with two widened connection zones, in particular connection plates, said connection plates being positioned opposite said terminals and electrically connected, by ohmic contact, to the latter, and in that the surface defined by the connection plates, at the surface of the active integrated circuit having said plates, is greater than ½ of the surface of said surface. The invention can be used, in particular, for RFID objects.

Thermally and dimensionally stable polyimide films and methods relating thereto

The present disclosure is directed to a polyimide film. The film is composed of a polyimide and a sub-micron filler. The polyimide is derived from at least one aromatic dianhydride component selected from rigid rod dianhydride, non-rigid rod dianhydride and combinations thereof, and at least one aromatic diamine component selected from rigid rod diamine, non-rigid rod diamine and combinations thereof. The mole ratio of dianhydride to diamine is 48-52:52-48 and the ratio of X:Y is 20-80:80-20 where X is the mole percent of rigid rod dianhydride and rigid rod diamine, and Y is the mole percent of non-rigid rod dianhydride and non-rigid rod diamine. The sub-micron filler is less than 550 nanometers in at least one dimension; has an aspect ratio greater than 3:1; is less than the thickness of the film in all dimensions.

Coverlay compositions and methods relating thereto

The present disclosure is directed to a coverlay comprising a polyimide film and an adhesive layer. The polyimide film is composed of a polyimide and a sub-micron filler. The polyimide is derived from at least one aromatic dianhydride component selected from rigid rod dianhydride, non-rigid rod dianhydride and combinations thereof, and at least one aromatic diamine component selected from rigid rod diamine, non-rigid rod diamine and combinations thereof. The mole ratio of dianhydride to diamine is 48-52:52-48 and the ratio of X:Y is 20-80:80-20 where X is the mole percent of rigid rod dianhydride and rigid rod diamine, and Y is the mole percent of non-rigid rod dianhydride and non-rigid rod diamine. The sub-micron filler is less than 550 nanometers in at least one dimension; has an aspect ratio greater than 3:1; is less than the thickness of the film in all dimensions.

Through wafer vias and method of making same

A method of forming and structure for through wafer vias and signal transmission lines formed of through wafer vias. The method of forming through wafer vias includes forming an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via through a semiconductor substrate having a top surface and an opposite bottom surface, each through wafer via of the array of through wafer vias extending from the top surface of the substrate to the bottom surface of the substrate.

Bump-on-trace (bot) structures

A bump-on-trace (BOT) structure is described. The BOT structure includes a first work piece with a metal trace on a surface of the first work piece, wherein the metal trace has a first axis. The BOT structure further includes a second work piece with an elongated metal bump, wherein the elongated metal bump has a second axis, wherein the second axis is at a non-zero angle from the first axis. The BOT structure further includes a metal bump, wherein the metal bump electrically connects the metal trace and the elongated metal bump. A package having a BOT structure and a method of forming the BOT structure are also described.

Through Silicon Via Layout

A system and method for forming under bump metallization layers that reduces the overall footprint of UBMs, through silicon vias, and trace lines is disclosed. A preferred embodiment comprises forming an under bump metallization layer over a plurality of through silicon vias, whereas the UBM is connected to only a portion of the total number of through silicon vias over which it is located. The trace lines connected to the through silicon vias may additionally be formed beneath the UBM to save even more space on the surface of the die.

INTEGRATED ANTENNAS IN WAFER LEVEL PACKAGE

A semiconductor module, comprises a package molding compound layer comprising an integrated circuit (IC) device embedded within a package molding compound, the integrated circuit device and the package molding compound having a common surface. Structures are formed to connect the semiconductor module to an external board, the structures electrically connected to the integrated circuit device. A layer is formed on the common surface, the layer comprising at least one integrated antenna structure, the integrated antenna structure being coupled to the IC device. 1. A semiconductor module , comprising:a package molding compound layer comprising an integrated circuit (IC) device embedded within a package molding compound, the integrated circuit device and the package molding compound having a common surface;structures to connect the semiconductor module to an external board, the structures electrically connected to the integrated circuit device; anda layer formed on the common surface, the layer comprising at least one integrated antenna structure, the integrated antenna structure coupled to the IC device.2. The module of claim 1 , wherein the structures are provided lateral to the integrated circuit device.3. The module of claim 1 , wherein the layer formed on the common surface comprises a dielectric coat.4. The module of claim 1 , wherein the structure comprises surface-mountable solder balls providing external contacts and a mechanical support structure with at least one bond wire.5. The module of claim 1 , wherein a further layer is located on a surface of the package molding compound layer opposite to the common surface claim 1 , the further layer comprising metal.6. The module of claim 5 , wherein the further layer comprises bonding interface structures connected to the integrated circuit device claim 5 , the bonding interface structures provided for contacting surfaces external to the module.7. The module of claim 1 , further comprising at least one parasitic ...

SEMICONDUCTOR CHIP AND MANUFACTURING METHOD THEREOF

A semiconductor device comprising stacked substrates through a bump, the bump comprising a solder bump formed on a copper bump wherein the solder bump includes Zn. 1. A semiconductor device comprising:a first substrate; anda second substrate stacked on the first substrate through a bump,the bump comprising a solder bump formed on a copper bump formed over the second substrate;wherein the solder bump includes Zn.2. The semiconductor device according to claim 1 , further comprising;a through-electrode penetrating the second substrate, the bump being electrically connected with the through-electrode.3. The semiconductor device according to claim 1 ,wherein a concentration of Zn in an upper portion of the solder bump is lower than a concentration of Zn in a lower portion of the solder bump, the lower portion of the solder bump is in contact with the copper bump.4. The semiconductor device according to ;wherein the solder bump includes 1 to 5% by weight of Zn.5. The semiconductor device according to ;wherein the solder bump further includes Bi6. The semiconductor device according to ;wherein the solder bump further includes Bi.7. The semiconductor device according to ;wherein the solder bump further includes Cu.8. The semiconductor device according to ;wherein the solder hump further includes Cu.9. The semiconductor device according to ;wherein the solde bump further includes Cu.10. A method of manufacturing a semiconductor device claim 4 , the semiconductor device comprising a first substrate stacked on a second substrates through a bump claim 4 , the bump comprising a solder bump formed on a copper hump formed over the first substrate claim 4 , the method comprising:forming the copper bump over the first substrate;forming a Sn/Zn alloy layer on the copper bump;forming a Sn/Ag alloy layer on the Sn/Zn alloy; andheating and reflowing the Sn/Zn alloy layer and the Sn/Ag alloy layer.11. The method according to ;wherein the first substrate has a through-electrode ...

Semiconductor device bonding with stress relief connection pads

An inventive semiconductor device includes: a semiconductor chip; an internal pad provided on a surface of the semiconductor chip for electrical connection; a surface protective film covering the surface of the semiconductor chip and having a pad opening from which the internal pad is exposed; a stress relief layer provided on the surface protective film and having an opening portion through which the internal pad exposed from the pad opening is exposed; a connection pad including an anchor buried in the pad opening and the opening portion and connected to the internal pad, and a projection provided integrally with the anchor as projecting on the stress relief layer, the projection having a width greater than an opening width of the opening portion; and a metal ball provided for external electrical connection as covering the projection of the connection pad.

Semiconductor Device

Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion () formed on the upper surface of a semiconductor substrate (), a passivation layer () so formed on the upper surface of the semiconductor substrate () as to overlap a part of the electrode pad portion () and having a first opening portion () where the upper surface of the electrode pad portion () is exposed, a barrier metal layer () formed on the electrode pad portion (), and a solder bump () formed on the barrier metal layer (). The barrier metal layer () is formed such that an outer peripheral end () lies within the first opening portion () of the passivation layer () when viewed in plan. 110-. (canceled)11. A semiconductor chip comprising:an electrode pad portion formed on a face of a substrate;a first protection layer including a first opening through which a top face of the electrode pad portion is exposed, the first protection layer disposed on the face of the substrate and overlapping part of the electrode pad portion;a barrier metal layer formed on the electrode pad portion; anda bump electrode on the barrier metal layer,wherein the first protection layer has a step part formed therein as a result of the first protection layer overlapping the part of the electrode pad portion;wherein the barrier metal layer has a circumferential end part thereof formed outward of the step part as seen in a plan view, andwherein the bump electrode is bonded to the barrier metal layer so as to cover a side surface of the barrier metal layer in the circumferential end part thereof.12. The semiconductor chip according to claim 11 , further comprising:a second protection layer covering a region on the first protection layer and a region on the electrode pad portion,wherein the barrier metal layer is on the electrode pad portion with a peripheral part of the barrier metal layer located over the second protection layer.13. The semiconductor chip ...

Substrate and semiconductor device

A substrate includes a base member having a predetermined thickness, and an electrode array provided in one surface in a thickness direction of the base member and having a plurality of electrodes arranged two-dimensionally in a plan view, and the electrode array includes a central portion and an incremental region provided around the central portion in the planar view and is formed so that a height of the electrodes in the incremental region gradually increase as approaching toward the central portion.

BONDING OF SUBSTRATES INCLUDING METAL-DIELECTRIC PATTERNS WITH METAL RAISED ABOVE DIELECTRIC AND STRUCTURES SO FORMED

Bonding of substrates including metal-dielectric patterns on a surface with the metal raised above the dielectric, as well as related structures, are disclosed. One method includes providing a first substrate having a metal-dielectric pattern on a surface thereof; providing a second substrate having a metal-dielectric pattern on a surface thereof; performing a process resulting in the metal being raised above the dielectric; cleaning the metal; and bonding the first substrate to the second substrate. A related structure is also disclosed. The bonding of raised metal provides a strong bonding medium, and good electrical and thermal connections enabling creation of three dimensional integrated structures with enhanced functionality. 18-. (canceled)9. A structure comprising: a metal having a convex-dome shape; and', 'a dielectric having a substantially uniform upper surface,', 'wherein the metal on the first substrate is raised above the dielectric on the first substrate; and, 'a first substrate having a metal-dielectric pattern on a surface thereof, the metal-dielectric pattern including a dielectric; and', 'a metal positioned substantially below the dielectric of the second substrate,, 'a second substrate bonded with the first substrate, the second substrate includingwherein the first substrate and the second substrate are bonded at the metal from the first substrate and the metal from the second substrate,wherein the first substrate and the second substrate are bonded only by the metal of the first substrate and the metal of the second substrate.10. The structure of claim 9 , wherein the metal positioned substantially below the dielectric on the second substrate includes a concave upper surface.11. (canceled)12. The structure of claim 10 , wherein the bonded metals of the first substrate and the second substrate are bonded substantially seamlessly.13. The structure of claim 9 , wherein the bonded metal of the first substrate and the metal of the second substrate are ...

Electrical Interconnections of Semiconductor Devices and Methods for Fabricating the Same

Provided are electrical interconnections and methods for fabricating the same. The electrical interconnection may include a substrate including a bonding pad, a solder ball electrically connected to the bonding pad, a solder supporter on the bonding pad, a portion of the solder ball filling the solder supporter, and a metal layer between the bonding pad and the solder supporter, the metal layer having an ionization tendency lower than the bonding pad. 1. An electrical interconnection comprising:a substrate comprising a bonding pad formed thereon;a solder ball electrically connected to the bonding pad;a solder supporter on the bonding pad, a portion of the solder ball filling the solder supporter; anda metal layer between the bonding pad and the solder supporter, the metal layer having an ionization tendency lower than the bonding pad.2. The electrical interconnection of claim 1 , further comprising a passivation layer on the substrate through which the bonding pad is exposed.3. The electrical interconnection of claim 1 , wherein the solder supporter comprises:a floor adjacent to the bonding pad; anda vertical wall upright from an edge of the floor,wherein the floor and the vertical wall define an inner space of the solder supporter, the inner space being filled with a portion of the solder ball, andwherein the other portion of the solder ball protrudes outside of the solder supporter.4. The electrical interconnection of claim 3 , wherein at least one of the floor and the vertical wall has a shape of stairs.5. The electrical interconnection of claim 3 , wherein the solder supporter further comprises an extension extending outwardly from the vertical wall.6. The electrical interconnection of claim 3 , wherein a contacting portion of the solder supporter between the floor and the vertical wall is rounded.7. The electrical interconnection of claim 1 , further comprising a bump pillar between the bonding pad and the metal layer claim 1 ,wherein the metal layer has an ...

Semiconductor integrated circuit device

In semiconductor integrated circuit devices for vehicle use, an aluminum pad on a semiconductor chip and an external device are coupled to each other by wire bonding using a gold wire for the convenience of mounting. Such a semiconductor integrated circuit device, however, causes a connection failure due to the interaction between aluminum and gold in use for a long time at a relatively high temperature (about 150 degrees C.). A semiconductor integrated circuit device can include a semiconductor chip as a part of the device, an electrolytic gold plated surface film (gold-based metal plated film) provided over an aluminum-based bonding pad on a semiconductor chip via a barrier metal film, and a gold bonding wire (gold-based bonding wire) for interconnection between the plated surface film and an external lead provided over a wiring board (wiring substrate).

Discrete semiconductor device package and manufacturing method

Disclosed is a discrete semiconductor device package ( 100 ) comprising a semiconductor die ( 110 ) having a first surface and a second surface opposite said first surface carrying a contact ( 112 ); a conductive body ( 120 ) on said contact; an encapsulation material ( 130 ) laterally encapsulating said conductive body; and a capping member ( 140, 610 ) such as a solder cap, a further semiconductor die or a combination thereof in conductive contact with the solder portion, said solder cap extending over the encapsulation material. A further solder cap ( 150 ) may be provided over the first surface. A method of manufacturing such a discrete semiconductor device package is also disclosed.

Semiconductor device

A semiconductor device includes a protective layer, a redistribution pattern, a pad pattern and an insulating polymer layer. The protective layer may be formed on a substrate. The redistribution pattern may be formed on the protective layer. An upper surface of the redistribution may be substantially flat. The pad pattern may be formed directly on the redistribution pattern. An upper surface of the pad pattern may be substantially flat. The insulating polymer layer may be formed on the redistribution pattern and the pad pattern. An upper surface of the insulating polymer layer may be lower than the upper surface of the pad pattern. The semiconductor device may have a high reliability.

SEMICONDUCTOR DEVICE, MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, CIRCUIT SUBSTRATE, AND ELECTRONIC APPARATUS

A semiconductor device includes an integrated circuit that is disposed at a first face side of a semiconductor substrate, the semiconductor substrate having a first face and a second face, the second face opposing the first face, the semiconductor substrate having a through hole from the first face to the second face; an external connection terminal that is disposed at the first face side; a conductive portion that is disposed in the through hole, the conductive portion being electrically connected to the external connection terminal; and an electronic element that is disposed at a second face side. 1. A device comprising:a semiconductor substrate including a first face and a second face on a side opposite to the first face;a foundation layer formed on the first face of the semiconductor substrate;a first electrode formed on the foundation layer;a second electrode formed on the foundation layer;an integrated circuit comprising at least two interconnected semiconductor devices, the at least two interconnected semiconductor devices formed on the first face of the semiconductor substrate, and the integrated circuit being electrically connected to the first electrode and the second electrode;a groove portion formed through the semiconductor substrate;an insulating film formed on a side wall of the groove portion;a conductive portion formed inside the groove portion on the insulating film and electrically connected to the second electrode;a first insulation layer formed on the foundation layer;a first interconnection formed on the first insulation layer, the first interconnection being electrically connected to the first electrode;a second insulation layer formed on the first interconnection and the first insulation layer;a second interconnection formed on the second insulation layer, the second interconnection being electrically connected to the first interconnection; anda third insulation layer formed on the second interconnection and the second insulation layer; ...

METHOD AND APPARATUS FOR WAFER LEVEL PACKAGING

Methods and apparatus for wafer level packaging are described herein. According to one embodiment, a method comprises depositing an adhesive layer atop a carrier, placing at least a portion of a substrate pre-fabricated with a plurality of die cavities and a plurality of through vias atop the laminate, inserting a die into each of the die cavities, encapsulating the die and the substrate and debonding and removing the laminate and the carrier from the encapsulated die and substrate. Another embodiment provides an apparatus comprising a substrate, a plurality of die cavities formed through the substrate and a plurality of conductive through vias disposed through the substrate and arranged about the perimeter of each die cavity, wherein a top surface of the substrate is exposed for application of an encapsulating layer and a bottom surface of the substrate is exposed for placement on an adhesive layer. 1. A apparatus for use in wafer package processing , comprising:a substrate;a plurality of die cavities formed through the substrate; anda plurality of conductive through vias disposed through the substrate and arranged about the perimeter of each die cavity,wherein a top surface of the substrate is exposed for application of an encapsulating layer and a bottom surface of the substrate is exposed for placement on an adhesive layer.2. The substrate of claim 1 , wherein the substrate is a printed circuit board.3. The substrate of claim 1 , wherein the substrate is a glass wafer.4. The substrate of claim 1 , wherein the plurality of conductive through vias are filled with one of copper or solder.5. An electronics package comprising:a substrate consisting of an array of die cavities formed in the substrate, wherein each die cavity is surrounded by one or more rows of through vias having conductive materials disposed therein;a plurality of dies disposed in a cavity in the array of die cavities;an encapsulating material disposed on the top surface of the substrate for ...

Semiconductor Device and Method

In an embodiment, a device includes: a first reflective structure including first doped layers of a semiconductive material, alternating ones of the first doped layers being doped with a p-type dopant; a second reflective structure including second doped layers of the semiconductive material, alternating ones of the second doped layers being doped with a n-type dopant; an emitting semiconductor region disposed between the first reflective structure and the second reflective structure; a contact pad on the second reflective structure, a work function of the contact pad being less than a work function of the second reflective structure; a bonding layer on the contact pad, a work function of the bonding layer being greater than the work function of the second reflective structure; and a conductive connector on the bonding layer.

Light emitting device and method for manufacturing same

A method for manufacturing a light emitting device includes forming a multilayer body including a light emitting layer so that a first surface thereof is adjacent to a first surface side of a translucent substrate. A dielectric film on a second surface side opposite to the first surface of the multilayer body is formed having first and second openings on a p-side electrode and an n-side electrode. A seed metal on the dielectric film and an exposed surface of the first and second openings form a p-side metal interconnect layer and an n-side metal interconnect layer separating the seed metal into a p-side seed metal and an n-side seed metal by removing a part of the seed metal. A resin is formed in a space from which the seed metal is removed.

Semiconductor device having planarized passivation layer and method of fabricating the same

A semiconductor device includes a semiconductor substrate divided into a pad region and a cell region and having an active surface and an inactive surface opposite to the active surface, a plurality of metal lines on the active surface of the semiconductor substrate, passivation layers on the active surface of the semiconductor substrate, and a plurality of bumps in the cell region. The passivation layers include a first passivation layer covering the plurality of metal lines and having a non-planarized top surface along an arrangement profile of the plurality of metal lines, and a second passivation layer on the non-planarized top surface of the first passivation layer and having a planarized top surface on which the plurality of bumps are disposed.

SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device package includes a first substrate having a first surface, a first electrical contact disposed on the first surface of the first substrate, a second substrate having a second surface facing the first surface of the first substrate, and a second electrical contact disposed on the second surface of the second substrate. The first electrical contact has a base portion and a protrusion portion. The second electrical contact covers at least a portion of the protrusion portion of the first electrical contact. The second electrical contact has a first surface facing the first substrate and a second surface facing the second substrate. A slope of a first interface between the second electrical contact and the protrusion portion of the first electrical contact adjacent to the first surface of the second electrical contact is substantially the same as a slope of a second interface between the second electrical contact and the protrusion portion of the first electrical contact adjacent to the second surface of the second electrical contact. A method of manufacturing a semiconductor device package is also disclosed. 1. A semiconductor device package , comprising:a first substrate having a first surface;a first electrical contact disposed on the first surface of the first substrate, the first electrical contact having a base portion and a protrusion portion;a second substrate having a second surface facing the first surface of the first substrate; anda second electrical contact disposed on the second surface of the second substrate and covering at least a portion of the protrusion portion of the first electrical contact, the second electrical contact having a first surface facing the first substrate and a second surface facing the second substrate;wherein a slope of a first interface between the second electrical contact and the protrusion portion of the first electrical contact adjacent to the first surface of the second electrical contact is ...

Integrated circuit chip and display device including the same

An exemplary embodiment provides a driving circuit chip including: a substrate; a terminal electrode disposed on the substrate; and an electrode pad disposed on the terminal electrode, wherein the electrode pad includes: a bump structure protruded from the substrate to include a short side and a long side; and a bump electrode disposed on the bump structure and connected with the terminal electrode around a short edge portion of the bump structure, wherein the bump electrode is disposed to not cover at least a part of a long edge portion of the bump structure.

FAN-OUT PACKAGE STRUCTURE INCLUDING ANTENNA

The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package including a first redistribution layer (RDL) structure having a first surface and a second surface opposite to the first substrate. The first RDL structure includes a plurality of first conductive traces close to the first surface of the first RDL structure. An antenna pattern is disposed close to the second surface of the first RDL structure. A first semiconductor die is disposed on the first surface of the first RDL structure and electrically coupled to the first RDL structure. A plurality of conductive structures is disposed on the first surface of the first RDL structure and electrically coupled to the first RDL structure. The plurality of conductive structures is spaced apart from the antenna pattern through the plurality of first conductive traces of the first RDL structure. 1. A semiconductor package assembly , comprising: [ a plurality of first conductive traces close to the first surface of the first RDL structure; and', 'an antenna pattern close to the second surface of the first RDL structure;, 'a first redistribution layer (RDL) structure having a first surface and a second surface opposite to the first substrate, wherein the first RDL structure comprises, 'a first semiconductor die disposed on the first surface of the first RDL structure and electrically coupled to the first RDL structure; and, 'a first semiconductor package, comprisinga plurality of conductive structures disposed on the first surface of the first RDL structure and electrically coupled to the first RDL structure, wherein the plurality of conductive structures is spaced apart from the antenna pattern through the plurality of first conductive traces of the first RDL structure.2. The semiconductor package assembly as claimed in claim 1 , wherein the first semiconductor package comprises:a first molding compound surrounding the first semiconductor die, being in ...

SEMICONDUCTOR DEVICE, MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, CIRCUIT SUBSTRATE, AND ELECTRONIC APPARATUS

A semiconductor device includes an integrated circuit that is disposed at a first face side of a semiconductor substrate, the semiconductor substrate having a first face and a second face, the second face opposing the first face, the semiconductor substrate having a through hole from the first face to the second face; an external connection terminal that is disposed at the first face side; a conductive portion that is disposed in the through hole, the conductive portion being electrically connected to the external connection terminal; and an electronic element that is disposed at a second face side. 1. A device comprising:a semiconductor substrate including a first face and a second face on a side opposite to the first face;an external connection terminal formed on the first face of the semiconductor substrate;a first electrode formed on the first face of the semiconductor substrate and electrically connected to the external connection terminal;a second electrode formed on the first face of the semiconductor substrate;an integrated circuit formed on the first face, the integrated circuit being electrically connected to the first electrode and the second electrode;a rear face electrode formed on the second face of the semiconductor substrate;a groove portion formed in the semiconductor substrate, the groove portion having an inner wall;an insulating film formed on side walls of the groove portion; anda conductive portion formed inside the groove portion on the insulating portion and electrically connected to the second electrode and the rear face electrode;wherein the integrated circuit and the first electrode are electrically disposed between the second electrode and the external connection terminal.2. The device of claim 1 , wherein the semiconductor substrate is silicon.3. The device of claim 2 , wherein:the second electrode comprises a second electrode rear face facing the first face of the semiconductor substrate;the rear face electrode comprises a rear face ...

Single-Shot Encapsulation

A semiconductor device includes a semiconductor wafer. A plurality of pillar bumps is formed over the semiconductor wafer. A solder is deposited over the pillar bumps. The semiconductor wafer is singulated into a plurality of semiconductor die after forming the pillar bumps while the semiconductor wafer is on a carrier. An encapsulant is deposited around the semiconductor die and pillar bumps while the semiconductor die remains on the carrier. The encapsulant covers an active surface of the semiconductor die between the pillar bumps.

Methods to fabricate integrated circuits by assembling components

The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the present fabrication separation of an IC structure into multiple discrete components can take advantages of dedicated IC fabrication facilities and achieve more cost effective products. The present process can fabricate multiple components separately before assembling them into a complete integrated circuit. In an aspect, the ready-for-assembling components are taken directly from processed wafers without any additional assembling processes, and/or having lateral dimensions less than 1 mm.

Integrated circuit die having a split solder pad

The invention relates to an electronic system comprising: an integrated circuit die having: at least 2 bond pads a redistribution layer, said redistribution layer having: at least a solder pad comprising 2 portions arranged to enable an electrical connection between each other by a same solder ball placed on said solder pad, but electrically isolated of each other in the absence of a solder ball on the solder pad at least 2 redistribution wires, each one connecting one of the 2 portions to one of the 2 bond pads, a second bond pad connected via a second redistribution wire to a second portion of the solder pad being dedicated to testing said integrated circuit die a grounded printed circuit board track, a solder ball being placed between the solder pad and the printed circuit board track.

Semiconductor package and semiconductor device

A semiconductor package includes a semiconductor die encapsulated by an insulating encapsulation, a redistribution circuit structure disposed over the semiconductor die and the insulating encapsulation, the redistribution circuit structure being electrically connected to the semiconductor die; and a conductive feature having a first portion embedded in the redistribution circuit structure and a second portion connected to the first portion, the first portion having a first long axis and a first short axis perpendicular to the long axis in a top view, the second portion disposed over and electrically connected to the first portion. A semiconductor device having the semiconductor package, a circuit substrate and a circuit board is also provided.

SEMICONDUCTOR PACKAGE

The present disclosure provides a semiconductor package including a semiconductor chip and a package substrate. The semiconductor chip includes a substrate, a plurality of conductive pads in the substrate, and a plurality of conductive bumps. Each of the conductive bumps is over corresponding conductive pad. At least one of the conductive bumps proximity to an edge of the semiconductor chip is in contact with at least two discrete regions of the corresponding conductive pad. The package substrate has a concave surface facing the semiconductor chip and joining the semiconductor chip through the plurality of conductive bumps. 1. A semiconductor package , comprising: a substrate;', 'a plurality of conductive pads in the substrate; and', 'a plurality of conductive bumps, each over corresponding conductive pad, at least one of the conductive bumps proximity to an edge of the semiconductor chip being in contact with at least two discrete regions of the corresponding conductive pad; and, 'a semiconductor chip, comprisinga package substrate having a concave surface facing the semiconductor chip and joining the semiconductor chip through the plurality of conductive bumps.2. The semiconductor package of claim 1 , wherein one of the at least two discrete regions closer to a center of the semiconductor chip is larger than another one of the at least two discrete regions closer to the edge of the semiconductor chip.3. The semiconductor package of claim 1 , wherein the conductive pads having at least two discrete regions are ellipses from top view perspective.4. The semiconductor package of claim 3 , wherein the two discrete regions are on a major axis of each of the conductive pads from top view perspective.5. The semiconductor package of claim 1 , further comprising:an active region in the substrate; andan interconnecting layer over the active region and in contact with a bottom of each of the conductive pads.6. The semiconductor package of claim 5 , further comprising a ...

CURABLE RESIN FILM AND FIRST PROTECTIVE FILM FORMING SHEET

This curable resin film forms a first protective film on a surface having bumps of a semiconductor wafer by being attached to the surface and being cured, in which a cured material of the curable resin film has a Young's modulus of equal to or greater than 0.02 MPa and a peak value of a load measured by a probe tack test at 80° C. is equal to or less than 500 g. A first protective film forming sheet is provided with a first supporting sheet, and the curable resin film is provided on one surface of the first supporting sheet. 1. A curable resin film for forming a first protective film on a surface having bumps of a semiconductor wafer by being attached to the surface and being cured ,wherein a cured material of the curable resin film has a Young's modulus of equal to or greater than 0.02 MPa and a peak value of a load measured by a probe tack test at 80° C. is equal to or less than 500 g.2. A first protective film forming sheet comprising the curable resin film according to on one surface of a first supporting sheet. The present invention relates to a curable resin film and a first protective film forming sheet using the same.Priority is claimed on Japanese Patent Application No. 2015-217108, filed on Nov. 4, 2015, the disclosure of which is incorporated herein by reference.In the related art, in a case in which a multi-pin LSI package, which is used in MPU or a gate array, is mounted on a printed wiring board, a flip chip mounting method in which a semiconductor chip in which convex electrodes (bumps) made of eutectic solder, high-temperature solder, gold, or the like are formed in connection pad portions is used, and these bumps are made to face, brought into contact with, and melting/diffusion-joined to the corresponding terminal portions on a chip mounting substrate using a so-called face down method has been employed.The semiconductor chip that is used in this mounting method is obtained by, for example, grinding a surface opposite to a circuit surface of a ...

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device. 113-. (canceled)14. A manufacturing method of a semiconductor device , comprising the steps of:(a) providing a semiconductor wafer equipped with a plurality of device formation regions,each device formation region having a semiconductor circuit, a pad electrically coupled to the semiconductor circuit, a first insulating film formed over the pad such that a surface portion of the pad is exposed from an opening of the first insulating film, and a second insulating film formed over the first insulating film such that the surface portion of the pad is exposed from the second insulating film;(b) contacting a probe needle to a first region of the surface portion of the pad of each device formation region; and(c) after the step (b), forming an interconnect layer over a second region of the surface portion of each pad adjacent to the first region by plating, such that the interconnect layer is electrically coupled to the pad at the second region.15. The manufacturing method of a semiconductor device according to claim 14 , further comprising the steps of:(d) after the step (c), coupling a conductive member to one end portion of the ...

SURFACE FINISH ON TRACE FOR A THERMAL COMPRESSION FLIP CHIP (TCFC)

Some implementations provide a semiconductor device that includes a substrate coupled to a die through a thermal compression bonding process. The semiconductor device also includes a trace coupled to the substrate. The trace includes a first conductive material having a first oxidation property. The trace also includes a first surface layer including a second conductive material having a second oxidation property. The second oxidation property is less susceptible to oxidation than the first oxidation property. The first and second conductive materials are configured to provide an electrical path between the die and the substrate. The first surface layer has a thickness that is microns (μm) or less. 1. A semiconductor device comprising:a substrate coupled to a die through a thermal compression bonding process; anda trace coupled to the substrate, the trace comprising a first conductive material having a first oxidation property, and a first surface layer comprising a second conductive material having a second oxidation property, the second oxidation property being less susceptible to oxidation than the first oxidation property, the first and second conductive materials configured to provide an electrical path between the die and the substrate, the first surface layer having a thickness that is 0.3 microns (μm) or less.2. The semiconductor device of claim 1 , wherein the second material is palladium claim 1 , the thickness of the palladium being 0.2 microns (μm) or less claim 1 ,3. The semiconductor device of claim 2 , wherein the first surface layer made palladium is coupled to the trace using an electroless plating process.4. The semiconductor device of claim 1 , wherein the trace further includes a second surface layer made of a third conductive material.5. The semiconductor device of claim 4 , wherein the second material is palladium and the third material is gold. claim 4 , the thickness of the palladium first surface layer being 0.1 microns (μm) or less claim 4 ...

Semiconductor Devices and Methods for Forming a Semiconductor Device

A semiconductor device includes an electrically conductive contact pad structure. Moreover, the semiconductor device includes a bond structure. The bond structure is in contact with the electrically conductive contact pad structure at least at an enclosed interface region. Additionally, the semiconductor device includes a degradation prevention structure laterally surrounding the enclosed interface region. The degradation prevention structure is vertically located between a portion of the bond structure and a portion of the electrically conductive contact pad structure.

Semiconductor chip, display panel, and electronic device

A semiconductor chip, a display device or an electronic device includes a substrate, one or more conductive pads disposed on the substrate, and one or more bumps electrically connected to the one or more conductive pads, in which the one or more bumps includes a metal core, a polymer layer disposed over a surface of the metal core, and a conductive coating layer disposed over a surface of the polymer layer and electrically connected to the one or more conductive pads.

Semiconductor package and method for manufacturing the same

A semiconductor package structure includes at least one semiconductor die, at least one conductive pillar, an encapsulant and a circuit structure. The semiconductor die has an active surface. The conductive pillar is disposed adjacent to the active surface of the semiconductor die. The encapsulant covers the semiconductor die and the conductive pillar. The encapsulant defines at least one groove adjacent to and surrounding the conductive pillar. The circuit structure is electrically connected to the conductive pillar.

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES

In one example, a semiconductor device can comprise a unit substrate comprising a unit conductive structure and a unit dielectric structure, and an electronic component coupled to the unit conductive structure. The unit substrate can comprise a portion of a singulated subpanel substrate of a panel substrate. Other examples and related methods are also disclosed herein. 1. A method , comprising:providing a subpanel substrate on a subpanel base, the subpanel substrate comprising a dielectric structure and a conductive structure, wherein the subpanel substrate comprises a singulated portion of a panel substrate; a first electronic component on a first side of the subpanel substrate and electrically coupled to a first portion of the conductive structure, and', 'a second electronic component on the first side of the subpanel substrate and electrically coupled to a second portion of the conductive structure;, 'providingremoving the subpanel base; a first external interconnect on a second side of the subpanel substrate and electrically coupled to the first portion of the conductive structure, and', 'a second external interconnect on the second side of the subpanel substrate and electrically coupled to the second portion of the conductive structure; and, 'providingsingulating the subpanel substrate to provide individual unit substrates.2. The method of claim 1 , further comprising providing a subpanel body on a top side of the subpanel substrate contacting a lateral side of the first electronic component and a lateral side of the second electronic component.3. The method of claim 1 , further comprising providing a first metal lid on a top side of the subpanel substrate over the first electronic component and electrically coupled to the first portion of the conductive structure claim 1 , and a second metal lid on the top side of the subpanel substrate over the second electronic component and electrically coupled to the second portion of the conductive structure.4. The method ...

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

Semiconductor devices and methods for fabricating the same are provided. For example, the semiconductor device includes a substrate, a first contact pad formed on the substrate, an insulation layer formed on the substrate and including a first opening which exposes the first contact pad, a first bump formed on the first contact pad and electrically connected to the first contact pad, and a reinforcement member formed on the insulation layer and adjacent to a side surface of the first lower bump. The first bump includes a first lower bump and a first upper bump, which are sequentially stacked on the first contact pad. 1. A semiconductor device comprising:a substrate;a first contact pad on the substrate;an insulation layer on the substrate, the insulation layer including a first opening which exposes the first contact pad;a first bump on the first contact pad and electrically connected to the first contact pad, the first bump including a first lower bump and a first upper bump; anda reinforcement member on the insulation layer and adjacent to a side surface of the first lower bump.2. The semiconductor device of claim 1 , wherein the first lower bump includes a first part having a first width and a second part having a second width claim 1 , the second width greater than the first width claim 1 , the first part filling the first opening claim 1 , and the second part being higher than the insulation layer and surrounded by the reinforcement member.3. The semiconductor device of claim 2 , wherein the second part has a pillar shape claim 2 , and includes a first surface facing the insulation layer claim 2 , and a second surface connecting the first surface to a side surface of the second part.4. The semiconductor device of claim 3 , wherein a cross-section between the second surface and the insulation layer is wedge-shaped claim 3 , and a portion of the reinforcement member is interposed between the second surface and the insulation layer.5. The semiconductor device of ...

Semiconductor Device and Method of Self-Confinement of Conductive Bump Material During Reflow Without Solder Mask

A semiconductor device has a semiconductor die with a die bump pad and substrate with a trace line and integrated bump pad. Conductive bump material is deposited on the substrate bump pad or die bump pad. The semiconductor die is mounted over the substrate so that the bump material is disposed between the die bump pad and substrate bump pad. The bump material is reflowed without a solder mask around the die bump pad or substrate bump pad to form an interconnect. The bump material is self-confined within a footprint of the die bump pad or substrate bump pad. The bump material can be immersed in a flux solution prior to reflow to increase wettability. Alternatively, the interconnect includes a non-fusible base and fusible cap. The volume of bump material is selected so that a surface tension maintains self-confinement of the bump material within the bump pads during reflow.

FLIP-CHIP HIGH SPEED COMPONENTS WITH UNDERFILL

A flip-chip manufacture is described. Methods of blocking adhesive underfill in flip-chip high speed component manufacture include creating topology discontinuities to prevent adhesive underfill material from interacting with RF sensitive regions on substrates. 1. A flip-chip structure utilizing two adjacent layers , the flip-chip structure comprising:at least one topology discontinuity formed, on at least one of a pair of opposed surfaces of the two adjacent layers, outside at least one sensitive region of the flip-chip structure; andadhesive underfill material, between the pair of opposed surfaces, substantially outside the at least one sensitive region to create a substantially adhesive underfill material-free region.2. The flip-chip structure as claimed in claim 1 , the topology discontinuity being configured to snag a liquid meniscus of the adhesive underfill material.3. The flip-chip structure as claimed in claim 1 , the topology discontinuity being configured to snag a liquid meniscus of a non-adhesive underfill material immiscible with the adhesive underfill material.4. The flip-chip structure as claimed in claim 1 , wherein the substantially adhesive underfill material-free region is vented.5. The flip-chip structure as claimed in claim 1 , further comprising a via in a one of the layers configured to vent the at least one adhesive underfill material free region.6. The flip-chip structure as claimed in claim 1 , the topology discontinuity comprising one of a surface variation and a surface roughness.7. The flip-chip structure as claimed in claim 6 , the surface variation comprising a protruding patterned material layer comprising one of Al claim 6 , Au claim 6 , Cr claim 6 , Cu claim 6 , Ni claim 6 , Pd claim 6 , Pt claim 6 , Ti claim 6 , TW claim 6 , W claim 6 , Al203 claim 6 , AlN claim 6 , SiO2 claim 6 , Si3N4 claim 6 , SixNOy claim 6 , Polyimide claim 6 , polyamide claim 6 , patternable polymer and epoxy.8. The flip-chip structure as claimed in claim 6 ...

WIRING BOARD AND ELECTRONIC DEVICE

A wiring board includes: a connection pad; an insulating layer that covers the connection pad and has an opening portion exposing a portion of the connection pad; and a metal pin that is disposed on the insulating layer and that is connected to the connection pad through a metal bonding material provided in the opening portion. The opening portion includes a main opening portion, and a plurality of protrusive opening portions that communicate with the main opening portion and that protrude outward from an outer circumference of the main opening portion. An outer circumference of a lower end surface of the metal pin, which is opposed to the insulating layer, is located outside the outer circumference of the main opening portion. 1. A wiring board comprising:a connection pad;an insulating layer that covers the connection pad and has an opening portion exposing a portion of the connection pad; anda metal pin that is disposed on the insulating layer and that is connected to the connection pad through a metal bonding material provided in the opening portion,wherein the opening portion comprises a main opening portion, and a plurality of protrusive opening portions that communicate with the main opening portion and that protrude outward from an outer circumference of the main opening portion, andan outer circumference of a lower end surface of the metal pin, which is opposed to the insulating layer, is located outside the outer circumference of the main opening portion.2. The wiring board according to claim 1 , whereinthe plurality of protruding opening portions comprise:a first protrusive opening portion that protrudes outward from the outer circumference of the main opening portion in a first direction;a second protrusive opening portion that protrudes outward from the outer circumference of the main opening portion in the first direction, wherein the second protrusive opening portion is opposed to the first protrusive opening portion;a third protrusive opening portion ...

RADAR MODULE WITH WAFER LEVEL PACKAGE AND UNDERFILL

A semiconductor radar module includes an integrated circuit (IC) radar device embedded within a wafer level package compound layer, the wafer level package compound layer extending at least partially lateral to the IC radar device. An interface layer abutting the wafer level package compound layer comprises a redistribution layer coupled to the IC radar device for connecting the IC radar device externally. An underfill material extends between the interface layer and an external substrate and abuts the interface layer and the external substrate. The interface layer is disposed between the wafer level package compound layer and the underfill material. 1. A semiconductor radar module comprising:an integrated circuit (IC) radar device embedded within a wafer level package compound layer, the wafer level package compound layer extending at least partially lateral to the IC radar device;an interface layer abutting the wafer level package compound layer, wherein the interface layer comprises a redistribution layer coupled to the IC radar device for connecting the IC radar device externally, andan underfill material, extending between the interface layer and an external substrate and abutting the interface layer and the external substrate, wherein the interface layer is disposed between the wafer level package compound layer and the underfill material.2. The semiconductor radar module of further comprising claim 1 ,a 3D interconnect structure to contact the external substrate.3. The semiconductor radar module of claim 2 , wherein the 3D interconnect structure extends within the underfill material.4. The semiconductor radar module of claim 2 , wherein the 3D interconnect structure is a solder ball.5. The semiconductor radar module of claim 2 , wherein the underfill material comprises an organic material.6. The semiconductor radar module of claim 2 , wherein the underfill material comprises epoxy material.7. The semiconductor radar module of claim 1 , wherein the IC radar ...

Semiconductor device, manufacturing method for semiconductor device, electronic component, circuit substrate, and electronic apparatus

A semiconductor device includes an integrated circuit that is disposed at a first face side of a semiconductor substrate, the semiconductor substrate having a first face and a second face, the second face opposing the first face, the semiconductor substrate having a through hole from the first face to the second face; an external connection terminal that is disposed at the first face side; a conductive portion that is disposed in the through hole, the conductive portion being electrically connected to the external connection terminal; and an electronic element that is disposed at a second face side.

SEMICONDUCTOR PACKAGE

Provided is a semiconductor package, including: a lower package to which elements are mounted; a metal post connected to the lower package and including at least one metal material portion; and an upper package to which elements is mounted, and which is connected to the metal post via a solder ball. 1. A semiconductor package , comprising:a lower package to which elements are mounted;a metal post connected to the lower package and including at least one metal material portion; andan upper package to which elements is mounted, and which is connected to the metal post via a solder ball.2. The semiconductor package of claim 1 , wherein the metal material portion has a surface treatment layer formed on a surface thereof.3. The semiconductor package of claim 2 , wherein the surface treatment layer is formed an upper surface and a side of the metal post.4. The semiconductor package of claim 2 , wherein the surface treatment layer is made of at least one metal material of Au and Ni.5. The semiconductor package of claim 1 , wherein the metal post is configured such that a width of one end of the metal post connected to the solder ball is smaller than that of another end.6. The semiconductor package of claim 1 , wherein a width of the metal post increases gradually from the one end connected to the solder ball to the other end.7. The semiconductor package of claim 1 , wherein the metal post is configured such that a width of one end is formed in 50% to 90% of a width of another end.8. The semiconductor package of claim 1 , wherein the metal post is configured such that a surface in a longitudinal direction is inclined at an angle of 5° to 45° with respect to a surface of a substrate of the lower package.9. The semiconductor package of claim 1 , wherein the one end of the metal post connected to the solder ball is entered into the solder ball.10. The semiconductor package of claim 1 , wherein the metal post is made of at least one material of Cu claim 1 , Sn claim 1 , Pb ...

Semiconductor Die Contact Structure and Method

A system and method for forming a semiconductor die contact structure is disclosed. An embodiment comprises a top level metal contact, such as copper, with a thickness large enough to act as a buffer for underlying low-k, extremely low-k, or ultra low-k dielectric layers. A contact pad or post-passivation interconnect may be formed over the top level metal contact, and a copper pillar or solder bump may be formed to be in electrical connection with the top level metal contact. 1. A method of manufacturing a semiconductor device , the method comprising:forming a conductive material within a first passivation layer over a semiconductor substrate, the first passivation layer having a height greater than 15,000 Å, the conductive material having a constant composition;depositing a second passivation layer on the first passivation layer, the second passivation layer covering the conductive material;patterning the second passivation layer to form a first opening extending to a top surface of the conductive material;forming a polyimide coating over the second passivation layer;patterning the polyimide coating to expose at least a portion of the conductive material; andforming an external contact in electrical contact with the conductive material, a portion of the external contact being interposed between sidewalls of the polyimide coating.2. The method of further comprising forming a conductive contact on the conductive material claim 1 , the conductive contact comprising a saddle profile in a cross section view.3. The method of further comprising forming an underbump metallization under the external contact claim 1 , the underbump metallization comprising a U shape in a cross section view.4. The method of further comprising forming the first passivation layer over the semiconductor substrate to a thickness in a range of 0.6 μm to 1.4 μm.5. The method of claim 4 , wherein forming the first passivation layer comprises a plasma enhanced chemical vapor deposition process.6. ...

SEMICONDUCTOR METHOD FOR FORMING SEMICONDUCTOR STRUCTURE HAVING BUMP ON TILTING UPPER CORNER SURFACE

A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate and a first conductive bump. The semiconductor substrate has an integrated circuit and an interconnection metal layer, and a tilt surface is formed on an edge of the semiconductor substrate. The first conductive bump is electrically connected to the integrated circuit via the interconnection metal layer, and is disposed on the tilt surface, wherein a profile of the first conductive bump extends beyond a side surface of the edge of the semiconductor layer. 1. A method for forming a semiconductor device , the method comprising:forming a tilt surface on an edge each of at least one semiconductor substrate having an integrated circuit and an interconnection metal layer; andforming a first conductive bump on the tilt surface, wherein the first conductive bump is electrically connected to the integrated circuit via the interconnection metal layer, and a profile of the first conductive bump extends beyond a side surface of the edge.2. The method for forming a semiconductor device of claim 1 , wherein the at least one semiconductor substrate includes two semiconductor substrates claim 1 , the method further comprising:jointing the first conductive bumps of the two semiconductor substrates so as to connect the two semiconductor structures laterally.3. The method for forming a semiconductor device of claim 1 , wherein forming the tilt surface on the edge of the at least one semiconductor substrate comprises:providing a substrate;forming a passivation layer on the substrate;forming an inclined plane on an edge of the substrate;forming a metal layer on the passivation layer;patterning the metal layer to form a first conductor layer on the passivation layer, wherein an upper surface of a portion of the first conductor layer on the edge of the substrate is the tilt surface;forming a second conductor layer on the passivation layer and the first conductor layer, wherein the second ...

Tin-zinc microbump structures and method of making same

Techniques and mechanisms for providing effective connectivity with surface level microbumps on an integrated circuit package substrate. In an embodiment, different metals are variously electroplated to form a microbump which extends through a surface-level dielectric of a substrate to a seed layer including copper. The microbump includes a combination of tin and zinc that mitigates precipitation of residual copper by promoting the formation of miconstituents in the microbump. In another embodiment, the microbump has a mass fraction of zinc, or a mass fraction of tin, that is different in various regions along a height of the microbump.

METHOD OF MANUFACTURING WAFER LEVEL LOW MELTING TEMPERATURE INTERCONNECTIONS

A method of manufacturing a wafer assembly includes forming an array of planar wafer level metal posts extending from a surface of a substrate of a first wafer. After forming the array of posts, an oxide layer is applied over the surface of the first wafer and around the array of posts, the oxide layer being applied at a temperature of below 150 degrees Celsius. 1. A method of manufacturing an array of planar wafer level metal posts comprising:plating an array of posts within a photoresist (PR) pattern mold on a substrate of a first wafer;stripping the PR pattern mold from the substrate and array of posts;applying an oxide layer, at a temperature of below 150 degrees Celsius, over a surface of the first wafer and around the array of posts extending from the surface; andapplying chemical-mechanical polishing (CMP) to planarize the oxide layer and the array of posts.2. The method of further comprising claim 1 , after the step of stripping the pattern mold claim 1 , applying a PR layer around each of the posts.3. The method of further comprising claim 2 , after the step of applying a PR layer claim 2 , etching a metal seed layer on the substrate to singulate the array of posts.4. The method of further comprising claim 3 , after the step of etching a metal seed layer claim 3 , stripping the PR layer.5. The method of further comprising claim 2 , after the step of applying CMP claim 2 , protecting exposed surfaces of the array of posts with a second PR layer.6. The method of further comprising claim 5 , after the step of protecting exposed surfaces of the array of posts claim 5 , cleaning a surface of the oxide layer.7. The method of wherein claim 6 , in the step of cleaning a surface of the oxide layer claim 6 , the surface is cleaned by applying HCl.8. The method of wherein claim 1 , in the step of applying an oxide layer claim 1 , the oxide layer is applied at a temperature of between 127 degrees Celsius and 147 degrees Celsius.9. The method of wherein claim 1 , in the ...

Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices

Microelectronic devices and method of forming a plurality of microelectronic devices on a semiconductor workpiece are disclosed herein. One such method includes placing a plurality of first interconnect elements on a side of a semiconductor workpiece, forming a layer on the side of the workpiece, reshaping the first interconnect elements by heating the first interconnect elements, and coupling a first portion of a plurality of individual second interconnect elements to corresponding first interconnect elements with a second portion of the individual second interconnect elements exposed.

SEMICONDUCTOR PACKAGE

A semiconductor package including an insulating layer, a chip, a thermal interface material, a heat-dissipating cover and a re-distribution layer is provided. The insulating layer has an accommodating opening. The chip is disposed in the accommodating opening. The chip has an active surface, a back surface opposite to the active surface and a side surface connected to the active surface and the back surface. The thermal interface material is filled in the accommodating opening for at least encapsulating the side surface of the chip and exposing the active surface. The re-distribution layer and the heat-dissipating cover are disposed on two side of the insulating layer respectively. The heat-dissipating cover is thermally coupled to the chip through the thermal interface material. The re-distribution layer directly covers the insulating layer, the active surface of the chip and the thermal interface material, and the re-distribution layer is electrically connected to the chip. 1. A semiconductor package , comprising:an insulating layer, having an accommodating opening;a chip, disposed in the accommodating opening, the chip having an active surface, a back surface opposite to the active surface and a side surface connected to the active surface and the back surface;a thermal interface material, filled in the accommodating opening for at least encapsulating the side surface of the chip and exposing the active surface;a heat-dissipating cover; anda re-distribution layer, wherein the re-distribution layer and the heat-dissipating cover are disposed on two side of the insulating layer respectively, the heat-dissipating cover is thermally coupled to the chip through the thermal interface material, and the re-distribution layer directly covers the insulating layer, the active surface of the chip and the thermal interface material, and the re-distribution layer is electrically connected to the chip.2. The semiconductor package according to claim 1 , wherein the thermal ...

SEMICONDUCTOR PACKAGE WITH EMBEDDED CAPACITOR AND METHODS OF MANUFACTURING SAME

A semiconductor package with an embedded capacitor and corresponding manufacturing methods are described. The semiconductor package with the embedded capacitor includes a semiconductor die having a first metal layer extending across at least a portion of a first side of the semiconductor die and a package structure formed on the first side of the semiconductor die. A first electrical conductor of the embedded capacitor is formed in the first metal layer of the semiconductor die. The package structure includes a second metal layer that has formed therein a second electrical conductor of the embedded capacitor. A dielectric of the embedded capacitor is positioned within either the semiconductor die or the package structure of the semiconductor package to isolate the first electrical conductor from the second electrical conductor of the embedded capacitor. 1. A semiconductor package with an embedded capacitor , the semiconductor package comprising:a semiconductor die having a first metal layer extending across at least a portion of a first side of the semiconductor die, wherein a first electrical conductor of a first embedded capacitor is formed in the first metal layer;a package structure formed on the first side of the semiconductor die, wherein the package structure comprises a second metal layer, wherein a second electrical conductor of the first embedded capacitor is formed at least partially in the second metal layer; anda first dielectric of the first embedded capacitor positioned for isolating the first electrical conductor from the second electrical conductor.2. The semiconductor package of claim 1 , wherein the first metal layer is a finally-formed metal layer of the semiconductor die.3. The semiconductor package of claim 1 , wherein the semiconductor die is one of a plurality of semiconductor die embedded in a reconstituted semiconductor die panel claim 1 , and the package structure is one of a plurality of package structures formed on the reconstituted ...

Semiconductor Device

Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion () formed on the upper surface of a semiconductor substrate (), a passivation layer () so formed on the upper surface of the semiconductor substrate () as to overlap a part of the electrode pad portion () and having a first opening portion () where the upper surface of the electrode pad portion () is exposed, a barrier metal layer () formed on the electrode pad portion (), and a solder bump () formed on the barrier metal layer (). The barrier metal layer () is formed such that an outer peripheral end () lies within the first opening portion () of the passivation layer () when viewed in plan. 110.-. (canceled)11. A semiconductor device comprising: an electrode pad portion on a face of a substrate;', 'a first protection layer including a first opening through which a top face of the electrode pad portion is exposed, the first protection layer disposed on the face of the substrate and overlapping part of the electrode pad portion;', 'a barrier metal layer on the electrode pad portion;', 'a second protection layer covering a region on the first protection layer and a region on the electrode par portion; and', 'a plurality of bump electrodes on the barrier metal layer;, 'a semiconductor chip includinga circuit board on which the semiconductor chip is mounted, the circuit board having, formed on a first face thereof facing the semiconductor chip, a connection pad portion connected to the bump electrodes;a plurality of electrode terminals formed on a second face of the circuit board facing away from the semiconductor chip, the electrode terminals being electrically connected to the connection pad portion; anda resin member filling a gap between the semiconductor chip and the circuit board,wherein the barrier metal layer has a circumferential end part thereof formed inward of the first opening in the first protection layer as seen in a plan ...

Solder-Pinning Metal Pads for Electronic Components

Solder-pinning metal pads for electronic components and techniques for use thereof to mitigate de-wetting are provided. In one aspect, a structure includes: a substrate; and a solder pad on the substrate, wherein the solder pad has sidewalls extending up from a surface thereof. For instance, the sidewalls can be present at edges of the solder pad, or inset from the edges of the solder pad. The sidewalls can be vertical or extend up from the solder pad at an angle. The sidewalls can be formed from the same material or a different material as the solder pad. A method is also provided that includes forming a solder pad on a substrate, the solder pad comprising sidewalls extending up from a surface thereof. 1. A structure , comprising:a substrate; anda solder pad on the substrate, wherein the solder pad has sidewalls extending up from a surface thereof.2. The structure of claim 1 , wherein the solder pad comprises at least one metal selected from the group consisting of: as nickel (Ni) claim 1 , copper (Cu) claim 1 , gold (Au) claim 1 , titanium (Ti) chromium (Cr) claim 1 , iron (Fe) claim 1 , platinum (Pt) claim 1 , palladium (Pd) claim 1 , ruthenium (Ru) claim 1 , and combinations thereof.3. The structure of claim 1 , wherein the sidewalls are present at edges of the solder pad.4. The structure of claim 1 , wherein the sidewalls are inset from edges of the solder pad.5. The structure of claim 1 , wherein the sidewalls are vertical.6. The structure of claim 1 , wherein the sidewalls extend up from the solder pad at an angle of greater than 10 degrees.7. The structure of claim 1 , wherein the sidewalls comprise a different material from the solder pad.8. The structure of claim 1 , wherein the substrate comprises a cavity formed therein claim 1 , and wherein the solder pad is disposed in the cavity.9. The structure of claim 8 , wherein the cavity is formed having a depth D of from 1 μm to 10 μm and ranges therebetween claim 8 , and a width W of from 30 μm to 300 μm and ...

Semiconductor Device and Method of Using a Standardized Carrier in Semiconductor Packaging

A semiconductor device has a carrier with a fixed size. A plurality of first semiconductor die is singulated from a first semiconductor wafer. The first semiconductor die are disposed over the carrier. The number of first semiconductor die on the carrier is independent from the size and number of first semiconductor die singulated from the first semiconductor wafer. An encapsulant is deposited over and around the first semiconductor die and carrier to form a reconstituted panel. An interconnect structure is formed over the reconstituted panel while leaving the encapsulant devoid of the interconnect structure. The reconstituted panel is singulated through the encapsulant. The first semiconductor die are removed from the carrier. A second semiconductor die with a size different from the size of the first semiconductor die is disposed over the carrier. The fixed size of the carrier is independent of a size of the second semiconductor die.

ROOM TEMPERATURE METAL DIRECT BONDING

A bonded device structure including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads formed by contact bonding of the first non-metallic region to the second non-metallic region. At least one of the first and second substrates may be elastically deformed. 1. A bonded structure comprising:a first plurality of metallic pads disposed on a first substrate;a first non-metallic region located on a first surface of said first substrate proximate to the first plurality of metallic pads;a second plurality of metallic pads disposed on a second substrate; anda second non-metallic region located on a second surface of the second substrate proximate to the second plurality of metallic pads,wherein a portion of each metallic pad of the first plurality of metallic pads directly contacts a corresponding metallic pad of the second plurality of metallic pads to form a metallic contact, andwherein the first non-metallic region contacts and is directly bonded to the second non-metallic region along an interface, the interface between the first non-metallic region and the second non-metallic region extending substantially to the metallic contact.2. The bonded structure of claim 1 , wherein each metallic pad comprises a reflowable material.3. The bonded structure of claim 1 , wherein the first non-metallic region comprises silicon oxide. This application is a continuation of application Ser. No. 14/959,204 filed Dec. 4, 2015, which is a continuation of application Ser. No. 14/474,476 ...

PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME

A package structure and a method of forming the same are provided. The package structure includes a die, an encapsulant, and an RDL structure. The encapsulant is laterally encapsulating the die. The RDL structure is electrically connected to the die. The RDL structure includes a first dielectric layer, a first RDL, a second dielectric layer and a second RDL. The first dielectric layer is disposed on the encapsulant and the die. The first RDL is embedded in the first dielectric layer. The first RDL includes a first via and a first trace connected to each other. A top surface of the first RDL is coplanar with a top surface of the first dielectric layer. The second dielectric layer is on the first dielectric layer and the first RDL. The second RDL is embedded in the second dielectric layer and includes a second via and a second trace connected to each other. A top surface of the second RDL is coplanar with a top surface of the second dielectric layer. The second via is stacked directly on the first via. 1. A package structure , comprising:a die;an encapsulant, laterally encapsulating the die; a first dielectric layer on the encapsulant and the die;', 'a first RDL embedded in the first dielectric layer and comprising a first via and a first trace connected to each other, wherein a top surface of the first RDL is coplanar with a top surface of the first dielectric layer;', 'a second dielectric layer on the first dielectric layer and the first RDL; and', 'a second RDL embedded in the second dielectric layer and comprising a second via and a second trace connected to each other, wherein a top surface of the second RDL is coplanar with a top surface of the second dielectric layer,, 'a redistribution layer (RDL) structure electrically connected to the die, comprisingwherein the second via is stacked directly on the first via.2. The package structure of claim 1 , wherein the top surface of the first RDL is coplanar with an interface between the first dielectric layer and the ...

METHOD FOR FABRICATING ELECTRONIC PACKAGE

An electronic package and a method for fabrication the same are provided. The method includes: disposing an electronic component on a substrate; forming an encapsulant layer on the substrate to encapsulate the electronic component; and forming a shielding layer made of metal on the encapsulant layer. The shielding layer has an extending portion extending to a lateral side of the substrate along a corner of the encapsulant layer, without extending to a lower side of the substrate. Therefore, the present disclosure prevents the shielding layer from coming into contact with conductive pads disposed on the lower side of the substrate and thereby avoids a short circuit from occurrence. 17-. (canceled)8. A method for fabricating an electronic package , comprising:providing a substrate having a first side, a second side opposite to the first side, and a lateral side adjacent to the first side and the second side;disposing an electronic component on the first side of the substrate, and electrically connecting the electronic component to the substrate;forming on the substrate an encapsulant layer encapsulating the electronic component and having a first surface bonded to the first side of the substrate, a second surface opposite to the first surface, and a side surface adjacent to the first surface and the second surface; andforming on the second surface of the encapsulant layer a shielding layer having an extending portion extending from a portion of an edge of the second surface of the encapsulant layer to the lateral side of the substrate along the side surface of the encapsulant layer, the extending portion being free from extending to the second side of the substrate, with a portion of the side surface of the encapsulant layer and a portion of the lateral side of the substrate exposed from the shielding layer.9. The method of claim 8 , wherein the substrate has a plurality of conductive pads exposed from the second side of the substrate.10. The method of claim 8 , ...

PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

A package structure includes a redistribution layer, a chip, an encapsulant, a plurality of under ball release layers, and a plurality of solder balls. The redistribution layer includes a first surface, a second surface opposite to the first surface, and a patterned circuit layer, wherein the patterned circuit layer includes a plurality of pads protruding from the first surface. The chip is disposed on the second surface and electrically connected to the patterned circuit layer. The encapsulant is disposed on the second surface and encapsulates the chip. The under ball release layers cover the pads respectively. The solder balls are disposed on the under ball release layers and electrically connected to the pads. 1. A package structure , comprising:a redistribution layer having a first surface, a second surface opposite to the first surface, and a patterned circuit layer, wherein the patterned circuit layer comprises a plurality of pads protruding from the first surface;a chip disposed on the second surface and electrically connected to the patterned circuit layer;an encapsulant disposed on the second surface and encapsulating the chip;a plurality of under ball release layers respectively covering the pads protruding from the first surface; anda plurality of solder balls respectively disposed on the under ball release layers and electrically connected to the pads.2. The package structure according to claim 1 , wherein each of the under ball release layers comprises a contact surface in contact with each of the solder balls claim 1 , and each of the pads comprises an outer surface facing away from the first surface claim 1 , wherein an area of the contact surface is greater than an area of the outer surface.3. The package structure according to claim 1 , wherein a surface roughness of each of the under ball release layers is less than a surface roughness of each of the pads.4. The package structure according to claim 1 , wherein a material of each of the under ball ...

Semiconductor Die Contact Structure and Method

A system and method for forming a semiconductor die contact structure is disclosed. An embodiment comprises a top level metal contact, such as copper, with a thickness large enough to act as a buffer for underlying low-k, extremely low-k, or ultra low-k dielectric layers. A contact pad or post-passivation interconnect may be formed over the top level metal contact, and a copper pillar or solder bump may be formed to be in electrical connection with the top level metal contact.

Semiconductor Die Contact Structure and Method

A system and method for forming a semiconductor die contact structure is disclosed. An embodiment comprises a top level metal contact, such as copper, with a thickness large enough to act as a buffer for underlying low-k, extremely low-k, or ultra low-k dielectric layers. A contact pad or post-passivation interconnect may be formed over the top level metal contact, and a copper pillar or solder bump may be formed to be in electrical connection with the top level metal contact.

Solder Ball Protection in Packages

An integrated circuit structure includes a substrate, a metal pad over the substrate, a passivation layer having a portion over the metal pad, and a polymer layer over the passivation layer. A Post-Passivation Interconnect (PPI) has a portion over the polymer layer, wherein the PPI is electrically coupled to the metal pad. The integrated circuit structure further includes a first solder region over and electrically coupled to a portion of the PPI, a second solder region neighboring the first solder region, a first coating material on a surface of the first solder region, and a second coating material on a surface of the second solder region. The first coating material and the second coating material encircle the first solder region and the second solder region, respectively. The first coating material is spaced apart from the second coating material. 1. An integrated circuit structure comprising:a substrate;a metal feature over the substrate; a solder ball; and', 'a coating material surrounding the solder ball, wherein the coating material comprises metal plated plastic spheres in a dielectric material; and, 'a coated solder region over and electrically coupled to the metal feature, wherein the coated solder region comprisesa partially-looped conductive trace between the substrate and the metal feature, the partially-looped conductive trace underlying the metal feature, wherein a center of the partially-looped conductive trace is aligned to a center of the metal feature.2. The integrated circuit of claim 1 , wherein a first end of the partially-looped conductive trace is spaced apart from a second end of the partially-looped conductive trace by a dielectric material.3. The integrated circuit of claim 2 , wherein the first end of the partially-looped conductive trace is coupled to a positive pole of a power source and the second end of the partially-looped conductive trace is coupled to a negative pole of the power source.4. The integrated circuit of claim 1 , ...

PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME

A package structure and a method of forming the same are provided. The package structure includes a die, an encapsulant, a first polymer material layer, a second polymer material layer and a first redistribution layer. The encapsulant encapsulates sidewalls of the die. The first polymer material layer is on the encapsulant and the die. The second polymer material layer is on the first polymer material layer. The first redistribution layer is embedded in the first polymer material layer and the second polymer material layer and electrically connected to the die. The first redistribution layer has a top surface substantially coplanar with a top surface of the second polymer material layer, and a portion of a top surface of the first polymer material layer is in contact with the first redistribution layer. 1. A package structure , comprising:a die;an encapsulant encapsulating sidewalls of the die;a first polymer material layer on the encapsulant and the die;a second polymer material layer on the first polymer material layer; anda first redistribution layer embedded in the first polymer material layer and the second polymer material layer and electrically connected to the die,wherein the first redistribution layer has a top surface substantially coplanar with a top surface of the second polymer material layer, and a portion of a top surface of the first polymer material layer is in contact with the first redistribution layer.2. The package structure of claim 1 , wherein the first redistribution layer comprises:a via penetrating through the second polymer material layer and the first polymer material layer to connect to the die; anda trace connected to the via and embedded in the second polymer material layer and in contact with the portion of the top surface of the first polymer material layer.3. The package structure of claim 2 , wherein the trace has a thickness substantially equal to a thickness of the second polymer material layer.4. The package structure of claim 2 ...

Semiconductor Device and Method of Using a Standardized Carrier in Semiconductor Packaging

A semiconductor device has a carrier with a fixed size. A plurality of first semiconductor die is singulated from a first semiconductor wafer. The first semiconductor die are disposed over the carrier. The number of first semiconductor die on the carrier is independent from the size and number of first semiconductor die singulated from the first semiconductor wafer. An encapsulant is deposited over and around the first semiconductor die and carrier to form a reconstituted panel. An interconnect structure is formed over the reconstituted panel while leaving the encapsulant devoid of the interconnect structure. The reconstituted panel is singulated through the encapsulant. The first semiconductor die are removed from the carrier. A second semiconductor die with a size different from the size of the first semiconductor die is disposed over the carrier. The fixed size of the carrier is independent of a size of the second semiconductor die. 1. A method of making a semiconductor device , comprising:providing a first semiconductor wafer including a plurality of first semiconductor die;singulating the first semiconductor wafer to separate first semiconductor die;providing a carrier, wherein a size of the carrier is independent of a size of the first semiconductor die and a size of the first semiconductor wafer; anddisposing the first semiconductor die over the carrier in a high-density arrangement.2. The method of claim 1 , further including:providing a second semiconductor wafer including a plurality of second semiconductor die;singulating the second semiconductor wafer to separate the plurality of second semiconductor die; anddisposing one of the plurality of second semiconductor die over the carrier with the first semiconductor die.3. The method of claim 1 , further including depositing an encapsulant over the first semiconductor die and carrier to form a reconstituted panel.4. The method of claim 3 , further including backgrinding the reconstituted panel to remove a ...

Semiconductor package

A semiconductor package includes: a semiconductor chip having an active surface having connection pads disposed thereon; a connection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads; a passivation layer disposed on the connection member; and an underbump metallurgy (UBM) layer embedded in the passivation layer and electrically connected to the redistribution layer of the connection member, wherein the UBM layer includes a UBM pad embedded in the passivation layer, at least one plating layer disposed on the UBM pad and having side surfaces of which at least portions are covered by the UBM pad, and a UBM via penetrating through at least portions of the passivation layer and electrically connecting the redistribution layer of the connection member and the UBM pad to each other.

Integrated circuit, semiconductor device and method of manufacturing same

An integrated circuit includes a first and second semiconductor wafer, a bonding layer, a first and second interconnect structure, an inductor, and a through substrate via. The first semiconductor wafer has a first device in a first side of the first semiconductor wafer. The second semiconductor wafer is over the first semiconductor wafer. The bonding layer is between the first and the second semiconductor wafer. The first interconnect structure is on a second side of the first semiconductor wafer. The inductor is below the first semiconductor wafer. At least a portion of the inductor is within the first interconnect structure. The second interconnect structure is on the first side of the first semiconductor wafer. The through substrate via extends through the first semiconductor wafer. The inductor is coupled to at least the first device by the second interconnect structure and the through substrate via.

SEMICONDUCTOR PACKAGING AND MANUFACTURING METHOD THEREOF

The present disclosure provides a semiconductor package includes a contact pad, a device external to the contact pad and a solder bump on the contact pad. The device has a conductive contact pad corresponding to the contact pad. The solder bump connects the contact pad with the conductive contact pad. The solder bump comprises a height from a top of the solder bump to the contact pad; and a width which is a widest dimension of the solder bump in a direction perpendicular to the height. A junction portion of the solder bump in proximity to the contact pad comprises an hourglass shape. 1. A semiconductor package , comprising:a contact pad;a device external to the contact pad and including a conductive contact pad corresponding to the contact pad; a height from a top of the solder bump to the contact pad; and', 'a width which is a widest dimension of the solder bump in a direction perpendicular to the height; and, 'a solder bump connecting the contact pad with the conductive contact pad, wherein the solder bump compriseswherein a junction portion of the solder bump in proximity to the contact pad comprises an hourglass shape.2. The semiconductor package in claim 1 , further comprising a molding compound surrounding the junction portion and a lower portion of the solder bump claim 1 , wherein a thickness of the molding compound is from about 0.4 times to about 0.6 times of the height of the solder bump claim 1 , and wherein the lower portion of the solder bump is in proximity to the contact pad.3. The semiconductor package in claim 2 , further comprising an underfill layer surrounding an upper portion of the solder bump claim 2 , wherein the upper portion of the solder bump is in proximity to the top of the solder bump.4. The semiconductor package in claim 1 , wherein the height to the width ratio of the solder bump is about from 0.85 to about 1.15.5. The semiconductor package in claim 1 , wherein the junction portion of the solder bump comprises SnX alloys having an ...

Semiconductor Device and Method

A semiconductor device includes a substrate, a first redistribution layer (RDL) over a first side of the substrate, one or more semiconductor dies over and electrically coupled to the first RDL, and an encapsulant over the first RDL and around the one or more semiconductor dies. The semiconductor device also includes connectors attached to a second side of the substrate opposing the first side, the connectors being electrically coupled to the first RDL. The semiconductor device further includes a polymer layer on the second side of the substrate, the connectors protruding from the polymer layer above a first surface of the polymer layer distal the substrate. A first portion of the polymer layer contacting the connectors has a first thickness, and a second portion of the polymer layer between adjacent connectors has a second thickness smaller than the first thickness.

Copper pillar bump having annular protrusion

A copper pillar bump for an electrode pad of a semiconductor chip includes a first copper layer, a first metal layer formed directly on the first copper layer, a second copper layer formed directly on the first metal layer, and a second metal layer formed directly on the second copper layer, wherein the first metal layer and the second metal layer are made of a metal having a different etching rate than copper, wherein an outer perimeter ring of the first metal layer protrudes beyond a lateral surface of the first copper layer, and wherein an outer perimeter ring of the second metal layer protrudes beyond a lateral surface of the second copper layer.

ELECTRONIC COMPONENT AND METHOD OF FABRICATING THE SAME

An electronic component includes: a substrate; a device chip including a functional element located on a lower surface thereof and mounted on an upper surface of the substrate so that the functional element faces the upper surface of the substrate across an air gap; a ring-shaped metal layer located on the upper surface of the substrate and surrounding the device chip in plan view, a side surface of the ring-shaped metal layer being located further in than a side surface of the substrate; a metal sealing portion surrounding the device chip in plan view and bonding with an upper surface of the ring-shaped metal layer, a side surface of the metal sealing portion being located further out than the side surface of the ring-shaped metal layer; and a metal film located on the side surface of the metal sealing portion and the side surface of the ring-shaped metal layer. 1. An electronic component comprising:a substrate;a device chip that includes a functional element located on a lower surface thereof and is mounted on an upper surface of the substrate so that the functional element faces the upper surface of the substrate across an air gap;a ring-shaped metal layer that is located on the upper surface of the substrate and surrounds the device chip in plan view, a side surface of the ring-shaped metal layer being located further in than a side surface of the substrate;a metal sealing portion that surrounds the device chip in plan view and bonds with an upper surface of the ring-shaped metal layer, a side surface of the metal sealing portion being located further out than the side surface of the ring-shaped metal layer; anda metal film located on the side surface of the metal sealing portion and the side surface of the ring-shaped metal layer.2. The electronic component according to claim 1 , wherein a distance between the side surface of the metal sealing portion and the side surface of the ring-shaped metal layer is greater than a film thickness of the metal film.3. The ...

Stacked and Bonded Semiconductor Device

A semiconductor device and method utilizing a dummy structure in association with a redistribution layer is provided. By providing the dummy structure adjacent to the redistribution layer, damage to the redistribution layer may be reduced from a patterning of an overlying passivation layer, such as by laser drilling. By reducing or eliminating the damage caused by the patterning, a more effective bond to an overlying structure, such as a package, may be achieved. 1. A semiconductor device comprising:a first die;an encapsulant in contact with and extending away from a sidewall of the first die;a through via extending through the encapsulant;a passivation layer over the encapsulant and the first die;a first conductive feature and a second conductive feature in the passivation layer, the first conductive feature electrically contacting the through via; anda conductive dummy portion extending from the second conductive feature into the encapsulant, the encapsulant extending along sidewalls and a bottom surface of the conductive dummy portion.2. The device of claim 1 , wherein the conductive dummy portion has a width in a range of 50 μm and 500 μm.3. The device of claim 1 , wherein the conductive dummy portion has a thickness in a range of 0.5 μm and 20 μm.4. The device of claim 1 , wherein the conductive dummy portion comprises tungsten.5. The device of claim 1 , wherein the through via has a thickness in a range of 30 μm and 350 μm.6. The device of further comprising a third conductive feature interposed between the first conductive feature and the through via claim 1 , wherein the third conductive feature and the conductive dummy portion comprise a same combination of one or more conductive layers.7. The device of claim 6 , wherein the encapsulant extends along a sidewall of the third conductive feature.8. A semiconductor device comprising:a first redistribution structure;a die over the first redistribution structure;an encapsulant over the first redistribution ...

SEMICONDUCTOR PACKAGE

A semiconductor package includes a substrate, through-electrodes penetrating the substrate, first bumps spaced apart from each other in a first direction parallel to a top surface of the substrate and electrically connected to the through-electrodes, respectively, and at least one second bump disposed between the first bumps and electrically insulated from the through-electrodes. The first bumps and the at least one second bump constitute one row in the first direction. A level of a bottom surface of the at least one second bump from the top surface of the substrate is a substantially same as levels of bottom surfaces of the first bumps from the top surface of the substrate. 120-. (canceled)21. A semiconductor package , comprising:a substrate;through-electrodes penetrating the substrate;first bumps spaced apart from each other in a first direction parallel to a top surface of the substrate, the first bumps being electrically connected to the through-electrodes, respectively;at least one second bump disposed between the first bumps, the at least one second bump being electrically insulated from the through-electrodes; andan underfill covering the substrate, the first bumps, and the at least one second bump,wherein the first bumps and the at least one second bump constitute one row in the first direction, andwherein at least one second bump is disposed at a higher level from the substrate than the first bumps.22. The semiconductor package as claimed in claim 21 , further comprising:an insulating pattern disposed between the substrate and the at least one second bump.23. The semiconductor package as claimed in claim 22 , wherein the insulating pattern has through-holes overlapping top surfaces of the through-electrodes claim 22 , respectively claim 22 , andwherein the first bumps are provided in the through-holes so as to be electrically connected to the through-electrodes, respectively.24. The semiconductor package as claimed in claim 21 , further comprising:a pad ...

Semiconductor device and method of manufacturing semiconductor device

The present technology relates to a semiconductor device and a method of manufacturing the semiconductor device capable of suppressing warpage of the semiconductor device. A mold release agent 101 is applied to a side surface of an upper chip 11 . According to this, when a sealing resin 31 for protecting a bump 21 is applied, the bump 21 between the upper chip 11 and a lower chip 12 is protected and a fillet-shaped protruding portion does not adhere to the side surface of the upper chip 11 due to the mold release agent 101 , so that a gap 111 is formed. According to this, a stress to warp the lower chip 12 is not generated even when contraction associated with drying of the sealing resin 31 between the side surface of the upper chip 11 and an upper surface of the lower chip 12 occurs, so that it becomes possible to suppress the warpage. The present technology may be applied to the semiconductor device.

INORGANIC DIES WITH ORGANIC INTERCONNECT LAYERS AND RELATED STRUCTURES

Disclosed herein are inorganic dies with organic interconnect layers and related structures, devices, and methods. In some embodiments, an integrated circuit (IC) structure may include an inorganic die and one or more organic interconnect layers on the inorganic die, wherein the organic interconnect layers include an organic dielectric. 1. An integrated circuit (IC) structure , comprising:an inorganic die; andone or more organic interconnect layers on the inorganic die, wherein the organic interconnect layers include an organic dielectric, and the organic dielectric has a loss tangent that is less than 0.01.2. The IC structure of claim 1 , wherein the inorganic die includes an inorganic substrate claim 1 , and the inorganic substrate includes glass claim 1 , ceramic claim 1 , or a semiconductor material.3. The IC structure of claim 1 , wherein the inorganic die includes one or more inorganic interconnect layers claim 1 , and the inorganic interconnect layers include an inorganic dielectric.4. The IC structure of claim 3 , wherein the one or more inorganic interconnect layers are between an inorganic substrate of the inorganic die and the one or more organic interconnect layers.5. The IC structure of claim 4 , wherein the one or more inorganic interconnect layers are one or more first inorganic interconnect layers claim 4 , the inorganic die includes one or more second inorganic interconnect layers claim 4 , and the inorganic substrate is between the one or more first inorganic interconnect layers and the one or more second inorganic interconnect layers.6. The IC structure of claim 3 , wherein an inorganic substrate of the inorganic die is between the one or more inorganic interconnect layers and the one or more organic interconnect layers.7. The IC structure of claim 1 , wherein the inorganic die includes at least one device layer.8. The IC structure of claim 7 , wherein the at least one device layer includes one or more transistors or one or more diodes.9. The IC ...

STRUCTURE OF A SEMICONDUCTOR CHIP WITH SUBSTRATE VIA HOLES AND METAL BUMPS AND A FABRICATION METHOD THEREOF

A structure of a semiconductor chip with substrate via holes and metal bumps and a fabrication method thereof. The structure comprises a substrate, at least one backside metal layer, at least one first metal layer, at least one electronic device, and at least one metal bump. The substrate has at least one substrate via hole penetrating through the substrate. The at least one first metal layer and electronic device are formed on the front side of the substrate. The at least one metal bump is formed on the at least one first metal layer. The at least one backside metal layer is formed on the backside of the substrate covering the inner surface of the substrate via hole and at least part of the backside of the substrate and connected to the first metal layer on the top of the substrate via hole.

SEMICONDUCTOR PACKAGE

A semiconductor package includes a substrate, through-electrodes penetrating the substrate, first bumps spaced apart from each other in a first direction parallel to a top surface of the substrate and electrically connected to the through-electrodes, respectively, and at least one second bump disposed between the first bumps and electrically insulated from the through-electrodes. The first bumps and the at least one second bump constitute one row in the first direction. A level of a bottom surface of the at least one second bump from the top surface of the substrate is a substantially same as levels of bottom surfaces of the first bumps from the top surface of the substrate. 120.-. (canceled)21. A semiconductor package comprising:a substrate;a first chip on the substrate, the first chip has first through-electrodes penetrating the first chip;a second chip on the first chip;bumps between the first chip and the second chip; andan underfill filling a space between the first chip and the second chip, first bumps spaced apart from each other in a first direction parallel to a top surface of the first chip, the first bumps being electrically connected to the through-electrodes, respectively, and', 'at least one second bump between the first bumps, the at least one second bump being electrically insulated from the through-electrodes,, 'wherein the bumps includewherein the first bumps and the at least one second bump constitute one row in the first direction,wherein a level of a bottom surface of the at least one second bump from the top surface of the substrate is a substantially same level as levels of bottom surfaces of the first bumps from the top surface of the substrate, andwherein the underfill covers a space between the first bumps and covers a space between the first bumps and the at least one second bump.22. The semiconductor package as claimed in claim 21 , wherein:the first bumps have a first thickness in a second direction perpendicular to the top surface of ...

Method for manufacturing electronic component

A manufacturing method comprises preparing a bonding substrate having bumps thereon; preparing a mounted member having external conductive members; applying a fixing material to the surface of the bonding substrate and/or to a surface of the mounted member; and fixing the bonding substrate and the mounted member with the fixing material such that the bumps contact the external conductive members. The fixing material is prepared to contain a first compound and a second compound, each having respective viscosities which change depending on their respective temperature profiles; and applying the fixing material to the bonding substrate and/or the mounted member at a temperature lower than a first temperature, and the fixing comprises pressing the bonding substrate against the mounted member when the fixing material has a temperature lower than the first temperature; and heating the fixing material to a temperature higher than the second temperature and curing the fixed material.

HIGH DENSITY SUBSTRATE AND STACKED SILICON PACKAGE ASSEMBLY HAVING THE SAME

An improved interconnect substrate having high density routings for a chip package assembly, a chip package assembly having a high density substrate, and methods for fabricating the same are provided that utilize substrates having a region of high density routings disposed over a region of low density routings. In one example, a method for fabricating an interconnect substrate is provided that includes forming a high density routing region by depositing a seed layer on a top surface of a low density routing region, patterning a mask layer on the seed layer, forming a plurality of conductive posts on the seed layer, removing the mask layer and the seed layer exposed between the conductive posts, and depositing a dielectric layer between the between the conductive posts, wherein at least some of the conductive posts are electrically coupled to conductive routing comprising the low density routing region. 1. A method for fabricating an interconnect substrate for a chip package assembly , the method comprising:forming a low density routing region; and depositing a first seed layer on the top surface of the low density routing region;', 'patterning a first mask layer on the first seed layer;', 'forming a plurality of first conductive posts on the first seed layer;', 'removing the first mask layer and the first seed layer exposed between the plurality of first conductive posts; and', 'depositing a first dielectric layer between the between the plurality of first conductive posts, wherein at least some of the plurality of first conductive posts are electrically coupled to conductive routing comprising the low density routing region., 'forming a high density routing region on a top surface of the low density routing region, wherein forming the high density routing region comprises2. The method of further comprising:thinning the first dielectric layer.3. The method of claim 2 , wherein thinning further comprises:etching, polishing or grinding the first dielectric layer.4. ...

PACKAGE MODULE

A package module includes a core structure including a frame having a penetrating portion, an electronic component disposed in the penetrating portion, and an insulating material covering at least a portion of each of the frame and the electronic component and filling at least a portion of the penetrating portion. The core structure further has a recessed portion in which a stopper layer is disposed on a bottom surface of the recessed portion. A semiconductor chip has a connection pad and is disposed in the recessed portion such that an inactive surface faces the stopper layer. An encapsulant covers at least a portion of each of the core structure and the semiconductor chip, and fills at least a portion of the recessed portion. An interconnect structure is disposed on the core structure and an active surface of the semiconductor chip, and includes a redistribution layer. 1. A package module , comprising:a core structure including a frame having a penetrating portion, an electronic component disposed in the penetrating portion, and an insulating material covering at least a portion of each of the frame and the electronic component and filling at least a portion of the penetrating portion, and the core structure further having a recessed portion in which a stopper layer is disposed on a bottom surface of the recessed portion;a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, and disposed in the recessed portion such that the inactive surface faces the stopper layer;an encapsulant covering at least a portion of each of the core structure and the semiconductor chip, and filling at least a portion of the recessed portion; andan interconnect structure disposed on the core structure and the active surface of the semiconductor chip, and including a redistribution layer electrically connected to the electronic component and the connection pad.2. The package module of claim 1 ,wherein the ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME, AND STACKED SEMICONDUCTOR DEVICE

A semiconductor device includes: a semiconductor substrate; a through silicon via which penetrates the semiconductor substrate; an insulating film which is provided between a side surface of the through silicon via and the semiconductor substrate; and a MOS transistor which is provided on the semiconductor substrate, wherein: the semiconductor substrate has a first crystal axis and a second crystal axis, and a propagation amount of stress occurring from the through silicon via is larger in a direction of the first crystal axis than in a direction of the second crystal axis; and the insulating film has a thickness in a direction of a diameter of the through silicon via being a thickness along the direction of the first crystal axis larger than a thickness along the direction of the second crystal axis. 1. A semiconductor device comprising:a semiconductor layer;a through silicon via configured to penetrate the semiconductor layer;an insulating film configured to be provided between a side surface of the through silicon via and the semiconductor layer; anda functional element configured to be provided on the semiconductor layer, wherein:the semiconductor layer has a first crystal axis and a second crystal axis, and a propagation amount of stress occurring from the through silicon via is larger in a direction of the first crystal axis than in a direction of the second crystal axis; andthe insulating film has a thickness in a direction of a diameter of the through silicon via being a thickness along the direction of the first crystal axis larger than a thickness along the direction of the second crystal axis.2. The semiconductor device according to claim 1 , wherein:the semiconductor layer is a Si layer including a surface having a plane index of (100); andan orientation index in the direction of the first crystal axis is <110> and an orientation index in the direction of the second crystal axis is <100>.3. The semiconductor device according to claim 1 , wherein the ...

SEMICONDUCTOR PACKAGE

A semiconductor package includes a substrate, through-electrodes penetrating the substrate, first bumps spaced apart from each other in a first direction parallel to a top surface of the substrate and electrically connected to the through-electrodes, respectively, and at least one second bump disposed between the first bumps and electrically insulated from the through-electrodes. The first bumps and the at least one second bump constitute one row in the first direction. A level of a bottom surface of the at least one second bump from the top surface of the substrate is a substantially same as levels of bottom surfaces of the first bumps from the top surface of the substrate. 1. A semiconductor package comprising:a substrate;through-electrodes penetrating the substrate;first bumps spaced apart from each other in a first direction parallel to a top surface of the substrate, the first bumps being electrically connected to the through-electrodes, respectively; andat least one second bump disposed between the first bumps, the at least one second bump being electrically insulated from the through-electrodes,wherein the first bumps and the at least one second bump constitute one row in the first direction, andwherein a level of a bottom surface of the at least one second bump from the top surface of the substrate is a substantially same as levels of bottom surfaces of the first bumps from the top surface of the substrate.2. The semiconductor package as claimed in claim 1 , further comprising:an insulating pattern provided on the substrate,wherein the insulating pattern has: first through-holes overlapping with the through-electrodes, respectively; and a second through-hole exposing the top surface of the substrate,wherein the first bumps are provided in the first through-holes, respectively, andwherein the second bump is provided in the second through-hole.3. The semiconductor package as claimed in claim 1 , further comprising:first pads, each of which is disposed between ...

Method of manufacturing semiconductor device

As one embodiment, a method of manufacturing a semiconductor device includes the following steps. That is, the method of manufacturing a semiconductor device includes a first step of applying ultrasonic waves to a ball portion of a first wire in contact with a first electrode of the semiconductor chip while pressing the ball portion with a first load. In addition, the method of manufacturing a semiconductor device includes a step of, after the first step, applying the ultrasonic waves to the ball portion while pressing the ball portion with a second load larger than the first load, thereby bonding the ball portion and the first electrode.

Method for manufacturing semiconductor device

A method for manufacturing a semiconductor device includes: supplying a resist to a first surface of a semiconductor element having a plurality of electrode pads to cover the electrode pad surfaces; opening the resist on the electrode pad surfaces to expose the electrode pad surfaces from the resist; curing the resist by applying light or heat to the resist; forming bump electrodes on the electrode pad surfaces by filling a plating solution into the openings of the resist; and peeling the resist from the first surface of the semiconductor element.

Semiconductor Package Using A Coreless Signal Distribution Structure

A semiconductor package using a coreless signal distribution structure (CSDS) is disclosed and may include a CSDS comprising at least one dielectric layer, at least one conductive layer, a first surface, and a second surface opposite to the first surface. The semiconductor package may also include a first semiconductor die having a first bond pad on a first die surface, where the first semiconductor die is bonded to the first surface of the CSDS via the first bond pad, and a second semiconductor die having a second bond pad on a second die surface, where the second semiconductor die is bonded to the second surface of the CSDS via the second bond pad. The semiconductor package may further include a metal post electrically coupled to the first surface of the CSDS, and a first encapsulant material encapsulating side surfaces and a surface opposite the first die surface of the first semiconductor die, the metal post, and a portion of the first surface of the CSDS. 120-. (canceled)21. A semiconductor device , comprising:a signal distribution structure comprising a signal distribution structure top side and a signal distribution structure bottom side;a first semiconductor die comprising a first die top side and a first die bottom side that is coupled to the signal distribution structure top side;a first encapsulant that encapsulates at least the first die top side and a portion of the signal distribution structure top side;a second semiconductor die comprising a second die top side, a second die bottom side, a second die sidewall between the second die top side and the second die bottom side, wherein the second die top side is coupled to the signal distribution structure bottom side;an electrical interconnect comprising an interconnect lower end, an interconnect upper end, and an interconnect sidewall between the interconnect lower end and the interconnect upper end, wherein the interconnect upper end is coupled to the signal distribution structure bottom side; anda ...

INTERPOSER AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME

A semiconductor package includes an interposer having multiple connection structures, each including redistribution layers electrically connected to each other, and a passivation layer covering at least a portion of each of the connection structures and filling a space between the connection structures. A first semiconductor chip is disposed on the interposer and has first connection pads, and a second semiconductor chip is disposed adjacent to the first semiconductor chip on the interposer and has second connection pads. The connection structures are independently arranged to each at least partially overlap with one or both of the first and second semiconductor chips, in a stacking direction of the first and second semiconductor chips on the interposer. The redistribution layers of each of the connection structures are electrically connected to at least one of the first and second connection pads via under bump metals. 1. A semiconductor package comprising: a plurality of connection structures disposed to be spaced apart from each other, and each including a respective insulation layer and a respective plurality of redistribution layers disposed in or on the respective insulation layer and electrically connected to each other, the redistribution layers of different connection structures of the plurality of connection structures being parallel to each other, and', 'a passivation layer covering at least a portion of each of the plurality of connection structures and filling at least a portion of a space between the plurality of connection structures;, 'an interposer including'}a first semiconductor chip disposed on the interposer and having a plurality of first connection pads; anda second semiconductor chip disposed adjacent to the first semiconductor chip on the interposer and having a plurality of second connection pads,wherein the plurality of connection structures are independently disposed to each at least partially overlap with at least one of the first and ...

Semiconductor Device and Method of Self-Confinement of Conductive Bump Material During Reflow Without Solder Mask

A semiconductor device has a semiconductor die with a die bump pad. A substrate has a conductive trace with an interconnect site. A conductive bump material is deposited on the interconnect site or die bump pad. The semiconductor die is mounted over the substrate so that the bump material is disposed between the die bump pad and interconnect site. The bump material is reflowed without a solder mask around the die bump pad or interconnect site to form an interconnect structure between the die and substrate. The bump material is self-confined within the die bump pad or interconnect site. The volume of bump material is selected so that a surface tension maintains self-confinement of the bump material substantially within a footprint of the die bump pad and interconnect site. The interconnect structure can have a fusible portion and non-fusible portion. An encapsulant is deposited between the die and substrate.

Semiconductor devices with duplicated die bond pads and associated device packages and methods of manufacture

Semiconductor devices with duplicated die bond pads and associated device packages and methods of manufacture are disclosed herein. In one embodiment, a semiconductor device package includes a plurality of package contacts and a semiconductor die having a plurality of first die bond pads, a plurality of second die bond pads, and a plurality of duplicate die bond pads having the same pin assignments as the first die bond pads. The semiconductor die further includes an integrated circuit operably coupled to the package contacts via the plurality of first die bond pads and either the second die bond pads or the duplicate die bond pads, but not both. The integrated circuit is configured to be programmed into one of (1) a first pad state in which the first and second die bond pads are enabled for use with the package contacts and (2) a second pad state in which the first and duplicate die bond pads are enabled for use with the package contacts.

Semiconductor Device and Method of Using a Standardized Carrier in Semiconductor Packaging

A semiconductor device has a carrier with a fixed size. A plurality of first semiconductor die is singulated from a first semiconductor wafer. The first semiconductor die are disposed over the carrier. The number of first semiconductor die on the carrier is independent from the size and number of first semiconductor die singulated from the first semiconductor wafer. An encapsulant is deposited over and around the first semiconductor die and carrier to form a reconstituted panel. An interconnect structure is formed over the reconstituted panel while leaving the encapsulant devoid of the interconnect structure. The reconstituted panel is singulated through the encapsulant. The first semiconductor die are removed from the carrier. A second semiconductor die with a size different from the size of the first semiconductor die is disposed over the carrier. The fixed size of the carrier is independent of a size of the second semiconductor die.

Electronic devices with bond pads formed on a molybdenum layer

An electronic device comprises: a molybdenum layer; a bond pad formed on the molybdenum layer, the bond pad comprising aluminum; and a wire bonded to the bond pad, the wire comprising gold.

EPLB/EWLB BASED POP FOR HBM OR CUSTOMIZED PACKAGE STACK

Embodiments of the invention include an eWLB or ePLB based PoP device and methods of forming such devices. According to an embodiment, such a device may include a die embedded within a mold layer. A substrate may be directly contacting a surface of the mold layer. Additionally, embodiments of the invention may include a through mold via formed through the mold layer that is electrically coupled to a contact formed on a surface of the substrate that is contacting the mold layer. In order to form such a device, embodiments may include dispensing a molding material over a die positioned on a mold carrier. Thereafter, a substrate may be pressed into the molding material. After curing the molding material, a mold layer may be formed that encases the die and is adhered to the substrate. 1. A semiconductor package , comprising:a die embedded within a mold layer;a substrate positioned above the mold layer, wherein a surface of the substrate directly contacts a surface of the mold layer, and wherein an active side of the die faces away from the substrate; anda through mold via formed through the mold layer, wherein the through mold via is electrically coupled to a contact formed on the surface of the substrate that is contacting the mold layer.2. The semiconductor package of claim 1 , further comprising:a conductive structure that electrically couples the through mold via to the contact, and wherein the conductive structure is embedded in the mold layer.3. The semiconductor package of claim 2 , wherein the conductive structure is a solder ball.4. The semiconductor package of claim 3 , wherein the solder ball has a core.5. The semiconductor package of claim 4 , wherein the core is a polymer core or a copper core.6. The semiconductor package of claim 1 , wherein one or more components are mounted to the surface of the substrate that is contacting the mold layer claim 1 , and wherein the one or more components are embedded in the mold layer.7. The semiconductor package of claim ...

Semiconductor package using a coreless signal distribution structure

A semiconductor package using a coreless signal distribution structure (CSDS) is disclosed and may include a CSDS comprising at least one dielectric layer, at least one conductive layer, a first surface, and a second surface opposite to the first surface. The semiconductor package may also include a first semiconductor die having a first bond pad on a first die surface, where the first semiconductor die is bonded to the first surface of the CSDS via the first bond pad, and a second semiconductor die having a second bond pad on a second die surface, where the second semiconductor die is bonded to the second surface of the CSDS via the second bond pad. The semiconductor package may further include a metal post electrically coupled to the first surface of the CSDS, and a first encapsulant material encapsulating side surfaces and a surface opposite the first die surface of the first semiconductor die, the metal post, and a portion of the first surface of the CSDS.

Semiconductor Device and Method

A semiconductor device and method utilizing a dummy structure in association with a redistribution layer is provided. By providing the dummy structure adjacent to the redistribution layer, damage to the redistribution layer may be reduced from a patterning of an overlying passivation layer, such as by laser drilling. By reducing or eliminating the damage caused by the patterning, a more effective bond to an overlying structure, such as a package, may be achieved. 1. A method comprising:forming a first redistribution layer on a substrate;plating conductive features on the first redistribution layer until the conductive features have a first thickness;covering a first subset of the conductive features with a first photoresist, a second subset of the conductive features not covered by the first photoresist;plating the second subset of the conductive features until the conductive features have a second thickness greater than the first thickness;removing the first photoresist;attaching a die laterally separated from the conductive features; andencapsulating the die and the conductive features with an encapsulant.2. The method of claim 1 , wherein the plating the conductive features on the first redistribution layer comprises:forming a passivation layer over the first redistribution layer;patterning the passivation layer with openings exposing the first redistribution layer;depositing a seed layer over the passivation layer and in the openings; andplating the conductive features from the seed layer.3. The method of claim 2 , further comprising:removing portions of the seed layer not covered by the conductive features to expose a portion of the passivation layer between each of the conductive features.4. The method of claim 3 , wherein:the conductive features have a first width after the plating the conductive features on the first redistribution layer, andthe conductive features have a second width after the removing the portions of the seed layer, the first width greater ...

Semiconductor packages including a multi-chip stack and methods of fabricating the same

Semiconductor packages are provided. The semiconductor package includes a first semiconductor chip to which a first elevated pillar bump is connected, a second semiconductor chip stacked on the first semiconductor chip to leave revealed the first elevated pillar bump and configured to include a first chip pad disposed on a center region of the second semiconductor chip, a third semiconductor chip offset and stacked on the second semiconductor chip to leave revealed the first chip pad, and a chip supporter supporting an overhang of the third semiconductor chip.

SUBSTRATES FOR SEMICONDUCTOR PACKAGES

A substrate includes a dielectric layer, a first metal bar, a plurality of first traces, a plurality of first openings, a second metal bar, and at least one second opening. The dielectric layer has a first major surface and a second major surface opposite to the first major surface. The first metal bar is on the first major surface. The plurality of first traces are on the first major surface. Each first trace is connected at one end to the first metal bar. The plurality of first openings expose the dielectric layer on the first major surface and intersect a first trace. The second metal bar is on the second major surface. The at least one second opening exposes the dielectric layer on the second major surface and intersects the second metal bar. The first openings are laterally offset with respect to the at least one second opening. 1. A substrate comprising:a dielectric layer having a first major surface and a second major surface opposite to the first major surface;a first metal bar on the first major surface;a plurality of first traces on the first major surface, each first trace connected at one end to the first metal bar;a plurality of first openings exposing the dielectric layer on the first major surface, each first opening intersecting a first trace;a second metal bar on the second major surface; andat least one second opening exposing the dielectric layer on the second major surface, the at least one second opening intersecting the second metal bar,wherein the first openings are laterally offset with respect to the at least one second opening.2. The substrate of claim 1 , wherein the substrate comprises package areas and singulation areas between the package areas claim 1 , andwherein the first openings are within the package areas and spaced apart from edges of the package areas, and the at least one second opening is within the singulation areas.3. The substrate of claim 1 , further comprising:a resist layer on a portion of each first trace and the first ...

Semiconductor Device and Method

In an embodiment, a device includes: a first reflective structure including first doped layers of a semiconductive material, alternating ones of the first doped layers being doped with a p-type dopant; a second reflective structure including second doped layers of the semiconductive material, alternating ones of the second doped layers being doped with a n-type dopant; an emitting semiconductor region disposed between the first reflective structure and the second reflective structure; a contact pad on the second reflective structure, a work function of the contact pad being less than a work function of the second reflective structure; a bonding layer on the contact pad, a work function of the bonding layer being greater than the work function of the second reflective structure; and a conductive connector on the bonding layer.

Warpage Balancing In Thin Packages

Representative implementations of devices and techniques provide reinforcement for a carrier or a package. A reinforcement layer is added to a surface of the carrier, often a bottom surface of the carrier that is generally under-utilized except for placement of terminal connections. The reinforcement layer adds structural support to the carrier or package, which can be very thin otherwise. In various embodiments, the addition of the reinforcement layer to the carrier or package reduces warpage of the carrier or package.

METHOD OF PRODUCING AN OPTOELECTRONIC COMPONENT, AND OPTOELECTRONIC COMPONENT

A method of producing an optoelectronic component includes providing an opto-electronic semiconductor chip including a layer sequence arranged on a substrate, wherein the layer sequence includes a contact side including two electrical contact locations, the contact side facing away from the substrate; arranging the optoelectronic semiconductor chip on an auxiliary carrier such that the contact side faces away from the auxiliary carrier; arranging a molding material above the auxiliary carrier such that a housing is formed that at least partly encloses the optoelectronic semiconductor chip, wherein the contact side is covered by the molding material; and detaching the housing from the auxiliary carrier. 120-. (canceled)21. A method of producing an optoelectronic component comprising:providing an optoelectronic semiconductor chip comprising a layer sequence arranged on a substrate, wherein the layer sequence comprises a contact side comprising two electrical contact locations, said contact side facing away from the substrate;arranging the optoelectronic semiconductor chip on an auxiliary carrier such that the contact side faces away from the auxiliary carrier;arranging a molding material above the auxiliary carrier such that a housing is formed that at least partly encloses the optoelectronic semiconductor chip, wherein the contact side is covered by the molding material; anddetaching the housing from the auxiliary carrier.22. The method according to claim 21 , further comprising claim 21 , after detaching the housing from the auxiliary carrier claim 21 , removing the substrate claim 21 , wherein the layer sequence remains at the molding material of the housing.23. The method according to claim 22 , further comprising claim 22 , after removing the substrate claim 22 , arranging a wavelength-converting material in a free space produced as a result of removing the substrate.24. The method according to claim 22 , wherein removing the substrate is carried out by a laser ...