Ein Schaltkreisgehäuse, ein elektronisches Schaltkreisgehäuse und Verfahren zum Verkapseln eines elektronischen Schaltkreises

Ein Schaltkreisgehäuse wird bereitgestellt, das Schaltkreisgehäuse aufweisend: einen elektronischen Schaltkreis; einen Metallblock neben dem elektronischen Schaltkreis; eine erste Metallschichtstruktur elektrisch kontaktiert mit mindestens einem ersten Kontakt auf einer ersten Seite des elektronischen Schaltkreises; eine zweite Metallschichtstruktur elektrisch kontaktiert mit mindestens einem zweiten Kontakt auf einer zweiten Seite des elektronischen Schaltkreises, wobei die zweite Seite gegenüberliegend der ersten Seite ist; wobei der Metallblock elektrisch kontaktiert ist mit der ersten Metallschichtstruktur und der zweiten Metallschichtstruktur mittels eines elektrisch leitfähigen Mediums; und wobei das elektrisch leitfähige Medium ein Material verschieden von dem Material der ersten und der zweiten Metallschichtstruktur oder eine Materialstruktur verschieden von dem Material der ersten und der zweiten Metallschichtstruktur aufweist.

Leistungshalbleiterchip mit zwei Metallschichten auf einer Fläche

Ein Halbleiterchip beinhaltet eine Leistungstransistorschaltung mit mehreren aktiven Transistorzellen. Eine erste Lastelektrode und eine Steuerelektrode sind auf einer ersten Fläche des Halbleiterchips angeordnet, wobei die erste Lastelektrode eine erste Metallschicht beinhaltet. Eine zweite Lastelektrode ist auf einer zweiten Fläche des Halbleiterchips angeordnet. Eine zweite Metallschicht ist über der ersten Metallschicht angeordnet, wobei die zweite Metallschicht elektrisch gegenüber der Leistungstransistorschaltung isoliert ist und die zweite Metallschicht über einen Bereich der Leistungstransistorschaltung angeordnet ist, der mindestens eine der mehreren aktiven Transistorzellen umfasst.

High temperature change-fixed insertion diode e.g. trench junction barrier schottky diode, for use in motor vehicle-generator system, has isolating plastic layer overlapping radial inner-lying end area of another isolating plastic layer

The diode (1) has a semiconductor chip (3) fixed between a socket and a head wire (6) by an interconnection layer i.e. solder layer (5), and made from semiconductor material e.g. silicon carbide or gallium nitride. The layer is arranged on a chip front side relative to a chip outer edge, and a circulating, isolating plastic layer (10) is arranged above an interconnection layer-free area of the chip. Another completely circulating, isolating plastic layer (11) overlaps a radial inner-lying end area of the former plastic layer, where the latter plastic layer is made from polyimide.

Verfahren zur Herstellung einer Halbleiter-anordnung

Halbleitervorrichtung

Eine Halbleitervorrichtung weist auf: einen Halbleiterchip (12), der unter Verwendung eines Siliziumkarbids gebildet ist und Elektroden auf einer ersten Oberfläche 12a sowie einer zweiten, der ersten Oberfläche gegenüberliegenden Oberfläche, einen Anschluss (14), der benachbart zu der ersten Oberfläche angeordnet ist und mit der Elektrode auf der ersten Oberfläche durch ein Bond-Element verbunden ist, und einen Kühlkörper (22) der benachbart zu der zweiten Oberfläche angeordnet ist und mit der Elektrode auf zweiten Oberfläche mittels eines Bond-Elements verbunden ist. Die erste Oberfläche (12a) ist eine (0001) Ebene und eine Dickenrichtung des Halbleiterchips entspricht einer [0001] Richtung. Von den Abständen zwischen dem Endabschnitt des Halbleiterchips (12) mit einer quadratischen, zweidimensionalen Form und dem Endabschnitt des Anschlusses (14) mit einer rechteckigen, zweidimensionalen Form ist der kürzeste Abstand L1 in einer [1-100] Richtung kürzer als der kürzeste Abstand L2 in einer ...

Compensating circular lamination for power semiconductor modules

Use is made in power semiconductor modules of compensating circular laminations which absorb thermal stresses due to unequal coefficients of expansion of silicon semiconductor chips and metal parts connected thereto, e.g. copper connecting parts or copper/ceramic substrates. The compensating circular laminations are intended, moreover, to exhibit good electrical and thermal conductivity. The object of the invention is to specify a compensating circular lamination which by comparison with known compensating circular laminations leads to a reduction in the thermal stresses occurring during operation. This object is achieved by means of a compensating circular lamination in which a powdery mixture of different materials, e.g. molybdenum and copper, is sintered to produce a moulded part, the concentration of the powder components used varying by location. The circular lamination exhibits a high molybdenum concentration, e.g. on the side facing a silicon chip, and a high copper fraction on the ...

Halbleitereinheit und Verfahren zur Herstellung einer Halbleitereinheit

Eine Halbleitereinheit weist Folgendes auf: ein isolierendes Substrat (1), das durch Integrieren einer keramischen Basisplatte (1b) und einer Kühlrippe (1a) gebildet wird; mehrere Plattenzwischenverbindungselemente (5); sowie eine Mehrzahl von Halbleiterelementen (3a). Die einen Seiten der Halbleiterelemente (3a) sind mit einem Lot (4) an der Chip-Unterseite an die keramische Basisplatte (lb) des isolierenden Substrats (1) gebondet, und die anderen Seiten derselben sind mit einem Lot (6) an der Chip-Oberseite so an die Plattenzwischenverbindungselemente (5) gebondet, dass die Plattenzwischenverbindungselemente (5) jeweils den Halbleiterelementen (3a) entsprechen. Das Lot (4) an der Chip-Unterseite und das Lot (6) an der Chip-Oberseite enthalten beide vorwiegend Sn und 0,3 Gew.% bis 3 Gew.% Ag sowie 0,5 Gew.% bis 1 Gew.% Cu. Dadurch wird eine Reduzierung der Abmessungen der Halbleitereinheit ermöglicht, ohne die Wärmeabführung zu beeinträchtigen.

HALBLEITERVORRICHTUNG UND LEISTUNGSMODUL

Eine Halbleitervorrichtung ist elektrisch mit Stromschienen (61, 62) verbunden und wird durch Kühler (63, 64) gekühlt, die sich auf beiden Seiten der Halbleitervorrichtung befinden. Die Halbleitervorrichtung weist auf: einen Halbleiterchip (20), der eine erste Hauptelektrode auf einer ersten Hauptoberfläche (22) und eine zweite Hauptelektrode auf einer zweiten Hauptoberfläche (23) hat; einen Dichtungsharzkörper (24); eine erste Wärmesenke (31), die elektrisch mit der ersten Hauptelektrode verbunden ist; und eine zweite Wärmesenke (39), die elektrisch mit der zweiten Hauptelektrode verbunden ist. Die erste Wärmesenke ist nur zu einer ersten Oberfläche freigelegt und eine Oberfläche gegenüberliegend zu einer Oberfläche, die dem Halbleiterchip zugewandt ist, ist freigelegt. Die zweite Wärmesenke ist nur zu einer zweiten Oberfläche freigelegt und eine Oberfläche gegenüberliegend zu einer Oberfläche, die dem Halbleiterchip zugewandt ist, ist von der zweiten Oberfläche freigelegt. In der ersten ...

Vorrichtung und Verfahren zum Verbinden von Komponenten

Vorrichtung zum Verbinden von mindestens zwei Komponenten, wobei die Vorrichtung ein Ober- (96) und ein Unterwerkzeug (95) aufweist, wobei das Unterwerkzeug (95) die mindestens zwei Komponenten (3, 2, 21, 22, 23, 1, 11, 12, 13) umfasst, wobei eine erste Komponente (3) die mindestens eine zweite Komponente (2, 21, 22, 23, 1, 11, 12, 13) mit einem zumindest teilweisen Überlapp relativ zur ersten Komponente (3) trägt; das Unterwerkzeug (95) und das Oberwerkzeug (96) relativ zueinander bewegt werden können; das Oberwerkzeug (96) mindestens zwei heizbare Stempel (7, 8, 15, 16, 71, 72, 81, 82, 83) umfasst, die so verbunden sind, dass sie sich relativ zueinander über ein abgedichtetes Druckkissen (5) bewegen können; wobei die Stempel (7, 8, 15, 16, 71, 72, 81, 82, 83) und das Druckkissen (5) zwischen sich eine erste flexible Schicht (6) aufweisen; dadurch gekennzeichnet, dass zwischen dem Oberwerkzeug (96) und dem Unterwerkzeug...

Halbleitervorrichtung mit Wärmeabstrahlplatte und Anheftteil

Eine Halbleitervorrichtung mit: einem Wärmeerzeugungselement (10), das durch einen IGBT bereitgestellt wird; einem Anheftteil (50); ersten und zweiten Wärmeabstrahlplatten (20, 30), welche auf ersten und zweiten Seiten (12, 13) des Wärmeerzeugungselementes (10) entsprechend über das Anheftteil (50) angeordnet sind; einem Wärmeabstrahlblock (40), der zwischen der ersten Wärmeabstrahlplatte (30) und dem Wärmeerzeugungselement (10) über das Anheftteil (50) angeordnet ist; und einem Kunstharzverguss (60), der praktisch die gesamte Vorrichtung eingießt, wobei die ersten und zweiten Wärmeabstrahlplatten (20, 30) in der Lage sind, von dem Wärmeerzeugungselement (10) erzeugte Wärme abzustrahlen; das Wärmeerzeugungselement (10) elektrisch und thermisch mit der ersten Wärmeabstrahlplatte (30) über das Anheftteil (50) und den Wärmeabstrahlblock (40) verbunden ist; das Wärmeerzeugungselement (10) elektrisch und thermisch mit der zweiten Wärmeabstrahlplatte (20) über das Anheftteil (50) verbunden ist ...

Halbleiterchip, Halbleiterbauteil und Verfahren zu deren Herstellung

Halbleiterchip (1) mit einer haftvermittlungsschichtfreien Dreischichtmetallisierung (2) bestehend aus einer Aluminiumschicht (4), die direkt auf dem Halbleiterchip (1) aufgebracht ist, einer Diffusionssperrschicht (5), die direkt auf der Aluminiumschicht (4) aufgebracht ist, einer Lotschicht (6), die direkt auf die Diffusionssperrschicht (5) aufgebracht ist, wobei, die Diffusionssperrschicht (5) Ti, Ni, Pt oder Cr ist, und die Lotschicht (6) eine Diffusionslotschicht ist, die AuSn, AgSn oder CuSn aufweist, und wobei der Halbleiterchip (1) eine aktive Oberseite (16) und eine passive Rückseite (3) aufweist, und wobei alle drei Schichten in einer Prozessabfolge auf der passiven Rückseite (3) aufgesputtert sind.

Halbleiterbauteil mit einem vertikalen Halbleiterbauelement und Verfahren zu dessen Herstellung

Ein Halbleiterbauteil (1; 25) weist ein vertikales Halbleiterbauelement (2), eine erste Metallisierung (8) und eine zweite Metallisierung (13) auf. Die zweite Metallisierung (13) weist eine einstückige Folie mit einem ersten Ende (14) mit einer ersten Kontaktfläche (17), einem Zwischenbereich (15) und einem zweiten Ende (16) mit einer zweiten Kontaktfläche (19) auf. Die erste Kontaktfläche (17) ist auf der Rückseite (6) des Halbleiterbauelements (2) angeordnet und die zweite Kontaktfläche (19) ist im Wesentlichen in der Ebene der Außenkontaktfläche (12) der ersten Metallisierung (8) angeordnet und sieht eine Außenkontaktfläche (12) vor. Die erste Kontaktfläche (17) und die zweite Kontaktfläche (19) sind auf gegenüberliegenden Oberflächen der Folie der zweiten Metallisierung (13) angeordnet.

Electronic power package for e.g. diode, has two non-planar insulating substrates connected in connection regions, so that mechanical separation between substrates is controlled by number, arrangement, design and material of regions

The package (100) has two non-planar insulating substrates (1, 2) with high thermal conductivity. Electronic components e.g. semiconductor power transistor chip (20) and diode chip (30), are attached on each of the substrates. The substrates are connected with each other in connection regions, so that a mechanical separation between the substrates is controlled by the number of connection regions, an arrangement of connection regions, and design and material of the connection regions. The mechanical separation supplies an axially directed net compression force into the electronic components.

Schichtbauelement-Herstellungsverfahren

Schichtbauelement-Herstellungsverfahren zur Herstellung eines Schichtbauelements unter Verwendung eines verstärkten Wafers (20), bei dem der verstärkte Wafer (20) durch auf einer vorderen Oberfläche (20a) in einem Gittermuster angeordnete Straßen (21) in mehrere Bereiche unterteilt ist und einen mit Bauelementen (22) in den so abgeteilten Bereichen ausgebildeten Bauelementbereich (23) und einen äußeren Umfangsüberschussbereich (24), der den Bauelementbereich (23) umgibt, beinhaltet, ein Bereich einer hinteren Oberfläche (20b), der dem Bauelementbereich (23) entspricht, so geschliffen wird, dass der Bauelementbereich (23) so ausgebildet werden kann, dass er eine vorgegebene Dicke aufweist, und ein Bereich, der dem äußeren Umfangsüberschussbereich (24) entspricht, belassen werden kann, um einen ringförmigen verstärkten Abschnitt (24b) zu bilden, wobei das Verfahren umfasst:einen Waferschichtungsschritt, bei dem ein unten liegender Wafer (200), der einen Durchmesser aufweist, der geringfügig ...

Packung mit aufgerauter verkapselter Oberfläche zur Förderung einer Haftung

Eine Packung (100), die mindestens einen elektronischen Chip (102), einen ersten wärmeabführenden Körper (104), der thermisch mit einer Hauptoberfläche des mindestens einen elektronischen Chips (102) gekoppelt ist und dafür ausgelegt ist, Wärmeenergie von dem mindestens einen elektronischen Chip (102) abzuführen, ein Kapselungsmittel (108), das mindestens einen Teil des mindestens einen elektronischen Chips (102) und einen Teil des ersten wärmeabführenden Körpers (104) verkapselt, wobei mindestens ein Teil einer Oberfläche des ersten wärmeabführenden Körpers (104) aufgeraut ist.

Halbleitervorrichtung

Halbleitervorrichtung (2), die aufweist:ein erstes Halbleiterelement (3) und ein zweites Halbleiterelement (5), wobei jedes der Halbleiterelemente, erstes Halbleiterelement (3) und zweites Halbleiterelement (5), Elektroden (3a, 3b, 5a, 5b) an beiden Hauptflächen davon aufweist,eine erste Metallplatte (12) und eine zweite Metallplatte (15), die das erste Halbleiterelement (3) dazwischen eingefügt haben, wobei die erste Metallplatte (12) und die zweite Metallplatte (15) an die Elektroden (3a, 3b) des ersten Halbleiterelements (3) jeweils mit entsprechenden ersten gelöteten Abschnitten (18a, 18b, 18c) gebondet sind,eine dritte Metallplatte (22) und eine vierte Metallplatte(25), die das zweite Halbleiterelement (5) dazwischen eingefügt haben, wobei die dritte Metallplatte (22) und die vierte Metallplatte (25) an die Elektroden (5a, 5b) des zweiten Halbleiterelements (5) jeweils mit entsprechenden zweiten gelöteten Abschnitten (28a, 28b, 28c) gebondet sind,eine Harzpackung (9), in der das erste ...

Leitungsintegrierter Schalter und Verfahren zum Herstellen eines leitungsintegrierten Schalters

Leitungsintegrierter Schalter mit zumindest einem ersten metallischen Flachteil 2, zumindest einen zweiten metallischen Flachteil 8, wobei die Flachteile in einem Überlappungsbereich mit ihren breiten Seiten übereinander angeordnet sind und in dem Überlappungsbereich ein Halbleiterschalter 18 zwischen den Flachteilen 2, 8, die Flachteile 2, 8 schaltend miteinander verbindend, angeordnet ist. Ein einfacher Aufbau ist dadurch möglich, dass zumindest im Überlappungsbereich ein erstes der Flachteile 2 auf einer dem zweiten der Flachteile 8 zugewandten Seite zumindest teilweise mit einer Isolation beschichtet ist, wobei in der Isolation in einem Kontaktbereich 10 eine Ausnehmung vorgesehen ist und der Halbleiterschalter 18 in dem Kontaktbereich 10 mit dem Flachteil 8 elektrisch kontaktiert ist.

Leistungsmodul

Das Leistungsmodul weist mindestens ein elektrisches Bauteil mit einer Kontaktfläche auf, wobei welchem das elektrische Bauteil mittels der Kontaktfläche an mindestens ein mit offenporigem Material gebildetes Kontaktstück des Leistungsmoduls elektrisch kontaktiert ist und das zumindest eine elektrische Bauteil und das zumindest eine Kontaktstück, zumindest in Richtungen der flächigen Erstreckungen der mindestens einen Kontaktfläche, relativ zueinander zumindest formschlüssig festgelegt sind.

Semiconductor component especially for low voltage power components has chip with contact bumps surrounded by conductive adhesive and electrodes shorted to a metal contact layer

A semiconductor component comprises housing (2) and chip (3) with a large surface contact between contact metal (5) on the chip and external contacts (6). Many small chip electrodes (7) are shorted to the contact metal and a transition layer (9) has contact bumps (11) surrounded by electrically conductive adhesive (12) on the contact metal.

Miniaturisiertes SMD-Diodenpaket und Herstellungsverfahren dafür

Miniaturisiertes SMD-Diodenpaket (10), umfassend:einen Diodenchip (30a, 30b, 30c) mit einer TVS-Diode, einer Schottkydiode, einer Schaltdiode, einer Zenerdiode oder einer Gleichrichterdiode, der eine Bodenfläche aufweist, die mit einer positiven Elektrode (31) und einer negativen Elektrode (31) versehen ist;eine Bodenleiterplatte (50) aus einer Keramikplatte, einer Kunststoffplatte, einer Verbundplatte oder einer wärmeableitenden Platte;zwei Schaltkreiselektroden (56a, 56b), die separat auf der Bodenleiterplatte (50) aufgebracht sind und elektrisch mit der jeweiligen positiven Elektrode und negativen Elektrode (31) an der Bodenfläche des Diodenchips (30a, 30b, 30c) verbunden sind;eine Kapselung (75) aus einem Keramikmaterial oder einem Kunststoffmaterial zur Bildung einer integrierten Struktur mit der Bodenleiterplatte (50), um den Diodenchip (30a, 30b, 30c) und die zwei Schaltkreiselektroden (56a, 56b) zu kapseln, derart dass sich jeweils ein Ende der zwei Schaltkreiselektroden (56a, 56b ...

Leistungshalbleitermodul und Verfahren zur Herstellung eines Leistungshalbleitermoduls

Ein Leistungshalbleitermodul kann einen Träger, einen Leistungshalbleiterchip, der so über dem Träger angeordnet ist, dass eine erste Hauptseite des Leistungshalbleiterchips dem Träger zugewandt ist, einen Kontaktclip, der so über dem Leistungshalbleiterchip angeordnet ist, dass eine zweite, der ersten Hauptseite gegenüberliegende Hauptseite des Leistungshalbleiterchips; dem Kontaktclip zugewandt ist, und ein zwischen der zweiten Hauptseite und dem Kontaktclip angeordnetes Abstandshalterelement umfassen, wobei eine erste Lötverbindung die zweite Hauptseite und das Abstandshalterelement verbindet und wobei eine zweite Lötverbindung das Abstandshalterelement und den Kontaktclip verbindet.

Halbleitervorrichtung mit Metallplatten und Halbleiterchip

Es wird eine Halbleitervorrichtung geschaffen, die aufweist: einen Halbleiterchip (10); eine erste Metallplatte (20), die mittels einer ersten Lötschicht (51) auf einer Seite des Chips (10) angeordnet ist; eine zweite Metallplatte (40), die mittels einer zweiten Lötschicht (52) auf der anderen Seite des Chips (10) angeordnet ist; eine dritte Metallplatte (30), die mittels einer dritten Lötschicht (53) auf der zweiten Metallplatte (40) angeordnet ist; eine Stützeinrichtung (80, 85, 87) zum Halten eines Abstands zwischen dem Chip (10) und der ersten Metallplatte (20) und/oder zwischen dem Chip (10) und der zweiten Metallplatte (40); und eine Aufnahmeeinrichtung (90) zum Aufnehmen von überschüssigem Lot, wenn die dritte Lötschicht (53) das überschüssige Lot aufweist.

Leistungstransistor und Leistungshalbleiterbauteil

Die Erfindung betrifft einen Leistungstransistor und ein Leistungshalbleiterbauteil. Der vertikal leitende Leistungstransistor weist an seiner Vorderseite (11) eine Sourcezone (14) und einen Steuereingang (16) auf. Eine Durchführung für den Steuereingang weist eine Elektrode auf der Vorderseite (11) und eine Elektrode auf der Rückseite (12) auf, sodass der Steuereingang sowohl von der Vorderseite (11) als auch von der Rückseite (12) kontaktiert werden kann.

Electrical assembly comprises cooler structure and electrical component on metal-ceramic substrate having electrical module, where electrical module comprises two metal-ceramic substrates

Electrical assembly comprises cooler structure and an electrical component (6) on a metal-ceramic substrate (4,5) having electrical module. The electrical module comprises two metal-ceramic substrates, where each substrate includes a ceramic layer (7,10), which are provided with partially structured metal plating (9,12). An active cooler (2,3) and an electrical component are also provided between two metal-ceramic substrates, which are thermally connected.

Halbleitervorrichtung mit Abstrahlungsbauteilen

Semiconductor element including an electrode construction

Wafer metallization of high power semiconductor devices

A power semiconductor device for high current density applications, i.e. an insulated gate bipolar transistor (IGBT) or MOSFET, comprising: a plurality of semiconductor regions (201, 203, 204, figure 2) formed on top of one another and a contact layer (207) formed above a first surface of one of the semiconductor regions. The contact layer comprises a first portion placed in direct contact of said first surface of said one of the semiconductor regions and a second portion formed over an insulation region (209) formed in direct contact of said first surface of said one of the semiconductor regions. The device further comprises a first metal layer (230, 235) formed at least partly on the second portion of the contact layer; and a second metal layer 240 formed at least partly on the first metal layer. A gap or void present between the second metal layer and contact layer reduces pressure during fabrication. This structure is suitable for the pressure pack, double sided silver sintering or ...

A process for use in the production of a semi-conductor device

... 898,119. Semi-conductor devices. SIEMENS-SCHUCKERTWERKE A.G. March 20, 1961 [March 18, 1960], No. 10149/61. Class 37. A terminal plate to be soldered to an alloy containing electrode in a semi-conductor device is provided with a silver layer and heated in vacuo to remove gases occluded therein. Silicon disc 2 is provided with alloy electrodes 3, 4 of boron-containing and antimony-containing Au- Si alloys, respectively. In a separate operation molybdenum terminal plate 5 is provided on its upper face with a copper layer 6, or a layer of nickel followed by a layer of copper, and a silver foil 7 is then soldered to the copper layer in vacuo, or under a protective gas, at 770‹ to 850‹ C., to form the Cu-Ag eutectic. This temperature is maintained for at least ten minutes to de-gas the silver layer, and after cooling in vacuo it is immediately alloyed to electrode 3. If the silver coated terminal plate is stored for some time before alloying it is de-gassed by heating in vacuo to 700‹ to 770 ...

SEMICONDUCTOR DEVICE

Improvements in or relating to the mounting of electrical components

... 1,004,020. Rectifier mountings. STANDARD TELEPHONES & CABLES Ltd. April 24, 1964, No. 17027/64. Heading H1K. A composite disc comprising a uniform layer 6 of one material and a slotted layer 7 of another material is designed for use in the attachment of an electrical component such as a solid state rectifier to a mounting of markedly different thermal expansion coefficient. When the component is a silicon semi-conductor and the mounting of copper, layer 6 is preferably of molybdenum and will be soft soldered to the component and layer 6 of copper which will be similarly soldered to the mounting. The composite disc itself may be prepared by hard soldering copper and molybdenum discs together and subsequently cutting the slots 13 to extend as deep as the solder: it may also be formed by casting or powder metallurgy. Fig. 1 (not shown) depicts a P-N junction rectifier mounted between a pair of the composite discs. The rectifier is produced by coating the surface of an intrinsic silicon wafer ...

SEMICONDUCTORS

... 1535195 Semi-conductor devices GENERAL ELECTRIC CO 19 Dec 1975 [23 Dec 1974] 52131/75 Heading H1K A semi-conductor device comprises a planar semi-conductor device chip 22 bonded to substantially co-extensive planar regions of metallic mounting plates 32, 33 which have peripheral edges that are not coplanar with said planar region so as to alleviate the effects of burrs 37 formed during manufacture of the mounting plates 32, 33. The mounting plates may be of Cu or Mo and they may be soldered to the device chip 22. The edges of the mounting plates are separated from the planar regions by transition regions 36 which may be straight, stepped or arcuate. One face of the device chip 22 may have ribbon contacts that bend away from the device chip 22 and terminate in flat portions that are coplanar with the outer face of the mounting plate on the opposite face of the chip 22, to facilitate attachment to a printed circuit board.

MANUFACTURING PROCESS OF AN ARRANGEMENT WITH POWER SEMICONDUCTOR ELEMENTS, WHICH CONTAINS A STEP PRINTINGINTERNALLY

SEMICONDUCTOR COMPONENT WITH DRUCKKONAKT

PROCEDURE FOR THE CONTACTING OF THE ADHESIVE-LATERAL ELECTRODE OF AN ELECTRICAL CONSTRUCTION UNIT.

BUTTON RECTIFIER PACKAGE FOR NON-PLANAR DIE

BUTTON RECTIFIER PACKAGE FOR NON-PLANAR DIE An axial lead semiconductor device package is provided for use with non-planar semiconductor die. By using solders of predetermined strength, wetting and flow characteristics, melting temperature, shape, area, and thickness, reliable attachment of non-planar die to planar mounting surfaces is achieved.

REACTIVE FOIL ASSEMBLY

PH SENSOR WITH BONDING AGENT DISPOSED IN A PATTERN

Embodiments described herein provide for a pH sensor that comprises a substrate and an ion sensitive field effect transistor (ISFET) die. The ISFET die includes an ion sensing part that is configured to be exposed to a medium such that it outputs a signal related to the pH level of the medium. The ISFET die is bonded to the substrate with at least one composition of bonding agent material disposed between the ISFET die and the substrate. One or more strips of the at least one composition of bonding agent material is disposed between the substrate and the ISFET die in a first pattern.

Halbleitereinrichtung mit mindestens einem flächenhaften p-n-Übergang

Halbleitereinrichtung mit mindestens einem flächenhaften p-n-Übergang

Lötverbindung für Halbleiterelemente

Verfahren zur Herstellung einer Halbleiteranordnung

Halbleiterbauelement

Halbleiterzelle mit einer gekapselten Halbleiteranordnung mit vier Schichten von abwechselnd gegensätzlichem Leitfähigkeitstyp und Verfahren zu ihrer Herstellung

Halbleiterbauelement mit einer gasdichten Kammer sowie Verfahren zur Herstellung eines solchen Halbleiterelementes und Vorrichtung zur Durchführung des Verfahrens

Verfahren zur Herstellung einer Halbleiteranordnung aus Silizium

Halbleiteranordnung

Lötverbindung an einem Halbleiterelement

Verfahren zum Herstellen einer Halbleiteranordnung

Verfahren zum Montieren einer Halbleitervorrichtung

Verfahren zum Herstellen einer Halbleiteranordnung und nach diesem Verfahren hergestellte Halbleiteranordnung

Verfahren zur Herstellung einer Halbleitergleichrichteranordnung und Vorrichtung zur Durchführung des Verfahrens

Halbleiteranordnung

Halbleiteranordnung

Metallschicht auf einer isolierenden Unterlage

Verfahren zur Herstellung von lötfähigen Kontaktstellen

Flächengleichrichteranordnung mit einem Halbleiterelement mit p-n-Übergang und Verfahren zur Herstellung einer solchen Anordnung

Verfahren zur Herstellung einer Halbleiteranordnung aus Silizium

Lötverbindung für Halbleiterelemente

Halbleiteranordnung

Halbleiterbauelement und Verfahren zum Herstellen eines solchen

Verfahren zur Herstellung einer Halbleiterbauelementeanordnung

Halbleiteranordnung

Halbleiter-Gleichrichter-Anordnung

Halbleiterbauelement mit Aluminiumkontakt

HALBLEITERBAUELEMENT.

Halbleitergerät, Verfahren zur Herstellung dieses Halbleitergerätes und Verwendung desselben

Halbleiteranordnung mit Kühlkörper

Halbleitergleichrichterelement für Starkstrom

Halbleitervorrichtung

Halbleiterelement und Verfahren zu dessen Herstellung

Halbleiterbauelement mit mindestens einem Druckkontaktübergang

Halbleiterbauelement und Verfahren zu seiner Herstellung

Halbleiterelement

Dispositif de contrôle à semi-conducteurs pour courant alternatif

SEMICONDUCTOR COMPONENT.

Chipmodul, Verwendung des Chipmoduls, Prüfanordnung sowie Prüfverfahren.

Die vorliegende Anmeldung betrifft ein Chipmodul, umfassend einen Chip (1), aufweisend eine Vorder- und eine Rückseite, einen Chipträger, aufweisend eine dem Chip (1) zugewandte Oberseite, eine auf der Oberseite des Chipträgers und zwischen der Rückseite des Chips und der Oberseite des Chipträgers angeordnete leitfähige Kontaktschicht, ein auf einer dem Chip zugewandten Oberseite der Kontaktschicht zumindest bereichsweise angeordneter, elektrisch leitfähiger Klebstoff, der die Oberseite der Kontaktschicht und eine Rückseite des Chips miteinander verbindet Die Kontaktschicht weist zumindest zwei voneinander elektrisch isolierte Bereiche auf, die jeweils über den im jeweiligen isolierten Bereich auf der Oberseite der Kontaktschicht angeordneten leitfähigen Klebstoff mit dem Chip elektrisch verbunden sind Ein leitfähiger Klebstoff kann in der vorliegenden Anmeldung sowohl ein leitfähiger Klebstoff im engeren Sinne als auch eine geeignete leitfähige Verbindung sein, z B Lot Die Erfindung betrifft ...

Chipmodul, Verwendung des Chipmoduls, Prüfanordnung sowie Prüfverfahren.

Die vorliegende Anmeldung betrifft ein Chipmodul, umfassend einen Chip (1), aufweisend eine Vorder- und eine Rückseite; einen Chipträger, aufweisend eine dem Chip (1) zugewandte Oberseite; eine auf der Oberseite des Chipträgers und zwischen der Rückseite des Chips und der Oberseite des Chipträgers angeordnete leitfähige Kontaktschicht, ein auf einer dem Chip zugewandten Oberseite der Kontaktschicht zumindest bereichsweise angeordneter, elektrisch leitfähiger Klebstoff, der die Oberseite der Kontaktschicht und eine Rückseite des Chips miteinander verbindet. Die Kontaktschicht weist zumindest zwei voneinander elektrisch isolierte Bereiche auf, die jeweils über den im jeweiligen isolierten Bereich auf der Oberseite der Kontaktschicht angeordneten leitfähigen Klebstoff mit dem Chip elektrisch verbunden sind. Ein leitfähiger Klebstoff kann in der vorliegenden Anmeldung sowohl ein leitfähiger Klebstoff im engeren Sinne als auch eine geeignete leitfähige Verbindung sein, z.B. Lot. Die Erfindung ...

Semiconductor structure and manufacturing method thereof

Stacked electronic part

Semiconductor package

Semiconductor device

Sheet type diode

Semiconductor device and method for manufacturing method of semiconductor device

Semiconductor package

Packaged IC having printed dielectric adhesive on die pad

A method of assembling a packaged integrated circuit (IC) includes printing a viscous dielectric polymerizable material onto a die pad of a leadframe having metal terminals positioned outside the die pad. An IC die having a top side including a plurality of bond pads is placed with its bottom side onto the viscous dielectric polymerizable material. Bond wires are wire bonded between the plurality of bond pads and the metal terminals of the leadframe.

Semiconductor device

Solder-top enhanced semiconductor device and method for low parasitic impedance packaging

This invention provides a solder-top enhanced semiconductor device for low parasitic impedance packaging and a method. The solder-top device includes a device die with a top metal layer patterned into contact zones and contact enhancement zones. At least one contact zone is electrically connected to at least one contact enhancement zone. Atop each contact enhancement zone is a solder layer for an increased composite thickness thus lowered parasitic impedance. Where the top metal material can not form a uniform good electrical bond with the solder material, the device die further includes an intermediary layer sandwiched between and forming a uniform electrical bond with the top metal layer and the solder layer. A method for making the solder-top device includes: a) Lithographically patterning the top metal layer into the contact zones and the contact enhancement zones. b) Forming a solder layer atop each of the contact enhancement zones using a stencil process for an increased composite ...

Chip-scale package

A method for manufacturing a semiconductor package that includes forming a frame inside a conductive can, the frame being unwettable by liquid solder.

Improvements with the transistors

CASE Of ENCAPSULATION FOR MODULE OF POWER IN HYBRID CIRCUIT

A method of manufacturing a silicon semiconductor device

Rectifying device with semiconductors in parallel

METHOD OF SOLDERING A METAL TERMINAL TO A SEMICONDUCTOR BODY AND THE COMPONENT SO-FORMED

ASSEMBLING AN INTEGRATED CIRCUIT DIE AND A PLATE

A method for welding two parts, in particular an electric component, and/or a plaquettesemi-driver

... a) Procédé pour souder deux pièces notamment un composant électrique, et/ou une plaquette semiconducteur. b) procédé caractérisé en ce que la cavité est réalisée sous la forme d'un chemin fermé (11), notamment d'une encoche circulaire (10), et en ce que plusieurs encoches (10) réalisées concentriquement les unes par rapport aux autres. c) l'invention concerne un procédé pour souder deux pièces, notamment un composant électrique, et/ou une plaquette semi-conducteur ...

DISMOUNTABLE SUBSTRATE.

L'invention concerne un substrat démontable comprenant successivement au moins un premier substrat (10), une couche de liaison démontable (20) et un deuxième substrat (30) semiconducteur. Le substrat est remarquable en ce que ladite couche de liaison (20) comporte une pluralité d'îlots répartis sur la surface du premier substrat (10) selon un motif déterminé et séparés les uns des autres par des régions de nature différente réparties selon un motif complémentaire. L'invention concerne également un procédé de fabrication d'un tel substrat.

Package with reinforced structure for an integrated circuit, and card comprising such a package

L'invention concerne la protection des circuits intégrés destinés à être montés dans des dispositifs tels que des cartes dans lesquels ils ne doivent pas faire de surépaisseur. Elle consiste a renforcer le circuit intégré (101) par au moins une armature de renforcement (107) formée d'une plaque rigide et résistante noyée dans le matériau (106) formant habituellement le boîtier du circuit intégré. Cette armature de renforcement est de préférence fabriquée à partir d'une plaquette de silicium, selon les techniques utilisées pour fabriquer les circuits intégrés. Elle permet de renforcer la protection des circuits intégrés utilisés dans les "cartes à puces" et donc d'améliorer la fiabilité de celles-ci.

Ohmic connection to large surface

Semiconductor device

Semiconductor device

The semiconductor device has a unit stack body including a plurality of units stacked on one another. Each unit includes a power terminal constituted of a lead part and a connection part. The connection part is formed with a projection and a recess. When the units are stacked on one another, the projection of one unit is fitted to the recess of the adjacent unit, so that the power terminals of the respective unit are connected to one another.

Semiconductor device and package

A semiconductor device includes a semiconductor substrate having an upper surface, a lower surface, a first side and a second side, wherein the lower surface has a slope so that the first side is thicker than the second side, and a circuit pattern including a bonding pad on the upper surface of the semiconductor substrate.

Chip package and fabricating method thereof

A chip package and a fabrication method thereof are provided. The chip package includes a substrate and a chip disposed over the substrate. A solder layer is disposed between the chip and the substrate. A conductive pad is disposed between the solder layer and the substrate, wherein the conductive pad includes a first portion disposed under the solder layer, a second portion disposed away from the first portion and a connective portion disposed between the first portion and the second portion. The connective portion has a width which is narrower than a width of the first portion along a first direction perpendicular to a second direction extending from the first portion to the connective portion.

Stitch bump stacking design for overall package size reduction for multiple stack

A method for die stacking is disclosed. In one embodiment a first die is formed overlying a substrate. A first wire is bonded to the first die and to a bond finger of the substrate, wherein the first wire is bonded to the bond finger with a first bond. A first stitch bump is formed overlying the first stitch bond, wherein the first stitch bump is formed from a molten ball of conductive material. A second die is formed overlying the first die. A second wire is bonded to the second die and to the first stitch bump, wherein the second wire is bonded to the first stitch bump with a second bond.

Integrated circuit packaging system with warpage control and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit device having chip interconnects; applying an attachment layer directly on the integrated circuit device; attaching a device stiffener to the integrated circuit device with the attachment layer; attaching a chip carrier to the chip interconnects with the device stiffener attached to the integrated circuit device for controlling warpage of the integrated circuit device to prevent the warpage from causing some of the chip interconnects to separate from the chip carrier during attachment of the chip interconnects to the chip carrier; and applying an underfill between the chip carrier and the integrated circuit device for controlling connectivity of all the chip interconnects to the chip carrier.

Semiconductor package device with a heat dissipation structure and the packaging method thereof

The present invention provide a heat dissipation structure on the active surface of the die to increase the performance of the heat conduction in longitude direction of the semiconductor package device, so that the heat dissipating performance can be improved when the semiconductor package device is associated with the exterior heat dissipation mechanism.

Electronic element unit and reinforcing adhesive agent

It is an object of the present invention to provide an electronic element unit and a reinforcing adhesive agent in which a bonding strength can be improved between an electronic element and a circuit board and a repairing work can be carried out without giving a thermal damage to the electronic element or the circuit board. In an electronic element unit ( 1 ) including an electronic element ( 2 ) having a plurality of connecting terminals ( 12 ) on a lower surface thereof, a circuit board ( 3 ) having a plurality of electrodes ( 22 ) corresponding to the connecting terminals ( 12 ) on an upper surface thereof. The connecting terminals ( 12 ) and the electrodes ( 22 ) are connected by solder bumps ( 23 ), and the electronic element ( 2 ) and the circuit board ( 3 ) are partly bond by a resin bond part ( 24 ) made of a thermosetting material of a thermosetting resin, and a metal powder ( 25 ) is included in the resin bond parts ( 24 ) in a dispersed state. The metal powder ( 25 ) has a melting point lower than a temperature at which the resin bond parts ( 24 ) are heated when a work (a repairing work) is carried out for removing the electronic element ( 2 ) from the circuit board ( 3 ).

Semiconductor apparatus, method for manufacturing the same and electric device

A semiconductor apparatus includes: a semiconductor device including a first electrode; a substrate including a second electrode and a recess; and a heat-dissipating adhesive material to set the semiconductor device in the recess so as to arrange the first electrode close to the second electrode, wherein the first electrode is coupled to the second electrode and the heat-dissipating adhesive material covers a bottom surface and at least part of a side surface of the semiconductor device.

Multilayer resin sheet and method for producing the same, method for producing cured multilayer resin sheet, and highly thermally conductive resin sheet laminate and method for producing the same

A multilayer resin sheet is constituted by including a resin layer containing an epoxy resin having a mesogenic skeleton, a curing agent and an inorganic filler, and an insulating adhesive layer formed on at least either of the surfaces of the resin layer. A cured multilayer resin sheet originated from the multilayer resin sheet has high thermal conductivity, good insulation and adhesive strength, and, further, superior thermal shock resistance, and is suitable as an electric insulating material to be used for an electric or electronic device.

Method for Making Solder-top Enhanced Semiconductor Device of Low Parasitic Packaging Impedance

A solder-top enhanced semiconductor device is proposed for packaging. The solder-top device includes a device die with a top metal layer patterned into contact zones and contact enhancement zones. At least one contact zone is electrically connected to at least one contact enhancement zone. Atop each contact enhancement zone is a solder layer for an increased composite thickness thus lowered parasitic impedance. Where the top metal material can not form a uniform good electrical bond with the solder material, the device die further includes an intermediary layer sandwiched between and forming a uniform electrical bond with the top metal layer and the solder layer. A method for making the solder-top device includes lithographically patterning the top metal layer into the contact zones and the contact enhancement zones; then forming a solder layer atop each of the contact enhancement zones using a stencil process for an increased composite thickness.

Stacked semiconductor package

A stacked semiconductor package includes a substrate having an upper surface and a lower surface, and divided into a first region and a second region that adjoins the first region; a support member formed in the second region on the upper surface of the substrate; and a semiconductor chip module including a plurality of semiconductor chips each of which has bonding pads near one edge of a first surface thereof and which are stacked on the support member in a step-like shape such that their bonding pads face the first region and are bent such that the bonding pads are electrically connected with the substrate.

Stacked electronic component and manufacturing method thereof

A stacked electronic component comprises a first electronic component adhered on a substrate via a first adhesive layer, and a second electronic component adhered by using a second adhesive layer thereon. The second adhesive layer has a two-layer structure formed by a same material and having different modulus of elasticity. The second adhesive layer of the two-layer structure has a first layer disposed at the first electronic component side and a second layer disposed at the second electronic component side. The first layer softens or melts at an adhesive temperature. The second layer maintains a layered shape at the adhesive temperature. According to the stacked electronic component, occurrences of an insulation failure and a short circuiting are prevented, and in addition, a peeling failure between the electronic components, an increase of a manufacturing cost, and so on, can be suppressed.

Power Module and Power Converter Containing Power Module

A power module includes a semiconductor chip, a first coupling conductor with one main surface coupled to one main surface of the semiconductor chip, a second coupling conductor with one main surface coupled to the other main surface of the semiconductor chip, a coupling terminal supplied with electrical power from the direct current power source, and resin material to seal the semiconductor chip, and in which the resin member has a protruding section that protrudes from the space where the first and second coupling conductors are formed opposite each other, and the coupling terminal is clamped on the protruding section, and at least one of the first or second coupling conductors is coupled to a coupling terminal by way of a metallic material that melts at a specified temperature.

SEED LAYER PASSIVATION

A microfeature workpiece generally includes a first conducting layer, a chemisorbed layer or a monolayer directly on the first conducting layer, and a second conducting layer. The chemisorbed layer or monolayer includes a first material that may be selected from the group consisting of nitrogen-containing compounds, sulfur-containing compounds, and mixtures thereof. 1. A microfeature workpiece , comprising;(a) a first conducting layer;(b) a chemisorbed layer including at least a first material directly on the first conducting layer, wherein the first material is selected from the group consisting of nitrogen-containing compounds, sulfur-containing compounds, and mixtures thereof; and(c) a second conducting layer directly on the chemisorbed layer.2. The workpiece of claim 1 , wherein the first conducting layer is a seed layer.3. The workpiece of claim 2 , wherein the seed layer includes a metal selected from the group consisting of ruthenium claim 2 , copper claim 2 , cobalt claim 2 , nickel claim 2 , other noble metals besides ruthenium claim 2 , copper manganese claim 2 , copper alloys claim 2 , ruthenium alloys claim 2 , nickel alloys claim 2 , and cobalt alloys.4. The workpiece of claim 1 , further comprising a barrier layer on the workpiece prior to the first conducting layer.5. The workpiece of claim 4 , wherein the barrier layer is deposited on a substrate.6. The workpiece of claim 1 , wherein the second conducting layer includes copper.7. The workpiece of claim 1 , wherein the second conducting layer is deposited using a damascene fill process.8. The workpiece of claim 1 , wherein the second conducting layer is deposited using an electrochemical deposition process.9. The workpiece of claim 1 , further including a wet seed layer on the chemisorbed layer claim 1 , then depositing the second conducting layer on the wet seed layer using a damascene fill process.10. The workpiece of claim 9 , wherein the wet seed layer is composed of copper deposited on the ...

Semiconductor device

The reliability of a semiconductor device is improved. A package of a semiconductor device internally includes a first semiconductor chip and a second semiconductor chip in which power MOS•FETs are formed and a third semiconductor chip in which a control circuit controlling the first and second semiconductor chips is formed. The first to third semiconductor chips are mounted on die pads respectively. Source electrode bonding pads of the first semiconductor chip on a high side are electrically connected with a first die pad of the die pads via a metal plate. On a top surface of the die pad 7 D 2 , a plated layer formed in a region where the second semiconductor chip is mounted, and another plated layer formed in a region where the metal plate is joined are provided and the plated layers are separated each other with a region where no plated layer is formed in between.

Power Device with Solderable Front Metal

Some exemplary embodiments of a III-nitride power device including a HEMT with multiple interconnect metal layers and a solderable front metal structure using solder bars for external circuit connections have been disclosed. The solderable front metal structure may comprise a tri-metal such as TiNiAg, and may be configured to expose source and drain contacts of the HEMT as alternating elongated digits or bars. Additionally, a single package may integrate multiple such HEMTs wherein the front metal structures expose alternating interdigitated source and drain contacts, which may be advantageous for DC-DC power conversion circuit designs using III-nitride devices. By using solder bars for external circuit connections, lateral conduction is enabled, thereby advantageously reducing device Rdson.

Circuit package, an electronic circuit package, and methods for encapsulating an electronic circuit

A circuit package is provided, the circuit package including: an electronic circuit; a metal block next to the electronic circuit; encapsulation material between the electronic circuit and the metal block; a first metal layer structure electrically contacted to at least one first contact on a first side of the electronic circuit; a second metal layer structure electrically contacted to at least one second contact on a second side of the electronic circuit, wherein the second side is opposite to the first side; wherein the metal block is electrically contacted to the first metal layer structure and to the second metal layer structure by means of an electrically conductive medium; and wherein the electrically conductive medium includes a material different from the material of the first and second metal layer structures or has a material structure different from the material of the first and second metal layer structures.

Semiconductor power module and method of manufacturing the same

A semiconductor power module according to the present invention includes a base member, a semiconductor power device having a surface and a rear surface with the rear surface bonded to the base member, a metal block, having a surface and a rear surface with the rear surface bonded to the surface of the semiconductor power device, uprighted from the surface of the semiconductor power device in a direction separating from the base member and employed as a wiring member for the semiconductor power device, and an external terminal bonded to the surface of the metal block for supplying power to the semiconductor power device through the metal block.

Discrete semiconductor device package and manufacturing method

Disclosed is a discrete semiconductor device package ( 100 ) comprising a semiconductor die ( 110 ) having a first surface and a second surface opposite said first surface carrying a contact ( 112 ); a conductive body ( 120 ) on said contact; an encapsulation material ( 130 ) laterally encapsulating said conductive body; and a capping member ( 140, 610 ) such as a solder cap, a further semiconductor die or a combination thereof in conductive contact with the solder portion, said solder cap extending over the encapsulation material. A further solder cap ( 150 ) may be provided over the first surface. A method of manufacturing such a discrete semiconductor device package is also disclosed.

Cooling apparatus

A cooling apparatus includes a case in which a refrigerant passage through which a refrigerant flows is formed inside, and an element module partially disposed within the refrigerant passage and including an element provided inside. A portion of the element module in contact with the refrigerant is formed of an insulating material.

Semiconductor device and method for manufacturing the same

A semiconductor device includes a first semiconductor chip including a first surface and a plurality of first electrodes disposed on the first surface; a second semiconductor chip including a second surface which faces the first surface, a plurality of second electrodes each of which includes at least one end disposed on the second surface, and a plurality of first protrusions each of which surrounds the one end of each of the second electrodes on an electrode by electrode basis; a plurality of conductive joint materials each of which joins a third electrode included in the first electrodes to the one end of an electrode which faces the third electrode among the second electrodes; and a plurality of first underfill resins each of which is disposed inside one of the first protrusions and covers one of the conductive joint materials on a material by material basis.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device has a connection structure in which a power semiconductor chip is mounted on an insulating substrate having conductor patterns bonded to front and rear surfaces thereof, and the insulating substrate is connected to a heat-dissipating base member to dissipate heat generated from the power semiconductor chip to outside. The conductor pattern on the rear surface bonded to the heat-dissipating base member has a bonding portion having a rectangular shape and a predetermined curvature radius in vicinity of corners. 1. A semiconductor device comprising:a connection structure in which a power semiconductor chip is mounted on an insulating substrate having conductor patterns bonded to front and rear surfaces thereof, and the insulating substrate is connected to a heat-dissipating base member to dissipate heat generated from the power semiconductor chip to outside,wherein the conductor pattern on the rear surface bonded to the heat-dissipating base member has a bonding portion having a rectangular shape and a predetermined curvature radius in vicinity of corners.2. The semiconductor device according to claim 1 , wherein a metal terminal having one end bonded to the conductor pattern on the front surface mounted with the power semiconductor chip has a bonding portion having a circular shape.3. The semiconductor device according to claim 1 , wherein the rear surface of the insulating substrate bonded to the heat-dissipating base member is formed with the conductor pattern including a plurality of divided conductor layers.4. The semiconductor device according to claim 1 , wherein the conductor pattern on the rear surface bonded to the heat-dissipating base member includes bonding portions protruding toward the heat-dissipating base member on each of a plurality of divided regions of the conductor pattern.5. The semiconductor device according to claim 1 , wherein the conductor pattern on the rear surface bonded to the heat-dissipating base member is formed ...

Semiconductor device, and method of manufacturing semiconductor device

A semiconductor device which can reduce a heat stress to a solder layer while suppressing an increase of thermal resistance is provided. A semiconductor device includes a semiconductor element, a solder layer which is arranged on at least one surface of the semiconductor element and a lead frame which is arranged on the solder layer so that a porous nickel plating part is sandwiched between the lead frame and the solder layer. Compared with a case that the semiconductor element and the lead frame are jointed by a solder directly, an increased part of a thermal resistance of the solder junction is held down only to a part of the porous nickel plating part and a thermal resistance applied to the solder layer can be reduced.

Method of manufacturing semiconductor device

In a semiconductor device formed by mounting a chip laminate including a semiconductor chip having a small diameter and a semiconductor chip having a large diameter over the top surface of a substrate, an excessive stress is prevented from being added to a joint of the two semiconductor chips. By mounting a first semiconductor chip having a large diameter over a support substrate and thereafter mounting a second semiconductor chip having a small diameter over the first semiconductor chip, it is possible to: suppress the inclination and unsteadiness of the second semiconductor chip mounted over the first semiconductor chip; and hence inhibit an excessive stress from being added to a joint of the first semiconductor chip and the second semiconductor chip.

Resin-encapsulated semiconductor device and method of manufacturing the same

A resin-encapsulated semiconductor device includes: a semiconductor element mounted on a die pad portion; a plurality of lead portions disposed so that distal end parts thereof are opposed to the die pad portion; a metal thin wire for connecting an electrode of the semiconductor element to the lead portion; and an encapsulating resin for partially encapsulating those components. A bottom surface part of the die pad portion, and a bottom surface part, an outer surface part, and an upper end part of the lead portion are exposed from the encapsulating resin. A plated layer is formed on the exposed lead bottom surface part and the exposed lead upper end part.

Power Semiconductor Package with Non-Contiguous, Multi-Section Conductive Carrier

In one implementation, a power semiconductor package includes a non-contiguous, multi-section conductive carrier. A control transistor with a control transistor terminal is coupled to a first section of the multi-section conductive carrier, while a sync transistor with a sync transistor terminal is coupled to a second section of the multi-section conductive carrier. The first and second sections of the multi-section conductive carrier sink heat generated by the control and sync transistors. The first and second sections of the multi-section conductive carrier are electrically connected only through a mounting surface attached to the power semiconductor package. Another implementation of the power semiconductor package includes a driver IC coupled to a third section of the multi-section conductive carrier. A method for fabricating the power semiconductor package is also disclosed. The power semiconductor package according to the present disclosure results in effective thermal protection, current carrying capability, and a relatively small size.

Die connections using different underfill types for different regions

Die connections are described using different underfill types for different regions. In one example, a first electrically-non-conductive underfill paste (NCP) type is applied to an I/O region of a first die. A second NCP type is applied outside the I/O region of the first die, the second NCP type having more filler than the first NCP type, and the second die is bonded to a first die using the NCP.

LEAD FRAME AND STACK PACKAGE MODULE INCLUDING THE SAME

A lead frame and a stack package module including the same are provided. The lead frame including a lower-end coupling portion coupled to a lower package through soldering, and an upper-end connecting portion contacting a side surface groove formed in a side surface of an upper package to support the upper package. 1. A lead frame comprising:a lower-end coupling portion coupled to a lower package through soldering; andan upper-end connecting portion contacting a side surface groove formed in a side surface of an upper package to support the upper package.2. The lead frame of claim 1 , further comprising an intermediate seating portion disposed between the lower-end coupling portion and the upper-end connecting portion claim 1 , the intermediate seating portion protruding in a direction different from a reference direction perpendicular to an upper surface of the lower package so as to allow the upper package to be seated thereon.3. The lead frame of claim 2 , wherein the intermediate seating portion is closer to the upper-end connecting portion than the lower-end coupling portion.4. The lead frame of claim 3 , wherein the intermediate seating portion is formed so that the lower-end coupling portion and the upper-end connecting portion are aligned along a same axis in the reference direction claim 3 , andthe intermediate seating portion protrudes toward the upper package.5. The lead frame of claim 4 , wherein the intermediate seating portion has a laid “U” shape or a laid “I” shape.6. The lead frame of claim 3 , wherein the intermediate seating portion comprises an inclined portion that is inclined with respect to the reference direction so that the lower-end coupling portion is positioned inwardly of the upper-end connecting portion in a direction parallel with the upper package.7. The lead frame of claim 1 , wherein the upper-end connecting portion is inclined toward the upper package from a reference direction perpendicular to an upper surface of the lower package ...

Display panel and manufacturing method for same

A display panel having a display region and a non-display region, the display panel includes: a substrate having at least one first opening; an electronic component disposed on the substrate; a plurality of pads disposed in the non-display region and including a first pad and a second pad are spaced apart from each other in a first direction with the at least one first opening therebetween; and an adhesive layer disposed between the substrate and the electronic component and overlapping the at least one first opening.

Printed circuit board element and method for producing a printed circuit board element

The invention relates to an electronic component, namely a printed circuit board element comprising a first semiconductor component () which is arranged on an upper side of an electrically conductive intermediate plate () such that a connector pad () of the semiconductor component () is electrically contacted with the intermediate plate () and comprising a second semiconductor component () which is arranged on a lower side of the intermediate plate (). The second semiconductor component () comprises a first connector pad () and a second connector pad (), wherein both connector pads () are aligned in the direction of the intermediate plate () and wherein the first connector pad () is contacted with the intermediate plate (), and wherein the second connector pad () is not contacted with the intermediate plate (). Moreover, the invention relates to a method for producing such a printed circuit board element. 1. A printed circuit board element comprising:a first semiconductor component which is arranged on an upper side of an electrically conductive intermediate plate such that a connector pad of the first semiconductor component has a whole-area electrical contact with the intermediate plate;a second semiconductor component which is arranged on a lower side of the intermediate plate;the second semiconductor component comprises a first connector pad and a second connector pad;both connector pads are aligned in the direction of the intermediate plate; andthe first connector pad is contacted with the intermediate plate, the second connector pad is not contacted with the intermediate plate, and the intermediate plate forms a phase tap of the printed circuit board element.2. The printed circuit board element as claimed in claim 1 , wherein the intermediate plate comprises a recess for avoiding electrical contact between the intermediate plate and the second connector pad of the second semiconductor component.3. The printed circuit board element as claimed in claim 2 , ...

Semiconductor assemblies including vertically integrated circuits and methods of manufacturing the same

Semiconductor assemblies including thermal management configurations for reducing heat transfer between vertically stacked devices and associated systems and methods are disclosed herein. In some embodiments, the semiconductor assemblies comprise at least one memory device mounted over a logic device with a thermally conductive layer, a thermal-insulator interposer, or a combination thereof disposed between the memory device and the logic device. The thermally conductive layer includes a structure configured to transfer the thermal energy across a horizontal plane. The thermal-insulator interposer includes a structure configured to reduce heat transfer between the logic device and the memory device.

SCALABLE PACKAGE ARCHITECTURE AND ASSOCIATED TECHNIQUES AND CONFIGURATIONS

Embodiments of the present disclosure describe scalable package architecture of an integrated circuit (IC) assembly and associated techniques and configurations. In one embodiment, an integrated circuit (IC) assembly includes a package substrate having a first side and a second side disposed opposite to the first side, a first die having an active side coupled with the first side of the package substrate and an inactive side disposed opposite to the active side, the first die having one or more through-silicon vias (TSVs) configured to route electrical signals between the first die and a second die, and a mold compound disposed on the first side of the package substrate, wherein the mold compound is in direct contact with a sidewall of the first die between the active side and the inactive side and wherein a distance between the first side and a terminating edge of the mold compound that is farthest from the first side is equal to or less than a distance between the inactive side of the first die and the first side. Other embodiments may be described and/or claimed. 111-. (canceled)12. A method for fabricating an integrated circuit (IC) assembly , comprising:providing a package substrate having a first side and a second side disposed opposite to the first side;coupling an active side of a first die with the first side of the package substrate, the first die including an inactive side disposed opposite to the active side and one or more through-silicon vias (TSVs) configured to route electrical signals between the first die and a second die; andforming a mold compound on the first side of the package substrate, wherein the mold compound is in direct contact with a sidewall of the first die between the active side and the inactive side and wherein a distance between the first side and a terminating edge of the mold compound that is farthest from the first side is equal to or less than a distance between the inactive side of the first die and the first side;mounting ...

Semiconductor package

A semiconductor package includes a first die including a signal region and a peripheral region bordering the signal region and having first vias in the peripheral region, a second die stacked on the first die and having second vias at positions corresponding to the first vias in the peripheral region, and first connection terminals between the first die and the second die that are configured to connect the second vias to the first vias, respectively. The peripheral region includes first regions and second regions configured to transmit different signals, which are alternately arranged in a first direction. The first vias are arranged in at least two rows along a second direction intersecting the first direction in each of the first and second regions.

MICRO LED DISPLAY HAVING MULTI-COLOR PIXEL ARRAY AND METHOD OF FABRICATING THE SAME BASED ON INTEGRATION WITH DRIVING CIRCUIT THEREOF

Disclosed is a micro LED display having a multi-color pixel array and a method of fabricating the same based on integration with a driving circuit thereof. According to various embodiments, the display may be fabricated by providing an IC device in which a driving circuit has been wired, forming, in one surface of the IC device, a plurality of pixels on which a plurality of partial pixels for emitting different color lights has been stacked, and electrically connecting the partial pixels to the driving circuit using connection members. 1. A method of fabricating a display , comprising:providing an integrated circuit (IC) device in which a driving circuit has been wired;forming, in one surface of the IC device, a plurality of pixels on which a plurality of partial pixels for emitting different color lights has been stacked; andelectrically connecting the partial pixels to the driving circuit using connection members.2. The method of claim 1 , wherein the forming of the pixels comprises:forming, in the one surface, assemblies on which a plurality of pixels layers for emitting different color lights has been stacked; anddividing the assemblies into the pixels by cutting the assemblies.3. The method of claim 2 , wherein:the partial pixels are individually divided from the pixel layers, and the partial pixels comprise:a first partial pixel mounted on the one surface and for emitting a first color light;a second partial pixel stacked on the first partial pixel and for emitting a second color light; anda third partial pixel stacked on the second partial pixel and for emitting a third color light.4. The method of claim 3 , wherein the forming of the assemblies comprises:growing a first pixel layer to be divided as the first partial pixel, a second pixel layer to be divided as the second partial pixel, and a third pixel layer to be divided as the third partial pixel on a first substrate, a second substrate, and a third substrate, respectively;attaching the first pixel layer ...

SEMICONDUCTOR STRUCTURE AND FORMING METHOD THEREOF

The present invention relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a first substrate; a first adhesive layer disposed on a surface of the first substrate; and a first bonding layer disposed on a surface of the first adhesive layer. A density of the first adhesive layer is greater than a density of the first bonding layer. The first adhesive layer of the semiconductor structure has higher adhesion with the first substrate and first bonding layer, such that it is advantageous to improve a performance of the semiconductor structure. 1. A semiconductor structure , comprising:a first substrate;a first adhesive layer disposed on a surface of the first substrate; anda first bonding layer disposed on a surface of the first adhesive layer, wherein a density of the first adhesive layer is greater than a density of the first bonding layer.2. The semiconductor structure of claim 1 , wherein the first bonding layer comprises a dielectric material comprising carbon (C).3. The semiconductor structure of claim 2 , wherein the first bonding layer further comprises silicon (Si) and nitrogen (N).4. The semiconductor structure of claim 1 , wherein the first adhesive layer comprises at least one of silicon nitride claim 1 , silicon oxynitride and silicon oxide.5. The semiconductor structure of claim 1 , wherein a thickness of the first adhesive layer ranges from 30 Å to 100 Å.6. The semiconductor structure of claim 2 , wherein an atomic concentration of the carbon is uniform in the first bonding layer claim 2 , or the atomic concentration of the carbon is increased as a thickness of the first bonding layer is increased.7. The semiconductor structure of claim 1 , further comprising a second substrate claim 1 , wherein a second adhesive layer and a second bonding layer disposed on a surface of the second adhesive layer are formed on a surface of the second substrate claim 1 , a density of the second adhesive layer is ...

SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME

A semiconductor structure and a method of forming the same are provided. The semiconductor structure includes a first substrate; a first adhesive layer disposed on the surface of the first substrate; a first buffer layer disposed on the surface of the first adhesive layer; and a first bonding layer disposed on the surface of the first buffer layer, wherein the densities of the first adhesive layer and the first buffer layer are greater than that of the first bonding layer. The first adhesive layer of the semiconductor structure has higher adhesion with the first substrate and the first buffer layer, and the first buffer layer and the first bonding layer exhibit higher adhesion, which are beneficial to improve the performance of the semiconductor structure. 1. A semiconductor structure , comprising:a first substrate;a first adhesive layer disposed on a surface of the first substrate;a first buffer layer disposed on a surface of the first adhesive layer; and 'the first adhesive layer and a density of the first buffer layer are both greater than a density of the first bonding layer.', 'a first bonding layer disposed on a surface of the first buffer layer, wherein a density of'}2. The semiconductor structure of claim 1 , wherein a material of the first bonding layer and a material of the first buffer layer comprise a dielectric material comprising carbon (C) claim 1 , and an atomic concentration of carbon in the first bonding layer is greater than an atomic concentration of carbon in the first buffer layer.3. The semiconductor structure of claim 2 , wherein the atomic concentration of carbon in the first bonding layer is greater than 35% claim 2 , and the atomic concentration of carbon in the first buffer layer is in a range from 0% to 50%.4. The semiconductor structure of claim 2 , wherein the atomic concentration of carbon in the first bonding layer is increased as a thickness of the first bonding layer is increased claim 2 , and the atomic concentration of carbon in ...

Semiconductor structure and method of forming the same

The present invention relates to a semiconductor structure and method of forming the same. The semiconductor structure includes a first substrate, a first adhesive/bonding stack on the surface of first substrate, wherein the first adhesive/bonding stack includes at least one first adhesive layer and at least one first bonding layer. The material of first bonding layer includes dielectrics such as silicon, nitrogen and carbon, the material of first adhesive layer includes dielectrics such as silicon and nitrogen, and the first adhesive/bonding stack of semiconductor structure is provided with higher bonding force in bonding process.

SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME

The present invention relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a first substrate, and a bonding layer located on a surface of the first substrate. The material of the first bonding layer is a dielectric material containing element carbon (C). C atomic concentration of a surface layer of the first bonding layer away from the first substrate is higher than or equal to 35%. The first bonding layer of the semiconductor structure may be used to enhance bonding strength during bonding. 1. A semiconductor structure , comprising:a first substrate; anda first bonding layer located on a surface of the first substrate, wherein a material of the first bonding layer is a dielectric material containing element carbon (C), and C atomic concentration of a surface layer of the first bonding layer away from the first substrate is higher than or equal to 35%.2. The semiconductor structure according to claim 1 , wherein C atomic concentration distributes uniformly in the first bonding layer.3. The semiconductor structure according to claim 1 , wherein C atomic concentration in the first bonding layer increases gradually with increasing thickness of the first bonding layer.4. The semiconductor structure according to claim 1 , wherein the thickness of the surface layer ranges from 20 angstroms (Å) to 50 angstroms.5. The semiconductor structure according to claim 1 , further comprising:a second substrate, wherein a second bonding layer is formed on a surface of the second substrate, and the second bonding layer is bonded to and fixed on the first bonding layer with a surface of the second bonding layer facing a surface of the first bonding layer.6. The semiconductor structure according to claim 5 , wherein a material of the second bonding layer is a dielectric material containing element C claim 5 , and C atomic concentration of a surface layer of the second bonding layer away from the second substrate is higher than or ...

MANUFACTURING METHOD OF PACKAGE ON PACKAGE STRUCTURE

A manufacturing method of a package on package structure includes the following steps. A first package is provided on a tape carrier, wherein the first package includes an encapsulated semiconductor device, a first redistribution structure disposed on a first side of the encapsulated semiconductor device, and a plurality of conductive bumps disposed on the first redistribution structure and attached to the tape carrier. A second package is mounted on the first package through a plurality of electrical terminals by a thermo-compression bonding process, which deforms the conductive bumps into a plurality of deformed conductive bumps. Each of the deformed conductive bumps comprises a base portion connecting the first redistribution structure and a tip portion connecting the base portion, and a curvature of the base portion is substantially smaller than a curvature of the tip portion. 1. A manufacturing method of a package on package structure , comprising:providing a first package on a tape carrier, wherein the first package comprises an encapsulated semiconductor device, a first redistribution structure disposed on a first side of the encapsulated semiconductor device, and a plurality of conductive bumps disposed on the first redistribution structure and attached to the tape carrier; andmounting a second package on the first package through a plurality of electrical terminals by a thermo-compression bonding process, which deforms the conductive bumps into a plurality of deformed conductive bumps,wherein each of the deformed conductive bumps comprises a base portion connecting the first redistribution structure and a tip portion connecting the base portion, and a curvature of the base portion is substantially smaller than a curvature of the tip portion.2. The manufacturing method of the package on package structure as claimed in claim 1 , wherein a maximum diameter of the tip portion is substantially smaller than a maximum diameter of the base portion.3. The ...

COOLING SOLUTION DESIGNS FOR MICROELECTRONIC PACKAGES

Methods of forming microelectronic package structures/modules, and structures formed thereby, are described. Structures formed herein may include a first die disposed on a substrate and a second die disposed adjacent the first die on the substrate. A cooling solution is attached to the substrate, wherein a rib extends from a central region of the cooling solution and is attached to the substrate. The rib is disposed between the first die and the second die. 1. A microelectronic package structure comprising:a first die on a substrate;a second die adjacent the first die on the substrate; a planar portion at least partially over the first die and the second die;', 'a peripheral portion of the cooling solution extending from the planar portion and attached to a peripheral portion of the substrate; and', 'a rib extending from the planar portion and attached to a central portion of the substrate, wherein the rib is directly on a portion of a sidewall of at least one of the first die or the second die., 'a cooling solution comprising2. The microelectronic package structure of wherein the cooling solution comprises an integrated heat spreader.3. The microelectronic package structure of wherein a first thermal interface material (TIM) is on a backside of the first die claim 1 , wherein the backside of the first die is opposite an active side of the first die claim 1 , and a second TIM is on a backside of the second die claim 1 , wherein the backside of the second die is opposite an active side of the second die claim 1 , and wherein the rib is between the first TIM and the second TIM claim 1 , wherein a thickness of the first TIM is different than a thickness of the second TIM claim 1 , and wherein the rib is directly on the first TIM and is directly on the second TIM.4. The microelectronic package structure of wherein a sealant is between the rib and the substrate.5. The microelectronic package structure of wherein the rib is continuous between opposite sides of the ...

Semiconductor Package, and a Method for Forming a Semiconductor Package

A semiconductor package includes a semiconductor die arranged on a substrate. The semiconductor package includes a stiffener structure arranged on the substrate. The stiffener structure is spaced at a distance from the semiconductor die. The stiffener structure includes a molding compound material.

METHOD OF FORMING SEMICONDUCTOR STRUCTURE

The present invention relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a first substrate, and a bonding layer located on a surface of the first substrate. The material of the first bonding layer is a dielectric material containing element carbon (C). C atomic concentration of a surface layer of the first bonding layer away from the first substrate is higher than or equal to 35%. The first bonding layer of the semiconductor structure may be used to enhance bonding strength during bonding. 1. A method of forming a semiconductor structure , comprising:providing a first substrate;{'sub': '3', 'forming a first bonding layer on a surface of the first substrate, wherein a material of the first bonding layer is a dielectric material containing element carbon (C) and a CHbond;'}providing a second substrate;{'sub': '3', 'forming a second bonding layer on a surface of the second substrate, wherein a material of the second bonding layer is a dielectric material containing element C and a CHbond;'}{'sub': '3', 'oxidizing a surface layer of the first bonding layer and a surface layer of the second bonding layer, wherein the CHbonds are oxidized to be OH bonds; and'}bonding the first bonding layer and the second bonding layer to each other correspondingly.2. The method of forming the semiconductor structure according to claim 1 , wherein C atomic concentration within the surface layer of the first bonding layer and C atomic concentration within the surface layer of the second bonding layer are higher than or equal to 35%.3. The method of forming the semiconductor structure according to claim 1 , wherein the first bonding layer is formed by a plasma-enhanced chemical vapor deposition process.4. The method of forming the semiconductor structure according to claim 3 , wherein a reactive gas used in the plasma-enhanced chemical vapor deposition process comprises NHand one of trimethylsilane or tetramethylsilane.5. The method ...

Method for forming Board Assembly with Chemical Vapor Deposition Diamond (CVDD) Windows for Thermal Transport

A method for forming a board assembly includes identifying a location of a hot-spot on a semiconductor die and cutting an opening in a circuit board corresponding to the location of the identified hot-spot. A Chemical Vapor Deposition Diamond (CVDD) window is inserted into the opening. A layer of thermally conductive paste is applied over the CVDD window. The semiconductor die is placed over the layer of thermally conductive paste such that the CVDD window underlies the hot-spot and such that a surface of the semiconductor die is in direct contact with the layer of thermally conductive paste. 1. A method for forming a board assembly comprising:identifying a location of a hot-spot on a semiconductor die;cutting an opening in a circuit board corresponding to the location of the identified hot-spot;inserting a Chemical Vapor Deposition Diamond (CVDD) window into the opening;applying a layer of thermally conductive paste over the CVDD window; andplacing the semiconductor die over the layer of thermally conductive paste such that the CVDD window underlies the hot-spot and such that a surface of the semiconductor die is in direct contact with the layer of thermally conductive paste.2. The method of further comprising: attaching leads to the semiconductor die and the circuit board to electrically couple the die to the first circuit board.3. The method of further comprising: forming a dam around the semiconductor die and attaching an additional circuit board to the dam so as to enclose the semiconductor die within the dam and between the circuit board and the additional circuit board.4. The method of further comprising: dispensing filler material within the enclosure.5. The method of claim 4 , wherein the filler material comprises diamond paste.6. The method of claim 1 , wherein the CVDD window has a thickness that is the same as the thickness of the circuit board.7. The method of claim 1 , wherein the CVDD window has a thickness that is greater than a thickness of the ...

Semiconductor module

A semiconductor module includes a semiconductor device having a gate runner extending in a first direction at an upper surface of the semiconductor device, and a metal wiring plate having a first bonding portion with a bonding surface to which the upper surface of the semiconductor device is bonded via a first bonding material. The first bonding portion has a plurality of first protrusions at the bonding surface. Each first protrusion protrudes toward the semiconductor device, and is provided in a position away from the gate runner by a first distance in a plan view of the semiconductor module.

MICROELECTRONIC ASSEMBLIES WITH INTEGRATED CIRCUITS AND INTERPOSERS WITH CAVITIES, AND METHODS OF MANUFACTURE

Semiconductor integrated circuits () or assemblies are disposed at least partially in cavities between two interposers (). Conductive vias (M) pass through at least one of the interposers or at least through the interposer's substrate, and reach a semiconductor integrated circuit or an assembly. Other conductive vias (M.) pass at least partially through multiple interposers and are connected to conductive vias that reach, or are capacitively coupled to, a semiconductor IC or an assembly. Other features are also provided. 1. A method for fabricating a microelectronic assembly , the method comprising: a plurality of interposers overlying one another and comprising a first interposer and a second interposer, each of the first and second interposers comprising a first side facing the other one of the first and second interposers and comprising a second side opposite to the first side, wherein at least the first interposer comprises one or more first contact pads at its first side; and', 'one or more first modules attached to the first interposer between the first and second interposers, at least one first module comprising a semiconductor integrated circuit and comprising one or more contact pads electrically coupled to the integrated circuit and to at least one first contact pad; and, 'obtaining a first structure comprisingwherein at least one of the first and second interposers comprises one or more first cavities, and at least part of each first module is located in a respective first cavity; andafter obtaining the first structure, forming one or more first conductive vias each of which passes through at least part of at least one of the first and second interposers to reach at least one respective first cavity and to physically contact, or be capacitively coupled to, circuitry of at least one respective first module at least partially located in the respective first cavity.2. The method of wherein at least one first conductive via enters at least one respective ...

SEMICONDUCTOR DEVICE

A semiconductor device includes a metal member, a first semiconductor chip, a second semiconductor chip, a first solder and a second solder. A quantity of heat generated in the first semiconductor chip is greater than the second semiconductor chip. The second semiconductor chip is formed of a material having larger Young's modulus than the first semiconductor chip. The first semiconductor chip has a first metal layer connected to the metal member through a first solder at a surface facing the metal member. The second semiconductor chip has a second metal layer connected to the metal member through a second solder at a surface facing the metal member. A thickness of the second solder is greater than a maximum thickness of the first solder at least at a portion of the second solder corresponding to a part of an outer peripheral edge of the second metal layer. 1. A semiconductor device comprising:a metal member;a first semiconductor chip that is disposed on a surface of the metal member and has a first metal layer at a surface facing the metal member;a second semiconductor chip that is formed of a material having larger Young's modulus than the first semiconductor chip and is disposed at a position different from the first semiconductor chip on the surface of the metal member, the second semiconductor chip having a second metal layer at a surface facing the metal member;a first solder that is disposed between the metal member and the first metal layer of the first semiconductor chip and connects the metal member and the first metal layer; anda second solder that is disposed between the metal member and the second metal layer of the second semiconductor chip and connects the metal member and the second metal layer, whereina quantity of heat generated in the first semiconductor chip is greater than a quantity of heat generated in the second semiconductor chip, anda thickness of the second solder is greater than a maximum thickness of the first solder at least at a ...

Electronic component device

An electronic component device includes a first lead frame having a first connection terminal and an electronic component. The first connection terminal includes a first metal electrode, a first pad part formed on an upper surface of the first metal electrode and formed by a metal plated layer, and a first metal oxide layer formed on an upper surface of the first metal electrode in a surrounding region of the first pad part so as to surround an outer periphery of the first pad part. The electronic component has a first terminal part provided on its lower surface. The first terminal part of the electronic component is connected to the first pad part of the first connection terminal via a metal joining material.

BRIDGE INTERCONNECTION WITH LAYERED INTERCONNECT STRUCTURES

Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed. 1. An apparatus comprising:a substrate having a cavity;a bridge embedded in the substrate cavity;a dielectric material laminated over the bridge in the cavity;a joint electrically coupled with the bridge, to route electrical signals beyond a surface of the substrate, a barrier layer including a second conductive material disposed directly on the joint, and', 'a solder layer that includes a third conductive material, disposed directly on the barrier layer, wherein the barrier layer and the solder layer are to route the electrical signals., 'wherein the joint includes a first conductive material;'}2. The apparatus of claim 1 , wherein the joint comprises a via.3. The apparatus of claim 1 , wherein the solder layer comprises a substantially round bump claim 1 , formed by a reflow of the solder layer.4. The apparatus of claim 1 , wherein the first conductive material comprises copper (Cu) claim 1 , the second conductive material comprises nickel (Ni) claim 1 , and the third conductive material comprises tin (Sn).5. The apparatus of claim 1 , further comprising:a first die electrically coupled with the bridge; anda second die ...

LEADLESS PACKAGED DEVICE WITH METAL DIE ATTACH

A leadless packaged semiconductor device includes a metal substrate having at least a first through-hole aperture having a first outer ring and a plurality of cuts through the metal substrate to define spaced apart metal pads on at least two sides of the first through-hole aperture. A semiconductor die that has a back side metal (BSM) layer on its bottom side and a top side with circuitry coupled to bond pads is mounted top side up on the first outer ring. A metal die attach layer is directly between the BSM layer and walls of the metal substrate bounding the first through-hole aperture that provides a die attachment that fills a bottom portion of the first through-hole aperture. Bond wires are between metal pads and the bond pads. A mold compound is also provided including between adjacent ones of the metal pads. 19-. (canceled)10. A method of semiconductor device assembly , comprising:providing a metal substrate including a least a first through-hole aperture having a first outer ring that position matches at least a first semiconductor die, with metal pads with partial etch regions in between adjacent ones of the metal pads on at least two sides of the first through-hole aperture, with the first semiconductor die having a back side metal (BSM) layer on its bottom side and a top side with bond pads;inserting the first semiconductor die top side up into respective ones of the first through-hole aperture to sit on the first outer ring;sealing a top side of the first semiconductor die to secure the first semiconductor die in the first through-hole apertures to provide a stack;immersing the stack in a metal electroplating solution within a solution container, with the metal substrate connected to a negative terminal of a power supply and an electrically conductive structure spaced apart from the metal substrate connected to a positive terminal of the power supply, andelectroplating to deposit an electroplated metal die attach layer to fill a volume between the BSM ...

Multi-metal package stiffener

A semiconductor package system includes a semiconductor package including at least one semiconductor device having a first side and a second side and a substrate having a first side and a second side. The second side of the at least one semiconductor device is positioned on the first side of the substrate. At least one stiffener element is provided on the semiconductor package. The at least one stiffener element includes at least two metal elements having different coefficients of thermal expansion joined together.

METHOD OF MANUFACTURING 3DIC STRUCTURE

A method of manufacturing a 3DIC structure includes the following processes. A die is bonded to a wafer. A first dielectric layer is formed on the wafer and laterally aside the die. A second dielectric material layer is formed on the die and the first dielectric layer. A portion of the second dielectric material layer over a non-edge region of the wafer is selectively removed to form a protruding portion over an edge region of the wafer. The second dielectric material layer is planarized to form a second dielectric layer on the first dielectric layer and the die. A bonding film is formed on the second dielectric layer. A carrier is bonded to the wafer through the bonding film. 1. A method of manufacturing a 3DIC structure , comprising:bonding a die to a wafer;forming a first dielectric layer on the wafer and laterally aside the die;forming a second dielectric material layer on the die and the first dielectric layer;selectively removing a portion of the second dielectric material layer over a non-edge region of the wafer to form a protruding portion over an edge region of the wafer; andplanarizing the second dielectric material layer to form a second dielectric layer on the first dielectric layer and the die.2. The method of claim 1 , where the selectively removing the portion of the second dielectric material layer comprises:forming a mask layer on the second dielectric material layer;pattering the mask layer to form a patterned mask layer having an opening, wherein the patterned mask layer covers the second dielectric material layer on the edge region of the wafer, and the opening exposes the portion of the second dielectric material layer over the non-edge region of the wafer;etching the portion of the second dielectric material layer exposed by the opening, wherein the second dielectric material layer covered by the patterned mask layer form the protruding portion; andremoving the patterned mask layer.3. The method of claim 1 , wherein the planarizing the second ...

SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME

A semiconductor chip includes a semiconductor substrate, a through electrode, an inter-mediation pad, an upper pad, and a rewiring line. The semiconductor substrate includes a first surface that is an active surface and a second surface that is opposite to the first surface. The through electrode penetrates the semiconductor substrate and is disposed in at least one column in a first direction in a center portion of the semiconductor substrate. The inter-mediation pad is disposed in at least one column in the first direction in an edge portion of the second surface. The upper pad is disposed on the second surface and connected to the through electrode. The rewiring line is disposed on the second surface and connects the inter-mediation pad to the upper pad. 1. A semiconductor chip , comprising:a semiconductor substrate comprising a first surface that is an active surface and a second surface that is opposite to the first surface;a through electrode penetrating the semiconductor substrate and disposed in at least one column in a first direction in a center portion of the semiconductor substrate;an inter-mediation pad disposed in at least one column in the first direction in an edge portion of the second surface;an upper pad disposed on the second surface and connected to the through electrode; anda rewiring line disposed on the second surface and connecting the inter-mediation pad to the upper pad.2. The semiconductor chip of claim 1 ,wherein a number of the at least one column of the inter-mediation pad is equal to a number of additional semiconductor chips disposed on the semiconductor substrate,wherein a region in which the inter-mediation pad is disposed is divided into a first region and a second region in the first direction,a region in which the upper pad is disposed is divided into a third region corresponding to the first region and a fourth region corresponding to the second region in the first direction,wherein the inter-mediation pad in the first region ...

SEMICONDUCTOR PACKAGE

A semiconductor package includes a substrate, a first chip on the substrate, a second chip on the substrate and arranged side-by-side with the first chip, and a support structure on the second chip. A width of the support structure is equal to or greater than a width of the second chip. 1. A semiconductor package , comprising:a substrate;at least one first chip on an upper surface of the substrate;a second chip on the upper surface of the substrate and located beside the at least one first chip as viewed in a plan view; anda support structure on the second chip,wherein a width of the support structure, in a direction parallel to the upper surface of the substrate, is equal to or greater than a width of the second chip in said direction.2. The semiconductor package of claim 1 , wherein a distance from the upper surface of the substrate to a top surface of the support structure is substantially the same as a distance from the upper surface of the substrate to a top surface of an uppermost one the at least one first chip.3. The semiconductor package of claim 1 , wherein the support structure comprises a block of insulating material claim 1 , a dummy chip claim 1 , or a memory chip.4. The semiconductor package of claim 1 , wherein the support structure comprises silicon (Si).5. The semiconductor package of claim 1 , wherein each said at least one first chip is a memory chip claim 1 , andthe second chip is a logic chip.6. The semiconductor package of claim 1 , wherein the at least one first chip is wire-bonded to the substrate claim 1 , andthe second chip is flip-chip bonded to the substrate.7. The semiconductor package of claim 5 , wherein the at least one first chip comprises a stack of first chips.8. The semiconductor package of claim 1 , further comprising at least one third chip on the at least one first chip and the second chip.9. The semiconductor package of claim 1 , further comprising at least one third chip on the at least one first chip and the support ...

SEMICONDUCTOR DEVICE FOR ELECTRIC POWER

Herein provided are: a ceramic board; a semiconductor element for electric power, on one surface of which an electrode is formed, and the other surface of which is bonded to the ceramic board; a lead terminal, one end side of which is bonded to the electrode, and the other end side of which is to be electrically connected to an outside thereof; and a sealing member by which the semiconductor element for electric power is sealed together with a part, in the lead terminal, bonded to the electrode; wherein, near an end in said one end side of the lead terminal, an inclined surface is formed which becomes farther from the circuit board as it becomes closer to the end. 1. A semiconductor device for electric power , comprising:a circuit board;a semiconductor element for electric power, on one surface of which an electrode is formed, and the other surface of which is bonded to the circuit board;a lead terminal, one end side of which is bonded to the electrode, and the other end side of which is to be electrically connected to an outside thereof; anda sealing member by which the semiconductor element for electric power is sealed together with a part, in the lead terminal, bonded to the electrode;wherein, near an end in said one end side of the lead terminal, an inclined surface is formed which becomes farther from the circuit board as it becomes closer to the end.2. The semiconductor device for electric power according to claim 1 , wherein the lead terminal is bent near the end so as to form the inclined surface.38-. (canceled)9. The semiconductor device for electric power according to claim 1 , wherein claim 1 , the lead terminal has a wall thickness that becomes thinner toward the end so as to form the inclined surface.10. The semiconductor device for electric power according to claim 2 , wherein claim 2 , the lead terminal has a wall thickness that becomes thinner toward the end so as to form the inclined surface.11. The semiconductor device for electric power according ...

METHOD, APPARATUS AND SYSTEM TO INTERCONNECT PACKAGED INTEGRATED CIRCUIT DIES

Techniques and mechanisms for interconnecting stacked integrated circuit (IC) dies. In an embodiment, a first end of a wire is coupled to a first IC die of a stack, where a second end of the wire is further anchored to the stack independent of the coupled first end. A package material is subsequently disposed around IC dies of the stack and a first portion of the wire that includes the first end. Two-point anchoring of the wire to the stack aids in providing mechanical support to resist movement that might otherwise displace and/or deform the wire while the package material is deposited. In another embodiment, the first portion of the wire is separated from the rest of the wire, and a redistribution Layer is coupled to the first portion to enable interconnection between the first IC die and another IC die of the stack. 124-. (canceled)25. A method comprising:forming a stack comprising multiple integrated circuit (IC) dies including a first IC die and a second IC die;coupling to the first IC die a first end of a first wire;anchoring a second end of the first wire to the stack, wherein the first wire comprises the second end and a first portion including the first end;while the first end is coupled to the first IC die and the second end is anchored to the stack, disposing a package material around the multiple IC dies and the first portion;after disposing the package material around the multiple IC die, separating the second end from the first portion, including exposing another end of the first portion at a first surface of the package material; andcoupling the first IC die to the second IC die, including forming a redistribution layer on the first surface, wherein the redistribution layer is coupled to the second IC die and to the other end of the first portion.26. The method of claim 25 , wherein the stack further comprises a dummy layer claim 25 , and wherein anchoring the second end includes coupling the second end to the dummy stack.27. The method of claim 26 , ...

METHOD FOR MANUFACTURING AN ELECTRONIC ASSEMBLY

A method for manufacturing an electronic assembly features a semiconductor device with a first side and a second side opposite the first side to facilitate enhanced thermal dissipation. The first side has a first conductive pad. The second side has a primary metallic surface. By heating the assembly once, a first substrate (e.g. lead frame) is bonded to a first conductive pad via first metallic bonding layer; and second substrate (e.g., heat sinking circuit board) is bonded to a primary metallic surface via a second metallic bonding layer. In one configuration the second metallic bonding layer is composed of solder and copper, for example. 1. A method for manufacturing an electronic assembly , the method comprising:depositing solder paste on a second substrate;embedding or providing copper material in the deposited solder paste;depositing solder paste on a plurality of upper conductive pads of one or more semiconductor devices, each semiconductor device having a first side with upper conductive pads and a second side opposite the first side;placing and aligning the one or more semiconductor devices on the second substrate;placing and aligning a first substrate on the upper conductive pads; andheating the assembly once to form a first metallic bonding layer between the first substrate and the upper conductive pads and to form a second metallic bonding layer between the second substrate and primary metallic surface on the second side of the one or more semiconductor devices, wherein the second metallic bonding layer is composed of solder and copper pellets or a copper material embedded in the solder as filler, wherein the one or more semiconductor devices have a primary coefficient of thermal expansion (CTE) and wherein the first substrate has a secondary coefficient of thermal expansion (CTE), and wherein the copper material in the first metallic bonding layer or the second metallic bonding layer, respectively, reduces a mismatch between the primary CTE and the ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME, AND POWER CONVERSION DEVICE

A semiconductor device includes an insulating substrate, a semiconductor element, a conductor substrate, and a case member. The semiconductor element is connected above the insulating substrate, and the conductor substrate is connected above the semiconductor element. The case member surrounds a region overlapping with the insulating substrate, the semiconductor element, and the conductor substrate in plan view to avoid the region. A plurality of metal patterns are arranged on a main surface of an insulating layer. A groove is formed between a pair of adjacent metal patterns of the plurality of metal patterns. A through hole is formed in the conductor substrate at a position overlapping with the groove in plan view. 1. A semiconductor device comprising:an insulating substrate including an insulating layer;a semiconductor element connected above the insulating substrate;a conductor substrate connected above the semiconductor element; anda case member surrounding a region overlapping with the insulating substrate, the semiconductor element, and the conductor substrate in plan view to avoid the region,a plurality of metal patterns being arranged to be spaced from each other on a main surface of the insulating layer,a groove being formed between a pair of adjacent metal patterns of the plurality of metal patterns,a through hole being formed in the conductor substrate at a position overlapping with the groove in plan view,a sealant being filled into the region surrounded by the case member.2. The semiconductor device according to claim 1 , wherein claim 1 , in the insulating substrate claim 1 , the insulating layer is joined to a metal plate to be integrated therewith.3. The semiconductor device according to claim 1 , wherein the groove is formed to linearly extend in plan view between the pair of adjacent metal patterns.4. The semiconductor device according to claim 1 , whereinthe case member has a rectangular planar shape having long sides and short sides, andthe ...

SEMICONDUCTOR PACKAGE

A semiconductor package includes: a first structure including a plurality of stacked first semiconductor chips and electrically connected to a first redistribution layer through connection vias having different heights; and a second structure including a second semiconductor chip electrically connected to a second redistribution layer. The first and second redistribution layers are electrically connected to each other through an electrical connection member formed on the second structure. 1. A semiconductor package comprising:a plurality of first semiconductor chips each having a first active surface on which a first connection pad is disposed and a first inactive surface, opposing the first active surface, the first semiconductor chips being stacked such that the first connection pads are respectively exposed;a first encapsulant covering at least a portion of each of the plurality of first semiconductor chips;a first connection member disposed in a position lower than a position of the plurality of first semiconductor chips and in a lower portion of the first encapsulant, and including one or more first redistribution layers, and a plurality of connection vias electrically connecting the first connection pads of each of the first semiconductor chips to the one or more first redistribution layers, each of the connection vias penetrating into the first encapsulant, and heights of the connection vias being different from each other;a second semiconductor chip disposed in a position lower than a position of the first connection member, and having a second active surface on which a second connection pad is disposed, and a second inactive surface opposing the second active surface;a second encapsulant disposed in a position lower than a position of the first connection member, and covering at least a portion of the second semiconductor chip;a second connection member disposed in a position lower than positions of the second semiconductor chip and in a lower portion of ...

SEMICONDUCTOR PACKAGE INCLUDING STRESS-EQUALIZING CHIP

A semiconductor package includes a chip stack having a plurality of semiconductor chips vertically stacked on a package substrate. A stress-equalizing chip is disposed on the chip stack, the stress-equalizing chip providing means to reduce the variation in the electrical characteristics of the plurality of semiconductor chips. An encapsulant is disposed on the package substrate and is configured to cover at least a portion of the chip stack. Each of the plurality of semiconductor chips is electrically connected to the package substrate. The stress-equalizing chip is not electrically connected to the substrate or to the plurality of semiconductor chips. 1. A semiconductor package comprising:a chip stack having a plurality of semiconductor chips vertically stacked on a package substrate;a stress-equalizing chip disposed on the chip stack the stress-equalizing chip providing means to reduce a variation in electrical characteristics between the plurality of semiconductor chips; andan encapsulant disposed on the package substrate and configured to cover at least a portion of the chip stack,wherein each of the plurality of semiconductor chips is electrically connected to the package substrate, and the stress-equalizing chip is not electrically connected to the package substrate or the plurality of semiconductor chips.2. The semiconductor package of claim 1 , wherein:each of the plurality of semiconductor chips comprises at least one stress-sensitive region; andthe plurality of semiconductor chips comprises a lower semiconductor chip and an upper semiconductor chip disposed on the lower semiconductor chip,wherein the upper semiconductor chip overlaps the at least one stress-sensitive region of the lower semiconductor chip.3. The semiconductor package of claim 2 , wherein:the plurality of semiconductor chips comprise an uppermost semiconductor chip disposed at an uppermost layer of the chip stack; andthe stress-equalizing chip overlaps the at least one stress-sensitive ...

3DIC STRUCTURE AND METHOD OF FABRICATING THE SAME

Provided is a three dimensional integrated circuit (3DIC) structure including a first die, a second die, and a hybrid bonding structure bonding the first die and the second die. The hybrid bonding structure includes a first bonding structure and a second bonding structure. The first bonding structure includes a first bonding dielectric layer and a first bonding metal layer. The first bonding metal layer is disposed in the first bonding dielectric layer. The first bonding metal layer includes a first via plug and a first metal feature disposed over the first via plug, wherein a height of the first metal feature is greater than or equal to a height of the first via plug. A method of fabricating the 3DIC structure is also provided. 1. A three dimensional integrated circuit (3DIC) structure , comprising:a first die and a second die; and a first bonding dielectric layer; and', 'a first bonding metal layer, disposed in the first bonding dielectric layer, wherein the first bonding metal layer comprises a first via plug and a first metal feature disposed over the first via plug, a height of the first metal feature is greater than or equal to a height of the first via plug., 'a hybrid bonding structure bonding the first die and the second die, wherein the hybrid bonding structure comprises a first bonding structure and a second bonding structure, the first bonding structure comprises2. The 3DIC structure of claim 1 , wherein a ratio of the height of the first metal feature to the height of the first via plug is 1 to 3 and a width of the first metal feature is greater than a width of the first via plug.3. The 3DIC structure of claim 1 , wherein the first bonding dielectric layer comprises:a first bonding dielectric material conformally cover the first die; anda second bonding dielectric material, disposed over the first bonding dielectric material, wherein a thickness of the second bonding dielectric material is greater than or equal to a thickness of the first bonding ...

NEW DUAL-GATE TRENCH IGBT WITH BURIED FLOATING P-TYPE SHIELD

A method of manufacturing an insulated gate bipolar transistor (IGBT) device comprising 1) preparing a semiconductor substrate with an epitaxial layer of a first conductivity type supported on the semiconductor substrate of a second conductivity type; 2) applying a gate trench mask to open a first trench and second trench followed by forming a gate insulation layer to pad the trench and filling the trench with a polysilicon layer to form the first trench gate and the second trench gate; 3) implanting dopants of the first conductivity type to form an upper heavily doped region in the epitaxial layer; and 4) forming a planar gate on top of the first trench gate and apply implanting masks to implant body dopants and source dopants to form a body region and a source region near a top surface of the semiconductor substrate. 1. An insulated gate bipolar transistor (IGBT) device comprises:a semiconductor substrate comprising an epitaxial layer of a first conductivity type supported on a bottom layer of a second conductivity type electrically contacting a collector electrode disposed on a bottom surface of the semiconductor substrate;a body region of the second conductivity type disposed near a top surface of the semiconductor substrate encompassing a source region of the first conductivity type below a top surface of the semiconductor substrate;a first trench on a first side of the source region etching into the epitaxial layer through the body region, a dielectric layer lining a bottom and side walls of the first trench insulating a lower trench electrode and an upper trench electrode disposed inside the first trench from the epitaxial layer, the upper trench electrode being separated from the lower trench electrode by an inter-segment dielectric layer;a planar insulated gate disposed above the top surface of the semiconductor substrate, the planar insulated gate extending from the first trench to overlaying a portion of the source region.2. The IGBT device of wherein:the ...

SEMICONDUCTOR MODULE, SEMICONDUCTOR MODULE PACKAGE AND SEMICONDUCTOR APPARATUS

A semiconductor module comprising a plurality of electrically conductive top plates, an electrically conductive base plate, a plurality of semiconductor chips installed on the base plate, a first power supply connected to the plates, a second power supply connected to the plates and an electrically insulating outer casing component. The semiconductor chips are individually in contact with the top plates. Each semiconductor chip comprises a first electrode electrically coupled with the base plate, and a second electrical pole electrically coupled with the corresponding top plate. The first power supply connecting plate is equipped with protruding parts that are individually in electrical contact with the top plates. The second power supply connecting plate is electrically connected to the base plate. The outer casing component is used to integrate the first power supply connecting plate and the second power supply connecting plate. The outer casing component comprises at least one opening. 1. A semiconductor module , comprising:a plurality of conductive top plates;a conductive base plate;a plurality of semiconductor chips installed on the conductive base plate and contacting the conductive top plates respectively, each of the semiconductor chips comprising a first electrode electrically coupled to the conductive base plate and a second electrode electrically coupled to the corresponding conductive top plate;a first power supply connection plate;a plurality of protrusions extending from the first power supply connection plate and electrically connecting respective conductive top plates;a second power supply connection plate electrically connecting the conductive base plate; anda housing element for holding together the first power supply connection plate and the second power supply connection plate,wherein the housing element defines at least one opening.2. The semiconductor module of claim 1 , wherein an internal space of the semiconductor module is filled with an ...

SEMICONDUCTOR MODULE

A semiconductor module includes a printed circuit board having an insulating plate, first and fourth wiring layers disposed on a principal surface of the insulating plate, second and third wiring layers disposed on another surface opposite to the principal surface, a first via disposed in the insulating plate and electrically and mechanically connected to the first and third wiring layers, and a second via disposed in the insulating plate and electrically and mechanically connected to the second and fourth wiring layers; a first insulating substrate disposed with a first circuit plate; a second insulating substrate disposed with a second circuit plate; a first semiconductor chip; a second semiconductor chip; a first heat release member fixed between the third wiring layer and the third circuit plate; and a second heat release member fixed between the fourth wiring layer and the first circuit plate. 1. A semiconductor module , comprising: an insulating plate,', 'a first wiring layer and a fourth wiring layer disposed on a principal surface of the insulating plate,', 'a second wiring layer and a third wiring layer disposed on a surface opposite to the principal surface,', 'a first via disposed in the insulating plate, and electrically and mechanically connected to the first wiring layer and third wiring layer, and', 'a second via disposed in the insulating plate, and electrically and mechanically connected to the second wiring layer and the fourth wiring layer;, 'a printed circuit board having'}a first insulating substrate disposed facing the first wiring layer, and having a first circuit plate on a surface facing the first wiring layer and the fourth wiring layer;a second insulating substrate disposed facing the second wiring layer, and having a second circuit plate facing the second wiring layer and a third circuit plate facing the third wiring layer;a first semiconductor chip sandwiched between the first wiring layer and the first circuit plate, and having a ...

SEMICONDUCTOR DEVICE

[Problem] To provide a semiconductor device with a wafer level package structure that allows for probing while reducing the area occupied by the pad electrodes. [Solution] In the present invention, the following are provided: a semiconductor chip (100) that has first and second pad electrodes (120, 120) disposed on the main surface thereof; insulating films (310, 330) that cover the main surface of the semiconductor chip (100); a rewiring layer (320) that is disposed between the insulating films (310, 330); and a plurality of external terminals (340) disposed on the top of the insulating film (330). The plane size of the first pad electrode (120) and the second pad electrode (120) differ from one another, and the first pad electrode (120) and the second pad electrode (120) are connected to any of the plurality of external terminals (340) via the rewiring layer (320). According to the present invention, because the pad electrodes (120, 120) of different sizes are intermixed, probing can be easily performed while reducing the area occupied by the pad electrodes. 1. A semiconductor device , comprising:a semiconductor chip;a plurality of first pad electrodes formed running in a first direction through a center portion of a principal surface of the semiconductor chip; anda plurality of second pad electrodes formed on the principal surface of the semiconductor chip between a pad column formed by the first pad electrodes and a side of the semiconductor chip,wherein the first pad electrodes and the second pad electrodes have a different planar size.2. The semiconductor device as claimed in claim 1 , wherein the first pad electrodes supply a first power source voltage claim 1 , and the second pad electrodes supply a second power source voltage.3. The semiconductor device as claimed in claim 2 , wherein the first pad electrodes and the second pad electrodes both supply a same power source voltage.4. The semiconductor device as claimed in claim 1 , further comprising an ...

MULTILAYER SUBSTRATE

Provided is a multilayer substrate obtained by laminating semiconductor substrates each having a trough electrode. The multilayer substrate has excellent conduction characteristics and can be manufactured at low cost. Conductive particles are each selectively present at a position where the through electrodes face each other as viewed in a plan view of the multilayer substrate. The multilayer substrate has a connection structure in which the facing through electrodes are connected by the conductive particles, and the semiconductor substrates each having the through electrode are bonded by an insulating adhesive. 1. A multilayer substrate comprising semiconductor substrates which each have a through electrode and are laminated to each other , whereinconductive particles are each selectively present at a position where the through electrodes face each other as viewed in a plan view of the multilayer substrate, andthe multilayer substrate has a connection structure in which the facing through electrodes are connected by the conductive particles, and the semiconductor substrates each having the through electrode are bonded together by an insulating adhesive.2. The multilayer substrate according to claim 1 , comprising a first semiconductor substrate having a through electrode and a second semiconductor substrate having a through electrode claim 1 , the first and second semiconductor substrates being laminated together claim 1 , the multilayer substrate having a connection structure in whichthe through electrode of the first semiconductor substrate and the through electrode of the second semiconductor substrate are connected by the conductive particle which is selectively disposed between the through electrodes.3. The multilayer substrate according to claim 2 , comprising a third semiconductor substrate having a through electrode laminated on the second semiconductor substrate claim 2 , and having a connection structure in whichthe through electrode of the second ...

pH SENSOR WITH BONDING AGENT DISPOSED IN A PATTERN

Embodiments described herein provide for a pH sensor that comprises a substrate and an ion sensitive field effect transistor (ISFET) die. The ISFET die includes an ion sensing part that is configured to be exposed to a medium such that it outputs a signal related to the pH level of the medium. The ISFET die is bonded to the substrate with at least one composition of bonding agent material disposed between the ISFET die and the substrate. One or more strips of the at least one composition of bonding agent material is disposed between the substrate and the ISFET die in a first pattern. 1. A pH sensor comprising:a substrate;an ion sensitive field effect transistor (ISFET) die including an ion sensing part that responds to pH, wherein the ISFET die is bonded to the substrate; wherein the ion sensing part of the ISFET die is configured to be exposed to a medium, and wherein the ion sensing part outputs a signal related to a pH level of the medium; andone or more strips of at least one composition of a bonding agent material disposed in a first pattern between the substrate and the ISFET die.2. The pH sensor of claim 1 , further comprising:one or more strips of a second composition of a bonding agent material disposed between the substrate and the ISFET die in a second pattern, wherein the coefficient of thermal expansion (CTE) of the second composition is different from the CTE of the at least one composition such that at different temperatures the two materials induce forces on the die in different directions.3. The pH sensor of claim 2 , wherein the second pattern further comprises one or more strips of the second composition of bonding agent material that are disposed orthogonally to the one or more strips disposed in the first pattern of the at least one composition.4. The pH sensor of claim 1 , further comprising:an inert material, wherein the inert material supports a portion of the ISFET die and does not exert a force due to CTE on the said portion of the ISFET ...

PACKAGE STRUCTURE OF FINGERPRINT IDENTIFICATION CHIP

The present invention provides a package structure of a fingerprint identification chip, including: a metal substrate, having a through opening and two grooves extending from two opposite sides of the through opening; a fingerprint identification chip, disposed in the through opening and having an upper surface and a lower surface, the lower surface having a bonding pad; a cover plate, fixedly disposed on the metal substrate and covering the upper surface of the fingerprint identification chip; a flexible printed circuit (FPC), disposed on the lower surface of the fingerprint identification chip and having a first surface and a second surface, the second surface having a first metal contact; and a metal reinforcing plate, inserted into the two grooves and covering the through opening, where the bonding pad is electrically connected to the first metal contact through a wire. 1. A package structure of a fingerprint identification chip , comprising:a metal substrate, having a through opening and two grooves extending from two opposite sides of the through opening;a fingerprint identification chip, disposed in the through opening and having an upper surface and a lower surface, the lower surface having at least one bonding pad;a cover plate, fixedly disposed on the metal substrate and covering the upper surface of the fingerprint identification chip;a flexible printed circuit (FPC), disposed on the lower surface of the fingerprint identification chip and having a first surface and a second surface, the second surface having a first metal contact; anda metal reinforcing plate, inserted into the two grooves and covering the through opening;wherein the bonding pad is electrically connected to the first metal contact through a wire.2. The package structure of a fingerprint identification chip according to claim 1 , wherein a colloid is coated on the at least one bonding pad claim 1 , the wire and the first metal contact claim 1 , and the colloid is an underfill.3. The ...

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

A method of manufacturing a semiconductor device that includes a resin package sealing a semiconductor element and a pair of metal plates interposing the semiconductor element therebetween, in which each of the pair of metal plates is exposed at corresponding one of both surfaces of the resin package is disclosed. The method may include preparing an assembly in which the semiconductor element is connected to the pair of metal plates; setting the assembly in a cavity of a mold, wherein one metal plate is in contact with a bottom surface of the cavity and a space is provided above the other metal plate; forming the resin package by injecting a molten resin into the cavity so as to cover an upper side of the other metal plate, stopping the injecting of the molten resin with a part of the space on an upper side of the cavity unfilled. 1. A method of manufacturing a semiconductor device that comprises a resin package sealing a semiconductor element and a pair of metal plates interposing the semiconductor element therebetween , each of the pair of metal plates being exposed at corresponding one of both surfaces of the resin package , the method comprising:preparing an assembly in which the semiconductor element is connected to the pair of metal plates;setting the assembly in a cavity of a mold configured to form the resin package, wherein one metal plate of the pair of metal plates is in contact with a bottom surface of the cavity and a space is provided above the other metal plate of the pair of metal plates;forming the resin package by injecting a molten resin into the cavity so as to cover an upper side of the other metal plate, stopping the injecting of the molten resin with a part of the space on an upper side of the cavity unfilled, and hardening the molten resin injected into the cavity; andremoving a resin covering the other metal plate.2. The method as in claim 1 , whereina recess is provided in an area of an upper surface of the cavity, the area facing the other ...

PACKAGED INTEGRATED CIRCUIT HAVING STACKED DIE AND METHOD FOR THEREFOR

A packaged integrated circuit (IC) device includes a first set of stacked die having a first IC die, a first inductor in the first IC die, an isolation layer over the first IC die, a second IC die over the isolation layer, and a second inductor in the second IC die aligned to communicate with the first inductor, and a second set of stacked die having a third IC die, a third inductor in the third IC die, a second isolation layer over the third IC die, a fourth IC die over the second isolation layer, and a fourth inductor in the fourth IC die aligned to communicate with the third inductor. The isolation layer extends a prespecified distance beyond a first edge of the second IC die, and the second isolation layer extends a second prespecified distance beyond a first edge of the fourth IC die. 1. A packaged integrated circuit (IC) device comprising: a first IC die,', 'a first inductor in the first IC die,', 'an isolation layer over the first IC die,', 'a second IC die over the isolation layer, and', 'a second inductor in the second IC die aligned to communicate with the first inductor, wherein the isolation layer extends a prespecified distance beyond a first edge of the second IC die; and, 'a first set of stacked dies including a third IC die,', 'a third inductor in the third IC die,', 'a second isolation layer over the third IC die,', 'a fourth IC die over the second isolation layer, and', 'a fourth inductor in the fourth IC die aligned to communicate with the third inductor, wherein the second isolation layer extends a second prespecified distance beyond a first edge of the fourth IC die;, 'a second set of stacked dies includingwherein the first IC die and the third IC die are coupled to receive high voltage signals as compared to voltage signals received by the second and fourth IC die, and wherein the packaged IC device further comprises at least one wire bond connected between the second IC die and the fourth IC die.2. The packaged IC device of claim 1 , further ...

Pre-Plating of Solder Layer on Solderable Elements for Diffusion Soldering

A pre-soldered circuit carrier includes a carrier having a metal die attach surface, a plated solder region on the metal die attach surface, wherein a maximum thickness of the plated solder region is at most 50 μm, the plated solder region has a lower melting point than the first bond pad, and the plated solder region forms one or more intermetallic phases with the die attach surface at a soldering temperature that is above the melting point of the plated solder region.

ANTENNA MODULE

An antenna module includes: an antenna substrate including an antenna pattern; a semiconductor package disposed on a lower surface of the antenna substrate, electrically connected to the antenna substrate, and having at least one semiconductor chip embedded therein; and an electronic component disposed on the lower surface or a side surface of the antenna substrate, electrically connected to the antenna substrate, and spaced apart from the semiconductor package by a predetermined distance. The electronic component has a thickness greater than that of the semiconductor chip. 1. An antenna module comprising:an antenna substrate including an antenna pattern;a semiconductor package disposed on a lower surface of the antenna substrate, electrically connected to the antenna substrate, and having at least one semiconductor chip embedded therein; andan electronic component disposed on the lower surface or a side surface of the antenna substrate, electrically connected to the antenna substrate, and spaced apart from the semiconductor package by a predetermined distance,wherein the electronic component has a thickness greater than that of the semiconductor chip.2. The antenna module of claim 1 , wherein the electronic component has a thickness greater than that of the semiconductor package.3. The antenna module of claim 1 , wherein the semiconductor package includes a radio frequency integrated circuit (RFIC) and a power management integrated circuit (PMIC) as the semiconductor chip claim 1 , andat least one passive component is further embedded in the semiconductor package.4. The antenna module of claim 1 , wherein the electronic component is a power inductor (PI).5. The antenna module of claim 1 , wherein the antenna substrate has a recess portion formed in a lower side thereof claim 1 ,the electronic component is disposed in the recess portion of the antenna substrate, andthe electronic component is connected to an inner wiring layer of the antenna substrate.6. The antenna ...

Unit power module and power module package comprising the same

Disclosed herein is a unit power module including: a first semiconductor chip having one surface on which a 1-1-th electrode and a 1-2-th electrode spaced apart from the 1-1-th electrode are formed and the other surface on which a 1-3-th electrode is formed, a second semiconductor chip having one surface on which a 2-1-th electrode is formed and the other surface on which a 2-2-th electrode is formed, a first metal plate contacting the 1-1-th electrode of the first semiconductor chip and the 2-1-th electrode of the second semiconductor chip, a second metal plate contacting the 1-2-th electrode of the first semiconductor chip and spaced apart from the first metal plate, a third metal plate contacting the 1-3-th electrode of the first semiconductor chip and the 2-2-th electrode of the second semiconductor chip, and a sealing member formed to surround the first metal plate, the second metal plate, and the third metal plate.

SOLDER JOINT STRUCTURE, POWER MODULE, POWER MODULE SUBSTRATE WITH HEAT SINK AND METHOD OF MANUFACTURING THE SAME, AND PASTE FOR FORMING SOLDER BASE LAYER

There are provided a solder joint structure, a power module using the joint structure, a power module substrate with a heat sink and a method of manufacturing the same, as well as a solder base layer forming paste which is disposed and fired on a metal member to thereby react with an oxide film generated on the surface of the metal member and form the solder base layer on the metal member, capable of suppressing the occurrence of waviness and wrinkles on the surface of the metal member even at the time of loading the power cycle and heat cycle and improving the joint reliability with a joint member. 1. A solder joint structure obtained by joining an aluminum member made of aluminum or aluminum alloy with a joint member using a solder material ,the solder joint structure comprising:a glass layer formed on a surface of the aluminum member;an Ag layer laminated on the glass layer; anda solder layer laminated on the Ag layer,wherein crystalline oxide particles are dispersed in the Ag layer.2. The solder joint structure according to claim 1 ,wherein the crystalline oxide particles are composed of any one or two or more of titanium oxide, silicon oxide, and zinc oxide.3. A power module comprising: a power module substrate in which a circuit layer made of an aluminum member is disposed on one surface of an insulating layer claim 1 , and a semiconductor device joined to one surface of the circuit layer claim 1 ,{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'wherein a junction between the circuit layer and the semiconductor device is the solder joint structure described in .'}4. A power module substrate with a heat sink claim 1 , comprising:a power module substrate in which a circuit layer is disposed on one surface of an insulating layer; anda heat sink that is joined to the other surface side of the power module substrate;wherein at least one of a joint surface of the heat sink and a joint surface of the power module substrate is composed of the aluminum member, and{' ...

Stack package

A stack package includes a substrate, a stack of semiconductor chips mounted to the substrate, a side semiconductor chip disposed on one side of the stack, and adhesive interposed between the lower surface of the side semiconductor chip and the stack of semiconductor chips and which attaches the side semiconductor chip to the stack.

ELECTRONIC COMPONENT PACKAGE

An electronic component package includes: a frame, including a through-hole and a through-wiring; an electronic component disposed in the through-hole of the frame; a metal plate disposed on a first side of the electronic component and the frame; and a redistribution layer disposed on a second side of the electronic component opposing the first side and electrically connected to the electronic component. 1. An electronic component package comprising:a frame including a through-hole and a through-wiring;an electronic component disposed in the through-hole of the frame;a metal plate disposed on a first side of the electronic component and the frame; anda redistribution layer disposed on a second side of the electronic component opposing the first side and electrically connected to the electronic component,wherein the frame includes a wiring layer formed on an upper surface thereof, and the metal plate and the wiring layer directly contact each other.2. The electronic component package of claim 1 , further comprising a first adhesive layer interposed between the metal plate and the electronic component.3. The electronic component package of claim 2 , wherein the first adhesive layer is formed of conductive epoxy.4. The electronic component package of claim 1 , wherein the metal plate and the electronic component directly contact each other.5. The electronic component package of claim 1 , wherein the metal plate is electrically disconnected from the electronic component.6. The electronic component package of claim 1 , wherein the number of through-wirings is plural claim 1 , andthe metal plate is electrically connected to some of the plurality of through-wirings, and is electrically disconnected from the others of the plurality of through-wirings.7. The electronic component package of claim 1 , further comprising a first adhesive layer interposed between the metal plate and the electronic component.8. The electronic component package of claim 7 , wherein the first ...

SEMICONDUCTOR PACKAGES AND METHODS OF PACKAGING SEMICONDUCTOR DEVICES

Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a package substrate having first and second major surfaces. The package substrate includes a base substrate having a mold material and a plurality of interconnect structures including via contacts extending through the first to the second major surface of the package substrate. A die having conductive contacts on its first or second surface is provided. The conductive contacts of the die are electrically coupled to the interconnect structures. A cap is formed over the package substrate to encapsulate the die. 1. A semiconductor package comprising:a package substrate having planar top and bottom major surfaces, wherein the package substrate is defined with a die region and a non-die region surrounding the die region, and the package substrate comprises a base substrate having a mold material and a plurality of via contacts extending from the top to the bottom major surface of the package substrate;an insulating layer having planar top and bottom surfaces, wherein the insulating layer is disposed directly over the via contacts;a plurality of conductive studs disposed in the insulating layer, wherein the conductive studs extend from the top to the bottom surface of the insulating layer, wherein the conductive studs are disposed in the die region and the non-die region of the package substrate;conductive traces and connection pads disposed directly on the top surface of the insulating layer and over the conductive studs;a die having conductive contacts, wherein the die is disposed in the die region of the package substrate and the conductive contacts of the die are electrically coupled to the conductive traces or connection pads;a cap disposed over the package substrate to encapsulate the die, wherein a side surface of conductive studs disposed at a periphery of the non-die region of the package substrate is exposed.2. The semiconductor package of ...

PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME

A package structure includes a semiconductor die and a first redistribution circuit structure. The first redistribution circuit structure is disposed on and electrically connected to the semiconductor die, and includes a first build-up layer. The first build-up layer includes a first metallization layer and a first dielectric layer laterally wrapping the first metallization layer, wherein at least a portion of the first metallization layer is protruded out of the first dielectric layer. 1. A package structure , comprising:a semiconductor die; anda first redistribution circuit structure, disposed on and electrically coupled to the semiconductor die, and comprising a first build-up layer comprising a first metallization layer and a first dielectric layer laterally wrapping the first metallization layer, wherein a first end of the first metallization layer is disposed at a location in the first dielectric layer, a second end of the first metallization layer is protruded out of the first dielectric layer, and the first end is opposite to the second end, wherein the second end is further away from the semiconductor die than the first end is, and a second lateral size of the second end is less than a first lateral size of the first end.2. The package structure of claim 1 , wherein the second end of the first metallization layer is free of the first dielectric layer.3. The package structure of claim 1 , wherein the first redistribution circuit structure further comprises a second build-up layer disposed on the first build-up layer claim 1 , and the second build-up layer comprises a second metallization layer and a second dielectric layer laterally wraps around the second metallization layer claim 1 , wherein at least a portion of the second metallization layer is protruded out of the second dielectric layer.4. The package structure of claim 3 , wherein an interface of the first dielectric layer and the second dielectric layer is located at a sidewall of the first ...

Display panel, preparation method thereof, and display device

Provided are a display panel, a preparation method thereof, and a display device. The display panel includes a plurality of sub-panels. Each sub-panel includes first substrate, second substrate, bezel adhesive located therebetween, a plurality of bank structures, and a plurality of light-emitting elements. At least one light-emitting element forms a pixel unit. Each bank structure is located between adjacent pixel units. Seaming adhesive is located between adjacent sub-panels. The sub-panels share a same first substrate, and the seaming adhesive is disposed on the same first substrate. The first substrate includes a display region and a non-display region surrounding the display region. The light-emitting elements and the bank structures are located in the display region, and the bezel adhesive is located in the non-display region. In this manner, splicing gaps between adjacent sub-panels can be effectively reduced, and thus the display effect of the display panel can be improved.

ELECTRONIC MODULE

An electronic module comprises a substrate an other-side electronic component provided on the other side of the substrate a one-side electronic component provided on one side of the substrate and a connecting terminal having an other-side extending part extending to circumferential outside of the substrate on the other side of the substrate a one-side extending part extending to circumferential outside of the substrate on one side of the substrate and a connecting part connecting the other-side extending part with the one-side extending part at the circumferential outside of the substrate 2. The electronic module according to claim 1 , whereinthe substrate has a first substrate and a second substrate which is provided on one side of the first substrate,the other-side electronic component has an other-side second electronic component provided on the other side of the second substrate,the one-side electronic component has a one-side second electronic component provided on one side of the second substrate, andthe connecting terminal has a second connecting terminal, which has an other-side second extending part extending to circumferential outside of the second substrate on the other side of the second substrate, a one-side second extending part extending to circumferential outside of the second substrate on one side of the second substrate, and a second connecting part connecting the other-side second extending part with the one-side second extending part at circumferential outside of the second substrate, and the second connecting terminal electrically connects the other-side second electronic component with the one-side second electronic component.3. The electronic module claim 2 , according to claim 2 , further comprisinga first electronic component provided on one side of the first substrate; anda first terminal part, which is provided on a first substrate side, electrically connected with the first electronic component,wherein the first terminal part has a first ...

SEMICONDUCTOR DEVICE

A semiconductor device that is capable of suitably dissipating heat from a semiconductor chip is proposed. The proposed semiconductor device may include a semiconductor chip provided with a semiconductor substrate and a surface electrode provided on a surface of the semiconductor substrate; and a conductive plate provided with a plate shape portion and a convex portion protruding from the plate shape portion. An end surface of the convex portion may be corrected to the surface electrode. A width of the end surface of the convex portion may be narrower than a width of a base portion of the convex portion on a plate shape portion side. 1. A semiconductor device , comprising:a semiconductor chip comprising a semiconductor substrate and a surface electrode provided on a surface of the semiconductor substrate; anda conductive plate comprising a plate shape portion and a convex portion protruding from the plate shape portion, an end surface of the convex portion being connected to the surface electrode,whereina width of the end surface of the convex portion is narrower than a width of a base portion of the convex portion on a plate shape portion side.2. The semiconductor device of claim 1 , wherein a width of the convex portion narrows in stairs shape from the base portion to the end surface.3. The semiconductor device of claim 1 , wherein a width of the convex portion continuously narrows from the base portion to the end surface.4. The semiconductor device of claim 1 , wherein a groove extending along a periphery of the end surface is provided in a surface of the convex portion or a surface of the plate shape portion adjacent to the convex portion.5. The semiconductor device of claim 4 , wherein the groove is provided in the end surface of the convex portion.6. The semiconductor device of whereinthe semiconductor chip comprises a signal electrode provided on the surface of the semiconductor substrate, andthe semiconductor device further comprises a signal terminal ...

FAN-OUT SEMICONDUCTOR PACKAGE

A fan-out semiconductor package includes: a frame including first to third insulating layers, a first wiring layer disposed on a first surface of the first insulating layer and embedded in the second insulating layer, and a second wiring layer disposed on the third insulating layer, and having a through-hole penetrating through the first to third insulating layers; a semiconductor chip disposed in the through-hole and having an active surface on which connection pads are disposed and an inactive surface opposing the active surface; an encapsulant covering at least portions of each of the frame and the semiconductor chip and filling at least portions of the through-hole; and a connection structure disposed on the frame and the active surface of the semiconductor chip and including redistribution layers electrically connected to the connection pads. The first and second wiring layers are electrically connected to the connection pads. 1. A fan-out semiconductor package comprising:a frame including a first insulating layer, a second insulating layer disposed on a first surface of the first insulating layer, a third insulating layer disposed on a second surface of the first insulating layer opposing the first surface, a first wiring layer disposed on the first surface of the first insulating layer and embedded in the second insulating layer, and a second wiring layer disposed on the third insulating layer, and having a through-hole penetrating through the first to third insulating layers;a semiconductor chip disposed in the through-hole and having an active surface on which connection pads are disposed and an inactive surface opposing the active surface;an encapsulant covering at least portions of each of the frame and the semiconductor chip and filling at least portions of the through-hole; anda connection structure disposed on the frame and the active surface of the semiconductor chip and including redistribution layers electrically connected to the connection pads, ...

Step-type stacked chip packaging structure based on resin spacer and preparation process

A step-type stacked chip packaging structure based on a resin spacer that includes: a plastic packaging material, a circuit board, a resin spacer, a first chip, a second chip and an electrical connection assembly. The resin spacer, the first chip, and the second chip are stacked on the circuit board respectively. The second chip is stacked on the first chip in a stepped manner. The circuit board, the first chip and the second chip are electrically connected together through the electrical connection assembly. The resin spacer uses a fiber glass fabric as its base material, a weight percent of the fiber glass fabric is 10-60 wt %, and the following components are attached to the fiber glass fabric as a percentage by the total weight of the resin spacer: 8-40 wt % of epoxy resin, 10-30 wt % of quartz powder, 2-10 wt % of aluminum oxide, 1-8 wt % of calcium oxide, and 1-8 wt % of curing agent.

Board Assembly with Chemical Vapor Deposition Diamond (CVDD) Windows for Thermal Transport

A method and apparatus for conducting heat away from a semiconductor die are disclosed. A board assembly is disclosed that includes a first circuit board having an opening extending through the first circuit board. A Chemical Vapor Deposition Diamond (CVDD) window extends within the opening. A layer of thermally conductive paste extends over the CVDD window. A semiconductor die extends over the layer of thermally conductive paste such that a hot-spot on the semiconductor die overlies the CVDD window. 1. A board assembly comprising:a circuit board;a semiconductor die electrically coupled to the circuit board;a Chemical Vapor Deposition Diamond (CVDD) window; anda layer of thermally conductive paste in direct contact with a first surface of the CVDD window along the full extent of the first surface of the CVDD window, and in direct contact with the semiconductor die, the layer of thermally conductive paste positioned so that it covers a hot-spot on the semiconductor die, the CVDD window having a footprint that is less than twenty percent of the footprint of the semiconductor die.2. The board assembly of further comprising an opening extending through the circuit board claim 1 , the CVDD window extending within the opening.3. The board assembly of further comprising leads that extend from the semiconductor die to the circuit board for electrically coupling the semiconductor die to the circuit board.4. The board assembly of further comprising a dam extending around the die claim 3 , and filler material that extends within the dam.5. The board assembly of further comprising an additional circuit board and a dam extending around the die claim 3 , the additional circuit board attached to the dam so as to couple the circuit board to the additional circuit board and form an enclosure within the dam and between the circuit board and the additional circuit board claim 3 , the semiconductor die and the leads extending within the enclosure.6. The board assembly of further ...

Semiconductor package

A semiconductor package includes a substrate, a semiconductor die, a dummy die, a conductive layer, at least one first conductive wire, and at least one second conductive wire. The semiconductor die is disposed on the substrate. The dummy die is disposed on the semiconductor die. The conductive layer is disposed on the dummy die. The first conductive wire electrically connects the semiconductor die to a signal source. The second conductive wire electrically connects the conductive layer to a ground reference.

METHOD AND DEVICE FOR COMPRESSION BONDING CHIP TO SUBSTRATE

Method and device for compression bonding are disclosed. During compression bonding a chip to a substrate, an anti-adhesion layer on a stage is provided to contact with a solder resist layer on the substrate. The solder resist layer will not stick to the anti-adhesion layer such that the reduction of bonding precision due to the solder resist layer remains residues on the compression bonding device is preventable. 1. A compression bonding device , comprising:a stage; andan anti-adhesion layer formed on the stage, the anti-adhesion layer is provided to support a substrate and contact with a solder resist layer of the substrate during a compression bonding process for bonding a chip to the substrate.2. The compression bonding device in accordance with claim 1 , wherein the anti-adhesion layer is made of polytetrafluoroethylene (PTFE).3. The compression bonding device in accordance with claim 1 , wherein there are a plurality of first channels on the anti-adhesion layer claim 1 , and a plurality of openings of the first channels are located on a supporting surface of the anti-adhesion layer claim 1 , the supporting surface is directed toward the first solder resist layer claim 1 , wherein the substrate is sucked via the openings to be held on the anti-adhesion layer temporarily such that the first solder resist layer contacts with the anti-adhesion layer.4. The compression bonding device in accordance with claim 3 , wherein the first channels include a plurality of grooves claim 3 , and the openings of the first channels are openings of the grooves.5. The compression bonding device in accordance with claim 4 , wherein the anti-adhesion layer is not pierced by the grooves whose ends are closed claim 4 , and the first channels include a plurality of via holes communicating with the grooves.6. The compression bonding device in accordance with claim 4 , wherein the anti-adhesion layer is pierced by the grooves.7. The compression bonding device in accordance with claim 4 , ...

MICROELECTRONIC PACKAGES WITH HIGH INTEGRATION MICROELECTRONIC DICE STACK

A microelectronic package may include stacked microelectronic dice, wherein a first microelectronic die is attached to a microelectronic substrate, and a second microelectronic die is stacked over at least a portion of the first microelectronic die, wherein the microelectronic substrate includes a plurality of pillars extending therefrom, wherein the second microelectronic die includes a plurality of pillars extending therefrom in a mirror-image configuration to the plurality of microelectronic substrate pillars, and wherein the second microelectronic die pillars are attached to microelectronic substrate pillars with an attachment material. 1. A device , comprising:a substrate having a plurality of pillars extending from a surface and a plurality of bond pads on the surface;a first die including a plurality of pillars extending from a surface of the first die; anda second die extending over at least a portion of the first die, the second die including a plurality of pillars extending from a surface of the second die;wherein one of the plurality of pillars of the first die is coupled with one of the plurality of bond pads on the substrate by a solder material; andwherein one of the plurality of pillars of the second die is coupled with one of the plurality of pillars of the substrate by an attachment material.2. The device of claim 1 , wherein the attachment material comprises a solder material.3. The device of claim 1 , further comprising:a mold material on a back surface of the second die.4. The device of claim 3 , wherein the mold material encapsulates the first die claim 3 , the second die claim 3 , the plurality of substrate pillars claim 3 , the plurality of second die pillars claim 3 , and the attachment material.5. The device of claim 1 , further including an adhesive material between a back surface of the first die and the surface of the second die.6. The device of claim 1 , wherein the substrate further includes an external connection surface opposing the ...

METHOD FOR PRODUCING A LIGHT EMITTING DEVICE

A method for producing a light emitting device includes a first bonding step including disposing a first bonding member a mounting substrate, placing a light emitting element on the mounting substrate such that the first bonding member is located between a mounting face of the light emitting element and the mounting substrate, and hardening the first bonding member thereby bonding the light emitting element and the mounting substrate such that, in a plan view, an entirety of the first bonding member is contained within an area of the mounting face of the light emitting element; and a second bonding step including disposing a second bonding member on the upper face of the mounting substrate such that, in a plan view, the second bonding member is located at at least a portion of an outer edge of the mounting face of the light emitting element, and hardening the second bonding member. 1. A method for producing a light emitting device , the method comprising: disposing a first bonding member in a liquid or paste form on an upper face of a mounting substrate,', 'placing a light emitting element on the mounting substrate such that the first bonding member is located between a mounting face of the light emitting element and the upper face of the mounting substrate, wherein the light emitting element includes an electrode at an upper face of the light emitting element, and', 'hardening the first bonding member thereby bonding the light emitting element to the mounting substrate such that, in a plan view, an entirety of the first bonding member is contained within an area of the mounting face of the light emitting element; and, 'a first bonding step comprising disposing a second bonding member in a liquid or paste form on the upper face of the mounting substrate such that, in a plan view, the second bonding member extends around a periphery of the first bonding member, and', 'hardening the second bonding member., 'a second bonding step comprising2. The method according to ...

MICRO DEVICE ARRANGEMENT IN DONOR SUBSTRATE

This disclosure is related to arranging micro devices in the donor substrate by either patterning or population so that there is no interfering with unwanted pads and the non-interfering area in the donor substrate is maximized. This enables to transfer the devices to receiver substrate with fewer steps. 1. A method of arranging micro devices in the donor substrate , used to transfer micro devices to the receiver substrate , where micro devices are arranged in relation to the pixel area and the micro devices inside the area associated with the pixel has a pitch that is smaller than the pixel pitch.2. The arrangement method of claim 1 , wherein the pitch between the micro devices at the boundary of two pixels are different from the pitch of micro devices within the pixel. The present application is a division of U.S. patent application Ser. No. 16/684,820, filed on Nov. 15, 2019, now allowed, which is a division of U.S. patent application Ser. No. 15/696,700, filed on Sep. 6, 2017, now U.S. Pat. No. 10,535,546, issued on Jan 14, 2020, which claims the benefit of and priority to U.S. Provisional Patent Application No. 62/403,741, filed on Oct. 4, 2016, and Canadian Patent Application No. 2,941,038, filed on Sep. 6, 2016, each of which is hereby incorporated by reference herein in its entirety.The present disclosure relates to the integration of a transferred micro device system on a receiver substrate. More specifically, the present disclosure relates to patterning micro devices on a donor substrate and the landing area on a receiver substrate to increase the efficiency of the transfer process.A few embodiments of this description relate to patterning micro devices on the donor substrate to facilitate a selective transfer process. The micro device array may comprise micro light emitting diodes (LEDs), organic LEDs, sensors, solid state devices, integrated circuits, MEMS (microelectromechanical systems), and/or other electronic components. Other embodiments are related ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device according to the present embodiment includes a circuit board comprising a plurality of electrodes provided on a first surface, a first resin layer provided on the first surface around the electrodes, and a second resin layer provided on the first resin layer. A first semiconductor chip is connected to a first one of the electrodes. A second semiconductor chip is provided above the first semiconductor chip, being larger than the first semiconductor chip, and is connected to a second one of the electrodes via a metal wire. A third resin layer is provided between the first semiconductor chip and the second semiconductor chip and between the second resin layer and the second semiconductor chip, and covers the first semiconductor chip. 1. A semiconductor device comprising:a circuit board comprising a plurality of electrodes provided on a first surface, a first resin layer provided on the first surface around the electrodes, and a second resin layer provided on the first resin layer;a first semiconductor chip connected to a first one of the electrodes;a second semiconductor chip provided above the first semiconductor chip, being larger than the first semiconductor chip, and connected to a second one of the electrodes via a metal wire; anda third resin layer provided between the first semiconductor chip and the second semiconductor chip and between the second resin layer and the second semiconductor chip, and covering the first semiconductor chip.2. The device of claim 1 , wherein the second resin layer surrounds the first semiconductor chip as viewed from above the first surface.3. The device of claim 1 , wherein an outer edge of the second resin layer is located between the first semiconductor chip and the second electrode as viewed from above the first surface.4. The device of claim 1 , wherein an outer edge of the second resin layer is located outside an outer edge of the second semiconductor chip and overlaps the first resin layer as viewed from ...

Semiconductor device

A semiconductor device includes a first lead portion and a second lead portion spaced from each other in a first direction. A semiconductor chip is mounted to the first lead portion. A first connector has a first portion contacting a second electrode on the chip and a second portion connected to the second lead portion. A second connector has third portion that contacts the second electrode, but at a position further away than the first portion, and a fourth portion connected to the second portion. At least a part of the second connector overlaps a part of the first connector between the first lead portion and the second lead portion.

ANTENNA MODULE

An antenna module includes an antenna substrate including an antenna pattern; a semiconductor package disposed on a lower surface of the antenna substrate, electrically connected to the antenna substrate, and having a semiconductor chip embedded therein; and an electronic component disposed at a side of the antenna substrate, electrically connected to the antenna substrate, and spaced apart from the semiconductor package by a predetermined distance. The antenna module includes a connection substrate connected to a portion of the antenna substrate, the connection substrate having an extension portion extending outward from the side of the antenna substrate, and the electronic component is disposed on the extension portion of the connection substrate to electrically connect to an inner wiring layer of the antenna substrate. 1. An antenna module comprising:an antenna substrate including an antenna pattern;a semiconductor package disposed on a lower surface of the antenna substrate, electrically connected to the antenna substrate, and having at least one semiconductor chip embedded therein; andan electronic component disposed at a side of the antenna substrate, electrically connected to the antenna substrate, and spaced apart from the semiconductor package by a predetermined distance,wherein the antenna module further comprises a connection substrate connected to a portion of the antenna substrate, the connection substrate having an extension portion extending outward from the side of the antenna substrate, andthe electronic component is disposed on the extension portion of the connection substrate to electrically connect to an inner wiring layer of the antenna substrate,wherein the semiconductor package includes a frame having a first through-hole, a first semiconductor chip of the at least one semiconductor chip disposed in the first through-hole and having a first active surface having first connection pads disposed thereon, an encapsulant covering the first ...

Memory module

According to one embodiment, a memory module includes a substrate, a semiconductor memory device, a plate-form conductive member, wire, and a mold member. The substrate includes a ground terminal to which a ground potential is applied. The semiconductor memory device is provided on the substrate. The plate-form conductive member is provided on the semiconductor memory device. The wire that electrically connects the ground terminal to the plate-form conductive member. The mold member seals the semiconductor memory device on the substrate, the plate-form conductive member and the wire.

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

In one embodiment, a semiconductor package includes a circuit substrate, a plurality of semiconductor chips stacked on the circuit substrate, insulating adhesive patterns interposed between the semiconductor chips, a heat slug provided on an uppermost semiconductor chip and adhered to the uppermost semiconductor chip by a heat dissipative adhesive pattern, and a mold structure provided on the circuit substrate to cover sidewalls of the semiconductor chips, the insulating adhesive patterns, the heat dissipative adhesive pattern and the heat slug. A failure of the semiconductor package during a manufacturing process of the mold structure may be reduced. The semiconductor package may therefore have good operating characteristics and reliability. 1. A semiconductor package , comprising:a circuit substrate;a plurality of semiconductor chips stacked on the circuit substrate;insulating adhesive patterns interposed between the semiconductor chips;a heat slug provided on an uppermost semiconductor chip and adhered to the uppermost semiconductor chip through a heat dissipative adhesive pattern; anda mold structure provided on the circuit substrate to cover sidewalls of the semiconductor chips, the insulating adhesive patterns, the heat dissipative adhesive pattern and the heat slug.2. The semiconductor package of claim 1 , wherein at least one of the semiconductor chips includes a through-silicon via (TSV).3. The semiconductor package of claim 1 , wherein the heat slug covers the uppermost semiconductor chip claim 1 , and wherein a top surface area of the heat slug is greater than a top surface area of the uppermost semiconductor chip.4. A method of manufacturing a semiconductor package claim 1 , the method comprising:stacking semiconductor chips on a circuit substrate by using insulating adhesive patterns to form a plurality of preliminarily stacked chips, each preliminarily stacked chip including the semiconductor chips having the insulating adhesive patterns interposed ...

CHIP-ON-WAFER BONDING METHOD AND BONDING DEVICE, AND STRUCTURE COMPRISING CHIP AND WAFER

[Problem] Provided is a technique for bonding chips efficiently onto a wafer to establish an electrical connection and raise mechanical strength between the chips and the wafer or between the chips that are chips laminated onto each other in the state that resin and other undesired residues do not remain on a bond interface therebetween. 1. A method for bonding plural chips each having a chip-side-bond-surface having one or more metal regions to a substrate having plural bond portions ,the method comprising:causing particles having a predetermined kinetic energy to collide with at least the metal region(s) of the chip-side-bond-surface to subject the metal region(s) to surface activating treatment, and further causing water to adhere onto the metal region(s) to subject the metal region(s) to hydrophilizing treatment,causing particles having a predetermined kinetic energy to collide with the bond portions of the substrate to subject the bond portions to surface activating treatment, and further causing water to adhere onto the bond portions to subject the bond portions to hydrophilizing treatment,fitting each of the chips subjected to the surface activating treatment and the hydrophilizing treatment onto the corresponding bond portion of the substrate subjected to the surface activating treatment and the hydrophilizing treatment to bring the metal region(s) of the chip into contact with the bond portion of the substrate, to obtain a resultant structure comprising the substrate and the chips fitted onto the substrate, andheating the resultant structure.2. The method according to claim 1 , wherein the fitting of each of the chips onto the corresponding bond portion of the substrate is performed by heating the metal region(s) of the chip and the bond portion of the substrate over a period of 0.1 to 10 seconds to have a temperature of 100 to 350° C. when the metal region(s) of the chip contact(s) the bond portion of the substrate.3. The method according to claim 1 , ...

Semiconductor chip and method of processing a semiconductor chip

Various embodiments provide a semiconductor chip, wherein the semiconductor chip comprises a first contact area and a second contact area both formed at a frontside of the semiconductor chip; a passivation layer arranged at the frontside between the first contact area and the second contact area; and a contact stack formed over the frontside of the semiconductor chip and comprising a plurality of layers, wherein at least one layer of the plurality of layers is removed from the passivation layer and boundary regions of the contact areas being adjacent to the passivation layer and wherein at least one another layer of the plurality of different layer is present in the boundary region of the contact areas adjoining the passivation layer. 1. A semiconductor chip comprising:a contact area formed at a frontside of the semiconductor chip, wherein a passivation layer is arranged at the frontside adjoining the contact area in a boundary region of the contact area;a multilayer metallization stack comprising an adhesion promoter layer, a contact layer and a planar protection layer, wherein the contact layer is arranged between the adhesion promoter layer and the protection layer,wherein only the adhesion promoter layer of the multilayer metallization stack is formed above at least portions of the contact area, the boundary region and portions of the passivation layer and the contact layer and the planar protection layer are formed only above portions of the contact area.2. The semiconductor chip according to claim 1 , wherein the multilayer metallization stack extends over at least portions of the contact area while at the boundary region only the adhesion promoter layer remains claim 1 , so that sidewalls of the contact layer and the planar protection layer are exposed to the boundary region and the adhesion layer extends laterally over the contact area and the passivation layer claim 1 , wherein the passivation layer is partially free of the adhesion layer.3. The ...

THERMAL MANAGEMENT SOLUTIONS FOR STACKED INTEGRATED CIRCUIT DEVICES

An integrated circuit structure may be formed having a substrate, a first integrated circuit device electrically attached to the substrate, a second integrated circuit device electrically attached to the first integrated circuit device, at least one first level channel between the substrate and the first integrated circuit device and/or at least one second level channel between the first integrated circuit device and the second integrated circuit device, and a heat dissipation device attached to the substrate which defines a fluid chamber, wherein the at least one of the first level channel and/or the at least one second level channel is opened to the fluid chamber, such that when a heat transfer fluid is introduced into the fluid chamber, the heat transfer fluid may make direct contact with the first integrated circuit device and/or the second integrated circuit device. 1. An integrated circuit assembly , comprising:a substrate;a first integrated circuit device electrically attached to the substrate;a second integrated circuit device electrically attached to the first integrated circuit device;at least one first level channel between the substrate and the first integrated circuit device and/or at least one second level channel between the first integrated circuit device and the second integrated circuit device; anda heat dissipation device attached to the substrate which defines a fluid chamber, wherein the at least one first level channel and/or the at least one second level channel is open to the fluid chamber.2. The integrated circuit assembly of claim 1 , wherein the at least one first level channel is formed in a first underfill material disposed between the substrate and the first integrated circuit device.3. The integrated circuit assembly of claim 2 , wherein the first underfill material surrounds at least one interconnect claim 2 , wherein the at least one interconnect electrically connects the first integrated circuit device and the substrate.4. The ...

BRIDGE INTERCONNECTION WITH LAYERED INTERCONNECT STRUCTURES

Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed. 1. An IC assembly , comprising:a package substrate having a cavity;a bridge embedded in the cavity of the package substrate, the bridge comprising silicon;a dielectric material over the bridge;a first joint over and electrically coupled to the bridge, the first joint in the dielectric material and extending above the dielectric material, and the first joint comprising copper;a first layer on the first joint, the first layer comprising nickel;a second joint over and electrically coupled to the bridge, the second joint in the dielectric material and extending above the dielectric material, and the second joint comprising copper;a second layer on the second joint, the second layer comprising nickel;a first interconnect structure in the package substrate, the first interconnect structure laterally spaced from a first side of the bridge;a second interconnect structure in the package substrate, the second interconnect structure laterally spaced from a second side of the bridge;a first die electrically coupled to the first joint and the first interconnect structure; anda second die electrically coupled to the second joint and the ...

PACKAGE STRUCTURES AND METHODS FOR FABRICATING THE SAME

A package structure includes a metal carrier, a conductive adhesive layer disposed on the metal carrier, a conductive post disposed on the conductive adhesive layer, a semiconductor chip disposed on the conductive adhesive layer and laterally spaced from the conductive post, and a redistribution layer disposed on the conductive post and the semiconductor chip. The semiconductor chip includes a first terminal at an upper surface of the semiconductor chip. The first terminal of the semiconductor chip is electrically connected to the bottom surface of the semiconductor chip through the redistribution layer, the conductive post and the conductive adhesive layer. 1. A package structure , comprising:a metal carrier;a conductive adhesive layer disposed on the metal carrier;a conductive post disposed on the conductive adhesive layer;a semiconductor chip disposed on the conductive adhesive layer and laterally spaced from the conductive post, wherein the semiconductor chip comprises a source terminal, a drain terminal, and a gate terminal at an upper surface of the semiconductor chip; anda redistribution layer disposed on the conductive post and the semiconductor chip, wherein the source terminal of the semiconductor chip is electrically connected to a bottom surface of the semiconductor chip through the redistribution layer, the conductive post and the conductive adhesive layer.2. (canceled)3. (canceled)4. The package structure as claimed in claim 1 , wherein the redistribution layer includes a first trace claim 1 , a second trace and a third trace which are electrically isolated from each other claim 1 , wherein the first trace claim 1 , the second trace and the third trace are electrically connected to the source terminal claim 1 , the drain terminal and the gate terminal respectively.5. The package structure as claimed in claim 4 , wherein when viewed from a top view claim 4 , a projected area of the conductive post is entirely located within a projected area of the first ...

Semiconductor device, method for manufacturing the same, and power conversion device

In a method for manufacturing a semiconductor device, a plurality of first provisional fixing portions are supplied on a front surface of a substrate such that the plurality of first provisional fixing portions are spaced from each other and thus dispersed. A first solder layer processed into a plate to be a first soldering portion is disposed in contact with the plurality of first provisional fixing portions. A semiconductor chip is disposed on the first solder layer. In addition a conductive member in the form of a flat plate is disposed thereon via a second provisional fixing portion and a second solder layer. A reflow process is performed to solder the substrate, the semiconductor chip and the conductive member together.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor device includes a substrate, first and second semiconductor chips, an adhesion layer, and a resin layer. The first and second semiconductor chips are provided on a surface of the substrate. The second semiconductor chip includes, on a side thereof facing the substrate, a first region and a second region that is recessed from the first region and is above at least part of the first semiconductor chip or at least part of a wire that electrically connects the first semiconductor chip and the substrate. The adhesion layer is provided at least between the first region of the second semiconductor chip and the substrate. The resin layer is on the surface of the substrate and enclosing the first and second semiconductor chips. 1. A semiconductor device comprising:a substrate;a first semiconductor chip provided on a surface of the substrate;a second semiconductor chip provided on the surface of the substrate, the second semiconductor chip including, on a side thereof facing the substrate, a first region and a second region that is recessed from the first region and is above at least part of the first semiconductor chip or at least part of a wire that electrically connects the first semiconductor chip and the substrate;an adhesion layer provided at least between the first region of the second semiconductor chip and the substrate; anda resin layer on the surface of the substrate and enclosing the first and second semiconductor chips.2. The semiconductor device according to claim 1 , wherein the adhesion layer is in contact with at least part of the wire.3. The semiconductor device according to claim 1 , wherein the adhesion layer is provided also between at least part of the second region of the second semiconductor chip and the substrate.4. The semiconductor device according to claim 1 , whereinthe second region of the second semiconductor chip is above at least part of the first semiconductor chip, andthe adhesion layer is provided also between the second ...