Bonddraht für Halbleitervorrichtung

Bonddraht für eine Halbleitervorrichtung, wobei der Bonddraht aufweist:ein Cu-Legierungskernmaterial; undeine auf einer Oberfläche des Cu-Legierungskernmaterials gebildete Pd-Überzugschicht, wobeibei Messung von Kristallorientierungen auf einem Querschnitt des Kernmaterials in senkrechter Richtung zu einer Drahtachse des Bonddrahts eine Kristallorientierung <100> im Winkel von höchstens 15 Grad zu einer Drahtachsenrichtung einen Anteil von mindestens 30 % unter Kristallorientierungen in Drahtachsenrichtung hat,eine mittlere Kristallkorngröße im Querschnitt des Kernmaterials in senkrechter Richtung zur Drahtachse des Bonddrahts 0,9 µm oder mehr und 1,5 µm oder weniger beträgt, undder Bonddraht ein oder mehrere Elemente enthält, die aus Ga und Ge ausgewählt sind, und eine Konzentration der Elemente insgesamt 0,011 bis 1,5 Masse-% relativ zum gesamten Draht beträgt.

A method of manufacturing a shielding

Ein Verfahren zum Herstellen einer Schirmung eines auf einer Leiterplatte (1) angeordneten Bauteils (2) mit induktiver Komponente, bei welchem zumindest ein Schirmdraht (7) zunächst mit einem Ende auf ein erstes Bondpad (5) an der Leiterplatte aufgebondet wird, der Schirmdraht das Bauteil umfangend zu einem zweiten Bondpad (6) geführt wird und sodann auf dieses aufgebondet wird. sowie eine entsprechend aufgebaute Leiterplatte.

접착시트 및 반도체 장치의 제조 방법

... 본 발명의 접착시트는, (A)고분자량 성분과, (B1)연화점이 50℃ 미만인 열경화성 성분과, (B2)연화점이 50℃ 이상 100℃ 이하인 열경화성 성분과, (C)연화점이 100℃ 이하인 페놀 수지를 포함하는 수지 조성물로 이루어지고, 그 수지 조성물 100질량%를 기준으로 하여, 상기 (A)고분자량 성분을 11∼22질량%, 상기 (B1)연화점이 50℃ 미만인 열경화성 성분을 10∼20질량%, 상기 (B2)연화점이 50℃ 이상 100℃ 이하인 열경화성 성분을 10∼20질량%, 상기 (C)연화점이 100℃ 이하인 페놀 수지를 15∼30질량% 함유한다.

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

The present invention relates to a semiconductor package with excellent electromagnetic wave shielding performance, interfacial adhesive force and bending properties, and a manufacturing method thereof. The semiconductor package comprises: a lead frame substrate; at least one semiconductor chip mounted on the lead frame substrate; a first sealing layer for sealing the semiconductor chip; and a second sealing layer formed on the first sealing layer and formed by an epoxy resin composition containing an electromagnetic wave shielding material. COPYRIGHT KIPO 2017 ...

SEMICONDUCTOR PACKAGE

A semiconductor package is provided. The semiconductor package includes memory chips mounted on the upper side of a package substrate and controller chips which are arranged on at least one of the upper side and the rear side of the package substrate and are vertically stacked. Accordingly, the present invention can provide the semiconductor package suitable for high integration and high speed. COPYRIGHT KIPO 2017 ...

반도체 장치용 구리 합금 본딩 와이어

... 반도체 장치용의 구리 합금 본딩 와이어에 있어서, 고온 고습 환경 하에서의 볼부 접합 수명의 향상을 실현한다. Ni, Zn, Ga, Ge, Rh, In, Ir, Pt에서 선택되는 적어도 1종 이상의 원소(제1 원소)를 총계로 0.03질량％ 이상 3질량％ 이하 함유하고, 잔부가 Cu와 불가피 불순물을 포함하는 것을 특징으로 하는 반도체 장치용 구리 합금 본딩 와이어이다. 제1 원소를 소정량 함유함으로써, 와이어 접합 계면에 있어서 고온 고습 환경 하에서 부식되기 쉬운 금속간 화합물의 생성을 억제하여, 볼부 접합 수명의 향상이 이루어진다.

Bonding wire for semiconductor device

A bonding wire for a semiconductor device includes a Cu alloy core material and a Pd coating layer formed on a surface thereof. Containing an element that provides bonding reliability in a high-temperature environment improves the bonding reliability of the ball bonded part in high temperature. Furthermore, making an orientation proportion of a crystal orientation <100> angled at 15 degrees or less to a wire longitudinal direction among crystal orientations in the wire longitudinal direction 30% or more when measuring crystal orientations on a cross-section of the core material in a direction perpendicular to a wire axis of the bonding wire, and making an average crystal grain size in the cross-section of the core material in the direction perpendicular to the wire axis of the bonding wire 0.9 to 1.5 [mu]m provides a strength ratio of 1.6 or less.

BONDING WIRE FOR SEMICONDUCTOR DEVICE

圧力センサ装置および圧力センサ装置の製造方法

RF SEMICONDUCTOR FOR COMMUNICATION

The present invention relates to an amplified semiconductor for communication, including: a substrate for the amplified semiconductor for communication; an active element and a passive element mounted on the substrate for the amplified semiconductor for communication to be connected to each other through a wire bonding; an insulator integrally laminated on the substrate for the amplified semiconductor for communication and having a shape of enclosing a mount space mounted thereon with the active element and the passive element; a lead frame member integrally bonded on the insulator to be connected to the active element or the passive element through the wire bonding; and a cover lead member bonded on the insulator by an adhesive to tightly seal the mount space. A position guide protrusion for designating a coupling position of the cover lead member protrudes on one of an upper surface of the insulator and a lower surface of the cover lead member, and a position guide groove inserted therein ...

BONDING WIRE FOR SEMICONDUCTOR DEVICE

A method of manufacturing a shielding

Ein Verfahren zum Herstellen einer Schirmung eines auf einer Leiterplatte (1) angeordneten Bauteils (2) mit induktiver Komponente, bei welchem zumindest ein Schirmdraht (7) zunächst mit einem Ende auf ein erstes Bondpad (5) an der Leiterplatte aufgebondet wird, der Schirmdraht das Bauteil umfangend zu einem zweiten Bondpad (6) geführt wird und sodann auf dieses aufgebondet wird. sowie eine entsprechend aufgebaute Leiterplatte.

Pressure sensor device and the pressure sensor device manufacturing method

... 在形成于树脂壳体(1)的凹状的传感器安装部(2)内收纳传感器单元(10)。传感器单元(10)是将半导体压力传感器芯片(11)与玻璃底座(12)的侧接合而成，通过粘接剂(13)将玻璃底座(12)的另侧贴片到传感器安装部(2)的底部。半导体压力传感器芯片(11)上的电极焊盘经由键合线(4)与贯通树脂壳体(1)而体地嵌件成型的外部导出用的引线端子(3)电连接。利用由含氟的聚对二甲苯系聚合物构成的保护膜(5)覆盖传感器单元(10)、引线端子(3)的露出于树脂壳体(1)内部的部分、键合线(4)、树脂壳体(1)的内壁(1a)的露出部分(也包括传感器安装部(2)的内壁)的整个表面。由此，能够提高压力传感器装置的可靠性。 ...

APPARATUS AND METHOD FOR GENERATING WIRING DATA, AND IMAGING SYSTEM

An apparatus for generating wiring data generates wiring data while preventing a short circuit of a wiring line and restraining processing time. The apparatus for generating wiring data includes a reference wiring data acquiring unit that acquires reference wiring data representing a reference wiring pattern, an area information acquiring unit that acquires area information defining a reference chip area and a rewiring area, a netlist generating unit that generates a netlist for a target wiring pattern surrounded by the rewiring area, and an error acquiring unit that acquires an arrangement error of a semiconductor chip, and further includes a first wiring data generating unit that generates fan out wiring data representing fan out wiring of the semiconductor chip, and a second wiring data generating unit that generates wiring data representing a new wiring pattern by rewiring the target wiring pattern according to the arrangement error so that the target wiring pattern may be connected ...

패키지 온 패키지 제품을 위한 와이어 리드를 갖는 집적 패키지 설계

... 패키지 온 패키지 제품용 집적 패키지 설계가 와이어 리드를 사용하여 기술된다. 일부 실시예는 전면 및 이면을 갖는 제 1 다이, 제 1 다이의 이면에 부착된 다이 패들, 일단이 외부 디바이스에 대한 접속을 위해 다이의 전면에 접속되는 복수의 와이어 리드, 제 1 다이 및 다이 패들의 적어도 일부를 캡슐화하는 몰드 화합물, 다이 패들로부터 절단되고 몰드 화합물에 의해 지지된 랜드 패드, 와이어 리드의 일단이 제 1 다이의 전면에 접속되고 와이어 리드의 타단이 랜드 패드에 접속되는 제 2 복수의 와이어 리드, 다이 패들 위에 적층된 제 2 다이, 및 일단이 제 2 다이에 접속되고 타단이 랜드 패드에 접속되는 제 3 복수의 와이어 리드를 포함하는 스택 패키지 어셈블리에 관한 것이다.

Bonding wire for semiconductor device

A bonding wire includes a Cu alloy core material, and a Pd coating layer formed on the Cu alloy core material. The bonding wire contains at least one element selected from Ni, Zn, Rh, In, Ir, and Pt. A concentration of the elements in total relative to the entire wire is 0.03% by mass or more and 2% by mass or less. When measuring crystal orientations on a cross-section of the core material in a direction perpendicular to a wire axis of the bonding wire, a crystal orientation <100> angled at 15 degrees or less to a wire axis direction has a proportion of 50% or more among crystal orientations in the wire axis direction. An average crystal grain size in the cross-section of the core material in the direction perpendicular to the wire axis of the bonding wire is 0.9 μm or more and 1.3 μm or less.

Bonddraht für Halbleitervorrichtung

Bonddraht für eine Halbleitervorrichtung, der aufweist:ein Cu-Legierungskernmaterial; undeine Pd-Überzugschicht, die auf einer Oberfläche des Cu-Legierungskernmaterials ausgebildet ist, wobeider Bonddraht wenigstens ein oder mehrere erste Elemente enthält, die aus Sb, Bi und Se ausgewählt sind,eine Konzentration der ersten Elemente insgesamt 0,1 Massen-ppm oder mehr und 100 Massen-ppm oder weniger relativ zu dem Gesamtdraht ist, undSb ≤ 10 Massen-ppm und Bi ≤ 1 Massen-ppm, undder Bonddraht wenigstens ein oder mehrere zweite Elemente enthält, die aus Ni, Zn, Rh, In, Ir, Pt, Ga und Ge ausgewählt sind, undeine Konzentration jedes der zweiten Elemente 0,011 Massen-% oder mehr und 1,2 Massen-% oder weniger relativ zu dem Gesamtdraht beträgt.

ADHESIVE SHEET AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

본 발명의 접착시트는, (A)고분자량 성분과, (B1)연화점이 50℃ 미만인 열경화성 성분과, (B2)연화점이 50℃ 이상 100℃ 이하인 열경화성 성분과, (C)연화점이 100℃ 이하인 페놀 수지를 포함하는 수지 조성물로 이루어지고, 그 수지 조성물 100질량%를 기준으로 하여, 상기 (A)고분자량 성분을 11∼22질량%, 상기 (B1)연화점이 50℃ 미만인 열경화성 성분을 10∼20질량%, 상기 (B2)연화점이 50℃ 이상 100℃ 이하인 열경화성 성분을 10∼20질량%, 상기 (C)연화점이 100℃ 이하인 페놀 수지를 15∼30질량% 함유한다. The adhesive sheet of this invention is a (A) high molecular weight component, (B1) thermosetting component whose softening point is less than 50 degreeC, (B2) thermosetting component whose softening point is 50 degreeC or more and 100 degrees C or less, and (C) softening point which is 100 degrees C or less. It consists of a resin composition containing a phenol resin, and based on 100 mass% of this resin composition, 11-22 mass% of said (A) high molecular weight components, and the said (B1) softening point 10-10-thermosetting components of less than 50 degreeC. 20 mass%, the said (B2) softening point contains 10-20 mass% of thermosetting components which are 50 degreeC or more and 100 degrees C or less, and 15-30 mass% of phenol resins whose said (C) softening point are 100 degrees C or less.

ANTENNA MODULE

Embedded wire bond wires

Apparatuses relating generally to a vertically integrated microelectronic package are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface. A first microelectronic device is coupled to the upper surface of the substrate. The first microelectronic device is a passive microelectronic device. First wire bond wires are coupled to and extend away from the upper surface of the substrate. Second wire bond wires are coupled to and extend away from an upper surface of the first microelectronic device. The second wire bond wires are shorter than the first wire bond wires. A second microelectronic device is coupled to upper ends of the first wire bond wires and the second wire bond wires. The second microelectronic device is located above the first microelectronic device and at least partially overlaps the first microelectronic device.

Module assembly

A module assembly includes an adapter substrate with at least one cavity and a surface mounted die mounted on a top surface of the adapter substrate. The first cavity extends through the adapter substrate and has at least one first side wall. A first metallization layer is provided within the cavity. A first recessed die is attached to the first metallization layer and mounted within the cavity such that the first recessed die is at least partially recessed into the first cavity and surrounded by a gap filler that resides between side portions of the first recessed die and the at least one first side wall. The top surface of the gap filler is flush with the top surface of the adapter substrate and a top surface of the first recessed die.

Bonding wire for semiconductor device

A bonding wire for a semiconductor device including a coating layer having Pd as a main component on the surface of a Cu alloy core material and a skin alloy layer containing Au and Pd on the surface of the coating layer has a Cu concentration of 1 to 10 at % at an outermost surface thereof and has the core material containing a metallic element of Group 10 of the Periodic Table of Elements in a total amount of 0.1 to 3.0% by mass, thereby achieving improvement in 2nd bondability and excellent ball bondability in a high-humidity heating condition. Furthermore, a maximum concentration of Au in the skin alloy layer is preferably 15 at % to 75 at %.

Method of manufacturing multi-chip package

A multi-chip package includes a package substrate including a first substrate pad, a first group of semiconductor chips stacked on the package substrate, each of the first group of the semiconductor chips including bonding pads, first stud bumps arranged on the bonding pads of the first group of the semiconductor chips except for a lowermost semiconductor chip in the first group, a first conductive wire downwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and connected to the first substrate pad, and a second conductive wire upwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and sequentially connected to the first stud bumps.

Semiconductor chip having pads with plural junctions for different assembly methods

Development efficiency and mass production efficiency of a semiconductor chip (LSI) is improved, whereby the LSI on which an integrated circuit is formed has plural pad parts connecting the integrated circuit with an external circuit. The pad part is provided with a first junction consisting of a window formed in the protective film and the pad exposed from the window, and a second junction consisting of a window formed in the protective film and a bump deposited on the pad exposed from the window. When it is required that the LSI is to be connected with an external circuit by wire bonding, the first junction is connected with the external circuit using a wire. When it is required to connect the LSI with an external circuit by the TAB method or the COG method, the second junction is directly connected to the external circuit.

Semiconductor chip having pads with plural junctions for different assembly methods

Development efficiency and mass production efficiency of a semiconductor chip (LSI) is improved, whereby the LSI on which an integrated circuit is formed has plural pad parts connecting the integrated circuit with an external circuit. The pad part is provided with a first junction consisting of a window formed in the protective film and the pad exposed from the window, and a second junction consisting of a window formed in the protective film and a bump deposited on the pad exposed from the window. When it is required that the LSI is to be connected with an external circuit by wire bonding, the first junction is connected with the external circuit using a wire. When it is required to connect the LSI with an external circuit by the TAB method or the COG method, the second junction is directly connected to the external circuit.

Cu ALLOY CORE BONDING WIRE WITH Pd COATING FOR SEMICONDUCTOR DEVICE

A bonding wire for a semiconductor device includes a Cu alloy core material and a Pd coating layer formed on a surface thereof, and the boding wire contains one or more elements of As, Te, Sn, Sb, Bi and Se in a total amount of 0.1 to 100 ppm by mass. The bonding longevity of a ball bonded part can increase in a high-temperature and high-humidity environment, improving the bonding reliability. When the Cu alloy core material further contains one or more of Ni, Zn, Rh, In, Ir, Pt, Ga and Ge in an amount, for each, of 0.011 to 1.2% by mass, it is able to increase the reliability of a ball bonded part in a high-temperature environment of 170° C. or more. When an alloy skin layer containing Au and Pd is further formed on a surface of the Pd coating layer, wedge bondability improves.

반도체 패키지 및 그 제조방법

... 와이어 본딩을 이용하는 반도체 패키지 및 이의 제조방법이 개시된다. 본 발명의 실시예에 따른 반도체 패키지는 관통부가 형성되고 관통부 주위에 마련되는 관통배선을 통해 상부면과 하부면 사이에 전기적 신호의 전달이 가능한 프레임과, 관통부에 수용되는 제1 반도체 칩과, 프레임과 제1 반도체 칩의 하부에 마련되고 관통배선과 제1 반도체 칩을 전기적으로 연결하는 배선부와, 제1 반도체 칩 상에 적층되는 제2 반도체 칩과, 제2 반도체 칩과 프레임의 신호부를 전기적으로 연결하는 와이어와, 프레임과 제1 및 제2 반도체 칩과 와이어를 일체화하도록 몰딩하는 봉지재를 포함한다.

POWER MODULE PACKAGE AND MANUFACTURING METHOD THEREOF

The present invention relates to a power module package which realizes uniform thickness for the package, and a manufacturing method thereof. The power module package comprises: a lower substrate having a pattern formed thereon; a power semiconductor element and a ribbon installed on an upper surface of the lower substrate by being separated at regular intervals; a first spacer bonded to an upper part of the power semiconductor element by using a first bonding layer as a medium; a second spacer bonded to an upper part of the ribbon by using a second bonding layer as a medium; and an upper substrate bonded to an upper part of the first and second spacers by using a third bonding layer as a medium. COPYRIGHT KIPO 2017 ...

SEMICONDUCTOR DEVICE

An object of the present invention is to improve the reliability of a semiconductor device. The semiconductor device includes semiconductor chips CP1 and CP2, a plurality of leads, a plurality of wires, and a sealing body sealing the stated components. The semiconductor CP1 has pad electrodes P1a and P1b, and inner wire NH electrically connected between the pad electrodes P1a and P1b. Wire BW1 is electrically connected as interposed between the pad electrode P2a of the semiconductor chip CP2 and the electrode P1a of the semiconductor chip CP1. The pad electrode P1b of the semiconductor ship CP1 is electrically connected to lead LD1 by interposing wire BW2 therebetween. A distance between the lead LD1 and the semiconductor chip CP1 is less than that between the lead LD1 and the semiconductor chip CP2. Also, the pad electrodes P1a and P1b and the inner wire NH are not connected to any circuits formed in the semiconductor chip CP1. COPYRIGHT KIPO 2016 (AA) Wire (BB) Semiconductor chip (CC) ...

Camera module

A camera module, in which a recessed portion that has a greater depth than the thickness of an imaging device is disposed on the surface (top surface) of an embedded-component substrate. An imaging device is bonded to a bottom of the recessed portion such that an opening is present between the surface (top surface) of the imaging device and the surface (top surface) of the embedded-component substrate. Connection pads on the imaging device are connected to conductor pads disposed on the surface (top surface) of the embedded-component substrate by bonding wires that go through the opening.

SEMICONDUCTOR CHIP HAVING PADS WITH PLURAL DIFFERENT JUNCTION TYPE

The present invention improves development efficiency and mass production efficiency of a semiconductor chip (LSI). The LSI on which an integrated circuit is formed has plural pad parts connecting the integrated circuit with an external circuit. The pad part is provided with the junction consisting of a window formed in the protective film and the pad exposing from the window, and the junction consisting of a window formed in the protective film and the bump deposited on the pad exposing from the window. When it is required the LSI is connected with an external circuit by wire bonding, the junction is connected with the external circuit through the wire, and when it is required to connect with an external circuit with the TAB method or the COG method, the junction is directly connected to the external circuit.

Embedded wire bond wires

Apparatuses relating generally to a vertically integrated microelectronic package are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface. A first microelectronic device is coupled to the upper surface of the substrate. The first microelectronic device is a passive microelectronic device. First wire bond wires are coupled to and extend away from the upper surface of the substrate. Second wire bond wires are coupled to and extend away from an upper surface of the first microelectronic device. The second wire bond wires are shorter than the first wire bond wires. A second microelectronic device is coupled to upper ends of the first wire bond wires and the second wire bond wires. The second microelectronic device is located above the first microelectronic device and at least partially overlaps the first microelectronic device.

Method and apparatus for integrating current sensors in a power semiconductor module

An improved system for measuring current within a power semiconductor module is disclosed, where the system is integrated within the power module. The system includes a point field detector sensing a magnetic field resulting from current flowing in one phase of the module. A lead frame conductor may be provided to shape the magnetic field and minimize the influence of cross-coupled magnetic fields from currents conducted in other power semiconductor devices within one phase of the module. Optionally, a second point field detector may be provided at a second location within the module to sense a magnetic field resulting from the current flowing in the same phase of the module. Each phase of the power module includes at least one point field detector. A decoupling circuit is provided to decouple multiple currents flowing within the same phase or to decouple currents flowing within different phases of the power module.

Photonic quantum computer assembly having dies with specific contact configuration and matched CTE

Techniques disclosed herein relate to devices that each include one or more photonic integrated circuits and/or one or more electronic integrated circuits. In one embodiment, a device includes a silicon substrate, a die stack bonded (e.g., fusion-bonded) on the silicon substrate, and a printed circuit board (PCB) bonded on the silicon substrate, where the PCB is electrically coupled to the die stack. The die stack includes a photonic integrated circuit (PIC) that includes a photonic integrated circuit, and an electronic integrated circuit (EIC) die that includes an electronic integrated circuit, where the EIC die and the PIC die are bonded face-to-face (e.g., by fusion bonding or hybrid bonding) such that the photonic integrated circuit and the electronic integrated circuit face each other. In some embodiments, the device also includes a plurality of optical fibers coupled to the photonic integrated circuit.

Bonding wire for semiconductor device

This invention relates to a bonding wire for a semiconductor device, said bonding wire having a Cu alloy core and a Pd coating layer formed on the surface of the Cu alloy core, and being characterized by achieving increased connection reliability of a ball connection part in HTS under 175DEG C to 200DEG C while the proof stress ratio (maximum proof stress / 0.2% proof stress) is 1.1-1.6. By containing in the wire a total of 0.03-2 mass% of at least one of Ni, Zn, Rh, In, Ir and Pt, the connection reliability of the ball connection part in HTS is increased, such that among the crystal orientations in the lengthwise direction of the wire as found in the measurement of crystal orientations in relation to a cross-section of the core in a direction perpendicular to the wire axis of the bonding wire, the orientation proportion of crystal orientation<100>, for which the angular difference does not exceed 15 degrees relative to the lengthwise direction of the wire, is at least 50%. The proof stress ...

SEMICONDUCTOR PACKAGE WITH INTEGRATED HEATSINK

One or more embodiments are directed to semiconductor packages having an integrated heatsink and methods of forming same. In one embodiment, a package includes a plurality of leads that support and enclose periphery portions of the semiconductor die. The leads have first and second, opposing surfaces that form outer surfaces of the package. The first surface of the leads may form a heatsink and the second surface of the leads form lands of the package for coupling to another device, substrate, or board. The package includes encapsulation material that surrounds the semiconductor die and located between upper portions of the leads. The package further includes a back filling material (or insulating material) that is below the semiconductor die and between lower portions of the leads.

Photonic quantum computer assembly

A device includes a die stack including a first die including a quantum circuit and a second die including an electronic circuit. The second die and the first die face each other. The device also includes a first interconnect between the quantum circuit and the electronic circuit and a second interconnect between the quantum circuit and the electronic circuit.

MODULE ASSEMBLY

A module assembly includes an adapter substrate with at least one cavity and a surface mounted die mounted on a top surface of the adapter substrate. The first cavity extends through the adapter substrate and has at least one first side wall. A first metallization layer is provided within the cavity. A first recessed die is attached to the first metallization layer and mounted within the cavity such that the first recessed die is at least partially recessed into the first cavity and surrounded by a gap filler that resides between side portions of the first recessed die and the at least one first side wall. The top surface of the gap filler is flush with the top surface of the adapter substrate and a top surface of the first recessed die. 1. An apparatus comprising:an adapter substrate having a backside surface, a top surface opposite the backside surface, and a first cavity that extends through the adapter substrate and has at least one first side wall;a first metallization layer formed within the first cavity;a first recessed die attached to the first metallization layer and mounted within the first cavity such that the first recessed die is at least partially recessed into the first cavity and surrounded by a gap filler that resides between side portions of the first recessed die and the at least one first side wall, wherein a top surface of the gap filler is flush with the top surface of the adapter substrate and a top surface of the first recessed die; anda surface mounted die attached to the top surface of the adapter substrate.2. The apparatus of further comprising:vias that extend into the top surface of the adapter substrate;surface traces on the top surface of the adapter substrate, wherein at least one of the vias is electrically connected to at least one other of the vias; andchip-to-chip interconnects that extend over the top surface of the gap filler and between the top surface of the first recessed die and at least one of the surface traces or at least ...

Bonding line and semiconductor packaging part

SEMICONDUCTOR DEVICE PACKAGE HAVING GALVANIC ISOLATION AND METHOD THEREFOR

A semiconductor device package having galvanic isolation is provided. The semiconductor device includes a package substrate having a first inductive coil formed from a first conductive layer and a second inductive coil formed from a second conductive layer. The first conductive layer and the second conductive layer are separated by a nonconductive material. A first semiconductor die is attached to a first major side of the package substrate. The first semiconductor die is conductively interconnected to the first inductive coil. A second semiconductor die is attached to the first major side of the package substrate. A first wireless communication link between the first semiconductor die and the second semiconductor die is formed by way of the first and second inductive coils.

Bonddraht für Halbleitervorrichtung

Es wird ein Bonddraht für eine Halbleitervorrichtung mit einer Überzugschicht mit Pd als einer Hauptkomponente auf einer Oberfläche eines Cu-Kernlegierungsmaterials und einer Außenlegierungsschicht, die Au und Pd enthält, auf einer Oberfläche der Überzugschicht bereitgestellt, wobei der Bonddraht ferner die Zweitbondfähigkeit einer Pd-metallisierten Leiterplatte verbessert und selbst unter einer Hochfeuchtigkeitsheizbedingung eine hervorragende Kugelbondfähigkeit erreicht. Der Bonddraht für eine Halbleitervorrichtung, der die Überzugschicht mit Pd als einer Hauptkomponente auf der Oberfläche des Cu-Legierungskernmaterials und die Außenlegierungsschicht, die Au und Pd enthält, auf der Oberfläche der Überzugschicht umfasst, hat eine Cu-Konzentration von 1 bis 10 At-% auf seiner äußersten Oberfläche und hat das Kernmaterial, das entweder Pd oder Pt oder beides in einer Gesamtmenge von 0,1 bis 3,0 Massen-% enthält, wodurch eine Verbesserung der Zweitbondfähigkeit und einer hervorragende Kugelbondfähigkeit ...

Bonddraht für Halbleitervorrichtung

Bereitgestellt wird ein Bonddraht für eine Halbleitervorrichtung, wobei der Bonddraht ein Cu-Legierungskernmaterial und eine auf einer Oberfläche davon gebildete Pd-Überzugschicht aufweist und Verbesserung der Bondzuverlässigkeit eines Kugelbondteils bei hoher Temperatur sowie gleichzeitig ein Festigkeitsverhältnis (= Bruchfestigkeit/0,2-%-Fließfestigkeit) von 1,1 bis 1,6 erreicht. Indem er ein Element enthält, das für Bondzuverlässigkeit in einer Umgebung mit hoher Temperatur sorgt, ist die Bondzuverlässigkeit des Kugelbondteils bei hoher Temperatur verbessert. Indem außerdem bewirkt wird, dass ein Orientierungsanteil einer Kristallorientierung <100> im Winkel von höchstens 15 Grad zu einer Drahtlängsrichtung unter Kristallorientierungen in Drahtlängsrichtung mindestens 30% bei Messung von Kristallorientierungen auf einem Querschnitt des Kernmaterials in senkrechter Richtung zu einer Drahtachse des Bonddrahts beträgt, und indem bewirkt wird, dass eine mittlere Kristallkorngröße im Querschnitt ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME

COPPER ALLOY BONDING WIRE FOR SEMICONDUCTOR DEVICE

패키지 온 패키지 제품을 위한 와이어 리드를 포함하는 적층 패키지 어셈블리, 컴퓨팅 디바이스 및 집적 패키지 설계 방법

... 패키지 온 패키지 제품용 집적 패키지 설계가 와이어 리드를 사용하여 기술된다. 일부 실시예는 전면 및 이면을 갖는 제 1 다이, 제 1 다이의 이면에 부착된 다이 패들, 일단이 외부 디바이스에 대한 접속을 위해 다이의 전면에 접속되는 복수의 와이어 리드, 제 1 다이 및 다이 패들의 적어도 일부를 캡슐화하는 몰드 화합물, 다이 패들로부터 절단되고 몰드 화합물에 의해 지지된 랜드 패드, 와이어 리드의 일단이 제 1 다이의 전면에 접속되고 와이어 리드의 타단이 랜드 패드에 접속되는 제 2 복수의 와이어 리드, 다이 패들 위에 적층된 제 2 다이, 및 일단이 제 2 다이에 접속되고 타단이 랜드 패드에 접속되는 제 3 복수의 와이어 리드를 포함하는 적층 패키지 어셈블리에 관한 것이다.

반도체 장치용 본딩 와이어

... 표면에 Pd 피복층을 갖는 Cu 본딩 와이어에 있어서, 고온 고습 환경에서의 볼 접합부의 접합 신뢰성을 개선하고, 차량 탑재용 디바이스에 바람직한 본딩 와이어를 제공한다. Cu 합금 코어재와 그 표면에 형성된 Pd 피복층을 갖는 반도체 장치용 본딩 와이어에 있어서, 본딩 와이어가 As, Te, Sn, Sb, Bi, Se의 1종 이상의 원소를 합계로 0.1 내지 100질량ppm 함유한다. 이에 의해, 고온 고습 환경 하에서의 볼 접합부의 접합 수명을 향상시켜, 접합 신뢰성을 개선할 수 있다. Cu 합금 코어재가 또한 Ni, Zn, Rh, In, Ir, Pt, Ga, Ge의 1종 이상을 각각 0.011 내지 1.2질량% 함유하면, 170℃ 이상의 고온 환경에서의 볼 접합부 신뢰성을 향상시킬 수 있다. 또한, Pd 피복층의 표면에 또한 Au와 Pd를 포함하는 합금 표피층을 형성하면 웨지 접합성이 개선된다.

Bonding wire for semiconductor device

This invention relates to a bonding wire for a semiconductor device, said bonding wire having a Cu alloy core and a Pd coating layer formed on the surface of the Cu alloy core, and being characterized by achieving increased connection reliability of a ball connection part in HTS under 175 DEG C to 200 DEG C while the proof stress ratio (maximum proof stress / 0.2% proof stress) is 1.1-1.6. By containing in the wire a total of 0.03-2 mass% of at least one of Ni, Zn, Rh, In, Ir and Pt, the connection reliability of the ball connection part in HTS is increased, such that among the crystal orientations in the lengthwise direction of the wire as found in the measurement of crystal orientations in relation to a cross-section of the core in a direction perpendicular to the wire axis of the bonding wire, the orientation proportion of crystal orientation<100>, for which the angular difference does not exceed 15 degrees relative to the lengthwise direction of the wire, is at least 50%. The proof ...

METHOD FOR REPLACING CAPILLARY

A method for replacing a capillary of a wire bonding apparatus that includes a holding unit that holds a capillary includes transferring a capillary replacing unit to the wire bonding apparatus by a mobile robot in response to receiving a capillary replacement start signal from the wire bonding apparatus, separating, by the capillary replacing unit, the capillary corresponding to the replacement signal from the wire bonding apparatus, and installing, by the capillary replacing unit, a new capillary in the wire bonding apparatus.

Bonddraht für Halbleitervorrichtung

Es wird ein Cu-Bonddraht mit einer Pd-Überzugschicht auf seiner Oberfläche bereitgestellt, der die Verbindungszuverlässigkeit eines kugelgebondeten Teils in einer Hochtemperatur- und Hochfeuchtigkeitsumgebung verbessert und für Vorrichtungen im Fahrzeug geeignet ist. Der Bonddraht für eine Halbleitervorrichtung umfasst ein Cu-Legierungskernmaterial und eine Pd-Überzugschicht, die auf seiner Oberfläche ausgebildet ist, und der Bonddraht enthält ein oder mehrere Elemente von As, Te, Sn, Sb, Bi und Se in einer Gesamtmenge von 0,1 bis 100 Massen-ppm. Mit diesem Aufbau ist er fähig, die Langlebigkeit der Verbindung eines kugelgebondeten Teils in einer Hochtemperatur- und Hochfeuchtigkeitsumgebung zu erhöhen und somit die Verbindungszuverlässigkeit zu verbessern. Wenn das Cu-Legierungskernmaterial ferner ein oder mehrere von Ni, Zn, Rh, In, Ir, Pt, Ga und Ge für jedes in einer Menge von 0,011 bis 1,2 Massen-% enthält, ist es fähig, die Zuverlässigkeit eines kugelgebondeten Teils in einer Hochtemperaturumgebung ...

Kupferlegierungs-Bonddraht für Halbleiterbauteile

Bei einem Kupferlegierungs-Bonddraht für Halbleiterbauteile wird die Bonding-Langlebigkeit einer Ball-gebondeten Komponente in Umgebungen mit hoher Temperatur und hoher Luftfeuchtigkeit verbessert. Der Kupferlegierungs-Bonddraht für Halbleiterbauteile weist insgesamt 0,03 % Massenanteil oder mehr bis 3 % Massenanteil oder weniger von wenigstens einer Art oder mehreren Arten von Elementen auf, die ausgewählt sind aus Ni, Zn, Ga, Ge, Rh, In, Ir und Pt (erstes Element) mit dem Rest Kupfer und unvermeidbaren Verunreinigungen. Das Einbinden einer bestimmten Menge des ersten Elements unterbindet die Erzeugung einer intermetallischen Verbindung, die in Umgebungen mit hoher Temperatur und hoher Luftfeuchtigkeit an der Draht-Bonding-Schnittstelle korrosionsanfällig ist, und verbessert die Bonding-Langlebigkeit bei einer Ball-gebondeten Komponente.

CAMERA MODULE

Method and apparatus for integrating current sensors in a power semiconductor module

An improved system for measuring current within a power semiconductor module is disclosed, where the system is integrated within the power module. The system includes a point field detector sensing a magnetic field resulting from current flowing in one phase of the module. A lead frame conductor may be provided to shape the magnetic field and minimize the influence of cross-coupled magnetic fields from currents conducted in other power semiconductor devices within one phase of the module. Optionally, a second point field detector may be provided at a second location within the module to sense a magnetic field resulting from the current flowing in the same phase of the module. Each phase of the power module includes at least one point field detector. A decoupling circuit is provided to decouple multiple currents flowing within the same phase or to decouple currents flowing within different phases of the power module.

접착시트 및 반도체 장치의 제조 방법

... 본 발명의 접착시트는, (A)고분자량 성분과, (B1)연화점이 50℃ 미만인 열경화성 성분과, (B2)연화점이 50℃ 이상 100℃ 이하인 열경화성 성분과, (C)연화점이 100℃ 이하인 페놀 수지를 포함하는 수지 조성물로 이루어지고, 그 수지 조성물 100질량%를 기준으로 하여, 상기 (A)고분자량 성분을 11∼22질량%, 상기 (B1)연화점이 50℃ 미만인 열경화성 성분을 10∼20질량%, 상기 (B2)연화점이 50℃ 이상 100℃ 이하인 열경화성 성분을 10∼20질량%, 상기 (C)연화점이 100℃ 이하인 페놀 수지를 15∼30질량% 함유한다.

LEADFRAME CAPACITORS

Bonddraht für Halbleitervorrichtung

Es wird ein Bonddraht für eine Halbleitervorrichtung bereitgestellt, wobei der Bonddraht ein Cu-Legierungskernmaterial und eine Pd-Überzugschicht, die auf einer Oberfläche davon ausgebildet ist, aufweist, der gleichzeitig eine Verbesserung der Verbindungszuverlässigkeit eines kugelgebondeten Teils im HTS bei 175°C bis 200°C und ein Streckgrenzenverhältnis (= maximale Streckgrenze/0,2%-Versatzstreckgrenze) von 1,1 bis 1,6 erreicht. Das Aufweisen von einem oder mehreren Elementen aus Ni, Zn, Rh, In, Ir und Pt in dem Draht in einer Gesamtmenge von 0,03 bis 2 Massen-% verbessert die Verbindungszuverlässigkeit des kugelgebondeten Teils im HTS, und außerdem wird ein Streckgrenzenverhältnis von 1,6 oder weniger bereitgestellt, indem ein Orientierungsanteil einer Kristallorientierung <100> mit 15 Grad oder weniger zu einer Drahtlängsrichtung an Kristallorientierungen in der Drahtlängsrichtung zu 50% oder mehr gemacht wird, wenn Kristallorientierungen auf einem Querschnitt des Kernmaterials in einer ...

Optoelektronisches Bauteil und Verfahren zur Herstellung eines optoelektronischen Bauteils

Optoelektronisches Bauteil mit einem Halbleiterchip, der Infrarotstrahlung emittiert, mit einem Reflektor, der die Infrarotstrahlung des Halbleiterchips reflektiert und mit einem Filter. Der Filter ist in Form einer Beschichtung ausgeführt, und durchlässig für die Infrarotstrahlung des Halbleiterchips. Sichtbares Licht, das auf das optoelektronische Bauteil trifft, wird vom Filter wenigstens zu 75 % absorbiert. Ein Verfahren zum Herstellen eines optoelektronischen Bauteils umfasst die Schritte Platzieren eines optoelektronischen Halbleiterchips auf einem Träger, elektrisches Kontaktieren des Halbleiterchips, platzieren eines Reflektors auf dem Träger und aufbringen eines Filters, indem eine Beschichtung aufgebracht wird.

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD

A semiconductor package and a manufacturing method are disclosed. The semiconductor package includes at least one chip disposed on a package substrate, a boundary wall including a conductive via part and a conductive trace disposed on the package substrate, a bonding wire for grounding the conductive via to the package substrate, a dielectric layer for exposing the conductive traces, and a conductive roof covering the conductive trace and extended to cover the surface of the dielectric layer. Therefore, it is possible to provide a semiconductor package with an electro-magnetic interference structure. COPYRIGHT KIPO 2017 ...

LGA PACKAGE SUBSTRATE HAVING SIDE PAD ON EDGE THEREOF, LGA PACKAGE SUBSTRATE, CHIP STACK, SEMICONDUCTOR PACKAGE, AND SSD SYSTEM INCLUDING SAME

An LGA semiconductor package according to the present invention includes an integrated substrate, one bottom chip stack which is mounted on the integrated substrate and charges a part of the whole memory capacity by stacking a plurality of semiconductor dies with a chip on chip type, at least one or more top chip stacks which are mounted on the bottom package and charge the remaining part of the whole memory capacity by stacking the plurality of memory semiconductor dies, an integrated wire which electrically connects the bottom chip stack and the top chip stack, and an integrated protection member which seals the integrated wire. Accordingly, the present invention provides a NAND flash memory LGA semiconductor package to implement the request of high capacitance and ultra slimness according to an SSD standardization trend. COPYRIGHT KIPO 2017 ...

POWER OVERLAY STRUCTURE HAVING WIRE BOND AND MANUFACTURING METHOD THEREOF

A power overlay (POL) structure comprises: a power device having at least one upper contact pad arranged on an upper surface of the power device; and a POL interconnection layer having a dielectric layer coupled to the upper surface of the power device and a metal layer having a metal interconnection extending by vias formed through the dielectric layer and electrically coupled to the at least one upper contact pad of the power device. The POL structure also includes at least one copper wire bond directly coupled to the metal layer. The purpose of the present invention is to provide a manufacturing method of a POL structure improving a manufacturing yield rate by reducing damage to a device. COPYRIGHT KIPO 2016 ...

ISOLATOR WITH SYMMETRIC MULTI-CHANNEL LAYOUT

An integrated circuit isolation product includes a first integrated circuit die. The first integrated circuit die includes a first terminal and a second terminal adjacent to the first terminal. The first terminal and the second terminal are configured as a differential pair of terminals configured to communicate a differential signal across an isolation barrier. The first integrated circuit die includes at least one additional terminal adjacent to the differential pair of terminals. The at least one additional terminal is disposed symmetrically with respect to the differential pair of terminals. The first terminal may have a first parasitic capacitance and the second terminal may have a second parasitic capacitance. The first parasitic capacitance may be substantially the same as the second parasitic capacitance. The at least one additional terminal may be disposed symmetrically with respect to a line of symmetry for the differential pair of terminals. 1. An integrated circuit isolation product comprising: a first terminal;', 'a second terminal adjacent to the first terminal, the first terminal and the second terminal being configured as a differential pair of terminals configured to communicate a differential signal across an isolation barrier; and', 'at least one additional terminal adjacent to the differential pair of terminals, the at least one additional terminal being disposed symmetrically with respect to the differential pair of terminals., 'a first integrated circuit die comprising2. The integrated circuit isolation product claim 1 , as recited in claim 1 , wherein the first terminal has a first parasitic capacitance and the second terminal has a second parasitic capacitance claim 1 , the first parasitic capacitance being substantially the same as the second parasitic capacitance.3. The integrated circuit isolation product claim 2 , as recited in claim 2 , wherein the first parasitic capacitance is within 1% of the second parasitic capacitance.4. The ...

COPPER ALLOY BONDING WIRE FOR SEMICONDUCTOR DEVICES

In a copper alloy bonding wire for semiconductor devices, the bonding longevity of a ball bonded part under high-temperature and high-humidity environments is improved. The copper alloy bonding wire for semiconductor devices includes in total 0.03% by mass or more to 3% by mass or less of at least one or more kinds of elements selected from Ni, Zn, Ga, Ge, Rh, In, Ir, and Pt (first element), with the balance Cu and inevitable impurities. The inclusion of a predetermined amount of the first element suppresses production of an intermetallic compound susceptible to corrosion under high-temperature and high-humidity environments at the wire bonding interface and improves the bonding longevity of a ball bonded part.

Bonddraht für Halbleitervorrichtung

Es wird ein Cu-Bonddraht mit einer Pd-Überzugschicht auf seiner Oberfläche bereitgestellt, der die Verbindungszuverlässigkeit eines kugelgebondeten Teils in einer Hochtemperatur- und Hochfeuchtigkeitsumgebung verbessert und für Vorrichtungen im Fahrzeug geeignet ist. Der Bonddraht für eine Halbleitervorrichtung umfasst ein Cu-Legierungskernmaterial und eine Pd-Überzugschicht, die auf seiner Oberfläche ausgebildet ist, und der Bonddraht enthält ein oder mehrere Elemente von As, Te, Sn, Sb, Bi und Se in einer Gesamtmenge von 0,1 bis 100 Massen-ppm. Mit diesem Aufbau ist er fähig, die Langlebigkeit der Verbindung eines kugelgebondeten Teils in einer Hochtemperatur- und Hochfeuchtigkeitsumgebung zu erhöhen und somit die Verbindungszuverlässigkeit zu verbessern. Wenn das Cu-Legierungskernmaterial ferner ein oder mehrere von Ni, Zn, Rh, In, Ir, Pt, Ga und Ge für jedes in einer Menge von 0,011 bis 1,2 Massen-% enthält, ist es fähig, die Zuverlässigkeit eines kugelgebondeten Teils in einer Hochtemperaturumgebung ...

Connection lines for semiconductor devices

ADHESIVE SHEET AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor device capable of preventing the uppermost semiconductor chip from being damaged even though an excessive force is applied to the semiconductor device during a die bonding process or a wire bonding process, and a manufacturing method thereof. The semiconductor device includes a substrate, a first semiconductor chip which is die-bonded on the substrate by a first bonding layer, and a second semiconductor chip which is die-bonded on the second die-bonding layer by a second die bonding layer. COPYRIGHT KIPO 2017 ...

Quantum computing die assembly with thru-silicon vias and connected logic circuit

Techniques disclosed herein relate to devices that each include one or more photonic integrated circuits and/or one or more electronic integrated circuits. In one embodiment, a device includes a silicon substrate, a die stack bonded (e.g., fusion-bonded) on the silicon substrate, and a printed circuit board (PCB) bonded on the silicon substrate, where the PCB is electrically coupled to the die stack. The die stack includes a photonic integrated circuit (PIC) that includes a photonic integrated circuit, and an electronic integrated circuit (EIC) die that includes an electronic integrated circuit, where the EIC die and the PIC die are bonded face-to-face (e.g., by fusion bonding or hybrid bonding) such that the photonic integrated circuit and the electronic integrated circuit face each other. In some embodiments, the device also includes a plurality of optical fibers coupled to the photonic integrated circuit.

BONDING WIRE AND WIRE BONDING USING SAME

Provided is a bonding wire with reduced manufacturing cost. The bonding wire according to embodiments of the present invention comprises: a wire core including a silver-palladium alloy; and a coating film covering a side wall of the wire core, wherein the content of palladium in the silver-palladium alloy is 0.1 wt% to 1.5 wt%. COPYRIGHT KIPO 2018 ...

ADHESIVE SHEET AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

The adhesive sheet of the invention comprises a resin composition containing (A) a high-molecular-weight component, (B1) a thermosetting component having a softening point of below 50° C., (B2) a thermosetting component having a softening point of between 50° C. and 100° C. and (C) a phenol resin having a softening point of no higher than 100° C., the composition containing 11 to 22 mass % of the (A) high-molecular-weight component, 10 to 20 mass % of the (B1) thermosetting component having a softening point of below 50° C., 10 to 20 mass % of the (B2) thermosetting component having a softening point of between 50° C. and 100° C. and 15 to 30 mass % of the phenol resin having a softening point of no higher than 100° C., based on 100 mass % of the resin composition.

Bonding wire for semiconductor device

The bonding wire for a semiconductor device includes a Cu alloy core material and a Pd coating layer formed on a surface of the Cu alloy core material, and the bonding wire contains In of 0.011 to 1.2% by mass and has the Pd coating layer of a thickness of 0.015 to 0.150 μm. With this configuration, it is able to increase the bonding longevity of a ball bonded part in a high-temperature and high-humidity environment, and thus to improve the bonding reliability. When the Cu alloy core material contains one or more elements of Pt, Pd, Rh and Ni in an amount, for each element, of 0.05 to 1.2% by mass, it is able to increase the reliability of a ball bonded part in a high-temperature environment of 175° C. or more. When an Au skin layer is further formed on a surface of the Pd coating layer, wedge bondability improves.

MODULE ASSEMBLY

A module assembly includes an adapter substrate with at least one cavity and a surface mounted die mounted on a top surface of the adapter substrate. The first cavity extends through the adapter substrate and has at least one first side wall. A first metallization layer is provided within the cavity. A first recessed die is attached to the first metallization layer and mounted within the cavity such that the first recessed die is at least partially recessed into the first cavity and surrounded by a gap filler that resides between side portions of the first recessed die and the at least one first side wall. The top surface of the gap filler is flush with the top surface of the adapter substrate and a top surface of the first recessed die.

Bonddraht für Halbleitervorrichtung

Bonddraht für eine Halbleitervorrichtung, der aufweist:ein Kernmaterial mit Cu als einer Hauptkomponente und das zumindest ein metallisches Element der Gruppe 10 des Periodensystems der Elemente in einer Gesamtmenge von 0,1 Massen-% oder mehr und 3,0 Massen-% oder weniger enthält;eine Beschichtungsschicht mit Pd als einer Hauptkomponente, die auf einer Oberfläche des Kernmaterials bereitgestellt ist; undeine Außenlegierungsschicht, die Au und Pd enthält, die auf einer Oberfläche der Beschichtungsschicht bereitgestellt ist,wobei eine Konzentration von Cu auf einer äußersten Oberfläche des Drahts 1 At-% oder mehr und 10 At-% oder weniger ist und das zumindest eine metallische Element der Gruppe 10 des Periodensystems der Elemente Ni aufweist.

반도체 장치용 본딩 와이어

Cu 합금 코어재와 그 표면에 형성된 Pd 피복층을 갖는 반도체 장치용 본딩 와이어에 있어서, 175℃∼200℃의 HTS에서의 볼 접합부의 접합 신뢰성 향상과, 내력비(＝최대 내력/0.2％ 내력): 1.1∼1.6의 양립을 도모한다. 와이어 중에 Ni, Zn, Rh, In, Ir, Pt 중 1종 이상을 총계로 0.03∼2질량％ 함유함으로써 HTS에서의 볼 접합부의 접합 신뢰성을 향상시키고, 또한 본딩 와이어의 와이어 축에 수직 방향인 코어재 단면에 대해 결정 방위를 측정한 결과에 있어서, 와이어 길이 방향의 결정 방위 중, 와이어 길이 방향에 대해 각도 차가 15도 이하인 결정 방위 <100>의 방위 비율을 50％ 이상으로 하고, 본딩 와이어의 와이어 축에 수직 방향인 코어재 단면에 있어서의 평균 결정입경을 0.9∼1.3㎛로 함으로써, 내력비를 1.6 이하로 한다.

반도체 장치용 본딩 와이어

... 표면에 Pd 피복층을 갖는 Cu 본딩 와이어에 있어서, 고온 고습 환경에서의 볼 접합부의 접합 신뢰성을 개선하고, 차량 탑재용 디바이스에 적합한 본딩 와이어를 제공한다. Cu 합금 코어재와, 상기 Cu 합금 코어재의 표면에 형성된 Pd 피복층을 갖는 반도체 장치용 본딩 와이어에 있어서, 본딩 와이어가 In을 0.011∼1.2질량％ 포함하고, Pd 피복층의 두께가 0.015∼0.150㎛이다. 이에 의해, 고온 고습 환경하에서의 볼 접합부의 접합 수명을 향상시키고, 접합 신뢰성을 개선할 수 있다. Cu 합금 코어재가 Pt, Pd, Rh, Ni의 1종 이상을 각각 0.05∼1.2질량％ 함유하면, 175℃ 이상의 고온 환경에서의 볼 접합부 신뢰성을 향상시킬 수 있다. 또한, Pd 피복층의 표면에 Au 표피층을 더 형성하면 웨지 접합성이 개선된다.

Bonding wire for semiconductor device

Provided is a bonding wire for a semiconductor device, said bonding wire having a Cu alloy core and a Pd coating layer formed on the surface of the Cu alloy core, and being characterized by including an element that imparts connection reliability in a high-temperature environment, wherein the proof stress ratio, as defined by formula (1), is 1.1-1.6. (1) Proof stress ratio = maximum proof stress / 0.2% proof stress.

COPPER ALLOY BONDING WIRE FOR SEMICONDUCTOR DEVICES

COPPER ALLOY BONDING WIRE FOR SEMICONDUCTOR DEVICES In a copper alloy bonding wire for semiconductor devices, the bonding longevity of a ball bonded part under high-temperature and high-humidity environments is improved. 5 The copper alloy bonding wire for semiconductor devices includes in total 0.03% by mass or more to 3% by mass or less of at least one or more kinds of elements selected from Ni, Zn, Ga, Ge, Rh, In, Ir, and Pt (first element), with the balance Cu and inevitable impurities. The 10 inclusion of a predetermined amount of the first element suppresses production of an intermetallic compound susceptible to corrosion under high-temperature and high- humidity environments at the wire bonding interface and improves the bonding longevity of a ball bonded part. 15 ...

Bonddraht für Halbleitervorrichtung

Bonddraht für eine Halbleitervorrichtung, wobei der Bonddraht aufweist: ein Cu-Legierungskernmaterial; und eine Pd-Überzugschicht, die auf einer Oberfläche des Cu-Legierungskernmaterials ausgebildet ist, wobei der Bonddraht wenigstens ein Element enthält, das aus Ni, Zn, Rh, In, Ir und Pt ausgewählt ist, eine Konzentration der Elemente insgesamt relativ zu dem Gesamtdraht 0,03 Massen-% oder mehr und 2 Massen-% oder weniger beträgt, wenn Kristallorientierungen auf einem Querschnitt des Kernmaterials in einer Richtung senkrecht zu einer Drahtachse des Bonddrahts gemessen werden, eine Kristallorientierung <100> mit einem Winkel von 15 Grad oder weniger zu einer Drahtachsenrichtung einen Anteil von 50% oder mehr an Kristallorientierungen in der Drahtachsenrichtung hat, und eine mittlere Kristallkorngröße in dem Querschnitt des Kernmaterials in der Richtung senkrecht zu der Drahtachse des Bonddrahts 0,9 µm oder mehr und 1,3 µm oder weniger beträgt. Bond wire for a semiconductor device, the bond wire comprising: a Cu alloy core material; and a Pd plating layer formed on a surface of the Cu alloy core material, wherein the bonding wire contains at least one element selected from Ni, Zn, Rh, In, Ir and Pt, a total concentration of the elements relative to the total wire is 0.03 mass% or more and 2 mass% or less, when crystal orientations are measured on a cross section of the core material in a direction perpendicular to a wire axis of the bonding wire, a crystal orientation <100> at an angle of 15 degrees or less to a wire axis direction accounts for 50% or more of crystal orientations in the wire axis direction, and an average crystal grain size in the cross section of the core material in the direction perpendicular to the wire axis of the bonding wire is 0.9 µm or more and 1.3 µm or less.

반도체 장치용 본딩 와이어

Cu 합금 코어재의 표면에 Pd를 주성분으로 하는 피복층과, 해당 피복층의 표면에 Au와 Pd를 포함하는 표피 합금층을 갖는 반도체 장치용 본딩 와이어이며, Pd 도금 리드 프레임에서의 2nd 접합성을 더욱 개선함과 함께, 고습 가열 조건에 있어서도 우수한 볼 접합성을 실현할 수 있는 본딩 와이어를 제공한다. Cu 합금 코어재의 표면에 Pd를 주성분으로 하는 피복층과, 해당 피복층의 표면에 Au와 Pd를 포함하는 표피 합금층을 갖는 반도체 장치용 본딩 와이어에 있어서, 와이어 최표면에 있어서의 Cu 농도를 1 내지 10at%로 하고, 코어재 내에 원소 주기율표 제10족의 금속 원소를 총계로 0.1 내지 3.0질량%의 범위에서 함유함으로써, 2nd 접합성의 개선과, 고습 가열 조건에 있어서의 우수한 볼 접합성을 실현할 수 있다. 또한, 표피 합금층의 Au의 최대 농도가 15at% 내지 75at%이면 바람직하다.

Bonding wire for semiconductor devices

Provided is a Cu bonding wire having a Pd coating layer on the surface, which has improved bonding reliability at a ball joint in a high-temperature high-humidity environment, and which is suitable to devices for in-vehicle use. A bonding wire for semiconductor devices, which comprises a Cu alloy core material and a Pd coating layer that is formed on the surface of the Cu alloy core material, and wherein the bonding wire contains In in an amount of 0.011-1.2% by mass and the Pd coating layer has a thickness of 0.015-0.150 [mu]m. Consequently, the bonding life in a ball joint in a high-temperature high-humidity environment is improved, and the bonding reliability is able to be improved. If the Cu alloy core material contains one or more elements selected from among Pt, Pd, Rh and Ni respectively in an amount of 0.05-1.2% by mass, the ball joint reliability in a high temperature environment at 175 DEG C or more is able to be improved. In addition, if an Au superficial layer is additionally ...

Semiconductor chip having pads with plural junctions for different assembly methods

The present invention improves development efficiency and mass production efficiency of a semiconductor chip (LSI). The LSI on which an integrated circuit is formed has plural pad parts connecting the integrated circuit with an external circuit. The pad part is provided with the junction consisting of a window formed in the protective film and the pad exposing from the window, and the junction consisting of a window formed in the protective film and the bump deposited on the pad exposing from the window. When it is required the LSI is connected with an external circuit by wire bonding, the junction is connected with the external circuit through the wire, and when it is required to connect with an external circuit with the TAB method or the COG method, the junction is directly connected to the external circuit.

Halbleitervorrichtung

Eine Halbleitervorrichtung umfasst ein Halbleiterelement (1) mit einer unteren Fläche, die mit einer isolierenden Seite eines Substrats (4a) verbunden ist, und einen plattenförmigen Leiteranschluss (3a), der mit einer oberen Fläche des Halbleiterelements (1) verbunden ist und einen sich horizontal erstreckenden Bereich aufweist. Der sich horizontal erstreckende Bereich des Leiteranschlusses (3a) ist mit dem Halbleiterelement (1) verbunden und umfasst einen sich linear erstreckenden Bereich bei planarer Ansicht. Die Halbleitervorrichtung umfasst ferner ein abdichtendes Harz (5), das das Halbleiterelement (1) zusammen mit dem sich linear erstreckenden Bereich im Leiteranschluss (3a) abdichtet. Ein linearer Ausdehnungskoeffizient des abdichtenden Harzes (5) stellt einen Wert zwischen einem linearen Ausdehnungskoeffizienten des Leiteranschlusses (3a) und einem linearen Ausdehnungskoeffizienten des Halbleiterelements (1) dar, und der Leiteranschluss (3a) umfasst eine Aussparung (7b) oder einen ...

접착시트 및 반도체 장치의 제조 방법

... 본 발명의 접착시트는, (A)고분자량 성분과, (B1)연화점이 50℃ 미만인 열경화성 성분과, (B2)연화점이 50℃ 이상 100℃ 이하인 열경화성 성분과, (C)연화점이 100℃ 이하인 페놀 수지를 포함하는 수지 조성물로 이루어지고, 그 수지 조성물 100질량%를 기준으로 하여, 상기 (A)고분자량 성분을 11∼22질량%, 상기 (B1)연화점이 50℃ 미만인 열경화성 성분을 10∼20질량%, 상기 (B2)연화점이 50℃ 이상 100℃ 이하인 열경화성 성분을 10∼20질량%, 상기 (C)연화점이 100℃ 이하인 페놀 수지를 15∼30질량% 함유한다.

반도체 장치용 본딩 와이어

Cu 합금 코어재의 표면에 Pd를 주성분으로 하는 피복층과, 당해 피복층의 표면에 Au와 Pd를 포함하는 표피 합금층을 갖는 반도체 장치용 본딩 와이어이며, Pd 도금 리드 프레임에서의 2nd 접합성을 더 개선함과 함께, 고습 가열 조건에 있어서도 우수한 볼 접합성을 실현할 수 있는 본딩 와이어를 제공한다. Cu 합금 코어재의 표면에 Pd를 주성분으로 하는 피복층과, 당해 피복층의 표면에 Au와 Pd를 포함하는 표피 합금층을 갖는 반도체 장치용 본딩 와이어에 있어서, 와이어 최표면 Cu 농도를 1 내지 10at％로 하고, 코어재 중에 Pd, Pt의 한쪽 또는 양쪽을 총계로 0.1 내지 3.0질량％의 범위에서 함유함으로써, 2nd 접합성의 개선과, 고습 가열 조건에 있어서의 우수한 볼 접합성을 실현할 수 있다. 또한, 표피 합금층의 Au의 최대 농도가 15at％ 내지 75at％이면 바람직하다.

METHOD FOR EXCHANGING CAPILLARY

The present invention relates to a method for exchanging a capillary for wire bonding facilities including a holding unit to hold a capillary. The method comprises the following steps. A driving robot transfers a capillary replacement unit to wire bonding facilities in response to a replacement signal of a capillary transferred from the wire bonding facilities. The capillary replacement unit transferred to the wire bonding facilities separates the capillary corresponding to the replacement signal from the wire bonding facilities. Then, the capillary replacement unit installs a new capillary in the wire bonding facilities from which the capillary is separated. COPYRIGHT KIPO 2018 ...

Embedded wire bond wires

Apparatuses relating generally to a vertically integrated microelectronic package are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface. A first microelectronic device is coupled to the upper surface of the substrate. The first microelectronic device is a passive microelectronic device. First wire bond wires are coupled to and extend away from the upper surface of the substrate. Second wire bond wires are-coupled to and extend away from an upper surface of the first microelectronic device. The second wire bond wires are shorter than the first wire bond wires. A second microelectronic device is coupled to upper ends of the first wire bond wires and the second wire bond wires. The second microelectronic device is located above the first microelectronic device and at least partially overlaps the first microelectronic device.

Method and Apparatus for Integrating Current Sensors in a Power Semiconductor Module

An improved system for measuring current within a power semiconductor module is disclosed, where the system is integrated within the power module. The system includes a point field detector sensing a magnetic field resulting from current flowing in one phase of the module. A lead frame conductor may be provided to shape the magnetic field and minimize the influence of cross-coupled magnetic fields from currents conducted in other power semiconductor devices within one phase of the module. Optionally, a second point field detector may be provided at a second location within the module to sense a magnetic field resulting from the current flowing in the same phase of the module. Each phase of the power module includes at least one point field detector. A decoupling circuit is provided to decouple multiple currents flowing within the same phase or to decouple currents flowing within different phases of the power module.

ENCAPSULATION METHOD

A method for encapsulating a printed circuit board according to the present invention includes the steps of: wire-bonding a post part to correspond to an IO pattern formed on the printed circuit board; forming support parts on both sides of the post part by injecting a filler into a dispenser with a nozzle; and injecting the filler between the formed supporting parts. Accordingly, the present invention can prevent a pad from being damaged and reduce process costs. COPYRIGHT KIPO 2017 ...

Binding wire and semiconductor package structure using the same

The present invention relates to a semiconductor package structure. The semiconductor package structure includes a substrate, a pre-package structure, a shielding layer covered on the pre-package structure and a protective layer covered on the shielding layer. The substrate includes a number of conductive tracing wires. The pre-package structure includes a semiconductor chip and a number of the binding wires. The semiconductor chip includes a number of welding spots. The welding spots and the conductive tracing wires are electrically connected by the binding wires. The binding wires consists a number of carbon nanotube composite wires. The carbon nanotube composite wire includes a carbon nanotube yarn and a metal layer coated on the surface of the carbon nanotube yarn. The carbon nanotube yarn is formed by twisting a number of carbon nanotube around an axial direction of the carbon nanotube yarn. The present invention relates to an above binding wire.

Cu alloy core bonding wire with Pd coating for semiconductor device

A bonding wire for a semiconductor device includes a Cu alloy core material and a Pd coating layer formed on a surface thereof, and the boding wire contains one or more elements of As, Te, Sn, Sb, Bi and Se in a total amount of 0.1 to 100 ppm by mass. The bonding longevity of a ball bonded part can increase in a high-temperature and high-humidity environment, improving the bonding reliability. When the Cu alloy core material further contains one or more of Ni, Zn, Rh, In, Ir, Pt, Ga and Ge in an amount, for each, of 0.011 to 1.2% by mass, it is able to increase the reliability of a ball bonded part in a high-temperature environment of 170° C. or more. When an alloy skin layer containing Au and Pd is further formed on a surface of the Pd coating layer, wedge bondability improves.

Wiring substrate and semiconductor package

A wiring substrate for a semiconductor device includes a heat spreader; a polyimide layer provided with through holes and provided on the heat spreader via an adhesion layer; through wirings formed to fill the through holes of the polyimide layer; a thermal diffusion wiring provided on the polyimide layer and is configured not to be electrically connected to the semiconductor device; an electrical connection wiring provided on the polyimide layer at a same plane with the thermal diffusion wiring and is configured to be electrically connected to the semiconductor device; and an insulating layer provided on the polyimide layer with a first open portion and a second open portion that expose the electrical connection wiring and the thermal diffusion wiring, respectively, the thermal diffusion wiring being formed to extend at an outer side of the second open portion and have a larger area than the electrical connection wiring.

Copper alloy bonding wire for semiconductor device

Copper alloy bonding wire for semiconductor device

반도체 장치용 본딩 와이어

표면에 Pd 피복층을 갖는 Cu 본딩 와이어에 있어서, 고온 고습 환경에서의 볼 접합부의 접합 신뢰성을 개선하고, 차량 탑재용 디바이스에 적합한 본딩 와이어를 제공한다. Cu 합금 코어재와, 상기 Cu 합금 코어재의 표면에 형성된 Pd 피복층을 갖는 반도체 장치용 본딩 와이어에 있어서, 본딩 와이어가 In을 0.011∼1.2질량％ 포함하고, Pd 피복층의 두께가 0.015∼0.150㎛이다. 이에 의해, 고온 고습 환경하에서의 볼 접합부의 접합 수명을 향상시키고, 접합 신뢰성을 개선할 수 있다. Cu 합금 코어재가 Pt, Pd, Rh, Ni의 1종 이상을 각각 0.05∼1.2질량％ 함유하면, 175℃ 이상의 고온 환경에서의 볼 접합부 신뢰성을 향상시킬 수 있다. 또한, Pd 피복층의 표면에 Au 표피층을 더 형성하면 웨지 접합성이 개선된다. A Cu bonding wire having a Pd coating layer on its surface improves bonding reliability of a ball joint in a high temperature and high humidity environment and provides a bonding wire suitable for a vehicle mounting device. Cu alloy core material and a Pd coating layer formed on the surface of the Cu alloy core material, wherein the bonding wire contains 0.011 to 1.2 mass% of In and the thickness of the Pd coating layer is 0.015 to 0.150 占 퐉. This improves the bonding life of the ball joint in a high temperature and high humidity environment and improves bonding reliability. When the Cu alloy core material contains 0.05 to 1.2 mass% of at least one of Pt, Pd, Rh, and Ni, the reliability of the ball joint in a high temperature environment of 175 캜 or more can be improved. Further, when an Au skin layer is further formed on the surface of the Pd coating layer, the wedge bonding property is improved.

Cu ALLOY CORE BONDING WIRE WITH Pd COATING FOR SEMICONDUCTOR DEVICE

A bonding wire for a semiconductor device includes a Cu alloy core material and a Pd coating layer formed on a surface thereof, and the boding wire contains one or more elements of As, Te, Sn, Sb, Bi and Se in a total amount of 0.1 to 100 ppm by mass. The bonding longevity of a ball bonded part can increase in a high-temperature and high-humidity environment, improving the bonding reliability. When the Cu alloy core material further contains one or more of Ni, Zn, Rh, In, Ir, Pt, Ga and Ge in an amount, for each, of 0.011 to 1.2% by mass, it is able to increase the reliability of a ball bonded part in a high-temperature environment of 170° C. or more. When an alloy skin layer containing Au and Pd is further formed on a surface of the Pd coating layer, wedge bondability improves.

Adhesive sheet and method for manufacturing semiconductor device

The adhesive sheet of the invention comprises a resin composition containing (A) a high-molecular-weight component, (B1) a thermosetting component having a softening point of below 50° C., (B2) a thermosetting component having a softening point of between 50° C. and 100° C. and (C) a phenol resin having a softening point of no higher than 100° C., the composition containing 11 to 22 mass % of the (A) high-molecular-weight component, 10 to 20 mass % of the (B1) thermosetting component having a softening point of below 50° C., 10 to 20 mass % of the (B2) thermosetting component having a softening point of between 50° C. and 100° C. and 15 to 30 mass % of the phenol resin having a softening point of no higher than 100° C., based on 100 mass % of the resin composition.

Three-dimensional semiconductor memory device and electronic system including the same

Disclosed are three-dimensional semiconductor memory devices and electronic systems including the same. The three-dimensional semiconductor memory device comprises a first structure and a second structure in contact with the first structure. Each of the first and second structures includes a substrate, a peripheral circuit region on the substrate, and a cell array region including a stack structure on the peripheral circuit region, a plurality of vertical structures that penetrate the stack structure, and a common source region in contact with the vertical structures. The stack structure is between the peripheral circuit region and the common source region. The common source regions of the first and second structures are connected with each other.

Stacked die package including wire bonding and direct chip attachment, and related methods, devices and apparatuses

Systems, apparatuses, and methods using wire bonds and direct chip attachment (DCA) features in stacked die packages are described. A stacked die package includes a substrate and at least a first semiconductor die and a second semiconductor die that are vertically stacked above the substrate. An active surface of the first semiconductor die faces an upper surface of the substrate and the first semiconductor die is operably coupled to the substrate by direct chip attachment DCA features. A back side surface of the second semiconductor die faces a back side surface of the first semiconductor die. The second semiconductor die is operably coupled to the substrate by wire bonds extending between an active surface thereof and the upper surface of the substrate.

ANTENNA MODULE

An antenna module includes an antenna substrate including a glass substrate having first and second surfaces opposing each other, an antenna pattern disposed on the first surface, and a wiring structure connected to the antenna pattern and extending to the second surface, and a semiconductor package including a semiconductor chip, having an inactive surface and an active surface, on which a connection pad is disposed, an encapsulant encapsulating the semiconductor chip, a connection member including a redistribution layer connected to the connection pad, and a through-via penetrating the encapsulant and connecting the redistribution layer and the wiring structure to each other. 1. An antenna module comprising:an antenna substrate including a glass substrate having first and second surfaces opposing each other, an antenna pattern disposed on the first surface, and a wiring structure connected to the antenna pattern and extending to the second surface; anda semiconductor package including a semiconductor chip, having an active surface, on which a connection pad is disposed, and an inactive surface disposed on the second surface of the glass substrate and opposing the active surface, an encapsulant encapsulating the semiconductor chip, a connection member including a redistribution layer connected to the connection pad, and a through-via penetrating the encapsulant and connecting the redistribution layer and the wiring structure of the antenna substrate to each other.2. The antenna module of claim 1 , wherein the semiconductor package further includes a first bonding layer bonding the inactive surface of the semiconductor chip and the second surface of the glass substrate to each other.3. The antenna module of claim 1 , further comprising:at least one passive component disposed on the second surface of the glass substrate to be encapsulated by the encapsulant and connected to the redistribution layer.4. The antenna module of claim 3 , wherein the semiconductor package ...

MODULE ASSEMBLY

A module assembly includes an adapter substrate with at least one cavity and a surface mounted die mounted on a top surface of the adapter substrate. The first cavity extends through the adapter substrate and has at least one first side wall. A first metallization layer is provided within the cavity. A first recessed die is attached to the first metallization layer and mounted within the cavity such that the first recessed die is at least partially recessed into the first cavity and surrounded by a gap filler that resides between side portions of the first recessed die and the at least one first side wall. The top surface of the gap filler is flush with the top surface of the adapter substrate and a top surface of the first recessed die. 1. A method comprising:providing an adapter substrate having a backside surface and a top surface opposite the backside surface;forming a first cavity that extends partially into the adapter substrate from the top surface, the first cavity having a first bottom surface and at least one first side wall;forming a first metallization layer on the first bottom surface of the first cavity;attaching a first recessed die to the first metallization layer such that the first recessed die is at least partially recessed into the first cavity, wherein a gap is formed between side portions of the first recessed die and the at least one first side wall;filling the gap with a gap filler such that a top surface of the gap filler is flush with the top surface of the adapter substrate and a top surface of the first recessed die;thinning the adapter substrate from the backside surface of the adapter substrate; andattaching a surface mounted die to the top surface of the adapter substrate.2. The method of further comprising:forming interconnects on the backside surface of the adapter substrate; andconnecting the adapter substrate to a top surface of a packaging substrate using the interconnects.3. The method of further comprising:forming partial vias ...

Methods of manufacturing light-emitting devices with metal inlays and bottom contacts

Methods of manufacturing light-emitting devices are described herein. A method includes obtaining a packaging substrate. The packaging substrate includes an embedded metal inlay, vias in the packaging substrate and contacts on a bottom surface of the packaging substrate, each electrically coupled to a respective one of the vias. The method also includes forming a hybridized device, attaching a bottom surface of the hybridized device to a top surface of the metal inlay, and wirebonding a top surface of the hybridized device to a stop surface of the packaging substrate using a plurality of conductive connectors.

OPTOELECTRONIC COMPONENT AND METHOD OF PRODUCING AN OPTOELECTRONIC COMPONENT

An optoelectronic component includes a semiconductor chip, the semiconductor chip emitting infrared radiation; a reflector that reflects the infrared radiation of the semiconductor chip; and a filter configured in the form of a coating, the filter being transparent for the infrared radiation of the semiconductor chip, wherein visible light striking the optoelectronic component being absorbed to at least %. 113-. (canceled)14. An optoelectronic component comprising:a semiconductor chip, the semiconductor chip emitting infrared radiation;a reflector that reflects the infrared radiation of the semiconductor chip; anda filter configured in the form of a coating, the filter being transparent for the infrared radiation of the semiconductor chip,wherein visible light striking the optoelectronic component being absorbed to at least 75%.15. The optoelectronic component as claimed in claim 14 , wherein the thickness of the filter is at most 50 μm.16. The optoelectronic component as claimed in claim 14 , wherein at least 90% of the infrared radiation emitted by the semiconductor chip passes through the filter.17. The optoelectronic component as claimed in claim 14 , wherein the filter comprises a matrix material with colorant.18. The optoelectronic component as claimed in claim 17 , wherein the matrix material comprises an epoxy resin claim 17 , silicone claim 17 , plastic or lacquer.19. The optoelectronic component as claimed in claim 14 , wherein the reflector is coated with silver or aluminum.20. The optoelectronic component as claimed in claim 14 , wherein the reflector is coated with gold.21. The optoelectronic component as claimed in claim 20 , wherein a combined system consisting of the filter and the gold coating of the reflector absorbs visible light striking the optoelectronic component to at least 75%.22. The optoelectronic component as claimed in claim 14 , wherein the semiconductor chip is covered with the filter.23. The optoelectronic component as claimed in ...

Binding wire and semiconductor package structure using the same

A semiconductor package structure includes a substrate, and a package preform. The substrate includes a plurality of conductive tracing wires. The package preform includes a semiconductor chip and a plurality of binding wires. The semiconductor chip includes a plurality of welding spots, and the welding spots are electrically connected with corresponding conductive tracing wires by the binding wires. Each binding wire comprises a carbon nanotube composite wire, the carbon nanotube composite wire includes a carbon nanotube wire and a metal layer. The carbon nanotube wire consists of a plurality of carbon nanotubes spirally arranged along an axial direction an axial direction of the carbon nanotube wire.

Semiconductor package structure

본 발명은 반도체패키지 구조에 관한 것이다. The present invention relates to a semiconductor package structure. 통상 구리재질의 반도체칩탑재부재를 몰드컴파운드(5)의 외부로 노출시켜 반도체패키지를 제조함에 있어서는 성형과정에서 반도체칩탑재부재인 반도체칩탑재판(1) 또는 히트싱크(2)의 가장자리에 플래시(4)가 묻게 되므로 이를 제저하기 위한 플래시제거공정을 수행해야 하는데 이 반도체칩탑재부재에서 구리재질과 친화력이 있은 플래시(40)를 제거하는데에 상당한 노력과 시간이 제공되고 자칫 반도체패키지를 손상시키게 되는 등의 문제점이 있었다. In manufacturing a semiconductor package by exposing a semiconductor chip mounting member made of a copper material to the outside of the mold compound 5, a flash is formed at the edge of the semiconductor chip mounting plate 1 or the heat sink 2, which is a semiconductor chip mounting member, during the molding process. (4) is asked, so a flash removal process must be performed to remove this, and considerable effort and time are required to remove the flash 40 having affinity with copper material from the semiconductor chip mounting member, and it may cause damage to the semiconductor package. There was a problem such as being. 이에, 본 발명에서는 몰드컴파운드(5)와 은(Ag)이 서로 접착력이 미약하다는 점에 착안하여 몰드컴파운드(5)의 외부로 노출되는 반도체칩탑재부재의 저면 가장자리에 은도금층(10) 처리를 하여 플래시(4)의 접착력을 약화시킴으로써 후공정에서의 플래시(4)의 제거가 용이하게 이루어질 수 있도록 한 것이다. Accordingly, in the present invention, the silver plating layer 10 treatment is applied to the bottom edge of the semiconductor chip mounting member exposed to the outside of the mold compound 5 in consideration of the weak adhesion between the mold compound 5 and silver Ag. By weakening the adhesive force of the flash (4) so that the removal of the flash (4) in a later step can be made easily.

Lead frame of inner lead stack

본 고안은 반도체패키지를 제작함에 있어서, 특히 핀수의 확장에 한계가 있는 플라스틱패키지의 핀수를 확장시켜 집적밀도를 향상시키기 위한 적층 내부리드 리드프레임에 관한 것으로, 일반적인 단층 구조의 리드프레임에서는 내부리드(3)가 본딩패드(5) 위에 어태치되는 칩에 연결될 수 있는 단자가 한정되어 있어 집적밀도면에 있어서 널리 활용할 수 없게 되는 문제점이 발생하는데, 본 고안은 와이어가 연결되는 내부리드의 구조를 적층하여 형성하면서 상층(20)과 하층(10)의 댐바(4, 14) 구조도 동일한 위치에 있도록 하여 외부리드의 수를 확장시킴을 특징으로 하는 리드프레임을 제공함으로써 외부리드의 수를 배 이상으로 확장시킬 수 있게 되어 집적밀도를 향상시킬 수 있다. The present invention relates to a laminated internal lead leadframe for improving the integration density by expanding the pin count of a plastic package, which is limited in the expansion of the number of pins, in the manufacture of a semiconductor package. 3) is limited to the terminal that can be connected to the chip attached on the bonding pad (5) has a problem that can not be widely used in terms of integration density, the present invention is laminated the structure of the inner lead to which the wire is connected The lead bar is characterized by extending the number of external leads by forming the dam bars 4 and 14 of the upper layer 20 and the lower layer 10 at the same position, thereby doubling the number of external leads by more than twice. Can be expanded to improve the integration density.

Lead frame

본 고안은 반도체 칩이 안착되는 패들의 가장자리에 형성된 이너리드의 단부에 테이프를 부착시켜 상기 이너리드를 고정시킨 후, 반도체 칩과 이너리드가 와이어본딩되는 리드프레임에 관한 것이다. The present invention relates to a lead frame in which the semiconductor chip and the inner lead are wire-bonded after fixing the inner lead by attaching a tape to an end of the inner lead formed at the edge of the paddle on which the semiconductor chip is seated. 따라서, 본 고안의 리드프레임을 통하여 이너리드와 본딩되는 와이어의 길이가 종래보다 짧아지므로 본딩된 와이어의 휨을 방지할 수 있다. Therefore, since the length of the wire bonded with the inner lead through the lead frame of the present invention is shorter than before, the bending of the bonded wire can be prevented. 또한, 반도체 칩과 창을 통한 본딩이 이루어지므로 본딩 불량을 줄일 수 있다. In addition, since bonding is performed through the semiconductor chip and the window, bonding failure may be reduced.

Semiconductor Package and Manufacturing Method

이 발명은 반도체패키지 및 그 제조 방법에 관한 것으로, 비교적 넓은 히트스프레더상에 다수의 반도체칩을 접착한 채 나머지 제조 공정을 실시함으로써 반도체칩의 손상을 방지하고, 제조 공정중 자재 취급이 용이하며, 뛰어난 방열 효과를 얻기 위해, 상면에 다수의 입출력패드가 형성된 반도체칩과; 상기 반도체칩의 저면에 그 반도체칩의 저면 넓이보다 넓은 평판형으로서, 접착제가 개재되어 접착된 히트스프레더와; 상기 반도체칩의 상면에 접착된 접착제와; 상기 접착제 상면에 폴리이미드층이 접착되고, 상기 폴리이미드층상에는 본드핑거, 연결부 및 솔더볼랜드의 회로패턴이 형성되어 있으며, 상기 본드핑거 및 솔더볼랜드를 제외한 상면이 커버코오트로 코팅되어 이루어진 회로기판시트와; 상기 반도체칩의 입출력패드와 회로기판시트의 본드핑거를 연결하는 도전성와이어와; 상기 반도체칩의 입출력패드, 도전성와이어 및 회로기판시트의 본드핑거 등을 외부 환경으로부터 보호하기 위해 그 상면에 봉지된 봉지재와; 상기 회로기판시트의 솔더볼랜드에 융착되어 반도체칩의 신호를 외부로 입출력하는 솔더볼을 포함하여 이루어진 것을 특징으로 함. The present invention relates to a semiconductor package and a method of manufacturing the same, and to attaching a plurality of semiconductor chips on a relatively wide heat spreader and performing the rest of the manufacturing process to prevent damage to the semiconductor chip, easy handling of materials during the manufacturing process, A semiconductor chip having a plurality of input / output pads formed on an upper surface thereof in order to obtain an excellent heat dissipation effect; A heat spreader on the bottom of the semiconductor chip, the plate being wider than the bottom of the semiconductor chip, the adhesive being interposed with an adhesive; An adhesive bonded to an upper surface of the semiconductor chip; The polyimide layer is bonded to the upper surface of the adhesive, the circuit pattern of the bond finger, the connecting portion and the solder borland is formed on the polyimide layer, the circuit board sheet is coated on the top surface except for the bond finger and solder borland Wow; Conductive wires connecting the input / output pads of the semiconductor chip and the bond fingers of the circuit board sheets; An encapsulant encapsulated on an upper surface of the semiconductor chip to protect the input / output pad, the conductive wire, the bond finger of the circuit board sheet, and the like from an external environment; It is characterized in that it comprises a solder ball fused to the ...

Semiconductor package

Stacked inner lead lead frame

Semiconductor device for wire bonding

본 고안은 반도체 장치에 있어서, 와이어 본딩중 버스바와 내부리드의 단락에 의한 쇼트를 방지하기 위한 것으로, 버스바를 내부리드 상단에 형성한 상태에서 먼저 칩의 본딩패드와 내부리드를 연결하고, 이후 내부리드와 버스바를 연결하는 2단계루프와, 본딩패드와 버스바를 연결하는 직접연결루프를 병행하여 구성하며, 제작 순서는 버스바가 없는 상태로 리드프레임을 형성하고, 테이프를 이용하여 리드프레임상에 절연막을 형성한 다음 그 위로 버스바를 접착하여 이루어짐을 특징으로 하는 와이어 본딩이 용이한 반도체 장치에 관한것이다. The present invention is to prevent a short circuit caused by short-circuit of the busbar and the inner lead in the wire bonding, and first connecting the bonding pad and the inner lead of the chip in the state where the busbar is formed on the upper end of the inner lead, A two-stage loop for connecting leads and busbars and a direct connection loop for connecting the bonding pads and the busbars are configured in parallel.The fabrication procedure is performed by forming a leadframe without the busbars, and insulating film on the leadframe using tape. It relates to a semiconductor device that is easy to wire bonding, characterized in that formed by forming a and then bonding the bus bar thereon.

Unit for stacking type semiconductor package and semiconductor package

본 발명에 따르면, 반도체 칩; 상기 반도체 칩이 부착되는 패드와, 다른 부분보다 두께가 두껍게 형성된 랜드와, 각 리이드가 절곡되어 연장되는 절곡부를 가지는 리이드 프레임; 상기 반도체 칩의 전극과 상기 리이드 프레임의 리이드 각각을 연결하는 와이어; 상기 반도체 칩과 와이어를 감싸며, 상기 패드 및, 상기 랜드의 저면이 외부로 노출되고 상기 각 리이드의 절곡부가 그 측부 및, 상부 표면을 따라 연장하도록 형성된 엔캡슐레이션;을 구비하는 적층형 반도체 팩키지의 유니트가 제공된다.

Stacked semiconductor package

Multilayer pad of semiconductor device and its manufacturing method

본 발명에 의한 반도체 소자의 다층 패드 및 그 제조방법에 관한 것이다. 본 발명에 의한 상기 다층 패드는 반도체 기판 상의 소정 부분에 형성된 하부 도전성 패드와, 상기 하부 도전성 패드를 포함한 상기 기판 상에 형성되며, 상기 하부 도전성 패드의 표면이 소정 부분 노출되도록 와이드 비어 홀이 구비된 층간 절연막 및 도전성막을 사이에 두고 상기 하부 도전성 패드와 연결되도록 와이드 비어 홀을 포함한 상기 층간 절연막 상의 소정 부분에 형성된 상부 도전성 패드로 이루어진다. 본 발명에 의하면, 상부 도전성 패드 자체의 두께가 그 하부에 형성된 도전성막의 두께 만큼 더 두꺼워진 효과를 얻을 수 있게 되므로, 웨이퍼 프로빙시 또는 와이어 본딩시에 도전성 패드에 스트레스가 가해지더라도 도전성 패드에 크랙이 발생하는 것을 막을 수 있게 된다. The present invention relates to a multilayer pad of a semiconductor device and a method of manufacturing the same. The multilayer pad according to the present invention includes a lower conductive pad formed on a predetermined portion on a semiconductor substrate and a substrate formed on the substrate including the lower conductive pad, and provided with a wide via hole to expose a predetermined portion of the surface of the lower conductive pad. And an upper conductive pad formed on a predetermined portion on the interlayer insulating film including a wide via hole so as to be connected to the lower conductive pad with an interlayer insulating film and a conductive film interposed therebetween. According to the present invention, since the thickness of the upper conductive pad itself is thicker than the thickness of the conductive film formed below, the conductive pad may be cracked even if stress is applied to the conductive pad during wafer probing or wire bonding. This can be prevented from occurring.

Semiconductor device

본 고안은 반도체 장치에 관한 것으로, 리드 온 칩(Lead On Chip: LOC)형 패케이지(Package)를 갖는 반도체 장치에서 리드 프레임에 형성된 버스 바(Bus Bar)로 인한 와이어 간의 접촉을 방지하기 위하여 공통으로 연결되는 본딩 패드(Bonding Pad)를 패턴 와이어(Pattern Wire)를 사용하여 연결하므로써 소자의 수율을 향상시킬 수 있도록 한 반도체 장치에 관한 것이다. The present invention relates to a semiconductor device, and in order to prevent contact between wires due to a bus bar formed in a lead frame in a semiconductor device having a lead on chip (LOC) type package. The present invention relates to a semiconductor device capable of improving device yield by connecting bonding pads connected to each other using a pattern wire.

Semiconductor package

Board, manufacturing method thereof, wire-bonding package using the same, and manufacturing method thereof

본 발명은 2 래이어로 구성된 기판과 와이어 본딩 패키지 및 그 제조 방법을 제공하는 것을 그 목적으로 한다. 이러한 목적을 달성하기 위하여 본 발명의 기판은, 절연판의 상면과 하면에 형성된 2개의 구리층들, 상기 절연판과 상기 2개의 구리층들을 관통하는 비어홀, 및 상기 비어홀에 형성된 도전물질에 의해 상기 구리층들이 상호 전기적으로 연결된 코어 기판; 및 두께를 증대시키기 위해 상기 코어 기판의 일면에 부착된 보강판을 구비한 기판을 제공한다. It is an object of the present invention to provide a substrate composed of two lathes, a wire bonding package, and a method of manufacturing the same. In order to achieve the above object, the present invention provides a substrate, comprising: two copper layers formed on an upper surface and a lower surface of an insulating plate; a via hole penetrating the insulating plate and the two copper layers; A core substrate electrically connected to each other; And a reinforcing plate attached to one surface of the core substrate to increase the thickness.

Stepped package

Semiconductor package and method for manufacturing the same

본 발명은 리드 프레임 기판, 상기 리드 프레임 기판 상에 탑재되는 적어도 하나 이상의 반도체 칩, 상기 반도체 칩을 밀봉하는 제1밀봉층, 및 상기 제1밀봉층 상부에 형성되며, 전자파 차폐 물질을 포함하는 에폭시 수지 조성물에 의해 형성되는 제2밀봉층을 포함하는 반도체 패키지 및 그 제조 방법에 관한 것이다.

Semiconductor package

본 고안은 반도체 패키지에 관한 것으로, 종래의 패들이 있는 리드프레임으로 이루어진 컨벤셔널 패키지에서는 그 형상이 엘오시(Lead On Chip)형 패키지와 달라 통상적인 컨벤셔널 패키지용 금형을 이용하여 엘오시형 패키지를 제조할 수 없다는 문제점이 있었던 바, 본 고안에서는 패들의 저면에 부착되는 반도체 칩과, 그 반도체 칩보다 높게 배치되는 리드프레임과, 그 리드프레임과 반도체 칩에 양단이 각각 본딩되는 와이어와, 그 와이어의 본딩상태를 보호하기 위하여 반도체 칩의 상, 하부가 동일한 두께로 몰딩되는 봉지부로 구성함으로써, 통상적인 엘오시형 금형으로도 컨벤셔널 패키지를 제조할 수 있도록 하여 생산원가를 절감할 수 있는 효과가 있다. The present invention relates to a semiconductor package, and in a conventional package consisting of a lead frame with a conventional paddle, its shape is different from that of a lead-on-chip package, using an mold for a conventional convention package. In the present invention, there is a problem in that the semiconductor chip is attached to the bottom of the paddle, a lead frame disposed higher than the semiconductor chip, wires bonded at both ends of the lead frame and the semiconductor chip, and In order to protect the bonding state of the wire, the upper and lower parts of the semiconductor chip are molded with the same thickness, so that the conventional package can be manufactured even with an ordinary mold. There is.

Stacked Semiconductor Package

본 발명은 몸체부의 외각틀을 수직 구조의 지지부재를 이용하여 구현한 적층형 반도체 패키지를 개시한다. 본 발명의 반도체 패키지는, 기판의 전면과 배면에 밑면이 서로 대향하게 부착되고, 상부에는 다수의 본딩 패드들을 갖는 한 쌍의 반도체 칩; 상기 기판의 양단이 안치되는 저부와 상기 저부와 연결되어, 상기 저부와 수직한 측부를 갖는 한쌍의 지지부재; 상기 기판과 상기 지지부재의 사이에 개재되어, 상기 기판의 외측으로 소정 부분 노출되어 상기 기판의 배면의 소정 위치까지 연장되고, 상기 기판과 상기 지지부재의 저부 사이를 통하여 상기 지지부재의 저부의 밑면까지 연장된 다수의 리드들; 상기 한 쌍의 반도체 칩의 본딩 패드들과 상기 리드들을 각각 전기적으로 연결되는 다수의 배선들; 및 상기 한쌍의 지지부재 사이의 반도체 칩, 기판, 배선, 및 리드를 덮어서 매립하는 캡슐층을 포함한다. The present invention discloses a stacked semiconductor package in which an outer frame of a body part is implemented using a supporting member having a vertical structure. A semiconductor package according to the present invention includes a pair of semiconductor chips having bottom surfaces facing each other on a front surface and a back surface of a substrate, and having a plurality of bonding pads thereon; A pair of supporting members connected to the bottom and the bottom of which both ends of the substrate are placed, and having a side portion perpendicular to the bottom; Interposed between the substrate and the support member, the substrate is partially exposed to the outside of the substrate and extends to a predetermined position on the rear surface of the substrate, and is formed on the bottom surface of the bottom of the support member through between the substrate and the bottom of the support member; A plurality of leads extending to; A plurality of wires electrically connected to the bonding pads and the leads of the pair of semiconductor chips, respectively; And a capsule layer covering and embedding the semiconductor chip, the substrate, the wiring, and the lead between the pair of supporting members.

Bonding wire for semiconductor package and semiconductor package including the same

본 발명의 실시예에 따른 반도체 패키지용 본딩 와이어는, 은을 포함하는 코어부, 2nm 내지 23nm 두께로 상기 코어부를 둘러싸며, 금을 포함하는 쉘층을 포함한다. 본 발명의 실시예에 따른 반도체 패키지는, 제1 및 제2 전극구조를 가지는 패키지 본체, 상기 제1 및 제2 전극구조와 각각 전기적으로 연결되는 제1 및 제2 전극부를 포함하는 반도체 소자, 및 상기 제1 및 제2 전극구조 중 적어도 하나와 상기 반도체 소자를 연결하는 본딩 와이어를 포함한다.

Transformer in enclosure substrate

Transformateur dans un substrat de boitier La présente description concerne un dispositif comprenant au moins une puce (94, 112) dans un boitier, le boitier comprenant un support (72), sur lequel repose la au moins une puce (94, 112), et une couche de protection (134) recouvrant la au moins une puce, le support comprenant par un empilement de couches en un matériau isolant, un transformateur (35) étant formé dans le support (72) par des premières (78) et deuxièmes (84) pistes conductrices. Figure pour l'abrégé : Fig. 3A Transformer in package substrate The present description relates to a device comprising at least one chip (94, 112) in a package, the package comprising a support (72), on which the at least one chip (94, 112) rests, and a protective layer (134) covering the at least one chip, the support comprising, by a stack of layers made of an insulating material, a transformer (35) being formed in the support (72) by first (78) and second (84 ) conductive tracks. Figure for the abstract: Fig. 3A

Semiconductor package lead frame

본 고안은 반도체 패키지용 리드 프레임에 관한 것으로, 양측 사이드 레일의 중간부에 반도체 칩이 부착되는 패들이 타이 바에 의하여 지지되고, 상기 패들의 주변에는 반도체 칩에 와이어 본딩되는 다수개의 인너 리드가 방사상으로 배치되며 이 인너 리드에 연장하여 기판에 접속되는 아웃 리드가 배치되어 이루어지는 반도체 패키지용 리드 프레임에 있어서, 상기 아웃 리드의 중간부에 그 길이 방향을 따라 소정의 홈을 형성하고, 이 홈에 골드 와이어와의 본딩을 위한 제2의 금속체를 충진하여 전기 전도성 및 열전도성을 개선시킬 수 있도록 한 것이다. 상기 홈은 상부가 트인 원형, 반원형 또는 브이형으로 형성되며, 이 홈에 충진되는 금속제는 금, 은 또는 구리 등과 같은 것이 사용된다. 이러한 본 고안에 의하면, 아웃 리드의 홈에 충진된 전도성이 우수한 금속체에 골드 와이어의 일단부가 본딩되므로 패키지의 전기 전도성 및 열 전도성을 개선할 수 있어 고용량 칩의 패키지를 제조할 수 있다. 또한 본 고안의 리드 홈에 금이나 은 같은 전도성 물질을 충진하여 구성할 경우 별도의 실버 플래팅 공정을 할 필요가 없어 공정의 단순화를 기할 수 있다. The present invention relates to a lead frame for a semiconductor package, in which paddles in which semiconductor chips are attached to middle portions of both side rails are supported by tie bars, and a plurality of inner leads wire-bonded to the semiconductor chips are radially around the paddles. A lead frame for a semiconductor package, the lead frame of which is arranged and extends to the inner lead and connected to the substrate, wherein a predetermined groove is formed in the middle portion of the out lead along the longitudinal direction, and the gold wire is formed in the groove. By filling a second metal body for bonding with and to improve the electrical conductivity and thermal conductivity. The groove is formed in a circular, semicircular or v-shaped top, and the metal filled in the groove is used such as gold, silver or copper. According to the present invention, since one end of the gold wire is bonded to a metal having excellent conductivity filled in the groove of the out lead, the electrical conductivity and the thermal conductivity of the package can be improved, thereby manufacturing a package of a high capacity chip. In addition, when the lead groove of the present invention is filled with a conductive material such as gold or silver, there is no need for a separate silver plating process, thereby simplifying the process.

Semiconductor device

Led module, led panel and led screen

FIELD: lighting engineering.SUBSTANCE: present invention relates to the field of LED displays. Proposed are the LED module, LED panel and LED screen. LED module contains a composite layer, at least one set of LED chips, at least one driver integrated circuit (IC); while the specified composite layer contains a substrate located on the front side; LED chip and driver integrated circuit are installed on the front side of the composite layer, the cathode of the LED chip is connected to the driver integrated circuit with a glued gold wire, and many blind holes are made on the front side of the composite layer. Anode of the LED chip is connected to the positive electrode inside the composite layer through one of the blind holes. Wire from the VDD stem of the driver integrated circuit is connected to the positive electrode inside the composite layer through at least one of the blind holes. Wire coming from the GND leg of the driver integrated circuit is connected to the negative electrode inside the composite layer through one of the blind holes. At least one driver integrated circuit is connected to other driver integrated circuits via a signal line.EFFECT: invention provides the ability to significantly reduce the complexity of the circuit pattern on the layer, the LED chip and the driver integrated circuit can be installed in the specified composite layer with high density, thus providing LED screen with perfect display, and since the dimensions of the unpackaged LED chip and unpackaged driver integrated circuit are extremely small and almost imperceptible to the human eye, the creation of a LED screen with high transparency is ensured.18 cl, 9 dwg РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) (13) 2 680 257 C1 (51) МПК H01L 23/498 (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ОПИСАНИЕ ИЗОБРЕТЕНИЯ К ПАТЕНТУ (52) СПК H01L 23/498 (2018.08) (21)(22) Заявка: 2018104444, 09.09.2016 (24) Дата начала отсчета срока действия патента: (73) Патентообладатель(и): ЛИНЬ И ...

Semiconductor Ball Grid Array Package

본 고안은 반도체 볼 그리드 어레이 패키지에 관한 것으로, 본 고안은 서브스트레이트와, 상기 서브스트레이트에 서브스트레이트보다 작은 크기로 부착되며 열방출을 촉진시키기 위해 금속재로 된 히트 싱크와, 상기 히트 싱크에 열전도성 및 절연성을 갖는 접착제에 의해 부착되어 칩패드와 서브스트레이트의 회로선 사이에 금속 와이어로서 전기적으로 연결되는 반도체 칩과, 상기 서브스트레이트의 양면에 부착되는 전기적인 연결 단자인 복수개의 솔더 볼을 포함하여 구성된 것을 그 특징으로 한다. 따라서, 볼 그리드 어레이 패키지의 양면을 인쇄 회로기판에 실장시킬수 있을 뿐만 아니라, 패키지가 실장된 상태에서도 패키지의 불량 상태 및 전기적인 특성을 용이하게 테스트할수 있게 된다.

Bonding wires for semiconductor devices

Ｃｕ合金芯材と、前記Ｃｕ合金芯材の表面に形成されたＰｄ被覆層とを有する半導体装置用ボンディングワイヤにおいて、前記ボンディングワイヤが高温環境下における接続信頼性を付与する元素を含み、下記（１）式で定義する耐力比が１．１〜１．６であることを特徴とする。耐力比＝最大耐力／０．２％耐力 （１） In a bonding wire for a semiconductor device having a Cu alloy core material and a Pd coating layer formed on the surface of the Cu alloy core material, the bonding wire contains an element that provides connection reliability in a high temperature environment, 1) The yield strength ratio defined by the formula is 1.1 to 1.6. Strength ratio = Maximum strength / 0.2% strength (1)

Adhesive sheet and the manufacture method of semiconductor device

本发明的粘接片材由包含(A)高分子量成分、(B1)软化点低于50℃的热固化性成分、(B2)软化点为50℃以上且100℃以下的热固化性成分、和(C)软化点为100℃以下的酚醛树脂的树脂组合物形成，并且以该树脂组合物100质量％为基准，含有11～22质量％的上述(A)高分子量成分、10～20质量％的上述(B1)软化点低于50℃的热固化性成分、10～20质量％的上述(B2)软化点为50℃以上且100℃以下的热固化性成分、15～30质量％的上述(C)软化点为100℃以下的酚醛树脂。

Stack-module type chip size package

본 고안은 스택 모듈형 칩 사이즈 패키지를 개시한다. 개시된 본 고안은, 패드가 하부를 향하게 배치된 반도체 칩; 인너 리드가 상기 반도체 칩의 하부에 배치되고, 상기 인너 리드로부터 반도체 칩의 양측면을 따라 상부로 연장된 아웃 리드는 그의 단부가 반도체 칩의 표면보다 높은 위치에서 표면과 평행하게 절곡된 리드 프레임; 상기 리드 프레임의 인너 리드와 반도체 칩의 패드를 전기적으로 연결하는 접속 수단; 및 상기 반도체 칩의 표면과 인너 리드의 밑면 및 아우터 리드의 단부가 노출되도록 전체를 몰디하는 봉지제를 포함하고, 상기된 인너 및 아웃 리드 구조를 갖는 리드 프레임으로 이루어진 수 개의 칩 사이즈 패키지가 봉지제에서 하부로 노출된 인너 리드 부분과 상부로 노출된 아우터 리드의 단부들이 서로 접속되도록 적층되어 이루어진 것을 특징으로 한다. The present invention discloses a stack modular chip size package. Disclosed is a semiconductor chip in which a pad is disposed downward; An inner lead disposed below the semiconductor chip, the out lead extending upward from the inner lead along both sides of the semiconductor chip, the lead frame being bent parallel to the surface at a position whose end is higher than the surface of the semiconductor chip; Connection means for electrically connecting the inner lead of the lead frame and the pad of the semiconductor chip; And an encapsulant, which encapsulates the entire surface such that the surface of the semiconductor chip, the bottom surface of the inner lead, and the end of the outer lead are exposed, and a plurality of chip size packages including the lead frame having the inner and out lead structures are encapsulant. The inner lead portion exposed to the lower portion and the ends of the outer lead exposed to the upper portion is characterized in that the stack is made so as to be connected to each other.

Thin system-in-package

【課題】パッケージ構造にプリント基板を有さないことで、大幅にコスト全体の削減を達成する薄型システム・イン・パッケージを提供する。【解決手段】薄型システム・イン・パッケージにおいて、プリント基板を有さず、銅基板１０の頂上面１３に複数のダイ２０を有する。ダイ２０と銅基板１０の複数の情報接続ピン１１が電気的に接続し、さらに、頂上面の受動素子４０とダイ２０が電気的に接続して、ダイ２０が銅基板１０の接地ピン１２に電気的に接続する。ダイ２０及び受動素子４０は、絶縁粘着剤５２を介して銅基板１０の頂上面１３に固定されて、最後に成形コンパウンド５０によって、銅基板１０の頂上面１３のダイ２０及び受動素子４０が封止される。【選択図】図１ A thin system-in-package that achieves significant overall cost savings by not having a printed circuit board in the package structure. A thin system-in-package has no printed circuit board and has a plurality of dies on a top surface of a copper substrate. The die 20 and the plurality of information connection pins 11 of the copper substrate 10 are electrically connected, and the passive element 40 on the top surface and the die 20 are electrically connected, and the die 20 is connected to the ground pins 12 of the copper substrate 10. Connect electrically. The die 20 and passive devices 40 are secured to the top surface 13 of the copper substrate 10 via an insulating adhesive 52 , and finally the molding compound 50 encapsulates the die 20 and passive devices 40 on the top surface 13 of the copper substrate 10 . be stopped. [Selection drawing] Fig. 1

Substrate and method of manufacturing semiconductor device

Wire joining structure, bonding wire used in same, and semiconductor device

In the present invention, the reliability of joining between a bonding wire for which the cost of materials was suppressed and an electrode is maintained over an extended period of time even in a harsh environment while increases in resistivity are suppressed despite joining of the bonding wire and the electrode. This wire joining structure 1 has an aluminum-containing electrode 2, a bonding wire 3, and a ball compression part 6 joined to the electrode 2. The bonding wire 3 has a core material 4 having silver as a main component, and a coating layer 5 having gold as a main component. The bonding wire 3 contains at least one group-15 or -16 element selected from sulfur, tellurium, selenium, arsenic, and antimony. With respect to the entirety of the wire, the gold concentration is 2.0-7.0 mass% inclusive, and the group-15 or -16 element concentration is 4-80 mass ppm inclusive in total. A gold-concentrated joining region in which the gold concentration reaches or exceeds 5.0 at% with respect to the total of aluminum, silver, and gold is present near the joining interface of the electrode 2 and the ball compression part 6.

manufacturing method of semiconductor package and its semiconductor package

이 발명은 반도체패키지의 제조 방법 및 그 반도체패키지에 관한 것으로, 패키지 워페이지(package warpage), 총두께 제어(total thickness control) 및 마스킹 결함(masking defect)을 해결하여 신뢰성을 향상시킬 수 있도록, 중앙에 상,하 방향으로 캐비티가 관통되어 형성된 회로기판을 제공하는 단계와, 상기 캐비티 내측의 상부에 반도체 다이를 접착시키는 단계와, 상기 반도체 다이와 회로기판을 도전성 와이어로 상호 연결하는 단계와, 상기 반도체 다이, 도전성 와이어 및 캐비티를 봉지재로 덮어 봉지부를 형성하는 단계와, 상기 회로기판의 타면에 다수의 솔더볼을 융착하는 단계와, 상기 회로기판의 상면에 잉크층을 갖는 필름을 접착시키고, 상기 필름을 지그로 압착한 상태에서, 상기 반도체 다이와 대응하는 일정 영역의 필름에 소정 광선을 조사하여, 상기 잉크층이 경화되면서 소정 문자, 문양 또는 기호 등이 형성되는 동시에, 상기 반도체 다이의 일면에 부착되도록 하는 단계와, 상기 회로기판에서 필름을 제거하여, 경화되지 않은 모든 잉크층이 제거되도록 하는 단계로 이루어짐. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor package and a semiconductor package thereof. The present invention relates to a package warpage, a total thickness control, and a masking defect, thereby improving reliability. Providing a circuit board having a cavity penetrated in the up and down directions, adhering a semiconductor die to an upper portion of the inside of the cavity, interconnecting the semiconductor die and the circuit board with conductive wires, and Forming an encapsulation part by covering the die, the conductive wire and the cavity with an encapsulant, fusing a plurality of solder balls to the other surface of the circuit board, adhering a film having an ink layer to the upper surface of the circuit board, and In a state of pressing with a jig, a predetermined light beam is irradiated to a film of a predetermined region corresponding to the semiconductor die, As the large layer is cured, predetermined letters, patterns, or symbols are formed, and attached to one surface of the semiconductor die, and the film is removed from the circuit board to remove all uncured ink layers. .

A lead frame of surface acoustic filter

본 고안은 표면탄성파필터의 리드프레임에 관한 것으로, 표면탄성파 필터칩(10)이 부착되는 패드(12)와, 도전성와이어(16)에 의해 상기 칩(10)을 외부회로에 연결시켜 주게 된 다수개의 리드(18)로 이루어진 표면탄성파필터의 리드프레임에 있어서, 상기 패드(12)가 양측단부에 소정의 절결부(22)가 형성되고, 이 절결부(22) 측에 리드의 전극패드(24)가 연장되어 설치된 구조로 되어, 와이어본딩작업을 용이하게 해줄 뿐아니라 칩설계의 자유도를 높여주는 효과가 있다. The present invention relates to a lead frame of a surface acoustic wave filter, and the pad 12 to which the surface acoustic wave filter chip 10 is attached and the conductive wire 16 connect the chip 10 to an external circuit. In the lead frame of the surface acoustic wave filter consisting of two leads 18, the pads 12 have predetermined cutouts 22 formed at both ends thereof, and the electrode pads 24 of the leads are formed on the cutouts 22 side. ) Has an extended structure, which not only facilitates wire bonding but also increases the degree of freedom of chip design.

Semiconductor package

Thin type system-in-package having no printed circuit board in the package structure, and multiple dies are on a top surface of a copper support

本發明陳述一種薄型系統級封裝，其主要特徵為封裝結構中不具備印刷電路板者，其具有一銅支架之一頂面上之複數晶粒，該些晶粒與該銅支架之複數資訊連結腳電性連接，另該該頂面上之一被動元件與該些晶粒電性連接，而該些晶粒電性連接於該銅支架之該接地腳，該些晶粒及該被動元件透過一絕緣膠固定於該銅支架之該頂面上，最後由一模製化合物，其囊封該銅支架之該頂面上之該些晶粒及該被動元件。

Bonding wires for semiconductor devices

表面にＰｄ被覆層を有するＣｕボンディングワイヤにおいて、高温高湿環境でのボール接合部の接合信頼性を改善し、車載用デバイスに好適なボンディングワイヤを提供する。Ｃｕ合金芯材と、前記Ｃｕ合金芯材の表面に形成されたＰｄ被覆層とを有する半導体装置用ボンディングワイヤにおいて、ボンディングワイヤがＩｎを０．０１１〜１．２質量％含み、Ｐｄ被覆層の厚さが０．０１５〜０．１５０μｍである。これにより、高温高湿環境下でのボール接合部の接合寿命を向上し、接合信頼性を改善することができる。Ｃｕ合金芯材がＰｔ、Ｐｄ、Ｒｈ、Ｎｉの１種以上をそれぞれ０．０５〜１．２質量％含有すると、１７５℃以上の高温環境でのボール接合部信頼性を向上できる。また、Ｐｄ被覆層の表面にさらにＡｕ表皮層を形成するとウェッジ接合性が改善する。 In a Cu bonding wire having a Pd coating layer on the surface, the bonding reliability of a ball bonding portion in a high temperature and high humidity environment is improved, and a bonding wire suitable for an in-vehicle device is provided. In a bonding wire for a semiconductor device having a Cu alloy core material and a Pd coating layer formed on the surface of the Cu alloy core material, the bonding wire contains 0.011 to 1.2% by mass of In, and the Pd coating layer The thickness is 0.015 to 0.150 μm. Thereby, the joint life of the ball joint portion in a high temperature and high humidity environment can be improved, and the joint reliability can be improved. When the Cu alloy core material contains 0.05 to 1.2% by mass of one or more of Pt, Pd, Rh, and Ni, the ball joint reliability in a high temperature environment of 175 ° C. or higher can be improved. Further, when an Au skin layer is further formed on the surface of the Pd coating layer, the wedge bondability is improved.

Semiconductor device

(57)【要約】 【課題】 半導体装置（ＬＳＩ）の開発効率と量産効率 を向上する 【解決手段】 集積回路が形成されたＬＳＩ３０には、 該集積回路を外部回路に接続するために複数のパッド部 ４０が形成されている。このパッド部４０には、保護膜 ３１に開口された窓とその窓から露出したパッド３２と で構成された接続部４０Ａと、保護膜３１に開口された 窓とその窓から露出したパッド３２に堆積されたバンプ ４５とで構成された接続部４０Ｂとを、備えている。Ｌ ＳＩ３０に、ワイヤボンディングで外部回路と接続する 要求がある場合には、ワイヤで接続部４０Ａと外部回路 を接続し、ＴＡＢやＣＯＧ方式で外部回路と接続する要 求がある場合には、接続部４０Ｂに直接外部回路を接続 する。

Semiconductor package with integrated heatsink

One or more embodiments are directed to semiconductor packages having an integrated heatsink and methods of forming same. In one embodiment, a package includes a plurality of leads that support and enclose periphery portions of the semiconductor die. The leads have first and second, opposing surfaces that form outer surfaces of the package. The first surface of the leads may form a heatsink and the second surface of the leads form lands of the package for coupling to another device, substrate, or board. The package includes encapsulation material that surrounds the semiconductor die and located between upper portions of the leads. The package further includes a back filling material (or insulating material) that is below the semiconductor die and between lower portions of the leads.

Semiconductor package

본 고안은 반도체 패키지에 관한 것으로, 반도체 칩이 부착되지 않는 패들 부위에 홀을 형성하여 패들과 컴파운드 간의 디라미네이션 현상에 의한 균열의 진행이 상기 홀에 트랩되게 함으로써, 균열로 인한 반도체 패키지의 파손을 방지한다.

Bonding wire for semiconductor device

Provided is a bonding wire for a semiconductor device, said bonding wire comprising a coating layer composed primarily of Pd on the surface of a Cu alloy core, and a cover alloy layer containing Au and Pd on the surface of the coating layer, wherein second bonding performance is further improved in a Pd-plated lead frame, and excellent ball bonding performance can be achieved even under high humidity and heat conditions.　In the bonding wire for a semiconductor device, said bonding wire comprising a coating layer composed primarily of Pd on the surface of a Cu alloy core, and a cover alloy layer containing Au and Pd on the surface of the coating layer, the concentration of Cu on the outermost surface of the wire is set at 1–10 at%, and the core contains 0.1–3.0 mass%, in total, of Pd and/or Pt, thus improving second bonding performance and enabling excellent ball bonding performance to be achieved under high humidity and heat conditions. In addition, the maximum concentration of Au in the cover alloy layer is preferably 15–75 at%.

Gold-coated bonding wire and its manufacturing method, semiconductor wire bonding structure, and semiconductor device

메모리 등의 반도체 장치의 칩 박형화, 다단 적층화의 니즈를 고려하여, 금을 주성분으로 한 본딩 와이어를 대신하는, 금과 동등한 특성을 갖고, 재료 비용이 들지 않는 다단 적층 칩 전극 사이를 직접 웨지 본딩하는 방법(CＷB)에 적용할 수 있는 금피복 본딩 와이어를 제공한다. 본 발명의 금피복 본딩 와이어(1)는, 은 또는 구리를 주성분으로서 포함하는 심재(2)와, 심재(2)의 표면에 마련되고, 금을 주성분으로서 포함하는 피복층(3)을 갖는다. 금피복층의 막두께를 5㎚ 이상 200㎚ 이하로 하고, 와이어 선 직경에 대해 60％ 변형시켰을 때의 압축 응력을 290MPa 이상 590MPa 이하로 제어함으로써 과제가 달성된다.

Bond wire for semiconductor device

Bonddraht für eine Halbleitervorrichtung, wobei der Bonddraht aufweist:ein Cu-Legierungskernmaterial; undeine auf einer Oberfläche des Cu-Legierungskernmaterials gebildete Pd-Überzugschicht, wobeibei Messung von Kristallorientierungen auf einem Querschnitt des Kernmaterials in senkrechter Richtung zu einer Drahtachse des Bonddrahts eine Kristallorientierung <100> im Winkel von höchstens 15 Grad zu einer Drahtlängsrichtung einen Anteil von mindestens 30 % unter Kristallorientierungen in Drahtlängsrichtung hat,eine mittlere Kristallkorngröße im Querschnitt des Kernmaterials in senkrechter Richtung zur Drahtachse des Bonddrahts 0,9 µm oder mehr und 1,5 µm oder weniger beträgt, undder Bonddraht ein oder mehrere Elemente ausgewählt aus Co, Rh, Ir, Ni, Pd, Pt, Ag, Au, Zn, Al, In, Sn, P, As, Sb, Bi, Se und Te enthält.

Electronic module and method for producing an electronic module

一种电子模块(100)，尤其功率电子模块，包括：‑用作为承载件的金属陶瓷衬底(1)，其具有陶瓷元件(10)和初级器件金属化部(21)和优选具有冷却件金属化部(20)；‑绝缘层(40)，其直接或间接连结于初级器件金属化部(21)，和‑次级器件金属化部(22)，其连结在绝缘层(40)的背离金属陶瓷衬底(1)的侧上，其中陶瓷元件(10)具有第一尺寸(L1、D1)并且绝缘层(40)具有第二尺寸(L2、D2)，并且其中为了在初级器件金属化部(21)上构成岛状的绝缘层(40)，第二尺寸(L2、D2)与第一尺寸(L1、D1)的比例具有小于0.8，优选小于0.6和特别优选小于0.4的值。

Bonding wire for semiconductor device

Bonding wire for semiconductor device

本发明涉及一种具有Cu合金芯材和在其表面形成的Pd被覆层的半导体装置用接合线，谋求提高175℃～200℃的HTS中的球接合部的接合可靠性和使耐力比(＝最大耐力/0.2％耐力)为1.1～1.6。通过使线中含有总计为0.03～2质量％的Ni、Zn、Rh、In、Ir、Pt中的1种以上，来提高HTS中的球接合部的接合可靠性，进而，在对与接合线的线轴垂直的方向的芯材截面测定晶体取向所得到的结果中，使线长度方向的晶体取向之中、相对于线长度方向角度差为15度以下的晶体取向<100>的取向比率为50％以上，且与接合线的线轴垂直的方向的芯材截面中的平均结晶粒径为0.9～1.3μm，由此使耐力比为1.6以下。

Semiconductor package

A stacked semiconductor package in an embodiment includes a first semiconductor package including a first circuit board and a first semiconductor element mounted on the first circuit board; and a second semiconductor package including a second circuit board and a second semiconductor element mounted on the second circuit board, the second semiconductor package being stacked on the first semiconductor package. The first semiconductor package further includes a sealing resin sealing the first semiconductor element; a conductive layer located in contact with the sealing resin; and a thermal via connected to the conductive layer and located on the first circuit board.

Method for exchanging capillary

본 발명은 캐필러리를 홀딩하는 홀딩 유닛을 포함하는 와이어 본딩 설비의 캐필러리 교체 방법에 관한 것이다. 본 발명의 캐필러리 교체 방법은 와이어 본딩 설비에서 전송된 캐필러리의 교체 신호에 대응하여, 주행 로봇이 상기 와이어 본딩 설비로 캐필러리 교체 유닛을 이송시키는 것; 상기 와이어 본딩 설비로 이송된 상기 캐필러리 교체 유닛이 상기 와이어 본딩 설비에서 상기 교체 신호에 대응되는 캐필러리를 분리하는 것; 및 상기 캐필러리 교체 유닛이 상기 캐필러리가 분리된 상기 와이어 본딩 설비에 새로운 캐필러리를 설치하는 것을 포함한다. The present invention relates to a capillary replacement method of a wire bonding equipment including a holding unit for holding the capillary. The capillary replacement method of the present invention includes, in response to a capillary replacement signal transmitted from a wire bonding facility, a traveling robot transferring the capillary replacement unit to the wire bonding facility; separating, by the capillary replacement unit transferred to the wire bonding facility, a capillary corresponding to the replacement signal from the wire bonding facility; and installing a new capillary in the wire bonding facility from which the capillary is separated by the capillary replacement unit.

Semiconductor device

본 발명은, 반도체 장치의 신뢰성을 향상시키는 것을 과제로 한다. 반도체 장치는, 반도체 칩 CP1, CP2와, 복수의 리드와, 복수의 와이어와, 그들을 밀봉하는 밀봉부를 갖고 있다. 반도체 칩 CP1은, 패드 전극 P1a, P1b와, 패드 전극 P1a, P1b 간을 전기적으로 접속하는 내부 배선 NH를 갖고 있다. 반도체 칩 CP2의 패드 전극 P2a와 반도체 칩 CP1의 패드 전극 P1a는 와이어 BW1을 개재하여 전기적으로 접속되고, 반도체 칩 CP1의 패드 전극 P1b는 와이어 BW2를 개재하여 리드 LD1에 전기적으로 접속되어 있다. 리드 LD1과 반도체 칩 CP1의 사이의 거리는, 리드 LD1과 반도체 칩 CP2의 사이의 거리보다도 작다. 그리고, 패드 전극 P1a, P1b 및 내부 배선 NH는, 반도체 칩 CP1 내에 형성되어 있는 어느 쪽의 회로와도 전기적으로 접속되어 있지 않다.

Hybrid semiconductor package

반도체 패키지는 기판과, 기판의 제 1 측에 부착된 RF 반도체 다이와, 기판의 제 1 측에 부착된 커패시터와, 기판의 제 1 측 상의 제 1 단자를 포함한다. 반도체 패키지는 제 1 단자를 RF 반도체 다이의 출력에 접속하는 구리 또는 알루미늄 본딩 와이어 또는 리본과, 커패시터를 RF 반도체 다이의 출력에 접속하는 금 본딩 와이어 또는 리본을 더 포함한다. 금 본딩 와이어 또는 리본은 RF 반도체 다이의 동작 동안, 구리 또는 알루미늄 본딩 와이어 또는 리본보다 큰 RF 주울 발열을 수용하도록 설계되어 있다. 대응하는 제조 방법이 또한 기술되어 있다. The semiconductor package includes a substrate, an RF semiconductor die attached to the first side of the substrate, a capacitor attached to the first side of the substrate, and a first terminal on the first side of the substrate. The semiconductor package further includes a copper or aluminum bonding wire or ribbon connecting the first terminal to the output of the RF semiconductor die, and a gold bonding wire or ribbon connecting the capacitor to the output of the RF semiconductor die. Gold bonding wires or ribbons are designed to accommodate greater RF joule heating than copper or aluminum bonding wires or ribbons during operation of the RF semiconductor die. Corresponding manufacturing methods are also described.

Bonding wire for semiconductor device

本发明涉及一种具有Cu合金芯材和在其表面形成的Pd被覆层的半导体装置用接合线，谋求提高175℃～200℃的HTS中的球接合部的接合可靠性和使耐力比(＝最大耐力/0.2％耐力)为1.1～1.6。通过使线中含有总计为0.03～2质量％的Ni、Zn、Rh、In、Ir、Pt中的1种以上，来提高HTS中的球接合部的接合可靠性，进而，在对与接合线的线轴垂直的方向的芯材截面测定晶体取向所得到的结果中，使线长度方向的晶体取向之中、相对于线长度方向角度差为15度以下的晶体取向<100>的取向比率为50％以上，且与接合线的线轴垂直的方向的芯材截面中的平均结晶粒径为0.9～1.3μm，由此使耐力比为1.6以下。

Plastic packaging type

내용 없음. No content.

Bond pad layout with radially bonded leadframe

리드프레임들이 방사상으로 접착되는 집적회로의 본드패드 레이아웃에 관한 것이다. 이 본드패드 레이아웃은 유효본드패드 피치를 감소시켜 반도체 다이가 보다 작게 되어 집적회로 패키지용으로 사용될 수 있게 한다. 본 발명의 1실시예에 의한 본드패드 레이 아웃은 유효본드 패드 피치가 종래의 다른 식으로 달성 할 수 있는 최소 본드패드 피치의 80％로 되게 한다. 본 발명에 의하면, 반도체 다이의 주위에 2열의 본드 본드패드들이 위치된다. 한 열상의 본드패드 피치는 다른 열상의 본드패드 피치와 다르다. 1실시예에 있어서, 한 열상의 본드패드 피치는 일정하고 제2열상의 본드패드 피치는 변화된다. 이 각 열상의 다른 본드패드 피치들은 인접 본드와이어들간의 간격이 거외 일정하게 유지되도록 하여 본딩 공정시 인접 본드 와이어들간의 간섭이나 본드 와이어들과 와이어본더 장치간의 간섭을 방지한다. 본 발명에 따른 본드패드 레이아웃은 리드 카운트에만 좌우된다. 이에따라, 레이아웃이 설계되는 동일한 리드 카운트를 갖는 어떠한 방사상으로 접착된 리드프레임에도 본 레이아웃이 사용될 수 있다.

Bonding wire for semiconductor device

Cu 합금 코어재와 그 표면에 형성된 Pd 피복층을 갖는 반도체 장치용 본딩 와이어에 있어서, 고온에 있어서의 볼 접합부의 접합 신뢰성 향상과, 내력비(＝최대 내력/0.2％ 내력): 1.1∼1.6의 양립을 도모한다. 와이어 중에 고온 환경 하에 있어서의 접속 신뢰성을 부여하는 원소를 포함함으로써 고온에 있어서의 볼 접합부의 접합 신뢰성을 향상시키고, 또한 본딩 와이어의 와이어 축에 수직 방향인 코어재 단면에 대해 결정 방위를 측정한 결과에 있어서, 와이어 길이 방향의 결정 방위 중, 와이어 길이 방향에 대해 각도 차가 15도 이하인 결정 방위 <100>의 방위 비율을 30％ 이상으로 하고, 본딩 와이어의 와이어 축에 수직 방향인 코어재 단면에 있어서의 평균 결정 입경을 0.9∼1.5㎛로 함으로써, 내력비를 1.6 이하로 한다.

Bonding wire for semiconductor device

本發明係於具有Cu合金芯材與形成於其表面之Pd被覆層之半導體裝置用接合導線，謀求175℃~200℃之HTS中之球接合部之接合可靠性提高、與耐力比(=最大耐力/0.2%耐力)：1.1~1.6之併存。藉由於導線中含有Ni、Zn、Rh、In、Ir、Pt之1種以上總計0.03~2質量%，而提高HTS中之球接合部之接合可靠性，進而藉由於對於接合導線之垂直於導線軸之方向之芯材剖面測定結晶方位之結果中，將導線長度方向之結晶方位中、相對於導線長度方向而角度差為15度以下的結晶方位<100>之方位比率設為50%以上，且將接合導線之垂直於導線軸之方向之芯材剖面中之平均結晶粒徑設為0.9~1.3μm，而使耐力比為1.6以下。

LED luminescence components, LED luminescent panels and LED display

本发明公开了LED发光组件、LED发光面板和LED显示屏。该LED发光组件包括一复合层、至少一个包含LED芯片的LED芯片组、至少一个驱动IC；复合层包括一位于前侧的基板；LED芯片和驱动IC均安装于复合层的前侧，LED芯片的负极通过打金线绑定(bonding)方式与驱动IC相连；复合层的前侧开设有多个盲孔，LED芯片的正极过一个盲孔从复合层内部接入正电极；驱动IC的VDD引脚引出导线过一个盲孔从复合层内部接入正电极；驱动IC的GND引脚引出导线过一个盲孔从复合层内部接入负电极；驱动IC之间由信号线连接。本方案实现了一种全透明的LED显示屏，透明度和像素密度都得到大幅度提高。

camera assembly

本发明提供一种能够满足薄型化要求的摄像机组件。该摄像机组件在部件内置基板(10)的表面(上表面)设置有具有大于摄像元件(15)的厚度的深度的凹部(CP)，摄像元件(15)以其表面(上表面)与部件内置基板(10)的表面(上表面)之间存在空隙(GA)的方式安装于凹部(CP)的底面(CPa)，并且摄像元件(15)的连接焊盘(15b)通过在空隙(GA)中经过的键合丝(BW)与设置于部件内置基板(10)的表面(上表面)的导体焊盘(12d)连接。

Semiconductor chip having pads with plural junctions for different assembly methods

Development efficiency and mass production efficiency of a semiconductor chip (LSI) is improved, whereby the LSI on which an integrated circuit is formed has plural pad parts connecting the integrated circuit with an external circuit. The pad part is provided with a first junction consisting of a window formed in the protective film and the pad exposed from the window, and a second junction consisting of a window formed in the protective film and a bump deposited on the pad exposed from the window. When it is required that the LSI is to be connected with an external circuit by wire bonding, the first junction is connected with the external circuit using a wire. When it is required to connect the LSI with an external circuit by the TAB method or the COG method, the second junction is directly connected to the external circuit.

Semiconductor package body with integral fin

一个或多个实施例涉及具有集成散热片的半导体封装体以及形成这些半导体封装体的方法。在一个实施例中，封装体包括多根引线，这些引线支撑并封闭该半导体裸片的多个周边部分。这些引线具有形成该封装体的多个外表面的第一和第二相对的表面。这些引线的第一表面可以形成散热片而这些引线的第二表面形成该封装体的用于耦接至另一个器件、衬底或板上的多个焊区。该封装体包括包封材料，该包封材料包围该半导体裸片并且位于这些引线的这些上部部分之间。该封装体进一步包括后部填充材料(或绝缘材料)，该后部填充材料在该半导体裸片下方并且在这些引线的这些下部部分之间。

Surface mounting power device packaging structure with embedded cooling fin

本发明的内嵌散热片的表面贴装功率器件封装结构，包括塑封体，塑封体内设置有引脚且引脚伸出至塑封体外，所述引脚位于塑封体内部分的上表面设置有散热片。本发明在不改变表面贴装功率器件外形的情况下，内嵌散热片，在保证兼容大多数类似封装的情况下，提高了散热效果，使得封装的产品有更低的热阻，较同外形尺寸的其它封装形式的稳态热阻减少大约5%，瞬态热阻减少大约50%，封装的功率密度（W/mm 2 ）装提高大约12%，提高了器件的可靠性。

Thin System-in-Package

本發明陳述一種薄型系統級封裝，其主要特徵為封裝結構中不具備印刷電路板者，其具有一銅支架之一頂面上之複數晶粒，該些晶粒與該銅支架之複數資訊連結腳電性連接，另該該頂面上之一被動元件與該些晶粒電性連接，而該些晶粒電性連接於該銅支架之該接地腳，該些晶粒及該被動元件透過一絕緣膠固定於該銅支架之該頂面上，最後由一模製化合物，其囊封該銅支架之該頂面上之該些晶粒及該被動元件。

Circuit for chip card module

本实用新型提供一种用于芯片卡模块(3)的电路，该电路包括多层结构。该多层结构包括绝缘衬底(4)以及由该绝缘衬底(4)的一个侧面支撑的第一导电层(7)。该第一导电层(7)旨在通过引线接合到该第一导电层(7)的电线(13)而电连接到电子芯片(12)。该第一导电层(7)是维氏硬度大于或等于100VHN的基于铜的层。

Jin Beifu bonding wire, method for manufacturing the same, semiconductor wire bonding structure, and semiconductor device

本发明考虑存储器等半导体装置的芯片薄型化、多段层叠化的需求，提供代替以金为主成分的接合丝线、具有与金同等的特性、不会花费材料成本的、可适用于将多段层叠芯片电极之间直接楔形接合的方法(CWB)的金被覆接合丝线。本发明的金被覆接合丝线(1)具有含银或铜作为主成分的芯材(2)和设置在芯材(2)的表面上且含金作为主成分的被覆层(3)。通过将覆金层的膜厚控制为5nm～200nm、且将相对于丝线线径变形60％时的压缩应力控制为290MPa～590MPa，从而达成技术问题。

Bonding wire for semiconductor device

Bonddraht für eine Halbleitervorrichtung, der aufweist: ein Cu-Legierungskernmaterial; und eine Pd-Überzugschicht, die auf einer Oberfläche des Cu-Legierungskernmaterials ausgebildet ist, wobei der Bonddraht wenigstens ein oder mehrere Elemente enthält, die aus As und Te ausgewählt sind, eine Konzentration der Elemente insgesamt 0,1 Massen-ppm oder mehr und 100 Massen-ppm oder weniger relativ zu dem Gesamtdraht ist, und das Cu-Legierungskernmaterial eine Konzentration von Pd aufweist, die kleiner als 50 At-% ist, die Pd-Überzugschicht eine Konzentration von Pd aufweist, die 50 At-% oder mehr ist, und das Cu-Legierungskernmaterial und die Pd-Überzugschicht eine gemeinsame Grenze aufweisen. A bonding wire for a semiconductor device, comprising: a Cu alloy core material; and a Pd-cladding layer formed on a surface of the Cu alloy core material, wherein the bonding wire contains at least one or more elements selected from As and Te, a concentration of the elements totaling 0.1 mass ppm or more and 100 Is mass ppm or less relative to the total wire, and the Cu alloy core material has a concentration of Pd that is less than 50 at%, the Pd-cladding layer has a concentration of Pd that is 50 at% or more, and the Cu alloy core material and the Pd coating layer have a common boundary.

Lead frame

Wire bonding structure and bonding wire and semiconductor device used therefor

재료 비용을 억제한 본딩 와이어와 전극을 접합해도 비저항의 상승을 억제하면서, 과혹한 환경 하에 있어서도 장기간 본딩 와이어와 전극의 접합 신뢰성을 유지한다. 와이어 접합 구조(1)는, 알루미늄을 포함하는 전극(2)과, 본딩 와이어(3)와, 전극(2)에 접합된 볼 압축부(6)를 갖는다. 본딩 와이어(3)는, 은을 주성분으로 하는 심재(4)와, 금을 주성분으로 하는 피복층(5)을 갖고, 황, 텔루륨, 셀레늄, 비소, 및 안티몬에서 선택되는 적어도 하나의 제15 및 16족 원소를 함유하고, 와이어 전체에 대해서, 금 농도가 2.0질량% 이상 7.0질량% 이하이고, 제15 및 16족 원소 농도가 합계로 4질량ppm 이상 80질량ppm 이하이고, 전극(2)과 볼 압축부(6)의 접합 계면 근방에, 금 농도가, 알루미늄과 은과 금의 합계에 대해서 5.0원자% 이상으로 되는 금 농화(濃化) 접합 영역을 갖는다.

Bonding wires for semiconductor devices

Ｃｕ合金芯材とその表面に形成されたＰｄ被覆層とを有する半導体装置用ボンディングワイヤにおいて、１７５℃〜２００℃のＨＴＳでのボール接合部の接合信頼性向上と、耐力比（＝最大耐力／０．２％耐力）：１．１〜１．６の両立を図る。ワイヤ中にＮｉ、Ｚｎ、Ｒｈ、Ｉｎ、Ｉｒ、Ｐｔの１種以上を総計で０．０３〜２質量％含有することによってＨＴＳでのボール接合部の接合信頼性を向上し、さらにボンディングワイヤのワイヤ軸に垂直方向の芯材断面に対して結晶方位を測定した結果において、ワイヤ長手方向の結晶方位のうち、ワイヤ長手方向に対して角度差が１５度以下である結晶方位＜１００＞の方位比率を５０％以上とし、ボンディングワイヤのワイヤ軸に垂直方向の芯材断面における平均結晶粒径を０．９〜１．３μｍとすることにより、耐力比を１．６以下とする。 In a bonding wire for a semiconductor device having a Cu alloy core material and a Pd coating layer formed on the surface thereof, the bonding reliability of the ball bonded portion at 175 ° C. to 200 ° C. is improved, and the yield strength ratio (= maximum yield strength / 0.2% proof stress): 1.1 to 1.6 is achieved. By including one or more of Ni, Zn, Rh, In, Ir, and Pt in the wire in a total amount of 0.03 to 2% by mass, the bonding reliability of the ball joint portion in the HTS is improved. As a result of measuring the crystal orientation with respect to the cross section of the core material perpendicular to the wire axis, the crystal orientation <100> in which the angle difference with respect to the wire longitudinal direction is 15 degrees or less among the crystal orientations in the wire longitudinal direction The yield ratio is set to 1.6 or less by setting the ratio to 50% or more and setting the average crystal grain size in the cross section of the core material perpendicular to the wire axis of the bonding wire to 0.9 to 1.3 μm.

RF Semiconductor For communication

본 발명에 의한 통신용 증폭 반도체는 통신용 증폭 반도체용 기판, 상기 통신용 증폭 반도체용 기판 상에 적층되어 능동소자와 수동소자가 실장되는 실장공간을 둘러싸는 형태를 가지는 절연체, 상기 절연체와 결합되어 상기 실장공간을 밀폐시키는 커버 리드부재 및 상기 절연체의 상부면과 상기 커버 리드부재의 하부면 중 어느 한면에 형성되어 내부에 상기 절연체와 커버 리드부재를 접착 고정하는 접착제가 주입되는 접착제 삽입홈부를 포함할 수 있다. Communication amplification semiconductor according to the present invention is a communication amplification semiconductor substrate, an insulator stacked on the communication amplification semiconductor substrate and enclosing a mounting space in which an active element and a passive element are mounted, and the insulator coupled to the mounting space It may include a cover lid member sealing the cover and an adhesive insertion groove formed on one of the upper surface of the insulator and the lower surface of the cover lead member and into which an adhesive for adhesively fixing the insulator and the cover lead member is injected. .

Leadframe and semiconductor package using the same

본 발명은 리드 프레임 및 그를 이용한 반도체 패키지에 관한 것으로, 성형 공정이 완료된 반도체 패키지를 성형 금형에서 분리하는 이형핀에 의해 반도체 패키지가 손상되는 것을 억제하기 위하여, 본 발명은 반도체 성형 금형의 이형핀에 대응되는 다이 패드 부분을 관통하는 구멍이 형성된 리드 프레임 및 그를 이용한 반도체 패키지를 제공한다. 특히, 다이 패드의 구멍의 내경은 이형핀의 외경보다는 크게 형성하는 것이 바람직하다. The present invention relates to a lead frame and a semiconductor package using the same. In order to prevent the semiconductor package from being damaged by the release pin separating the semiconductor package from which the molding process is completed from the molding die, the present invention relates to the release pin of the semiconductor molding die. A lead frame having a hole penetrating a corresponding die pad portion and a semiconductor package using the same are provided. In particular, the inner diameter of the hole of the die pad is preferably larger than the outer diameter of the release pin. 본 발명은 또한 중심에 소정의 공간을 두고 두 부분으로 나누어진 다이 패드를 포함하며, 나누어진 다이 패드 사이의 공간은 반도체 성형 금형의 이형핀에 대응되는 부분에 형성된 리드 프레임 및 그를 이용한 반도체 패키지를 제공한다. 특히, 다이 패드 사이의 공간은 이형핀의 외경보다는 크게 형성하는 것이 바람직하다. The present invention also includes a die pad divided into two parts with a predetermined space in the center, and the space between the divided die pads includes a lead frame formed at a portion corresponding to the release pin of the semiconductor molding die, and a semiconductor package using the same. to provide. In particular, the space between the die pads is preferably formed larger than the outer diameter of the release pin.

图像传感器封装件和制造该图像传感器封装件的方法

提供了具有改善的可靠性的图像传感器封装件和制造该图像传感器封装件的方法。所述图像传感器封装件包括：封装基底；图像传感器芯片，设置在封装基底上，并且包括像素区域和围绕像素区域的外围区域；坝状件，在外围区域中，坝状件具有矩形环形状并围绕像素区域；透明盖，设置在坝状件上，并且覆盖图像传感器芯片的上部；以及密封材料，密封图像传感器芯片，并且覆盖透明盖的侧表面。坝状件包括应力驰豫层(SRL)和在SRL上的主体层，并且SRL的粘度低于主体层的粘度。

파워모듈

본 발명은 파워모듈에 관한 것으로, 베이스 플레이트와, 베이스 플레이트의 상면에 접합된 세라믹기판과, 세라믹기판의 상면에 접합된 반도체 칩과, 반도체 칩과 이격되게 세라믹기판의 상면에 접합된 스페이서와, 스페이서의 상면에 형성된 전극층에 설치된 연결핀과, 반도체 칩의 단자와 스페이서의 전극층을 연결하는 와이어 본딩을 포함한다.

반도체 패키지 구조 및 제조 방법

본 발명의 실시예는 반도체 패키지 구조 및 제조 방법을 개시하였고, 여기서, 상기 반도체 패키지 구조는, 제1 패키지 구조 및 제2 패키지 구조를 포함하고, 상기 제1 패키지 구조는 중계층 및 몰딩 컴파운드를 포함하며, 상기 중계층 위에는 제1 연결 패드가 설치되고, 상기 몰딩 컴파운드는 상기 중계층을 감싸며, 상기 제1 연결 패드와 공면이고; 상기 제2 패키지 구조는 상기 중계층 위에 설치되어, 상기 제1 연결 패드와 전기적으로 연결되며; 여기서, 상기 제1 패키지 구조와 상기 제2 패키지 구조 사이에는 공극이 존재한다.

와이어 구조체, 이를 포함하는 캐패시터 와이어 및 캐패시터 와이어를 포함하는 전자장치

캐패시터 와이어는 길이 방향으로 길게 연장되는 와이어 구조체, 및 상기 와이어 구조체의 외면을 덮는 전도성층을 포함한다. 상기 와이어 구조체는 상기 길이 방향으로 길게 연장되는 와이어 형상을 갖는 코어 전극 라인, 및 상기 코어 전극 라인의 외면을 둘러싸고 상기 길이 방향으로 연장되는 유전체 라인을 포함한다. 상기 와이어 구조체는 상기 길이 방향으로 서로 대향하는 제1 단부 및 제2 단부를 갖고, 상기 전도성층은 상기 와이어 구조체의 상기 제1 단부 및 상기 제2 단부를 노출한다.

Copper alloy bonding wire for semiconductor devices

This copper alloy bonding wire for a semiconductor device achieves improvement in the ball bond life in high temperature, high humidity environments. This semiconductor device bonding wire is characterized by containing a 0.03-3 mass pcnt total of one or more elements selected from Ni, Zn, Ga, Ge, Rh, In, Ir and Pt (first elements), the remainder being Cu and unavoidable impurities. By containing a prescribed amount of the first elements, the occurrence of intermetallic compounds, prone to corrosion in high temperature high humidity environments, is suppressed in the wire bonding interface, and ball bond life is improved.

파워 모듈

본 발명은 파워 모듈에 관한 것으로서, 외부 PCB 기판의 구동소자로부터 파워 모듈 내부의 반도체 칩으로 전달되는 구동 신호 전달 경로를 최소화하여 빠른 스위칭 속도와 적은 전력 손실을 구현할 수 있는 파워 모듈을 제공한다. 본 발명에 따른 파워 모듈은, 세라믹 기판과; 세라믹 기판에 병렬 배치된 복수의 반도체 칩과; 세라믹 기판의 측면으로부터 반도체 칩을 감싸도록 형성된 몰딩체와; 세라믹 기판에 수직으로 장착되고 단부가 몰딩체 외부로 돌출된 구조를 가지며 반도체 칩과 외부의 PCB 기판에 장착된 구동소자를 연결하는 복수의 스위칭 신호 전달핀과, 세라믹 기판에 수직으로 장착되고 단부가 몰딩체 외부로 돌출된 구조를 가지며 반도체 칩과 PCB 기판에 장착된 캐패시터를 연결하는 복수의 캐패시터 연결핀과, 반도체 칩과 연결되어 상기 몰딩체 외부로 인출된 복수의 전력 입출력 리드;를 포함하여 구성된 것을 특징으로 한다.

Semiconductor package

A semiconductor package includes at least one semiconductor module on a substrate. The semiconductor module includes a first semiconductor chip having a first surface and a second surface opposite to the first surface, a second semiconductor chip on the first surface, a plurality of conductive pillars on the first surface, and a redistribution substrate on the second semiconductor chip and the plurality of conductive pillars. The redistribution substrate has a third surface and a fourth surface opposite to the third surface. The third surface of the redistribution substrate faces the first surface of the first semiconductor chip, the plurality of conductive pillars are electrically connected to the first surface of the first semiconductor chip and the third surface of the redistribution substrate, and the fourth surface of the redistribution substrate is electrically connected to the substrate of the semiconductor package.

Stacked semiconductor dies for semiconductor device assemblies

Stacked semiconductor dies for semiconductor device assemblies and associated methods and systems are disclosed. In some embodiments, the semiconductor die assembly includes a substrate with a first opening in an inner portion and a second opening in an outer portion of the substrate. Further, the semiconductor die assembly can include a master die attached to a front side of the substrate, where the master die includes a first bond pad proximate to the first opening and a second bond pad proximate to the second opening. The first and second bond pads of the master die can be coupled with first and second substrate bond pads on a back side of the substrate, opposite to the front side, using first and second bonding wires extending through the first and second openings, respectively.

Semiconductor package

A semiconductor package includes a substrate having a lower surface and an opposite upper surface, an insulating layer, and a wiring layer on the insulating layer. A first upper protective layer is on the upper surface and includes first openings. A second upper protective layer is on the first upper protective layer. A semiconductor chip is on the first upper protective layer and includes connection pads electrically connected to the wiring layer through the first openings. An encapsulant seals at least a portion of the semiconductor chip, and the second upper protective layer. The first upper protective layer includes a first insulating material. The second upper protective layer includes a second insulating material having a coefficient of thermal expansion lower than that of the first insulating material and a tensile strength higher than that of the first insulating material.

半导体装置用铜合金接合线

在半导体装置用的铜合金接合线中，实现高温高湿环境下的球部接合寿命的提高。一种半导体装置用铜合金接合线，其特征在于，总计含有0.03质量％以上3质量％以下的选自Ni、Zn、Ga、Ge、Rh、In、Ir、Pt的至少1种以上的元素(第1元素)，其余部分由Cu和不可避免杂质构成。通过含有预定量的第1元素，从而在线接合界面中抑制在高温高湿环境下容易腐蚀的金属间化合物的生成，提高球部接合寿命。

镀金方法及镀覆膜

本发明提供镀金方法及镀覆膜，其防止由于安装等引起的热历程而导致引线键合特性降低。另外，提供一种即使减少镀金覆膜的膜厚也能防止由于安装等引起的热历程而导致引线键合特性降低的镀金方法及镀覆膜。一种镀金方法，其特征在于，其是在铜或铜合金覆膜上使用银催化剂进行镀覆的、用于引线键合连接的镀金方法，所述方法包括：银催化剂形成工序，其中，为了形成钯覆膜而形成作为银催化剂的银覆膜；钯覆膜形成工序，其中，在所述银催化剂上形成钯覆膜；以及，镀金覆膜形成工序，其中，在在所述钯覆膜上形成镀金覆膜，所述银覆膜的膜厚为0.05μm～0.5μm。

Image sensor package and method of fabricating the same

Provided are an image sensor package with improved reliability and a method of fabricating the same. The image sensor package includes: a package substrate; an image sensor chip provided on the package substrate, and including a pixel area and a peripheral area surrounding the pixel area; a dam in the peripheral area, the dam having a rectangular ring shape and surrounding the pixel area; a transparent cover provided on the dam and covering an upper portion of the image sensor chip; and a sealing material sealing the image sensor chip and covering side surfaces of the transparent cover. The dam includes a stress relaxation layer (SRL) and a body layer on the SRL, and the SRL has a lower viscosity than a viscosity of the body layer.

半導體封裝

本發明提供一種半導體封裝，包含：第一重佈線基底；半導體晶片，位於第一重佈線基底上；以及豎直導電結構，與半導體晶片的側表面間隔開。豎直導電結構中的各者包含導線及覆蓋導線的側表面的金屬層。導線的頂部表面自金屬層暴露。

金被覆ボンディングワイヤとその製造方法、半導体ワイヤ接合構造、及び半導体装置