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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 17308. Отображено 200.
26-02-2015 дата публикации

Bildung von Source-Drain-Erweiterungen in Metall-Ersatz-Gate-Transistoreinheit

Номер: DE102012223655B4

Verfahren zur Herstellung eines Feldeffekttransistors, aufweisend: Bilden einer Platzhalter-Gate-Struktur, die aus einem Stopfen besteht, auf einer Fläche eines Halbleiters; Bilden eines ersten Abstandhalters, welcher den Stopfen umgibt, wobei der erste Abstandhalter ein Opfer-Abstandhalter ist; und Durchführen einer abgewinkelten Ionenimplantation, um in Nachbarschaft zu einer äußeren Seitenwand des ersten Abstandhalters eine Dotierstoffspezies in die Fläche des Halbleiters zu implantieren, um eine Source-Erweiterungszone und eine Drain-Erweiterungszone zu bilden, wobei sich die implantierte Dotierstoffspezies in einem Ausmaß unter der äußeren Seitenwand des ersten Abstandhalters erstreckt, welches eine Funktion des Winkels der Ionenimplantation ist; und Durchführen eines Laser-Temperns, um die Implantation der Source-Erweiterung und der Drain-Erweiterung zu aktivieren.

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31-12-2020 дата публикации

HALBLEITERVORRICHTUNG UND HERSTELLUNGSVERFAHREN

Номер: DE102020104370A1
Принадлежит:

Es werden ein Halbleiter-Bauelement und ein Verfahren bereitgestellt, mit dem eine Mehrzahl von Abstandshaltern in einem ersten Bereich und einem zweiten Bereich eines Substrats hergestellt wird. Die Mehrzahl von Abstandshaltern in dem ersten Bereich wird strukturiert, während die Mehrzahl von Abstandshaltern in dem zweiten Bereich geschützt wird, um die Eigenschaften der Abstandshalter in dem ersten Bereich von den Eigenschaften der Abstandshalter in dem zweiten Bereich zu trennen.

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31-12-2020 дата публикации

DEPOP UNTER VERWENDUNG ZYKLISCHER SELEKTIVER ABSTANDHALTER-ÄTZUNG

Номер: DE102020113776A1
Принадлежит:

Eine Integrierte-Schaltung-Struktur umfasst eine Halbleiterfinne, die durch eine Grabenisolationsregion über einem Substrat hervorsteht. Eine Gate-Struktur befindet sich über einer Halbleiterfinne. Eine Mehrzahl von vertikal gestapelten Nanodrähten verläuft durch die Gate-Struktur, die Mehrzahl von vertikal gestapelten Nanodrähten umfassend einen oberen Nanodraht benachbart zu einer Oberseite der Gate-Struktur und einen unteren Nanodraht benachbart zu einer Oberseite der Halbleiterfinne. Ein Dielektrikumsmaterial deckt nur einen Abschnitt der Mehrzahl von vertikal gestapelten Nanodrähten außerhalb der Gate-Struktur ab, sodass einer oder mehrere der Mehrzahl von vertikal gestapelten Nanodrähten, beginnend mit dem oberen Nanodraht, von dem Dielektrikumsmaterial freigelegt sind. Source- und Drain-Regionen befinden sich an gegenüberliegenden Seiten der Gate-Struktur, die mit den freiliegenden der Mehrzahl von vertikal gestapelten Nanodrähten verbunden sind.

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19-03-2015 дата публикации

Verfahren zum selektiven Erzeugen von Verformung in einem Transistor durch eine Verspannungsgedächtnistechnik ohne Hinzufügung weiterer Lithographieschritte

Номер: DE102008007003B4

Verfahren mit: Bilden von tiefen Drain- und Sourcegebieten eines ersten Transistors; Ausheizen des ersten Transistors und eines zweiten Transistors, um einen im Wesentlichen kristallinen Zustand in dem tiefen Draingebiet und dem tiefen Sourcegebiet des ersten Transistors zu erzeugen; Einführen einer Implantationssorte, die eine nicht-dotierende Sorte umfasst, in den zweiten Transistor, um Gitterschäden benachbart zu einem Kanalgebiet des zweiten Transistors zu erzeugen; Bilden einer Deckschicht über dem ersten Transistor und dem zweiten Transistor nach dem Bilden der tiefen Drain- und Sourcegebiete des ersten Transistors; und Ausheizen des ersten und des zweiten Transistors in Anwesenheit der Deckschicht, um die Gitterschäden zu rekristallisieren und eine Verspannung in dem zweiten Transistor hervorzurufen.

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16-06-2005 дата публикации

Verbesserte Technik zur Herstellung eines Transistors mit erhöhten Drain- und Sourcegebieten

Номер: DE0010351237A1
Принадлежит:

Durch Bilden einer Vertiefung in einer Halbleiterschicht, vorzugsweise durch lokales Oxidieren der Halbleiterschicht, kann ein spannungserzeugendes Material und/oder eine Dotierstoffspezies in die gedünnte Halbleiterschicht in der Nähe einer Gateelektrodenstruktur mittels eines nachfolgenden epitaktischen Wachstumsprozesses eingeführt werden. Insbesondere das spannungserzeugende Material, das benachbart zu der Gateelektrodenstruktur ausgebildet ist, übt eine Druck- oder Zugspannung, abhängig von der Art des abgeschiedenen Materials, aus, wodurch die Beweglichkeit der Ladungsträger in einem Kanalgebiet des Transistorelements erhöht wird.

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11-01-2007 дата публикации

Halbleiterbauelement mit verspanntem aktiven Gebiet

Номер: DE0010352730B4

Halbleiterbauelement mit einem aktiven Halbleiterbereich (11) und einem den aktiven Halbleiterbereich (11) lateral begrenzenden Isolatorbereich (13), der auf den aktiven Halbleiterbereich (11) eine entweder teilweise oder vollständig lateral gerichtete Kraft ausübt, dadurch gekennzeichnet, dass der lateral begrenzende Isolatorbereich (13) hinsichtlich des Materials oder seiner lateralen Erstreckung oder beider so gewählt ist, dass im aktiven Halbleiterbereich eine uniaxiale oder eine biaxiale, tensile oder kompressive Gitterdilatation mit einem vorbestimmten Betrag ε von entweder 0,01 oder mehr als 0,01 vorliegt.

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14-02-2013 дата публикации

Herstellung einer Kanalhalbleiterlegierung durch Erzeugen einer nitridbasierten Hartmaskenschicht

Номер: DE102011080589A1
Принадлежит:

Die vorliegende Erfindung stellt Fertigungstechniken bereit, in denen komplexe Metallgateelektrodenstrukturen mit großem in einer frühen Fertigungsphase auf der Grundlage einer selektiv aufgebrachten schwellwertspannungseinstellenden Halbleiterlegierung hergestellt werden. Um die Oberflächentopographie beim Strukturieren der Abscheidemaske zu verringern, wobei dennoch die Verwendung gut etablierter epitaktischer Aufwachsrezepte, die für siliziumdioxidbasierte Hartmaskenmaterialien entwickelt sind, möglich ist, wird ein Siliziumnitridbasismaterial in Verbindung mit einer Oberflächenbehandlung verwendet. Auf diese Weise zeigt die Oberfläche des Siliziumnitridmaterials ein Siliziumdioxid-artiges Verhalten, während die Strukturierung der Hartmaske dennoch auf der Grundlage sehr selektiver Ätztechniken bewerkstelligt werden kann.

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03-11-2011 дата публикации

Verspannungsgedächtnistechnik mit geringerer Randzonenkapazität auf der Grundlage von Siliziumnitrid in MOS-Halbleiterbauelementen

Номер: DE102010028462A1
Принадлежит:

In komplexen Halbleiterbauelementen werden Verspannungsgedächtnistechnologien auf der Grundlage eines Siliziumnitridmaterials angewendet, das nachfolgend in ein dielektrisches Material mit kleinem modifiziert wird, um damit Abstandshalterelemente mit kleinem zu erhalten, wodurch das Leistungsverhalten komplexer Halbleiterbauelemente verbessert wird. Die Modifizierung des anfänglichen siliziumnitridbasierten Abstandshaltermaterials kann auf der Grundlage eines Sauerstoffimplantationsprozesses bewerkstelligt werden.

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16-06-2005 дата публикации

Technik zur Herstellung eines Transistors mit erhöhten Drain- und Source-Gebieten, wobei eine reduzierte Anzahl von Prozessschritten erforderlich ist

Номер: DE0010351006A1
Принадлежит:

Durch Verwendung von Seitenwandabstandselementen benachbart zu einer Gateelektrodenstruktur sowohl als eine Epitaxiewachstumsmaske als auch eine Implantationsmaske wird die Komplexität eines konventionellen Prozessablaufs zur Herstellung erhöhter Drain- und Sourcegebiete deutlich reduziert, wodurch Produktionskosten verringert und die Ausbeute durch Absenken der Defektrate verbessert wird.

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21-06-2012 дата публикации

Leistungssteigerung in Transistoren mit Metallgatestapeln mit großem ε und einem eingebetteten Verspannungsmaterial durch Ausführen eines zweiten Epitaxieschrittes

Номер: DE102010063782A1
Принадлежит:

Bei der Herstellung komplexer Transistoren, die beispielsweise Metallgateelektrodenstukturen mit großem aufweisen, wird ein ausgeprägter Materialverlust eines eingebetteten verformungsinduzierenden Halbleitermaterials kompensiert oder zumindest deutlich verringert, indem ein zweiter epitaktischer Aufwachsprozess nach dem Einbau der Drain- und Sourceerweiterungsdotiermittel ausgeführt wird. Auf diese Weise werden bessere Verformungsbedingungen erreicht, wobei auch die erforderlichen Drain- und Sourcedotierprofile eingerichtet werden.

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11-02-2016 дата публикации

Fein-Strukturierungsverfahren und Verfahren zum Herstellen von Halbleitervorrichtungen mit denselben

Номер: DE102015110689A1
Принадлежит:

Ein Fein-Strukturierungsverfahren weist ein Bilden einer Maskenschicht (45, 145) mit einer unteren und einer oberen Maskenschicht auf einer unterliegenden Schicht (20, 120), ein Bilden eines Paars von Opferstrukturen (50, 150) auf der Maskenschicht (45, 145), ein Bilden eines Verbindungsabstandshalters (64, 164) zwischen den Opferstrukturen (50, 150) und ersten Abstandshaltern (62, 162), welche voneinander mit dem Paar von Opferstrukturen (50, 150) dazwischenliegend angeordnet beabstandet sind und ein Bedecken von Seitenoberflächen der Opferstrukturen (50, 150), ein Ätzen der oberen Maskenschicht unter Verwendung der ersten Abstandshalter (62, 162) und des Verbindungsabstandshalters (64, 164) als einer Ätzmaske, um obere Maskenstrukturen zu bilden, ein Bilden von zweiten Abstandshaltern (72, 172), um Seitenoberflächen der oberen Maskenstrukturen zu bedecken, ein Ätzen der unteren Maskenschicht unter Verwendung der zweiten Abstandshalter (72, 172) als einer Ätzmaske, um untere Maskenstrukturen ...

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02-01-2020 дата публикации

Source- oder Drainstrukturen mit Kontaktätzstoppschicht

Номер: DE102019114022A1
Принадлежит:

Ausführungsbeispiele der Offenbarung liegen im Bereich der Herstellung fortgeschrittener integrierter Schaltungsstrukturen und insbesondere werden integrierte Schaltungsstrukturen mit Source- oder Drainstrukturen mit einer Kontaktätzstoppschicht beschrieben. Bei einem Beispiel umfasst eine integrierte Schaltungsstruktur eine Finne, umfassend ein Halbleitermaterial, wobei die Finne einen unteren Finnenabschnitt und einen oberen Finnenabschnitt aufweist. Ein Gate-Stapel ist über dem oberen Finnenabschnitt der Finne, wobei der Gate-Stapel eine erste Seite gegenüber einer zweiten Seite aufweist. Eine erste epitaxiale Source- oder Drainstruktur ist in die Finne an der ersten Seite des Gate-Stapels eingebettet. Eine zweite epitaxiale Source- oder Drainstruktur ist in die Finne auf der zweiten Seite des Gate-Stapels eingebettet, wobei die erste und zweite epitaxiale Source- oder Drainstruktur eine untere Halbleiterschicht, eine Zwischenhalbleiterschicht und eine obere Halbleiterschicht umfassen ...

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03-03-2016 дата публикации

Hochintegriertes Halbleiterbauelement mit Silicidschicht und zugehöriges Herstellungsverfahren

Номер: DE102004041066B4

Hochintegriertes Halbleiterbauelement mit einem Halbleitersubstrat (100), einer Gateelektrode (110), die auf einem vorgegebenen Bereich des Halbleitersubstrats angeordnet ist, einem Offset-Abstandshalter (115) an wenigstens einer Seitenwand der Gateelektrode, einer epitaxialen Schicht (120) auf dem Halbleitersubstrat (100) beidseits neben der Gateelektrode (110) mit dem Offset-Abstandshalter und daran angrenzend, wobei die Gateelektrode um eine vorgegebene Tiefe (d) in der epitaxialen Schicht vertieft ist, einem Sourcebereich und einem Drainbereich (150a, 150b) die beidseits der Gateelektrode in der epitaxialen Schicht und einem vorgegebenen oberen Bereich des Halbleitersubstrats unterhalb der epitaxialen Schicht ausgebildet sind und jeweils einen schwach dotierten Bereich (130a, 130b), der sich im oberen Bereich des Halbleitersubstrats lateral bis zur Seitenwand einer Gateisolationsschicht (105) der Gateelektrode erstreckt, und einen stark dotierten Bereich (140a, 140b) lateral angrenzend ...

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14-07-2005 дата публикации

MOS transistor drain/source path manufacturing method for use in nitride ROM, involves etching spacer made of tetra ethyl ortho silicate to create spacing between gate contact and source region and between contact and drain region

Номер: DE102004059636A1
Принадлежит:

The method involves placing a structure with a gate contact (8) over a gate oxide layer (1) coated over a substrate (S). A silicon nitride layer (2) is laid over areas that are not covered by the structure. A spacer (3) made of tetra ethyl ortho silicate (TEOS) and placed on the nitride layer is etched to create a spacing of about 200 to 215 nanometer between the contact and a source region, and the contact and a drain region. An independent claim is also included for a semiconductor device with a MOS transistor having drain/source path.

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23-07-2009 дата публикации

Verfahren zum Reduzieren von Kristalldefekten in verformten Transistoren durch eine geneigte Voramorphisierung

Номер: DE102005057074B4

Verfahren mit: Bilden eines im Wesentlichen amorphisierten Gebiets in einer anfänglich kristallinen Halbleiterschicht benachbart zu einer und sich erstreckend unter eine Gateelektrode, die über der Halbleiterschicht gebildet ist, mittels eines geneigten Implantationsprozesses; Bilden einer verspannten Schicht mit einer spezifizierten inneren Spannung von einem Giga Pascal oder mehr zumindest über einem Bereich der Halbleiterschicht, der die Gateelektrode enthält, um damit mechanische Spannung in die Halbleiterschicht zu übertragen; und Rekristallisieren des im Wesentlichen amorphisierten Gebiets bei Anwesenheit der verspannten Schicht durch Ausführen einer Wärmebehandlung.

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11-06-2014 дата публикации

High selectivity nitride etch process

Номер: GB0201407290D0
Автор:
Принадлежит:

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07-11-2001 дата публикации

A silicon nitride sidewall spacer

Номер: GB0002362028A
Принадлежит:

A sidewall spacer 20 is formed in a CMOS device by depositing a layer of silicon nitride 18 on a wafer 10 and anisotropically etching away the silicon nitride layer 18 with a chorine-based plasma etchant. A thin layer of silicon oxide 17 may be formed prior to the deposition of silicon nitride 18. The etchant may comprise chlorine, hydrogen bromide, and a mixture of helium and oxygen.

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24-06-2009 дата публикации

Stressed field effect transistor and methods for its fabrication

Номер: GB2455669A
Принадлежит:

A stressed field effect transistor (40) and methods for its fabrication are provided. The field effect transistor (40) comprises a silicon substrate (44) with a gate insulator (54) overlying the silicon substrate. A gate electrode (62) overlies the gate insulator and defines a channel region (68) in the silicon substrate underlying the gate electrode. A first silicon germanium region (76) having a first thickness is embedded in the silicon substrate and contacts the channel region. A second silicon germanium region (82) having a second thickness greater than the first thickness and spaced apart from the channel region is also embedded in the silicon substrate.

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23-06-1999 дата публикации

Method of fabricating a semiconductor device

Номер: GB0009909490D0
Автор:
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11-08-2021 дата публикации

Methods for forming multiple gate sidewall spacer widths

Номер: GB2591787A
Автор: NICOLAS PONS, Nicolas Pons
Принадлежит:

A method of forming gate sidewall spacers of two different widths, the method comprising: providing a semiconductor substrate 10; providing first and second gate structures 11,12 having respective sidewalls; blanket depositing a first nitride layer; anisotropically etching the first nitride layer to form a first nitride sidewall spacer 15 on each gate structure; removing the first nitride sidewall spacer 15 from the first gate structure 11; blanket depositing a second nitride layer; anisotropically etching the second nitride layer to form a second nitride sidewall spacer 22 on each gate structure. Also disclosed is a semiconductor device comprising the gate structures with the above sidewall spacers. Further disclosed is a method as above with N total gate structures, where the steps of blanket depositing the nitride layer, anisotropically etching said layer to form spacers are performed on all N structures and the step of removing the spacers is performed then on a subgroup of the structures ...

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29-03-2004 дата публикации

Semiconductor component and method of manufacture

Номер: AU2003265862A8
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30-11-2004 дата публикации

SELF-ADDRESSABLE SELF-ASSEMBLING MICROELECTRONIC SYSTEMS ANDDEVICES FOR MOLECULAR BIOLOGICAL ANALYSIS AND DIAGNOSTICS

Номер: CA0002175483C
Принадлежит: NANOGEN, INC., NANOGEN INC

A self-addressable, self-assembling microelectronic device is designed and f abricated to actively carry out and control multi-step and multiplex molecular biological reactions in microscopic formats. These reactions include nucleic acid hybridization, antibody/a ntigen reaction, diagnostics, and biopolymer synthesis. The device can be fabricat ed using both microlithographic and micro-machining tech niques. The device can electronically control the transport and attachment of specif ic binding entities to specific micro-locations. The sp ecific binding entities include molecular biological molecules such as nucleic acids and po lypeptides. The device can subsequently control the tra nsport and reaction of analytes or reactants at the addressed specific micro-locations. The device is able to concentrate analytes and reactan ts, remove non-specifically bound molecules, provide stringency control for DNA hybridi zation reactions, and improve the detection of analytes. The device can be electronically ...

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21-11-2012 дата публикации

Semiconductor apparatus and manufacturing method thereof

Номер: CN102789986A
Автор: Xu Weizhong
Принадлежит:

The invention discloses a semiconductor apparatus and a manufacturing method of the semiconductor apparatus. The method comprises the steps of: forming a grid on a substrate; forming an overlapping layer which orderly includes a first material layer, a second material layer and a third material layer from inside to outside to cover the substrate surface, the upper surface of the grid, and two lateral walls of the grid; etching the overlapping layer to form lateral wall spacers on the two lateral walls of the grid, wherein each lateral wall spacer comprises residual parts of the first material layer, the second material layer and the third material layer; carrying out ion injection to respectively form a source area and a drain area at two sides of the grid; removing part of the residual part or all residual part of the third material layer; carrying out a pre-cleaning process, wherein the partial or all residual part of the second material is removed, and silicide is formed at the upper ...

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12-05-2020 дата публикации

Semiconductor device and method for forming pattern for semiconductor device

Номер: CN0111146183A
Автор:
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06-06-2017 дата публикации

With asymmetric source/drain structure in the FinFET and its manufacturing method

Номер: CN0104037226B
Автор:
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15-01-2019 дата публикации

A memory structure and a method for manufacture that same

Номер: CN0109216363A
Принадлежит:

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03-12-2019 дата публикации

Semiconductor device

Номер: CN0110534570A
Автор:
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04-11-2009 дата публикации

Semiconductor component and method of manufacturing the same

Номер: CN0100557818C
Принадлежит:

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06-05-2009 дата публикации

Semiconductor device and its forming method

Номер: CN0100485964C
Автор:
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13-05-2005 дата публикации

SEMICONDUCTOR DEVICE ON SOI SUBSTRATE AND METHOD OF MANUFACTURE

Номер: FR0002827708B1
Принадлежит:

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30-09-2005 дата публикации

TRANSISTOR AND MANUFACTORING PROCESS

Номер: FR0002831713B1
Принадлежит:

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26-08-2005 дата публикации

MANUFACTORING PROCESS Of a DEVICE SEMICONDUCTOR HAS

Номер: FR0002779008B1
Принадлежит:

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05-08-2016 дата публикации

METHOD OF FORMING SPACERS OF A GATE OF A TRANSISTOR

Номер: FR0003023971B1
Автор: POSSEME NICOLAS

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21-06-2019 дата публикации

TRANSISTOR REGIONS NEATLY ACCESS MASTERY

Номер: FR0003050315B1
Принадлежит:

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03-07-2020 дата публикации

TRANSISTOR COMPRISING AN ENLARGED GATE

Номер: FR0003069376B1
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24-11-2017 дата публикации

"PRODUCTION METHOD ON THE SAME SUBSTRATE OF TRANSISTORS WITH DIFFERENT CHARACTERISTICS"

Номер: FR0003051597A1

L'invention porte notamment sur un procédé de réalisation sur un même substrat (100) d'au moins un premier transistor et d'au moins un deuxième transistor présentant des caractéristiques différentes, le procédé comprenant au moins les étapes suivantes : - Réalisation sur un substrat (100) d'au moins un premier motif (200) de grille et d'au moins un deuxième motif (300) de grille; - Dépôt sur le premier et le deuxième motif (200, 300) de grille d'au moins : une première couche de protection (500) et une deuxième couche de protection (600) surmontant la première couche de protection (500) et faite en un matériau différent de celui de la première couche de protection (500) et; - Masquage du deuxième motif (300) de grille par une couche de masquage (700) ; - Gravure isotrope de la deuxième couche de protection (600) ; - Retrait de la couche de masquage (700); - Gravure anisotrope de la deuxième couche de protection (600) sélectivement à la première couche de protection (500).

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25-05-2018 дата публикации

METHOD FOR PRODUCING A SPILLOVER-GATE FET

Номер: FR0003059150A1

Procédé de réalisation d'un transistor FET (103), comportant les étapes suivantes : - réalisation, sur une couche semi-conductrice cristalline, d'une couche diélectrique de grille sur laquelle est disposée une couche conductrice de grille, - gravure de la couche conductrice telle qu'une portion restante de cette couche recouvre entièrement une première portion (120) semi-conductrice formant une zone active et une deuxième portion semi-conductrice adjacente à la zone active, - implantation d'atomes et/ou de dopants dans la couche semiconductrice , amorphisant le semi-conducteur autour de la première portion et celui de la deuxième portion, - gravure de la portion restante de la couche conductrice et de la couche diélectrique selon un motif de grille recouvrant partiellement la première portion et la deuxième portion, formant la grille (122) et un débordement de grille, - gravure du semi-conducteur amorphe.

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02-05-2003 дата публикации

TRANSISTOR AND MANUFACTORING PROCESS

Номер: FR0002831713A1
Принадлежит:

Dispositif à semiconducteur, caractérisé en ce qu'il comprend : un substrat (4); un élément à semiconducteur incluant (a) une électrode de grille (79) formée sur une surface principale du substrat (4), avec une pellicule d'isolation de grille (78) interposée entre elles, et s'étendant dans une direction prédéterminée, (b) une première paroi latérale (83) formée sur chaque surface latérale de l'électrode de grille (79), (c) une région de corps (88) formée dans le substrat (4) sous l'électrode de grille (79), et (d) une paire de régions de source/drain (76) formées dans le substrat (4), avec la région de corps (48) disposée entre la paire de régions de source/ drain (76); une pellicule d'isolation inter-couche (90) formée sur le substrat (4) pour recouvrir l'élément à semiconducteur; et une ligne d'interconnexion de grille (92) en contact avec la surface supérieure de l'électrode de grille (79) et s'étendant dans la direction prédéterminée, cette ligne d'interconnexion de grille (92) étant ...

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19-05-2020 дата публикации

INTEGRATED CIRCUIT WITH SIDEWALL SPACERS FOR GATE STACKS

Номер: KR0102112641B1
Автор:
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31-03-2010 дата публикации

Method of fabricating the semiconductor device having gate spacer layer with uniform thickness

Номер: KR0100950473B1
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14-08-2014 дата публикации

TECHNIQUE FOR PROVIDING STRESS SOURCES IN TRANSISTORS IN CLOSE PROXIMITY TO A CHANNEL REGION BY RECESSING DRAIN AND SOURCE REGIONS

Номер: KR0101430703B1
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29-04-2013 дата публикации

Strained silicon, gate engineered Fermi-FETs

Номер: KR0101258864B1
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28-09-2005 дата публикации

SEMICONDUCTOR DEVICE HAVING SALICIDE LAYERS AND METHOD OF FABRICATING THE SAME

Номер: KR0100517555B1
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06-01-2011 дата публикации

STRAINED CHANNEL FET USING SACRIFICIAL SPACER

Номер: KR0101006306B1
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10-07-2008 дата публикации

Flash Memory Device and Method of Manufactruing the same

Номер: KR0100845720B1
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09-05-2011 дата публикации

SELF-ALIGNED PROCESS FOR NANOTUBE/NANOWIRE FETS

Номер: KR0101033445B1
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18-01-2018 дата публикации

반도체 디바이스 내에 자기-정렬 컨택을 제조하기 위한 방법

Номер: KR0101809349B1

... 반도체 디바이스는, 기판 위에 배치된 게이트 구조체, 및 게이트 구조체의 측벽들 둘 모두 상에 배치된 측벽 스페이서들을 포함한다. 측벽 스페이서들은, 게이트 구조체로부터 이러한 순서로 적층된 제 1 내지 제 4 스페이서 층들을 포함하여 적어도 4개의 스페이서 층들을 포함한다.

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22-04-2008 дата публикации

SEMICONDUCTOR DEVICE AND A METHOD FOR MANUFACTURING THE SAME, TO IMPROVE A DEGREE OF INTEGRATION BY SECURING A CONTACT REGION

Номер: KR0100824532B1
Автор: PARK, JIN HA
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PURPOSE: A semiconductor device and a method for manufacturing the same are provided to improve characteristics by forming a spacer with a double structure of an oxide layer and a nitride layer. CONSTITUTION: A gate insulating layer(20), a gate electrode(21), and an LDD region(30) are formed on a semiconductor substrate(10) including an isolation layer. A spacer of a double insulating layer structure is formed on the gate electrode. A source/drain region(70) is formed by using the spacer as a mask. A lateral surface of the gate electrode in contact with the insulating layer and an upper part of the LDD region are exposed by etching the insulating layer positioned inside the spacer. A salicide layer(80,81) is formed in the gate electrode and the source/drain regions. The spacer is removed. An interlayer dielectric(90) is formed on the salicide layer. A contact(100) connected to the salicide layer is formed by etching the interlayer dielectric. © KIPO 2008 ...

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05-11-2010 дата публикации

SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE

Номер: KR0100992180B1
Автор:
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10-01-1995 дата публикации

Номер: KR19950000141B1
Автор:
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17-04-2012 дата публикации

SEMICONDUCTOR DEVICE FOR REDUCING AN INCREASE OF CONTACT RESISTANCE AND A MANUFACTURING METHOD THEREOF

Номер: KR1020120036185A
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PURPOSE: A semiconductor device and a manufacturing method thereof are provided to prevent process failure by including an etching stop pattern which covers source/drain regions under the upper surface of a metal gate electrode. CONSTITUTION: A metal gate electrode(163) is laminated by arranging a gate insulating film on a semiconductor substrate(100). Spacer structures are arranged on the semiconductor substrate. A source/drain region is formed within the semiconductor substrate. An etching stop pattern(141) comprises a sidewall part and a bottom part for covering the source/drain region. The sidewall part covers a part of a sidewall of the spacer structure by being extended from the bottom part. COPYRIGHT KIPO 2012 ...

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28-11-2018 дата публикации

GATE STRUCTURE FOR SEMICONDUCTOR DEVICE

Номер: KR1020180127156A
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A method for forming a semiconductor device includes forming a source/drain region and spacers on a substrate. The method further includes forming an etching stop layer on the spacers and the source/drain region; and forming a gate structure between the spacers. The method further includes: etching back the gate structure; etching back the spacers and an etching back layer; and forming a gate capping structure on the etched back gate structure, the spacers, and the etching stop layer. COPYRIGHT KIPO 2019 ...

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28-05-2015 дата публикации

확장 소스-드레인 MOS 트랜지스터 및 형성 방법

Номер: KR1020150058513A
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... 트랜지스터 및 이를 제조하는 방법은 기판, 기판 위의 도전성 게이트, 및 도전성 게이트 아래의 기판 내 채널 영역을 포함한다. 제1 및 제2 절연 스페이서가 도전성 게이트의 제1 및 제2 측면에 측방향으로 인접한다. 기판 내의 소스 영역은 도전성 게이트의 제1 측면 및 제1 스페이서에 인접하지만 그들로부터 측방향으로 이격되고, 기판 내의 드레인 영역은 도전성 게이트의 제2 측면 및 제2 스페이서에 인접하지만 그들로부터 측방향으로 이격된다. 제1 및 제2 LD 영역은 기판 내에 있고 채널 영역과 소스 또는 드레인 영역 사이에서 각각 측방향으로 연장되며, 각각은 그의 일부가 제1 및 제2 스페이서 아래에도 또한 도전성 게이트의 아래에도 배치되지 않고, 각각은 도펀트 농도가 소스 또는 드레인 영역의 것보다 작다.

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25-01-2000 дата публикации

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

Номер: KR20000006579A
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PURPOSE: A semiconductor device is provided to reduce a parasite capacitance and a parasite resistance of the source/drain region by reducing an area occupied by a source/drain region. CONSTITUTION: The semiconductor device comprises an isolation region(101), an active region(102), a gate oxide layer(103), a source/drain region(106), and an electrode(104). The active region(102) is contacted with the gate oxide layer(103) at a first plane, and a part of the source/drain region(106) is disposed at a top of the first plane. The electrode(104) is contacted with the source/drain region(106) at a second plane. The second plane has prominence and depression, and is disposed so as to have a predetermined angle against the first plane. COPYRIGHT 2000 KIPO ...

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28-12-2018 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Номер: KR1020180137861A
Автор: KIM, JU YOUN
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Provided is a semiconductor device capable of improving reliability by improving device isolation characteristics, and improving device performance by improving design suitability. The semiconductor device comprises: a fin-shaped pattern on a substrate; a first gate structure including a first gate spacer and a first gate insulating layer extending along a sidewall of the first gate spacer, on the fin-shaped pattern; a second gate structure spaced apart from the first gate structure and including a second gate spacer and a second gate insulating layer extending along a sidewall of the second gate spacer, on the fin-shaped pattern; a pair of dummy spacers spaced apart from each other between the first gate structure and the second gate structure; an isolation trench including a sidewall defined by the fin-shaped pattern and the dummy spacers, between the dummy spacers; a device isolation layer disposed on a portion of the sidewall of the isolation trench; and a connection conductive pattern ...

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28-12-2016 дата публикации

비 평면형 트랜지스터용의 텅스텐 게이트

Номер: KR1020160150123A
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... 본 발명은 비 평면형 트랜지스터를 갖는 마이크로 전자 장치의 제조 분야에 관한 것이다. 본 설명의 실시 형태는 비 평면형 NMOS 트랜지스터 내의 게이트의 형성에 관한 것인데, 여기서 알루미늄, 티타늄 및 탄소의 조성물 등의 NMOS 일함수 물질은, 티타늄-함유 게이트 충전 장벽과 함께 사용될 수 있어서, 비 평면형 NMOS 트랜지스터 게이트의 게이트 전극의 형성 시에 텅스텐 함유 도전성 물질의 사용을 용이하게 한다.

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04-10-2002 дата публикации

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

Номер: KR20020075189A
Автор: KUNIKIYO TATSUYA
Принадлежит:

PURPOSE: To obtain a method for manufacturing a semiconductor device in which the variation of a threshold voltage caused by breakthrough a dopant can be suppressed appropriately. CONSTITUTION: An amorphous silicon film 21 is heavily doped with hydrogen ions 40. Consequently, the amorphous silicon film 21 is formed in a hydrogen ion implantation layer 41. It is then heat-treated and columnar grains are formed in the amorphous silicon film 21 except a part where the hydrogen ion implantation layer 41 is formed. On the other hand, columnar grains are formed in the hydrogen ion implantation layer 41. A columnar grain layer 42 has a large number of grain boundaries extending in many directions, e.g. a grain boundary extending along the thickness direction of a polysilicon film 44a, a grain boundary extending along the direction other than the thickness direction of the polysilicon film 44a. © KIPO & JPO 2003 ...

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29-08-2001 дата публикации

METHOD FOR FORMING MOSFET DEVICE

Номер: KR20010082029A
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PURPOSE: To provide a metal oxide film semiconductor field effect type(MOSFET) device, which has a gate insulator of high permittivity (permittivity higher than 7), low overlap capacity (at most 0.35 fF/μm) and a channel length shorter than the gate length as defined by lithography. CONSTITUTION: This method contains a damascene treatment process and a chemical oxide removal(COR) process. In the COR process, a large tape is formed on a pad oxide layer. When the pad oxide layer is combined with the gate insulator of high permittivity, low overlap capacity, short channel length and superior device characteristic can be realized, as compared with an MOSFET device which is formed by using a normal complementary metal oxide film semiconductor(CMOS) method. © KIPO & JPO 2002 ...

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20-06-2006 дата публикации

MOS TRANSISTOR SUPPRESSION OF DETERIORATION OF CHANNEL HOT CARRIER AND FABRICATING METHOD THEREOF TO EFFECTIVELY SUPPRESS PENETRATION AND DIFFUSION PHENOMENA OF BORON, ESPECIALLY IN P-CHANNEL MOS TRANSISTOR

Номер: KR1020060067374A
Автор: BYUN, DONG IL
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PURPOSE: A MOS transistor is provided to control deterioration of channel hot carriers by dispersing the distribution of an electric field parallel with a channel to the entire part of a drain junction. CONSTITUTION: A gate insulation layer(210) and a gate conductive layer(220) are sequentially disposed on a channel region of a semiconductor substrate(200). A poly oxide layer(230) is formed on the sidewall of the gate conductive layer. A gate spacer layer(250) is disposed on the sidewall of the gate insulation layer and the gate conductive layer. A cap oxide layer(240) is formed between the poly oxide layer and the gate spacer layer. A deep source/drain extension region(261) is formed in the semiconductor substrate, confined by both sidewalls of the gate conductive layer and having the first depth which is a source/drain junction depth of an LDD(lightly doped drain) structure. The first deep source/drain region(262) is formed in the semiconductor substrate adjacent to the deep source/drain ...

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04-02-2016 дата публикации

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Номер: KR1020160013459A
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According to the present invention, a method for manufacturing a semiconductor device includes forming a gate pattern on a semiconductor substrate; forming an amorphous region on a side of the gate pattern by injecting amorphizatoin ions into the semiconductor substrate; forming a recess region by removing the amorphous region; and forming a source/drain pattern which is filled in the recess region. The etch rate of the amorphous region in a first direction is the same as that of the amorphous region in a second direction. The first direction may face the [111] crystal plane of the semiconductor substrate. COPYRIGHT KIPO 2016 ...

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27-05-2019 дата публикации

Номер: KR1020190056907A
Автор:
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16-07-2008 дата публикации

OXIDE ETCH WITH NH3-NF3 CHEMISTRY CAPABLE OF ETCHING SELECTIVELY OXIDES ACCORDING TO THE SAME ETCH RATIO

Номер: KR1020080066614A
Принадлежит:

PURPOSE: An oxide etch with NH3-NF3 chemistry is provided to remove uniformly and/or selectively one or more oxides from a surface of a substrate using an etch gas mixture. CONSTITUTION: A loading process is performed to load a substrate(110) into a vacuum chamber(100). A surface of the substrate has a structure including the oxide. A cooling process is performed to cool the substrate to the first temperature. Active species of an etching gas mixture are generated within the vacuum chamber. The etching gas mixture includes a first gas and a second gas. A ratio of the first gas and the second gas is determined by a desired removal rate. An exposure process is performed to expose the structure on the surface of the substrate to the active species to form a film on the structure. A heating process is performed to heat the substrate in order to vaporize the film formed on the structure. A removing process is performed to remove the vaporized film from the vacuum chamber. © KIPO 2008 ...

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22-06-2018 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Номер: KR1020180068844A
Принадлежит:

In a method for forming a semiconductor device including a fin field effect transistor (FinFET), a first sacrificial layer is formed on a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is patterned, thereby forming an opening. A first liner layer is formed on the isolation insulating layer on the bottom of the opening and at least a latera side of the patterned first sacrificial layer. After the first liner layer is formed, a dielectric layer is formed in the opening. After the dielectric layer is formed, the patterned first sacrificial layer is removed, thereby forming a contact opening on the source/drain structure. A conductive layer is formed in the contact opening. COPYRIGHT KIPO 2018 ...

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10-06-2011 дата публикации

TRANSISTOR OF A SEMICONDUCTOR DEVICE AND A METHOD FOR FORMING THE SAME CAPABLE OF PREVENTING THE OUT-DIFFUSION OF BORON BY ELIMINATING HYDROGEN FROM AN OXIDE FILM

Номер: KR1020110063203A
Автор: NAM, KI BONG
Принадлежит:

PURPOSE: The transistor of a semiconductor device and a method for forming the same are provided to increase the current of a PMOS by reducing the tensile stress applied to a PMOS transistor. CONSTITUTION: A gate(24) is formed in the NMOS region and the PMOS region of a semiconductor substrate. A gate spacer(30) is formed at the sidewall of the gate. A junction region is formed in the NMOS region by implanting ions into the NMOS region. An oxide film(40) is deposited on the front surface of the semiconductor substrate including the gate. Hydrogen is eliminated from the oxide film and the gate spacer. The oxide film is eliminated from the PMOS region. The junction region is formed in the PMOS region by implanting ions into the PMOS region. COPYRIGHT KIPO 2011 ...

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26-09-2017 дата публикации

SEMICONDUCTOR DEVICE

Номер: KR1020170107626A
Принадлежит:

The present invention provides a semiconductor device with improved electrical properties. According to an embodiment of the present invention, the semiconductor device comprises: a substrate including an active area extended in a first direction; bit line structures crossing the active area in a second direction intersecting the first direction; a first spacer disposed on one side wall of the bit line structures on the substrate; and a storage node contact disposed on an end part of the active area between the adjacent bit line structures. The first spacer includes: a first part between each of the bit line structures and the storage node contact; a second part between the first part and the storage node contact; and a third part between the first part and the second part. The minimum vertical thickness of the first part is greater than the maximum vertical thickness of the third part, and the maximum vertical thickness of the third part can be greater than the maximum vertical thickness ...

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22-06-2018 дата публикации

ETCHING COMPOSITION AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE BY USING SAME

Номер: KR1020180068591A
Принадлежит:

The present invention provides an etching composition which removes a silicon-germanium film with a high selectivity ratio in a laminated structure including a silicon film and the silicon-germanium film. The etching composition for selectively etching silicon-germanium (SiGe) contains a peracetic acid mixture, a fluorine compound, an acetate based organic solvent, and water. COPYRIGHT KIPO 2018 ...

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21-11-2003 дата публикации

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Номер: KR20030089082A
Принадлежит:

PURPOSE: A method for manufacturing a semiconductor device is provided to be capable of preventing the oxidation of a metal layer contained in a gate electrode and restraining the stress concentrated at the lower corner portion of the gate electrode by forming a PETEOS(Plasma Enhanced Tetra Ethyl Ortho Silicate) layer before depositing a nitride layer. CONSTITUTION: After forming a gate oxide layer(22) on a semiconductor substrate(21), a gate electrode is formed at the upper portion of the gate oxide layer. At this time, the gate electrode includes at least a metal layer. A PETEOS layer is formed at the entire surface of the resultant structure at a predetermined low temperature. Then, the PETEOS layer is hardened by carrying out a heat treatment. A PETEOS spacer(31) is formed at both sidewalls of the gate electrode by selectively etching the hardened PETEOS layer. Preferably, the PETEOS layer is formed by carrying out a plasma chemical deposition process. © KIPO 2004 ...

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16-10-2017 дата публикации

GATE ELECTRODE STRUCTURE AND HIGH VOLTAGE SEMICONDUCTOR DEVICE INCLUDING SAME

Номер: KR1020170114703A
Принадлежит:

The present invention provides a gate electrode structure capable of reducing a parasitic capacitance between a gate electrode and a drift area, and a high voltage semiconductor device including the same. The high voltage semiconductor device comprises: the gate electrode structure disposed on a substrate; a first drift area disposed adjacent to one side of the gate electrode structure; a drain area electrically connected with the first drift area; and a source area disposed adjacent to the other side of the gate electrode structure. The gate electrode structure comprises: a gate insulating film pattern disposed on the substrate; a gate electrode disposed on the gate insulating film pattern, and having an edge part adjacent to the first drift area and at least one aperture formed in the edge part; and at least one insulating pattern disposed in the at least one aperture. COPYRIGHT KIPO 2017 ...

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15-12-2016 дата публикации

SEMICONDUCTOR DEVICE

Номер: KR1020160143945A
Принадлежит:

The present invention relates to a semiconductor device and a manufacturing method thereof. Provided is the semiconductor device which includes an active pattern which protrudes from a substrate, a gate electrode which crosses the active pattern, a gate spacer on the sidewalls of the gate electrode, source/drain regions which are arranged on the active patterns of both sides of the gate electrode, wherein each of the source/drain regions includes a part which is exposed by the gate spacer and a second part which is extended from the first part and is covered by the gate spacer, and a remaining space which is interposed between the gate spacer and both sidewalls of the second part to face each other. Accordingly, the present invention can improve electrical properties of the semiconductor device. COPYRIGHT KIPO 2016 ...

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24-07-2017 дата публикации

SEMICONDUCTOR APPARATUS AND MANUFACTURING METHOD THEREOF

Номер: KR1020170085177A
Принадлежит:

Provided is a semiconductor apparatus having a simplified structure. The semiconductor apparatus comprises: an element separation membrane provided on a substrate and defining first and second sub-active patterns; first and second gate electrodes crossing the first and second sub-active patterns respectively; and a separation structure provided on the element separation membrane between the first and second sub-active patterns, wherein the first and second sub-active patterns are extended in a first direction and are spaced apart from each other in the first direction. The element separation membrane includes a diffusion break region defined as an element separation membrane part between the first and second sub active patterns, and the separation structure covers an upper surface of the diffusion break region. COPYRIGHT KIPO 2017 ...

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15-09-2000 дата публикации

LAMINATED ASSEMBLY FOR ACTIVE BIOELECTRONIC DEVICES

Номер: KR20000057400A
Принадлежит:

PURPOSE: Devices containing active electrodes especially adapted for electrophoretic transport of nucleic acids, their hybridization and analysis, are provided. CONSTITUTION: Methods of manufacture and devices for performing active biological operations utilize laminated structures(30). A first planar sample support(50) includes at least one sample through hole(56) a planar electrode(32,70) is disposed adjacent the first planar sample support(50), and includes an electrode through region(38), a second planar support(40) includes a vent through hole(48), the planar electrode(32) being in a laminated relationship between the first planar sample support(50) and the second planar support(40), further characterized in that the sample through hole(56), electrode through hole(38) and vent through hole(48) are in overlapping arrangement. Preferably, some or all of the through holes, through regions and vent through holes are aligned. COPYRIGHT 2000 KIPO ...

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11-02-2019 дата публикации

집적회로 장치

Номер: KR1020190013342A
Принадлежит:

... 집적회로 장치는, 핀형 활성 영역을 갖는 기판; 상기 기판 상에서 상기 핀형 활성 영역과 교차하는 게이트 구조물; 상기 게이트 구조물의 양 측벽 상에 배치되는 스페이서 구조물로서, 상기 게이트 구조물의 양 측벽의 적어도 일부분과 접촉하는 제1 스페이서층과, 상기 제1 스페이서층 상에 배치되며 상기 제1 스페이서층보다 낮은 유전 상수를 갖는 제2 스페이서층을 포함하는 스페이서 구조물; 상기 게이트 구조물 양 측에 배치되는 소스/드레인 영역; 및 상기 소스/드레인 영역과 전기적으로 연결되는 제1 콘택 구조물로서, 상기 소스/드레인 영역 상에 배치되는 제1 콘택 플러그와, 상기 제1 콘택 플러그 상에 배치되는 제1 금속성 캡핑층을 포함하는 상기 제1 콘택 구조물을 포함한다.

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11-11-2009 дата публикации

METHOD FOR FORMING A PATTERN OF A SEMICONDUCTOR DEVICE AND A METHOD FOR FORMING A TRANSISTOR USING THE SAME, CAPABLE OF FORMING A PATTERN WITH LOW RESISTANCE

Номер: KR1020090116383A
Принадлежит:

PURPOSE: A method for forming a pattern of a semiconductor device and a method for forming a transistor using the same are provided to obtain high operation speed and reliability by forming a capping layer along a conductive film pattern and a surface of the substrate with an atom layer stacking method. CONSTITUTION: A conductive film is formed on a substrate(100). A conductive film pattern(110) is formed by patterning the conductive film. An oxide layer(112) is formed on a part of the conductive film pattern and the substrate by heating the conductive film pattern. A capping layer(114) is formed along the surface of the substrate and the conductive film pattern with the atom layer stacking method. The conductive layer is formed by stacking a polysilicon layer(102a) and a metal layer. The metal layer(104a) is formed between the polysilicon layer and the metal layer. COPYRIGHT KIPO 2010 ...

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21-06-2006 дата публикации

CMOS SEMICONDUCTOR DEVICES HAVING ELEVATED SOURCE CAPABLE OF OPTIMIZING OPERATING CHARACTERISTICS OF NMOS AND PMOS TRANSISTORS AND METHOD FOR FABRICATING THE SAME

Номер: KR1020060069561A
Принадлежит:

PURPOSE: A CMOS semiconductor devices having an elevated source and a method for fabricating the same are provided to optimize operating characteristics of NMOS and PMOS transistors by preventing an excessive diffusion of low-concentration source/drain regions. CONSTITUTION: An isolation layer is provided on a semiconductor substrate to define first and second active regions(3a,3b) and a first gate pattern(8a) crosses over the first active region. A first elevated source region(17s') and a first elevated drain region(17d') are disposed at both sides of the first gate pattern, being provided on the first active region. A first gate spacer(28a) is interposed between the first gate pattern and the first elevated source/drain region and a second gate pattern(8b) crosses over the second active region. A second elevated source region(17s") and a second elevated drain region(17d") are disposed at both sides of the second gate pattern, being provided on the second active region. A second gate spacer ...

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09-01-2003 дата публикации

METHOD FOR MANUFACTURING SDRAM

Номер: KR20030002908A
Автор: SUNG, YANG SU
Принадлежит:

PURPOSE: A fabrication method of an SDRAM(Synchronous Dynamic Random Access Memory) is provided to improve refresh property and to reduce a leakage current due to stress of a nitride layer without using additional processes. CONSTITUTION: A gate which is sequentially stacked on a gate insulating layer(44), a polysilicon layer(46) and a metal film(48) is formed on a substrate(40). After forming an insulating layer(44) on the gate, the first oxide layer(52) is formed at both sidewalls of the polysilicon layer(46). The first nitride spacer(54) is formed at both sidewalls of the gate and the insulating layer(44). A source/drain(56) is formed in the substrate by implanting dopants and annealing at the atmosphere of oxygen, and the second oxide layer is simultaneously formed on the surface of the substrate(40). After forming the second nitride spacer(60), a deep source/drain(62) is formed in the substrate by implanting dopants and annealing. © KIPO 2003 ...

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01-10-2008 дата публикации

Method for forming silicon/germanium containing drain/source regions in transistors with reduced silicon/germanium loss

Номер: TW0200839950A
Принадлежит:

By providing a protection layer on a silicon/germanium material of high germanium concentration, a corresponding loss of strained semiconductor material may be significantly reduced or even completely avoided. The protection layer may be formed prior to critical cleaning processes and may be maintained until the formation of metal silicide regions. Hence, high performance gain of P-type transistors may be accomplished without requiring massive overfill during the selective epitaxial growth process.

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01-06-2011 дата публикации

Semiconductor device and method for manufacturing the same

Номер: TW0201119038A
Принадлежит:

An object is to reduce the resistance of each member included in a transistor, to improve ON current of the transistor, and to improve performance of an integrated circuit. A semiconductor device including an n-channel FET and a p-channel FET which are provided over a single crystal semiconductor substrate with an insulating layer interposed therebetween and are isolated by an element isolation insulating layer. In the semiconductor device, each FET includes a channel formation region including a semiconductor material, a conductive region which is in contact with the channel formation region and includes the semiconductor material, a metal region in contact with the conductive region, a gate insulating layer in contact with the channel formation region, a gate electrode in contact with the gate insulating layer, and a source or drain electrode partly including the metal region.

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01-05-2011 дата публикации

Semiconductor device comprising metal gates and a silicon containing resistor formed on an isolation structure

Номер: TW0201115719A
Принадлежит:

In a semiconductor device comprising sophisticated high-k metal gate structures formed in accordance with a replacement gate approach, semiconductor-based resistors may be formed above isolation structures substantially without being influenced by the replacement gate approach. Consequently, enhanced area efficiency may be achieved compared to conventional strategies, in which the resistive structures may have to be provided on the basis of a gate electrode metal, while, nevertheless, a low parasitic capacitance may be accomplished due to providing the resistive structures above the isolation structure.

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01-03-2017 дата публикации

High-mobility semiconductor source/drain spacer

Номер: TW0201709527A
Принадлежит:

Monolithic FETs including a majority carrier channel in a first high carrier mobility semiconductor material disposed over a substrate. While a mask, such as a gate stack or sacrificial gate stack, is covering a lateral channel region, a spacer of a high carrier mobility semiconductor material is overgrown, for example wrapping around a dielectric lateral spacer, to increase effective spacing between the transistor source and drain without a concomitant increase in transistor footprint. Source/drain regions couple electrically to the lateral channel region through the high-mobility semiconductor spacer, which may be substantially undoped (i.e. intrinsic). With effective channel length for a given lateral gate dimension increased, the transistor footprint for a given off-state leakage may be reduced or off-state source/drain leakage for a given transistor footprint may be reduced, for example.

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16-09-2015 дата публикации

FinFET device and method for manufacturing the same

Номер: TW0201535488A
Принадлежит:

The present disclosure relates to a method of forming a FinFET device having sidewalls spacers comprising an air gap that provides for a low dielectric constant, and an associated apparatus. In some embodiments, the method is performed by forming a fin of semiconductor material on a semiconductor substrate. A gate structure, having a gate dielectric layer and an overlying gate material layer, is formed at a position overlying the fin of semiconductor material. Sidewall spacers are formed at positions abutting opposing sides of the gate structure. Respective sidewall spacers have a first layer of insulating material abutting the gate structure and a second layer of insulating material separated from the first layer of insulating material by an air gap. By forming the FinFET device to have sidewall spacers with air gaps, the parasitic capacitance of the FinFET device and a corresponding RC time delay are decreased.

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16-01-2019 дата публикации

Semiconductor device and manufacturing method thereof

Номер: TW0201904032A
Автор: LEE KI-HONG, LEE, KI-HONG
Принадлежит:

A semiconductor device includes a stacked structure, channel layers passing through the stacked structure, a well plate located under the stacked structure, a source layer located between the stacked structure and the well plate, a connection structure coupling the channel layers to each other and including a first contact contacting the source layer and a second contact contacting the well plate, and an isolation pattern insulating the source layer and the well plate from each other.

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01-07-2021 дата публикации

Semiconductor device

Номер: TW202125828A
Принадлежит:

Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a first semiconductor channel member and a second semiconductor channel member over the first semiconductor channel member and a porous dielectric feature that includes silicon and nitrogen. In the semiconductor device, the porous dielectric feature is sandwiched between the first and second semiconductor channel members and a density of the porous dielectric feature is smaller than a density of silicon nitride.

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01-10-2020 дата публикации

Gate stacks for FinFET transistors

Номер: TW0202036918A
Принадлежит:

Embodiments herein describe techniques for a semiconductor device including a substrate and a FinFET transistor on the substrate. The FinFET transistor includes a fin structure having a channel area, a source area, and a drain area. The FinFET transistor further includes a gate dielectric area between spacers above the channel area of the fin structure and below a top surface of the spacers; spacers above the fin structure and around the gate dielectric area; and a metal gate conformally covering and in direct contact with sidewalls of the spacers. The gate dielectric area has a curved surface. The metal gate is in direct contact with the curved surface of the gate dielectric area. Other embodiments may be described and/or claimed.

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01-04-2021 дата публикации

Semiconductor device

Номер: TW202114230A
Принадлежит:

Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a substrate; a gate structure disposed over the substrate and over a channel region of the semiconductor device, wherein the gate structure includes a gate stack and spacers disposed along sidewalls of the gate stack, the gate stack including a gate dielectric layer and a gate electrode; a first metal layer disposed over the gate stack, wherein the first metal layer laterally contacts the spacers over the gate dielectric layer and the gate electrode; and a gate via disposed over the first metal layer.

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16-07-2021 дата публикации

Semiconductor device

Номер: TW202127662A
Принадлежит:

Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a substrate; semiconductor layers over the substrate, wherein the semiconductor layers are separate from each other and are stacked up along a direction generally perpendicular to a top surface of the substrate; a dielectric feature over and separate from the semiconductor layers; and a gate structure wrapping around each of the semiconductor layers, the gate structure having a gate dielectric layer and a gate electrode layer, wherein the gate dielectric layer interposes between the gate electrode layer and the dielectric feature and the dielectric feature is disposed over at least a part of the gate electrode layer.

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02-02-2012 дата публикации

Method and structure to improve formation of silicide

Номер: US20120028430A1
Принадлежит: International Business Machines Corp

A method begins with a structure having: a gate insulator on a silicon substrate between a gate conductor and a channel region within the substrate; insulating sidewall spacers on sidewalls of the gate conductor; and source and drain regions within the substrate adjacent the channel region. To silicide the gate and source and drain regions, the method deposits a metallic material over the substrate, the gate conductor, and the sidewalls, and performs a first heating process to change the metallic material into a metal-rich silicide at locations where the metallic material contacts silicon. The method removes the sidewall spacers, and performs a second heating process to change the metal-rich silicide into silicide having a lower metallic concentration than the metal-rich silicide. The silicide thus formed avoids being damaged by the spacer removal process.

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23-02-2012 дата публикации

Methods of forming memory cells, memory cells, and semiconductor devices

Номер: US20120043611A1
Принадлежит: Micron Technology Inc

A memory device and method of making the memory device. Memory device may include a storage transistor at a surface of a substrate. The storage transistor comprises a body portion between first and second source/drain regions, wherein the source/drain regions are regions of a first conductivity type. The storage transistor also comprises a gate structure that wraps at least partially around the body portion in at least two spatial planes. A bit line is connected to the first source/drain region and a word line is connected to the gate structure.

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15-03-2012 дата публикации

Transistor devices and methods of making

Номер: US20120061684A1
Принадлежит: International Business Machines Corp

In an embodiment, a method of fabricating a transistor device comprises: providing a semiconductor topography comprising a gate conductor disposed above a semiconductor substrate between a pair of dielectric spacers; anisotropically etching exposed regions of the semiconductor substrate on opposite sides of the dielectric spacers to form recessed regions in the substrate; oxidizing exposed surfaces of the substrate in the recessed regions to form an oxide thereon; removing the oxide from bottoms of the recessed regions while retaining the oxide upon sidewalls of the recessed regions; and isotropically etching the substrate such that the recessed regions undercut the pair of dielectric spacers.

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15-03-2012 дата публикации

Plasma etching apparatus, plasma etching method, and semiconductor device manufacturing method

Номер: US20120064726A1
Принадлежит: Tokyo Electron Ltd

There is provided a plasma etching apparatus provided for performing an etching in a desirable shape. The plasma etching apparatus includes a processing chamber 12 for performing a plasma process on a target substrate W; a gas supply unit 13 for supplying a plasma processing gas into the processing chamber 12; a supporting table positioned within the processing chamber 12 and configured to support the target substrate thereon; a microwave generator 15 for generating a microwave for plasma excitation; a plasma generation unit for generating plasma within the processing chamber 12 by using the generated microwave; a pressure control unit for controlling a pressure within the processing chamber 12; a bias power supply unit for supplying AC bias power to the supporting table 14; and a control unit for controlling the AC bias power by alternately repeating supply and stop of the AC bias power.

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12-04-2012 дата публикации

Method for manufacturing semiconductor device

Номер: US20120088359A1
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Example embodiments relate to a method for manufacturing a semiconductor device, wherein a metal gate electrode therein may be formed without a void in a lower portion of the metal gate electrode. The method may include providing a substrate, forming a dummy gate electrode on the substrate, forming a gate spacer on the substrate to be contiguous to the dummy gate electrode, forming a first recess by simultaneously removing a portion of the dummy gate electrode and a portion of the gate spacer, the first recess having an upper end wider than a lower end, forming a second recess by removing the dummy gate electrode remaining after forming the first recess, and forming a metal gate electrode by depositing a metal to fill the first and second recesses.

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19-04-2012 дата публикации

Method for fabricating mos transistors

Номер: US20120094460A1
Принадлежит: Individual

A method for fabricating a MOS transistor is disclosed. First, a semiconductor substrate having a gate thereon is provided. A spacer is then formed on the sidewall of the gate, and two recesses are formed adjacent to the spacer and within the semiconductor substrate. Next, the spacer is thinned, and epitaxial layer is grown in each of the two recesses. By thinning the spacer before the epitaxial layer is formed, the present invention could stop the epitaxial layer to grow against the sidewall of the spacer, thereby preventing problem such as Ion degradation.

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26-04-2012 дата публикации

Integrated Circuitry Comprising Nonvolatile memory Cells And Methods Of Forming A Nonvolatile Memory Cell

Номер: US20120097913A1
Автор: John K. Zahurak, Jun Liu
Принадлежит: Individual

An integrated circuit has a nonvolatile memory cell that includes a first electrode, a second electrode, and an ion conductive material there-between. At least one of the first and second electrodes has an electrochemically active surface received directly against the ion conductive material. The second electrode is elevationally outward of the first electrode. The first electrode extends laterally in a first direction and the ion conductive material extends in a second direction different from and intersecting the first direction. The first electrode is received directly against the ion conductive material only where the first and second directions intersect. Other embodiments, including method embodiments, are disclosed.

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31-05-2012 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20120135574A1
Автор: Naoyoshi Tamura
Принадлежит: Fujitsu Semiconductor Ltd

Aimed at providing a highly reliable semiconductor device appropriately increased in stress at the channel region so as to improve carrier injection rate, thereby dramatically improved in transistor characteristics, and made adaptable also to recent narrower channel width, and a method of manufacturing the same, and a method of manufacturing the same, a first sidewall composed of a stress film having expandability is formed on the side faces of a gate electrode, a second sidewall composed of a film having smaller stress is formed on the first sidewall, and a semiconductor, which is a SiC layer for example, is formed as being positioned apart from the first sidewall while placing the second sidewall in between.

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07-06-2012 дата публикации

Semiconductor device

Номер: US20120139055A1
Принадлежит: Panasonic Corp

A semiconductor device includes a first MIS transistor and a second MIS transistor. The first MIS transistor includes a first gate insulating film which is formed on a first active region of a semiconductor substrate and has a first high dielectric constant film, and a first gate electrode formed on the first gate insulating film. The second MIS transistor includes a second gate insulating film which is formed on a second active region of the semiconductor substrate and has a second high dielectric constant film, and a second gate electrode formed on the second gate insulating film. The second high dielectric constant film contains first adjusting metal. The first high dielectric constant film has a higher nitrogen concentration than the second high dielectric constant film, and does not contain the first adjusting metal.

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14-06-2012 дата публикации

Structure and method for mobility enhanced mosfets with unalloyed silicide

Номер: US20120146092A1
Принадлежит: International Business Machines Corp

While embedded silicon germanium alloy and silicon carbon alloy provide many useful applications, especially for enhancing the mobility of MOSFETs through stress engineering, formation of alloyed silicide on these surfaces degrades device performance. The present invention provides structures and methods for providing unalloyed silicide on such silicon alloy surfaces placed on semiconductor substrates. This enables the formation of low resistance contacts for both mobility enhanced PFETs with embedded SiGe and mobility enhanced NFETs with embedded Si:C on the same semiconductor substrate. Furthermore, this invention provides methods for thick epitaxial silicon alloy, especially thick epitaxial Si:C alloy, above the level of the gate dielectric to increase the stress on the channel on the transistor devices.

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14-06-2012 дата публикации

Method of fabricating an integrated circuit having a strain inducing hollow trench isolation region

Номер: US20120146152A1
Автор: Barry Dove
Принадлежит: STMicroelectronics lnc USA

A shallow trench isolation is formed in a semiconductor substrate adjacent a MOS transistor. The shallow trench is filled with a fill material while other processing steps are performed. The fill material is later removed through a thin well etched into layers above the trench, leaving the trench hollow. A thin strain inducing layer is then formed on the sidewall of the hollow trench. The well is then plugged, leaving the trench substantially hollow except for the thin strain inducing layer on the sidewall of the trench. The strain inducing layer is configured to induce compressive or tensile strain on a channel region of the MOS transistor and thereby to enhance conduction properties of the transistor.

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05-07-2012 дата публикации

Field effect transistor (fet) and method of forming the fet without damaging the wafer surface

Номер: US20120168834A1
Принадлежит: International Business Machines Corp

Disclosed are a field effect transistor structure and a method of forming the structure. A gate stack is formed on the wafer above a designated channel region. Spacer material is deposited and anisotropically etched until just prior to exposing any horizontal surfaces of the wafer or gate stack, thereby leaving relatively thin horizontal portions of spacer material on the wafer surface and relatively thick vertical portions of spacer material on the gate sidewalls. The remaining spacer material is selectively and isotropically etched just until the horizontal portions of spacer material are completely removed, thereby leaving only the vertical portions of the spacer material on the gate sidewalls. This selective isotropic etch removes the horizontal portions of spacer material without damaging the wafer surface. Raised epitaxial source/drain regions can be formed on the undamaged wafer surface adjacent to the gate sidewall spacers in order to tailor source/drain resistance values.

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05-07-2012 дата публикации

Method of manufacturing semiconductor device

Номер: US20120171864A1
Принадлежит: Fujitsu Semiconductor Ltd

The method of manufacturing the semiconductor device comprises the steps of forming a MOS transistor 26 including a gate electrode 16 and source/drain diffused layers 24 formed in the silicon substrate 10 on both sides of the gate electrode 16 , forming a NiPt film 28 over the silicon substrate 10 , covering the gate electrode 16 and the source/drain diffused layers 26 , making thermal processing to react the NiPt film 28 with the upper parts of the source/drain diffused layers 24 to form Ni(Pt)Si films 34 a, 34 b on the source/drain diffused layers 24 , and removing selectively the unreacted part of the NiPt film 28 using a chemical liquid of above 71° C. including 71° C. containing hydrogen peroxide and forming an oxide film on the surface of the Ni(Pt)Si films 34 a, 34 b.

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12-07-2012 дата публикации

Self-Aligned Contacts for High k/Metal Gate Process Flow

Номер: US20120175711A1
Принадлежит: International Business Machines Corp

A semiconductor structure is provided that includes a semiconductor substrate having a plurality of gate stacks located on a surface of the semiconductor substrate. Each gate stack includes, from bottom to top, a high k gate dielectric layer, a work function metal layer and a conductive metal. A spacer is located on sidewalls of each gate stack and a self-aligned dielectric liner is present on an upper surface of each spacer. A bottom surface of each self-aligned dielectric liner is present on an upper surface of a semiconductor metal alloy. A contact metal is located between neighboring gate stacks and is separated from each gate stack by the self-aligned dielectric liner. The structure also includes another contact metal having a portion that is located on and in direct contact with an upper surface of the contact metal and another portion that is located on and in direct contact with the conductive metal of one of the gate stacks. Methods of forming the semiconductor structure using a replacement gate and a non-replacement gate scheme are also disclosed.

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12-07-2012 дата публикации

Semiconductor structures and methods of manufacturing the same

Номер: US20120175713A1
Автор: Viorel C. Ontalus, Xi Li
Принадлежит: International Business Machines Corp

A semiconductor structure has embedded stressor material for enhanced transistor performance. The method of forming the semiconductor structure includes etching an undercut in a substrate material under one or more gate structures while protecting an implant with a liner material. The method further includes removing the liner material on a side of the implant and depositing stressor material in the undercut under the one or more gate structures.

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12-07-2012 дата публикации

Method of fabricating a device using low temperature anneal processes, a device and design structure

Номер: US20120180010A1
Принадлежит: International Business Machines Corp

A method of fabricating a device using a sequence of annealing processes is provided. More particularly, a logic NFET device fabricated using a low temperature anneal to eliminate dislocation defects, method of fabricating the NFET device and design structure is shown and described. The method includes forming a stress liner over a gate structure and subjecting the gate structure and stress liner to a low temperature anneal process to form a stacking force in single crystalline silicon near the gate structure as a way to memorized the stress effort. The method further includes stripping the stress liner from the gate structure and performing an activation anneal at high temperature on device.

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26-07-2012 дата публикации

Metal High-K Transistor Having Silicon Sidewall For Reduced Parasitic Capacitance, and Process to Fabricate Same

Номер: US20120187506A1
Принадлежит: International Business Machines Corp

A method forms a metal high dielectric constant (MHK) transistor and includes: providing a MHK stack disposed on a substrate, the MHK stack including a first layer of high dielectric constant material, a second overlying layer, and a third overlying layer, selectively removing only the second and third layers, without removing the first layer, to form an upstanding portion of a MHK gate structure; forming a first sidewall layer on sidewalls of the upstanding portion of the MHK gate structure; forming a second sidewall layer on sidewalls of the first sidewall layer; removing a portion of the first layer to form exposed surfaces; forming an offset spacer layer over the second sidewall layer and over the first layer, and forming in the substrate extensions that underlie the first and second sidewall layers and that extend under a portion but not all of the upstanding portion of the MHK gate structure.

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02-08-2012 дата публикации

Method to increase silicon nitride tensile stress using nitrogen plasma in-situ treatment and ex-situ uv cure

Номер: US20120196450A1
Принадлежит: Applied Materials Inc

Stress of a silicon nitride layer may be enhanced by deposition at higher temperatures. Employing an apparatus that allows heating of a substrate to substantially greater than 400° C. (for example a heater made from ceramic rather than aluminum), the silicon nitride film as-deposited may exhibit enhanced stress allowing for improved performance of the underlying MOS transistor device. In accordance with some embodiments, a deposited silicon nitride film is exposed to curing with plasma and ultraviolet (UV) radiation, thereby helping remove hydrogen from the film and increasing film stress. In accordance with other embodiments, a silicon nitride film is formed utilizing an integrated process employing a number of deposition/curing cycles to preserve integrity of the film at the sharp corner of the underlying raised feature. Adhesion between successive layers may be promoted by inclusion of a post-UV cure plasma treatment in each cycle.

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06-09-2012 дата публикации

Sealing structure for high-k metal gate and method of making

Номер: US20120225529A1

The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.

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27-09-2012 дата публикации

Field effect transistor

Номер: US20120241722A1
Принадлежит: Individual

A field effect transistor according to an embodiment includes: a semiconductor layer; a source region and a drain region formed at a distance from each other in the semiconductor layer; a gate insulating film formed on a portion of the semiconductor layer, the portion being located between the source region and the drain region; a gate electrode formed on the gate insulating film; and a gate sidewall formed on at least one of side faces of the gate electrode, the side faces being located on a side of the source region and on a side of the drain region, the gate sidewall being made of a high dielectric material. The source region and the drain region are separately-placed from the corresponding side faces of the gate electrode.

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04-10-2012 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20120248545A1
Автор: Jiro Yugami
Принадлежит: Renesas Electronics Corp

A p-type MIS transistor Qp arranged in a pMIS region Rp of a silicon substrate 1 includes a pMIS gate electrode GEp formed so as to interpose a pMIS gate insulating film GIp formed of a first insulating film z 1 and a first high-dielectric film hk 1 , and an n-type MIS transistor Qn arranged in an nMIS region Rn includes an nMIS gate electrode GEn formed so as to interpose an nMIS gate insulating film GIn formed of a first insulating film z 1 and a second high-dielectric film hk 2. The first high-dielectric film hk 1 is formed of an insulating film mainly made of hafnium and oxygen with containing aluminum, titanium, or tantalum. Also, the second high-dielectric film hk 2 is formed of an insulating film mainly made of hafnium, silicon, and oxygen with containing an element of any of group Ia, group IIa, and group IIIa.

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22-11-2012 дата публикации

Semiconductor Device and Manufacturing Method Thereof

Номер: US20120292673A1
Автор: Weizhong Xu

A semiconductor device and manufacture method thereof is disclosed. The method includes: forming a gate on a substrate; forming a stack including a first material layer, a second material layer, and a third material layer from inner to outer in sequence; etching the stack to form sidewall spacers on opposite sidewalls of the gate; performing ion implantation to form a source region and a drain region; partially or completely removing the remaining portion of the third material layer; performing a pre-cleaning process, wherein all or a portion of the remaining portion of the second material layer is removed; forming silicide on top of the source region, the drain region, and the gate; depositing a stress film to cover the silicide and the remaining portion of the first material layer. According to the above method, the stress proximity technique (SPT) can be realized while avoiding silicide loss.

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29-11-2012 дата публикации

Semiconductor device and method for fabricating the same

Номер: US20120299058A1
Принадлежит: United Microelectronics Corp

A semiconductor device comprising a silicon substrate, a gate structure and a heteroatom-containing epitaxial structure is provided. The gate structure is disposed on a surface of the silicon substrate. The heteroatom-containing epitaxial structure is disposed adjacent to the gate structure and has a major portion and an extension portion, wherein the major portion virtual vertically extends downwards into the silicon substrate from the surface; and the extension portion further extends downwards into the silicon substrate with a tapered cross-section continuing with the major portion.

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29-11-2012 дата публикации

Thin body silicon-on-insulator transistor with borderless self-aligned contacts

Номер: US20120299101A1
Принадлежит: International Business Machines Corp

A thin-silicon-on-insulator transistor with borderless self-aligned contacts includes a buried oxide layer above a substrate. A silicon layer overlays the buried oxide layer. A gate stack is on the silicon layer. The gate stack includes a gate oxide layer on the silicon layer and a gate electrode on the gate oxide layer. An off-set spacer surrounds the gate stack. Raised source/drain regions each have a first part overlying a portion of the silicon layer, a second part adjacent to off-set spacer, and a third part extending about a top portion of the gate stack.

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06-12-2012 дата публикации

Method for fabricating semiconductor device

Номер: US20120309158A1
Принадлежит: Individual

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a dummy gate on the substrate; forming a contact etch stop layer on the dummy gate and the substrate; performing a planarizing process to partially remove the contact etch stop layer; partially removing the dummy gate; and performing a thermal treatment on the contact etch stop layer.

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17-01-2013 дата публикации

Transistor, Semiconductor Device, and Method for Manufacturing the Same

Номер: US20130015510A1
Автор: Jiang Yan, Lichuan Zhao
Принадлежит: Institute of Microelectronics of CAS

The invention provides a transistor, a semiconductor device and a method for manufacturing the same. The method for manufacturing a transistor comprises: defining an active area on a semiconductor substrate, forming a dummy gate stack on the active area, primary spacers surrounding said dummy gate stack, and an insulating layer surrounding said primary spacers, and forming source/drain regions embedded in said active area; removing the dummy gate in said dummy gate stack to form a first recessed portion surrounded by the primary spacers; filling Cu simultaneously in said first recessed portion and in the source/drain contact holes penetrating said insulating layer to form a gate and source/drain contacts. By filling the gate and the source/drain contact holes with the metal Cu simultaneously in the Gate Last structure, the gate serial resistance and the source/drain contact holes resistance in the Gate Last process are decreased. Besides, the effect of metal filling is improved in small scale, and the process complexity and difficulty is efficiently decreased.

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18-04-2013 дата публикации

Deposited Material and Method of Formation

Номер: US20130093048A1

A system and method for manufacturing a semiconductor device is provided. An embodiment comprises forming a deposited layer using an atomic layer deposition (ALD) process. The ALD process may utilize a first precursor for a first time period, a first purge for a second time period longer than the first time period, a second precursor for a third time period longer than the first time period, and a second purge for a fourth time period longer than the third time period.

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02-05-2013 дата публикации

Graphene and Nanotube/Nanowire Transistor with a Self-Aligned Gate Structure on Transparent Substrates and Method of Making Same

Номер: US20130105765A1
Принадлежит: International Business Machines Corp

Transistor devices having a self-aligned gate structure on transparent substrates and techniques for fabrication thereof are provided. In one aspect, a method of fabricating a transistor device includes the following steps. A channel material is formed on a transparent substrate. Source and drain electrodes are formed in contact with the channel material. A dielectric layer is deposited on the channel material. A photoresist is deposited on the dielectric layer and developed using UV light exposure through the transparent substrate. A gate metal(s) is deposited on the exposed portions of the dielectric layer and the undeveloped portions of the photoresist. The undeveloped portions of the photoresist are removed along with portions of the gate metal over the source and drain regions to form a gate of the device on the dielectric layer over the channel material which is self-aligned to the source and drain electrodes.

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02-05-2013 дата публикации

Method for fabricating oxides/semiconductor interfaces

Номер: US20130109199A1
Автор: Georgios Vellianitis

By depositing a layer of oxidizing metal on the semiconductor surface first and then depositing a layer of the high-k oxide material over the layer of oxidizing metal by an atomic layer deposition, a high-k metal oxide is formed at the interface between the semiconductor substrate and the high-k oxide and prevents formation of the undesirable low-k semiconductor oxide layer at the semiconductor/high-k oxide interface.

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16-05-2013 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20130119470A1
Принадлежит: Renesas Electronics Corp

Characteristics of a semiconductor device are improved. A semiconductor device of the present invention includes: (a) a MISFET arranged in an active region formed of a semiconductor region surrounded by an element isolation region; and (b) an insulating layer arranged below the active region. Further, the semiconductor device includes: (c) a p-type semiconductor region arranged below the active region so as to interpose the insulating layer; and (d) an n-type semiconductor region whose conductivity type is opposite to the p-type, arranged below the p-type semiconductor region. And, the p-type semiconductor region includes a connection region extending from below the insulating layer, and the p-type semiconductor region and a gate electrode of the MISFET are connected to each other by a shared plug which is an integrally-formed conductive film extending from above the gate electrode to above the connection region.

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23-05-2013 дата публикации

EPITAXIAL PROCESS FOR FORMING SEMICONDUCTOR DEVICES

Номер: US20130130461A1
Автор: WANG Shiang-Bau

A method for forming a semiconductor device such as a MOSFET. The method includes forming gate electrode pillars on a silicon substrate via material deposition and etching. Following the etching step to define the pillars, an epitaxial silicon film is grown on the substrate between the pillars prior to forming recesses in the substrate for the source/drain regions of the transistor. The epitaxial silicon film compensates for substrate material that may be lost during formation of the gate electrode pillars, thereby producing source/drain recesses having a configuration amenable to be filled uniformly with silicon for later forming the source/drain regions in the substrate. 1. A method for fabricating a MOS transistor comprising the steps of:(a) providing a silicon substrate;(b) forming a dielectric gate oxide layer on the semiconductor substrate;(c) forming a conductive gate layer on the gate oxide layer;(d) forming a hard mask layer on the gate layer;(e) forming a patterned photoresist layer above the gate layer, the patterned photoresist layer having a gate electrode pattern;(f) forming recesses in the hard mask and gate layer defining raised gate electrode pillars corresponding to the gate electrode pattern;(g) implanting impurities through the recesses into the substrate to form lightly doped drain regions;(h) forming an epitaxial silicon film on the substrate between the gate electrode pillars;(i) forming sidewall spacers on the gate electrode pillars;(j) forming source and drain recesses in the silicon substrate to define source and drain regions, wherein the epitaxial silicon film is removed; and(k) depositing epitaxial silicon in the source and drain regions.2. The method of claim 1 , further comprising a step of removing the photoresist layer after the implanting step but before the forming an epitaxial silicon film on the substrate step.3. The method of claim 1 , wherein the epitaxial silicon film has a substantially flat top surface prior to forming the ...

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04-07-2013 дата публикации

Method for growing conformal epi layers and structure thereof

Номер: US20130168736A1
Принадлежит: International Business Machines Corp

A method for forming a conformal buffer layer of uniform thickness and a resulting semiconductor structure are disclosed. The conformal buffer layer is used to protect highly-doped extension regions during formation of an epitaxial layer that is used for inducing mechanical stress on the channel region of transistors.

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04-07-2013 дата публикации

Epitaxial extension cmos transistor

Номер: US20130171794A1
Принадлежит: International Business Machines Corp

A pair of horizontal-step-including trenches are formed in a semiconductor layer by forming a pair of first trenches having a first depth around a gate structure on the semiconductor layer, forming a disposable spacer around the gate structure to cover proximal portions of the first trenches, and by forming a pair of second trenches to a second depth greater than the first depth. The disposable spacer is removed, and selective epitaxy is performed to form an integrated epitaxial source and source extension region and an integrated epitaxial drain and drain extension region. A replacement gate structure can be formed after deposition and planarization of a planarization dielectric layer and subsequent removal of the gate structure and laterally expand the gate cavity over expitaxial source and drain extension regions. Alternately, a contact-level dielectric layer can be deposited directly on the integrated epitaxial regions and contact via structures can be formed therein.

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11-07-2013 дата публикации

Self-aligned contacts

Номер: US20130178033A1
Принадлежит: Intel Corp

A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

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25-07-2013 дата публикации

SELF-ALIGNED CONTACTS FOR HIGH k/METAL GATE PROCESS FLOW

Номер: US20130189834A1
Принадлежит: International Business Machines Corp

A semiconductor structure is provided that includes a semiconductor substrate having a plurality of gate stacks located thereon. Each gate stack includes a high k gate dielectric layer, a work function metal layer and a conductive metal. A spacer is located on sidewalls of each gate stack and a self-aligned dielectric liner is present on an upper surface of each spacer. A bottom surface of each self-aligned dielectric liner is present on an upper surface of a semiconductor metal alloy. A contact metal is located between neighboring gate stacks and is separated from each gate stack by the self-aligned dielectric liner. The structure also includes another contact metal having a portion that is located on and in direct contact with an upper surface of the contact metal and another portion that is located on and in direct contact with the conductive metal of one of the gate stacks.

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01-08-2013 дата публикации

Methods for fabricating mos devices with stress memorization

Номер: US20130196495A1
Принадлежит: Globalfoundries Inc

A MOS device and methods for its fabrication are provided. In one embodiment the MOS device is fabricated on and within a semiconductor substrate. The method includes forming a gate structure having a top and sidewalls and having a gate insulator overlying the semiconductor substrate, a gate electrode overlying the gate insulator, and a cap overlying the gate electrode. An oxide liner is deposited over the top and sidewalls of the gate structure. In the method, the cap is etched from the gate structure and oxide needles extending upward from the gate structure are exposed. A stress-inducing layer is deposited over the oxide needles and gate structure and the semiconductor substrate is annealed. Then, the stress-inducing liner is removed.

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15-08-2013 дата публикации

Symmetric ldmos transistor and method of production

Номер: US20130207180A1
Принадлежит: ams AG

The symmetric LDMOS transistor comprises a semiconductor substrate ( 1 ), a well ( 2 ) of a first type of conductivity in the substrate, and wells ( 3 ) of an opposite second type of conductivity. The wells ( 3 ) of the second type of conductivity are arranged at a distance from one another. Source/drain regions ( 4 ) are arranged in the wells of the second type of conductivity. A gate dielectric ( 7 ) is arranged on the substrate, and a gate electrode ( 8 ) on the gate dielectric. A doped region ( 10 ) of the second type of conductivity is arranged between the wells of the second type of conductivity at a distance from the wells. The gate electrode has a gap ( 9 ) above the doped region ( 10 ), and the gate electrode overlaps regions that are located between the wells ( 3 ) of the second type of conductivity and the doped region ( 10 ).

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15-08-2013 дата публикации

Stepped-source ldmos architecture

Номер: US20130207186A1
Автор: Jun Cai
Принадлежит: Fairchild Semiconductor Corp

A semiconductor device can include a source region near a working top surface of a semiconductor region. The device can also include a gate located above the working top surface and located laterally between the source and a drain region. The source region and the gate can at least partially laterally overlap a body region near the working top surface. The source region can include a first portion having the first conductivity type, a second portion having a second conductivity type, and a third portion having the second conductivity type. The second portion can be located laterally between the first and third portions and can penetrate into the semiconductor region to a greater depth than the third portion but no more than the first portion. The lateral location of the third portion can be determined at least in part using the lateral location of the gate.

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15-08-2013 дата публикации

Fabrication method of semiconductor device and fabrication method of dynamic threshold transistor

Номер: US20130210207A1
Принадлежит: Fujitsu Semiconductor Ltd

A method includes: etching a silicon substrate except for a silicon substrate portion on which a channel region is to be formed to form first and second trenches respectively at a first side and a second side of the silicon substrate portion; filling the first and second trenches by epitaxially growing a semiconductor layer having etching selectivity against silicon and further a silicon layer; removing the semiconductor layer selectivity by a selective etching process to form voids underneath the silicon layer respectively at the first side and the second side of the substrate portion; burying the voids at least partially with a buried insulation film; forming a gate insulation film and a gate electrode on the silicon substrate portion; and forming a source region in the silicon layer at the first side of the silicon substrate portion and a drain region at the second side of the silicon substrate portion.

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12-09-2013 дата публикации

Method of hybrid high-k/metal-gate stack fabrication

Номер: US20130234254A1

A process fabricating a semiconductor device with a hybrid HK/metal gate stack fabrication is disclosed. The process includes providing a semiconductor substrate having a plurality of isolation features between a PFET region and a NFET region, and forming gate stacks on the semiconductor substrate. In the PFET region, the gate stack is formed as a HK/metal gate. In the NFET region, the gate stack is formed as a polysilicon gate. A high-resistor is also formed on the semiconductor substrate by utilizing another polysilicon gate.

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12-09-2013 дата публикации

Semiconductor structure and fabrication method thereof

Номер: US20130234261A1
Принадлежит: United Microelectronics Corp

A semiconductor structure includes a gate structure disposed on a substrate and having an outer spacer, a recess disposed in the substrate and adjacent to the gate structure, a doped epitaxial material filling up the recess, a cap layer including an undoped epitaxial material and disposed on the doped epitaxial material, a lightly doped drain disposed below the cap layer and sandwiched between the doped epitaxial material and the cap layer, and a silicide disposed on the cap layer and covering the doped epitaxial material to cover the cap layer together with the outer spacer without directly contacting the lightly doped drain.

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26-09-2013 дата публикации

Short channel semiconductor devices with reduced halo diffusion

Номер: US20130249000A1
Автор: Bin Yang, Man Fai NG
Принадлежит: Globalfoundries Inc

A short channel semiconductor device is formed with halo regions that are separated from the bottom of the gate electrode and from each other. Embodiments include implanting halo regions after forming source/drain regions and source/drain extension regions. An embodiment includes forming source/drain extension regions in a substrate, forming source/drain regions in the substrate, forming halo regions under the source/drain extension regions, after forming the source drain regions, and forming a gate electrode on the substrate between the source/drain regions. By forming the halo regions after the high temperature processing involved informing the source/drain and source/drain extension regions, halo diffusion is minimized, thereby maintaining sufficient distance between halo regions and reducing short channel NMOS Vt roll-off.

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10-10-2013 дата публикации

Diode Biased ESD Protection Device and Method

Номер: US20130264645A1
Принадлежит: INFINEON TECHNOLOGIES AG

An ESD protection device includes an MOS transistor with a source region, drain region and gate region. A node designated for ESD protection is electrically coupled to the drain. A diode is coupled between the gate and source, wherein the diode would be reverse biased if the MOS transistor were in the active operating region.

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31-10-2013 дата публикации

Compact tid hardening nmos device and fabrication process

Номер: US20130285147A1
Автор: Fethi Dhaoui
Принадлежит: Individual

A radiation-hardened transistor is formed in a p-type semiconductor body having an active region doped to a first level and surrounded by a dielectric filled shallow trench isolation region. N-type source/drain regions are disposed in the active region and spaced apart to define a channel. A gate is disposed above the channel, and is self-aligned with the source/drain regions. First and second p-type regions are disposed in the p-type semiconductor body on either side of one of the source/drain regions and are doped to a second level higher than the first doping level. The first and second p-type regions are self aligned with and extend outwardly from a first side edge of the gate. The ends of the gate extend past the first and second p-type regions.

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07-11-2013 дата публикации

Semiconductor device and method for manufacturing semiconductor device

Номер: US20130295741A1
Автор: Takuji Matsumoto
Принадлежит: Sony Corp

A semiconductor device including a gate electrode disposed on a semiconductor substrate and source/drain regions disposed at both sides of the gate electrode, the source/drain regions being formed by implanting impurities. The source/drain regions include an epitaxial layer formed by epitaxially growing a semiconductor material having a different lattice constant from that of the semiconductor substrate in a recessed position at a side of the gate electrode, and a diffusion layer disposed in a surface layer of the semiconductor substrate.

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14-11-2013 дата публикации

Semiconductor device and method for manufacturing the same

Номер: US20130299920A1
Автор: Haizhou Yin, Keke Zhang
Принадлежит: Institute of Microelectronics of CAS

The present invention discloses a semiconductor device, comprising a substrate, a gate stack structure on the substrate, a gate spacer structure at both sides of the gate stack structure, source/drain regions in the substrate and at opposite sides of the gate stack structure and the gate spacer structure, characterized in that the gate spacer structure comprises at least one gate spacer void filled with air. In accordance with the semiconductor device and the method for manufacturing the same of the present invention, carbon-based materials are used to form a sacrificial spacer, and at least one air void is formed after removing the sacrificial spacer, the overall dielectric constant of the spacer is effectively reduced. Thus, the gate parasitic capacitance is reduced and the device performance is enhanced.

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05-12-2013 дата публикации

Process for fabricating a transistor comprising nanoscale semiconductor features using block copolymers

Номер: US20130323888A1

A process for fabricating one transistor, comprising a semiconductor region, comprising a source region, a drain region, and a channel region covered with a gate, comprises: production of an primary etching mask on the surface of the semiconductor region, said mask containing at least one primary aperture; depositing in said primary aperture a block copolymer containing, in alternation, at least first polymer domains and second polymer domains; removing either a series of first polymer domains or a series of second polymer domains in order to create a secondary mask containing secondary apertures; etching said active region through said secondary apertures in order to define nanoscale self-aligned semiconductor features; producing said gate on the surface of said self-aligned semiconductor features.

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05-12-2013 дата публикации

Integrated Circuit Device with Well Controlled Surface Proximity and Method of Manufacturing Same

Номер: US20130323891A1

An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite the LDD region.

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26-12-2013 дата публикации

Method of manufacturing semiconductor device

Номер: US20130344690A1
Автор: Masahiko Kanda
Принадлежит: Toshiba Corp

According to one embodiment, in a method of manufacturing a semiconductor device, a gate electrode material film is anisotropically etched using a mask having a predetermined pattern so as to form a first gate electrode on a first region, first dummy gates on the space area of the first region, a second gate electrode on a second region and second dummy gates on the space area of the second region. The first dummy gates have a first coverage and are disposed so as to surround the first gate electrode. The second dummy gates have a second coverage and are disposed so as to surround the second gate electrode. A first insulating film is anisotropically etched so as to form a first sidewall having a first thickness on the first gate electrode and a second sidewall having a second thickness larger than the first thickness on the second gate electrode.

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02-01-2014 дата публикации

High voltage three-dimensional devices having dielectric liners

Номер: US20140001569A1
Принадлежит: Intel Corp

High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric composed of a first dielectric layer disposed on the first fin active region, and a second, different, dielectric layer disposed on the first dielectric layer. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric composed of the second dielectric layer disposed on the second fin active region.

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23-01-2014 дата публикации

Method for Fabricating Semiconductor Device

Номер: US20140024192A1
Принадлежит:

A method for fabricating a semiconductor device comprises forming a dummy gate pattern and a spacer that is arranged on a sidewall of the dummy gate pattern on a substrate, forming an air gap on both sides of the dummy gate pattern by removing the spacer, exposing the substrate by removing the dummy gate pattern, and sequentially forming a gate insulating film including a high-k insulating film and a metal gate electrode on the exposed substrate. 1. A method for fabricating a semiconductor device comprising:forming a dummy gate pattern on a substrate;forming a spacer on a sidewall of the dummy gate pattern and on the substrate;forming an air gap on both sides of the dummy gate pattern by removing the spacer;exposing the substrate by removing the dummy gate pattern; andsequentially forming a gate insulating film including a high-k insulating film and a metal gate electrode on the exposed substrate.2. The method for fabricating a semiconductor device of claim 1 , wherein forming the air gap comprises:forming an interlayer insulating film that at least partially covers a sidewall of the spacer and exposes a top surface of the spacer; andforming a first recess in the interlayer insulating film by removing at least part of the spacer.3. The method for fabricating a semiconductor device of claim 2 , further comprising conformally forming a liner within the first recess.4. The method for fabricating a semiconductor device of claim 3 , further comprising forming a blocking film that covers the first recess and the dummy gate pattern.5. The method for fabricating a semiconductor device of claim 4 , wherein a part of the blocking film fills up an upper portion of the first recess while leaving an air gap in a lower portion of the first recess.6. The method for fabricating a semiconductor device of claim 5 , wherein removing the dummy gate pattern comprises:exposing the dummy gate pattern by smoothing the blocking film; andforming a trench that exposes the substrate in the ...

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06-02-2014 дата публикации

Method for manufacturing light emitting device, and light emitting device

Номер: US20140034994A1
Принадлежит: Panasonic Corp

A method for manufacturing a light-emitting device, comprising: forming, over a substrate, a plurality of multilayered light-emitting structures each including a first electrode, a light-emitting layer, and a second electrode; forming, in the substrate, a plurality of grooves that surround the multilayered light-emitting structures individually; forming, over the substrate, a sealing film that covers the multilayered light-emitting structures and the grooves; and separating the multilayered light-emitting structures from one another after forming the sealing film, by cutting the substrate such that, in each groove, part of the sealing film covering a given inner side surface of the groove remains, the given inner side surface being adjacent to any of the multilayered light-emitting structures.

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13-02-2014 дата публикации

Mos transistor and process thereof

Номер: US20140042501A1
Принадлежит: United Microelectronics Corp

A MOS transistor includes a gate structure and a spacer. The gate structure is located on a substrate. The spacer is located on the substrate beside the gate structure, and the spacer includes an L-shaped inner spacer and an outer spacer, wherein the outer spacer is located on the L-shaped inner spacer, and the two ends of the L-shaped inner spacer protrude from the outer spacer. Moreover, the present invention also provides a MOS transistor process for forming the MOS transistor.

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13-02-2014 дата публикации

Device active channel length/width greater than channel length/width

Номер: US20140042505A1
Автор: Trudy Benjamin
Принадлежит: Hewlett Packard Development Co LP

A device including a drain, a channel, and a gate. The channel surrounds the drain and has a channel length to width ratio. The gate is situated over the channel to provide an active channel region that has an active channel region length to width ratio that is greater than the channel length to width ratio.

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20-03-2014 дата публикации

ELECTRONIC DEVICES AND SYSTEMS, AND METHODS FOR MAKING AND USING THE SAME

Номер: US20140077312A1
Принадлежит: SUVOLTA, INC.

Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σVcompared to conventional bulk CMOS and can allow the threshold voltage Vof FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits. 1. A method for forming a group of biasable , deeply depleted channel (DDC) , field effect transistors (FET) on a die on a wafer , comprising the steps of:{'sup': 18', '20', '3, 'implanting a screening region into a well formed on the die on the wafer, the screening region being doped with a dopant to have a dopant concentration between 5×10to 1×10atoms/cm, the screening region being electrically coupled to a well, the screening region being positioned to set channel depletion depth during DDC FET operation;'}forming an undoped semiconductive layer above the screening region, the undoped semiconductor layer being coextensive with the screening region;maintaining throughout processing at least a portion of the undoped semiconductive layer as an undoped channel region;forming a gate stack positioned above the undoped channel region to control conduction between a drain and a source;forming an isolation structure to electrically separate at least some transistors formed on the die on the wafer; andforming at least one body tap electrically ...

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10-04-2014 дата публикации

Method for manufacturing a semiconductor device

Номер: US20140099784A1
Автор: Je-Don Kim, Ju-youn Kim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A method for manufacturing a semiconductor device includes forming an insulation film including a trench on a substrate, forming a first metal gate film pattern and a second metal gate film pattern in the trench, redepositing a second metal gate film on the first and second metal gate film patterns and the insulation film, and forming a redeposited second metal gate film pattern on the first and second metal gate film patterns by performing a planarization process for removing a portion of the redeposited second metal gate film so as to expose a top surface of the insulation film, and forming a blocking layer pattern on the redeposited second metal gate film pattern by oxidizing an exposed surface of the redeposited second metal gate film pattern.

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01-01-2015 дата публикации

TUCKED ACTIVE REGION WITHOUT DUMMY POLY FOR PERFORMANCE BOOST AND VARIATION REDUCTION

Номер: US20150001585A1
Принадлежит:

In one embodiment, a semiconductor device is provided that includes a semiconductor substrate including an active region and at least one trench isolation region at a perimeter of the active region, and a functional gate structure present on a portion of the active region of the semiconductor substrate. Embedded semiconductor regions are present in the active region of the semiconductor substrate on opposing sides of the portion of the active region that the functional gate structure is present on. A portion of the active region of the semiconductor substrate separates the outermost edge of the embedded semiconductor regions from the at least one isolation region. Methods of forming the aforementioned device are also provided. 1. A semiconductor device comprising:a semiconductor substrate including an active region and at least one trench isolation region at a perimeter of the active region;a functional gate structure present on a portion of the active region of the semiconductor substrate; andembedded semiconductor regions present in the active region of the semiconductor substrate on opposing sides of the portion of the active region that the functional gate structure is present on, wherein another portion of the active region of the semiconductor substrate laterally separates an outermost edge of each of the embedded semiconductor regions from the at least one isolation region.2. The semiconductor device of claim 1 , wherein the semiconductor substrate comprises Si claim 1 , SiGe claim 1 , SiGeC claim 1 , SiC claim 1 , polysilicon claim 1 , germanium claim 1 , gallium arsenide claim 1 , gallium nitride claim 1 , cadmium telluride claim 1 , or zinc sellenide.3. The semiconductor device of claim 2 , wherein the active region of the semiconductor substrate is doped with an n-type or a p-type dopant.4. The semiconductor device of claim 1 , wherein the at least one trench isolation region comprises an oxide claim 1 , a nitride claim 1 , or an oxynitride.5. The ...

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01-01-2015 дата публикации

DIVOT-FREE PLANARIZATION DIELECTRIC LAYER FOR REPLACEMENT GATE

Номер: US20150001598A1
Принадлежит:

After formation of a silicon nitride gate spacer and a silicon nitride liner overlying a disposable gate structure, a dielectric material layer is deposited, which includes a dielectric material that is not prone to material loss during subsequent exposure to wet or dry etch chemicals employed to remove disposable gate materials in the disposable gate structure. The dielectric material can be a spin-on dielectric material or can be a dielectric metal oxide material. The dielectric material layer and the silicon nitride liner are planarized to provide a planarized dielectric surface in which the disposable gate materials are physically exposed. Surfaces of the planarized dielectric layer is not recessed relative to surfaces of the silicon nitride layer during removal of the disposable gate materials and prior to formation of replacement gate structures, thereby preventing formation of metallic stringers.

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06-01-2022 дата публикации

SEMICONDUCTOR DEVICE HAVING A NECKED SEMICONDUCTOR BODY AND METHOD OF FORMING SEMICONDUCTOR BODIES OF VARYING WIDTH

Номер: US20220005953A1
Автор: Sell Bernhard
Принадлежит:

Semiconductor devices having necked semiconductor bodies and methods of forming semiconductor bodies of varying width are described. For example, a semiconductor device includes a semiconductor body disposed above a substrate. A gate electrode stack is disposed over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack. Source and drain regions are defined in the semiconductor body on either side of the gate electrode stack. Sidewall spacers are disposed adjacent to the gate electrode stack and over only a portion of the source and drain regions. The portion of the source and drain regions under the sidewall spacers has a height and a width greater than a height and a width of the channel region of the semiconductor body. 1. An integrated circuit structure , comprising:a semiconductor body having a semiconductor channel, the semiconductor channel having a first side opposite a second side;a gate electrode over the semiconductor body, the gate electrode comprising a first gate electrode portion proximate the first side of the semiconductor channel, and the gate electrode comprising a second gate electrode portion proximate the second side of the semiconductor channel, the second gate electrode portion in alignment with the first gate electrode portion, wherein the semiconductor channel has a first width at a first location between the first gate electrode portion and the second gate electrode portion, and wherein the semiconductor channel has a second width at a second location between the first gate electrode portion and the second gate electrode portion, the second width different than the first width;a source or drain region adjacent to the semiconductor channel;a first sidewall spacer portion proximate a first portion of the source or drain region and proximate the first gate electrode portion;a second sidewall spacer portion proximate the first portion of the source or drain region and proximate ...

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05-01-2017 дата публикации

METHOD OF FABRICATING A SEMICONDUCTOR STRUCTURE WITH A SELF-ALIGNED CONTACT

Номер: US20170004997A1
Принадлежит:

A method of fabricating a semiconductor structure includes the following steps: forming a first interlayer dielectric on a substrate; forming a gate electrode on the substrate so that the periphery of the gate electrode is surrounded by the first interlayer dielectric; forming a patterned mask layer comprising at least a layer of organic material on the gate electrode; forming a conformal dielectric layer to conformally cover the layer of organic material; and forming a second interlayer dielectric to cover the conformal dielectric layer. 1. A method of fabricating a semiconductor structure , comprising:forming a dummy gate electrode on the substrate;forming a first interlayer dielectric on a substrate after the step of forming the dummy gate electrode;removing the dummy gate electrode to leave a trench in the first interlayer dielectric;forming a gate electrode in the trench, wherein a periphery of the gate electrode is surrounded by the first interlayer dielectric;forming a hard mask on a top surface of the gate electrode;forming a patterned mask layer comprising at least a layer of organic material on the gate electrode after the step of forming the hard mask;forming a conformal dielectric layer to conformally cover the layer of organic material; andforming a second interlayer dielectric to cover the conformal dielectric layer.2. The method of claim 1 , wherein the step of forming the patterned mask layer comprises:coating a photoresist layer on the first interlayer dielectric; andpatterning the photoresist layer so as to form a patterned photoresist.3. The method of claim 1 , wherein the step of forming the patterned mask layer further comprises:coating an organic dielectric layer on the first interlayer dielectric;coating an anti-reflection layer on the organic dielectric layer;coating a photoresist layer on the anti-reflection layer;patterning the photoresist layer so as to form a patterned photoresist; andetching the anti-reflection layer by using the ...

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05-01-2017 дата публикации

METHOD OF USING A SACRIFICAL GATE STRUCTURE TO MAKE A METAL GATE FINFET TRANSISTOR

Номер: US20170005169A1
Принадлежит:

A self-aligned SiGe FinFET device features a relaxed channel region having a high germanium concentration. Instead of first introducing germanium into the channel and then attempting to relax the resulting strained film, a relaxed channel is formed initially to accept the germanium. In this way, a presence of germanium can be established without straining or damaging the lattice. Gate structures are patterned relative to intrinsic silicon fins, to ensure that the gates are properly aligned, prior to introducing germanium into the fin lattice structure. After aligning the gate structures, the silicon fins are segmented to elastically relax the silicon lattice. Then, germanium is introduced into the relaxed silicon lattice, to produce a SiGe channel that is substantially stress-free and also defect-free. Using the method described, concentration of germanium achieved in a structurally stable film can be increased to a level greater than 85%. 1. A method , comprising:forming a plurality of fins extending vertically outward from a surface of a substrate comprised of a first semiconductor material, each of the fins being a contiguous single crystal member extending from the substrate and also being comprised of the first semiconductor material;forming a plurality of gate structures in contact with three sides of each of the fins, each gate structure including a sacrificial gate member;relaxing the fins elastically by segmenting each of the fins into a respective plurality of fin segments, the segmenting exposing sidewalls of each of the fin segments;removing sacrificial gate members from the gate structures;incorporating a second semiconductor material into the fin segments;forming metal gates in the gate structures, each metal gate substantially centered over one of the plurality of fin segments and extending on at least three sides of the respective fin segment; andforming source and drain regions on the exposed sidewalls of the fin segments, with a channel region ...

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05-01-2017 дата публикации

SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF

Номер: US20170005181A1
Принадлежит:

A semiconductor device includes first fin-shaped structures and second fin-shaped structures, which are separately disposed on a semiconductor substrate. Each of the first and second fin-shaped structures includes a base portion and a top portion protruding from the top portion. The base portions of the second fin-shaped structures are wider than the top portions of the second fin-shaped structures, and the top portions of the second fin-shaped structures are as wide as the top portions of the first fin-shaped structures. Each second fin-shaped structure further includes a recessed region on its sidewall. 1. A semiconductor device , comprising:a plurality of first fin-shaped structures disposed on a semiconductor substrate, wherein each of the first fin-shaped structures comprises:a base portion disposed on the semiconductor substrate; anda top portion extending from the base portion of the first fin-shaped structure, wherein the top portion of each of the first fin-shaped structure has a first width;a plurality of second fin-shaped structures disposed on the semiconductor substrate, wherein each of the second fin-shaped structures comprises:a base portion disposed on the semiconductor substrate; anda top portion extending from the base portion of the second fin-shaped structure, wherein the top portion of each of the second fin-shaped structure has the first width; anda recessed region disposed on a sidewall of each of the second fin-shaped structures; anda shallow trench isolation disposed between the first fin-shaped structures and the second fin-shaped structures so that portions of each of the top portions protrude from the surface of the shallow trench isolation, wherein the base portions of the second fin-shaped structures are separately disposed on the semiconductor substrate.2. The semiconductor device of claim 1 , wherein the base portions of the second fin-shaped structures and the top portions of the second fin-shaped structures have smooth sidewalls.3. ...

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05-01-2017 дата публикации

LOCAL GERMANIUM CONDENSATION FOR SUSPENDED NANOWIRE AND FINFET DEVICES

Номер: US20170005190A1
Принадлежит:

A semiconductor wafer is provided, where the semiconductor wafer includes a semiconductor substrate and a hard mask layer formed on the semiconductor substrate. Fins are formed in the semiconductor substrate and the hard mask layer. A spacer is formed on an exposed sidewall of the hard mask layer and the semiconductor substrate. The exposed portion of the semiconductor substrate is etched. A silicon-germanium layer is epitaxially formed on the exposed portions of the semiconductor substrate. An annealed silicon-germanium region is formed by a thermal annealing process within the semiconductor substrate adjacent to the silicon-germanium layer. The silicon-germanium region and the silicon-germanium layer are removed. The hard mask layer and the spacer are removed. 1. A method of forming a suspended nanowire , the method comprising:providing a semiconductor substrate, wherein the semiconductor substrate includes a semiconductor layer and a hard mask layer formed on the semiconductor layer;forming at least one fin in the semiconductor layer and the hard mask layer;forming one or more spacers on one or more exposed sidewalls of the hard mask layer and the semiconductor layer;etching exposed regions of the semiconductor layer;epitaxially forming a silicon-germanium layer on the exposed portions of the semiconductor layer;performing a thermal annealing process such that an annealed silicon-germanium region is formed within the semiconductor layer adjacent to the silicon-germanium layer;removing the annealed silicon-germanium region and the silicon-germanium layer; andremoving the hard mask layer and the spacer.2. The method of claim 1 , wherein forming the at least one fin in the semiconductor layer and the hard mask layer comprises removing at least a portion of the hard mask layer and the semiconductor layer.3. The method of claim 1 , wherein etching the exposed regions of the semiconductor layer comprises performing an isotropic etch process on the exposed regions of ...

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07-01-2016 дата публикации

CONTROL OF O-INGRESS INTO GATE STACK DIELECTRIC LAYER USING OXYGEN PERMEABLE LAYER

Номер: US20160005620A1
Принадлежит:

A method of manufacturing a semiconductor structure, by depositing a dielectric layer is a dummy gate, or an existing gate structure, prior to the formation of gate spacers. Following the formation of spacers, and in some embodiments replacing a dummy gate with a final gate structure, oxygen is introduced to a gate dielectric through a diffusion process, using the deposited dielectric layer as a diffusion pathway. 1. A method of forming a semiconductor structure , the method comprising:depositing a first dielectric layer over a substrate and a gate structure, the gate structure including a gate dielectric layer located above the substrate and a gate electrode located above the gate dielectric layer, wherein a portion of the first dielectric layer is formed on opposing sidewalls of the gate structure;depositing a second dielectric layer over the deposited first dielectric layer;forming a spacer pair on the gate structure based on a portion of the second dielectric being deposited on the portion of the first dielectric layer located on the opposing sidewalls;wherein the portion of the first dielectric layer transports oxygen to the gate dielectric layer when exposing the semiconductor structure to an oxygen environment.2. The method of claim 1 , wherein the exposing the semiconductor structure to the oxygen environment comprises diffusing the oxygen into an exposed top region of the first dielectric layer for transporting the diffused oxygen to the gate dielectric layer via the bottom region of the first dielectric layer.3. The method of claim 2 , wherein the bottom region of the first dielectric layer comprises a contact region between the first dielectric layer and the gate dielectric layer.4. The method of claim 1 , wherein exposing the semiconductor structure to an oxygen environment comprises an oxygen anneal.5. The method of claim 4 , wherein the oxygen anneal comprises heating the semiconductor structure to a temperature between approximately 300° Celsius to ...

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07-01-2016 дата публикации

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME

Номер: US20160005650A1
Принадлежит:

A semiconductor structure and a method for forming the same are provided. The method includes forming a gate structure over a substrate and forming source and drain regions adjacent to the gate structure. The method also includes forming a first ILD layer surrounding the gate structure over the source and drain regions and forming a contact modulation structure over the gate structure. The method also includes etching the first ILD layer and the contact modulation structure to form a first contact trench over the source and drain regions and a second contact trench over the gate structure. The method further includes forming a first contact in the first contact trench and a second contact in the second contact trench. In addition, the first ILD layer has a first etching rate and the contact modulation structure has a second etching rate that is less than the first etching rate. 1. A method for forming a semiconductor structure , comprising:forming a gate structure over a substrate;forming source and drain regions adjacent to the gate structure in the substrate;forming a first inter-layer dielectric layer surrounding the gate structure over the source and drain regions over the substrate;forming a contact modulation structure over the gate structure;etching the first inter-layer dielectric layer to form a first contact trench over the source and drain regions and etching the contact modulation structure to form a second contact trench over the gate structure by performing a same etching process using a same etchant;forming a first contact in the first contact trench and a second contact in the second contact trench,wherein the first inter-layer dielectric layer has a first etching rate and the contact modulation structure has a second etching rate that is less than the first etching rate during the same etching process.2. The method for forming a semiconductor structure as claimed in claim 1 , wherein a ratio of the first etching rate to the second etching rate is in ...

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07-01-2016 дата публикации

HKMG HIGH VOLTAGE CMOS FOR EMBEDDED NON-VOLATILE MEMORY

Номер: US20160005756A1
Принадлежит:

The present disclosure relates to a structure and method for embedding a non-volatile memory (NVM) in a HKMG (high-κ metal gate) integrated circuit which includes a high voltage (HV) HKMG transistor. NVM devices (e.g., flash memory) are operated at high voltages for its read and write operations and hence a HV device is necessary for integrated circuits involving non-volatile embedded memory and HKMG logic circuits. Forming a HV HKMG circuit along with the HKMG periphery circuit reduces the need for additional boundaries between the HV transistor and rest of the periphery circuit. This method further helps reduce divot issue and reduce cell size. 1. An integrated circuit (IC) , comprising:an embedded memory region comprising an embedded non-volatile memory (NVM) device; anda periphery region comprising a high voltage high-κ metal gate (HV HKMG) transistor disposed over a high voltage (HV) gate insulating layer, and a periphery circuit disposed over a gate oxide layer.2. The IC of claim 1 , wherein the HV HKMG transistor is disposed at a location between the embedded NVM device and the periphery circuit.3. The IC of claim 1 , wherein the periphery region is separated from the embedded memory region by a boundary region.4. The IC of claim 1 , wherein the HV gate insulating layer is thicker than the gate oxide layer.5. The IC of claim 1 , wherein the periphery circuit comprises a static random access memory (SRAM) cell claim 1 , an input/output cell or a core cell.6. An integrated circuit (IC) comprising:a semiconductor substrate including a periphery region and a memory cell region separated by a boundary region;a pair of split gate flash memory cells disposed on the memory cell region;a HKMG logic circuit disposed over a gate oxide layer on the periphery region; anda high voltage (HV) high-κ metal gate (HKMG) transistor disposed over a HV gate insulating layer on the periphery region at a position between the boundary region and the HKMG logic circuit.7. The IC of ...

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07-01-2016 дата публикации

SELF-ALIGNED VIA FOR GATE CONTACT OF SEMICONDUCTOR DEVICES

Номер: US20160005822A1
Принадлежит:

Systems and methods are directed to a three-terminal semiconductor device including a self-aligned via for connecting to a gate terminal Hardmasks and spacers formed over top portions and sidewall portions of a drain connection to a drain terminal and a source connection to a source terminal protect and insulate the drain connection and the source connection, such that short circuits are avoided between the source and drain connections and the self-aligned via. The self-aligned via provides a direct metal-gate connection path between the gate terminal and a metal line such as a M1 metal line while avoiding a separate gate connection layer. 1. A method of forming a three-terminal semiconductor device comprising:forming a drain connection to a drain terminal and a source connection to a source terminal;forming hardmasks over top portions of the drain connection and the source connection and spacers covering sidewall portions of the drain connection and the source connection, wherein the hardmasks and spacers have a first etch chemistry;filling a first dielectric layer around the hardmasks and spacers, wherein the first dielectric layer has a second etch chemistry;etching a via hole in the first dielectric layer to contact a gate terminal, using the second etch chemistry, such that the hardmasks and spacers are not affected by the second etch chemistry; andfilling the via hole with a via material, such that the via material is prevented from short-circuits with the drain connection and the source connection, and wherein the via material provides a direct metal-gate connection path between the gate terminal and a metal line.2. The method of claim 1 , wherein the direct metal-gate connection path is self-aligned with respect to the source connection claim 1 , and the drain connection.3. The method of claim 1 , wherein forming the hardmasks comprises forming a recess over a top portion of the source connection and the drain connection claim 1 , depositing a hardmask ...

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07-01-2016 дата публикации

GATE DIELECTRIC PROTECTION FOR TRANSISTORS

Номер: US20160005828A1
Принадлежит:

At least one method, apparatus and system disclosed herein involves forming a device comprising a transistor comprising an active gate and at least one inactive gate in parallel to the active gate. A source region on a substrate is formed. An active gate region is formed on the substrate adjacent the source region. A drain region is formed on the substrate adjacent the active gate region. A first inactive gate region is formed on the substrate in parallel to the active gate region. The source region, the drain region, the active gate region, and the first inactive gate region comprise the transistor. The first inactive gate region is capable of dissipating the at least a portion of a charge. 1. (canceled)2. (canceled)3. A method for forming a transistor , comprising:forming a source region on a substrate, comprising forming forming a first n+ dopant region on a p-type substrate and forming a first contact region above said first n+ dopant region;forming a drain region on said substrate adjacent said active gate region, comprising forming a second n+ dopant region on said p-type substrate and forming a second contact region above said second n+ dopant region;forming an active gate region on said substrate adjacent said source region, comprising forming a first gate oxide region above said p-type substrate between said first and second n+ dopant regions and forming a first polysilicon conductor region above said first gate oxide region; andforming a first inactive gate region on said substrate in parallel to said active gate region, comprising forming a second gate oxide region above said p-type substrate adjacent said first n+ dopant region, forming a second polysilicon conductor region above second first gate oxide region, and electrically coupling said second polysilicon conductor region to said first polysilicon conductor region, wherein said source region, said drain region, said active gate region, and said first inactive gate region comprise said transistor, ...

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07-01-2016 дата публикации

High-K Film Apparatus and Method

Номер: US20160005832A1
Принадлежит:

A device may include: a high-k layer disposed on a substrate and over a channel region in the substrate. The high-k layer may include a high-k dielectric material having one or more impurities therein, and the one or more impurities may include at least one of C, Cl, or N. The one or more impurities may have a molecular concentration of less than about 50%. The device may further include a cap layer over the high-k layer over the channel region, the high-k layer separating the cap layer and the substrate. 1. A device , comprising:a high-k layer disposed on a substrate and over a channel region in the substrate, the high-k layer comprising a high-k dielectric material having one or more impurities therein, the one or more impurities comprising at least one of C, Cl, or N, and having a molecular concentration of less than about 50%; anda cap layer over the high-k layer over the channel region, the high-k layer separating the cap layer and the substrate.2. The device of claim 1 , wherein the high-k layer comprises hafnium oxide.3. The device of claim 1 , wherein the cap layer and the high-k layer differ in composition.4. The device of claim 1 , further comprising an interfacial layer disposed between the substrate and the high-k layer.5. The device of claim 4 , wherein a thickness of the interfacial layer is in a range from about 5 Angstroms to about 25 Angstroms.6. The device of claim 1 , wherein a thickness of the high-k layer is less than about 2 nanometers.7. The device of claim 1 , wherein the high-k layer has a dielectric constant greater than 3.9.8. The device of claim 1 , wherein the high-k layer has a dielectric constant greater than 15.9. The device of claim 1 , wherein the cap layer comprises titanium nitride.10. A method claim 1 , comprising:forming a source region and a drain region in a substrate; andforming a gate stack disposed between the source region and the drain region, the gate stack comprising a high-k dielectric layer disposed over the substrate ...

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07-01-2016 дата публикации

FEOL LOW-K SPACERS

Номер: US20160005833A1
Принадлежит:

Transistors and their methods of formation are described. Low dielectric constant material (e.g. a void) is placed between an elongated gate and a contact to increase the attainable switching speed of the gate of the device. An elongated structural slab of silicon nitride is temporarily positioned on both sides of the gate. Silicon oxide is formed over the silicon nitride slabs and the gate. Contacts are formed through the silicon oxide. The silicon oxide is selectively etched back to expose the silicon nitride slab. A portion or all the silicon nitride slab is removed and replaced with low-K dielectric or any dielectric with an air-gap to enable higher switching speed of the transistor. The highly-selective silicon nitride etch uses remotely excited fluorine and a very low electron temperature in the substrate processing region. 1. A transistor , comprisinga gate formed around a semiconducting fin extending from a semiconducting substrate, wherein the gate comprises a conducting portion; andtwo low-k dielectric regions disposed on both sides of the gate, wherein one of the two low-k dielectric regions is disposed laterally between the gate and a source region and the other of the two low-k dielectric regions is disposed laterally between the gate and a drain region.2. The transistor of wherein each of the two low-k dielectric regions contacts the gate.3. The transistor of wherein the gate extends around the entirety of the semiconducting fin.4. The transistor of wherein one of the two low-k dielectric regions extends all the way around the semiconducting fin.5. The transistor of wherein at least one of the two low-k dielectric regions comprises an air gap extending at least half-way across a width of the low-k-dielectric region.6. The transistor of wherein a dielectric constant of at least one of the two low-k dielectric regions is less than three.7. (canceled)8. A transistor prepared by the process of:providing a substrate having a gate formed all the way around a ...

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07-01-2016 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20160005865A1
Принадлежит: Renesas Electronics Corp

The semiconductor device has a gate electrode GE formed on a substrate via a gate insulating film GI and a source/drain semiconductor layer EP 1 formed on the substrate. The upper surface of the semiconductor layer EP 1 is positioned higher than the upper surface of the substrate straight below the gate electrode GE. And, end parts of the gate electrode GE in a gate length direction are positioned on the semiconductor layer EP 1.

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04-01-2018 дата публикации

FORMING FINS UTILIZING ALTERNATING PATTERN OF SPACERS

Номер: US20180005898A1
Автор: Cheng Kangguo, Xu Peng
Принадлежит:

A method of forming a semiconductor structure includes forming a first pattern of alternating spacers of a first material and a second material on a semiconductor substrate, forming a second pattern of the alternating spacers of the first material and the second material by selectively removing at least a portion of at least one of one or more of the spacers of the first material and one or more of the spacers of the second material to form a remaining pattern of spacers of the first material and the second material on the semiconductor substrate, and transferring the second pattern of the spacers of the first material and the second material to the semiconductor substrate to form two or more fins in the semiconductor substrate by etching the semiconductor substrate selective to the first material and the second material. 1. A semiconductor structure , comprising:a substrate; andtwo or more fins formed in the substrate in a given pattern, each of the two or more fins having a pad layer formed on a top surface thereof and a spacer formed over a top of the pad layer;wherein the given pattern comprises alternating spacers of a first material and a second material with at least a portion of one of the spacers removed via a cut mask.2. The semiconductor structure of claim 1 , wherein a fin pitch between at least two of the fins is less than 30 nanometers.3. The semiconductor structure of claim 1 , wherein the first material comprises a nitride and the second material comprises an oxide.4. The semiconductor structure of claim 1 , wherein the substrate comprises one of bulk semiconductor and a semiconductor-on-insulator.5. The semiconductor structure of claim 1 , wherein the pad layer comprises silicon oxynitride.6. The semiconductor structure of claim 1 , wherein the pad layer comprises at least one of silicon carbide nitride claim 1 , silicon oxy carbide nitride and silicon boron carbide nitride.7. The semiconductor structure of claim 1 , wherein the first material ...

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04-01-2018 дата публикации

DEVICE HAVING AN ACTIVE CHANNEL REGION

Номер: US20180006020A1
Автор: Benjamin Trudy
Принадлежит:

In some examples, a transistor includes a drain, a channel, and a gate. The channel surrounds the drain and has a channel length to width ratio. The gate is over the channel to provide an active channel region that has an active channel region length to width ratio that is greater than the channel length to width ratio. 1. A transistor comprising:a substrate;a drain in the substrate;a source in the substrate;a channel between the drain and the source, the channel surrounding the drain and having a channel length to width ratio; anda gate over the channel to provide an active channel region that has an active channel region length to width ratio that is greater than the channel length to width ratio.2. The transistor of claim 1 , wherein the gate comprises polysilicon.3. The transistor of claim 1 , wherein the channel comprises a plurality of channel regions claim 1 , and the gate comprises a plurality of gate regions over respective channel regions of the plurality of channel regions.4. The transistor of claim 3 , further comprising a gate lead electrically contacted to the gate regions claim 3 , a drain lead electrically contacted to the drain claim 3 , and a source lead electrically contacted to the source claim 3 , the gate lead claim 3 , the drain lead claim 3 , and the source lead formed by a first metal layer.5. The transistor of claim 1 , wherein the gate is disposed over a first portion of the channel claim 1 , and is not disposed over a second portion of the channel claim 1 , wherein the active channel region is provided by the first portion claim 1 , and the inactive channel region is provided by the second portion.6. The transistor of claim 5 , further comprising a dielectric layer between the gate and the first portion of the channel.7. The transistor of claim 5 , wherein a width of the active channel region is less than a width of the channel.8. The transistor of claim 7 , wherein the width of the active channel region is defined by a width of the gate. ...

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04-01-2018 дата публикации

FORMATION OF A SEMICONDUCTOR DEVICE WITH RIE-FREE SPACERS

Номер: US20180006030A1
Принадлежит:

A method of forming a fin-type field effect transistor (FinFET) can comprise forming at least one fin having an active region and a non-active region. Thereafter, a nitride is deposited on the fin. A dummy gate and nitride mask are formed on the fin over the nitride. Oxide spacers are formed on sidewalls of the dummy gate. The nitride is removed from the fin. Thereafter, a source region and a drain region are formed in the active region of the at least one fin. The result is a more reliable finFET without any possible pinch-off problems and fin erosion. Other embodiments are also described herein. 1. A method of forming a structure of a semiconductor device , the method comprising:forming at least one fin having an active region and a non-active region;forming a single first nitride on the fin;forming a dummy gate and nitride mask on the fin over the single first nitride, wherein the dummy gate is in contact with the single first nitride on the fin;forming oxide spacers on sidewalls of the dummy gate; andremoving the single first nitride and forming a source region and a drain region.2. The method of further comprising removing the dummy gate and nitride mask to form a trench.3. The method of further comprising forming a gate structure in the trench.4. The method of wherein forming the gate structure comprises:removing nitride covering the fin in the gate trench;depositing a high-K dielectric material in the trench; anddepositing a metal material on the dielectric material.5. The method of wherein the metal material is chosen from aluminum and tungsten.6. The method of further comprising depositing a metal liner between the high-K dielectric material and the gate metal.7. The method of further comprising performing a native oxide clean prior to forming oxide spacers.8. The method of wherein depositing the single first nitride on the fin comprises performing a nitradation in NH.9. The method of wherein the dummy gate comprises either an amorphous silicon or a ...

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07-01-2021 дата публикации

INTEGRATED CIRCUIT DEVICE

Номер: US20210005606A1
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

An integrated circuit device includes a first fin separation insulating portion over the first device region; a pair of first fin-type active regions apart from each other with the first fin separation insulating portion therebetween and collinearly extending in a first horizontal direction; a first dummy gate structure vertically overlapping the first fin separation insulating portion; a second fin separation insulating portion apart from the first fin separation insulating portion and arranged over the second device region; and a plurality of second fin-type active regions apart from each other with the second fin separation insulating portion therebetween in the second device region and collinearly extending in the first horizontal direction, wherein a vertical level of a lowermost surface of the second fin separation insulating portion is equal to or lower than a vertical level of a lowermost surface of the first fin separation insulating portion. 1. An integrated circuit device comprising:a substrate comprising a first device region and a second device region;a first fin separation insulating portion over the first device region, the first fin separation insulating portion having a first vertical length in a vertical view;a pair of first fin-type active regions spaced apart from each other in the first device region with the first fin separation insulating portion therebetween, the pair of first fin-type active regions collinearly extending in a first horizontal direction;a plurality of dummy gate structures extending parallel to each other in a second horizontal direction over the first fin separation insulating portion and the pair of first fin-type active regions, the second horizontal direction crossing the first horizontal direction;a second fin separation insulating portion spaced apart from the first fin separation insulating portion and arranged over the second device region, the second fin separation insulating portion having a second vertical length ...

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07-01-2021 дата публикации

SEMICONDUCTOR DEVICE WITH FIN TRANSISTORS AND MANUFACTURING METHOD OF SUCH SEMICONDUCTOR DEVICE

Номер: US20210005607A1
Автор: Matsumoto Koichi
Принадлежит: SONY CORPORATION

A semiconductor device and method of making same. The semiconductor device includes: a first conductivity type transistor and a second conductivity type transistor, wherein each of the first conductivity type transistor and the second conductivity type includes a gate insulating film formed on a base, a metal gate electrode formed on the gate insulating film, and side wall spacers formed at side walls of the metal gate electrode, wherein the gate insulating film is made of a high dielectric constant material, and wherein offset spacers are formed between the side walls of the metal gate electrode and the inner walls of the side wall spacers in any one of the first conductivity type transistor and the second conductivity type transistor, or offset spacers having different thicknesses are formed in the first conductivity type transistor and the second conductivity type transistor. 1each of the first conductivity type transistor and the second conductivity type includes agate insulating film formed on a base, a metal gate electrode formed on the gate insulating film, and side wall spacers formed at side walls of the metal gate electrode;the gate insulating film is made of a high dielectric constant material; andoffset spacers are (a) between the side walls of the metal gate electrode and the inner walls of the side wall spacers in any one of the first conductivity type transistor and the second conductivity type transistor, or (b) offset spacers in the first conductivity type transistor have a different thickness than offset spacers in the second conductivity type transistor.. A semiconductor device including a first conductivity type transistor and a second conductivity type transistor, wherein: This application is a continuation of U.S. Ser. No. 16/443,319 filed Jun. 17, 2019, which is a division of U.S. patent application Ser. No. 15/588,072 filed May 5, 2017, now U.S. Pat. No. 10,373,955 issued Aug. 6, 2019, which is a continuation of U.S. patent application Ser. ...

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04-01-2018 дата публикации

DEVICE WITH REINFORCED METAL GATE SPACER AND METHOD OF FABRICATING

Номер: US20180006133A1
Принадлежит:

A semiconductor device with reinforced gate spacers and a method of fabricating the same. The semiconductor device includes low-k dielectric gate spacers adjacent to a gate structure. A high-k dielectric material is disposed over an upper surface of the low-k dielectric gate spacers to prevent unnecessary contact between the gate structure and a self-aligned contact structure. The high-k dielectric material may be disposed, if desired, over an upper surface of the gate structure to provide additional isolation of the gate structure from the self-aligned contact structure. 1. A semiconductor device comprising:a substrate;a gate structure on a channel portion of the substrate;a gate spacer adjacent to the gate structure;a first high-k dielectric material directly on an upper surface of the gate spacer; anda second high-k dielectric material directly on an upper surface of the gate structure.2. The semiconductor device of claim 1 , further comprising a mask material disposed directly on the second high-k dielectric material.3. The semiconductor device of claim 2 , wherein the mask material is within inner sidewalls of the first high-k dielectric material.4. The semiconductor device of claim 3 , wherein a bottom surface of the first high-k dielectric material is higher than a bottom surface of the second high-k dielectric material.5. The semiconductor device of claim 3 , wherein a bottom surface of the first high-k dielectric material is lower than a bottom surface of the second high-k dielectric material.6. The semiconductor device of claim 3 , wherein a bottom surface of the first high-k dielectric material is substantially level to a bottom surface of the second high-k dielectric material.7. The semiconductor device of claim 1 , wherein the upper surface of the gate spacer is higher than the upper surface of the gate structure.8. The semiconductor device of claim 7 , further comprising a self-aligned contact structure directly contacting a sidewall of the first high- ...

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04-01-2018 дата публикации

Semiconductor device including optimized elastic strain buffer

Номер: US20180006154A1
Принадлежит: International Business Machines Corp

According to yet another non-limiting embodiment, a fin-type field effect transistor (finFET) including a strained channel region includes a semiconductor substrate extending along a first axis to define a length, a second axis perpendicular to the first axis to width, and a third direction perpendicular to the first and second axes to define a height. At least one semiconductor fin on an upper surface of the semiconductor substrate includes a semiconductor substrate portion on an upper surface of the semiconductor substrate, a strain-inducing portion on an upper surface of the semiconductor substrate portion, and an active semiconductor portion defining a strained channel region on an upper surface of the strain-inducing portion. A first height of the semiconductor substrate portion is greater than a second height of the strain-inducing portion.

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04-01-2018 дата публикации

Radiation Sensor, Method of Forming the Sensor and Device Including the Sensor

Номер: US20180006181A1
Принадлежит:

A semiconductor device includes a semiconductor structure formed on a substrate, a gate formed on a first side of the semiconductor structure, and a charge collector layer formed on a second side of the semiconductor structure. 1. A semiconductor device , comprising:a semiconductor structure formed on a substrate;a gate formed on a first side of the semiconductor structure; anda charge collector layer formed on a second side of the semiconductor structure.2. The semiconductor device of claim 1 , wherein the semiconductor device comprises a radiation sensor claim 1 , andwherein the semiconductor structure comprises a fin structure comprising semiconductor material, and the charge collector layer comprises a charge collector dielectric layer.3. The semiconductor device of claim 2 , wherein the fin structure comprises a pair of fin structures.4. The semiconductor device of claim 2 , further comprising:a gate dielectric formed between the gate and the first side of the fin structure.5. The semiconductor device of claim 4 , wherein the gate comprises a metal gate and the gate dielectric comprises a high-k dielectric material.6. The semiconductor device of claim 2 , wherein the charge collector dielectric layer comprises an oxide layer.7. The semiconductor device of claim 2 , wherein the radiation sensor comprises a modified vertical field effect transistor (VFET) claim 2 , a threshold voltage of the modified VFET shifting as a function of radiation dose claim 2 , and the gate being operable to sense the shifting of the threshold voltage.8. The semiconductor device of claim 2 , further comprising:a first source/drain region formed on the substrate, the fin structure being formed on the first source/drain region.9. The semiconductor device of claim 8 , further comprising:a second source/drain region formed on an upper surface of the fin structure.10. The semiconductor device of claim 8 , further comprising:a bottom spacer formed on the first source/drain region, the gate ...

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02-01-2020 дата публикации

Forming Nitrogen-Containing Low-K Gate Spacer

Номер: US20200006151A1
Автор: Kao Wan-Yi, Ko Chung-Chi
Принадлежит:

A method includes forming a dummy gate stack over a semiconductor region of a wafer, and depositing a gate spacer layer using Atomic Layer Deposition (ALD) on a sidewall of the dummy gate stack. The depositing the gate spacer layer includes performing an ALD cycle to form a dielectric atomic layer. The ALD cycle includes introducing silylated methyl to the wafer, purging the silylated methyl, introducing ammonia to the wafer, and purging the ammonia. 1. A method comprising:forming a dummy gate stack over a semiconductor region of a wafer; and introducing silylated methyl to the wafer;', 'purging the silylated methyl;', 'introducing ammonia to the wafer; and', 'purging the ammonia., 'depositing a gate spacer layer using Atomic Layer Deposition (ALD) on a sidewall of the dummy gate stack, wherein the depositing the gate spacer layer comprises performing an ALD cycle to form a dielectric atomic layer, wherein the ALD cycle comprises2. The method of further comprising performing an anneal on the wafer after the gate spacer layer is formed claim 1 , wherein the anneal is performed with the wafer placed in an oxygen-containing gas.3. The method of claim 2 , wherein the anneal is performed at a temperature in a range between about 400° C. and about 500° C.4. The method of claim 2 , wherein before the anneal claim 2 , the gate spacer layer has a first nitrogen atomic percentage claim 2 , and after the anneal claim 2 , a portion of the gate spacer layer has a second nitrogen atomic percentage lower than the first nitrogen atomic percentage.5. The method of claim 2 , wherein before the anneal claim 2 , the gate spacer layer has a first k value higher than a k value of silicon oxide claim 2 , and after the anneal claim 2 , a portion of the gate spacer layer has a second k value lower than the k value of silicon oxide.6. The method of claim 1 , wherein the depositing the gate spacer layer further comprises introducing ammonia to the wafer before performing the ALD cycle.7. The ...

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03-01-2019 дата публикации

Production of semiconductor regions in an electronic chip

Номер: US20190006229A1
Автор: Franck Julien
Принадлежит: STMICROELECTRONICS ROUSSET SAS

A method can be used for fabricating first and second semiconductor regions separated by isolating trenches. A semiconductor substrate is covered with a first silicon nitride layer. The first region is covered with a protection layer that can be etched selectively with respect to the silicon nitride. The structure is covered with a second silicon nitride layer. The trenches are etched through the second and first silicon nitride layers and filled with a filling silicon oxide to a level situated above the protection layer. The second silicon nitride layer and the part of the first silicon nitride layer situated on the second region are selectively removed and the protection layer is removed. The filling oxide is selectively etched by wet etching, thus resulting in pits on the surface of the filling oxide around the second region.

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03-01-2019 дата публикации

Self-Aligned Spacers and Method Forming Same

Номер: US20190006236A1
Принадлежит:

A method includes forming a bottom source/drain contact plug in a bottom inter-layer dielectric. The bottom source/drain contact plug is electrically coupled to a source/drain region of a transistor. The method further includes forming an inter-layer dielectric overlying the bottom source/drain contact plug. A source/drain contact opening is formed in the inter-layer dielectric, with the bottom source/drain contact plug exposed through the source/drain contact opening. A dielectric spacer layer is formed to have a first portion extending into the source/drain contact opening and a second portion over the inter-layer dielectric. An anisotropic etching is performed on the dielectric spacer layer, and a remaining vertical portion of the dielectric spacer layer forms a source/drain contact spacer. The remaining portion of the source/drain contact opening is filled to form an upper source/drain contact plug. 1. A device comprising:a semiconductor substrate;a gate stack over the semiconductor substrate;a source/drain region on a side of the gate stack;a first inter-layer dielectric over the source/drain region, wherein at least a portion of the gate stack is in the first inter-layer dielectric;a second inter-layer dielectric overlying the first inter-layer dielectric;a third inter-layer dielectric overlying the second inter-layer dielectric;a gate contact spacer penetrating through the second inter-layer dielectric and the third inter-layer dielectric; anda gate contact plug electrically coupling to the gate stack, wherein the gate contact plug is encircled by the gate contact spacer.2. The device of further comprising:gate spacers on opposite sides of the gate stack, wherein top surfaces of the gate spacers are higher than a top surface of the gate stack, and the gate contact spacer extends between the gate spacers.3. The device of claim 2 , wherein a sidewall of the gate contact spacer contacts a sidewall of the gate spacers to form a vertical interface.4. The device of ...

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03-01-2019 дата публикации

SEMICONDUCTOR DEVICES, FINFET DEVICES, AND MANUFACTURING METHODS THEREOF

Номер: US20190006244A1
Принадлежит:

Semiconductor devices, fin field effect transistor (FinFET) devices, and methods of manufacturing semiconductor devices are disclosed. In some embodiments, a semiconductor device includes a substrate comprising a first fin and a second fin. A first epitaxial fin is disposed over the first fin, and a second epitaxial fin is disposed over the second fin. The second fin is proximate the first fin. The first epitaxial fin and the second epitaxial fin have an upper portion with a substantially pillar shape. 1. A semiconductor device comprising:a substrate comprising a first fin;an isolation region surrounding a lower portion of the first fin;a first epitaxial fin disposed over the first fin, the first epitaxial fin extending above a top surface of the isolation region;a gate electrode over the first fin and the first epitaxial fin; anda first epitaxial source/drain region on the first fin and adjacent the first epitaxial fin, the first epitaxial source/drain region having a first portion extending above the top surface of the isolation region and a second portion below the top surface of the isolation region, a lowest portion of the first portion of the first epitaxial source/drain region being the widest portion of the first epitaxial source/drain region.2. The semiconductor device of claim 1 , wherein an upper portion of the first portion of the first epitaxial source/drain region has parallel sidewalls.3. The semiconductor device of claim 1 , wherein an upper portion of the first portion of the first epitaxial source/drain region has a first width claim 1 , wherein the second portion of the first epitaxial source/drain region has a second width claim 1 , the second width being less than the first width.4. The semiconductor device of claim 1 , wherein the widest portion of the first epitaxial source/drain region contacts the top surface of the isolation region.5. The semiconductor device of further comprising:a first barrier portion residue disposed under first edges ...

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02-01-2020 дата публикации

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME

Номер: US20200006333A1
Принадлежит:

A semiconductor device may include first channels on a first region of a substrate and spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate, second channels on a second region of the substrate and spaced apart from each other in the vertical direction, a first gate structure on the first region of the substrate and covering at least a portion of a surface of each of the first channels, and a second gate structure on the second region of the substrate and covering at least a portion of a surface of each of the second channels. The second channels may be disposed at heights substantially the same as those of corresponding ones of the first channels, and a height of a lowermost one of the second channels may be greater than a height of a lowermost one of the first channels. 1. A semiconductor device , comprising:a substrate including a first region and a second region adjacent to or spaced apart from the first region;first channels disposed on the first region of the substrate, the first channels being spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate;second channels disposed on the second region of the substrate, the second channels being spaced apart from each other in the vertical direction;a first gate structure disposed on the first region of the substrate, the first gate structure covering at least a portion of a surface of each of the first channels; anda second gate structure disposed on the second region of the substrate, the second gate structure covering at least a portion of a surface of each of the second channels,wherein the second channels are disposed at heights substantially the same as those of corresponding ones of the first channels, and a height of a lowermost one of the second channels is greater than a height of a lowermost one of the first channels.2. The semiconductor device of claim 1 , wherein a height of an ...

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02-01-2020 дата публикации

Method for forming an integrated circuit and an integrated circuit

Номер: US20200006360A1

A method for forming an integrated circuit (IC) and an IC are disclosed. The method for forming the IC includes: forming an isolation structure separating a memory semiconductor region from a logic semiconductor region; forming a memory cell structure on the memory semiconductor region; forming a memory capping layer covering the memory cell structure and the logic semiconductor region; performing a first etch into the memory capping layer to remove the memory capping layer from the logic semiconductor region, and to define a slanted, logic-facing sidewall on the isolation structure; forming a logic device structure on the logic semiconductor region; and performing a second etch into the memory capping layer to remove the memory capping layer from the memory semiconductor, while leaving a dummy segment of the memory capping layer that defines the logic-facing sidewall.

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02-01-2020 дата публикации

Stacked Vertically Isolated Mosfet Structure and Method of Forming the Same

Номер: US20200006389A1
Принадлежит:

A MOSFET structure including stacked vertically isolated MOSFETs and a method for forming the same are disclosed. In an embodiment, the method may include depositing a first buffer layer over a substrate; depositing a first channel layer over the first buffer layer; depositing a second buffer layer over the first channel layer; depositing a second channel layer over the second buffer layer; depositing a third buffer layer over the second channel layer; etching the first buffer layer, the first channel layer, the second buffer layer, the second channel layer, and the third buffer layer to form a fin structure; etching the first buffer layer, the second buffer layer, and the third buffer layer to form a first plurality of openings; forming a first gate stack in the first opening disposed in the first buffer layer, a second gate stack in the first opening disposed in the second buffer layer, and a third gate stack in the first opening disposed in the third buffer layer; and replacing the second buffer layer and a portion of the second gate stack with an isolation structure. 1. A method comprising:depositing a first buffer layer over a substrate;depositing a first channel layer over the first buffer layer;depositing a second buffer layer over the first channel layer;depositing a second channel layer over the second buffer layer;depositing a third buffer layer over the second channel layer;etching the first buffer layer, the first channel layer, the second buffer layer, the second channel layer, and the third buffer layer to form a fin structure;etching the first buffer layer, the second buffer layer, and the third buffer layer to form a first plurality of openings;forming a first gate stack in the first opening disposed in the first buffer layer, a second gate stack in the first opening disposed in the second buffer layer, and a third gate stack in the first opening disposed in the third buffer layer; andreplacing the second buffer layer and a portion of the second gate ...

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03-01-2019 дата публикации

ENHANCED CHANNEL STRAIN TO REDUCE CONTACT RESISTANCE IN NMOS FET DEVICES

Номер: US20190006363A1
Принадлежит:

A semiconductor device includes a substrate, a fin structure and an isolation layer formed on the substrate and adjacent to the fin structure. The semiconductor device includes a gate structure formed on at least a portion of the fin structure and the isolation layer. The semiconductor device includes an epitaxial layer including a strained material that provides stress to a channel region of the fin structure. The epitaxial layer has a first region and a second region, in which the first region has a first doping concentration of a first doping agent and the second region has a second doping concentration of a second doping agent. The first doping concentration is greater than the second doping concentration. The epitaxial layer is doped by ion implantation using phosphorous dimer. 1. A method of fabricating a fin field-effect transistor (Fin FET) device , the method comprising:forming a first gate structure over a channel region in a first portion of a first fin structure on a semiconductor substrate;forming first source/drain regions on a second portion of the first fin structure on opposing sides of the gate structure;implanting a first dopant in a first region of the first source/drain regions, the first region having a first doping concentration of the first dopant, the first doping concentration being greater than a second doping concentration of a second dopant in a second region of the first source/drain regions; andapplying a thermal anneal operation to at least the first fin structure and the first source/drain regions, the channel region of the first fin structure having greater channel mobility than a channel region of a second fin structure on the substrate.2. The method of claim 1 , further comprising:forming a second gate structure over a channel region in a first portion of a second fin structure on the semiconductor substrate; andforming second source/drain regions on a second portion of the second fin structure on opposing sides of the second gate ...

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03-01-2019 дата публикации

EIGHT-TRANSISTOR STATIC RANDOM-ACCESS MEMORY, LAYOUT THEREOF, AND METHOD FOR MANUFACTURING THE SAME

Номер: US20190006372A1
Принадлежит:

A Static Random Access Memory (SRAM) cell includes a write port including a first inverter including a first pull-up transistor and a first pull-down transistor, and a second inverter including a second pull-up transistor and a second pull-down transistor and cross-coupled with the first inverter; and a read port including a read pass-gate transistor and a read pull-down transistor serially connected to each. A first doped concentration of impurities doped in channel regions of the second pull-down transistor and the read pull-down transistor is greater than a second doped concentration of the impurities doped in a channel region of the first pull-down transistor, or the impurities are doped in the channel regions of the second pull-down transistor and the read pull-down transistor and are not doped in the channel region of the first pull-down transistor. 1. A Static Random Access Memory (SRAM) cell , comprising:a write port including a first inverter including a first pull-up transistor and a first pull-down transistor, and a second inverter including a second pull-up transistor and a second pull-down transistor and cross-coupled with the first inverter; anda read port including a read pass-gate transistor and a read pull-down transistor serially connected to each, gate electrodes of the read pass-gate transistor, the second pull-down transistor, and the second pull-up transistors being electrically connected to each other,wherein a first doping concentration of impurities doped in channel regions of the second pull-down transistor and the read pull-down transistor is greater than a second doping concentration of the impurities doped in a channel region of the first pull-down transistor, or the impurities are doped in the channel regions of the second pull-down transistor and the read pull-down transistor and are not doped in the channel region of the first pull-down transistor.2. The SRAM cell of claim 1 , wherein:the first and second pass-gate transistors, the ...

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03-01-2019 дата публикации

SIDEWALL IMAGE TRANSFER NANOSHEET

Номер: US20190006463A1
Принадлежит:

A method for forming active regions of a semiconductor device comprising forming a nanosheet stack on a substrate, forming the nanosheet stack comprising forming a sacrificial nanosheet layer on the substrate, and forming a nanosheet layer on the sacrificial nanosheet layer, forming an etch stop layer on the nanosheet stack, forming a mandrel layer on the etch stop layer, removing portions of the mandrel layer to form a mandrel on the etch stop layer, forming sidewalls adjacent to sidewalls of the mandrel, depositing a fill layer on exposed portions of the etch stop layer, removing the sidewalls and removing exposed portions of the etch stop layer and the nanosheet stack to expose portions of the substrate. 1. A semiconductor device comprising:a substrate;a first semiconductor nanosheet arranged over the substrate in a first direction;a second semiconductor nanosheet arranged over the substrate in the first direction, the second semiconductor nanosheet arranged adjacent to the first semiconductor nanosheet in a second direction and separated by a gap having a gap length of approximately 2-10 nm in the second direction, the second direction being orthogonal to the first direction, wherein at least a portion of the gap resides in the substrate, wherein the first semiconductor nanosheet and the second semiconductor nanosheet are not arranged above the gap in the substrate; anda gate stack arranged over the substrate and channel regions of the first semiconductor nanosheet and the second semiconductor nanosheet.2. The device of claim 1 , wherein:the first semiconductor nanosheet has a width of approximately 10-50 nm in the second direction; andthe second semiconductor nanosheet has a width of approximately 10-50 nm in the second direction.3. The device of claim 1 , wherein each of the first semiconductor nanosheet and the second semiconductor nanosheet includes silicon.4. The device of claim 1 , wherein the gate stack includes a high-k dielectric and a work function ...

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03-01-2019 дата публикации

Semiconductor structure and fabrication method thereof

Номер: US20190006478A1
Автор: Fei Zhou

A semiconductor structure and a method for fabricating the semiconductor structure are provided. The method includes forming a gate structure and a dielectric layer on a substrate; and forming a sidewall spacer on a sidewall surface of the gate structure. The method also includes forming a source and drain doped region in the substrate on both sides of the gate structure. The dielectric layer covers a surface of the sidewall spacer. In addition, the method includes forming a source-drain plug in the dielectric layer. The source-drain plug is connected to the source and drain doped region. Moreover, the method includes forming an isolation opening in the dielectric layer by at least partially removing the sidewall spacer. Further, the method includes forming an isolation structure in the isolation opening, wherein the isolation structure has a dielectric constant less than the sidewall spacer.

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03-01-2019 дата публикации

Gate Structure, Semiconductor Device and the Method of Forming Semiconductor Device

Номер: US20190006483A1

A gate structure, a semiconductor device, and the method of forming a semiconductor device are provided. In various embodiments, the gate structure includes a gate stack and a doped spacer overlying a sidewall of the gate stack. The gate stack contains a doped work function metal (WFM) stack and a metal gate electrode overlying the doped WFM stack.

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03-01-2019 дата публикации

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

Номер: US20190006484A1
Принадлежит:

A semiconductor device includes a substrate, a gate structure, a spacer, a mask layer, and at least one void. The gate structure is disposed on the substrate, and the gate structure includes a metal gate electrode. The spacer is disposed on sidewalls of the gate structure, and a topmost surface of the spacer is higher than a topmost surface of the metal gate electrode. The mask layer is disposed on the gate structure. At least one void is disposed in the mask layer and disposed between the metal gate electrode and the spacer. 1. A manufacturing method of a semiconductor device , comprising:forming a gate structure on a substrate and in a trench surrounded by a spacer, wherein the gate structure comprises a metal gate electrode and a gate dielectric layer encompassing the metal gate electrode, and a topmost surface of the spacer is higher than a topmost surface of the metal gate electrode;forming a mask layer on the gate structure and in the trench, wherein at least one void is formed in the mask layer within the trench, and the at least one void is formed between the metal gate electrode and the spacer, wherein the bottom surface of the mask layer and the top surface of the gate dielectric layer are coplanar;forming a source/drain structure adjacent to the spacer;forming an etching stop layer on the source/drain structure; andforming a contact structure penetrating the etching stop layer, wherein the etching stop layer and the spacer are disposed between the at least one void and the contact structure.2. The manufacturing method of the semiconductor device according to claim 1 , further comprising:performing an etching back process to the gate structure before the step of forming the mask layer, wherein the gate structure further comprises a work function layer encompassing the metal gate electrode, and a topmost surface of the work function layer is lower than the topmost surface of the metal gate electrode after the etching back process.3. The manufacturing method ...

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03-01-2019 дата публикации

METHOD FOR FABRICATING SEMICONDUCTOR DEVICE

Номер: US20190006485A1
Принадлежит:

A method for fabricating a semiconductor device includes forming a stacked structure including at least one sacrificial layer and at least one semiconductor layer alternately stacked on a substrate, forming a dummy gate structure on the stacked structure, etching a recess in the stacked structure using the dummy gate structure as a mask, etching portions of the sacrificial layer exposed by the recess to form an etched sacrificial layer, forming a first spacer film on the etched sacrificial layer, forming a second spacer film on the first spacer film, the second spacer film including a material different from a material of the first spacer film, removing a first portion of the second spacer film, such that a second portion of the second spacer film remains, and forming a third spacer film on the second portion of the second spacer film. 1. A method for fabricating a semiconductor device , the method comprising:forming a stacked structure on a substrate, the stacked structure including at least one sacrificial layer and at least one semiconductor layer alternately stacked on the substrate;forming a dummy gate structure on the stacked structure;etching a recess in the stacked structure using the dummy gate structure as a mask;etching portions of the at least one sacrificial layer exposed by the recess to form at least one etched sacrificial layer;forming a first spacer film on the at least one etched sacrificial layer;forming a second spacer film on the first spacer film, the second spacer film including a material different from a material of the first spacer film;removing a first portion of the second spacer film, such that a second portion of the second spacer film remains; andforming a third spacer film on the second portion of the second spacer film.2. The method as claimed in claim 1 , wherein forming the dummy gate structure includes:forming a dummy gate on the stacked structure;conformally depositing an insulating film to cover an upper surface of the stacked ...

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02-01-2020 дата публикации

DIELECTRIC LINING LAYERS FOR SEMICONDUCTOR DEVICES

Номер: US20200006501A1
Принадлежит: Intel Corporation

Solid-state assemblies including dielectric lining layers having localized charges are provided. Processes to form the solid-state assemblies also are provided. The solid-state assemblies can included in CMOS transistors, where first dielectric lining layers having localized charges of positive polarity can be adjacent to the PMOS member and a second dielectric lining layers having localized charges of positive polarity can be adjacent to an NMOS member. The first dielectric lining layers can be adjacent to a first gate electrode of the CMOS transistor, and the second dielectric lining can be adjacent to a second gate electrode of the CMOS transistor. The first dielectric lining layers and the second dielectric lining layers can improve, at least in part, the performance of the CMOS transistor by attracting mobile carriers into respective transport channels of the PMOS member and the NMOS member. 125-. (canceled)26. A solid assembly , comprising:a carrier-doped semiconductor layer including mobile charges of a first polarity;a dielectric layer including localized charges of a second polarity opposite the first polarity; andan electrode member adjacent to the dielectric layer and further adjacent to the carrier-doped semiconductor layer.27. The solid assembly of claim 26 , wherein the carrier-doped semiconductor layer comprises an n-type III-V semiconductor compound claim 26 , and wherein the second polarity is positive polarity.28. The solid assembly of claim 26 , wherein the carrier-doped semiconductor layer comprises a p-type III-V semiconductor compound claim 26 , and wherein the second polarity is negative polarity.29. The solid assembly of claim 26 , wherein the dielectric layer comprises a low-K material comprising oxygen claim 26 , nitrogen claim 26 , carbon claim 26 , or silicon.30. The solid assembly of claim 26 , wherein the localized charges of the second polarity are arranged within the dielectric layer to an average charge density in a range of 10cmto ...

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02-01-2020 дата публикации

SOURCE OR DRAIN STRUCTURES WITH CONTACT ETCH STOP LAYER

Номер: US20200006504A1
Принадлежит:

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having source or drain structures with a contact etch stop layer are described. In an example, an integrated circuit structure includes a fin including a semiconductor material, the fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first epitaxial source or drain structure is embedded in the fin at the first side of the gate stack. A second epitaxial source or drain structure is embedded in the fin at the second side of the gate stack, the first and second epitaxial source or drain structures including a lower semiconductor layer, an intermediate semiconductor layer and an upper semiconductor layer. 1. An integrated circuit structure , comprising:a fin comprising a semiconductor material, the fin having a lower fin portion and an upper fin portion;a gate stack over the upper fin portion of the fin, the gate stack having a first side opposite a second side;a first epitaxial source or drain structure embedded in the fin at the first side of the gate stack; anda second epitaxial source or drain structure embedded in the fin at the second side of the gate stack, the first and second epitaxial source or drain structures comprising a lower semiconductor layer, an intermediate semiconductor layer and an upper semiconductor layer, wherein the intermediate semiconductor layer is different in composition than the upper and lower semiconductor layers.2. The integrated circuit structure of claim 1 , wherein the lower semiconductor layer claim 1 , the intermediate semiconductor layer and the upper semiconductor layer comprise silicon and germanium claim 1 , and wherein the intermediate semiconductor layer has a lower concentration of germanium and higher concentration of silicon than the upper and lower ...

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02-01-2020 дата публикации

Raised Epitaxial LDD in MuGFETs and Methods for Forming the Same

Номер: US20200006505A1
Принадлежит:

Embodiments include Multiple Gate Field-Effect Transistors (MuGFETs) and methods of forming them. In an embodiment, a structure includes a substrate, a fin, masking dielectric layer portions, and a raised epitaxial lightly doped source/drain (LDD) region. The substrate includes the fin. The masking dielectric layer portions are along sidewalls of the fin. An upper portion of the fin protrudes from the masking dielectric layer portions. A first spacer is along a sidewall of a gate structure over a channel region of the fin. A second spacer is along the first spacer. The raised epitaxial LDD region is on the upper portion of the fin, and the raised epitaxial LDD region adjoins a sidewall of the first spacer and is disposed under the second spacer. The raised epitaxial LDD region extends from the upper portion of the fin in at least two laterally opposed directions and a vertical direction. 1. A method comprising:forming a fin extending from a substrate;forming an isolation region around the fin, sidewalls of the fin protruding above the isolation region;forming a first dielectric layer over the fin and the isolation region;forming a metal-containing layer over the first dielectric layer;patterning the metal-containing layer to form a gate electrode;patterning the first dielectric layer to simultaneously form a gate dielectric and a mask, the mask being along lower portions of the sidewalls of the fin above the isolation region;growing a first epitaxial region on upper portions of the sidewalls of the fin and an upper surface of the fin, the first epitaxial region grown while the mask is along the lower portions of the sidewalls of the fin;forming a gate spacer adjacent the gate electrode and over the first epitaxial region;forming a recess in the fin; andgrowing a second epitaxial region in the recess.2. The method of claim 1 , wherein the first epitaxial region is an epitaxial region having a faceted surface.3. The method of claim 1 , wherein the substrate is a (001) ...

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02-01-2020 дата публикации

Transistor with inner-gate spacer

Номер: US20200006509A1
Принадлежит: Intel Corp

Techniques are disclosed for forming a transistor with one or more additional spacers, or inner-gate spacers, as referred to herein. The additional spacers may be formed between the gate and original spacers to reduce the parasitic coupling between the gate and the source/drain, for example. In some cases, the additional spacers may include air gaps and/or dielectric material (e.g., low-k dielectric material). In some cases, the gate may include a lower portion, a middle portion, and an upper portion. In some such cases, the lower and upper portions of the gate may be wider between the original spacers than the middle portion of the gate, which may be as a result of the additional spacers being located between the middle portion of the gate and the original spacers. In some such cases, the gate may approximate an I-shape, C-shape,

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02-01-2020 дата публикации

Gate Spacer and Methods of Forming

Номер: US20200006512A1
Принадлежит:

Methods and structures for forming devices, such as transistors, are discussed. A method embodiment includes forming a gate spacer along a sidewall of a gate stack on a substrate; passivating at least a portion of an exterior surface of the gate spacer; and epitaxially growing a material in the substrate proximate the gate spacer while the at least the portion of the exterior surface of the gate spacer remains passivated. The passivating can include using at least one of a thermal treatment, a plasma treatment, or a thermal treatment. 1. A method comprising:forming an electrode on a substrate;forming a spacer along a sidewall of the electrode;treating at least a portion of an exterior surface of the spacer, the treating terminating the at least the portion of the exterior surface with a passivating species;forming a recess in the substrate proximate the spacer;depositing a material in the recess while the at least the portion of the exterior surface is terminated with the passivating species; andafter depositing the material in the recess, removing the passivating species from the exterior surface of the spacer.2. The method of claim 1 , wherein the passivating species comprises oxygen claim 1 , fluorine claim 1 , or a combination thereof.3. The method of claim 1 , wherein the treating comprises exposing the at least the portion of the exterior surface of the spacer to a thermal treatment.4. The method of claim 1 , wherein the treating comprises exposing the at least the portion of the exterior surface of the spacer to a plasma treatment.5. The method of claim 1 , wherein the treating comprises a wet treatment applied to the at least the portion of the exterior surface of the spacer.6. The method of claim 1 , wherein depositing the material in the recess comprises epitaxially growing a semiconductor material in the recess.7. The method of claim 1 , wherein forming the spacer comprises:conformally depositing a spacer layer along the electrode; andetching the spacer ...

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02-01-2020 дата публикации

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

Номер: US20200006517A1
Принадлежит: UNITED MICROELECTRONICS CORP.

A structure of semiconductor device includes a gate structure, disposed on a substrate. A spacer is disposed on a sidewall of the gate structure, wherein the spacer is an l-like structure. A first doped region is disposed in the substrate at two sides of the gate structure. A second doped region is disposed in the substrate at the two sides of the gate structure, overlapping the first doped region. A silicide layer is disposed on the substrate within the second doped region, separating from the spacer by a distance. A dielectric layer covers over the second doped region and the gate structure with the spacer. 1. A structure of semiconductor device , comprising:a first gate structure and a second gate structure, disposed on a substrate, wherein a gap is between the first gate structure and the second gate structure;{'smallcaps': 'I', 'a spacer on a sidewall of the first gate structure and the second gate structure, wherein the spacer is an -like structure in cross-section view from top to bottom of the gate structure on the substrate;'}a first doped region in the substrate at two sides of the first gate structure and the second gate structure;a second doped region in the substrate at the two sides of the first gate structure and the second gate structure, overlapping with the first doped region;a silicide layer, disposed on the substrate within the second doped region, separating from the spacer by a distance, wherein a portion of the second doped region adjacent to the first doped region is not covered by the silicide layer; anda dielectric layer, disposed over the second doped region and the gate structure with the spacer, wherein the portion of the second doped region directly contacts the dielectric layer,wherein a part of the second doped region and a part of the silicide layer within the gap is a commonly shared by the first gate structure and the second gate structure,{'smallcaps': 'I', 'wherein a part of the dielectric layer within the gap is directly ...

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03-01-2019 дата публикации

UTILIZING MULTILAYER GATE SPACER TO REDUCE EROSION OF SEMICONDUCTOR FIN DURING SPACER PATTERNING

Номер: US20190006506A1
Принадлежит:

FinFET devices comprising multilayer gate spacers are provided, as well as methods for fabricating FinFET devices in which multilayer gate spacers are utilized to prevent or otherwise minimize the erosion of vertical semiconductor fins when forming the gate spacers. For example, a method for fabricating a semiconductor device comprises forming a dummy gate structure over a portion of a vertical semiconductor fin of a FinFET device, and forming a multilayer gate spacer on the dummy gate structure. The multilayer gate spacer comprises a first dielectric layer and a second dielectric layer, wherein the first dielectric layer has etch selectivity with respect to the vertical semiconductor fin and the second dielectric layer. In one embodiment, the first dielectric layer comprises silicon oxycarbonitride (SiOCN) and the second dielectric layer comprises silicon boron carbon nitride (SiBCN). 1. A method for fabricating a semiconductor device , comprising:forming a dummy gate structure over a portion of a vertical semiconductor fin of a FinFET (field effect transistor) device; andforming a multilayer gate spacer on the dummy gate structure;wherein the multilayer gate spacer comprises a first dielectric layer and a second dielectric layer; andwherein forming the multilayer gate spacer on the dummy gate structure comprises:depositing a first conformal layer of dielectric material over the dummy gate structure and portions of the vertical semiconductor fin which extend from sidewalls of the dummy gate structure;depositing a second conformal layer of dielectric material over the first conformal layer of dielectric material;performing a first etch process to etch the second conformal layer of dielectric material selective to the first conformal layer of dielectric material to form the second dielectric layer of the multilayer gate spacer, wherein the first etch process results in (i) removing portions of the second conformal layer of dielectric material covering the portions of ...

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