Halbleiteranordnung mit Metallplatte

MODUL-AUFBAU MIT INTEGRIERTEM HALBLEITERCHIP UND CHIPTRAEGER

Gehäuse eines integrierten Schaltkreises und Verfahren zum Bilden desselben

Eine Ausführungsform einer Gehäuse-auf-Gehäuse(PoP)-Vorrichtung umfasst eine Gehäusestruktur, einen Gehäuseträger und eine Vielzahl von Anschlüssen, die die Gehäusestruktur mit dem Gehäuseträger verbinden. Die Gehäusestruktur umfasst einen Logikchip, der mit einem Speicherchip verbunden ist, eine Formmasse, die den Speicherchip umschließt und eine Vielzahl leitfähiger Stifte, die sich durch die Formmasse hindurch erstrecken. Die Vielzahl der leitfähigen Stifte ist an Kontaktpolstern auf dem Logikchip befestigt.

Verfahren zur Herstellung eines Halbleiterbauteils mit Durchkontakten zwischen Oberseite und Rückseite

Die Erfindung betrifft ein Verfahren zur Herstellung eines Halbleiterbauteils (1) mit Durchkontakten (2) zwischen Oberseite (3) und Unterseite (4), wobei die Durchkontakte (2) in mindestens einem Randbereich (5) des Halbleiterbauteils (1) angeordnet sind. Die Durchkontakte (2) verbinden elektrisch miteinander Außenkontaktflächen (7, 8) des Halbleiterbauteils (1) auf der Oberseite (3) und Unterseite (4). Eine Kunststoffgehäusemasse (10) umgibt mindestens einen Halbleiterchip (9) mit Kontaktflächen (11) auf der aktiven Oberseite (12) des Halbleiterchips (9). Die Kontaktflächen (11) stehen mit den Durchkontakten (2) über eine Verdrahtungsstruktur (14) elektrisch in Verbindung, wobei die Durchkontakte (2) in mindestens einer vorgefertigten Durchkontaktleiste (15) angeordnet sind, die in dem Randbereich (5) des Halbleiterbauteils (1) positioniert ist.

Carrier for multilayer semiconductor device and process for manufacturing multilayer semiconductor device

Carrier for multilayer semiconductor device and process for manufacturing multilayer semiconductor device

A carrier for a multilayer semiconductor device comprising a lower stage carrier (3) having a first containing section (12) for containing a first semiconductor device (110) to be the lower side device, and an upper stage carrier (2) having a second containing section (14) for containing a second semiconductor device (120) to be stacked on the first semiconductor device (110) and arranging the second semiconductor device (120) at a specified position on the first semiconductor device (110). By having such a structure, no dedicated stacking device is required, and thus cost can be reduced.

Components, methods and assemblies for multi-chip packages

半导体装置及其制造方法、电子设备及其制造方法

... 一种半导体装置，在载体基板(11)背面所设的连接盘(12a)上，形成熔点比突出电极(24)还低的突出电极(17)，通过在比突出电极(24)的熔点还低、比突出电极(17)的熔点还高的温度下进行回流焊处理，可以使突出电极(17)接合在母基板(31)的连接盘(32)上。这样，可以防止在载体基板的2次安装时突出电极的融解。 ...

Thermal interface material layer and includes a thermal interface material layer of the stacked package device

Semiconductor device

The invention discloses a device which comprises a first semiconductor chip; a moulding compounds layer, embedded with the first semiconductor chip; a first electrical conductive layer, applied to moulding compounds layer, a through-hole, disposed at moulding compounds layer; and solder material, for filling through-hole.

Integrated circuit collector

반도체 패키지

... 본 발명의 일 실시예에 따른 반도체 패키지는 복수의 배선들이 형성된 기판, 상기 복수의 배선들 중 일부의 배선과 전기적으로 연결된 적어도 하나의 반도체 칩, 및 상기 기판에 실장되어 상기 적어도 하나의 반도체 칩을 둘러싸고, 상기 복수의 배선 중 적어도 하나의 배선과 전기적으로 연결되며, 연자성 물질을 포함하는 쉴딩 캔(shielding can)을 포함하여 전자기 간섭을 제거할 수 있다.

SUPPORT WITH SOLDER GLOBULE ELEMENTS AND A METHOD FOR ASSEMBLY OF SUBSTRATES WITH GLOBULE CONTACTS

STACKED PACKAGE AND METHOD FOR MANUFACTURING THE PACKAGE

ＴＳＶ를 가지는 인터포저를 포함하는 반도체 패키지 및 그 제조 방법

... 본 발명은, 상면과 하면을 포함하는 하부 기저 기판; 하부 기저 기판의 하면에 접촉하게 형성된 외부 연결 부재들, 하부 기저 기판의 상면 상에 위치하고 TSV(through silicon via)를 가지는 인터포저, 인터포저 상에 실장되고 인터포저에 전기적으로 연결된 하부 반도체 칩, 및 하부 반도체 칩을 밀봉하는 하부 몰딩 부재를 포함하는 하부 반도체 패키지; 하부 반도체 패키지 상에 위치하고, 상부 반도체 칩 및 상부 반도체 칩을 몰딩하는 상부 몰딩 부재를 포함하는 상부 반도체 패키지; 인터포저 상에 위치하고, 상부 반도체 패키지와 인터포저를 전기적으로 연결하는 패키지 연결 부재들; 하부 기저 기판의 상면으로부터 상부 반도체 패키지의 하면으로 연장되면서 인터포저를 밀봉하는 외측 몰딩 부재; 및 상기 상부 반도체 패키지와 상기 하부 반도체 패키지 사이에 위치하는 공기 간극을 포함하되, 상기 하부 몰딩 부재는 상기 하부 반도체 칩의 상면을 노출하면서 상기 패키지 연결 부재들이 위치하는 개구부를 포함한다.

Stack type package

A semiconductor package having a buried conductive post in sealing resin and manufacturing method thereof

SEMICONDUCTOR DEVICE, STACKED SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE

적층가능 마이크로전자 패키지 구조

... 마이크로전자 어셈블리(8)는 제 1 면(14) 및 제 2 면(16) 및 기판 콘택(24)이 있는 기판(12)을 가지는 제 1 마이크로전자 패키지(10A)를 포함한다. 제 1 패키지는 기판 콘택과 전기적으로 접속되고 제 1 면 상에서 서로로부터 이격되어 제 1 및 제 2 마이크로전자 소자 사이에 상호접속 영역을 제공하는 소자 콘택(24)을 가지는 제 1 및 제 2 마이크로전자 소자(40)를 더 포함한다. 제 2 면에서의 복수 개의 패키지 단자(26)는 패키지를 외부 컴포넌트와 접속시키기 위하여 기판 콘택과 상호접속된다. 복수 개의 스택 단자(58)는 패키지를 기판의 제 1 면에 상재하는 컴포넌트와 접속시키기 위하여 상호접속 영역 내의 제 1 면에서 노출된다. 어셈블리는 제 1 마이크로전자 패키지에 상재하며 제 1 마이크로전자 패키지의 스택 단자에 결합되는 단자(26)를 가지는 제 2 마이크로전자 패키지(10B)를 더 포함한다.

SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME

이중 랜드를 갖는 반도체패키지 및 관련된 장치

... 이중 랜드(dual land)를 갖는 반도체패키지를 제공한다. 상기 반도체패키지는 다수의 내부 패드들을 갖는 기판을 구비한다. 반도체 칩이 상기 기판에 부착된다. 상기 반도체 칩은 상기 내부 패드들에 전기적으로 접속된다. 상기 기판에 형성되고 상기 내부 패드들에 전기적으로 접속된 다수의 랜드들을 제공한다. 상기 기판에 형성된 적어도 하나의 우회배선을 제공한다. 상기 우회배선은 제 1 랜드 및 제 2 랜드에 접속된다. 상기 제 1 랜드는 상기 랜드들 중 선택된 하나이고, 상기 제 2 랜드는 상기 랜드들 중 선택된 다른 하나이다. 상기 제 1 랜드 및 상기 제 2 랜드는 상기 랜드들 사이의 평균거리보다 3배 이상 떨어진다.

Substrate of Semiconductor Package, Semiconductor Package including the same and Stack Package using the same

반도체 패키지들, 그들의 적층 구조와 그 제조 방법들

... 반도체 패키지들의 적층 구조들과 그 제조 방법들, 반도체 패키지들의 적층 구조를 포함하는 반도체 모듈 및 전자 시스템이 설명된다. 본 발명의 기술적 사상에 의한 반도체 패키지들의 적층 구조는, 하부 패키지 기판 및 상기 하부 패키지 기판의 상부에 배치된 하부 반도체 칩을 포함하는 하부 반도체 패키지, 상부 패키지 기판 및 상기 상부 패키지 기판의 상부에 배치된 상부 반도체 칩을 포함하는 상부 반도체 패키지, 및 상기 하부 패키지 기판과 상기 상부 패키지 기판을 전기적으로 연결하는 패키지간 연결부를 포함하고, 상기 패키지간 연결부는 상기 하부 패키지 기판의 상부에 형성된 제1 수직 높이를 가진 하부 연결부 및 상기 상부 패키지 기판의 하부에 형성된 상기 제1 수직 높이보다 큰 제2 수직 높이를 가진 상부 연결부를 포함한다.

STACKED SEMICONDUCTOR PACKAGE CAPABLE OF INCREASING JOINT RELIABILITY AND HEAT EMITTING FEATURES

PURPOSE: A stacked semiconductor package is provided to arrange an external connection terminal on the entire area of a lower package, thereby suppressing warpage of the semiconductor package during a molding process or a thermal processing process. CONSTITUTION: A lower package(100) includes a first substrate(110) and a first semiconductor chip(120). The first substrate includes one side(110A) and the other side(110B) facing the one side. The first semiconductor chip is attached to the central part of the other side of the first substrate by a first adhesive member(170). An upper package(200) is mounted on the first borland of the first substrate. The upper package includes a second substrate(210), a second semiconductor chip(220), and a second external connection terminal(250). COPYRIGHT KIPO 2012 ...

SEMICONDUCTOR PACKAGE, CAPABLE OF PROVIDING A MULTI-CHIP PACKAGE INCLUDING AN IMPROVED THERMAL RELIABILITY

PURPOSE: A semiconductor package is provided to reduce heat concentration in the semiconductor package by spacing the heat of a first semiconductor chip apart from the heat of a second semiconductor chip. CONSTITUTION: A frost substrate(300) includes a first substrate pad(320) and a second substrate pad(322) which are spaced apart. A first semiconductor chip(100) includes a first side(101), a second side(102), a cell area(C) and a peripheral circuit area(P). A second semiconductor chip includes a first chip pad(110) and a second chip pad(210). The first chip pad is arranged on the peripheral circuit area the first semiconductor chips and is electrically connected to the first substrate pad. The second chip pad is electrically connected to the second substrate pad. COPYRIGHT KIPO 2010 ...

COMPOSITE TYPE SEMICONDUCTOR DEVICE SPACER SHEET, SEMICONDUCTOR PACKAGE USING THE SAME, COMPOSITE TYPE SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND COMPOSITE TYPE SEMICONDUCTOR DEVICE

Provided is a composite type semiconductor device spacer sheet to be arranged between semiconductor packages of a composite type semiconductor device formed by layering a plurality of semiconductor packages. The composite type semiconductor device spacer sheet has through holes arranged to correspond to electrodes which can be attached top a first semiconductor substrate and are formed on the substrate to make electric connections between the first semiconductor package and the second semiconductor package and a void portion corresponding to a main part of the first semiconductor package or a main part of the second semiconductor package. Also provided is a composite type semiconductor device manufacturing method using the spacer sheet. In a POP type semiconductor package, it is possible to provide a wire connection method using the spacer sheet which simultaneously satisfies the sufficient height of the connection terminal distance and a narrow pitch. This enables provision of a POP type ...

MULTI FUNCTIONAL MULTI CHIP PACKAGE STRUCTURE OF A PACKAGE-ON-PACKAGE TYPE, CAPABLE OF SIMULTANEOUSLY INCREASING THE CAPACITY OF AN ELECTRIC DEVICE AND MINIMIZING A MOUNT AREA

PURPOSE: A multi functional multi chip package structure of a package-on-package type is provided to implement a package stack structure of a package-on-package type by mounting a multi chip package to perform a high speed image process function on a memory package with high capacity. CONSTITUTION: A plurality of memory semiconductor chips(120) is vertically stacked on a PCB substrate(110) using a chip-on-chip method. The semiconductor chips are electrically connected to each other by bonding with a PCB substrate using a wire(140). The semiconductor chip is electrically connected to the outside by a solder ball(150). The solder ball is bonded with a ball land of a lower PCB substrate(210). A protection member(160) is molded on the substrate to protect the semiconductor chip and the wire. COPYRIGHT KIPO 2010 ...

DIGITAL TELEVISION RECEIVER CIRCUIT MODULE

A digital television receiver circuit module (1) is formed by superimposing a decoder layer board (507) including a decoder LSI (2), which incorporates a CPU and a decoder, and also including a CA interface circuit (3); a demodulating function layer board (620-1) including a demodulator (12); and an expanding function layer board (401) including a communication controller (404). Either one of the demodulating function layer board (620-1) and expanding function layer board (401) can be selectively superimposed on the decoder layer board (507) in accordance with the type of the broadcast system of a digital television signal or the type of CA module. © KIPO & WIPO 2007 ...

INTEGRATED CIRCUIT PACKAGE SYSTEM FOR PACKAGE STACKING TO REDUCE A VERTICAL HEIGHT OF FINAL PACKAGES

PURPOSE: An IC package system for package stacking is provided to improve fatigue lifetime and reliability of package by implementing a package body in which flip chip ICs and bumps are embedded. CONSTITUTION: An area array substrate(102) is formed. Surface conductors(120) are mounted on the area array substrate. A molded package body(122) is formed on the area array substrate and the surface conductors. At this time, a first IC(Integrated Circuit)(110) is electrically connected to the area array substrate. A second IC(118) is positioned on the first IC. Molding compound is provided on the area array substrate, the surface conductors, and the first and second ICs. Then a step(124) is provided to the molded package body. The surface conductors are exposed by the step. The surface conductors are contacted with the area array substrate. © KIPO 2008 ...

BALL GRID ARRAY SOLDER ATTACHMENT

A reflow grid array (RGA) technology can be conducted on an interposer device which is disposed between a mother board and an RGA package. The interposer can provide a heat source which is controlled to reflow a solder between the interposer and a BGA package. A technical issue confronted by the interposer which uses the RGA technology is to apply the solder to the RGA interposer. To solve the issue, the solder is applied to make the RGA interposer connected to the BGA package, and a process and facility for forming a solder ball are provided as well. COPYRIGHT KIPO 2017 (110A,110B,120C) Package (120A,120B,120C) RGA interposer (130A,130B,130C) Motherboard ...

SEMICONDUCTOR PACKAGE HAVING AN INK-JET TYPE DAM AND A METHOD OF MANUFACTURING THE SAME, CAPABLE OF EFFECTIVELY PREVENTING BLEEDING OF UNDERFILL MATERIAL

PURPOSE: A semiconductor package having an ink-jet type dam and a method of manufacturing the same are provided to form easily a dam without an additional process by installing a semiconductor chip on a substrate and forming a dam in a marking process of a semiconductor chip. CONSTITUTION: A substrate(100) is arranged on the edge of a chip mount area. A pad forming part arranging a plurality of pads(111) is included. A first semiconductor chip(200) is arranged on the substrate corresponding to the chip mount part. A dam is arranged between the first semiconductor chip and the pad forming part. The dam separates at least one part among a plurality of pads from the first semiconductor chip. The underfill material covers a mobilized plane of the first semiconductor chip. COPYRIGHT KIPO 2010 ...

Lead-Free Solder Ball

SEMICONDUCTOR DEVICE TO MORE EASILY MOUNT SHIELD MEMBER ON BOARD

PURPOSE: A semiconductor device is provided to reduce the size of a semiconductor device by disposing a semiconductor chip, a ground terminal and a connection terminal on a side of a board. CONSTITUTION: A ground terminal(76) is disposed on a board. A connection terminal(75) is disposed on the board. A semiconductor chip(68) is mounted on the board. A shield member(85) is connected to the ground terminal. The semiconductor chip, the ground terminal and the connection terminal are disposed on one side of the board, and the shield member is directly disposed on the other side of the board. The semiconductor chip is covered with a transfer molded resin part(77), but the ground terminal and the connection terminal are exposed from the transfer molded resin part. © KIPO 2006 ...

Semiconductor packages for a mobile device

High quality factor inductor implemented in wafer level packaging (WLP)

Some novel features pertain to a first example provides a semiconductor device that includes a printed circuit board (PCB), asset of solder balls and a die. The PCB includes a first metal layer. The set of solder balls is coupled to the PCB. The die is coupled to the PCB through the set of solder balls. The die includes a second metal layer and a third metal layer. The first metal layer of the PCB, the set of solder balls, the second and third metal layers of the die are configured to operate as an inductor in the semiconductor device. In some implementations, the die further includes a passivation layer. The passivation layer is positioned between the second metal layer and the third metal layer. In some implementations, the second metal layer is positioned between the passivation layer and the set of solder balls.

Semiconductor device

Miniaturization and high-performance of a semiconductor device are promoted, which has a package on package (POP) structure in which a plurality of semiconductor packages is stacked in a multistage manner. A testing conductive pad for determining the quality of a conduction state of a microcomputer chip and a memory chip is arranged outside a conductive pad for external input/output and thereby the route of a wire that couples the microcomputer chip and the memory chip to the testing conductive pad is reduced in length. Further, the wire that couples the microcomputer chip and the memory chip to the testing conductive pad is coupled to a pad in the outer row among conductive pads in two rows to be coupled to the microcomputer chip.

Chip package structure and stacked type chip package structure

A stacked type chip package structure employs a substrate having a pseudo-cavity or a keep-out zone at one side or both sides thereof. Through the pattern arrangement of the wiring layer and the solder mask layer, the thickness of the entire stacked type chip package structure is effectively reduced as lower wire loops and a thinner mold-cap can be achieved by mounting the chip within the depressed keep-out zone. In particular, the double-sided chip package structures are suitable for package on package structures adopted by mobile applications.

A semiconductor package structure and the method for forming the same

The present invention provides a semiconductor package structure and the method for forming the same. Wherein the semiconductor package structure including a first semiconductor package. The first semiconductor package includes a first redistribution layer (RDL) structure having a first surface and a second surface opposite thereto. A first semiconductor die is disposed on and electrically coupled to the first surface of the first RDL structure. A first molding compound is disposed on the first surface of the first RDL structure and surrounds the first semiconductor die. A plurality of solder balls or conductive pillar structures is disposed in the first molding compound and electrically coupled to the first semiconductor die through the first RDL structure.

Package-on-package structures

Embodiments of the present disclosure provide a first package configured to be coupled to a second package, wherein the first package comprises: a ball grid array substrate; a die coupled to the ball grid array substrate; two rows of ball pads arranged around a periphery of the ball grid array substrate, wherein the ball pads of the two rows of ball pads are configured to receive solder balls to couple the first package to the second package, wherein an outer row of the two rows of ball pads comprises at least some ball pads configured as a first type of ball pad, wherein an inner row of the two rows of ball pads comprises at least some ball pads configured as a second type of ball pad, wherein the first type of ball pad is different than the second type of ball pad.

Semiconductor device and method of forming low profile 3d fan-out package

A semiconductor device includes a substrate having an insulating layer and a conductive layer embedded in the insulating layer. The conductive layer is patterned to form conductive pads or conductive pillars. The substrate includes a first encapsulant formed over the conductive layer. A first opening is formed through insulating layer and first encapsulant using a stamping process or laser direct ablation. The substrate is separated into individual units, which are mounted to a carrier. A semiconductor die is disposed in the first opening in the substrate. A second encapsulant is deposited over the semiconductor die and substrate. An interconnect structure is formed over the semiconductor die and substrate. An opening is formed through the second encapsulant and through the insulating layer to expose the conductive layer. A bump is formed in the second opening over the conductive layer outside a footprint of the semiconductor die.

Method of forming semiconductor structure

Structures and methods of forming fan-out packages are provided. The packages described herein may include a cavity substrate, one or more semiconductor devices located in a cavity of the cavity substrate, and one or more redistribution structures. Embodiments include a cavity preformed in a cavity substrate. Various devices, such as integrated circuit dies, packages, or the like, may be placed in the cavity. Redistribution structures may also be formed.

Semiconductor package

Offset integrated circuit package-on-package stacking system and method for fabricating the same

SEMICONDUCTOR DEVICE

An electronic component such as a semiconductor device wherein disconnection of wiring is prevented in a stress concentrating region of a surface layer wiring of a package. In the semiconductor device provided with a support pole (5), a normal wiring is not arranged in a region (7(A)), which is the stress concentrating region of a package substrate (2) in the vicinity of the support ball (5), and in a semiconductor chip edge region (7(B)) facing the support ball (5). A wiring (6(C)) is arranged at a distance from these regions or a wide wiring is arranged in these regions.

ELECTRONICS PACKAGE AND MANUFACTURING METHOD THEREOF

A method for manufacturing an electronics package is provided that comprises forming at least one module block by providing a carrier substrate having a recess, placing at least one electronic component die in said recess, filling said recess with a molding material, and depositing a circuit layer connected with said at least one component die. It further provides an electronics package, comprising a carrier substrate having a recess, at least one electronic component die placed in said recess, a molding material filling said recess, and a circuit layer connected with said at least one component die.

METHODS AND ARRANGEMENTS RELATING TO SEMICONDUCTOR PACKAGES INCLUDING MULTI-MEMORY DIES

In an embodiment, there is provided a packaging arrangement comprising a substrate; a multi-memory die coupled to the substrate, wherein the multi-memory die comprises multiple individual memory dies, and each of the multiple individual memory dies is defined as an individual memory die within a wafer of semiconductor material during production of memory dies, and the multi-memory die is created by singulating the wafer of semiconductor material into memory dies, where at least one of the memory dies is the multi-memory die that includes the multiple individual memory dies that are still physically connected together; and a semiconductor die coupled to the multi-memory die and the substrate, wherein the semiconductor die is configured as a system on a chip, wherein at least one of the multi-memory die and the semiconductor die is attached to the substrate.

STACKED PACKAGE AND METHOD OF FABRICATING THE SAME

Disclosed herein is a stacked package. The stacked package includes two or more of a first BGA package and a second BGA package and a circuit board having a circuit pattern. The first BGA package is mounted on one face of the circuit board, and the second BGA package is mounted on the other face of the circuit board. A signal connection member is provided for transmitting signals of the first BGA package and the second BGA package to each other. The second BGA package is provided with a signal connection pad. One end of the signal connection member is bonded to the signal connection pad and the other end of the signal connection member is bonded to the circuit pattern of the circuit board. A method of fabricating the stacked package is also disclosed.

SUBSTRATE WITH BUILT-IN CHIP AND METHOD FOR MANUFACTURING SUBSTRATE WITH BUILT-IN CHIP

A method for manufacturing a substrate having a built-in chip is provided with a first step of mounting a semiconductor chip on a first substrate whereupon a first wiring is formed, and a second step of bonding a second substrate whereupon a second wiring is formed with the first substrate. In the second step, the semiconductor chip is sealed between the first substrate and the second substrate, the first wiring is electrically connected with the second wiring, and a multilayer wiring connected with the semiconductor chip is formed.

METHOD OF MANUFACTURING PRINTED WIRING BOARD

... [PROBLEMS] To provide a method of manufacturing a printed wiring board capable of surely forming a high solder bump on a small diameter connection pad provided in the opening of a solder resist. [MEANS FOR SOLVING THE PROBLEMS] A solder ball (77) is molten by reflowing to form a high solder bump (78U) from the solder ball (77) installed in the upper surface opening (71). Since a distance between the solder ball (77) installed in the opening (71) and the connection pad (158P) is reduced by adjusting the thickness of a solder resist layer (70), the solder bump (78U) can be surely connected to the connection pad (158P) when the solder ball (77) is molten by reflowing.

MICROELECTRONIC DEVICES, STACKED MICROELECTRONIC DEVICES, AND METHODS FOR MANUFACTURING MICROELECTRONIC DEVICES

Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices are described herein. In one embodiment, a set of stacked microelectronic devices includes (a) a first microelectronic die having a first side and a second side opposite the first side, (b) a first substrate attached to the first side of the first microelectronic die and electrically coupled to the first microelectronic die, (c) a second substrate attached to the second side of the first microelectronic die, (d) a plurality of electrical couplers attached to the second substrate, (e) a third substrate coupled to the electrical couplers, and (f) a second microelectronic die attached to the third substrate. The electrical couplers are positioned such that at least some of the electrical couplers are inboard the first microelectronic die.

MICROELECTRONIC ASSEMBLIES HAVING VERY FINE PITCH STACKING

A method of making a stacked microelectronic assembly includes providing a first microelectronic package 122A having a first substrate 124A and conductive posts 130A extending from a surface 128A of the first substrate 124A, and providing a second microelectronic package 122B having a second substrate 124B and conductive, fusible masses 148B extending from a surface 126B of the second substrate 124B. A microelectronic element 154A is secured over one of the surfaces of the first and second substrates 124A, 124B, the microelectronic element 154A defining a vertical height H1 that extends from the one of the surfaces of the first and second substrate to which the microelectronic element is secured. The tips 131A of the conductive posts 130A of the first substrate are abutted against the apexes of the fusible masses 148B of the second substrate, whereby the vertical height of each conductive post/fusible mass combination is equal to or greater than the vertical height of the microelectronic ...

STABLE GOLD BUMP SOLDER CONNECTIONS

A metallic interconnect structure (200) for connecting a gold bump (205) and a copper pad (212), as used for example in semiconductor flip-chip assembly. A first region (207) of binary AuSn2 intermetallic is adjacent to the gold bump. A region (208) of binary AuSn4 intermetallic is adjacent to the first AuSn2 region. Then, a region (209) of binary gold-tin solid solution is adjacent to the AuSn4 region, and a second region (210) of binary AuSn2 intermetallic is adjacent to the solid solution region. The second AuSn2 region is adjacent to a nickel layer (213) (preferred thickness about 0.08 μm), which covers the copper pad. The nickel layer insures that the gold/tin intermetallic s and solutions remain substantially free of copper and thus avoid ternary compounds, providing stabilized gold bump/solder connections.

SEMICONDUCTOR MULTI-PACKAGE MODULE HAVING WIRE BOND INTERCONNECTION BETWEEN STACKED PACKAGES

A semiconductor multi-package module having stacked lower and upper packages, each package including a die attached to a substrate, in which the upper and lower substrates are interconnected by wire bonding. Also, a method for making a semiconductor multi-package module, by providing a lower molded package including a lower substrate and a die, affixing an upper molded package including an upper substrate onto the upper surface of the lower package, and forming z-interconnects between the upper and lower substrates.

Method of making a semiconductor chip assemby with a metal containment wall and a solder terminal

A method of making a semiconductor chip assembly includes providing a metal base, a routing line, a metal containment wall and a solder layer in which the metal containment wall includes a cavity and the solder terminal contacts the metal containment wall in the cavity, mechanically attaching a semiconductor chip to the routing line, forming a connection joint that electrically connects the routing line and the pad, etching the metal base to reduce contact area between the metal base and the routing line and between the metal base and the metal containment wall, and providing a solder terminal that includes the solder layer.

THIN PLANAR SEMICONDUCTOR DEVICE HAVING ELECTRODES ON BOTH SURFACES AND METHOD OF FABRICATING SAME

A thin, planar semiconductor device having electrodes on both surfaces is disclosed. This semiconductor device is provided with an IC chip and a wiring layer having one side that is electrically connected to surface electrodes of the IC chip. On this surface of the wiring layer, conductive posts are provided on wiring of the wiring layer, and an insulating resin covers all portions not occupied by the IC chip and conductive posts. The end surfaces of the conductive posts are exposed from the insulating resin and are used as first planar electrodes. In addition, a resist layer is formed on the opposite surface of the wiring layer. Exposed portions are formed in the resist layer to expose desired wiring portions of the wiring layer. These exposed portions are used as second planar electrodes. Stacking semiconductor devices of this construction enables an improvement in the integration of semiconductor integrated circuits.

Packaged electronic devices having die attach regions with selective thin dielectric layer

A packaged electronic device including a package substrate having a top substrate surface including a die attach region including at least one land pad thereon and a first dielectric layer positioned lateral to the land pad and a non-die attach region. The non-die attach region includes a second dielectric layer, wherein a thickness of the second dielectric layer is>a thickness of the first dielectric layer by at least 5 m. An IC die has a top semiconductor surface including active circuitry and at least one bonding conductor formed on the top semiconductor surface, and a bottom surface, wherein the bonding conductor of the IC die is joined to the land pad of the package substrate. An underfill layer is between the IC die and the die attach region.

Package alignment structure and method of forming same

An embodiment is a semiconductor device comprising a first bond pad on a first substrate, the first bond pad having a first center line through a center of the first bond pad and orthogonal to a top surface of the first substrate, and a first conductive connector on a second substrate, the first conductive connector having a second center line through a center of the first conductive connector and orthogonal to a top surface of the second substrate, the second substrate over the first substrate with the top surface of the first substrate facing the top surface of the second substrate. The semiconductor device further comprises a first alignment component adjacent the first bond pad on the first substrate, the first alignment component configured to align the first center line with the second center line.

Semiconductor Bonding Structures and Methods

A system and method for applying an underfill is provided. An embodiment comprises applying an underfill to a substrate and patterning the underfill. Once patterned other semiconductor devices, such as semiconductor dies or semiconductor packages may then be attached to the substrate through the underfill, with electrical connections from the other semiconductor devices extending into the pattern of the underfill.

Electronic device and semiconductor device

There is a need to alleviate or reduce crosstalk between bonding wires or wires in a device substrate. One selection configuration divides a multiplexed terminal group into three groups according to functions differently from another selection configuration that divides the multiplexed terminal group into two groups. A first multi-pin semiconductor device is configured such that the groups are successively arranged along one edge of the chip. The first semiconductor device connects with a second semiconductor device via a multiplexed terminal group. The multiplexed terminal group includes first through third interface terminal groups that differ from each other in signal input/output configurations.

Packaging substrate, method for manufacturing same, and chip packaging structure having same

A packaging substrate includes a circuit board, a number of first conductive posts, and a number of second conductive posts. The circuit board includes a first base and a first conductive pattern layer formed on a first surface of the first base. The first conductive posts extend from and are electrically connected to the first conductive pattern layer. The second conductive posts extend from and are electrically connected to the first conductive pattern layer. The height of each of the second conductive posts are larger than that of each of the first conductive posts.

Semiconductor device, electronic device, electronic apparatus, method of manufacturing semiconductor device, and method of manufacturing electronic device

A method and device are provided to realize a structure in which different kinds of chips are three-dimensionally mounted while suppressing the deterioration of the connection reliability. A semiconductor package PK12 in which a semiconductor chip 13 is sealed with a sealing resin 17 is stacked on a semicoductor package PK11 in which a semiconductor chip 3 is mounted on a carrier substrate 1 by anisotropic conductive film (ACF) bonding. The range in which the semiconductor chip 13 is sealed with a sealing resin 17 is set so as to cover the semiconductor chip 13 and to be attached to the region for arranging the protruding electrodes 16 on the side of the surface on which the semiconductor chip 13 is mounted.

Three dimensional package type stacking for thinner package application

A stacked semiconductor device, and method of making, having a plurality of semiconductor chips of desired sizes stacked as one package, a first semiconductor chip is mounted on a first substrate. Solder balls are connected to contacts on the upper surface of the first substrate and a non-conductive layer is provided overlaying the first substrate and the first semiconductor chip. The solder balls are secured in cavities formed in the layer and extend beyond the top surface of the layer. A second semiconductor chip mounted on a second substrate is stacked on the layer with contacts on the lower surface of the second substrate in electrical contact with the extended portion of the solder balls, thereby connecting the second semiconductor chip with the first semiconductor chip.

Microelectronic assemblies incorporating inductors

Inductors are provided in chip assemblies such as in packaged semiconductor chips. The inductors may be incorporated in a chip carrier which forms part of the package, and may include, for example, spiral or serpentine inductors formed from traces on the chip carrier. The chip carrier may include a flap bearing the inductive element, and this flap may be bent to tilt the inductive element out of the plane of the chip carrier to reduce electromagnetic interaction between the inductive element and surrounding electrical components. Other inductors include solenoids formed in part by leads on the chip carrier as, for example, by displacing leads out of the plane of the chip carrier to form loops in vertically-extensive planes transverse to the plane of the chip carrier. Additional features provide trimming of the inductor to a desired inductance value during by breaking or connecting leads during assembly.

Components, methods and assemblies for multi-chip packages

An ultra thin system-in-a-package (SIP) with independent test and repair capability comprises an interposer having arranged on a top surface and a bottom surface thereof a number of packaged semiconductor chips mounted via solder bumps in accordance with a Land Grid Array (LGA) format and wherein no underfill is used on the SIP.

Modular integrated circuit chip carrier

An apparatus and method is disclosed that allows for the arranging in a three dimensional array semiconductor chips on a circuit board. A unique chip carrier is disclosed on which any IC chip can be positioned on above the other on a circuit board. Additionally, the carrier allows for the testing of IC chips on the carrier and underneath it without having to remove the carrier and chips from the system even if they are of the BGA or CSP type. The carrier includes exposed test points to allow an on site test.

Semiconductor package and method of fabricating same

A semiconductor package comprises a semiconductor chip provided with a plurality of electric terminals, a plurality of electrically conductive members electrically connected with the electric terminals, respectively, a connection terminal spherical in shape, made of solder, electrically connected with each of the electrically conductive members, corresponding thereto, and a sealing member for sealing a semiconductor chip and the electrically conductive members, and for covering the connection terminals so as to allow a part thereof to be exposed. The electrically conductive members are provided with a bonding promoter for promoting bonding thereof by solder with the connection terminal spherical in shape, and are connected with the respective connection terminals spherical in shape, corresponding thereto, at the respective bonding promoters.

Method of bonding a flexible polymer tape to a substrate to reduce stresses on the electrical connections

The present invention is directed to a semiconductor package and its method of manufacture. Conductors mounted on a flexible polymer tape are used to connect a semiconductor chip to a substrate. The flexible polymer tape can be folded back under the chip to reduce the size necessary for mounting the assembly to almost that of the chip itself. The polymer tape also provides flexibility to reduce stresses on the electrically connections caused by thermal expansion and compression. Additionally, the present invention allows for the stacking of semiconductor chips on top of one another, reducing signal propagation delays between them.

Semiconductor device

Described herein is a stacked package according to the present invention, wherein a plurality of tape carriers which seal semiconductor chips, are multilayered in upward and downward directions. In the stacked package, one ends of leads formed over the whole surfaces of each tape carrier are electrically connected to their corresponding connecting terminals of the semiconductor chip. Other ends of the leads are electrically connected to their corresponding through holes defined in the tape carrier. Connecting terminals common to the plurality of semiconductor chips are formed at the same places of the plurality of tape carriers and withdrawn to the same external connecting terminals through a plurality of mutually-penetrated through holes.

Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect

A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame. The interposer is mounted over the carrier and first die with the conductive pillars disposed around the die. A cavity can be formed in the interposer frame to contain a portion of the first die. An encapsulant is deposited through the opening in the interposer frame over the carrier and first die. Alternatively, the encapsulant is deposited over the carrier and first die and the interposer frame is pressed against the encapsulant. Excess encapsulant exits through the opening in the interposer frame. The carrier is removed. An interconnect structure is formed over the encapsulant and first die. A second semiconductor die can be mounted over the first die or over the interposer frame.

Electronic component packaging structure and method for producing the same

An electronic component packaging structure, includes: circuit boards each having a wiring at least on a surface thereof; and an electronic component package secured between the circuit boards. The electronic component package includes at least one electronic component embedded within an electrical insulating encapsulation resin molded member made of an inorganic filler and a resin, the at least one electronic component being selected from an active component and a passive component, protruding electrodes are arranged on both faces of the electrical insulating encapsulation resin molded member, and the electronic component is connected electrically with at least a part of the protruding electrodes. This configuration allows circuit boards to be connected with each other and a high-density and high-performance structure.

Ball grid array chip packages having improved testing and stacking characteristics

A stackable ball grid array (BGA) or fine ball grid array (FBGA) semiconductor package particularly suitable for board-on-chip or chip-on-board applications in which a low profile BGA or FBGA semiconductor package is needed. The stackable ball grid array (BGA) or fine ball grid array (FBGA) provides a semiconductor package that is capable of being burned in and tested in a more efficient and cost effective manner than prior known BGA or FBGA semiconductor packages. A high density, low profile memory module incorporating a plurality of the disclosed BGA or FBGA semiconductor packages in a stacked arrangement is further disclosed.

Wiring board with built-in electronic component and method for manufacturing the same

A wiring board with a built-in electronic component includes a substrate having cavity, an insulating layer formed on the substrate such that the insulating layer is covering the cavity, a conductor layer formed on the insulating layer, and an electronic component accommodated in the cavity and including a rectangular cuboid body and terminal electrodes such that each electrode has a metal film form formed on outer surface of the body, and via conductors formed in the insulating layer such that the via conductors are connecting the conductor layer and electrodes. The electrodes are arrayed in a matrix having rows and columns such that adjacent electrodes in row and column directions have the opposite polarities, and the conductor layer includes a line pattern shunting first group of the electrodes in one polarity and a solid pattern shunting second group of the electrodes in the other polarity.

Semiconductor package devices including interposer openings for heat transfer member

A semiconductor package device includes a lower package, an interposer disposed on the lower package and including a ground layer and at least one opening, and an upper package on the interposer. The lower package includes a first package substrate, a first semiconductor chip on the first package substrate, and a first molding compound layer on the first package substrate. The upper package includes a second package substrate and at least one upper semiconductor chip on the second package substrate. A heat transfer member includes a first portion disposed between the interposer and the upper package, a second portion disposed in the at least one opening of the interposer, and a third portion disposed between the interposer and the lower package.

Method for manufacturing semiconductor package having improved bump structures

A method for manufacturing a semiconductor package includes the steps of forming first circuit patterns on an upper surface of a carrier substrate. Bumps are formed in recesses defined on the upper surface of the carrier substrate. An insulation layer is formed on the upper surface of the carrier substrate to cover the first circuit patterns. Second circuit patterns are formed on an upper surface of the insulation layer so as to be electrically connected with the first circuit patterns. The carrier substrate is then separated from the insulation layer.

Package on package arrangement and method

A method of forming a package on package, semiconductor package arrangement is described. In one aspect, solder bumps on a lower surface of a first grid array package substrate are fused to corresponding unencapsulated solder bumps on an upper surface of a second grid array package substrate. The fused solder bumps form solder joints that electrically connect the first and second packages. The height of the resulting solder joints is greater than a height of a die that is flip chip mounted to the second substrate such that the first substrate does not contact any portion of the second package and an air gap is formed that separates the second die from the first package. Corresponding PoP packages structures are also described.

Multiple Die Packaging Interposer Structure and Method

System and method for providing a multiple die interposer structure. An embodiment comprises a plurality of interposer studs in a molded interposer, with a redirection layer on each side of the interposer. Additionally, the interposer studs may be initially attached to a conductive mounting plate by soldering or wirebond welding prior to molding the interposer, with the mounting plate etched to form one of the redirection layers. Integrated circuit dies may be attached to the redirection layers on each side of the interposer, and interlevel connection structures used to mount and electrically connect a top package having a third integrated circuit to the interposer assembly.

Semiconductor package and fabrication method thereof

A semiconductor package is provided, which includes: a first semiconductor device having a first top surface and a first bottom surface opposite to the first top surface; a plurality of conductive balls formed on the first top surface of the first semiconductor device; a second semiconductor device having a second top surface and a second bottom surface opposite to the second top surface; and a plurality of conductive posts formed on the second bottom surface of the second semiconductor device and correspondingly bonded to the conductive balls for electrically connecting the first semiconductor device and the second semiconductor device, wherein the conductive posts have a height less than 300 um. Therefore, the present invention can easily control the height of the semiconductor package and is applicable to semiconductor packages having fine-pitch conductive balls.

Embedded die flip-chip package assembly

Embodiments of the present disclosure describe integrated circuit (IC) package assemblies and methods of fabricating IC package assemblies. These embodiments include dies embedded in embedding substrates to provide larger pitch interconnects to facilitate coupling to substrates or circuit boards through flip chip techniques. The embedding substrates may contain conductive pathways for coupling die contacts to larger pitch contacts located on the embedding substrate. By embedding the dies in the embedding substrates, dies having smaller pitch contacts can be used in package assemblies with larger pitch components without the need for silicon interposers and without having to utilize more stringent pick and place operations. Other embodiments may be described and/or claimed.

Semiconductor Package Having Semiconductor Chip Within Central Aperture Of Substrate

Semiconductor packages having a thin structure capable of easily discharging heat from a semiconductor chip included therein, and methods for fabricating such semiconductor packages, are disclosed. An embodiment of a semiconductor package includes a semiconductor chip having a first major surface and a second major surface, the semiconductor chip being provided at the second major surface with a plurality of input/output pads; a circuit board including a resin substrate having a first major surface and a second major surface, a first circuit pattern formed at the first major surface and provided with a plurality of ball lands, a second circuit pattern formed at the second major surface and provided with a plurality of bond fingers connected with the ball lands by conductive via holes through the resin substrate, cover coats respectively coating the first and second circuit patterns while allowing the bond fingers and the ball lands to be exposed therethrough, and a central through hole ...

METHOD AND MOLD FOR MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, AND METHOD FOR MOUNTING THE DEVICE

A method includes a resin sealing step of placing, in a cavity 28 of a mold 20, a substrate 16 to which semiconductor elements 11 on which bumps 12 are arranged, a resin sealing step of supplying resin 35 to positions of the bumps 12 so that a resin layer 13 sealing the bumps 12 is formed, a protruding electrode exposing step of exposing at least ends of the bumps 12 sealed by the resin layer 13 so that ends of the bumps 12 are exposed from the resin layer 13, and a separating step of cutting the substrate 16 together with the resin layer 13 so that the semiconductor elements 11 are separated from each other.

Connection system of semiconductor packages using a printed circuit board

A connection system of semiconductor packages includes: a printed circuit board; a first semiconductor package disposed on a first surface of the printed circuit board and connected to the printed circuit board through first electrical connection structures; a second semiconductor package disposed on a second surface of the printed circuit board and connected to the printed circuit board through second electrical connection structures; and a third semiconductor package disposed on the first semiconductor package and connected to the first semiconductor package through third electrical connection structures. The first semiconductor package includes an application processor (AP), the second semiconductor package includes a memory, and the third semiconductor package includes a power management integrated circuit (PMIC).

Stacked semiconductor structure and fabrication method thereof

A stacked semiconductor structure and fabrication method thereof are provided. The method includes mounting and connecting electrically a semiconductor chip to a first substrate, mounting on the first substrate a plurality of supporting members corresponding in position to a periphery of the semiconductor chip, mounting a second substrate having a first surface partially covered with a tape and a second surface opposite to the first surface on the supporting members via the second surface, connecting electrically the first and second substrates by bonding wires, forming on the first substrate an encapsulant for encapsulating the semiconductor chip, the supporting members, the second substrate, the bonding wires, and the tape with an exposed top surface, and removing the tape to expose the first surface of the second substrate and allow an electronic component to be mounted thereon. The present invention prevents reflow-induced contamination, spares a special mold, and eliminates flash.

Method for manufacturing a substrate with cavity

An aspect of the present invention features a method for manufacturing a substrate having a cavity. The method can comprises: (a) forming an upper layer circuit on an upper seed layer; (b) laminating a dry film on a portion of the-upper seed layer where a cavity is to be formed; (c) fabricating an upper outer layer by forming an insulation layer on top of the upper seed layer and on top and sides of the upper layer circuit; (d) stacking the upper outer layer on one side of a core layer where an internal circuit is formed; (e) removing the upper seed layer; and (f) forming the cavity by removing the dry film. The method for manufacturing a substrate with a cavity according to the present invention can reduce the total thickness of the substrate while the thickness of an insulation layer remains the same, by forming the insulation layer on sides of an external circuit.

ELECTRONIC ASSEMBLY AND METHOD OF FORMING SAME

Various embodiments of an electronic assembly and a method of forming such assembly are disclosed. The electronic assembly includes a first integrated circuit package electrically connected to a second integrated circuit package. The first integrated circuit package includes a dielectric layer, a patterned conductive layer disposed within the dielectric layer, a device disposed on the first major surface of the dielectric layer and electrically connected to the patterned conductive layer, and an encapsulant layer disposed on the device and at least a portion of the first major surface of the dielectric layer. A conductive pillar of the second integrated circuit package is disposed within a trench of the first integrated circuit package such that the conductive pillar is electrically connected to a conductor disposed within the trench of the first integrated circuit package. The conductive pillar is electrically connected to a patterned conductive layer of the second integrated circuit package ...

Low profile, chip-scale package and method of fabrication

Disclosed is a semiconductor device that includes an electrically insulating, sheet-like substrate ( 301 ) with first and second surfaces ( 301 a , 301 b), at least one opening ( 310 ), and a certain thickness ( 302 ). On the first surface are a plurality of electrically conductive routing strips and a plurality of contact pads ( 330 ); at least one of the contact pads is electrically connected with at least one of the routing strips, and may have a solder body ( 901 ) attached. A semiconductor chip ( 102 ) is positioned in the opening while leaving a gap ( 311 ) to the substrate; the chip has an active surface ( 102 a) including at least one bond pad ( 103 ), and a passive surface ( 102 b) substantially coplanar with the second substrate surface ( 301 b). Substrate thickness and chip thickness may be substantially equal. Bonding elements ( 501 ) bridge the gap to connect electrically bond pad and routing strip. Encapsulation material ( 701 ) protects the active chip surface and the bonding ...

SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD THEREFOR

To provide a semiconductor device with improved reliability. The semiconductor device includes a wiring board, a microcomputer chip flip-chip bonded over the wiring board via gold bumps, a first memory chip laminated over the microcomputer chip, wires for coupling the first memory chip to the wiring board, an underfill material with which a flip-chip coupling portion of the microcomputer chip is filled, and a sealing member for sealing the microcomputer chip and the first memory chip with resin. Further, the corner of a second opening portion of a solder resist film of the wiring board corresponding to the corner of the chip on the air vent side in charging the underfill material is made close to the microcomputer chip, which can improve the wettability and spread of the underfill material at the second opening portion, thus reducing the exposure of leads to the second opening portion, thereby improving the reliability of the semiconductor device.

MULTI-DIE MEMORY DEVICE

A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and includes first and second memory arrays. The first memory array couples to the first memory interface circuit. The second memory array couples to the second interface circuit. A second memory die is stacked with the logic die and the first memory die. The second memory die includes third and fourth memory arrays. The third memory array couples to the first memory interface circuit. The fourth memory array couples to the second memory interface circuit. Accesses to the first and third memory arrays are carried out independently from accesses to the second and fourth memory arrays.

Semiconductor device

Described herein is a stacked package according to the present invention, wherein a plurality of tape carriers which seal semiconductor chips, are multilayered in upward and downward directions. In the stacked package, one ends of leads formed over the whole surfaces of each tape carrier are electrically connected to their corresponding connecting terminals of the semiconductor chip. Other ends of the leads are electrically connected to their corresponding through holes defined in the tape carrier. Connecting terminals common to the plurality of semiconductor chips are formed at the same places of the plurality of tape carriers and withdrawn to the same external connecting terminals through a plurality of mutually-penetrated through holes.

Electronic component built-in substrate and method of manufacturing the same

In an electronic component built-in substrate of the present invention, an electronic component is mounted on a mounted body having a first wiring layer, the electronic component is embedded in an insulating layer, a conductive ball is arranged to pass through the insulating layer and connected electrically to the first wiring layer, a second wiring layer connected electrically to the conductive ball is formed on the insulating layer, and the first wiring layer and the second wiring layer are interlayer-connected via the conductive ball.

SEMICONDUCTOR PACKAGES

A semiconductor package comprises a lower package comprising a lower substrate, a lower semiconductor chip on the lower substrate, a lower graphene layer on the lower semiconductor chip, and a lower molding layer between the lower substrate and the lower graphene layer. An upper package is on the lower substrate, the upper package spaced apart from the lower package, the upper package comprising an upper substrate, an upper semiconductor chip, and an upper molding layer. Lower conductive bumps are positioned between the lower substrate and the upper substrate, the lower bumps comprising a ground bump and a signal transmitting bump.

Integrated circuit packaging system with encapsulation and underfill and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing a package carrier having a dispense port; attaching an integrated circuit to the package carrier and over the dispense port; placing a mold chase over the integrated circuit and on the package carrier, the mold chase having a hole; and forming an encapsulation through the dispense port or the hole, the encapsulation surrounding the integrated circuit including completely filled in a space between the integrated circuit and the package carrier, and in a portion of the hole, the encapsulation having an elevated portion or a removal surface resulting from the elevated portion detached.

Porous alumina templates for electronic packages

Interposers and methods of making the same are disclosed herein. In one embodiment, an interposer includes a region having first and second oppositely facing surfaces and a plurality of pores, each pore extending in a first direction from the first surface towards the second surface, wherein alumina extends along a wall of each pore; a plurality of electrically conductive connection elements extending in the first direction, consisting essentially of aluminum and being electrically isolated from one another by at least the alumina; a first conductive path provided at the first surface for connection with a first component external to the interposer; and a second conductive path provided at the second surface for connection with a second component external to the interposer, wherein the first and second conductive paths are electrically connected through at least some of the connection elements.

Stacked board-on-chip package having mirroring structure and dual inline memory module on which the stacked board-on-chip packages are mounted

Embodiments of the invention include a stacked board-on-chip (BOC) package having a mirroring structure and a dual inline memory module (DIMM) on which the stacked BOC package is mounted. A bottom surface of a first semiconductor chip faces a bottom surface of a second semiconductor chip. An interposer electrically connects first and second packages, respectively comprising the first and second semiconductor chips, to each other. The DIMM is obtained by electrically connecting BOC packages to each other on upper and lower substrates of a printed circuit board. Since a height of the stacked BOC packages is greater than a height of a conventional stacked BOC package, the DIMM has a minimum stub length and an optimal topology. Hence, the DIMM can have a signal with excellent fidelity by reducing a load upon a signal line, and installation or wiring of components within the DIMM 300 requires less effort.

Integrated circuit package system with stackable devices and a method of manufacture thereof

An integrated circuit package system includes: providing a package substrate; mounting an interposer chip containing active circuitry over the package substrate; attaching a conductive bump stack having a base bump end and a stud bump end, the base bump end on the interposer chip; connecting a stack connector to the interposer chip and the package substrate; and applying a package encapsulant over the interposer chip, the stack connector, and the conductive bump stack with the stud bump end of the conductive bump stack substantially exposed.

Stacked semiconductor packages

Semiconductor package includes a first semiconductor package including a first printed circuit board, and a first semiconductor device mounted on the first printed circuit board, and a second semiconductor package stacked on the first semiconductor package, and including a second printed circuit board and a second semiconductor device mounted on the second printed circuit board. The semiconductor package includes at least one first through electrode electrically connecting the second semiconductor package to the first printed circuit board through the first semiconductor device.

Stacked package, method of fabricating stacked package, and method of mounting stacked package fabricated by the method

Provided are a stacked package, method of fabricating a stacked package, and method of mounting a stacked package. A method includes providing an upper semiconductor package including an upper package substrate, upper semiconductor chips formed on a top surface of the upper package substrate, and first solders formed on a bottom surface of the upper package substrate and having a first melting temperature, providing a lower semiconductor package including a lower package substrate, lower semiconductor chips formed on a top surface of the lower package substrate, and solder paste nodes formed on the top surface of the lower package substrate and having a second melting temperature lower than the first melting temperature, and forming inter-package bonding units by attaching respective first solders and solder paste nodes to each other by performing annealing at a temperature higher than the second melting temperature and lower than the first melting temperature.

METHOD AND MOLD FOR MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, AND METHOD FOR MOUNTING THE DEVICE

A method for manufacturing semiconductor devices includes a resin sealing step of putting a substrate (16) on which bumps (12) and a plurality of semiconductor chips (11) are arranged in the cavity (28) of a mold (20) and supplying a resin (35) to the region where the bumps (12) are provided so as to coat the bumps (12) and form a resin layer (13), a protruded electrode exposing step of exposing at least the front end sections of the bumps (12) coated with the resin layer (13) from the layer (13), and a separating step of separating the semiconductor chips (11) into individual chips (11) by cutting the substrate (16) together with the layer (13).

Method of manufacture of integrated circuit packaging system with stacked integrated circuit

A method of manufacture of an integrated circuit packaging system includes: forming a base lead having an outer protrusion and an inner protrusion with a recess in between; forming a stack lead having an elongated portion; mounting a base integrated circuit over the inner protrusion or under the elongated portion; mounting the stack lead over the base lead and the base integrated circuit; connecting a stack integrated circuit and the stack lead with the stack integrated circuit over the base integrated circuit; and encapsulating at least a portion of both the base integrated circuit and the stack integrated circuit with the base lead and the stack lead exposed.

Integrated circuit packaging system with stack interconnect and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: forming a connection carrier having base device pads and base interconnect pads on a carrier top side of the connection carrier; connecting a base integrated circuit to the base device pads and mounted over the carrier top side; mounting base vertical interconnects directly on the base interconnect pads; attaching a base package substrate to the base integrated circuit and directly on the base vertical interconnects; forming a base encapsulation on the base package substrate, the base device pads, and the base interconnect pads; and removing a portion of the connection carrier with the base device pads and the base interconnect pads partially exposed opposite the base package substrate.

Methods of fabricating package stack structure and method of mounting package stack structure on system board

A package stack structure includes a lower semiconductor chip on a lower package substrate having a plurality of lower via plug lands, a lower package having a lower molding compound surrounding a portion of a top surface of the lower package substrate and side surfaces of the lower semiconductor chip, an upper semiconductor chip on an upper package substrate having a plurality of upper via plug lands, an upper package having an upper molding compound covering the upper semiconductor chip, via plugs vertically penetrating the lower molding compound, the via plugs connecting the lower and upper via plug lands, respectively, and a fastening element and an air space between a top surface of the lower molding compound and a bottom surface of the upper package substrate.

Semiconductor device and test system for the semiconductor device

A semiconductor package including a stress mitigation unit that mitigates stress to the semiconductor chip. The semiconductor package includes a substrate, a semiconductor chip on the substrate, an encapsulation member formed on the substrate and covering the first semiconductor chip, and the stress mitigation unit mitigating stress from a circumference of the first semiconductor chip to the first semiconductor chip. The stress mitigation unit includes at least one groove formed in the encapsulation member.

Integrated circuit packaging system with interposer interconnections and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit; mounting a routing structure having a functional side above the integrated circuit; mounting a vertical interconnect to the functional side of the routing structure and the vertical interconnect extending vertically away from the routing structure; forming an encapsulation covering the integrated circuit, the routing structure, and sides of the vertical interconnect above the routing structure, and leaves a surface of the routing structure exposed from the encapsulation, and a portion of the vertical interconnect exposed from the encapsulation above the surface of the routing structure; mounting a first-external-package-component to the routing structure; and forming a first-external-package-encapsulation covering the first-external-package-component.

Package with embedded chip and method of fabricating the same

A package embedded with a chip and a method of fabricating the package of embedded chip. The package of embedded chip includes a dielectric layer having a first surface and a second surface opposing the first surface; a plurality of conductive pillars formed in the dielectric layer and exposed from the second surface of the dielectric layer; a chip embedded in the dielectric layer; a circuit layer formed on the first surface of the dielectric layer; a plurality of conductive blind vias formed in the dielectric layer, allowing the circuit layer to be electrically connected via the conductive blind vias to the chip and each of the conductive pillars; and a first solder mask layer formed on the first surface of the dielectric layer and the circuit layer, thereby using conductive pillars to externally connect with other electronic devices as required to form a stacked structure. Therefore, the manufacturing process can be effectively simplified.

Integrated circuit packaging system with connection structure and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing a substrate; attaching a connection post to the substrate, the connection post having a post top and a post side; mounting an integrated circuit die on the substrate, the integrated circuit die having a top die surface; and forming a package body on the substrate, the connection post, and the integrated circuit die.

Dram device with built-in self-test circuitry

A dynamic random access memory (DRAM) device includes a first and second integrated circuit (IC) die. The first integrated circuit die has test circuitry to generate redundancy information. The second integrated circuit die is coupled to the first integrated circuit die in a packaged configuration including primary storage cells and redundant storage cells. The second integrated circuit die further includes redundancy circuitry responsive to the redundancy information to substitute one or more of the primary storage cells with one or more redundant storage cells.

Packaged semiconductor device for high performance memory and logic

A packaged semiconductor device is disclosed. The device comprises a substrate having multiple layers between first and second oppositely disposed faces, and a cavity with an opening at the first face to nest at least one integrated circuit memory device. Logic circuitry is disposed on the second face and includes contacts for electrically coupling to the stacked integrated circuit memory devices. The logic circuitry is coupled to electrical contacts formed on the first face through first electrical paths formed in the multiple layers of the substrate, the first electrical paths including conductive traces and vias.

Package 3D Interconnection and Method of Making Same

A method of manufacturing an integrated circuit (IC) package is provided. The method includes stacking an interposer substrate and a device structure, the interposer substrate having a first plurality of contact members formed on a first surface of the interposer substrate and the device structure having a second plurality of contact members that are exposed at a surface of the device structure, and laminating the interposer substrate and the device structure such that the first plurality of contact members are physically and electrically coupled to the second plurality of contact members. The interposer substrate is configured such that a circuit member mounted to a second surface of the interposer substrate is electrically coupled to the second plurality of contact members.

Electronic device and method for producing a device

An electronic device or devices and method for producing a device is disclosed. One embodiment provides an integrated component, a first package body and a contact device. The contact device penetrates the package body.

Unpackaged and packaged IC stacked in a system-in-package module

There is provided a system and method for unpackaged and packaged IC stacked in a system-in-package module. There is provided a system-in-package module comprising a substrate including a first contact pad and a second contact pad disposed thereon, a packaged device disposed on the substrate, and an unpackaged device stacked atop the packaged device, wherein a first electrode of the packaged device is electrically and mechanically coupled to the first contact pad, and wherein a second electrode of the unpackaged device is electrically coupled to the second contact pad. The structure of the disclosed system-in-package module provides several advantages over conventional designs including increased yields, facilitated die substitution, enhanced thermal and grounding performance through direct connect vias, stacking of wider devices without a spacer, and a simplified single package structure for reduced fabrication time and cost.

Exposed interconnect for a package on package system

An integrated circuit packaging system includes: providing a substrate; mounting an integrated circuit above the substrate; connecting an interposer to the integrated circuit with a wire-in-film adhesive; connecting an exposed interconnect having an upper surface to the substrate; and encapsulating the integrated circuit with an encapsulation.

Semiconductor package

A semiconductor package includes a plurality of connection pads, which are electrically connected to connection terminals of a mounted component that is mounted on the semiconductor package, and recognition marks. The recognition marks are formed respectively within the area of each of at least two of the connection pads. Each recognition mark has an area that is smaller than the area of the connection mark in which it is formed.

Flip chip assembly process for ultra thin substrate and package on package assembly

In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including receiving a coreless substrate strip, attaching solder balls to a backside of the coreless substrate strip, and forming a backside stiffening mold amongst the solder balls. Other embodiments are also disclosed and claimed.

Integrated circuit packaging system with interconnects and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing a substrate; attaching an integrated circuit to the substrate; attaching a vertical interconnect over the substrate; forming an encapsulation on the substrate and covering the vertical interconnect; and forming a rounded cavity, having a curved side, in the encapsulation with the vertical interconnect exposed in the rounded cavity.

Low-noise flip-chip packages and flip chips thereof

A low-noise flip-chip package, comprising: a carrier substrate having first and second opposing main faces; and a flip-chip substrate connected in a face-down manner onto the first main face of the carrier substrate via a connection array, wherein: the flip-chip substrate comprises at least first and second circuitry portions spaced apart from one another; the flip-chip substrate comprises a substrate-contact boundary located between the first and second circuitry portions; and each of the first circuitry portion, the second circuitry portion and the substrate-contact boundary has its own separate signal-reference connection extending via a respective connection of the connection array through the carrier substrate to a respective electrical contact at the second main face of the carrier substrate for connection to a common signal-reference element in an external circuit.

High io substrates and interposers without vias

An interconnection component includes a substrate having first and second opposed major surfaces defining a thickness of less than 1000 microns and a first slot extending between the first and second surfaces, the first slot being enclosed by the substrate at the first and second surfaces. The first slot defines an edge surface between the first surface and the second surface. First conductive traces extend along the first surface and are electrically connected with first contact pads that overlie the first surface. Second conductive traces extend along the second surface and electrically connected with second contact pads that overlie the second surface. Interconnect traces extend along the edge surface of the first slot. Each interconnect trace directly connects at least one first trace with at least one second trace.

Stacked semiconductor device

Provided is a stacked semiconductor device ( 50 ) in which a semiconductor package ( 5 ) is stacked via connection terminals ( 8 ) on a semiconductor package ( 1 ), including a heat dissipating member ( 10 ) which is disposed between the semiconductor packages ( 1, 5 ), is brought into thermal contact with both of the packages ( 1, 5 ), and hangs over whole outer peripheral portions of the package ( 5 ). Such a structure causes heat generated from the package ( 5 ) to be released by heat dissipation into air above the package ( 5 ), heat dissipation into the air below the semiconductor package ( 5 ), heat transfer via the heat dissipating member ( 10 ) and a semiconductor element ( 3 ) to a first wiring substrate ( 2 ), heat transfer via the connection terminals ( 8 ) to the first wiring substrate ( 2 ), and heat dissipation via the heat dissipating member ( 10 ) into the air, thereby enhancing a temperature reduction effect of the semiconductor element.

Forming Packages Having Polymer-Based Substrates

A method includes applying a polymer-comprising material over a carrier, and forming a via over the carrier. The via is located inside the polymer-comprising material, and substantially penetrates through the polymer-comprising material. A first redistribution line is formed on a first side of the polymer-comprising material. A second redistribution line is formed on a second side of the polymer-comprising material opposite to the first side. The first redistribution line is electrically coupled to the second redistribution line through the via.

Method Of Manufacturing Package-On-Package (Pop)

A method of manufacturing package-on-packages (POPs) includes: forming a plurality of internal connection members that are separated from each other on a first circuit substrate; forming a first package by attaching a plurality of first chips between the internal connection members on the first circuit substrate; forming a second package by attaching a plurality of second chips that are separated from each other on a second circuit substrate; electrically connecting the first circuit substrate and the second circuit substrate by stacking the internal connection members onto the second circuit substrate; forming an encapsulant to encapsulate the first package and the second package; and forming the POPs in which the first chips and the second chips are respectively formed by cutting the first circuit substrate, the second circuit substrate, and the encapsulant.

Power management applications of interconnect substrates

Various applications of interconnect substrates in power management systems are described.

Silicon based microchannel cooling and electrical package

A chip package includes: a substrate; a plurality of conductive connections in contact with the silicon carrier; a silicon carrier in a prefabricated shape disposed above the substrate, the silicon carrier including: a plurality of through silicon vias for providing interconnections through the silicon carrier to the chip stack; liquid microchannels for cooling; a liquid coolant flowing through the microchannels; and an interconnect to one or more chip stacks. The chip package further includes a cooling lid disposed above the chip stack providing additional cooling.

Semiconductor device and fabrication method therefore

Various embodiments of the present invention include a semiconductor device and a fabrication method therefore, the semiconductor device including a first semiconductor chip disposed on a substrate, a first sealing resin sealing the first semiconductor chip, a built-in semiconductor device disposed on the first sealing resin, and a second sealing resin sealing the first sealing resin and the built-in semiconductor device and covering a side surface of the substrate. According to an aspect of the present invention, it is possible to provide a high-quality semiconductor device and a fabrication method therefore, in which downsizing and cost reduction can be realized.

Semiconductor Device and Method of Forming Interposer Frame Over Semiconductor Die to Provide Vertical Interconnect

A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame. The interposer is mounted over the carrier and first die with the conductive pillars disposed around the die. A cavity can be formed in the interposer frame to contain a portion of the first die. An encapsulant is deposited through the opening in the interposer frame over the carrier and first die. Alternatively, the encapsulant is deposited over the carrier and first die and the interposer frame is pressed against the encapsulant. Excess encapsulant exits through the opening in the interposer frame. The carrier is removed. An interconnect structure is formed over the encapsulant and first die. A second semiconductor die can be mounted over the first die or over the interposer frame.

System in package process flow

A method comprises connecting a substrate having a plurality of integrated circuit (IC) dies to a package substrate, so that the package substrate extends beyond at least two edges of the substrate, leaving first and second edge portions of the package substrate having exposed contacts. The first and second edge portions meet at a first corner of the package substrate. At least a first upper die package is placed over the substrate, so that first and second edge portions of the first upper die package extend beyond the at least two edges of the substrate. Pads on the first and second edge portions of the first upper die package are connected to the contacts of the first and second edge portions of the package substrate.

Package Structures and Methods for Forming the Same

A device includes a redistribution line, and a polymer region molded over the redistribution line. The polymer region includes a first flat top surface. A solder region is disposed in the polymer region and electrically coupled to the redistribution line. The solder region includes a second flat top surface not higher than the first flat top surface.

Semiconductor device

A semiconductor device includes an insulating substrate including a first surface and an opposing second surface, and a semiconductor chip. The semiconductor chip is mounted over the first surface, includes signal electrodes, power-supply electrodes and ground electrodes, which connect to pads on the first surface of the insulating substrate. Lands provided on the second surface of the insulating substrate include signal lands, power-supply lands and ground lands through vias penetrate from the first surface to the second surface of the insulating substrate, and include signal vias electrically connected the signal connection pads to the signal lands, power-supply vias electrically connected the power-supply connection pads to the power-supply lands and ground vias electrically connected the ground connection pads to the ground lands. At least one of the signal vias are closer to the connection pads than immediately adjacent one of the power-supply vias or the ground vias.

Semiconductor package

A semiconductor package includes a first semiconductor package, a second semiconductor package, and a package-connecting member. The first semiconductor package includes a first substrate, a chip stacking portion disposed on the first substrate and including a plurality of first semiconductor chips, and a first sealant for surrounding the chip stacking portion on the first substrate. The second semiconductor package includes a second substrate, at least one second semiconductor chip disposed on the second substrate, and a second sealant for surrounding the second semiconductor chip on the second substrate. The package-connecting member electrically connects the first semiconductor package and the second semiconductor package. The plurality of first semiconductor chips include a first chip including through silicon vias (TSVs) and a second chip electrically connected to the first chip via the TSVs, and the chip stacking portion includes an internal sealant for filling a space between the first chip and the second chip and extending to a side of the second chip.

Semiconductor package

A semiconductor package includes a substrate including a mounting surface having a plurality of ground pads, a semiconductor chip disposed on the mounting surface, a conductive connection part connected to at least one of the plurality of ground pads and having a greater width at a center than at an end, a molding member exposing a top surface of the conductive connection part while wrapping the mounting surface, the conductive connection part and the semiconductor chip, and a heat slug disposed on the molding member and connected to the top surface of the conductive connection part.

System and Method for Fine Pitch PoP Structure

A fine pitch package-on-package (PoP), and a method of forming, are provided. The PoP may be formed by placing connections, e.g., solder balls, on a first substrate having a semiconductor die attached thereto. A first reflow process is performed to elongate the solder balls. Thereafter, a second substrate having another semiconductor die attached thereto is connected to the solder balls. A second reflow process is performed to form an hourglass connection.

Semiconductor Packages with Integrated Heat Spreaders

One implementation of present disclosure includes a semiconductor package stack. The semiconductor package stack includes an upper package coupled to a lower package by a plurality of solder balls. The semiconductor package stack also includes a lower active die situated in a lower package substrate in the lower package. The lower active die is thermally coupled to a heat spreader in the upper package by a thermal interface material. An upper active die is situated in an upper package substrate in the upper package, the upper package substrate being situated over the heat spreader. The thermal interface material can include an array of aligned carbon nanotubes within a filler material. The heat spreader can include at least one layer of metal or metal alloy. Furthermore, the heat spreader can be connected to ground or a DC voltage source. The plurality of solder balls can be situated under the heat spreader.

Integrated circuit packaging system with terminals and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing a leadframe having a mounting platform; applying an attach layer on the mounting platform; mounting an integrated circuit die on the attach layer; forming an encapsulation on the integrated circuit die and the attach layer, the mounting platform exposed from the encapsulation; and forming a terminal having a terminal protrusion from the leadframe, the terminal protrusion below a horizontal plane of the mounting platform.

Wiring substrate and method of manufacturing the same

There is provided a wiring substrate. The wiring substrate includes: an insulating layer; first electrode pads having first exposed surfaces, the first exposed surfaces being exposed from the insulating layer; and second electrode pads having second exposed surfaces, the second exposed surfaces being exposed from the insulating layer. There is a level difference between the first exposed surfaces and the second exposed surfaces.

Package including an underfill material in a portion of an area between the package and a substrate or another package

Embodiments include but are not limited to apparatuses and systems including semiconductor packages, e.g. memory packages, having a substrate or a first package, and a second package coupled to the substrate or the first package, wherein the second package includes at least one die and an underfill material disposed in a portion, but not an entirety, of an area between the package and the substrate or the first package. Other embodiments may be described and claimed.

Method and apparatus for reducing package warpage

Embodiments of mechanisms for flattening a packaged structure are provided. The mechanisms involve a flattening apparatus and the utilization of protection layer(s) between the packaged structure and the surface(s) of the flattening apparatus. The protection layer(s) is made of a soft and non-sticking material to allow protecting exposed fragile elements of the packaged structure and easy separation after processing. The embodiments of flattening process involve flattening the warped packaged structure by pressure under elevated processing temperature. Processing under elevated temperature allows the package structure to be flattened within a reasonable processing time.

Semiconductor device

A semiconductor device is provided, which comprises a first semiconductor package, a second semiconductor package, and a connection structure. The first semiconductor package includes a first substrate. The first substrate includes a first region and a second region. The second semiconductor package is mounted on the first semiconductor package. The connection structure electrically connects the second semiconductor package and the first semiconductor package. The connection structure comprises first connection patterns at the first region. The first connection patterns provide a data signal at the first region. The connection structure further comprises second connection patterns at the second region. The second connection patterns provide a control/address signal at the second region. A number of the second connection patterns is less than a number of the first connection patterns.

Package-on-package assembly with wire bond vias

A structure includes a substrate having a first region and a second region, the substrate also having a first surface and a second surface. Electrically conductive elements are exposed at the first surface within the second region. Wire bonds have bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. At least one of the wire bonds has a shape such that the wire bond defines an axis between the free end and the base thereof and such that the wire bond defines a plane. A bent portion of the at least one wire bond extends away from the axis within the plane. A dielectric encapsulation layer covers portions of the wire bonds such that unencapsulated portions, including the ends, of the wire bonds are defined by portions of the wire bonds that are uncovered by the encapsulation layer.

Semiconductor package and package on package having the same

A semiconductor package and a package on package are provided. The semiconductor package includes a substrate; a semiconductor chip attached to a surface of the substrate; connecting conductors disposed on the surface of the substrate; a mold formed on the substrate and in which the connecting conductors and the semiconductor chip are provided; and connecting via holes extending through the mold and exposing the connecting conductors. With respect to a first connecting via hole of the connecting via holes, a planar distance between a first connecting conductor exposed by the first connecting via hole and an entrance of the first connecting via hole is not uniform.

Semiconductor package and method of manufacturing the same

A semiconductor package is provided with a package on package (PoP) configuration, and which may be implemented having a fine pitch. The semiconductor package can include a lower printed circuit board (PCB) having a top surface onto which at least one lower semiconductor chip is attached; an upper printed circuit board (PCB) disposed on the lower printed circuit board (PCB) and having a top surface onto which at least one upper semiconductor chip is attached; and a lower mold layer formed on the top surface of the lower printed circuit board (PCB) so as to be disposed between the lower printed circuit board (PCB) and the upper printed circuit board (PCB). A through via hole, including a first section formed in the lower mold layer and a second section formed on the first section can also be provided. The through via hole extends through the lower mold layer, and a solder layer is formed in the through via hole to electrically connect the upper printed circuit board (PCB) and the lower printed circuit board (PCB). A horizontal cross-sectional area of the first section of the through via hole varies over substantially an entire height of the first section, and a horizontal cross-sectional area of the second section gradually decreases from a top surface thereof toward an inner portion of the lower mold layer.

Methods and Apparatus for Package on Package Structures

A package-on-package (“PoP”) structure and a method of forming are provided. The PoP structure may be formed by forming a first set of electrical connections on a first substrate. A first material may be applied to the first set of electrical connections. A second substrate may be provided having a second set of electrical connections formed thereon. The first set of electrical connections of the first substrate having the epoxy flux applied may be contacted to the second electrical connections of the second substrate. A reflow process may be performed to electrically connect the first substrate to the second substrate. The epoxy flux applied to the first electrical connections of the first substrate may prohibit electrical bridges or shorts from forming during the reflow process.

Package assembly for embedded die and associated techniques and configurations

Embodiments of the present disclosure are directed towards a package assembly for embedded die and associated techniques and configurations. In one embodiment, an apparatus includes a package assembly comprising a die attach layer, a die coupled with the die attach layer, the die having an active side including active devices of the die and an inactive side disposed opposite to the active side, a reinforced plate coupled with the die attach layer, the reinforced plate having a first side and a second side disposed opposite to the first side and a cavity disposed in the reinforced plate and one or more build-up layers coupled with the second side of the reinforced plate, the one or more build-up layers including an insulator and conductive features disposed in the insulator, the conductive features being electrically coupled with the die, wherein the inactive side of the die is in direct contact with the die attach layer, the first side of the reinforced plate is in direct contact with the die attach layer and the die is disposed in the cavity. Other embodiments may be described and/or claimed.

MICROELECTRONIC DEVICES, STACKED MICROELECTRONIC DEVICES, AND METHODS FOR MANUFACTURING SUCH DEVICES

Microelectronic devices and methods for manufacturing such devices are disclosed herein. In one embodiment, a packaged microelectronic device can include an interposer substrate with a plurality of interposer contacts. A microelectronic die is attached and electrically coupled to the interposer substrate. The device further includes a casing covering the die and at least a portion of the interposer substrate. A plurality of electrically conductive through-casing interconnects are in contact with and projecting from corresponding interposer contacts at a first side of the interposer substrate. The through-casing interconnects extend through the thickness of the casing to a terminus at the top of the casing. The through-casing interconnects comprise a plurality of filaments attached to and projecting away from the interposer contacts in a direction generally normal to the first side of the interposer substrate. 1. A packaged microelectronic device , comprising:an interposer substrate having a first side with a plurality of interposer contacts and a second side opposite the first side, the second side including a plurality of interposer pads arranged in an array corresponding to a standard JEDEC pinout;a microelectronic die attached and electrically coupled to the interposer substrate;a casing covering the die and at least a portion of the interposer substrate, wherein the casing has a thickness and a top facing away from the interposer substrate; anda plurality of electrically conductive through-casing interconnects in contact with and projecting from corresponding interposer contacts, wherein the through-casing interconnects extend through the thickness of the casing to a terminus at the top of the casing, and wherein the through-casing interconnects are at least partially encapsulated in the casing,wherein the through-casing interconnects comprise a plurality of filaments attached to and projecting away from the interposer contacts in a direction generally normal to ...

Lead-Free Solder Ball

A lead-free solder ball is provided which suppresses interfacial peeling in a bonding interface of a solder ball, fusion defects which develop between the solder ball and solder paste, and which can be used both with Ni electrodes plated with Au or the like and Cu electrodes having a water-soluble preflux applied atop Cu. The lead-free solder ball for electrodes of BGAs or CSPs consists of 1.6-2.9 mass % of Ag, 0.7-0.8 mass % of Cu, 0.05-0.08 mass % of Ni, and a remainder of Sn. It has excellent resistance to thermal fatigue and to drop impacts regardless of the type of electrodes of a printed circuit board to which it is bonded, which are Cu electrodes or Ni electrodes having Au plating or Au/Pd plating as surface treatment.

STUD BUMP STRUCTURE FOR SEMICONDUCTOR PACKAGE ASSEMBLIES

A semiconductor package structure comprises a substrate, a die bonded to the substrate, and one or more stud bump structures connecting the die to the substrate, wherein each of the stud bump structures having a stud bump and a solder ball encapsulating the stud bump to enhance thermal dissipation and reduce high stress concentrations in the semiconductor package structure. 116.-. (canceled)17. A method of forming a stud bump structure in a package structure , comprising:providing a conductive wire;pressing one end of the conductive wire to a bond pad and melting the conductive wire end to form a stud bump on the bond pad;severing the other end of the conductive wire close above the stud bump; andsoldering a solder ball to a top surface of the stud bump, the solder ball encapsulating the stud bump.18. The method of forming a stud bump structure of claim 17 , wherein the conductive wire comprises aluminum claim 17 , aluminum alloy claim 17 , copper claim 17 , copper alloy claim 17 , gold claim 17 , or gold alloy.19. The method of forming a stud bump structure of claim 17 , wherein the pressing and melting the conductive wire to form a stud bump on the bond pad is performed by wire bonding tool.20. The method of forming a stud bump structure of claim 17 , wherein the pressing and melting the conductive wire to form a stud bump on the bond pad is performed by a stud bump bonder.21. The method of forming a stud bump structure of claim 17 , wherein the severing the other end of the conductive wire leaves a tail extending from the bond pad.22. The method of forming a stud bump structure of claim 17 , further comprising applying ultrasonic energy to form the stud bump.23. The method of forming a stud bump structure of claim 17 , wherein the stud bump is disposed at a corner of a die.24. A method for forming a package structure claim 17 , the method comprising:providing a die wherein the die has a first periphery region adjacent a first edge of the die and a second ...

Semiconductor Device and Method of Forming Build-Up Interconnect Structures Over a Temporary Substrate

A semiconductor device has a first build-up interconnect structure formed over a substrate. The first build-up interconnect structure includes an insulating layer and conductive layer formed over the insulating layer. A vertical interconnect structure and semiconductor die are disposed over the first build-up interconnect structure. The semiconductor die, first build-up interconnect structure, and substrate are disposed over a carrier. An encapsulant is deposited over the semiconductor die, first build-up interconnect structure, and substrate. A second build-up interconnect structure is formed over the encapsulant. The second build-up interconnect structure electrically connects to the first build-up interconnect structure through the vertical interconnect structure. The substrate provides structural support and prevents warpage during formation of the first and second build-up interconnect structures. The substrate is removed after forming the second build-up interconnect structure. A portion of the insulating layer is removed exposing the conductive layer for electrical interconnect with subsequently stacked semiconductor devices. 1. A method of making a semiconductor device , comprising:providing a substrate;forming a first interconnect structure over the substrate;disposing a first semiconductor die over the first interconnect structure;disposing the substrate over a carrier with the first semiconductor die oriented away from the carrier;depositing an encapsulant over the carrier, substrate, and first semiconductor die;forming a second interconnect structure over the encapsulant and semiconductor die; andremoving the substrate to expose the first interconnect structure after forming the second interconnect structure.2. The method of claim 1 , further including forming a conductive column over the first interconnect structure.3. The method of claim 2 , wherein the conductive column extends from the first interconnect structure to the second interconnect structure ...

Fan-Out Package with Cavity Substrate

Structures and methods of forming fan-out packages are provided. The packages described herein may include a cavity substrate, one or more semiconductor devices located in a cavity of the cavity substrate, and one or more redistribution structures. Embodiments include a cavity preformed in a cavity substrate. Various devices, such as integrated circuit dies, packages, or the like, may be placed in the cavity. Redistribution structures may also be formed.

Circuit substrate and method for manufacturing the same

A circuit substrate includes a core substrate having cavity penetrating through the core substrate, a metal block accommodated in the cavity of the core substrate, a first build-up layer including an insulating layer and laminated on first side of the core substrate such that the first build-up layer is covering the cavity on the first side of the core substrate, and a second build-up layer including an insulating layer and laminated on second side of the core substrate such that the second build-up layer is covering the cavity on the second side of the core substrate, and a filling resin filling gap formed between the cavity and block positioned in the cavity of the core substrate. The block has roughened surfaces such that the roughened surfaces are in contact with the insulating layers in the first and second build-up layers on the first and second sides of the core substrate.

Wiring substrate and semiconductor package

A wiring substrate includes an insulating layer that is an outermost layer of the wiring substrate and includes an external exposed surface, a pad forming part formed on a side of the external exposed surface, and a pad that projects from the external exposed surface. The pad forming part includes a recess part recessed from the external exposed surface, and a weir part that projects from the external exposed surface and encompasses the recess part from a plan view. The pad includes a pad body formed within the recess part and the weir part, and an eave part formed on the weir part. The pad body includes an end part that projects to the weir part. The eave part projects in a horizontal direction from the end part of the pad body. The end part of the pad body includes a flat surface.

Semiconductor package

A semiconductor package is provided. The semiconductor package includes a package substrate, a semiconductor chip, bonding wires, and a molding film. The package substrate includes a first surface having a recessed portion, a second surface opposed to the first surface, an opening extending from the recessed portion of the first surface to the second surface, and bonding pads provided on the first surface. The semiconductor chip is disposed on the second surface of the package substrate to cover the opening, and includes center pads exposed through the opening. Bonding wires electrically connect the center pads and the bonding pads through the opening. The molding film covers the bonding pads, the center pads, and the bonding wires. A depth of the recessed portion is greater than a distance between the recessed portion of the first surface and a lowermost surface of the molding film.

SEMICONDUCTOR DEVICE

This invention provides a multi-pin semiconductor device as a low-cost flip-chip BGA. In the flip-chip BGA, a plurality of signal bonding electrodes in a peripheral area of the upper surface of a multilayer wiring substrate are separated into inner and outer ones and a plurality of signal through holes coupled to a plurality of signal wirings drawn inside are located between a plurality of rows of signal bonding electrodes and a central region where a plurality of bonding electrodes for core power supply are located so that the chip pad pitch can be decreased and the cost of the BGA can be reduced without an increase in the number of layers in the multilayer wiring substrate. 1a wiring substrate having a first insulating layer which has a first main surface and a second main surface opposite the first main surface, a plurality of through-holes which penetrate the first main surface to the second main surface of the first insulating layer, a plurality of wirings being formed over the first main surface of the first insulating layer and electrically connected to the plurality of through-holes, respectively, a solder resist layer formed over the first main surface of the first insulating layer such that the solder resist layer covers a part arranged on the first main surface of each of the plurality of through-holes; anda semiconductor chip having an obverse surface over which a plurality of bump electrodes are formed and a reverse surface opposite the obverse surface and mounted over the first main surface of the first insulating layer of the wiring substrate such that the obverse surface thereof faces to the first main surface of the first insulating layer of the wiring substrate,wherein a plurality of openings are formed in the solder resist layer such that a part of each of the plurality of wirings is exposed from each of the plurality of openings, and therefore, the part exposed from each of the plurality of openings of the plurality of wirings is provided as an ...

Semiconductor Device and Method of Forming Protrusion E-Bar for 3D SIP

A semiconductor device has a first substrate and a semiconductor die disposed over the first substrate. A second substrate has a multi-layered conductive post. The conductive post has a first conductive layer and a second conductive layer formed over the first conductive layer. The first conductive layer is wider than the second conductive layer. A portion of the conductive post can be embedded within the second substrate. The second substrate is disposed over the first substrate adjacent to the semiconductor die. An encapsulant is deposited around the second substrate and semiconductor die. An opening is formed in the second substrate aligned with the conductive post. An interconnect structure is formed in the opening to contact the conductive post. A discrete electrical component is disposed over a surface of the first substrate opposite the semiconductor die. A shielding layer is formed over the discrete electrical component. 1. A method of making a semiconductor device , comprising:providing a first substrate;disposing a semiconductor die over the first substrate;providing a second substrate including a conductive post protruding from the second substrate;disposing the second substrate over the first substrate;forming an opening in the second substrate aligned with the conductive post; andforming an interconnect structure in the opening to contact the conductive post.2. The method of claim 1 , further including depositing an encapsulant around the second substrate and semiconductor die.3. The method of claim 1 , wherein a portion of the conductive post is embedded within the second substrate.4. The method of claim 1 , wherein the conductive post includes:forming a first conductive layer; andforming a second conductive layer over the first conductive layer, wherein the first conductive layer is wider than the second conductive layer.5. The method of claim 1 , further including disposing a discrete electrical component over a surface of the first substrate ...

Bonding Package Components Through Plating

A method includes aligning a first electrical connector of a first package component to a second electrical connector of a second package component. With the first electrical connector aligned to the second electrical connector, a metal layer is plated on the first and the second electrical connectors. The metal layer bonds the first electrical connector to the second electrical connector.

Package-on-Package Structure Including a Thermal Isolation Material and Method of Forming the Same

A semiconductor device includes a first package component and a second package component. The first package component has a first die formed on a first substrate. A second package component has a second die formed on a second substrate. A thermal isolation material is attached on the first die, wherein the thermal isolation material thermally insulates the second die from the first die, and the thermal isolation material has a thermal conductivity of from about 0.024 W/mK to about 0.2 W/mK. A first set of conductive elements couples the first package component to the second package component.

Flip-chip, face-up and face-down centerbond memory wirebond assemblies

A microelectronic assembly can include a substrate having first and second surfaces and an aperture extending therebetween, the substrate having terminals. The assembly can also include a first microelectronic element having a front surface facing the first surface of the substrate, a second microelectronic element having a front surface facing the first microelectronic element and projecting beyond an edge of the first microelectronic element, first and second leads electrically connecting contacts of the respective first and second microelectronic elements to the terminals, and third leads electrically interconnecting the contacts of the first and second microelectronic elements. The contacts of the first microelectronic element can be exposed at the front surface thereof adjacent the edge thereof. The contacts of the second microelectronic element can be disposed in a central region of the front surface thereof. The first, second, and third leads can have portions aligned with the aperture.

PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS

A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer. 1. A structure comprising:a substrate having a first region and a second region, the substrate also having a first surface and a second surface remote from the first surface, wherein the first surface extends in first and second lateral directions to define a first plane;electrically conductive elements exposed at the first surface of the substrate within the second region;wire bonds having bases bonded to respective ones of the conductive elements and free ends remote from the substrate and remote from the bases, at least one of the wire bonds having a shape such that the at least one wire bond defines an axis between the free end and the base thereof coincident with a side surface of the at least one wire bond and such that the at least one wire bond defines a second plane, a bent portion of the at least one wire bond extending away from the axis within the second plane, wherein the entire at least one wire bond is positioned on one side of the axis and a substantially straight portion of the at least one wire bond extends between the free end ...

Semiconductor Device and Method of Forming a Vertical Interconnect Structure for 3-D FO-WLCSP

A semiconductor device has an encapsulant deposited over a first surface of the semiconductor die and around the semiconductor die. A first insulating layer is formed over a second surface of the semiconductor die opposite the first surface. A conductive layer is formed over the first insulating layer. An interconnect structure is formed through the encapsulant outside a footprint of the semiconductor die and electrically connected to the conductive layer. The first insulating layer includes an optically transparent or translucent material. The semiconductor die includes a sensor configured to receive an external stimulus passing through the first insulating layer. A second insulating layer is formed over the first surface of the semiconductor die. A conductive via is formed through the first insulating layer outside a footprint of the semiconductor die. A plurality of stacked semiconductor devices is electrically connected through the interconnect structure.

Methods and Apparatus for Package with Interposers

An interposer may comprise a metal layer above a substrate. A dam or a plurality of dams may be formed above the metal layer. A dam surrounds an area of a size larger than a size of a die which may be connected to a contact pad above the metal layer within the area. A dam may comprise a conductive material, or a non-conductive material, or both. An underfill may be formed under the die, above the metal layer, and contained within the area surrounded by the dam, so that no underfill may overflow outside the area surrounded by the dam. Additional package may be placed above the die connected to the interposer to form a package-on-package structure.

DYNAMIC RANDOM ACCESS MEMORY (DRAM) MOUNTS

Donut-shaped Dynamic Random Access Memory (DRAM) includes a hole that fits around a processor, such that the DRAM and the processor are adjacent to one another on an Integrated Circuit (IC) package. In an embodiment, a heat spreader is mounted on top of the processor and covers a top of the DRAM without touching the DRAM. 1. (canceled).2. A circuit package , comprising:a first memory device situated to a first side of a processor in parallel to the processor and mounted on a package board of a processor assembly; anda second memory device situated to a second side of the processor in parallel to the processor and mounted on the package board of the processor assembly.3. The circuit package of claim 2 , wherein the first memory device and the second memory device are donut-shaped.4. The circuit package of further comprising a heat spreader mounted on top of the processor and extending past a first outer edge along the first side past the first memory device and the heat spreader extending past a second outer edge along the second side past the second memory device.5. The circuit package of further comprising claim 2 , at least one additional first memory device stacked on top of the first memory device.6. The circuit package of further comprising claim 5 , at least one additional second memory device stacked on top of the second memory device.7. The circuit package of claim 6 , wherein the at least one additional first memory device claim 6 , the first memory device claim 6 , the at least one additional second memory device claim 6 , and the second memory device have heights that are less than a processor height for the processor on the packaging board of the processor assembly.8. The circuit package of claim 7 , wherein a first outer edge of the first memory device overhangs beyond a first side edge of the packaging board claim 7 , and wherein a second outer edge of the second memory device overhangs beyond a second side edge of the packaging board.9. The circuit ...

SEMICONDUCTOR TSV DEVICE PACKAGE FOR CIRCUIT BOARD CONNECTION

An electronic device includes a circuit board and a semiconductor device package. The semiconductor device package includes a laminate layer. The semiconductor device package includes a semiconductor die having an active side, an inactive side opposite the active side, and through-silicon vias (TSVs) conductively connecting the active side to the inactive side and conductively connecting the semiconductor die to one of the laminate layer and the circuit board. The semiconductor device package includes a laminate layer having a side attached to the active side or the inactive side semiconductor die. The semiconductor device package includes solder balls at the side of the laminate layer attached to the semiconductor die, around the semiconductor die, and attached to the circuit board. 1. A method comprising:preparing a semiconductor die having an active side, an inactive side opposite the active side, and a plurality of through-silicon vias (TSVs) conductively connecting the active side to the inactive side;attaching a laminate layer to the semiconductor die; andattaching a circuit board to the semiconductor die.2. The method of claim 1 , wherein the laminate layer is attached to the semiconductor die before the circuit board is attached to the semiconductor die claim 1 ,wherein attaching the laminate layer to the semiconductor die comprises employing a plurality of solder bumps to attach a side of the laminate layer to the active side of the semiconductor die, employing a plurality of solder balls at the side of the laminate layer attached to the semiconductor die, around the semiconductor die, to attach laminate layer to the circuit board; and', 'employing solder paste to attach the circuit board to the inactive side of the semiconductor at which the TSVs are exposed., 'and wherein attaching the circuit board to the semiconductor die includes attaching the circuit board to the laminate layer and comprises3. The method of claim 1 , wherein the laminate layer is ...

Semiconductor Bonding Structures and Methods

A system and method for applying an underfill is provided. An embodiment comprises applying an underfill to a substrate and patterning the underfill. Once patterned other semiconductor devices, such as semiconductor dies or semiconductor packages may then be attached to the substrate through the underfill, with electrical connections from the other semiconductor devices extending into the pattern of the underfill. 1. A method of manufacturing a semiconductor device , the method comprising:applying an underfill material to a substrate;patterning the underfill material to form a first opening through the underfill material and a second opening through the underfill material, wherein the first opening has a first width, the second opening has a second width, and the first width is different from the second width; andafter the patterning the underfill material, bonding a first semiconductor die to the substrate through the first opening and bonding a first package to the substrate through the second opening.2. The method of claim 1 , wherein the first width is between about 10 μm and about 100 μm.3. The method of claim 2 , wherein the second width is between about 50 μm and about 400 μm.4. The method of claim 1 , further comprising partially curing the underfill material prior to the patterning the underfill material.5. The method of claim 4 , further comprising curing the underfill material after the bonding the first semiconductor die.6. The method of claim 1 , further comprising forming external connectors to the substrate claim 1 , wherein the external connectors are located on an opposite side of the substrate from the first semiconductor die.7. A method of manufacturing a semiconductor device claim 1 , the method comprising:removing a first portion of an underfill material to expose a first portion of a substrate;removing a second portion of the underfill material to expose a second portion of the substrate;after the removing the first portion of the underfill ...

Package-on-package Assembly With Wire Bond Vias

A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer.

Semiconductor package having discrete antenna device

One embodiment of the present disclosure provides a semiconductor package including a bottom chip package having a first side and a second side opposing the first side, and a top antenna package mounted on the first side of the bottom chip package. The bottom chip package further includes a semiconductor chip. The semiconductor chip may include a RFIC chip. The top antenna package has at least one radiative antenna element.

LOW-NOISE FLIP-CHIP PACKAGES AND FLIP CHIPS THEREOF

A low-noise flip-chip package, comprising: a carrier substrate having first and second opposing main faces; and a flip-chip substrate connected in a face-down manner onto the first main face of the carrier substrate via a connection array, wherein: the flip-chip substrate comprises at least first and second circuitry portions spaced apart from one another; the flip-chip substrate comprises a substrate-contact boundary located between the first and second circuitry portions; and each of the first circuitry portion, the second circuitry portion and the substrate-contact boundary has its own separate signal-reference connection extending via a respective connection of the connection array through the carrier substrate to a respective electrical contact at the second main face of the carrier substrate for connection to a common signal-reference element in an external circuit. 16-. (canceled)7. A flip chip package , comprising:a first substrate;a flip chip provided above the first substrate;a first circuitry provided in the flip chip;a second circuitry provided in the flip chip, the second circuitry being apart from the first circuitry;a first substrate contact provided in the flip chip and provided between the first circuitry and the second circuitry;a first signal path coupled with the first circuitry and the second circuitry, signals passing from the first circuitry to the second circuitry in the first signal path, the first signal path crossing the first substrate contact;a second signal path coupled with the first circuitry and the second circuitry, signals passing from the second circuitry to the first circuitry in the second signal path, the second signal path crossing the first substrate contact;a first buffer circuitry provided in the first signal path, the first buffer being coupled with the first substrate contact; anda second buffer circuitry provided in the second signal path, the second being coupled with the first substrate contact.8. The flip chip package ...

Semiconductor package, semiconductor device using the same and manufacturing method thereof

A semiconductor package includes a substrate, a first electronic component, a first conductive layer, a first pillar layer and a first package body. The first electronic component is disposed on the substrate. The first pillar layer connects the first conductive layer and the substrate. The first package body encapsulates the first conductive layer, the first pillar layer and the first electronic component. The first conductive layer is embedded in the first package body.

Porous alumina templates for electronic packages

Interposers and methods of making the same are disclosed herein. In one embodiment, an interposer includes a region having first and second oppositely facing surfaces and a plurality of pores, each pore extending in a first direction from the first surface towards the second surface, wherein alumina extends along a wall of each pore; a plurality of electrically conductive connection elements extending in the first direction, consisting essentially of aluminum and being electrically isolated from one another by at least the alumina; a first conductive path provided at the first surface for connection with a first component external to the interposer; and a second conductive path provided at the second surface for connection with a second component external to the interposer, wherein the first and second conductive paths are electrically connected through at least some of the connection elements.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device and manufacturing method thereof. Various aspects of the disclosure may, for example, comprise forming a back end of line layer on a dummy substrate, completing at least a first portion of an assembly, and removing the dummy substrate. 120-. (canceled)21. A semiconductor device comprising:a first redistribution layer comprising a first dielectric and a first conductive layer;a semiconductor die mounted to and electrically connected to an upper side of the first redistribution layer, where the semiconductor die comprises a die bonding pad on a lower die side of the semiconductor die and over the upper side of the first redistribution layer, and where the die bonding pad electrically connects the semiconductor die to the first conductive layer of the first redistribution layer;a conductive pillar on the first redistribution layer, where a lower end of the conductive pillar is electrically connected to the first conductive layer of the first redistribution layer, and the lower end of the conductive pillar is vertically lower than the die bonding pad;an encapsulant that encapsulates the upper side of the first redistribution layer, the conductive pillar, and the semiconductor die, where the encapsulant comprises an upper encapsulant side facing away from the first redistribution layer and a lower encapsulant side facing toward the first redistribution layer;a second conductive layer on the upper encapsulant side, where the second conductive layer is electrically connected to the first conductive layer of the first redistribution layer through the conductive pillar; andan underfill material directly vertically between the semiconductor die and the first redistribution layer.22. The semiconductor device of claim 21 , comprising a plurality of metallic balls comprising solder and coupled to a lower side of the first redistribution layer.23. The semiconductor device of claim 21 , wherein the underfill material and the encapsulant are formed of a same ...

Connection system of semiconductor packages

A connection system of semiconductor packages includes: a printed circuit board; a first semiconductor package disposed on a first surface of the printed circuit board and connected to the printed circuit board through first electrical connection structures; a second semiconductor package disposed on a second surface of the printed circuit board and connected to the printed circuit board through second electrical connection structures; and a third semiconductor package disposed on the first semiconductor package and connected to the first semiconductor package through third electrical connection structures. The first semiconductor package includes an application processor (AP), the second semiconductor package includes a memory, and the third semiconductor package includes a power management integrated circuit (PMIC).

Integrated circuit package having surface-mount blocking elements

A first cavity-down ball grid array (BGA) package includes a substrate member and an array of bond balls. The array of bond balls includes a pair of parallel extending rows of outer mesh bond balls and a row of inner signal bond balls that is parallel to the pair of rows of outer mesh bond balls. A surface-mount blocking element is disposed between the row of inner signal bond balls and the pair of rows of outer mesh bond balls. The surface-mount blocking element is either a passive or an active component of the BGA package. In one example, the first cavity-down BGA package is surface-mounted to a second cavity-down BGA package to form a package-on-package (POP) security module. The surface-mount blocking element provides additional physical barrier against the probing of the inner signal bond balls. Sensitive data is therefore protected from unauthorized access. 1. A method comprising:(a) providing a first cavity-down Ball Grid Array (BGA) package having a substrate member and an array of bond balls, wherein the array of bond balls includes a pair of parallel extending rows of outer mesh bond balls and a row of inner signal bond balls that is parallel to the pair of rows of outer mesh bond balls, wherein each of the bond balls has a diameter, and wherein the distance between the row of inner signal bond balls and the pair of rows of outer mesh bond balls is less than five times the diameter of the bond balls;(b) providing a second cavity-down BGA package having a substrate member and a surface-mount blocking element; and(c) surface-mounting the first BGA package to the substrate member of the second BGA package such that the surface-mount blocking element is disposed between the pair of rows of outer mesh bond balls and the row of inner signal bond balls.2. The method of claim 1 , wherein step (b) involves attaching the surface-mount blocking element to the substrate member of the second BGA package.3. The method of claim 1 , wherein the substrate member of the ...

Package-On-Package (PoP) Structure Including Stud Bulbs

Embodiments concern Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures. According to an embodiment, a structure includes a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs. 1. A device comprising:a first pad on a first surface of a first substrate;a second pad on a second surface of a second substrate;a metallic element interposed between the first pad and the second pad, the metallic element electrically coupled to the first pad, the metallic element comprising a base portion and an elongated portion extending from the base portion toward the second pad;a solder connector in contact with the elongated portion and electrically coupled to the second pad; andan inter-metallic compound (IMC) between the elongated portion and the solder connector.2. The device of claim 1 , further comprising a protection layer extending over the base portion and the elongated portion.3. The device of claim 1 , further comprising a die attached to the first substrate adjacent the metallic element.4. The device of claim 3 , wherein a height of the metallic element from the first substrate is greater than a height of the die from the first substrate.5. The device of claim 1 , wherein the metallic element comprises a copper wire.6. The device of claim 1 , wherein the base portion and the elongated portion comprises a single continuous element.7. A device comprising:a first substrate having a first pad;a second substrate having a second pad;a first connector interposed between the first pad and the second pad, the first connector having a first wide portion and a second elongated portion, the first wide portion being ...

Memory module and memory system

A memory module is provided which includes a printed circuit board; first semiconductor packages provided on one surface of the printed circuit board; and second semiconductor packages provided on the other surface of the printed circuit board, the first semiconductor packages and the second semiconductor packages having semiconductor dies that form ranks. A number of the ranks formed by the first semiconductor packages being different from a number of the ranks formed by the second semiconductor packages. Semiconductor packages forming a same one of the ranks receive a chip selection signal in common and semiconductor packages forming other ranks receive a different chip selection signal.

SEMICONDUCTOR DEVICE

A semiconductor device includes a memory component, which is a semiconductor component (a semiconductor chip or a semiconductor package), to be mounted over an upper surface of a wiring substrate. In addition, in the upper surface, a distance between the memory component and a first substrate side of the upper surface is smaller than a distance between the memory component and a second substrate side of the upper surface. In addition, in the upper surface, a dam portion is formed between the memory component and the first substrate side. 1. A semiconductor device comprising:a wiring substrate including a first surface, a first insulating film formed on the first surface, and a dam portion formed on the first insulating film;a first semiconductor component mounted over the first surface of the wiring substrate; anda first resin located between the first insulating film and the first semiconductor component,wherein the first surface includes a first side, and a second side opposite to the first side,wherein a distance between the first semiconductor component and the first side is smaller than a distance between the first semiconductor component and the second side, andwherein the dam portion is formed between the first semiconductor component and the first side, but is not formed between the first semiconductor component and the second side.2. The semiconductor device according to claim 1 ,wherein a plane shape of the first surface has a quadrangle including the first side, the second side, a third side intersecting with each of the first side and the second side, and a fourth side opposite to the third side and intersecting with each of the first side and the second side,wherein a distance between the first semiconductor component and the third side is smaller than a distance between the first semiconductor component and the second side,wherein the wiring substrate includes a first dam portion formed on the first insulating film and formed between the first ...

SUBSTRATE ON SUBSTRATE PACKAGE

Embodiments herein may relate to a patch on interposer (PoINT) architecture. In embodiments, the PoINT architecture may include a plurality of solder joints between a patch and an interposer. The solder joints may include a relatively high temperature solder ball and a relatively low temperature solder paste that at least partially surrounds the solder ball. Other embodiments may be described and/or claimed. 1. A package comprising:a first substrate with a first side and a second side opposite the first side;a second substrate with a first side and a second side opposite the first side, wherein the first substrate and second substrate define a space between the first side of the first substrate and the first side of the second substrate;a solder ball disposed within the space and physically coupled with the first side of the first substrate and the first side of the second substrate; anda solder paste positioned within the space and physically coupled with the solder ball, the first side of the first substrate, and the first side of the second substrate, wherein the solder paste partially surrounds the solder ball while the solder ball is partially exposed.2. (canceled)3. The package of claim 1 , wherein the solder ball includes an alloy of tin claim 1 , silver and copper claim 1 , or an alloy of tin and bismuth.4. The package of claim 1 , wherein the solder paste includes epoxy.5. The package of claim 1 , wherein the first substrate has approximately 20 inptut/output connections or more per millimeter claim 1 , or has a line/space measurement of less than approximately 20/20 micrometers.6. The package of claim 1 , wherein the second substrate has approximately 10 input/output connections or less per millimeter claim 1 , or has a line/space measurement of greater than approximately 20/20 micrometers.7. The package of claim 1 , wherein the first substrate includes a die coupled with the second side of the first substrate by a solder joint without being in contact ...

PRINTED CIRCUIT BOARD AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME

A semiconductor package including a package substrate including a mounting region and at least one through-hole arranged in the mounting region, and a semiconductor chip mounted on the mounting region, the semiconductor chip including a first side and a second side, the second side of the semiconductor chip being opposite to the first side of the semiconductor chip, the at least one through-hole of the package substrate being closer to the second side of the semiconductor chip than the first side of the semiconductor chip may be provided. 1. A semiconductor package comprising:a package substrate including a mounting region and at least one through-hole arranged in the mounting region; anda semiconductor chip mounted on the mounting region, the semiconductor chip including a first side and a second side, the second side of the semiconductor chip being opposite to the first side of the semiconductor chip, the second side of the semiconductor chip being closer to the at least one through-hole of the package substrate than the first side of the semiconductor chip.2. The semiconductor package of claim 1 , further comprising:a molding layer between the semiconductor chip and the package substrate, the molding layer filling at least a portion of the at least one through-hole.3. The semiconductor package of claim 1 , wherein a first distance between the at least one through-hole and the first side of the semiconductor chip is about 1.5 to 3 times a second distance between the at least one through-hole and the second side of the semiconductor chip.4. The semiconductor package of claim 1 , wherein the at least one through-hole comprises a plurality of through-holes.5. The semiconductor package of claim 4 , wherein the plurality of through-holes are arranged in a first direction perpendicular to the first side of the semiconductor chip or in a second direction parallel to the first side of the semiconductor chip.6. The semiconductor package of claim 4 , wherein the plurality ...

SHIELDED FAN-OUT PACKAGED SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING

Several aspects of the present technology are directed toward fan-out packaged semiconductor devices having an integrated shield to protect against electromagnetic interference and methods of manufacturing such devices. The shield can be constructed by forming a conductive wall on a redistribution structure and disposing a conductive cap on an upper surface of an encapsulant. The conductive wall and the conductive cap are electrically connected to each other. By forming the conductive wall directly on the redistribution structure and separately disposing the conductive cap onto an upper surface of the encapsulant, an electromagnetic shield can be readily formed using wafer-level or panel-level processing techniques that are efficient and cost-effective. Several embodiments of semiconductor devices in accordance with the present technology accordingly shield the integrated circuitry of semiconductor dies from electromagnetic interference. 1. A method of packaging a semiconductor device , comprising:electrically coupling a semiconductor die to die contacts at a first side of a redistribution structure, wherein the die contacts are electrically coupled to ball pads at a second side of the redistribution structure;forming a contiguous conductive wall around the semiconductor die by depositing a conductive material onto the redistribution structure such that the conductive wall is formed progressively with increasing height, wherein the conductive wall is electrically coupled to at least one shield contact at the first side of the redistribution structure, and wherein the shield contact is electrically coupled to a ball pad at the second side of the redistribution structure;depositing an encapsulant over the semiconductor die, wherein the encapsulant has an upper surface;removing a portion of the encapsulant and a portion of the conductive wall to form the upper surface on the encapsulant over the semiconductor die and a top surface on the conductive wall, wherein the ...

Semiconductor Device and Method of Forming Interconnect Structure for Encapsulated Die Having Pre-Applied Protective Layer

A semiconductor device has a protective layer formed over an active surface of a semiconductor wafer. The semiconductor die with pre-applied protective layer are moved from the semiconductor wafer and mounted on a carrier. The semiconductor die and contact pads on the carrier are encapsulated. The carrier is removed. A first insulating layer is formed over the pre-applied protective layer and contact pads. Vias are formed in the first insulating layer and pre-applied protective layer to expose interconnect sites on the semiconductor die. An interconnect structure is formed over the first insulating layer in electrical contact with the interconnect sites on the semiconductor die and contact pads. The interconnect structure has a redistribution layer formed on the first insulating layer, a second insulating layer formed on the redistribution layer, and an under bump metallization layer formed over the second dielectric in electrical contact with the redistribution layer.

Ball arrangement for integrated circuit package devices

An integrated circuit package includes a ball arrangement that includes transmitter contact pairs arranged in a first portion of a ball grid array disposed in the integrated circuit package. Each of the transmitter contact pairs include transmitter differential signal contacts. Pairs of the transmitter contact pairs located adjacent to one another are in a staggered arrangement. The ball arrangement also includes receiver contact pairs arranged in a second portion of the ball grid array. Each of the receiver contact pairs include receiver differential signal contacts. Pairs of the receiver contact pairs located adjacent to one another are in a staggered arrangement. The ball arrangement also includes voltage supply contacts arranged at least between every two pairs of the transmitter contact pairs and the receiver contact pairs.

SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME

A method for manufacturing a semiconductor package includes: (a) providing a package device, the package device comprising a substrate, a package body and a plurality of connecting elements, the substrate having a first surface, the package body being disposed adjacent to the first surface of the substrate, and the connecting elements being disposed adjacent to the first surface of the substrate and encapsulated by the package body; and (b) removing a portion of the package body along one or more machining paths to expose the connecting elements, wherein each machining path has one or more first paths passing over, between, or along a side of at least two connecting elements, wherein a portion of each of the at least two connecting elements is within the package body, and another portion of each of the at least two connecting elements protrudes from a surface of the package body. 1. A method for manufacturing a semiconductor package , comprising:(a) providing a package device, the package device comprising a substrate, a package body and a plurality of connecting elements, the substrate having a first surface, the package body being disposed adjacent to the first surface of the substrate, and the connecting elements being disposed adjacent to the first surface of the substrate and encapsulated by the package body; and(b) removing a portion of the package body along one or more machining paths to expose the connecting elements, wherein each machining path has one or more first paths passing over, between, or along a side of at least two connecting elements, wherein a portion of each of the at least two connecting elements is within the package body, and another portion of each of the at least two connecting elements protrudes from a surface of the package body.2. The method according to claim 1 , wherein in (b) claim 1 , the machining paths are paths followed by one or more laser beams.3. The method according to claim 1 , wherein in (b) claim 1 , the multiple ...

SEMICONDUCTOR PACKAGE WITH REDUCED NOISE

The present disclosure provides a semiconductor package including a bottom package having a substrate, a radio-frequency (RF) die and a system-on-a-chip (SoC) die arranged on the substrate in a side-by-side manner, a molding compound covering the RF die and the SoC die, and an interposer over the molding compound. Connection elements and a column of signal interference shielding elements are disposed on the substrate. The connection elements surround the SoC die. The column of signal interference shielding elements is interposed between the RF die and the SoC die. A top package is mounted on the interposer. 1. A semiconductor package , comprising:a bottom package comprising a substrate, an radio-frequency (RF) die and a system-on-a-chip (SoC) die arranged on said substrate in a side-by-side manner, a molding compound covering said RF die and said SoC die, and an interposer over said molding compound;a plurality of connection elements disposed on a top surface of said substrate, wherein said plurality of connection elements surrounds said SoC die;a column of signal interference shielding elements interposed between said RF die and said SoC die; anda top package mounted on the interposer.2. The semiconductor package according to claim 1 , wherein said top package is a memory package.3. The semiconductor package according to claim 2 , wherein said memory package is a dynamic random access memory (DRAM) package having at least one encapsulated DRAM die.4. The semiconductor package according to claim 1 , wherein said RF die is a millimeter wave (mmw) intermediate-frequency (IF) RF die.5. The semiconductor package according to claim 1 , wherein said plurality of connection elements comprise Cu/Sn balls claim 1 , Cu pillars claim 1 , Cu bumps claim 1 , Cu vias claim 1 , or through mold vias.6. The semiconductor package according to claim 1 , wherein said plurality of connection elements and said column of signal interference shielding elements are surrounded by the molding ...

Semiconductor device having a boundary structure, a package on package structure, and a method of making

A semiconductor device includes a substrate and a first conductive pad on a top surface of the substrate. The semiconductor device further includes a boundary structure on the top surface of the substrate around the conductive pad.

BALL GRID ARRAY (BGA) APPARATUS AND METHODS

Embodiments herein may relate to an apparatus with a ball grid array (BGA) package that includes a plurality of solder balls of an off-eutectic material. In embodiments, the respective solder balls of the plurality of solder balls may form solder joints between a substrate of the BGA and a second substrate. In some embodiments the joints may be less than approximately micrometers from one another. Other embodiments may be described and/or claimed. 1. An apparatus comprising:a first substrate; anda ball grid array (BGA) package that includes a second substrate soldered to the first substrate via a plurality of solder balls comprising an off-eutectic material such that respective solder balls of the plurality of solder balls form respective joints between the first substrate and the second substrate, wherein a first joint of the respective joints is less than 0.6 micrometers from a second joint of the respective joints.2. The apparatus of claim 1 , wherein the off-eutectic material includes tin (Sn) and bismuth (Bi).3. The apparatus of claim 1 , wherein the first joint is an interior joint and a third joint of the respective joints is an edge joint claim 1 , and the first joint and third joint have an approximately equal height as measured from the first substrate to the second substrate.4. The apparatus of claim 3 , wherein the height of the first joint is greater than or equal to a height of one of the plurality of solder balls prior to a soldering process.5. The apparatus of claim 1 , wherein the off-eutectic material has a solidus temperature and a liquidus temperature that is higher than the solidus temperature.6. The apparatus of claim 5 , wherein the solidus temperature is a temperature at which the off-eutectic material transitions from a liquid to a solid while cooling.7. The apparatus of claim 6 , wherein the solidus temperature is between approximately 135 degrees Celsius and approximately 145 degrees Celsius.8. The apparatus of claim 5 , wherein the ...

System on package

A system on package includes a first package and a second package stacked on the first package and electrically connected to one another through metal contacts. The first package includes a first printed circuit board (PCB), a system on chip which is connected to the first PCB through bumps, and a first memory device which is connected to the system on chip through micro bumps connected to vias in the system on chip. The second package includes a second PCB, a second memory device connected to the second PCB, a third memory device connected to the second PCB, and a memory controller which is connected to the second PCB and controls the third memory device.

Semiconductor package and method of fabricating the same

Disclosed are a semiconductor package and a method of fabricating the same. The semiconductor package comprises a lower semiconductor chip on a lower substrate, a lower molding layer covering the lower semiconductor chip on the lower substrate and including a molding cavity that extends toward the lower semiconductor chip from a top surface of the lower molding layer, an interposer substrate on the top surface of the lower molding layer and including a substrate opening that penetrates the interposer substrate and overlaps the molding cavity, and an upper package on the interposer substrate. The molding cavity has a floor surface spaced apart from the upper package across a substantially hollow space.

Semiconductor Device and Method of Forming a POP Device with Embedded Vertical Interconnect Units

A semiconductor device has a substrate. A plurality of conductive vias is formed through the substrate. A conductive layer is formed over the substrate. An insulating layer is formed over conductive layer. A portion of the substrate is removed to expose the conductive vias. A plurality of vertical interconnect structures is formed over the substrate. A first semiconductor die is disposed over the substrate. A height of the vertical interconnect structures is less than a height of the first semiconductor die. An encapsulant is deposited over the first semiconductor die and the vertical interconnect structures. A first portion of the encapsulant is removed from over the first semiconductor die while leaving a second portion of the encapsulant over the vertical interconnect structures. The second portion of the encapsulant is removed to expose the vertical interconnect structures. A second semiconductor die is disposed over the first semiconductor die. 1. A semiconductor device , comprising:a substrate including a conductive via formed through the substrate;a modular interconnect unit including a vertical interconnect structure disposed over the substrate;a first semiconductor die disposed over the substrate adjacent to the modular interconnect unit; andan encapsulant deposited around the first semiconductor die and over modular interconnect unit with an opening in the encapsulant extending to the modular interconnect unit.2. The semiconductor device of claim 1 , further including a second semiconductor die disposed over the first semiconductor die with a bump of the second semiconductor die within the opening of the encapsulant to contact the vertical interconnect structure.3. The semiconductor device of claim 1 , further including a first interconnect structure disposed between the substrate and modular interconnect unit.4. The semiconductor device of claim 3 , further including a second interconnect structure disposed between the first interconnect structure and ...

Scalable semiconductor interposer integration

An electronic package including a first substrate, a second substrate, a first standoff substrate, and a second standoff substrate. A clearance is formed between the first standoff substrate, the second standoff substrate, the first substrate, and the second substrate. The first standoff substrate comprises an intervening plurality of TSVs passing through an entire thickness of the first standoff substrate. The second standoff substrate comprises an intervening plurality of TSVs passing through an entire thickness of the second standoff substrate. A portion of the second plurality of TSVs are electrically connected to a portion of the first TSVs by way of a portion of the intervening TSVs. A first electronic component disposed within the clearance and electrically coupled to the first substrate by a first plurality of electrical connections. A second electronic component disposed within the clearance and electrically coupled to one of the first substrate or the second substrate. The first electronic component and the second electronic component are spaced apart from one another.

Package-on-Package Structure with Through Molding Via

Disclosed herein is a device comprising a first package having a first side with a plurality of connectors disposed thereon and a second package mounted on the first package by the connectors. A molding compound is disposed on the first side of the first package and between the first package and the second package. A plurality of stress relief structures (SRSs) are disposed in the molding compound, the plurality of SRSs each comprising a cavity free of metal in the molding compound and spaced apart from each of the plurality of connectors.

SEMICONDUCTOR CHIP

A semiconductor chip includes a semiconductor substrate including a bump region and a non-bump region, a bump on the bump region, and a passivation layer on the bump region and the non-bump region of the semiconductor substrate. No bump is on the non-bump region. A thickness of the passivation layer in the bump region is thicker than a thickness of the passivation layer in the non-bump region. The passivation layer includes a step between the bump region and the non-bump region. 1. A semiconductor package comprising:a semiconductor substrate including a bump region, a non-bump region, a redistribution wiring region, and a dummy region between the bump region and the non-bump region;a redistribution wiring pattern on the redistribution wiring region;a dummy pattern on the dummy region;a bump on the bump region, a via extending through the semiconductor substrate in bump region, the non-bump region having no bump;a passivation layer on the bump region, the dummy region, and the non-bump region of the semiconductor substrate; anda plurality of chips on the semiconductor substrate, at least two chips of the plurality of the chips being stacked on the semiconductor substrate,a thickness of the passivation layer at the bump region being thicker than a thickness of the passivation layer at the non-bump region,the passivation layer covering the dummy pattern and insulating the dummy pattern, andthe passivation layer including a step between the bump and redistribution wiring regions and the non-bump region, the step defined by an upper surface of the passivation layer at a portion of the passivation layer that protrudes upward over a boundary between the dummy region and the non-bump region.2. The semiconductor package of claim 1 , wherein the semiconductor substrate comprises an interposer substrate.3. The semiconductor package of claim 1 , wherein the at least two chips being stacked include memory chips electrically connected each other by a chip via.4. The semiconductor ...

PACKAGE DEVICES HAVING A BALL GRID ARRAY WITH SIDE WALL CONTACT PADS

Package devices (systems and methods for their manufacture) may have an integrated circuit (IC) chip mounted on a top surface of a package substrate of and IC package, and embedded in a mold compound formed onto the top surface. They may also have conductive elements mounted on the top surface of the package substrate, embedded in the mold compound, horizontally disposed at a first vertical sidewall of the package device, and having vertical contact pads exposed at the first vertical sidewall. Conductor material traces of the IC package may electrically couple contacts of the chip to the conductive elements. Traces of the IC package may also electrically couple contacts of the chip to bottom surface contacts of the IC package. The vertical contact pads provide a shorter signal path to another device having vertically mounted surface contacts or opposing contact pads, thus improving signaling to the other device. 1. A package device comprising:a package having a substrate with a top surface;a chip mounted on the top surface of the substrate;a mold compound embedding the chip and formed onto the top surface of the package;a plurality of conductive elements mounted on the top surface of the substrate, the conductive elements horizontally disposed at a first vertical sidewall of the package device and having vertical contact pads exposed at the first vertical sidewall; anda plurality of conductor material traces electrically coupling bottom surface contacts of the chip to the plurality of conductive elements.2. The package device of further comprising:a first bottom surface with first bottom surface contacts; andconductive traces and vias electrically coupling bottom surface contacts of the chip to the first bottom surface contacts;a plurality of conductor material bumps physically attaching and electrically coupling bottom surface contacts of the chip to the plurality of conductor material traces; andthe mold compound formed over and around sides of the chip; over and ...

PACKAGE STRUCTURE AND METHODS OF FORMING THE SAME

Embodiments relate to packages and methods of forming packages. A package includes a package substrate, a first device die, first electrical connectors, an encapsulant, a redistribution structure, and a second device die. The first device die is attached to a side of the package substrate, and the first electrical connectors are mechanically and electrically coupled to the side of the package substrate. The encapsulant at least laterally encapsulates the first electrical connectors and the first device die. The redistribution structure is on the encapsulant and the first electrical connectors. The redistribution structure is directly coupled to the first electrical connectors. The first device die is disposed between the redistribution structure and the package substrate. The second device die is attached to the redistribution structure by second electrical connectors, and the second electrical connectors are directly coupled to the redistribution structure. 1. A package comprising:a first redistribution structure disposed on a front side of a substrate;a first semiconductor device disposed on the first redistribution structure, the first semiconductor device electrically connected to the first redistribution structure;a first encapsulant laterally surrounding the first semiconductor device;a second redistribution structure over and physically contacting a top surface of the first semiconductor device;an electrical connector extending through the first encapsulant from the first redistribution structure to the second redistribution structure, wherein a top surface of the electrical connector is level with the top surface of the first semiconductor device; anda second semiconductor device disposed on the second redistribution structure, the second semiconductor device electrically connected to the second redistribution structure.2. The package of claim 1 , further comprising a third semiconductor device disposed on the second redistribution structure claim 1 , the ...

FLIP CHIP ASSEMBLY PROCESS FOR ULTRA THIN SUBSTRATE AND PACKAGE ON PACKAGE ASSEMBLY

In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including receiving a coreless substrate strip, attaching solder balls to a backside of the coreless substrate strip, and forming a backside stiffening mold amongst the solder balls. Other embodiments are also disclosed and claimed. 1. An apparatus comprising:a coreless substrate strip;a plurality of solder balls attached to a backside of the coreless substrate strip; anda backside stiffening mold amongst the solder balls.2. The apparatus of claim 1 , wherein the backside stiffening mold comprises a height of about 200 micrometers.3. The apparatus of claim 1 , wherein the coreless substrate strip comprises a height of about 200 micrometers.4. The apparatus of claim 3 , further comprising an integrated circuit device attached to a topside of the coreless substrate strip.5. An apparatus comprising:a direct laser lamination generation 3 (DLL3) substrate strip;a plurality of solder balls attached to a backside of the DLL3 substrate strip;a backside stiffening mold amongst the solder balls; andan integrated circuit device attached to a topside of the DLL3 substrate strip.6. The apparatus of claim 5 , wherein the backside stiffening mold comprises a height of about 200 micrometers.7. The apparatus of claim 5 , wherein the DLL3 substrate strip comprises a height of about 200 micrometers.8. The apparatus of claim 5 , wherein the solder balls comprise a diameter of about 10 mils.9. The apparatus of claim 5 , further comprising a second integrated circuit device package attached to the topside of the DLL3 substrate strip.10. An apparatus comprising:a coreless substrate strip, including topside contacts adapted for attachment to an integrated circuit device, and backside contacts formed at a pitch larger than the topside contacts;a plurality of solder balls attached to a backside of the coreless substrate strip; anda backside stiffening mold amongst ...

Stacked semiconductor package

A stacked semiconductor package including a first printed circuit board and a second printed circuit board is provided. The first printed circuit board may include a first surface upon which a first semiconductor chip is mounted and a second surface upon which at least one connecting structure is attached. The first printed circuit board may further include at least one thermal via and a heat sink and the at least one thermal via and the heat sink may be disposed under the first semiconductor chip with the heat sink being disposed between the first surface and the second surface. The second printed circuit board may include a third surface upon which a second semiconductor chip is mounted. The second printed circuit board may be disposed under the first printed circuit board with the at least one connecting structure connecting the first printed circuit board to the second printed circuit board.

Semiconductor device and fabrication method therefore

Various embodiments of the present invention include a semiconductor device and a fabrication method therefore, the semiconductor device including a first semiconductor chip disposed on a substrate, a first sealing resin sealing the first semiconductor chip, a built-in semiconductor device disposed on the first sealing resin, and a second sealing resin sealing the first sealing resin and the built-in semiconductor device and covering a side surface of the substrate. According to an aspect of the present invention, it is possible to provide a high-quality semiconductor device and a fabrication method therefore, in which downsizing and cost reduction can be realized.

Package on package structure and method of manufacturing the same

A package on package structure includes a first substrate having a first region and a second region, a bump formed on the first region of the first substrate, a first semiconductor die bonded to the second region of the first substrate, and a semiconductor die package bonded to the first substrate. The bump includes a metallic structure and a plurality of minor elements dispersed in the metallic structure. The semiconductor die package includes a connector bonded to the bump, and the first semiconductor die is between the semiconductor die package and the first substrate.

Semiconductor package having wafer-level active die and external die mount

Semiconductor packages and package assemblies having active dies and external die mounts on a silicon wafer, and methods of fabricating such semiconductor packages and package assemblies, are described. In an example, a semiconductor package assembly includes a semiconductor package having an active die attached to a silicon wafer by a first solder bump. A second solder bump is on the silicon wafer laterally outward from the active die to provide a mount for an external die. An epoxy layer may surround the active die and cover the silicon wafer. A hole may extend through the epoxy layer above the second solder bump to expose the second solder bump through the hole. Accordingly, an external memory die can be connected directly to the second solder bump on the silicon wafer through the hole.

Stack-type semiconductor package

According to example embodiments, a stack-type semiconductor package includes a lower semiconductor package, an upper semiconductor package, connection pads, and a metal layer pattern. The lower semiconductor package includes a lower semiconductor chip on a top surface of a lower package substrate, lower lands on the lower package substrate, and an encapsulant on the top surface of the lower package substrate. The encapsulant defines via holes that expose the lower lands. The upper semiconductor package is on the encapsulant. Upper solder balls are connected to a bottom surface of the upper semiconductor package. The connection pads are on the via holes and the encapsulant. The connection pads electrically connect the lower semiconductor package to the upper semiconductor package. The metal layer pattern is between the lower package substrate and the upper semiconductor package. The metal layer pattern surrounds the connection pads and is isolated from the connection pads.

Semiconductor packages including a plurality of upper semiconductor devices on a lower semiconductor device

Semiconductor packages are provided. The semiconductor packages may include an upper package including a plurality of upper semiconductor devices connected to an upper package substrate. The semiconductor packages may also include a lower package including a lower semiconductor device connected to a lower package substrate. The upper and lower packages may be connected to each other.

Semiconductor package

A semiconductor package including: a first substrate including a first surface including a first region and a second region at least partially surrounding the first region, wherein the first substrate includes a first insulating layer, a first conductive pattern in the first insulating layer, a first passivation layer disposed in the first region and the second region, and a second passivation layer disposed on the first passivation layer in the second region; an interposer overlapping the first substrate and including a second insulating layer and a second conductive pattern in the second insulating layer; a first connection terminal disposed on the first passivation layer in the first region; and a second connection terminal disposed on the second passivation layer in the second region, wherein the first conductive pattern and the second conductive pattern are connected to each other through the first connection terminal and the second connection terminal.

"Lead-Free Solder Ball"

A lead-free solder ball is provided which suppresses interfacial peeling in a bonding interface of a solder ball, fusion defects which develop between the solder ball and solder paste, and which can be used both with Ni electrodes plated with Au or the like and Cu electrodes having a water-soluble preflux applied atop Cu. The lead-free solder ball for electrodes of BGAs or CSPs consists of 1.6-2.9 mass % of Ag, 0.7-0.8 mass % of Cu, 0.05-0.08 mass % of Ni, and a remainder of Sn. It has excellent resistance to thermal fatigue and to drop impacts regardless of the type of electrodes of a printed circuit board to which it is bonded, which are Cu electrodes or Ni electrodes having Au plating or Au/Pd plating as surface treatment. 1. A lead-free solder ball which is installed for use as an electrode on a rear surface of a module substrate for a BGA or a CSP and which is fused with a solder paste , the solder ball having a solder composition consisting of:1.6-2.9 mass % of Ag;0.7-0.8 mass % of Cu;0.05-0.08 mass % of Ni; at least one of Fe and Co in a total amount of 0.003-0.1 mass %; and', 'Ge in a total amount of 0.003-0.1 mass %; and, 'at least one ofa remainder of Sn.2. The lead-free solder ball as set forth in claim 1 , wherein the solder composition consists of:1.6-2.9 mass % of Ag;0.7-0.8 mass % of Cu;0.05-0.08 mass % of Ni;at least one of Fe and Co in a total amount of 0.003-0.1 mass %; anda remainder of Sn.3. The lead-free solder ball as set forth in claim 1 , wherein the solder composition consists of:1.6-2.9 mass % of Ag;0.7-0.8 mass % of Cu;0.05-0.08 mass % of Ni;Ge in a total amount of 0.003-0.1 mass %; anda remainder of Sn.4. The lead-free solder ball as set forth in claim 1 , wherein the solder composition consists of:1.6-2.9 mass % of Ag;0.7-0.8 mass % of Cu;0.05-0.08 mass % of Ni;at least one of Fe and Co in a total amount of 0.003-0.1 mass %;Ge in a total amount of 0.003-0.1 mass %; anda remainder of Sn.5. The lead-free solder ball as set forth in claim 1 ...

MULTI-DIE MEMORY DEVICE

A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and includes first and second memory arrays. The first memory array couples to the first memory interface circuit. The second memory array couples to the second interface circuit. A second memory die is stacked with the logic die and the first memory die. The second memory die includes third and fourth memory arrays. The third memory array couples to the first memory interface circuit. The fourth memory array couples to the second memory interface circuit. Accesses to the first and third memory arrays are carried out independently from accesses to the second and fourth memory arrays.

Packaged integrated circuit device with cantilever structure

Techniques and mechanisms to facilitate connection with one or more integrated circuit (IC) dies of a packaged device. In an embodiment, the packaged device includes a first substrate coupled to a first side of a package, and a second substrate coupled to a second side of the package opposite the first side. Circuitry, coupled via the first substrate to one or more IC dies disposed in the package, includes a circuit structure disposed at a cantilever portion of the first substrate. The cantilever portion extends past one or both of an edge of the first side and an edge of the second side. In another embodiment, a hardware interface disposed on the second substrate enables coupling of the packaged device to another device.