Elektrischer Messfühler mit geformten Kontakten

Semi-additive elektrische Schaltungen mit erhöhten Einzelheiten unter Verwendung geformter Matrizen

Elektronische Vorrichtung mit einem elektrisch leitenden Klebstoff.

VERFAHREN ZUM HERSTELLEN EINER ELEKTRISCHEN VERBINDUNG UND VERBINDER ZUR DURCHFUEHRUNG DES VERFAHRENS

Polymer Stud Grid Array und Verfahren zur Herstellung eines derartigen Polymer Stud Grid Arrays

Auf einem Substrat (S) werden eine erste Verdrahtungslage (V1) und metallisierte Durchkontaktierungslöcher (D) gebildet. Auf die Oberseite (O1) des Substrats (S) wird dann durch Spritzgießen eine Substratlage (SL) aufgebracht, wobei das Material durch die Durchkontaktierungslöcher (D) hindurchtritt und auf der Unterseite (U) des Substrats (S) Polymerhöcker (PS) entstehen. Eine auf der Substratlage (SL) gebildete zweite Verdrahtungslage (V2) ist über Sackloch-Durchkontaktierungen (SD) mit der ersten Verdrahtungslage (V1) und damit über die Durchkontaktierungslöcher (D) mit Außenanschlüssen (AA) auf den Polymerhöckern (PS) elektrisch leitend verbunden.

PRINTED CIRCUIT CARD

... 1,221,968. Printed circuit assemblies. INTERNATIONAL BUSINESS MACHINES CORP. 17 April, 1968 [8 May, 1967], No. 18052/68. Heading H1R. [Also in Division H2] Electrical connection between two electrically conductive coatings 46, 48, Fig. 3, on a dielectric base 47 is produced by providing in one coating conical members 53 which project through holes in the base 47 and corresponding conical members in the second coating which fit over the first said members. Such connections are produced by depositing a conducting layer (72), Fig. 2b (not shown), of e.g. copper, on a steel former (70) having raised conical projections (71), and then assembling a prepunched dielectric layer (73), e.g. of epoxy or silicone glass, a further conducting layer (74), e.g. of copper, provided with conical members (76), on the deposited conducting layer. The various layers are then laminated together by heat and pressure and thereafter removed from the former. To ensure good electrical connections, solder may be provided ...

Integral copper column withsolder bump flip-chip

A method of making an inkjet printhead

A method of making an inkjet printhead for surface mounting comprises providing a substrate 10 having a plurality of ink ejection elements and a plurality of electrical contacts 18 formed on a first surface, the contacts being connected to the ink ejection elements to allow selective energisation of the elements. A plurality of through-holes 26 are formed in the substrate each extending from the opposite surface of the substrate fully through the thickness of the substrate to meet the underside of a respective electrical contact 18 on the first surface. Each through-hole is substantially completely filled with a conductive material 36 by electroplating. Finally, a further plurality of electrical contacts (solder mounds) 38 are provided on the second surface of the substrate each in contact with the conductive material in a respective through-hole.

Improvements in or relating to electric apparatus

... 524,433. Casting electric components. PHILIPS LAMPS, Ltd. Sept. 7, 1939, No. 25267. Convention date, Sept. 6, 1938. [Class 83 (i)] [Also in Groups V and XXXVI] Casting composite articles. - Radio - receiving or other electrical apparatus having a conductor system 2 die-cast as in Specification 515,354, wherein a member 5 integral with the system forms a stationary electrode of a condenser which can be adjusted by means of members not cast with the system. The movable electrode 4 screws on a shaft 7 in a ceramic sleeve 6 which is placed in position before casting the electrode 5. An electrode 4 and a shaft 7 for use in a subsequently cast conductor system, may be die-cast at the same time in another part of the mould. Contact between the shaft 7 and the electrode 4 is maintained by a spring 81. In a modification both electrodes 17, 18, Fig. 5, are stationary the adjustment being made by moving a rod 21 of a dielectric such as titanium-dioxide ceramic with or without an embedded ...

ELECTRICAL CONNECTOR

An electrical edge connector is provided with an insulating body accommodating spring contacts 2, 3 for engaging dome-shaped contacts 9, 10 of a printed circuit board 8. The body has a board-receiving opening the size and/or configuration of which is determined by the provision of spaced fingers at the opening so as to prevent the insertion of a board having raised contacts not of a predetermined size, form or spacing or to allow insertion of a board having conventional contact strips but to prevent the engagement of such contacts strips with the spring contacts within the connector body. ...

Process for manufacturing panels to be used in microelectronic systems

Conductors of desired shape are formed on a substrate (1) made from a metal that is selectively etchable with respect to the metal of the conductors. The conductors (3,5,6) are formed on both sides of the substrate and the conductors (3) have at least one constricted portion (4) on the side of the substrate opposite to that on which a base (7) will be laminated. The panel base (7) is laminated onto the appropriate side of the substrate (1), and the substrate metal is etched selectively with respect to the conductor metal through the entire thickness of the substrate until the metal of the latter is fully removed from under the constricted portions (4) only. ...

Circuit board assembly with discrete conductive adhesive regions

A circuit board assembly comprises: a substrate 5; a set of contact pads 6; and a plurality of discrete conductive adhesive regions disposed on the contact pads 6 and the substrate 5 such that at least one adhesive regions are disposed on and between the contact pads 6. Also disclosed is a device or module with the same features as said circuit board; and a method of providing the above circuit board assembly 1. The substrates 5 may be flexible or rigid and formed of paper, card, cardboard or plastic. The contact pads 6 may be formed of conductive ink or conductive foil. The discrete conductive adhesive regions may be formed of conductive ink, glue or tape. The discrete conductive adhesive regions may further be arranged in an array, either rectangular or hexagonal, or in a random pattern. The spacing between the contact pads 6 may be more than the maximum extent (width) of the adhesive regions, such that the adhesive regions do not create a short circuit between the contact pads 6. The ...

ELECTRONIC BUILDING GROUP

PRODUCTION A COUNTRY OF A GRID ARRAY OF MEANS ELASTOMER CORE AND DIRECTION METAL COVERING OR - LATTICES

VERBINDUNGSSYSTEM

ZWEI- ODER MEHRLAGIGE LEITERPLATTE, VERFAHREN ZUM HERSTELLEN EINER SOLCHEN LEITERPLATTE UND LAMINAT FÜR DIE HERSTELLUNG EINER SOLCHEN LEITERPLATTE NACH EINEM SOLCHEN VERFAHREN

TWO OR MULTI-LAYER PRINTED CIRCUIT BOARD, PROCEDURE FOR MANUFACTURING A SUCH A PRINTED CIRCUIT BOARD AND LAMINATE FOR THE PRODUCTION OF SUCH A PRINTED CIRCUIT BOARD IN SUCH PROCEDURES

ELEMENT ARRANGEMENT WITH STARING SUBSTRATE.

ARRANGEMENT FOR THE CONNECTION OF EACH OTHER GEGENUBERLIEGENDEN ELECTRICAL LEADERS AND PROCEDURE FOR THEIR PRODUCTION

MANUFACTURING PROCESS FOR A PROBE MAP WITH SEVERAL EDGE CONTACTS FOR THE EXAMINATION OF INTEGRATED CIRCUITS WITH BALL MATRIX PACKING (BGA)

PROCEDURE FOR THE PRODUCTION OF A SMART CARD AND AFTER THE PROCEDURE MANUFACTURED SMART CARD

Method for producing a chip card and chip card produced according to said method

A PROCESS FOR THE PRODUCTION OF PRINTED CIRCUITS PROVIDED WITH CONTACT SURFACES

ELECTRICAL CONNECTORS

Grid interposer

Method and materials for printing particle-enhanced electrical contacts

DENDRITIC ELECTRICAL CONTACTS AND CONNECTORS

DENDRITIC ELECTRICAL CONTACTS AND CONNECTORS An electrical contact is provided by forming on a contact pad or contact surface a bunch of tiny resilient metal projections by a dendritic growth thereon of conductive metal crystals. A separable or disconnectable electrical connection is provided by urging the dendritic projections on mating contacts into intermeshing or interwedging engagement. Good quality submillimeter size electrical contacts are readily fabricated and are particularly useful for providing low cost spaceefficient multipoint connector systems for large-scale integration (LSI) circuit modules, printed circuit cards and boards and other modern day electronics hardware.

Electrical Interconnection Method and Apparatus Utilizing Raised Connecting Means

HIGH DENSITY ELECTRICAL CONNECTORS

The present invention relates to self-aligned, flexible high density and impedance adjusted electrical connectors used in microelectronic systems. This invention solves the problem of having electrical connection and alignment at the same time. One connector (200) having a first part (204) consists of two metal layer structures, a first signal path (212) and a first ground path (210), covering the V-groove (202). The connector also has a second part (208) consisting of corresponding metal layers, a second signal path (224) covering the elastic bump (206) and a second signal ground plane (226), which fits into the V-groove (202). The first and the second signal path (212, 224) are in contact with each other when the first and the second part (204, 208) are brought together. The contact is self-aligned when put together. The electrical contact will remain even if displaced due to the thermal expansion.

Elektrischer Apparat.

Elektrischer Apparat.

Base part of an electromagnetic switchgear, in particular a contactor.

Spektroskopiemodul und Verfahren zu dessen Herstellung.

Ein Spektroskopiemodul beinhaltet einen Trägerkörper (10) mit einem Bodenwandbereich und einem Seitenwandbereich, umgebend einen Raum auf einer Seite des Bodenwandbereichs, einen Spektroskopiebereich, der auf der einen Seite des Bodenwandbereichs vorgesehen ist und eine Vielzahl von Gitterrillen aufweist, einen Photodetektor, der an dem Seitenwandbereich angebracht ist, um so zum Spektroskopiebereich über den Raum zu weisen und eine Vielzahl von Photodetektionskanälen aufweist, eine Vielzahl erster Anschlüsse, die auf einer Oberfläche des Trägerkörpers auf einer Seite entgegengesetzt zu dem Raum vorgesehen sind, um so längs der Oberfläche des Trägerkörpers angeordnet und mit dem Photodetektor elektrisch verbunden zu sein, und eine Verdrahtungseinheit (200), die eine Vielzahl von zweiten Anschlüssen aufweist, die jeweils zur Vielzahl von ersten Anschlüssen weisen und jeweils mit der Vielzahl von ersten Anschlüssen verbunden sind, und eine Vielzahl von dritten Anschlüssen (203), die jeweils ...

CONTACT UNIT

Wiring board and manufacturing method thereof

Method for manufacturing touch-panel conductive sheet, and touch-panel conductive sheet

A method for forming a metal contact on a semiconductor device

MICROSYSTEM FOR BIOLOGICAL ANALYSES AND ITS MANUFACTORING PROCESS

PROCESS Of ASSEMBLY Of a MICROCIRCUIT ON a PLASTIC SUPPORT

METHOD OF MANUFACTURING A WAFER HOLDING CONDUCTOR PATTERNS UPON TWO OPPOSITE FACES ELECTROCHEMICAL PRODUCTION OF SUBSTITUTED PYRIDINES

TETE D'INSCRIPTION ELECTROSTATIQUE

TETE D'INSCRIPTION ELECTROSTATIQUE FORMEE PAR UNE PLATINE ISOLANTE MUNIE DE PISTES CONDUCTRICES QUI COMPORTENT DES TRONCONS TERMINAUX A PARTIES PLUS EPAISSES SERVANT D'ELECTRODES D'INSCRIPTION, SITUES DANS UNE REGION EN FORME DE BANDE QUI S'ETEND SUR LA PARTIE CENTRALE DE LA PLATINE ET PARALLELES A LA DIRECTION LONGITUDINALE DE LADITE REGION. LES TRONCONS TERMINAUX DIRECTEMENT VOISINS DESDITES PISTES CONDUCTRICES SE PROLONGENT DANS DES PISTES CONDUCTRICES ORIENTEES DANS DEUX DIRECTIONS OPPOSEES ET UNE COUCHE ISOLANTE COUVRE LESDITS TRONCONS TERMINAUX MAIS LAISSE A DECOUVERT LEURS PARTIES EPAISSIES. APPLICATION AUX APPAREILS D'ENREGISTREMENT ETOU DE REPRODUCTION D'INFORMATION.

Improvements with the electricals appliance such as the receivers of t.s.f.

INTERCONNECTION METHOD BY EVERTING AN ELECTRONIC COMPONENT

Improvements with the electricals appliance, such as the receivers of t.s.f.

METHOD FOR PRODUCING A PRINTED CIRCUIT AND PRINTED CIRCUIT OBTAINED BY CARRYING OUT SAID METHOD

METHOD FOR MAKING A MULTI-LAYER CIRCUIT TO ELECTRIC POWER DISTRIBUTION

Procédé de fabrication d'un circuit (1) multicouche de distribution de courant électrique comprenant la fabrication d'une succession de plaques (2) conductrices destinées à être empilées, la mise en place d'une couche (3) isolante électriquement entre les plaques conductrices que l'on empile, ces dites plaques conductrices présentant des zones (5) de contacts destinées à établir une connexion avec un composant ce procédé étant caractérisé en ce que localement au droit des zones de contact on projette dynamiquement à vitesse supersonique et par gaz sous pression et au travers d'une tuyère convergente divergente sur ces zones de contact une poudre conductrice dont les particules de ladite poudre vont lors de l'impact se déformer plastiquement, s'agglomérer et s'incruster dans la surface, au niveau de la zone de contact, et créer ainsi une couche conductrice électrique et protectrice vis-à-vis de l'atmosphère ambiante.

METHOD FOR PRODUCING A FLAT CONNECTION

COMPONENT HAS CONDUCTING DUCTILE ENTERREES AND PROCEEDED PROTUBERANCES ELECTRIC DISCONNECTION BETWEEN THIS COMPONENT AND A COMPONENT PROVIDED WITH HARD POINTESCONDUCTRICES

L'invention concerne un procédé de connexion électrique entre un premier composant (10) comportant, sur une face, un ensemble de premiers plots (8) et un ensemble de pointes conductrices dures (13) et un second composant (11) comportant, sur une face, un ensemble de second plots (9) et un ensemble de protubérances conductrices ductiles (14), dans lequel on met en vis-à-vis les deux faces et on les rapproche de telle façon que les pointes (13) puissent pénétrer dans ces protubérances (14), dans lequel les protubérances sont enterrées. L'invention concerne également un composant muni d'un ensemble de protubérances conductrices ductiles enterrées.

ELECTROSTATIC HEAD Of INSCRIPTION

DEVICE OF ELECTRICAL CONTACT ELASTIC OR DEPASSIVANT WITHOUT RISE IN TEMPERATURE.

La présente invention est destinée à l'amélioration et à la définition de nouvelles méthodes de connexions électriques entre divers éléments (par exemple entre un boîtier comprenant une puce à semi-conducteur et un circuit imprimé), ou à l'amélioration de la prise de contact électrique (par exemple, accès électrique à l'aide d'une pointe (8) sur un plot de contact (4) appartenant à un circuit imprimé (2) en vue de son test) en compatibilité avec les méthodes industrielles actuelles de fabrication.Le dispositif utilise des matériaux polymères conducteurs (1) (là conductivité métallique) ayant entre autres comme caractéristiques une élasticité sensible ainsi que des propriétés dépassivantes, à température ambiante, et sur la gamme industrielle de température, facilitant l'établissement du contact électrique. Un moyen de compression est utilisé pour maintenir au contact les deux sous-ensembles à interconnecter; ...

METHOD AND APPARATUS FOR MEASURING SHAPE OF BUMPS

부품 실장 기판

... 층간 접속 도체(20)는 적층체(10)의 제 1 층(1~6)까지를 관통하고, 상면(10S)으로부터 돌출되어 있다. 부품 실장 기판(200)에서는 적층방향에 있어서, 상면(10S)으로부터의 층간 접속 도체(20)의 돌출 길이는 적층방향에 있어서의 층간 접속 도체(20) 및 도전 접합부(112)의 접속 위치와, 접속 전극(30) 및 도전 접합부(122)의 접속 위치의 차가 차분(d1)이 되도록 조정되어 있다. 적층방향에 있어서의 도전 접합부(112)의 길이와 도전 접합부(122)의 길이의 차분(d2)은 이 차분(d1)에 의해 상쇄된다. 그 결과, 상면(10S)과 하면(101S)이 평행하게 됨으로써 실장 기판(90)에 대한 고주파 부품(100)의 경사를 방지하고, 상기 경사에 기인하는 전기 접속의 불량 및 접합 강도의 저하를 방지할 수 있다.

CONTACTING COMPONENT, METHOD OF PRODUCING THE SAME, AND TEST TOOL HAVING THE CONTACTING COMPONENT

이미다졸 및 비스에폭사이드 화합물의 반응 산물을 함유하는 구리 전기도금조로부터 포토레지스트 정의된 특징부의 전기도금 방법

... 전기도금 방법은 실질적으로 균일한 형태를 갖는 포토레지스트 정의된 특징부의 도금을 가능케 한다. 전기도금 방법에는 포토레지스트 정의된 특징부를 전기도금하기 위해 이미다졸 및 비스에폭사이드의 반응 산물을 포함하는 구리 전기도금조가 포함된다. 이러한 특징부에는 기둥, 결합 패드 및 라인 스페이스 특징부가 포함된다.

FLEXIBLE PRINTED CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF

Provided is a flexible printed circuit board according to an embodiment of the present invention. The flexible printed circuit board includes a first flexible substrate, a pad disposed on the first flexible substrate, and a guide structure disposed along at least a part of the pad to guide a second flexible substrate electrically connected through the pad. According to the present invention, provided is the flexible printed circuit board capable of aligning two flexible printed circuit boards with higher precision without using an optical method and reducing a defective rate and a working time. COPYRIGHT KIPO 2017 ...

PRINTED WIRING BOARD, A SEMICONDUCTOR PACKAGE, AND A MANUFACTURING METHOD THEREOF, CAPABLE OF PREVENTING DAMAGE TO A SOLDER BUMP OF A SEMICONDUCTOR CHIP

PURPOSE: A printed wiring board, a semiconductor package, and a manufacturing method thereof are provided to suppress breakdown of a solder bump by uniformly distributing mechanical stress into a connection pad and an under bump metal. CONSTITUTION: A printed wiring board comprises a dielectric layer(26a) and a connection pad(24). A dielectric layer has a main surface. A connection pad is buried in the dielectric layer. The connection pad includes a plate part(36) and a contact part(38). The plate part has a front side and a rear side. The contact part is positioned on the front side of the plate part. The main surface of the contact part is exposed to the main surface of the dielectric layer. COPYRIGHT KIPO 2010 ...

PRINTED CIRCUIT BOARD WITH AN INSULATED METAL SUBSTRATE

Printed circuit board and method for manufacturing the same

METHOD OF ELECTROPLATING PHOTORESIST DEFINED FEATURES FROM COPPER ELECTROPLATING BATHS CONTAINING REACTION PRODUCTS OF ALPHA AMINO ACIDS AND BISEPOXDES

Package substrate and fabrication method thereof

Provided is a package substrate and fabrication method thereof, and the package substrate comprises a first dielectric layer, a first circuit layer, a first metal bump and a buildup structure. The first metal bump and the first circuit layer are, respectively, embedded in and exposed from two surfaces of the first dielectric layer, wherein one end of the first metal bump is embedded into the first circuit layer, and a electrically conductive layer is disposed between the first circuit layer and the first dielectric layer and between the first circuit layer and the first metal bump. The buildup structure is disposed above the first circuit layer and the first dielectric layer, and the outmost layer of the buildup structure is provided with a plurality of electrical contact pads. Compared to prior arts, this application can effectively improve the problem of a conventional a package substrate being excessively wrapped.

Routing material and manufacturing method thereof

The present invention relates to a manufacturing method of routing material, which includes the following steps of providing a main body; forming an insulation layer on an insulated routing surface and forming a plurality of conductor formation via holes in the insulation layer; forming a conductor formation metal layer on the insulation layer so as to fill the metal material of the conductor formation metal layer in those conductor formation via holes; grinding the conductor formation metal layer such that a portion of the conductor formation metal layer on the insulation layer is removed and a portion of the conductor formation metal layer inside the conductor formation via hole is left to serve as a conductor; forming a passivation layer on the insulation layer so as to cover those conductors and form a plurality of bump formation via holes in the passivation layer in which a portion of a conductor in a respective bump formation via hole is exposed; and forming a bump in each bump formation ...

Electric circuit board

The present invention provides an electric circuit board capable of connecting an IC or a semiconductor chip with high reliability. An electrode part 20 to which the metal electrode (bump) of an IC circuit will be connected from an upper part is formed on the glass substrate 11 of a liquid crystal display device. The electrode part 20 is constituted by opening an inter-layer insulating film 23 in a part corresponding to metal wiring 22 and forming a land-like electrode pad 25 in this opened part. In the present invention, the plane shape of the electrode pad 25 is made smaller than the opened part of the inter-layer insulating film 23. Thus the flatness of the peripheral surface of the electrode 20 is improved.

Anisotropic conductive film and production method therefor

An anisotropic conductive film in which conductive particles are positioned uniformly in a single layer, and which is compatible with fine pitch connection. Said anisotropic conductive film is produced by drying an applied coat of a particle dispersion (1), which is a diluted solution (2) of thermoplastic resin in which the conductive particles (3) are dispersed and which forms a coating upon drying. A conductive particle containing layer (7) is formed in which the coated conductive particles (4), which are coated by the dried coating of the diluted solution (2) of thermoplastic resin, are fixed in a single layer to the dried applied coat (6a), and the conductive particle containing layer (7) is laminated by an insulating resin layer (8).

Electrically connecting structure of circuit board and method for fabricating same

An electrically connecting structure of a circuit board and a method for fabricating same are proposed. A circuit board with electrically connecting pads formed thereon is provided. An insulating protecting layer is formed on the circuit board and has openings to expose the electrically connecting pads. A conducting layer is formed on the insulating protecting layer and on the sidewall of the openings. A resist layer with openings corresponding to the electrically connecting pads is formed on the conducting layer. A metal layer is formed in the opening of the resist layer by electroplating and fills the openings. Then, the resist layer is removed. The metal layer and the conducting layer on the surface of the insulating protecting layer are removed by thinning processing, and the metal layer and conducting layer are kept in the openings of the insulting protecting layer to form metal bumps. Afterwards, an adhesive layer is formed on the expose surface of the metal bumps, and electrically ...

Solder ball structure of circuit board and method for fabricating same

INTERCONNECT STRUCTURE FOR A MICROELECTRONIC DEVICE, METHOD OF MANFACTURING SAME, AND MICROELECTRONIC STRUCTURE CONTAINING SAME

An interconnect structure for a microelectronic device includes an electrically conductive material (130, 730, 930) adjacent to a metallization layer (120, 320, 920). The electrically conductive material has a base (131, 931) and a body (132, 932). The base is wider than the body. The base and the body form a single monolithic structure having no internal interface. The interconnect structure may be manufactured by providing a substrate (110, 310, 910) to which the metallization layer is applied, forming a sacrificial layer (410) adjacent to the metallization layer and a resist layer (510) adjacent to the sacrificial layer, patterning the resist layer to form an opening (610) (thereby removing a portion of the sacrificial layer), placing the electrically conductive material in the opening, and removing the resist layer, the sacrificial layer, and a portion of the metallization layer.

CONTACT NODE

Cette invention se rapporte à la fabrication de connexions à demeure lors de la production d'appareils à base de composants micro-électroniques et de dispositifs à semiconducteurs. Cette invention concerne plus précisément des noeuds de contact qui permettent d'assembler, entre autres, des structures de commutation multicouches pour des modules polycristallins, et de monter des cristaux de circuits intégrés à grande échelle sur une structure de commutation lors de la fabrication desdits modules polycristallins. Ce noeud de contact comprend au moins deux contacts métallisés qui sont connectés à des pistes électroconductrices (2, 6) disposées sur les surfaces de couches de commutation (3, 7). Ces couches sont à base d'un matériau diélectrique, sont superposées et sont connectées entre elles électriquement et mécaniquement par un matériau liant électroconducteur (8). Le noeud de contact consiste en une épissure qui relie, d'une part, le contact consistant en une plage métallisée (1) connectée ...

METHOD FOR PRODUCING MICRO PROBE TIPS

Micro-fabrication forms a plurality of stiff vertical micro probes on the front surface of a ceramic substrate and a plurality of contacts on the back surface of the ceramic substrate. Photolithography, various etching technologies and electroplating are used to form the micro probes on the surface of the ceramic substrate. The produced micro probes are mechanically strong and consequently have a long duty life. Moreover, the probes can be arranged into a high-density planar array to conform to the newest integrated circuit devices which have dense I/O terminal arrays.

Method for making memory cards and similar devices using isotropic thermoset materials with high quality exterior surfaces

Memory Cards containing Integrated Circuits and other electronic components (e.g. resistors) in a variety of form factors having high quality external surfaces of polycarbonate, synthetic paper (e.g. Teslin), or other suitable material (e.g. PVC) can be made through use of injection molded thermoplastic material or thermosetting material that becomes the core layer of said Memory Cards and similar devices. The object of the invention is to provide the following properties to Memory Cards: rapid production cycle, high volume manufacturing throughput, security, electronics protection, better tamper resistance, durability, and highly reliable complex electronics encapsulation, achieved through a process utilizing low temperature and low pressure.

Electrical device allowing for increased device densities

A device comprising a circuit, a lead having a first end connected to the circuit and having a second end, and a deformable structure connected to the second end of the lead. The invention may be embodied on a circuit board, so that the circuit board includes a substrate and a deformable structure connected to said substrate. Also disclosed is a device comprising a circuit having an active side and a non-active side, a package enclosing the active side of the circuit and not enclosing a portion of the non-active side of the circuit, and a lead having a first end connected to the active side of the circuit via a lead-over-chip connection, and having a second end extending from the package. Also disclosed is a device comprising a circuit and a lead formed from a flexible conductor, with the lead having a first end connected to the circuit.

Wiring board, semiconductor device, and method of manufacturing wiring board

A wiring board includes a first via hole in a first insulating layer to expose a first wiring layer. A first via in the first via hole includes an end surface. A second wiring layer is arranged on the first insulating layer and the end surface of the first via. A second insulating layer covers the second wiring layer. A second via hole in the second insulating layer exposes the second wiring layer. A second via in the second via hole is arranged above the first via through the second wiring layer. The outer surface of the first insulating layer is lower in surface roughness than an inner surface of the first via hole.

Packaging substrate, method for manufacturing same, and chip packaging structure having same

A packaging substrate includes a circuit board, a number of first conductive posts, and a number of second conductive posts. The circuit board includes a first base and a first conductive pattern layer formed on a first surface of the first base. The first conductive posts extend from and are electrically connected to the first conductive pattern layer. The second conductive posts extend from and are electrically connected to the first conductive pattern layer. The height of each of the second conductive posts are larger than that of each of the first conductive posts.

Components with posts and pads

A packaged microelectronic element includes connection component incorporating a dielectric layer ( 22 ) carrying traces ( 58 ) remote from an outer surface ( 26 ), posts ( 48 ) extending from the traces and projecting beyond the outer surface of the dielectric, and pads ( 30 ) exposed at the outer surface of the dielectric layer, the pads being connected to the posts by the traces. The dielectric element overlies the front surface of a microelectronic element, and contacts ( 74 ) exposed on the front surface of the microelectronic element are connected to the pads by elongated leads ( 76 ) such as wire bonds. Methods of making the connection component are also disclosed.

MOLDED FLUID FLOW STRUCTURE WITH SAW CUT CHANNEL

In an embodiment, a fluid flow structure includes a micro device embedded in a molding. A fluid feed hole is formed through the micro device, and a saw defined fluid channel is cut through the molding to fluidically couple the fluid feed hole with the channel.

METHOD OF MANUFACTURING MULTILAYER WIRING SUBSTRATE, AND MULTILAYER WIRING SUBSTRATE

Disclosed is a method of manufacturing a multilayer wiring substrate having a principal plane of the substrate and a rear plane thereof, having a structure such that a plurality of resin insulating layers and a plurality of conductor layers are laminated, and a plurality of chip component connecting terminals to which chip components are connectable are disposed on the principal plane of the substrate. This method has a feature including a plating layer forming process in which product plating layers which provide the plurality of chip component connecting terminals and a dummy plating layer on the surrounding of the product plating layers are formed on the surface of an exposed outermost resin insulating layer at the principal plane of the substrate. This method permits a thickness dispersion of the chip component connecting terminals to be suppressed and permits a connection reliability thereof to the chip components to be increased.

Method and apparatus for testing bumped die

An apparatus for testing unpackaged semiconductor dice having raised ball contact locations is disclosed. The apparatus uses a temporary interconnect wafer that is adapted to establish an electrical connection with the raised ball contact locations on the die without damage to the ball contact locations. The interconnect is fabricated on a substrate, such as silicon, where contact members are formed in a pattern that matches the size and spacing of the ball contact locations on the die to be tested. The contact members on the interconnect wafer are formed as either pits, troughs, or spike contacts. The spike contacts penetrate through the oxide layer formed on the raised ball contact locations. Conductive traces are provided in both rows and columns and are terminated on the inner edges of the walls of the pits formed in the substrate.

Manufacturing method of a probe head for semiconductor LSI inspection apparatus

The present invention relates to a manufacturing method of a probe head for an inspection apparatus of a semiconductor device represented by an LSI, and more particularly to a manufacturing method suitable for forming probes with high accuracy in forming into multipins at high density, and is characterized in that a structure is obtained, in which a probe forming conductive lower layer is formed on a formed conductive attaching layer for improving attaching strength after forming electrode pads on a wiring substrate, a mask pattern for forming a probe tip forming conductive upper layer is formed at a position corresponding to the probe position is removed by etching in a cylindrical form until the probe forming conductive lower layer is exposed, a probe tip forming conductive upper layer is grown at the position where etching removal has been performed, a mask pattern is removed, a mask pattern which covers a probe tip forming conductive upper layer is formed thereafter at a position corresponding ...

Polycrystalline contacting component and test tool having the contacting component

A contacting component has a probe contact formed by plating and adapted to be contacted with a target portion. The contacting component includes an insulating substrate, a conductive circuit formed on one surface of the insulating substrate, and the probe contact is made of a conductive material and formed on the other surface of the insulating substrate. The conductive circuit and the probe contact are electrically connected in a through hole penetrating the insulating substrate. The probe contact includes a bump contact of a convex shape, the bump contact is formed by plating and having a surface which has a shape of a semispherical protrusion to be contacted with the target portion. The bump contact is made of a material containing a metal and carbon, the content of carbon falling within a range between 0.2 at % and 1.2 at %, both inclusive.

Soft bond for semiconductor dies

On a semiconductor integrated circuit die, a semipermanent electrical connection is effected by the use of wirebond techniques, in which the parameters of the wirebond are controlled, so that less bonding force retains the leadwires to the bondpads than the attachment strength of the bondpads to the die. The wirebond techniques include attaching leadwires to bondpads on the die, using ultrasonic wedge bonding. The strength of the bond between the leadwires is significantly less than the attachment strength of the bondpads, preferably by a ratio which ensures that the bondpads are not lifted from the die when the leadwires are removed by breaking the bond between the leadwires and the bondpads. Subsequent to testing and burnin, the bond between the leadwires and the bondpads is severed. The die are then removed from the package body and the bondpads may then be attached by conventional means. The technique is useful in providing known good die.

Laminated film/metal structures

A process for producing laminated film/metal structures comprising bumped circuit traces on a non-conductive substrate wherein a copper sheet/polyimide film laminate is coated with resist on the exterior surfaces. The resist adjacent the polyimide film is selectively exposed and etched to expose an area of the polyimide film. The exposed polyimide film is etched to form vias through the polyimide film to the inner side of the copper sheet. The resist adjacent the polyimide film is stripped away and a metal bump is electrolytically plated through each via onto the copper sheet. A subsequent layer of resist is electrophoretically applied over the bumps. The resist material adjacent the copper sheet is then selectively exposed and etched to expose areas of the copper sheet. The exposed copper sheet is etched to form circuit traces and the remaining resist adjacent both the polyimide film and the copper sheet is stripped away.

Circuit board and manufacturing method thereof

A circuit board including a substrate, a photo imageable dielectric layer and a plurality of conductive bumps is provided. The substrate has a first surface and a first circuit layer, wherein the first surface has a chip disposing area and an electrical connection area, and the first circuit layer is embedded in the first surface. The photo imageable dielectric layer is disposed on the electrical connection area and has a plurality of openings, wherein parts of the first circuit layer is exposed by the openings. The conductive bumps are disposed at the openings respectively and connected to the first circuit layer, wherein a side surface of each of the conductive bumps is at least partially covered by the photo imageable dielectric layer. In addition, a manufacturing method of the circuit board is also provided.

Method for manufacturing semiconductor package having improved bump structures

A method for manufacturing a semiconductor package includes the steps of forming first circuit patterns on an upper surface of a carrier substrate. Bumps are formed in recesses defined on the upper surface of the carrier substrate. An insulation layer is formed on the upper surface of the carrier substrate to cover the first circuit patterns. Second circuit patterns are formed on an upper surface of the insulation layer so as to be electrically connected with the first circuit patterns. The carrier substrate is then separated from the insulation layer.

Plating solution using ammonium salt

A plating solution including a soluble salt containing at least a stannous salt; an acid selected from organic acid and inorganic acid or a salt thereof; and an additive containing a specific ammonium salt is provided.

Surface treated copper foil, copper foil with carrier, laminate, method for manufacturing printed wiring board, and method for manufacturing electronic device

Also disclosed is a surface treated copper foil, comprising a copper foil, and a surface treatment layer on one or both sides of the copper foil, wherein the surface treatment layer has a primary particle layer, or has a primary particle layer and s secondary particle layer in this order from the side of the copper foil; the surface treatment layer contains Zn, a deposition amount of Zn in the surface treatment layer is 150 μg/dm2 or more; the surface treatment layer does not contain Ni, or in the case where the surface treatment layer contains Ni, a deposition amount of Ni in the surface treatment layer is 800 μg/dm2 or less; the surface treatment layer does not contain Co, or in the case where the surface treatment layer contains Co, a deposition amount of Co in the surface treatment layer is 3000 μg/dm2 or less; and a ten point average roughness Rz of an outermost surface of the surface treatment layer is 1.5 μm or less.

ELECTRONIC MODULE, METHOD FOR MANUFACTURING SAME AND ELECTRONIC DEVICE COMPRISING A MODULE OF SAID TYPE

The invention relates to an electronic module comprising a dielectric support film having a first side, conductor paths that are printed on said first side, and a semiconductor component which connects the conductor paths by means of electrical connections. The electronic module of the invention is characterized in that each electrical connection includes a lead wire that connects a contact of the semiconductor component to each path directly or via an island or an interconnection pad.

INFORMATION HANDLING SYSTEM INTERPOSER ENABLING SPECIALTY PROCESSOR INTEGRATED CIRCUIT IN STANDARD SOCKETS

An information handling system (IHS) has a circuit board assembly with a dual-sided interposer substrate that is inserted between a baseboard and a processor integrated circuit having a second pattern of electrical contacts. The dual interposer substrate formed of a stack of printed circuit boards (PCBs) provides communication channels between a first coupling pad on the baseboard that has a first pattern of electrical contacts and a second coupling pad on top of the dual interposer substrate that provides the second pattern of electrical contacts. The second pattern receives another type of processor integrated circuit than a type supported by the first pattern. Stacked vias formed through the stack of PCBs electrically connect respective electrical contacts of the first and second coupling pads to form a corresponding communication channel. One or more grounded vias mitigate signal integrity (SI) anomalies on the communication channels.

Circuit component bridge device

A bridge device is described herein. The bridge device may include a first via of a bridge device, the first via of the bridge device having a short via stub or no via stub, the first via of the bridge device to be communicatively coupled to a first via of a printed circuit board (PCB). The bridge device may include a second via of the bridge device, the second via of the bridge device having a short via stub or no via stub, the second via of the bridge device to be communicatively coupled to a second via of the PCB. A trace of the bridge device may communicatively couple the first via of the bridge device to the second via of the bridge device.

METHOD OF MANUFACTURING CIRCUIT BOARD

Disclosed herein is a method of manufacturing a circuit board. The method of manufacturing a circuit board according to a preferred embodiment of the present invention is configured to include (A) forming a cavity 115 for a bump on one surface 111 of a carrier 110, (B) forming a bump 130 in the cavity 115 for the bump through an electroplating process, (C) laminating an insulating layer 140 on one surface 111 of the carrier 110 so as to apply the bump 130, (D) forming a circuit layer 150 including a via 155 connected with the bump 130 on the insulating layer 140, and (E) removing the carrier 110, whereby the process of forming separate solder balls is removed by forming the cavities 111 for the bumps in the carriers 110 to form the bumps, thereby simplifying the process of manufacturing a circuit board and reducing the lead time.

PACKAGING SUBSTRATE

A packaging substrate is disclosed, which includes: a dielectric layer; a circuit layer embedded in and exposed from a surface of the dielectric layer, wherein the circuit layer has a plurality of conductive pads; and a plurality of conductive bumps formed on the conductive pads and protruding above the surface of the dielectric layer. As such, when an electronic element is disposed on the conductive pads through a plurality of conductive elements, the conductive elements can come into contact with both top and side surfaces of the conductive bumps so as to increase the contact area between the conductive elements and the conductive pads, thereby strengthening the bonding between the conductive elements and the conductive pads and preventing delamination of the conductive elements from the conductive pads.

Solder Paste

A method of printing solder paste on a substrate through minute apertures in a mask member, in which the solder paste is supplied to the apertures of the mask member under less than atmospheric pressure and has a viscosity so that the solder paste is filled in the apertures under atmospheric pressure. It is preferable that the solder paste has a viscosity of 50 through 150 Pa·s and a thixotropic ratio of 0.3 through 0.5. Further, the solder paste is obtained by mixing a flux containing solvent having a boiling point such that volatilization thereof is suppressed under the less than atmospheric pressure and solder powders. It is preferable that in the flux, the solvent having the boiling point of 240° C. or more is used and the solvent is octanediol.

RESIN SUBSTRATE, COMPONENT-MOUNTED RESIN SUBSTRATE, AND METHOD OF MANUFACTURING COMPONENT-MOUNTED RESIN SUBSTRATE

A resin substrate includes a base portion including one first resin sheet made of a thermoplastic resin as a main material or a stack of two or more first resin sheets each made of a thermoplastic resin as a main material, the base portion including a main surface, and first and second connecting conductors provided on the main surface of the base portion and spaced away from each other. The base portion includes a convex portion separating the first and second connecting conductors on the main surface by a second resin sheet disposed at a position on a surface of the base portion or inside the base portion. The second resin sheet is made of the same material as the first resin sheet. 1. A resin substrate comprising:a base portion including one first resin sheet made of a thermoplastic resin as a main material or a stack of two or more first resin sheets each made of a thermoplastic resin as a main material, the base portion including a main surface; anda first connecting conductor and a second connecting conductor that are provided on the main surface of the base portion so as to be spaced away from each other; whereinthe base portion includes a convex portion separating the first connecting conductor and the second connecting conductor from each other on the main surface by a second resin sheet disposed at a position on a surface of the base portion or inside the base portion;a material of the second resin sheet is the same as a material of the first resin sheet; andthe convex portion includes a bridge portion and a frame-shaped portion that supports the bridge portion.2. The resin substrate according to claim 1 , wherein the second resin sheet includes an end that is covered by the first resin sheet on the main surface of the base portion.3. The resin substrate according to claim 1 , wherein each of the first connecting conductor and the second connecting conductor is a conductor via.4. The resin substrate according to claim 1 , wherein each of the first ...

Porous alumina templates for electronic packages

Interposers and methods of making the same are disclosed herein. In one embodiment, an interposer includes a region having first and second oppositely facing surfaces and a plurality of pores, each pore extending in a first direction from the first surface towards the second surface, wherein alumina extends along a wall of each pore; a plurality of electrically conductive connection elements extending in the first direction, consisting essentially of aluminum and being electrically isolated from one another by at least the alumina; a first conductive path provided at the first surface for connection with a first component external to the interposer; and a second conductive path provided at the second surface for connection with a second component external to the interposer, wherein the first and second conductive paths are electrically connected through at least some of the connection elements.

Probing device and manufacturing method thereof, as well as testing apparatus and manufacturing method of semiconductor with use thereof

A probing device for electrically contacting with a plurality of electrodes 3, 6 aligned on an object 1 to be tested so as to transfer electrical signal therewith, comprising: a wiring sheet being formed by aligning a plurality of contact electrodes 21, 110b, corresponding to each of said electrodes, each being planted with projecting probes 20, 110a covered with hard metal films on basis of a conductor thin film 41 formed on one surface of an insulator sheet 22 of a polyimide film by etching thereof, while extension wiring 23, 110c for electrically connecting to said each of said contact electrodes being formed on basis of a conductor thin film formed on either said one surface or the other surface opposing thereto of said insulator sheet of the polyimide film; and means for giving contacting pressure for obtaining electrical conduction between said extension wiring and said object to be tested by contacting tips of said projecting contact probe formed onto said each contact electrode ...

CIRCUIT DEVICE, METHOD OF MANUFACTURING THE CIRCUIT DEVICE, DEVICE MOUNTING BOARD AND SEMICONDUCTOR MODULE

A circuit device includes an insulating base provided with a resin layer mixed with a fibrous filler, bumps provided in the insulating base and functioning as electrodes for connection, a semiconductor device that is flip-chip mounted, and an underfill filling a gap between the semiconductor device and the insulating base. By allowing the fibrous filler projecting through the top surface of the resin layer to be in contact with the underfill, strength of adhesion between the underfill and the insulating base is improved.

PRINTED WIRING BOARD

A printed wiring board includes a resin insulating layer, pads formed on the resin insulating layer, an uppermost resin insulating layer formed on the resin insulating layer such that the uppermost resin insulating layer is covering the pads and has openings exposing the pads, respectively, via conductors formed in the uppermost resin insulating layer such that the via conductors are formed on the pads exposed from the openings in the uppermost resin insulating layer, respectively, and metal posts formed on the via conductors such that each of the metal posts has a portion on a surface of the uppermost resin insulating layer around the via conductors and a side surface having a flared bottom extending toward the uppermost resin insulating layer.

DEVICE OBTAINED BY NANOPRINTING COMPRISING METALLIC PATTERNS AND METHOD FOR NANOPRINTING OF METALLIC PATTERNS

Wiring substrate and manufacturing method thereof, and semiconductor device

A wiring substrate (11) includes a first insulation layer (14), a connection terminal (15), a second insulation layer (21), a via (24), and a wiring pattern (16). The connection terminal (15) is disposed in the first insulation layer (14) so as to be exposed from a first main surface (14B) of the first insulation layer (14), and is electrically connected with a semiconductor chip (12). The second insulation layer (21) is disposed on a second main surface (14C) of the first insulation layer (14) situated on the opposite side from the first main surface (14B). The via (24) is disposed in the second insulation layer (21), and is electrically connected with the connection terminal (15). The via (24) is separated from the connection terminal (15). The wiring pattern (16) is disposed on the second main surface (14C) of the first insulation layer (14) and electrically connects the connection terminal (15) and the via (24).

Electrical Connector, Electrical Connection System and Lithographic Apparatus

An electrical connector comprises a high voltage pad and a high voltage plate. When connected to another electrical connector, the two plates, which are at the same voltage as the pads, form a region of high voltage in which the field is low. The pads are positioned in that region. An electrostatic clamp of an EUV lithographic apparatus may have such a pad and plate, for connecting to the electrical connector. By placing the interconnection in a low field region, triple points (points of contact between a conductor, a solid insulator and a gas) may be present in that region.

Method of fabricating circuit board structure

A method of fabrication a circuit board structure comprising providing a circuit board main body, forming a molded, irregular plastic body having a non-plate type, stereo structure and at least one scraggy surface by encapsulating at least a portion of said circuit board main body with injection molded material, and forming a first three-dimensional circuit pattern on said molded, irregular plastic body thereby defining a three-dimensional circuit device.

Suspension board with circuit and producing method thereof

A suspension board with circuit includes a metal supporting board; an insulating layer formed on the metal supporting board having an opening penetrating in the thickness direction formed therein; and a conductive pattern formed on the insulating layer including an external-side terminal electrically connected to an external board. The external-side terminal is filled in the opening of the insulating layer. In the metal supporting board, a support terminal electrically insulated from the surrounding metal supporting board and electrically connected to the external-side terminal is provided. The suspension board with circuit includes a metal plating layer formed below the support terminal and an electrically-conductive layer interposed between the support terminal and the metal plating layer having a thickness of 10 nm or more to 200 nm or less.

Electronic apparatus and hard disk drive

According to one embodiment, an electronic apparatus includes a case, a printed circuit board contained in the case and having a through-hole, and a fixing member including a shaft portion inserted in the through-hole and a head portion located at one end of the shaft portion. The electronic apparatus also includes copper foil provided on the printed circuit board, and a cover film including an opening portion configured to expose part of the copper foil. The opening portion is located at a position which is to be covered with the head portion, and the cover film covers the copper foil at positions other than the position where the opening portion is located. The electronic apparatus further includes a conductive material provided on the copper foil inside the opening portion and configured to electrically connect the head portion and the copper foil to each other.

Method of manufacturing printed circuit board

A method of manufacturing a printed circuit board, including: applying a conductive paste including carbon nanotubes and a photosensitive binder on a bump-forming area of a circuit substrate having a circuit layer for transferring electrical signals; and patterning the conductive paste, thus forming bumps.

Semiconductor chip assembly and method for making same

A microelectronic assembly may include a substrate including a rigid dielectric layer having electrically conductive elements, a microelectronic element having a plurality of contacts exposed at a face thereof, and conductive vias extending through a compliant dielectric layer overlying the rigid dielectric layer. The vias electrically connect the substrate contacts respectively to the conductive elements, and the substrate contacts are joined respectively to the contacts of the microelectronic element. The vias, compliant layer and substrate contacts are adapted to appreciably relieve stress at the substrate contacts associated with differential thermal contact and expansion of the assembly.

Metalized pad to electrical contact interface

A surface mount electrical interconnect to provide an interface between a PCB and contacts on an integrated circuit device. The electrical interconnect includes a substrate with a plurality of recesses arranged along a first surface to correspond to the contacts on the integrated circuit device. Contact members are located in a plurality of the recess. The contact members include contact tips adapted to electrically couple with the contacts on the integrated circuit device. An electrical interface including at least one circuit trace electrically couples the contact member to metalized pads located along a second surface of the substrate at a location offset from a corresponding contact member. A solder ball is attached to a plurality of the metalized pads.

Packaging substrate with conductive structure

A packaging substrate with conductive structure is provided, including a substrate body having at least one conductive pad on a surface thereof, a stress buffer metal layer disposed on the conductive pad and a thickness of the stress buffer metal layer being 1-20 μm, a solder resist layer disposed on the substrate body and having at least one opening therein for correspondingly exposing a portion of top surface of the stress buffer metal layer, a metal post disposed on a central portion of the surface of the stress buffer metal layer, and a solder bump covering the surfaces of the metal post. Therefore, a highly reliable conductive structure is provided, by using the stress buffer metal layer to release thermal stresses, and using the metal post and the solder bump to increase the height of the conductive structure.

Module substrate, module-substrate manufacturing method, and terminal connection substrate

In a module substrate, a plurality of terminal connection substrates each including an insulator and a plurality of columnar terminal electrodes arranged on a single lateral surface or both lateral surfaces of the insulator is mounted on a single side of a composite substrate such that at least one of the terminal connection substrates extends over a border between a plurality of neighboring module substrates. The composite substrate, in which the plurality of terminal connection substrates is mounted on the single side and a plurality of electronic components is mounted on at least the single side, is divided at a location where the module substrates are to be cut from the composite substrate.

Method for manufacturing circuit board provided with metal posts and circuit board manufactured by the method

Provided is a method for manufacturing a circuit board provided with metal posts formed on at least one surface of the circuit board, the method including preparing a substrate made of a conductive material, performing a first selective etching a first surface of the substrate in regions corresponding to insulating portions of a first circuit pattern, laminating a first insulating layer over the first surface of the substrate, and performing a second etching on a second surface opposite of the first surface of the substrate, thereby forming the metal posts and the first circuit.

Method to form solder deposits and non-melting bump structures on substrates

Described is a method of forming a metal or metal alloy layer onto a substrate comprising the following steps i) provide a substrate including a permanent resin layer on top of at least one contact area and a temporary resin layer on top of the permanent resin layer, ii) contact the entire substrate area including the at least one contact area with a solution suitable to provide a conductive layer on the substrate surface and i) electroplate a metal or metal alloy layer onto the conductive layer.

PRINTED CIRCUIT BOARD AND METHOD FOR MANUFACTURING THE SAME

The present invention relates to a method for manufacturing a printed circuit board, which includes: preparing a base substrate with an electrode pad; providing a conductive material having a predetermined height; disposing the conductive material on the electrode pad; and forming a conductive post on the electrode pad by bonding the electrode pad and the conductive material, and can achieve a fine pitch and easily implement a conductive post with a high aspect ratio. 1. A method for manufacturing a printed circuit board , comprising:preparing a base substrate with an electrode pad;providing a conductive material having a predetermined height;disposing the conductive material on the electrode pad; andforming a conductive post on the electrode pad by bonding the electrode pad and the conductive material.2. The method for manufacturing a printed circuit board according to claim 1 , wherein providing the conductive material having a predetermined height provides the conductive material having a predetermined height by cutting the conductive material formed in a wire shape to a height to be formed.3. The method for manufacturing a printed circuit board according to claim 1 , wherein disposing the conductive material on the electrode pad disposes the conductive material on the electrode pad by moving the conductive material to the electrode pad through a jig.4. The method for manufacturing a printed circuit board according to claim 3 , wherein disposing the conductive material on the electrode pad comprises:forming a hole passing through the jig;inserting the conductive material in the hole; anddisposing the conductive material on the electrode pad by moving the jig in which the conductive material is inserted to the base substrate.5. The method for manufacturing a printed circuit board according to claim 4 , wherein inserting the conductive material in the hole inserts the conductive material in the hole using any one method selected from a vibration absorption method ...

Method of manufacturing coreless substrate having filled via pad

A method of manufacturing a coreless substrate having filled via pads, including: forming a first insulating layer on one side of a carrier forming a build-up layer including a build-up insulating layer and a build-up circuit layer having a build-up via on the first insulating layer, and forming a second insulating layer on the build-up layer; removing the carrier, and forming via-holes in the first and second insulating layers; and conducting a filled plating process in the via-holes of the first and second insulating layers thus forming first and second filled via pads therein.

Wiring substrate and method of manufacturing the same

There is provided a wiring substrate. The wiring substrate includes: an insulating layer; first electrode pads having first exposed surfaces, the first exposed surfaces being exposed from the insulating layer; and second electrode pads having second exposed surfaces, the second exposed surfaces being exposed from the insulating layer. There is a level difference between the first exposed surfaces and the second exposed surfaces.

Second Level Interconnect Structures and Methods of Making the Same

The various embodiments of the present invention provide a stress-relieving, second-level interconnect structure that is low-cost and accommodates TCE mismatch between low-TCE packages and PCBs. The various embodiments of the interconnect structure are reworkable and can be scaled to pitches from about 1 millimeter (mm) to about 150 micrometers (μm). The interconnect structure comprises at least a first pad, a supporting pillar, and a solder bump, wherein the first pad and supporting pillar are operative to absorb substantially all plastic strain, therefore enhancing compliance between the two electronic components. The versatility, scalability, and stress-relieving properties of the interconnect structure of the present invention make it a desirable structure to utilize in current two-dimensional and ever-evolving three-dimensional IC structures.

ELECTROPHORETIC DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME

An electrophoretic display apparatus includes a first substrate, a second substrate, a first electrode, a second electrode, an electrophoretic layer interposed between a TFT array substrate and an opposed substrate, a terminal for the second electrode provided in the first substrate, a conductive portion electrically connected to the second electrode and provided from a first surface to a second surface of the second substrate, and a connection member that electrically connects the conductive portion with the terminal for the second electrode. 1. An electrophoretic display apparatus comprising:a first substrate;a second substrate facing the first substrate;an electrophoretic layer that is interposed between the first substrate and the second substrate and contains electrophoretic particles;a first electrode that is provided between the first substrate and the electrophoretic layer;a second electrode that is provided between the second substrate and the electrophoretic layer;a terminal for a second electrode that is provided in the first substrate and is electrically connected to the second electrode;a conductive portion that is electrically connected to the second electrode and is provided from a first surface side of the second substrate facing the first substrate to a second surface side thereof not facing the first substrate; anda connection member that is connected to the conductive portion in a portion located on the second surface side of the second substrate in the conductive portion and electrically connects the conductive portion with the terminal for the second electrode.2. The electrophoretic display apparatus according to claim 1 ,wherein the conductive portion is constituted by a conductive film that is provided from the first surface of the second substrate to the second surface via an end surface of the second substrate.3. The electrophoretic display apparatus according to claim 1 ,wherein a through hole is provided which penetrates between the first ...

Printed circuit board and method for manufacturing same

A printed circuit board according the present embodiment includes an insulating layer; at least one circuit pattern or pad formed on the insulating layer; a solder resist having an opening section exposing the upper surface of the pad and formed on the insulating layer and a bump formed on the pad exposed through the opening section of the solder resist and having a lower area narrower than the upper area.

Printed circuit board and method of fabricating the same

Disclosed is a printed circuit board, which includes an insulating member having a circuit pattern embedded in one surface thereof, a bump pad formed in the insulating member so as to be connected to the circuit pattern and protruding from an outer surface of the insulating member, a build-up layer formed on one surface of the insulating member and including a build-up insulating layer and a circuit layer formed in the build-up insulating layer and having a via connected to the circuit pattern, and a solder resist layer formed on the build-up layer. A method of fabricating the printed circuit board is also provided. The printed circuit board is fabricated using a build-up process and the outermost circuit layer thereof is formed to have an embedded structure using an imprinting process, thus minimizing the separation of the circuit layer and reducing the lead time and the fabrication cost.

FABRICATING METHOD OF EMBEDDED PACKAGE STRUCTURE

A fabricating method of an embedded package structure includes following steps. First and second boards are combined to form an integrated panel. First and second circuit structures are respectively formed on the first and second boards that are then separated. An embedded element is electrically disposed on the first circuit structure. First and second conductive bumps are respectively formed on a conductive circuit substrate and the second circuit structure. First and second semi-cured films are provided; a laminating process is performed to laminate the first circuit structure on the first board, the first and second semi-cured films, the conductive circuit substrate, and the second circuit structure on the second board. The first and second semi-cured films encapsulate the embedded element. The first and second conductive bumps respectively pierce through the first and second semi-cured films and are electrically connected to the first circuit structure and the conductive circuit substrate, respectively. 1. A fabricating method of an embedded package structure , comprising:combining a first board and a second board to form an integrated panel;forming a first circuit structure on the first board and forming a second circuit structure on the second board;separating the first board from the second board;electrically disposing an embedded element on the first circuit structure;forming a first conductive bump on a surface of a conductive circuit substrate, the surface of the conductive circuit substrate facing a side of the first circuit structure;forming a second conductive bump on the second circuit structure; andproviding a first semi-cured film and a second semi-cured film and performing a laminating process to laminate the first circuit structure on the first board, the first semi-cured film, the conductive circuit substrate, the second semi-cured film, and the second circuit structure on the second board, wherein the first semi-cured film and the second semi- ...

BONDING PAD FOR THERMOCOMPRESSION BONDING, PROCESS FOR PRODUCING A BONDING PAD AND COMPONENT

A bonding pad for thermocompression bonding of a carrier material to a further carrier material includes a base layer and a top layer. The base layer is made of metal, is deformable, and is connected to the carrier material. The metal is nickel-based. The top layer is metallic and is connected directly to the base layer. The top layer is arranged at least on a side of the base layer which faces away from the carrier material. The top layer has a smaller layer thickness than the base layer. In at least one embodiment, the top layer has a greater oxidation resistance than the base layer. 1. A bonding pad for the thermocompression bonding of a carrier material to a further carrier material , the bonding pad comprising:a deformable base layer made of metal, which is connected to the carrier material, the metal being nickel-based; anda metallic top layer connected directly to the base layer and arranged at least on a side of the base layer which faces away from the carrier material,wherein a layer thickness of the top layer is smaller than a layer thickness of the base layer, andwherein an oxidation resistance of the top layer is greater than an oxidation resistance of the base layer.2. The bonding pad according to claim 1 , wherein the top layer includes at least one layer including at least partially one of palladium claim 1 , gold claim 1 , platinum claim 1 , and copper.3. The bonding pad according to claim 1 , wherein the layer thickness of the base layer has a predefined relationship with the layer thickness of the top layer.4. The bonding pad according to claim 1 , wherein a subarea of the top layer is at least one of planar and arranged parallel to a surface of the carrier material.5. A component claim 1 , comprising: a deformable base layer made of metal, which is connected to the carrier material, the metal being nickel-based; and', 'a metallic top layer connected directly to the base layer and arranged at least on a side of the base layer which faces away from ...

Compliant core peripheral lead semiconductor socket

An electrical interconnect between terminals on an IC device and contact pads on a printed circuit board (PCB). The electrical interconnect includes a substrate with a first surface having a plurality of openings arranged to correspond to the terminals on the IC device. A compliant material is located in the openings. A plurality of first conductive traces extend along the first surface of the substrate and onto the compliant material. The compliant material provides a biasing force that resists flexure of the first conductive traces into the openings. Vias extending through the substrate are electrically coupled the first conductive traces. A plurality of second conductive traces extend along the second surface of the substrate and are electrically coupled to a vias. The second conductive traces are configured to electrical couple with the contact pads on the PCB.

PRINTED CIRCUIT BOARD, SEMICONDUCTOR PACKAGE USING THE SAME, AND METHOD FOR MANUFACTURING THE PRINTED CIRCUIT BOARD AND THE SEMICONDUCTOR PACKAGE

The present invention relates to a printed circuit board, a semiconductor package using the same, and a method for manufacturing the printed circuit board and the semiconductor package. The method for manufacturing a semiconductor package in accordance with the present invention includes: forming a circuit of a predetermined pattern on a PCB substrate; applying a first insulating material on the substrate; removing the first insulating material in the remaining portion except a predetermined portion by exposing and developing the substrate; forming a solder bump in the circuit portion exposed; molding a certain region of an upper surface portion of the PCB substrate including the solder bump by filling a second insulating material on the PCB substrate including the circuit portion; mounting a semiconductor chip on the PCB substrate; and completing one package in which the semiconductor chip and the PCB substrate are integrated. 1. A printed circuit board comprising:a PCB substrate having a circuit of a predetermined pattern on an upper surface;a solder bump formed in the circuit portion to bond a semiconductor chip to the PCB substrate;a second insulating material for molding a certain region of the upper surface portion of the PCB substrate including the solder bump before bonding the semiconductor chip to the PCB substrate; anda first insulating material formed on the PCB substrate to surround the second insulating material and restrict the second insulating material from leaking to the outside.2. The printed circuit board according to claim 1 , wherein the second insulating material is a non-conductive film (NCF) or paste.3. The printed circuit board according to claim 1 , wherein the second insulating material is a B-stage thermosetting resin.4. The printed circuit board according to claim 3 , wherein the thermosetting resin is one of an epoxy resin claim 3 , an amino resin claim 3 , a phenol resin claim 3 , a urea resin claim 3 , a melamine resin claim 3 , an ...

Wiring board, semiconductor device, and method of manufacturing wiring board

A wiring board includes a first via hole in a first insulating layer to expose a first wiring layer. A first via in the first via hole includes an end surface. A second wiring layer is arranged on the first insulating layer and the end surface of the first via. A second insulating layer covers the second wiring layer. A second via hole in the second insulating layer exposes the second wiring layer. A second via in the second via hole is arranged above the first via through the second wiring layer. The outer surface of the first insulating layer is lower in surface roughness than an inner surface of the first via hole.

Display device and manufacturing method thereof

According to an exemplary embodiment of the present invention, the gap between a display panel and a driving circuit is maintained by an insulating side wall that covers the sides of conductors provided on a drive pad and that is higher than the surface of the conductors without adding a photolithography process. Even when, as the resolution of the display device is increased, the gap between two adjacent conductors is reduced, the two adjacent conductors may be prevented from being shorted.

MANUFACTURING METHOD OF A CIRCUIT BOARD HAVING A GLASS FILM

Provided is a manufacturing method of a circuit board structure including steps as below. A glass film is provided on an electrostatic chuck (E-chuck). A plurality of first conductive vias are formed in the glass film. A first circuit layer is formed on an upper surface of the glass film, such that the first circuit layer is electrically connected with the first conductive vias. A first polymer layer is formed on the first circuit layer. The first polymer layer covers a surface of the first circuit layer and the upper surface of the glass film. A plurality of second conductive vias are formed in the first polymer layer. A second circuit layer is formed on the first polymer layer, such that the second circuit layer is electrically connected with the second conductive vias. The E-chuck is removed. 1. A manufacturing method of a circuit board structure , comprising:providing a glass film having an upper surface and a lower surface, and the lower surface of the glass film being disposed on an electrostatic chuck;forming a plurality of first conductive vias in the glass film, and the plurality of the first conductive vias penetrate the upper surface and the lower surface of the glass film;forming a first circuit layer on the upper surface of the glass film, such that the first circuit layer is electrically connected with the first conductive vias;forming a first polymer layer on the first circuit layer, and the first polymer layer covering a surface of the first circuit layer and the upper surface of the glass film;forming a plurality of second conductive vias in the first polymer layer, wherein the second conductive vias are electrically connected with the first circuit layer;forming a second circuit layer on the first polymer layer, such that the second circuit layer is electrically connected with the second conductive vias; andremoving the electrostatic chuck, so as to form a first circuit board structure.2. The manufacturing method of the circuit board structure ...

SEMICONDUCTOR DEVICE

In a semiconductor device, protective films are formed on facing side surfaces of a plurality of circuit patterns and a plating process or the like is not performed on parts aside from the side surfaces where the protective films are formed. This means that when semiconductor elements and contact elements are directly bonded via solder onto the plurality of circuit patterns, a drop-in wettability of the plurality of circuit patterns for the solder is avoided. 1. A semiconductor device , comprising:a substrate including an insulating plate having a front surface and a plurality of circuit patterns formed on the front surface of the insulating plate, that have respective front surfaces, that have respective side portions, and that have respective edge portions on the front surfaces of the plurality of circuit patterns along the side portions;a plurality of protective films formed on at least facing side portions of the plurality of circuit patterns so as to expose bonding regions on the front surfaces of the plurality of circuit patterns; anda plurality of components bonded via solder onto the bonding regions of the plurality of circuit patterns.2. The semiconductor device according to claim 1 , wherein the plurality of protective films are formed on at least the facing side portions and on the edge portions of the front surfaces of the plurality of circuit patterns along the side portions.3. The semiconductor device according to claim 2 , wherein the plurality of protective films are formed on the side portions claim 2 , on the edge portions claim 2 , and on the front surfaces of the plurality of circuit patterns so as to expose the bonding regions.4. The semiconductor device according to claim 1 , wherein at least one of the plurality of components is bonded so as to span between adjacent circuit patterns among the plurality of circuit patterns.5. The semiconductor device according to claim 1 , wherein the plurality of components are at least one of semiconductor ...

ABSORBING TERMINATION IN AN INTERCONNECT

Embodiments of the present disclosure are directed toward techniques and configurations for electrical signal absorption in an interconnect disposed in a printed circuit board (PCB) assembly. In one instance, a PCB assembly may comprise a substrate, and an interconnect formed in the substrate to route an electrical signal within the PCB. The interconnect may be coupled with a connecting component that is disposed on a surface of the PCB. An absorbing material may be disposed on the PCB to be in direct contact with at least a portion of the connecting component to at least partially absorb a portion of the electrical signal. Other embodiments may be described and/or claimed. 125-. (canceled)26. An apparatus comprising:a printed circuit board (PCB) comprising at least one transmission line to route an electrical signal within the PCB, wherein at least one end of the transmission line is coupled to a connecting component that comprises a connector slot disposed on a surface of the PCB; anda connecting element inserted in the connector slot, wherein at least a surface of the connecting element that faces the connector slot is covered with an absorbing material in contact with at least a portion of the connector slot, to at least partially absorb a portion of the electrical signal.27. The apparatus of claim 26 , wherein the electrical signal comprises a transmission signal transmitted at a frequency between 5 and 7 GHz.28. The apparatus of claim 26 , wherein the connecting component is a first connecting component claim 26 , wherein the connector slot is a first connector slot claim 26 , wherein the connecting element is a first connecting element of a first computing component coupled with the apparatus.29. The apparatus of claim 28 , further comprising a second connecting component coupled with the transmission line claim 28 , wherein the second connecting component comprises a second connector slot to receive a corresponding second connecting element of a second ...

MULTILAYER CIRCUIT BOARD, SEMICONDUCTOR APPARATUS, AND METHOD OF MANUFACTURING MULTILAYER CIRCUIT BOARD

A multilayer circuit board with a laminated structure includes an outermost insulating layer provided as an uppermost or bottom layer of the multilayer circuit board and formed of a composite material containing a glass fiber; and a multilayer interconnect lamination provided as an adjacent layer next to the outermost insulating layer, the multilayer interconnect lamination having an interconnect provided in an insulating resin layer that does not contain a glass fiber, and an interlayer via electrically connected to the interconnect. 1. A multilayer circuit board with a laminated structure , comprising:an outermost insulating layer provided as an uppermost or bottom layer of the multilayer circuit board and formed of a composite material containing a glass fiber; anda multilayer interconnect lamination provided as an adjacent layer next to the outermost insulating layer, the multilayer interconnect lamination having an interconnect provided in an insulating resin layer that does not contain a glass fiber, and a interlayer via electrically connected to the interconnect.2. The multilayer circuit board as claimed in claim 1 , further comprising:a first surface electrode provided on a surface of the outermost insulating layer; anda via plug provided in the outermost insulating layer,wherein the first surface electrode is electrically connected to the interconnect by the via plug and the interlayer via.3. The multilayer circuit board as claimed in claim 1 ,wherein the interconnect provided in the insulating resin layer is a differential pair.4. The multilayer circuit board as claimed in claim 1 , wherein the insulating resin layer has a coefficient of thermal expansion similar or close to that of the interconnect.5. The multilayer circuit board as claimed in claim 1 , wherein the insulating resin layer is a polyimide layer and the interconnect is a copper interconnect.6. The multilayer circuit board as claimed in claim 1 , further comprising:a through via that passes ...

ELECTRONIC DEVICE MODULE AND METHOD OF MANUFACTURING ELECTRONIC DEVICE MODULE

An electronic device module may include: a board; a ground electrode disposed on a first surface of the board; a sealing portion disposed on the first surface of the board; electronic devices mounted on the first surface of the board such that at least one of the electronic devices is embedded in the sealing portion; a first shielding wall connected to the ground electrode and disposed along a side surface of the sealing portion; and a shielding layer formed of a conductive material and disposed along a surface formed by the sealing portion and the first shielding wall. 1. An electronic device module , comprising:a board;a ground electrode disposed on a first surface of the board;first and second electronic devices mounted on the first surface of the board;a sealing portion disposed on the first surface of the board embedding the second electronic device;a first shielding wall connected to the ground electrode and disposed to divide the sealing portion; anda shielding layer formed of a conductive material and disposed along a surface formed by the sealing portion and the first shielding wall,wherein the first shielding wall comprises an extension portion at the surface formed by the sealing portion and the first shielding wall.2. The electronic device module of claim 1 , wherein the second electronic device comprises a plurality of second electronic devices.3. The electronic device module of claim 1 , wherein the shielding layer is spaced apart from the board.4. The electronic device module of claim 3 , further comprising an external sealing portion disposed between the board and a bottom of the shielding layer.5. The electronic device module of claim 1 , wherein at least a portion of the shielding layer is disposed on the board.6. The electronic device module of claim 1 , wherein a width of the first shielding wall decreases in a direction from an end of the first shielding wall spaced from the board toward the board.7. The electronic device module of claim 6 , ...

INTERCONNECT STRUCTURE

An interconnect structure includes a substrate, a dielectric block, and a conductor. The dielectric block is in the substrate. A dielectric constant of the dielectric block is smaller than a dielectric constant of the substrate, and the dielectric block and the substrate have substantially the same thickness. The conductor includes a first portion extending from a top surface to a bottom surface of the dielectric block and a second portion extending along and contacting the top surface of the dielectric block. 1. An interconnect structure , comprising:a substrate;a dielectric block in the substrate, wherein a dielectric constant of the dielectric block is smaller than a dielectric constant of the substrate, and the dielectric block and the substrate have substantially the same thickness; anda conductor comprising a first portion extending from a top surface to a bottom surface of the dielectric block and a second portion extending along and contacting the top surface of the dielectric block.2. The interconnect structure of claim 1 , wherein the conductor further comprises a third portion extending along and contacting the bottom surface of the dielectric block.3. The interconnect structure of claim 2 , wherein the third portion of the conductor is spaced apart from the substrate.4. The interconnect structure of claim 1 , further comprising a plug laterally surrounded by the conductor.5. The interconnect structure of claim 4 , wherein the plug is electrically conductive.6. The interconnect structure of claim 4 , wherein the plug is electrically non-conductive.7. The interconnect structure of claim 1 , wherein the dielectric block contacts the substrate.8. An interconnect structure claim 1 , comprising:a substrate;a dielectric block in the substrate;a shielding element laterally surrounding the dielectric block; anda conductor extending from a top surface to a bottom surface of the dielectric block, wherein the shielding element and the conductor have substantially ...

WIRING SUBSTRATE, STACKED WIRING SUBSTRATE, AND MANUFACTURING METHOD OF WIRING SUBSTRATE

A wiring substrate includes: a wiring structure that includes a wiring layer and an insulating layer laminated; a plurality of first posts that are formed along a periphery of a predetermined area on a surface of the wiring structure, and that protrude out from the surface of the wiring structure; and a second post that is connected to the wiring layer at a position surrounded by the first posts, and that protrudes out from the surface of the wiring structure. The first posts are formed such that a post arranged at a central portion of a side constituting the periphery of the predetermined area is lower in height from the surface of the wiring structure than posts arranged at both ends of the side. 1. A wiring substrate comprising:a wiring structure that includes a wiring layer and an insulating layer laminated;a plurality of first posts that are formed along a periphery of a predetermined area on a surface of the wiring structure, and that protrude out from the surface of the wiring structure; anda second post that is connected to the wiring layer at a position surrounded by the first posts, and that protrudes out from the surface of the wiring structure, whereinthe first posts are formed such that a post arranged at a central portion of a side constituting the periphery of the predetermined area is lower in height from the surface of the wiring structure than posts arranged at both ends of the side.2. The wiring substrate according to claim 1 , further comprisinga solder resist layer that covers the surface of the wiring structure, whereinthe first posts are formed on the solder resist layer.3. The wiring substrate according to claim 1 , whereinthe first posts are formed on the insulating layer exposed to the surface of the wiring structure.4. The wiring substrate according to claim 1 , whereinthe first posts and the second post are made from an identical metal material.5. The wiring substrate according to claim 1 , whereinthe first posts are formed such that ...

ELECTRONIC COMPONENT MODULE AND MANUFACTURING METHOD THEREOF

An electronic device module includes a first substrate, at least one electronic device mounted on a lower surface of the first substrate, a second substrate mounted on a lower surface of the first substrate to electrically connect the first substrate to an external source of power, a connecting conductor bonded to a lower surface of the second substrate, and a sealing portion sealing the electronic device, the second substrate, and the connecting conductor, wherein a mounting height of the second substrate is configured to be lower than a mounting height of the electronic device. 1. An electronic device module comprising:a first substrate;an electronic device mounted on a lower surface of the first substrate;a second substrate mounted on the lower surface of the first substrate, the second substrate being configured to electrically connect the first substrate to an external source of power;a connecting conductor bonded to a lower surface of the second substrate; anda sealing portion that seals the electronic device, the second substrate, and the connecting conductor,wherein the sealing portion covers the lower surface of the second substrate,the connecting conductor passes through the sealing portion so that a surface of the connecting conductor is exposed to an exterior of the sealing portion, andthe exposed surface of the connecting conductor and a lower surface of the sealing portion are disposed on a same plane.2. The electronic device module of claim 1 , wherein a surface of the electronic device is exposed to the exterior of the sealing portion claim 1 , andthe exposed surface of the connecting conductor, the lower surface of the sealing portion, and the exposed surface of the electronic device are disposed on a same plane.3. The electronic device module of claim 1 , further comprising a protective layer disposed along a surface formed by the electronic device and the sealing portion.4. The electronic device module of claim 3 , further comprising a shielding ...

Polymeric Electromagnetic Shield for Electronic Components

An electronic device can include a circuit board, an electronic component mounted on the circuit board, a conductive contact disposed (e.g., deposited) on the circuit board, and a shielding polymer layer deposited over the electronic component. The shielding polymer layer includes a network of conductive pathways formed from sintered particles. The network of conductive pathways is electrically coupled to the conductive contact, which can be configured for connection to a power source ground. As such, the network of conductive pathways enables electromagnetic shielding of the electronic component. 1. (canceled)2. An electronic device comprising:a circuit board;an electronic component mounted on the circuit board;a conductive contact disposed on the circuit board and configured for connection to a power source ground; anda shielding polymer layer disposed over the electronic component and including a network of conductive pathways formed from sintered particles, wherein the network of conductive pathways is electrically coupled to the conductive contact and the sintered particles are produced from non-electrically conductive sinterable particles exposed to sufficient energy to sinter the particles.3. The electronic device of claim 2 , wherein the energy is electromagnetic energy selected from the group consisting of ultraviolet light claim 2 , visible laser light claim 2 , infrared light claim 2 , x-rays claim 2 , and microwaves.4. The electronic device of claim 2 , wherein the shielding polymer layer substantially encloses the electronic component.5. The electronic device of claim 2 , wherein the network of conductive pathways occupies an entire surface area of the shielding polymer layer.6. An electronic device comprising:a circuit board;an electronic component mounted on the circuit board;a conductive contact disposed on the circuit board and configured for connection to a power source ground; anda shielding polymer layer disposed over the electronic component and ...

Wiring substrate and semiconductor package

A wiring substrate includes an insulating layer that is an outermost layer of the wiring substrate and includes an external exposed surface, a pad forming part formed on a side of the external exposed surface, and a pad that projects from the external exposed surface. The pad forming part includes a recess part recessed from the external exposed surface, and a weir part that projects from the external exposed surface and encompasses the recess part from a plan view. The pad includes a pad body formed within the recess part and the weir part, and an eave part formed on the weir part. The pad body includes an end part that projects to the weir part. The eave part projects in a horizontal direction from the end part of the pad body. The end part of the pad body includes a flat surface.

THREE-DIMENSIONAL (3D) INTEGRATED CIRCUIT (IC) INTEGRATION OF AN EMBEDDED CHIP AND A PREFORMED METAL ROUTING STRUCTURE

An integrated circuit (IC) package is described. The IC package includes a metallization structure. The IC package also includes a first die in a package substrate layer. The package substrate includes a first surface and a second surface, opposite the first surface. The second surface of the package substrate layer is on the metallization structure. The IC package further includes a second die on the first surface of the package substrate layer and on the first die. The IC package also includes through vias in the package substrate layer to couple pads of the second die to metal routing layers at a first surface of the metallization structure. The IC package further includes package bumps on a second surface of the metallization structure, opposite the first surface, and coupled to the pads of the second die through the metal routing layers. 1. An integrated circuit (IC) package , comprising:a metallization structure;a first die in a package substrate layer having a first surface and a second surface, opposite the first surface, the second surface of the package substrate layer on the metallization structure;a second die on the first surface of the package substrate layer and on the first die, in which a performance level of the second die is greater than a performance level of the first die;through vias in the package substrate layer to couple pads of the second die to metal routing layers at a first surface of the metallization structure; andpackage bumps on a second surface of the metallization structure, opposite the first surface, and coupled to the pads of the second die through the metal routing layers.2. The IC package of claim 1 , in which a first surface of the first die is coplanar with the first surface of the package substrate layer.3. The IC package of claim 1 , in which a surface of the first die is directly bonded to a surface of the second die.4. (canceled)5. The IC package of claim 1 , in which the second die comprises a logic die and the first ...

METHOD OF FINISHING A METALLIC CONDUCTIVE LAYER

A process for finishing a conductive metallic layer (e.g. a layer of copper metal) involves coating a molecular silver ink on the conductive metallic layer and decomposing the silver ink to form a solderable coating of silver metal on the conductive metallic layer. The molecular silver ink includes a silver carboxylate, a carrier and a polymeric binder. The process is additive and enables the cost-effective formation of a silver metal finish on conductive metallic layers, which both protects the conductive metallic layer from oxidation and further corrosion and allows soldering with lead and lead-free solders. 1. A process for finishing a conductive metallic layer , the process comprising: coating a molecular silver ink on the conductive metallic layer , the molecular silver ink comprising a silver carboxylate , a carrier and a polymeric binder; and , decomposing the silver ink to form a solderable coating of silver metal on the conductive metallic layer.2. A process for soldering on a conductive metallic layer , the process comprising: coating a molecular silver ink on a conductive metallic layer , the molecular silver ink comprising a silver carboxylate , a carrier and a polymeric binder; decomposing the silver ink to form a solderable coating of silver metal on the conductive metallic layer; and , applying a solder to the solderable silver metal coated on the conductive metallic layer to form a solder joint with the silver metal.3. The process according to or , wherein the conductive metallic layer comprises copper , gold , tin , palladium , aluminum or an alloy thereof.4. The process according to any one of to , wherein the polymeric binder comprises polyester , polyimide , polyether imide , polyether or any mixture thereof.5. The process according to any one of to , wherein the polymeric binder comprises functional groups that render the polymeric binder compatible with the carrier.6. The process according to any one of to , wherein the polymeric binder ...

COPPER ELECTROPLATING COMPOSITIONS AND METHODS OF ELECTROPLATING COPPER ON SUBSTRATES

Copper electroplating compositions which include an imidazole compound enables the electroplating of copper having uniform morphology on substrates. The composition and methods of enable copper electroplating of photoresist defined features. Such features include pillars, bond pads and line space features. 2: The composition of claim 1 , wherein the one or more imidazole compounds are in amounts of 0.25 ppm to 1000 ppm.3: The composition of claim 1 , wherein R claim 1 , R claim 1 , R claim 1 , R claim 1 , Rand Rare independently chosen from hydrogen; and (C-C)alkyl.4: The composition of claim 3 , wherein R claim 3 , R claim 3 , Rand Rare independently chosen from hydrogen; and methyl; and Rand Rare hydrogen.59-. (canceled) The present invention is directed to copper electroplating compositions and methods of electroplating copper on substrates, wherein the copper electroplating compositions include an imidazole compound to provide copper deposits having uniform morphology. More specifically, the present invention is directed to copper electroplating compositions and methods of electroplating copper on substrates, wherein the copper electroplating compositions include an imidazole compound to provide copper deposits having uniform morphology and wherein the copper electroplating compositions and copper electroplating methods can be used to electroplate photoresist defined features.Photoresist defined features include copper pillars and redistribution layer wiring such as bond pads and line space features for integrated circuit chips and printed circuit boards. The features are formed by the process of lithography where a photoresist is applied to a substrate such as a semiconductor wafer chip often referred to as a die in packaging technologies, or epoxy/glass printed circuit boards. In general, the photoresist is applied to a surface of the substrate and a mask with a pattern is applied to the photoresist. The substrate with the mask is exposed to radiation such as ...

Test Fixture with Sintered Connections Between Mother Board and Daughter Board

A test fixture includes a mother board that has test signal lines configured to couple to a test station. The mother board includes a recessed region with contact pads coupled to the test signal lines. A daughter board is engaged with the recessed region such that a top surface of the daughter board is approximately coplanar with a top surface of the mother board. The daughter board includes test signal lines coupled to contact pads on the daughter board. The contact pads on the daughter board align with the contact pads on the mother board and are permanently coupled by sintered bonds.

Method for manufacturing electrical interconnection structure

Provided is a method of manufacturing an electrical connection structure which includes a female connection structure having an inner conductive material inside an insertion hole of a female connection member, and a male connection structure having a conductive column configured to be inserted into and fixed to the insertion hole to be in contact with the inner conductive material, and formed to protrude from a male connection member. The method includes preparing insulating members used for the female connection member and the male connection member, and forming the inner conductive material and the column by patterning a conductive material on each of the insulating member using a photolithography process.

DEPOSITING BULK OR MICRO-SCALE ELECTRODES

Thicker electrodes are provided on microelectronic device using thermo-compression bonding. A thin-film electrical conducting layer forms electrical conduits and bulk depositing provides an electrode layer on the thin-film electrical conducting layer. An insulating polymer layer encapsulates the electrically thin-film electrical conducting layer and the electrode layer. Some of the insulating layer is removed to expose the electrode layer. 1. A method of fabricating or depositing electrode materials , comprising the steps of:depositing an electrically insulating polymer layer on a substrate,depositing a thin-film electrical conducting layer to form electrical conduits connecting,bulk depositing an electrode layer on said thin-film electrical conducting layer,depositing an encapsulating electrically insulating polymer layer on said thin-film electrical conducting layer and said electrode layer,removing some of said insulating layer covering said electrode layer, andreleasing the electrode materials from said substrate.2. The method of fabricating or depositing electrode materials of wherein said step of bulk depositing an electrode layer on said thin-film electrical conducting layer comprises bulk depositing a metal electrode layer on said thin-film electrical conducting layer.3. The method of fabricating or depositing electrode materials of wherein said step of bulk depositing an electrode layer on said thin-film electrical conducting layer comprises bulk depositing a conducting polymer electrode layer on said thin-film electrical conducting layer.4. The method of fabricating or depositing electrode materials of wherein said step of bulk depositing an electrode layer on said thin-film electrical conducting layer is accomplished using a combination of pressure claim 1 , elevated temperature and ultrasonic energy to bond said electrode layer to said thin-film electrical conducting layer.5. The method of fabricating or depositing electrode materials of wherein said ...

WIRING BOARD

A wiring board includes an electronic component; an insulating layer containing the electronic component therein, and including a via hole that is open at one surface of the insulating layer to expose an electrode of the electronic component; a first wiring layer embedded in the insulating layer, one surface of the first wiring layer being exposed at the one surface of the insulating layer; a second wiring layer including a wiring pattern formed on the one surface of the first wiring layer, and a via wiring extended from the wiring pattern to be extended in the via hole and directly connected to an electrode of the electronic component. 1. A wiring board comprising:an electronic component;an insulating layer containing the electronic component therein, and including a via hole that is open at one surface of the insulating layer to expose an electrode of the electronic component;a first wiring layer embedded in the insulating layer, one surface of the first wiring layer being exposed at the one surface of the insulating layer; a wiring pattern formed on the one surface of the first wiring layer, and', 'a via wiring extended from the wiring pattern to be extended in the via hole and directly connected to an electrode of the electronic component., 'a second wiring layer including'}2. The wiring board according to claim 1 ,wherein the first wiring layer is formed to be positioned above the electrode of the electronic component, andwherein the via hole is formed to penetrate the first wiring layer that is positioned above the electrode of the electronic component, and penetrate the insulating layer positioned between the first wiring layer and the electrode of the electronic component.3. The wiring board according to claim 1 , wherein the second wiring layer includesa first layer directly formed on the one surface of the first wiring layer and including a through-hole that communicates with the via hole,a second layer formed on the first layer to be extended from above ...

POWER OVER DATA LINE (PODL) BOARD DESIGN METHOD TO IMPROVE DATA CHANNEL PERFORMANCE

Aspects of the disclosure provide for a system for a power over data line (PoDL) system. The system includes a ground plane that has a cutout. In addition, an alternating current (AC) capacitor pad configured to establish a bidirectional data channel. The AC capacitor pad is positioned in the cutout of the ground plane. Similarly, a PoDL pad connected to one or more inductors and a direct current (DC) power source is positioned in the cutout of the ground plane and is in series with the AC capacitor pad. 1. A system comprising:a ground plane including a cutout;an alternating current (AC) capacitor pad configured to establish a data channel, the AC capacitor pad being positioned in the cutout of the ground plane; anda power over data line (PoDL) pad positioned in the cutout of the ground plane and being in series with the AC capacitor pad.2. The system of claim 1 , wherein the PoDL pad is connected to a plurality of inductors and a power source.3. The system of claim 1 , further comprising a cable connecting the AC capacitor pad and the PoDL pad in series claim 1 , the cutout of the ground plane being located between a first end of the cable and a second end of the cable.4. The system of claim 3 , further comprising one or more computing devices at the first end of the cable claim 3 , the one or more computing devices being configured to transmit data at a rate of 4 Gbps or greater along the channel.5. The system of claim 4 , wherein the one or more computing devices are a serializer.6. The system of claim 3 , further comprising one or more computing devices at the second end of the cable claim 3 , the one or more computing devices being configured to process data received via the data channel.7. The system of claim 6 , wherein the one or more computing devices are a deserializer.8. The system of claim 3 , wherein the cutout has a size wherein an impedance at the AC capacitor pad and the PoDL pad within the cutout match or closely match an impedance at a point of the ...

SANDWICH-MOLDED CORES FOR HIGH-INDUCTANCE ARCHITECTURES

Embodiments include package substrates and method of forming the package substrates. A package substrate includes a first encapsulation layer over a substrate, and a second encapsulation layer below the substrate. The package substrate also includes a first interconnect and a second interconnect vertically in the first encapsulation layer, the second encapsulation layer, and the substrate. The first interconnect includes a first plated-through-hole (PTH) core, a first via, and a second via, and the second interconnect includes a second PTH core, a third via, and a fourth via. The package substrate further includes a magnetic portion that vertically surrounds the first interconnect. The first PTH core has a top surface directly coupled to the first via, and a bottom surface directly coupled to the second via. The second PTH core has a top surface directly coupled to the third via, and a bottom surface directly coupled to the fourth via. 1. A package substrate , comprising:a first encapsulation layer over a substrate;a second encapsulation layer below the substrate;a first interconnect and a second interconnect vertically in the first encapsulation layer, the second encapsulation layer, and the substrate, wherein the first interconnect includes a first plated-through-hole (PTH) core, a first via, and a second via, and wherein the second interconnect includes a second PTH core, a third via, and a fourth via; anda magnetic portion vertically surrounds the first interconnect, wherein the first PTH core has a top surface directly coupled to the first via, and a bottom surface directly coupled to the second via, and wherein the second PTH core has a top surface directly coupled to the third via, and a bottom surface directly coupled to the fourth via.2. The package substrate of claim 1 , wherein each of the first and second encapsulation layers is a photoimageable mold layer claim 1 , and wherein the first and second interconnects vertically extend from a bottom surface of ...

METHOD FOR PRODUCING ELECTRONIC COMPONENT, BUMP-FORMED PLATE-LIKE MEMBER, ELECTRONIC COMPONENT, AND METHOD FOR PRODUCING BUMP-FORMED PLATE-LIKE MEMBER

The present invention provides a method for producing an electronic component, capable of simply and efficiently producing an electronic component having both of a via electrode(s) (bump(s)) and a plate-like member. The method is a method for producing an electronic component. The electronic component includes: a substrate , a chip(s) , a resin , a plate-like member having a surface(s), a bump(s) that includes a deformable portion A, and a wiring pattern . The method includes: disposing the chip(s) on the surface(s); and encapsulating the bump(s) in the resin . The encapsulating includes: encapsulating the chip(s) in the resin between a bump -formed surface of the plate-like member on which the bump(s) is formed and a wiring pattern -formed surface of the substrate on which the wiring pattern is formed; and causing the bump(s) to be in contact with the wiring pattern

CORELESS PACKAGING SUBSTRATE AND FABRICATION METHOD THEREOF

A coreless packaging substrate is provided, which includes: a dielectric layer having opposite first and second surfaces; a first circuit layer embedded in the dielectric layer and exposed from the first surface of the dielectric layer, wherein the first circuit layer has a plurality of first conductive pads; a plurality of protruding elements formed on the first conductive pads, respectively, wherein each of the protruding elements has contact surfaces to be encapsulated by an external conductive element; a second circuit layer formed on the second surface of the dielectric layer; and a plurality of conductive vias formed in the dielectric layer for electrically connecting the first circuit layer and the second circuit layer. The present invention strengthens the bonding between the first conductive pads and the conductive elements due to a large contact area between the protruding elements and the conductive elements.

Printed wiring board and method for manufacturing the same

A printed wiring board includes an insulation layer, a first conductive layer embedded into first surface of the insulation layer, a second conductive layer formed on second surface of the insulation layer, a via conductor penetrating through the insulation layer and electrically connecting the first and second layers, and a solder-resist layer covering the first layer and having an opening structure forming an exposed structure of the first layer. The exposed structure is formed to connect an electronic component to the first layer, and the first layer has a barrier-metal layer and a metal layer on the first layer such that the barrier-metal layer is on surface of the first layer and includes metal different from metal forming the metal layer and that the metal layer is on surface of the barrier-metal layer in the exposed structure and protruding from the first surface of the insulation layer.

Substrate for semiconductor package and process for manufacturing

A semiconductor package substrate includes a core portion, an upper circuit layer and a plurality of pillars. The pillars are disposed on and project upward from the upper circuit layer. Top surfaces of the pillars are substantially coplanar. The pillars provide an electrical interconnect to a semiconductor die. Solder joint reliability as between the substrate and the semiconductor die is improved.

Carrier-Attached Copper Foil, Laminate, Laminate Producing Method, Printed Wiring Board Producing Method, And Electronic Device Producing Method

Provided herein is a carrier-attached copper foil having desirable laser drillability through an ultrathin copper layer, preferred for fabrication of a high-density integrated circuit substrate. The carrier-attached copper foil includes an interlayer and an ultrathin copper layer that are provided in this order on one or both surfaces of a carrier. The surface roughness Sz and the surface roughness Sa on the interlayer side of the ultrathin copper layer satisfy Sz≦3.6 μm, and Sz/Sa≦14.00 as measured with a laser microscope in case of detaching the carrier from the carrier-attached copper foil according to JIS C 6471 after the carrier-attached copper foil is laminated to an insulating substrate from the ultrathin copper layer side under a pressure of 20 kgf/cm 2 and heated at 220° C. for 2 hours. GMD, which is a 60-degree glossiness of the ultrathin copper layer surface on the interlayer side in MD direction, satisfies GMD≦150 in case of detaching the carrier from the carrier-attached copper foil according to JIS C 6471 after the carrier-attached copper foil is laminated using the same procedure.

MOUNTING SUBSTRATE, MANUFACTURING METHOD FOR THE SAME, AND COMPONENT MOUNTING METHOD

A mounting substrate includes a through-hole formed in a substrate , a first land part , a second land part , a first component attaching part , a second component attaching part , a conductive layer , and a filling member filled into a part of the through-hole . A shortest distance allowable value Lfrom the center of the first land part to a component is determined on the basis of the volume Vof a part of the through-hole positioned above a top surface of the filling member on the side of the first land part , the length Lof the component to be mounted to the first component attaching part , and the maximum allowable value of the inclination of the component to be mounted to the first component attaching part relative to the first surface of the substrate 1. A mounting substrate comprising:a through-hole configured to be formed in a substrate;a first land part configured to be formed on a first surface of the substrate and surround the through-hole;a second land part configured to be formed on a second surface of the substrate opposed to the first surface and surround the through-hole;a first component attaching part configured to be formed on the first surface of the substrate and be connected to the first land part;a second component attaching part configured to be formed on the second surface of the substrate and be connected to the second land part;a conductive layer configured to be formed on an inner wall of the through-hole and communicate the first land part with the second land part; anda filling member configured to be filled into a part of the through-hole, whereina shortest distance allowable value from the center of the first land part to a component is determined on the basis of a volume of a part of the through-hole positioned above a top surface of the filling member on the side of the first land part, a length of a component to be mounted to the first component attaching part, and an inclination of the component to be mounted to the first component ...

CIRCUIT BOARD ASSEMBLY AND METHOD OF MANUFACTURING SAME

The circuit board assembly includes a first circuit board having a first plurality of electronic components attached to a major surface of the first circuit board. The first plurality of electronic components is electrically interconnected to a first plurality of conductive pads defined on the major surface of the first circuit board. A second circuit board has a second plurality of electronic components attached to a first major surface of the second circuit board. The second plurality of electronic components is electrically interconnected to a second plurality of conductive pads defined on a second major surface of the second circuit board. The first and second circuit board are attached by coupling the first and second plurality of conductive pads. A portion of the first plurality of electronic components on the first circuit board are disposed within a cavity defined by the second major surface of the second circuit board. 1. A circuit board assembly , comprising:a first circuit board having a first plurality of electronic components attached to a major surface of the first circuit board and electrically interconnected by conductive traces with a first plurality of conductive pads defined on the major surface of the first circuit board; anda second circuit board having a second plurality of electronic components attached to a first major surface of the second circuit board and electrically interconnected to a second plurality of conductive pads defined on a second major surface of the second circuit board opposite the first major surface, wherein the first plurality of conductive pads are electrically and mechanically coupled to the second plurality of conductive pads and wherein a portion of the first plurality of electronic components are disposed within a cavity defined by the second major surface.2. The assembly according to claim 1 , wherein the cavity is characterized as a channel in the second major surface extending from a first minor surface of the ...

Methods of fluxless micro-piercing of solder balls, and resulting devices

A method of establishing conductive connections is disclosed. The method includes providing an integrated circuit die having a plurality of solder balls each of which has an oxide layer on an outer surface of the solder ball. The method also includes performing a heating process to heat at least the solder balls and applying a force causing each of a plurality of piercing bond structures on a substrate to pierce one of the solder balls and its associated oxide layer to thereby establish a conductive connection between the solder ball and the piercing bond structure.

Wiring board, electronic apparatus, and method for manufacturing electronic apparatus

A wiring board includes a substrate, an electrode on a surface of the substrate, a wall surface in a ring shape surrounding an outer circumference of the electrode, an upper end of the wall surface is located at a position higher than a surface of the electrode, and a protrusion at the upper end of the wall surface, the protrusion protruding with respect to the wall surface inward of a ring shape defined by the wall surface.

Circuit board and method for manufacturing the same

A circuit board element includes a glass substrate, a first dielectric layer, and a first patterned metal layer. The glass substrate has an edge. The first dielectric layer is disposed on the glass substrate and has a central region and an edge region. The edge region is in contact with the edge of the glass substrate, and the thickness of the central region is greater than the thickness of the edge region. The first patterned metal layer is disposed on the glass substrate and in the central region of the first dielectric layer.

FLUID DISCHARGE DEVICE, FLUID DISCHARGE METHOD, AND FLUID APPLICATION DEVICE

A defect may occur in which as the amount of fluid discharged by a fluid discharge device decreases, a mask is not filled with the fluid even when the fluid is discharged. In order to fill a workpiece with the fluid, it is necessary to replace air in the workpiece corresponding to a discharge part with the fluid. The air in the workpiece is removed in advance, thereby filling the workpiece with the discharged fluid. A fluid discharge device in which, at one end of a discharge head, a suction port for sucking air in the mask on the workpiece, and a fluid discharge device having a discharge nozzle formed thereon for discharging the fluid are formed is used. 1. A fluid discharge device for applying a fluid into a mask on a workpiece of an electronic component , the fluid discharge device comprising:a head part including a tank capable of containing a fluid, and a discharge head, whereinone end of the discharge head is provided with a suction port for sucking air in the mask on the workpiece, and a discharge nozzle for discharging the fluid,the suction port is installed in an advancing direction of the discharge head,the head part further comprises a heater unit for keeping the fluid in the tank at a desired temperature, andduring preparation for fluid discharge, the discharge head moves closer to the workpiece until the discharge head contacts the workpiece, and during the fluid discharge, air in the mask is sucked from the suction port in a state where the discharge head is in contact with the workpiece, and then the fluid is discharged into the mask.2. The fluid discharge device according to claim 1 , wherein the discharge head includes a discharge nozzle and an opening having a slit-like shape as a suction port shape.3. The fluid discharge device according to claim 1 , wherein an extension pipeline to be connected to pressure supply means and a suction extension pipeline to be connected to depressurization supply means are installed at an upper part of the discharge ...

MEMORY CARD AND MEMORY CARD SOCKET

A memory card comprising a first main surface and a second main surface opposing each other, and including a printed circuit board (PCB) constituting the first main surface, the PCB including a plurality of first external connection terminals, the plurality of first external connection terminals exposed on the first main surface, a plurality of memory devices stacked on the PCB, a memory controller configured to control the plurality of memory devices, a molding layer encapsulating the plurality of memory devices and the memory controller, the molding layer constituting the second main surface, and one or more second external connection terminals electrically connected to the memory controller, the one or more second external connection terminals embedded in the molding layer and exposed by the molding layer on the second main surface may be provided. 1. A memory card comprising a first main surface and a second main surface opposing each other , the memory card comprising:a printed circuit board (PCB) establishing the first main surface, the PCB including a plurality of first external connection terminals, the plurality of first external connection terminals exposed on the first main surface;a plurality of memory devices stacked on the PCB;a memory controller configured to control the plurality of memory devices;a molding layer encapsulating the plurality of memory devices and the memory controller, the molding layer establishing the second main surface; andone or more second external connection terminals electrically connected to the memory controller, the one or more second external connection terminals embedded in the molding layer and exposed by the molding layer at the second main surface.2. The memory card of claim 1 , wherein the one or more second external connection terminals comprises:one or more of (i) a pair of data input/output terminals; or (ii) a data input/output terminal having a one-lane structure in which a set of data input terminals and a set ...

Interconnect structure and method of manufacturing the same

A method for manufacturing an interconnect structure is provided. The method includes the following steps. An opening is through a substrate. A low-k dielectric block is formed in the opening. At least one first via is formed through the low-k dielectric block. A first conductor is formed in the first via.

VEHICLE-MOUNTED ELECTRONIC MODULE, CARD EDGE CONNECTOR, AND CONNECTOR

There is a problem that an oxide film or high resistance abrasion powder is formed at the contact interface due to micro sliding abrasion in a high temperature environment or temperature cycle to increase the contact resistance at the contact portion of a non-noble metal connection terminal. Provided is an in-vehicle electronic module, a connector, and a connection structure thereof, which have the same connection reliability as noble metals even when exposed to a harsh environment and can reduce cost of members. 1. An in-vehicle electronic module comprising:a circuit board on which an electronic component is mounted; anda protection member accommodating the circuit board,wherein the circuit board has an end portion of the board protruding into an external space from the protection member,the end portion of the board has a connection terminal on a surface thereof for being inserted into an external female connector to obtain electrical conduction, andthe connection terminal has a structure where a solder layer using Sn as a main component and containing Ag is formed on an outermost surface of a Cu wire line.2. The in-vehicle electronic module according to claim 1 , wherein the solder layer has an average thickness of 4 μm or more.3. The in-vehicle electronic module according to claim 1 , wherein an Ag—Sn intermetallic compound in a size having a grain size of 1 μm or more is dispersed in the solder layer on the outermost surface of the Cu wire line or is formed in a layer form on a surface of the solder layer.4. An in-vehicle electronic module comprising:a circuit board on which an electronic component is mounted; anda protection member accommodating the circuit board,wherein the circuit board has an end portion of the board protruding into an external space from the protection member,the end portion of the board has a connection terminal on a surface thereof for being inserted into an external female connector to obtain electrical conduction,the connection terminal ...

METHOD FOR PRODUCING A BACKPLANE CIRCUIT BOARD

A process for producing a backplane circuit board () having an internal face () adapted to be connected to connectors () of circuit boards () and an external face () adapted to be connected to an external connector (), blind holes () opening on the internal face () and external face () of the backplane circuit board (), wherein bonding layers () having zones () cleared of material facing the blind holes are used between the printed circuits (). 1. A process for producing a backplane circuit board having an internal face adapted to be connected to connectors of circuit boards and an external face adapted to be connected to an external connector , a series of first blind holes opening on the one hand on the internal face of the backplane circuit board and a series of second blind holes opening on the other hand on the external face of the backplane circuit board , the backplane circuit board comprising:a first printed circuit having a first face and a second face designed to form the internal face of the backplane circuit board;a second printed circuit having a first face and a second face designed to form the external face of the backplane circuit board and;a third printed circuit having a first face facing the first face of the first printed circuit and a second face facing the first face of the second printed circuit, the third printed circuit constituting an electrical insulator between its first face and its second face, said first blind holes passing through the first printed circuit but not passing through the third printed circuit and said second blind holes passing through the second printed circuit but not passing through the third printed circuit;wherein the process comprises the following steps:depositing on the first face of the third printed circuit of a first bonding layer, said first bonding layer having first zones cleared of material distributed on the first face of the third printed circuit, and depositing on the second face of the third printed ...

METHOD FOR MANUFACTURING INTERPOSER

A method for manufacturing an interposer to connect boards or elements with different pin or pad spacings comprises following steps. A mold with first and second plates is provided. The first plate defines a plurality of first units with a plurality of first holes, the second plate defines a plurality of second units with a plurality of second holes. Space between central lines of adjacent first holes is different from that of adjacent second holes. Conducting wires pass through the first holes and the second holes, and molding compound is injected into the mold to keep the conducting wires in place. A molded plate defining a plurality of plate units is thereby formed, and molded pieces constituting interposers are obtained by cutting the molded plate. 1. A method for manufacturing an interposer comprising:providing a mold comprising a first plate and a second plate disposed therein, the first plate defining a plurality of first units spaced away from each other, the second plate defining a plurality of second units respectively corresponding to the plurality of first units, each of the first units defining a plurality of first holes, each of the second units defining a plurality of second holes respectively corresponding to the plurality of first holes, a space between central lines of adjacent first holes being different from a space between central lines of two second holes corresponding to the adjacent first holes;providing a plurality of conducting wires, each of the conducting wires passing through the first hole and the corresponding second hole and being fixed to the first plate and the second plate;injecting molding compound into the mold;forming a molded plate, the molded plate comprising the molding compound and the plurality of conducting wires embedded into the molding compound;removing the mold from the molded plate;forming a plurality of molded pieces by cutting the molded plate; andforming a plurality of interposers.2. The method of claim 1 , wherein ...

CIRCUIT BOARD

The present invention relates to a circuit board including: a base board having a circuit region and a terminal region; a circuit pattern formed on an upper portion of the base board; and a low-melting-metal layer formed on an upper portion of the circuit pattern. A circuit board capable of reducing manufacturing time and manufacturing costs may be manufactured by omitting a photoresist process. 1. A circuit board comprising:a base board having a circuit region and a terminal region;a circuit pattern formed on an upper portion of the base board; anda low-melting-metal layer formed on an upper portion of the circuit pattern.2. The circuit board of claim 1 , wherein the low-melting-metal layer includes a first low-melting-metal layer disposed in the circuit region; a second low-melting-metal layer disposed in the terminal region; and a third low-melting-metal layer disposed in the circuit region so as to be adjacent to the terminal region.3. The circuit board of claim 1 , wherein the low-melting-metal layer is made of a metal melted in a temperature range of 100° C. and 250° C.4240. The circuit board of claim 1 , wherein the second low-melting-metal layer is heat-treated and forms a soldering portion claim 1 , and the third low-melting-metal layer is heat-treated claim 1 , such that a melted portion of the third low-melting-metal layer moves to the second low-melting-metal layer () to form the soldering portion.5. The circuit board of claim 4 , wherein the third low-melting-metal layer has an inclined surface.6. A method of manufacturing a circuit board claim 4 , the method comprising:providing a base board having a circuit region and a terminal region;forming a circuit pattern on an upper portion of the base board;forming a low-melting-metal layer which includes a first low-melting-metal layer disposed in the circuit region, a second low-melting-metal layer disposed in the terminal region, and a third low-melting-metal layer disposed in the circuit region so as to be ...

METHOD FOR MANUFACTURING TOUCH-PANEL CONDUCTIVE SHEET, AND TOUCH-PANEL CONDUCTIVE SHEET

An object of the invention is to provide a method for more easily manufacturing a touch-panel conductive sheet in which end portions of lead-out wires are collected on one surface side of a substrate with high productivity, and a touch-panel conductive sheet. The method for manufacturing a touch-panel conductive sheet of the invention includes: forming, on a rear surface of a substrate, first detection electrodes and rear surface-side wires of which one ends are electrically connected to the first detection electrodes and the other ends have first pad portions, and on a front surface of the substrate, second detection electrodes, second lead-out wires which are electrically connected to the second detection electrodes, and second pad portions which are arranged at positions opposed to the first pad portions via the substrate; forming through holes penetrating the first pad portions, the substrate, and the second pad portions; and producing through wires which electrically connect the first pad portions and the second pad portions by filling the through holes with a conductive material to form first lead-out wires which include the rear surface-side wires and the through wires and are electrically connected to the first detection electrodes. 1. A method for manufacturing a touch-panel conductive sheet , comprising:forming, on a rear surface of a substrate, first detection electrodes and rear surface-side wires of which one ends are electrically connected to the first detection electrodes and the other ends have first pad portions, and on a front surface of the substrate, second detection electrodes, second lead-out wires which are electrically connected to the second detection electrodes, and second pad portions which are arranged at positions opposed to the first pad portions via the substrate;forming through holes penetrating the first pad portions, the substrate, and the second pad portions; andproducing through wires which electrically connect the first pad ...

SPACE TRANSFORMER AND MANUFACTURING METHOD THEREOF

A space transformer for connecting a signal source and probing a semiconductor wafer and a manufacturing method thereof are provided. The space transformer includes a circuit board including a wiring structure, a redistribution structure bonded to the circuit board and including second contact pads configured to probe the semiconductor wafer, a conductive through via penetrating through the circuit board and providing a vertical conductive path between the circuit board and redistribution structure. A plurality of first contact pads of the wiring structure is configured to connect the signal source. The redistribution structure is thinner than the circuit board, wherein a pitch of the adjacent second contact pads is finer than that of the adjacent first contact pads. 1. A space transformer for connecting a signal source and probing a semiconductor wafer , the space transformer comprising:a circuit board comprising a wiring structure, a plurality of first contact pads of the wiring structure configured to connect the signal source;a redistribution structure bonded to the circuit board and comprising a plurality of second contact pads, the second contact pads configured to probe the semiconductor wafer, the redistribution structure being thinner than the circuit board, wherein a pitch of the adjacent second contact pads is finer than that of the adjacent first contact pads; anda conductive through via penetrating through the circuit board and providing a vertical conductive path between the circuit board and redistribution structure.2. The space transformer according to claim 1 , wherein the redistribution structure further comprises a patterned dielectric layer having an outer surface substantially leveled with outer surfaces of the second contact pads.3. The space transformer according to claim 1 , wherein the wiring structure of the circuit board comprises a first conductive via connected to the first contact pads claim 1 , the redistribution structure comprises a ...

CARRIER SUBSTRATE AND METHOD OF MANUFACTURING PRINTED CIRCUIT BOARD USING THE SAME

There are provided a carrier substrate including: a first metal layer; a barrier layer formed on one surface of the first carrier metal layer; and a second metal layer formed on one surface of the barrier layer, and a method of manufacturing a printed circuit board using the same. 1. A carrier substrate comprising:a first metal layer;a barrier layer formed on one surface of the first carrier metal layer; anda second metal layer formed on one surface of the barrier layer.2. The carrier substrate of claim 1 , further comprising:a carrier core, andthe first metal layer is formed on one surface or both surfaces of the carrier core.3. The carrier substrate of claim 1 , wherein the barrier layer is made of a material different from those of the first metal layer and the second metal layer.4. The carrier substrate of claim 1 , wherein the barrier layer is made of a material which does not react with an etching solution reacting with the first metal layer and the second metal layer.5. A method of manufacturing a printed circuit board comprising:preparing a carrier substrate including a first metal layer, a second metal layer, and a barrier layer formed between the first metal layer and the second metal layer;forming circuit patterns on one surface of the second metal layer;forming an insulation layer on one surface of the second metal layer to bury the circuit patterns;removing the first metal layer;patterning the barrier layer; andforming a bump pad by removing the second metal layer exposed to the outside through the barrier layer.6. The method of claim 5 , wherein in the preparing of the carrier substrate claim 5 , the carrier substrate further includes a carrier core claim 5 , and the first metal layer is formed on one surface or both surfaces of the carrier core.7. The method of claim 5 , wherein in the preparing of the carrier substrate claim 5 , the barrier layer is made of a material different from those of the first metal layer and the second metal layer.8. The ...

Embedded board and method of manufacturing the same

An embedded board and a method of manufacturing the same are provided. The embedded board includes a core substrate below which a mounting pad is formed, a first substrate formed below the core substrate and having a first cavity formed therein, and a second substrate formed below the first substrate and having a second cavity formed therein. The first cavity and the second cavity are connected to each other and externally expose the mounting pad.

WIRING BOARD WITH BUILT-IN ELECTRONIC COMPONENT AND METHOD FOR MANUFACTURING THE SAME

A wiring board with a built-in electronic component includes a substrate having a cavity, an electronic component accommodated in the cavity, a conductive layer formed on the substrate and extending over the electronic component in the cavity, and a solder-resist layer formed on the conductive layer and having first and second openings such that the first openings are forming first pads including the conductive layer exposed by the first openings and that the second openings are forming second pads including the conductive layer exposed by the second openings. The second pads include portions of the conductive layer formed directly over the electronic component, respectively, and connected to the electronic component, the first pads include portions of the conductive layer formed on outer side with respect to the electronic component, respectively, and each second opening has an opening diameter which is formed smaller than an opening diameter of each first opening. 1. A wiring board with a built-in electronic component , comprising:a substrate having a cavity;an electronic component accommodated in the cavity of the substrate;a conductive layer formed on the substrate such that the conductive layer is extending over the electronic component in the cavity of the substrate; anda solder-resist layer formed on the conductive layer and having a plurality of first opening portions and a plurality of second opening portions such that the plurality of first opening portions is forming a plurality of first conductive pads comprising the conductive layer exposed by the plurality of first opening portions and that the plurality of second opening portions is forming a plurality of second conductive pads comprising the conductive layer exposed by the plurality of second opening portions,wherein the plurality of second conductive pads is formed such that the plurality of second conductive pads comprises a plurality of portions of the conductive layer formed directly over the ...

Integrated Circuit Package Assembly Comprising a Stack of Slanted Integrated Circuit Packages

Embodiments of the present invention are directed to an integrated circuit (IC) package assembly. The IC package assembly includes a base printed circuit board (PCB), and a set of IC packages. Each of the IC packages includes at least one IC chip, mounted on or partly in a support component, which mechanically supports and electrically connects to the IC chip. In addition, each of the IC packages is laterally soldered to the base PCB (e.g., a motherboard PCB) and arranged transversally to the base PCB and forms an angle α therewith. As a result, a slanted stack of IC packages is obtained, wherein the IC packages are essentially parallel to each other. Further embodiments are directed to related devices, including the above assembly, and to related fabrication methods.

ELECTROCONDUCTIVE SUBSTRATE, ELECTRONIC DEVICE AND DISPLAY DEVICE

An electroconductive substrate, including: a base material; a foundation layer disposed on the base material; a trench formation layer disposed on the foundation layer, and an electroconductive pattern layer including metal plating. A trench including a bottom surface to which the foundation layer is exposed, is formed. The trench is filled with the electroconductive pattern layer. The foundation layer includes a mixed region which is formed from a surface of the foundation layer on the electroconductive pattern layer side towards the inside thereof, and contains metal particles which contain a metal configuring the electroconductive pattern layer, and enter the foundation layer. 1. An electroconductive substrate , comprising:a base material;a foundation layer which is disposed on the base material and contains a catalyst;a trench formation layer disposed on the foundation layer; andan electroconductive pattern layer including metal plating,wherein a trench including a bottom surface to which the foundation layer is exposed, and a lateral surface which includes a surface of the trench formation layer, is formed,the trench is filled with the electroconductive pattern layer, andthe foundation layer includes a mixed region which is formed from a surface of the foundation layer on the electroconductive pattern layer side towards the inside thereof, and contains metal particles containing a metal configuring the electroconductive pattern layer, and entering the foundation layer.2. The electroconductive substrate according to claim 1 ,wherein a ratio of a thickness of the mixed region to a thickness of the foundation layer is 0.1 to 0.9.3. The electroconductive substrate according to claim 1 ,wherein a width of the electroconductive pattern layer is 0.3 μm to 5.0 μm, and a ratio of the thickness of the electroconductive pattern layer to the width of the electroconductive pattern layer is 0.1 to 10.0.4. The electroconductive substrate according to claim 1 ,wherein surface ...

Embedded 3D Interposer Structure

A device includes an interposer, which includes a substrate; and at least one dielectric layer over the substrate. A plurality of through-substrate vias (TSVs) penetrate through the substrate. A first metal bump is in the at least one dielectric layer and electrically coupled to the plurality of TSVs. A second metal bump is over the at least one dielectric layer. A die is embedded in the at least one dielectric layer and bonded to the first metal bump. 1. A method comprising:attaching a device die to a first dielectric layer through an adhesive film, wherein the first dielectric layer covers a first plurality of redistribution lines, and the first plurality of redistribution lines comprise a first conductive feature;forming a second dielectric layer encapsulating the device die therein;forming a through-via, wherein the through-via penetrates through the second dielectric layer; and a second conductive feature electrically coupling to the first conductive feature through the through-via; and', 'a third conductive feature electrically coupling to the device die., 'forming a second plurality of redistribution lines over the second dielectric layer, wherein the second plurality of redistribution lines comprise2. The method of claim 1 , wherein in a same process for forming the through-via claim 1 , an additional via is formed underlying the through-via and extending into the first dielectric layer to contact the first conductive feature.3. The method of claim 1 , wherein the forming the through-via comprises:etching the second dielectric layer and the first dielectric layer to form an opening; andfilling the opening with a metallic material.4. The method of further comprising: a semiconductor substrate;', 'a through-substrate via penetrating through the semiconductor substrate; and', 'the first plurality of redistribution lines, wherein the first conductive feature in the first plurality of redistribution lines is electrically coupled to the through-substrate via., ' ...

METHOD OF ELECTROPLATING PHOTORESIST DEFINED FEATURES FROM COPPER ELECTROPLATING BATHS CONTAINING REACTION PRODUCTS OF IMIDAZOLE AND BISEPOXIDE COMPOUNDS

Electroplating methods enable the plating of photoresist defined features which have substantially uniform morphology. The electroplating methods include copper electroplating baths with reaction products of imidazole and bisepoxides to electroplate the photoresist defined features. Such features include pillars, bond pads and line space features. 1. A method of electroplating photoresist defined features comprising:a) providing a substrate comprising a layer of photoresist, wherein the layer of photoresist comprises a plurality of apertures;b) providing a copper electroplating bath comprising one or more reaction products of one or more imidazole compounds and one or more bisepoxides; an electrolyte; one or more accelerators; and one or more suppressors;c) immersing the substrate comprising the layer of photoresist with the plurality of apertures in the copper electroplating bath; andd) electroplating a plurality of copper photoresist defined features in the plurality of apertures, the plurality of photoresist defined features comprise an average % TIR of 5% to 8%.2. The method of claim 1 , wherein a % WID of the plurality of photoresist defined features is from 5% to 12%.4. The method of claim 3 , wherein R claim 3 , Rand Rare independently chosen from hydrogen and (C-C)alkyl.6. The method of claim 1 , wherein the reaction product is in amounts of 0.25 ppm to 20 ppm.7. The method of claim 1 , wherein electroplating is done at a current density of 0.25 ASD to 40 ASD.8. The method of claim 1 , wherein the one or more copper photoresist defined features are pillars claim 1 , bond pads or line space features.9. An array of photoresist defined features on a substrate comprising an average % TIR of 5% to 8% and a % WID of 5% to 12%. The present invention is directed to a method of electroplating photoresist defined features from copper electroplating baths which include reaction products of imidazole and bisepoxide compounds. More specifically, the present invention is ...

METHOD OF ELECTROPLATING PHOTORESIST DEFINED FEATURES FROM COPPER ELECTROPLATING BATHS CONTAINING REACTION PRODUCTS OF ALPHA AMINO ACIDS AND BISEPOXIDES

Electroplating methods enable the plating of photoresist defined features which have substantially uniform morphology. The electroplating methods include copper electroplating baths with reaction products of α-amino acids and bisepoxides to electroplate the photoresist defined features. Such features include pillars, bond pads and line space features. 1. A method comprising:a) providing a substrate comprising a layer of photoresist, wherein the layer of photoresist comprises a plurality of apertures;b) providing a copper electroplating bath comprising one or more reaction products of one or more α-amino acids and one or more bisepoxides; an electrolyte; one or more accelerators; and one or more suppressors;c) immersing the substrate comprising the layer of photoresist with the plurality of apertures in the copper electroplating bath; andd) electroplating a plurality of copper photoresist defined features in the plurality of apertures, the plurality of photoresist defined features comprise an average % TIR of -5% to -1%.2. The method of claim 1 , wherein an average % WID of an array of copper photoresist defined features on the substrate is 12% to 15%.3. The method of claim 1 , wherein the one or more α-amino acids are chosen from arginine and lysine.6. The method of claim 1 , wherein the one or more reaction products are in amounts of 0.25 ppm to 20 ppm in the copper electroplating bath.7. The method of claim 1 , wherein electroplating is done at a current density of 0.25 ASD to 40 ASD.8. The method of claim 1 , wherein the one or more copper photoresist defined features are pillars claim 1 , bond pads or line space features.9. A plurality of photoresist defined features on a substrate comprising an average % TIR of −5% to −1% and an average % WID of 12% to 15%. The present invention is directed to a method of electroplating photoresist defined features from copper electroplating baths which include reaction products of α-amino acids and bisepoxides. More ...

PRINTED WIRING BOARD AND METHOD FOR MANUFACTURING THE SAME

A printed wiring board includes an insulating layer, a first conductor layer embedded into first surface of the insulating layer and including multiple wirings such that the wirings include connecting portions positioned to connect an electronic component, respectively, a second conductor layer projecting from second surface of the insulating layer on the opposite side, a solder resist layer formed on the first surface of the insulating layer such that the solder resist layer is covering the first conductor layer and has an opening structure exposing the connecting portions of the wirings, and multiple metal posts formed on the connecting portions respectively such that each of the metal posts has a width which is larger than a width of a respective one of the wirings having the connecting portions. The wirings are formed such that the connecting portions are positioned side by side on every other adjacent one of the wirings. 1. A printed wiring board , comprising:a resin insulating layer;a first conductor layer embedded into a first surface of the resin insulating layer and comprising a plurality of wirings such that the plurality of wirings includes a plurality of connecting portions positioned to connect an electronic component, respectively;a second conductor layer projecting from a second surface of the resin insulating layer on an opposite side with respect to the first surface of the resin insulating layer;a solder resist layer formed on the first surface of the resin insulating layer such that the solder resist layer is covering the first conductor layer and has an opening structure exposing the connecting portions of the wirings; anda plurality of metal posts formed on the plurality of connecting portions respectively such that each of the metal posts has a width which is larger than a width of a respective one of the wirings having the connecting portions,wherein the plurality of wirings is formed such that the connecting portions are positioned side by ...

Printed wiring board and method for manufacturing printed wiring board

A printed wiring board includes a base insulating layer, a conductor layer formed on the base layer and including first and second pads, a solder resist layer formed on the base layer such that the solder resist layer has first opening exposing the first pad and second opening exposing the second pad with diameter smaller than diameter of the first opening, and bumps including a first bump on the first pad and a second bump on the second pad such that the second bump has diameter smaller than diameter of the first bump. The first bump has a base plating layer formed in the first opening and having raised portion, and a top plating layer formed on the base plating layer, and the second bump has a base plating layer formed in the second opening and having raised portion, and a top plating layer formed on the base plating layer.

Porous alumina templates for electronic packages

Interposers and methods of making the same are disclosed herein. In one embodiment, an interposer includes a region having first and second oppositely facing surfaces and a plurality of pores, each pore extending in a first direction from the first surface towards the second surface, wherein alumina extends along a wall of each pore; a plurality of electrically conductive connection elements extending in the first direction, consisting essentially of aluminum and being electrically isolated from one another by at least the alumina; a first conductive path provided at the first surface for connection with a first component external to the interposer; and a second conductive path provided at the second surface for connection with a second component external to the interposer, wherein the first and second conductive paths are electrically connected through at least some of the connection elements.

CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF

A circuit board including a substrate, a photo imageable dielectric layer and a plurality of conductive bumps is provided. The substrate has a first surface and a first circuit layer, wherein the first surface has a chip disposing area and an electrical connection area, and the first circuit layer is embedded in the first surface. The photo imageable dielectric layer is disposed on the electrical connection area and has a plurality of openings, wherein parts of the first circuit layer is exposed by the openings. The conductive bumps are disposed at the openings respectively and connected to the first circuit layer, wherein a side surface of each of the conductive bumps is at least partially covered by the photo imageable dielectric layer. In addition, a manufacturing method of the circuit board is also provided. 1. A circuit board , comprising:a substrate, having a first surface and a first circuit layer, wherein the first surface has a chip disposing area and an electrical connection area, and the first circuit layer is embedded in the first surface;a photo imageable dielectric layer, disposed on the electrical connection area and having a plurality of openings, wherein the openings expose parts of the first circuit layer; anda plurality of conductive bumps, respectively disposed at the openings, and connected to the first circuit layer, wherein the photo imageable dielectric layer covers at least a part of a side surface of each of the conductive bumps.2. The circuit board as claimed in claim 1 , further comprising:a solder mask layer, disposed on the photo imageable dielectric layer, and covering a part of the side surface of each of the conductive bumps.3. The circuit board as claimed in claim 2 , further comprising:a connection circuit, disposed on the photo imageable dielectric layer and connecting two of the conductive bumps, wherein the solder mask layer covers the connection circuit.4. The circuit board as claimed in claim 1 , wherein each of the conductive ...

METHOD OF ELECTROPLATING PHOTORESIST DEFINED FEATURES FROM COPPER ELECTROPLATING BATHS CONTAINING REACTION PRODUCTS OF PYRIDYL ALKYLAMINES AND BISEPOXIDES

Electroplating methods enable the plating of photoresist defined features which have substantially uniform morphology. The electroplating methods include copper electroplating baths with reaction products of pyridyl alkylamines and bisepoxides to electroplate the photoresist defined features. Such features include pillars, bond pads and line space features. 1. A method for electroplating photoresist defined features comprising:a) providing a substrate comprising a layer of photoresist, wherein the layer of photoresist comprises a plurality of apertures;b) providing a copper electroplating bath comprising one or more reaction products of one or more pyridyl alkylamines and one or more bisepoxides; an electrolyte; one or more accelerators; and one or more suppressors;c) immersing the substrate comprising the layer of photoresist with the plurality of apertures in the copper electroplating bath; andd) electroplating a plurality of copper photoresist defined features in the plurality of apertures, the plurality of photoresist defined features comprise an average % TIR of −5% to +12%.2. The method of claim 1 , wherein a % WID of the plurality of photoresist defined features is from 5% to 14%.6. The method of claim 1 , wherein the one or more reaction products are in amounts of 0.25 ppm to 20 ppm in the copper electroplating bath.7. The method of claim 1 , wherein the one or more photoresist defined features is chosen from a pillar claim 1 , bond pad and line space feature.8. The method of claim 1 , wherein a current density is from 0.25 ASD to 40 ASD.9. An array of photoresist defined features on a substrate comprising an average % TIR of −5% to +12% and a % WID of 5% to 14%. The present invention is directed to a method of electroplating photoresist defined features from copper electroplating baths which include reaction products of pyridyl alkylamines and bisepoxides. More specifically, the present invention is directed to a method of electroplating photoresist defined ...

FABRICATION METHOD OF PACKAGING SUBSTRATE

A packaging substrate is disclosed, which includes: a dielectric layer; a circuit layer embedded in and exposed from a surface of the dielectric layer, wherein the circuit layer has a plurality of conductive pads; and a plurality of conductive bumps formed on the conductive pads and protruding above the surface of the dielectric layer. As such, when an electronic element is disposed on the conductive pads through a plurality of conductive elements, the conductive elements can come into contact with both top and side surfaces of the conductive bumps so as to increase the contact area between the conductive elements and the conductive pads, thereby strengthening the bonding between the conductive elements and the conductive pads and preventing delamination of the conductive elements from the conductive pads. 18-. (canceled)9. A method for fabricating a packaging substrate , comprising the steps of:providing a carrier having a first circuit layer formed thereon, wherein the first circuit layer has a plurality of first conductive pads;forming a dielectric layer on the carrier and the first circuit layer, wherein the dielectric layer has a first surface in contact with and attached to the carrier and a second surface opposite to the first surface;removing the carrier so as to expose a surface of the first circuit layer from the first surface of the dielectric layer; andforming on the first conductive pads a plurality of conductive bumps protruding above the first surface of the dielectric layer.10. The method of claim 9 , wherein the surface of the first circuit layer is flush with or lower than the first surface of the dielectric layer.11. The method of claim 9 , wherein the carrier has a conductive layer that allows the first circuit layer to be formed thereon claim 9 , and the conductive layer is exposed after removing the carrier such that the step of forming the conductive bumps further comprises:forming a metal layer on the conductive layer; andremoving portions of ...

Coaxial copper pillar

A coaxial copper pillar for signal transmission with signal shield is disclosed so that signal integrity for the signal passes transmission is maintained. One embodiment shows at least one coaxial copper pillar is made as a terminal connector for a chip package, the coaxial copper pillars are made adaptive for electrically coupling the chip package to a mother board.

PRINTED WIRING BOARD ASSEMBLY, ELECTRICAL DEVICE, AND METHOD FOR ASSEMBLING PRINTED WIRING BOARD ASSEMBLY

A printed wiring board assembly includes a first board including a first surface; a second board including a second surface and facing the first surface; a plurality of first electrodes formed on a bottom surface of a recess formed in one of the first and the second surfaces; a plurality of second electrodes formed on the one of the first surface and the second surface and positioned outside the recess; a plurality of first solders each coupled to a respective one of the plurality of first electrodes; and a plurality of second solders each coupled to a respective one of the plurality of second electrodes, wherein the plurality of first electrodes are formed at a larger pitch than a pitch at which the plurality of second electrodes are formed, and a size of each the plurality of first solders is larger than a size of the plurality of second solders. 1. A printed wiring board assembly comprising:a first board that includes a first surface;a second board that includes a second surface and faces the first surface;a plurality of first electrodes formed on a bottom surface of a recess, the recess being formed in one of the first surface and the second surface;a plurality of second electrodes formed on the one of the first surface and the second surface, the plurality of second electrodes being positioned outside the recess;a plurality of first solders each coupled to a respective one of the plurality of first electrodes; anda plurality of second solders each coupled to a respective one of the plurality of second electrodes,wherein the plurality of first electrodes are formed at a larger pitch than a pitch at which the plurality of second electrodes are formed, and a size of each the plurality of first solders is larger than a size of the plurality of second solders.2. The printed wiring board assembly according to claim 1 , wherein when the recess is formed in the first surface claim 1 , the recess is positioned to face a central portion of the second board.3. The printed ...

ELECTRICAL CONNECTOR WITH FLEXIBLE CIRCUIT AND STIFFENER

An electrical connector includes a flexible circuit with a flexible material and traces at least partially embedded in the flexible material. The electrical connector further includes a first set of conductive bumps, a second set of conductive bumps, and a stiffener. The first set of conductive bumps is coupled to respective first end portions of the traces and extends from a first side of the flexible circuit. The second set of conductive bumps is coupled to respective second end portions of the traces. The stiffener is coupled to the flexible circuit on a second side of the flexible circuit opposite the first side. 1. An electrical connector assembly comprising: a flexible circuit comprising a flexible material and traces at least partially embedded in the flexible material,', 'a first set of conductive bumps coupled to respective first end portions of the traces and extending from a first side of the flexible circuit,', 'a second set of conductive bumps coupled to respective second end portions of the traces, and', 'a stiffener coupled to the flexible circuit on a second side of the flexible circuit opposite the first side, the stiffener including a body and fingers that extend from the body such that the fingers provide a spring force against the first set of conductive bumps., 'an electrical connector including2. The electrical connector assembly of claim 1 , wherein the conductive bumps of the first set of conductive bumps are circular shaped.3. The electrical connector assembly of claim 1 , wherein the conductive bumps of the first set of conductive bumps are rounded.4. The electrical connector assembly of claim 1 , wherein the first and the second sets of conductive bumps comprise gold.5. The electrical connector assembly of claim 1 , wherein the traces comprise copper.6. The electrical connector assembly of claim 1 , wherein the flexible material comprises a polyimide claim 1 , a polyester claim 1 , or a liquid crystal polymer.7. The electrical connector ...

PRINTED WIRING BOARD AND METHOD FOR MANUFACTURING PRINTED WIRING BOARD

A printed wiring board includes a support plate, a laminate formed on the support plate and including first conductor pads on first surface side of the laminate and first via conductors on second surface side of the laminate, and a solder resist layer interposed between the plate and the laminate and having openings formed such that the openings are exposing the first pads. The laminate has first surface on the first surface side and second surface on the second surface side on the opposite side and includes a first resin insulating layer forming the second surface of the laminate, and the first conductors are formed through the first insulating layer such that the first vias are tapering from the first surface side toward the second surface side of the laminate and have end surfaces recessed from the second surface of the laminate on the second surface side of the laminate. 1. A printed wiring board , comprising:a support plate;a laminate found on the support plate and comprising a plurality of first conductor pads on a first surface side of the laminate and a plurality of first via conductors on a second surface side of the laminate; anda solder resist layer interposed between the support plate and the laminate and having a plurality of openings formed such that the openings are exposing the first conductor pads respectively,wherein the laminate has a first surface on the first surface side and a second surface on the second surface side on an opposite side with respect to the first surface of the laminate and includes a first resin insulating layer forming the second surface of the laminate, and the plurality of first via conductors is formed through the first resin insulating layer such that the first via conductors are tapering from the first surface side toward the second surface side of the laminate and have end surfaces recessed from the second surface of the laminate on the second surface side of the laminate respectively.2. A printed wiring board according ...

PRINTED WIRING BOARD AND METHOD FOR MANUFACTURING PRINTED WIRING BOARD

A printed wiring board includes a support plate, a laminate formed on the support plate and including first conductor pads on first surface side of the laminate and second conductor pads on second surface side of the laminate, and a solder resist layer interposed between the support plate and laminate and having openings formed such that the openings are exposing the first pads. The laminate includes a resin insulating layer and has a first surface on the first surface side and a second surface on the second surface side on the opposite side, and a via conductor structure penetrating from the first surface to the second surface of the laminate such that the via structure includes via conductors formed in the insulating layer and tapering from the first surface side toward second surface side of the laminate, and the second pads are protruding from the second surface of the laminate. 1. A printed wiring board , comprising:a support plate;a laminate formed on the support plate and comprising a plurality of first conductor pads on a first surface side of the laminate and a plurality of second conductor pads on a second surface side of the laminate; anda solder resist layer interposed between the support plate and the laminate and having a plurality of openings formed such that the openings are exposing the first conductor pads respectively,wherein the laminate includes a resin insulating layer and has a first surface on the first surface side and a second surface on the second surface side on an opposite side with respect to the first surface of the laminate, and a via conductor structure penetrating from the first surface to the second surface of the laminate such that the via conductor structure comprises a plurality of via conductors formed in the resin insulating layer and tapering from the first surface side toward the second surface side of the laminate, and the plurality of second conductor pads is protruding from the second surface of the laminate respectively. ...

TRACE ANYWHERE INTERCONNECT

The present invention provides for a method and structure for forming three-dimensionally routed dielectric wires between discrete points on the two or more parallel circuit planes. The wires may be freely routed in three-dimensional space as to create the most efficient routing between the two arbitrarily defined points on the two or more parallel circuit planes. Metalizing the outer surfaces of these three dimensional dielectric wires electrically coupling the discrete wires to their respective discrete contact points. Two or more of these wires may be in intimate contact to one another electrically coupling to each other as well as to two or more discrete contact pads. These electrically coupled contact pads may be on opposite sides or on the same side of the structure and the formed metalized wires may originate on one side and terminate on the other or originate and terminate from the same side. 1. An electrical interconnect mechanism comprising:two or more discrete contact points such as but not limited to circuit pads within two or more circuit planes; andthree-dimensional dielectric wires routed between said discrete points on said two or more circuit planes in order to provide electrical coupling of two or more electrical devices through said interconnect mechanism, said dielectric wires having an electrically conductive coating.2. The interconnect mechanism to wherein said circuit planes are substantially parallel to each other.3. The interconnect mechanism according to further comprising outer surfaces of said dielectric wires being metalized for electrically coupling to their respective discrete contact points with any conductive material organic or inorganic.4. The interconnect mechanism according to wherein said conductive material is copper claim 3 , silver claim 3 , gold claim 3 , or conductive polymer.5. The interconnect mechanism according to further comprising placing two or more of said wires placed into intimate contact with one another ...

TRACE ANYWHERE INTERCONNECT

The present invention provides for a method and structure for forming three-dimensionally routed dielectric wires between discrete points on the two or more parallel circuit planes. The wires may be freely routed in three-dimensional space as to create the most efficient routing between the two arbitrarily defined points on the two or more parallel circuit planes. Metalizing the outer surfaces of these three dimensional dielectric wires electrically coupling the discrete wires to their respective discrete contact points. Two or more of these wires may be in intimate contact to one another electrically coupling to each other as well as to two or more discrete contact pads. These electrically coupled contact pads may be on opposite sides or on the same side of the structure and the formed metalized wires may originate on one side and terminate on the other or originate and terminate from the same side. 1. A method for fabricating an interconnect mechanism or device comprising the steps of:providing a flat carrier of glass, ceramic or some other smooth, flat material such as but not limited to s smooth metallic block;temporarily bonding a sheet of metallic foil preferably Cu to the flat material carrier to keep the Cu flat with a suitable bonding material such as but not limited to adhesive or wax. Said sheet of foil having a foil thickness in a range but not limited to 10 um to 35 um;forming on top of the Cu foils dielectric wires attached to the Cu foil grow-up from predetermined locations on the foil to predetermined location in free space in the z axis by utilizing commercially known 3d printing techniques;treating said foil to promote adhesion of the dielectric wires through micro-etching plasma or other surface treatment; said wires are in a range of 1 um to 50 um in diameter and are built up to a z-axis height approximately 25 um to 100 um above an overall height of the planned interconnect mechanism in a range of from 100 um to 0.200 thick;metalizing the free ...

SNAP-RF INTERCONNECTIONS

A radio frequency connector includes a substrate, a first ground plane disposed upon the substrate, a signal conductor having a first contact point, with the first contact point being configured to electrically mate with a second contact point, and a first ground boundary configured to electrically mate with a second ground boundary, with the first ground boundary being formed as an electrically continuous conductor within the substrate. 1. A method of manufacturing a radio frequency connector , the method comprising:forming a signal trace from a conductive material disposed on a first substrate, the signal trace including a terminal pad;bonding a second substrate to the first substrate to substantially encapsulate the trace and terminal pad between the first substrate and the second substrate;forming an access hole from the second substrate to the terminal pad;forming a trench through the first and second substrate, the trench being positioned at least partially around the terminal pad;depositing a conductor into the access hole, the conductor providing an electrical connection to the terminal pad; anddepositing a conductive ink into the trench to form an electrically continuous conductor within the first and second substrate.2. The method of claim 1 , further comprising depositing a solder bump on the terminal pad.3. The method of claim 1 , further comprising applying solder/reflow to the conductor at the access hole.4. The method of claim 1 , wherein forming the signal trace includes milling the conductive material disposed on the first substrate.5. The method of claim 1 , wherein forming the access hole includes drilling through the second substrate.6. The method of claim 1 , wherein forming the trench includes milling through the first and second substrates.7. The method of claim 6 , wherein milling through the first and second substrates includes milling to a ground plane substantially without piercing the ground plane.8. The method of claim 1 , wherein the ...

HYBRID FABRICATION METHOD FOR LARGE AREA MICROWAVE CIRCUITS

A microwave device can include a printed circuit board substrate having a first microwave device subcircuit and a microdevice substrate having a second microwave device subcircuit. The first microwave device subcircuit may be formed at a low resolution and a low tolerance, while the second microwave device subcircuit may be formed at a high resolution and a high tolerance. The first microwave device subcircuit and the second microwave device subcircuit may be electrically coupled using a conductor. 1. A microwave device , comprising: a printed circuit board substrate having a circuit side; and', 'a first microwave device subcircuit on the circuit side of the printed circuit board substrate;, 'a printed circuit board structure, comprising a microdevice substrate having a passive layer side; and', 'a second microwave device subcircuit on the passive layer side of the microdevice substrate; and, 'a passive microwave microdevice, comprisingan electrical conductor that electrically couples the first microwave device subcircuit to the second microwave device subcircuit.2. The microwave device of claim 1 , wherein:the first microwave device subcircuit comprises a first subcircuit type selected from the group consisting of a filter, a resonator, a capacitor, an inductor, an impedance transformer, an impedance tuning element, a phase shifter, a power divider, a power coupler, and an air bridge structure;the second microwave device subcircuit comprises a second subcircuit type selected from the group consisting of a filter, a resonator, a capacitor, an inductor, an impedance transformer, an impedance tuning element, a phase shifter, a power divider, a power coupler, and an air bridge structure; andthe first subcircuit type is different from the second subcircuit type.3. The microwave device of claim 2 , wherein:the first microwave device subcircuit has a minimum feature dimension of from 25 micrometers to 1,000 micrometers; andthe second microwave device subcircuit has a ...

Devices and Methods for Solder Flow Control in Three-Dimensional Microstructures

Structures, materials, and methods to control the spread of a solder material or other flowable conductive material in electronic and/or electromagnetic devices are provided. 1. An electronic microstructure , comprising:a plurality of layers of one or more of a metal and a material that is non-wetting to one or more of a metallic solder and a conductive epoxy;a mounting surface disposed at a selected one of the plurality of layers, the surface having at least a portion thereof configured to bond to one or more of a metallic solder and a conductive epoxy;a wick stop structure formed of one or more of the plurality of layers of the non-wetting material, disposed away from the mounting surface and within the microstructure, the wick stop structure configured to deter a flow of one or more of the metallic solder and the conductive epoxy from the mounting surface to a location on the microstructure beyond the location of the wick stop structure.2. The electronic microstructure of claim 1 , wherein the material that is non-wetting comprises one or more of an insulating material claim 1 , a dielectric claim 1 , plated nickel claim 1 , and a metal oxide.3. The electronic microstructure of claim 1 , comprising a stop pad at the mounting surface claim 1 , the stop pad formed of one or more of the plurality of layers claim 1 , for establishing the thickness of the metallic solder or conductive epoxy.4. The electronic microstructure of claim 3 , comprising a mechanical anchor disposed within the microstructure and attached to the stop pad claim 3 , the anchor formed of one or more of the plurality of layers.5. The electronic microstructure of claim 1 , comprising one or more of a circuit board claim 1 , hybrid circuit claim 1 , and a semiconductor device operatively coupled to the mounting surface.6. The electronic microstructure of claim 1 , wherein the wick stop structure comprises a shelf which extends outwardly away from a surface of the microstructure at which the shelf is ...

COMBINED PRINTED WIRING BOARD AND METHOD FOR MANUFACTURING THE SAME

A combined printed wiring board includes a multilayer printed wiring board having an outermost insulation layer, and a wiring film fixed to a portion of the outermost insulation layer of the multilayer printed wiring board. The wiring film includes dense-pitch pads formed on a semiconductor-mounting surface of the wiring film, the multilayer printed wiring board has sparse-pitch pads formed on a semiconductor-mounting surface of the multilayer printed wiring board, the dense-pitch pads are formed to facilitate electrical connection between a first semiconductor element and a second semiconductor element, and the sparse-pitch pads are formed to facilitate electrical connection between the multilayer printed wiring board and the first semiconductor element and/or the second semiconductor element. 1. A combined printed wiring board , comprising:a multilayer printed wiring board having an outermost insulation layer; anda wiring film fixed to a portion of the outermost insulation layer of the multilayer printed wiring board,wherein the wiring film includes a plurality of dense-pitch pads formed on a semiconductor-mounting surface of the wiring film, the multilayer printed wiring board has a plurality of sparse-pitch pads formed on a semiconductor-mounting surface of the multilayer printed wiring board, the plurality of dense-pitch pads is configured to facilitate electrical connection between a first semiconductor element and a second semiconductor element, and the plurality of sparse-pitch pads is configured to facilitate electrical connection between the multilayer printed wiring board and at least one of the first semiconductor element and the second semiconductor element.2. A combined printed wiring board according to claim 1 , wherein the plurality of dense-pitch pads of the wiring film is formed such that a line and space of the dense-pitch pads is less than 10 μm/10 μm claim 1 , and the plurality of sparse-pitch pads of the wiring film is formed such that a line ...

Flexible printed circuit board and display device including the same

A flexible printed circuit board and a display device including the same are provided. An embodiment of a display device includes a display panel; a first circuit board attached to a first side of the display panel in a first direction; and a second circuit board attached to a second side of the first circuit board in the first direction, wherein the first circuit board includes a first bump area overlapping the display panel and a second bump area overlapping the second circuit board, the first bump area includes a plurality of first divided board portions arranged along a second direction crossing the first direction, and the first divided board portions of the plurality of first divided board portions partially overlap each other.

PLATING SOLUTION USING AMMONIUM SALT

A plating solution including a soluble salt containing at least a stannous salt; an acid selected from organic acid and inorganic acid or a salt thereof; and an additive containing a specific ammonium salt is provided. 2. The plating solution according to claim 1 , wherein {'br': None, 'sub': 3', '1', '2', '4, 'R—Y—Z—Y—R\u2003\u2003(2)'}, 'the additive further comprises a nonionic surfactant represented by a general formula (2) below,'}{'sub': 3', '4, 'claim-text': {'br': None, 'sub': n', '2n', 'm, '—(CH—O)—H \u2003\u2003(A)'}, 'and wherein, in the formula (2), Rand Ris the group represented by the formula (A) below,'}{'sub': 1', '2, 'and wherein, Yand Yrepresent a single bond or a group selected from —O—, —COO— and —CONH—; and Z represents a benzene ring or 2,2-diphenylpropane, and'}in the formula (A), n indicates 2 or 3 and m indicates an integer from 1 to 15.3. The plating solution according to claim 1 , further comprising an additional additive of a complexing agent claim 1 , a brightener claim 1 , or an antioxidant.4. The plating solution according to claim 2 , further comprising an additional additive of a complexing agent claim 2 , a brightener claim 2 , or an antioxidant. The present invention relates to a plating solution for tin or a tin alloy which is excellent in uniform electrodepositivity and suppresses generation of voids when a bump electrode is formed.Priority is claimed on Japanese Patent Application No. 2015-064073, filed Mar. 26, 2015, and Japanese Patent Application No. 2016-056776, filed Mar. 22, 2016, the contents of which are incorporated herein by reference.Conventionally, a lead-tin alloy solder plating solution made of an aqueous solution, which contains: at least one selected from an acid and a salt thereof; a soluble lead compound; a soluble tin compound; a nonionic surfactant; and a formalin condensate of naphthalenesulfonic acid or a salt thereof, is disclosed (for example, see Patent Literature 1 (PTL 1)). The plating solution ...

Wiring substrate

A wiring substrate includes: a connection pad having a first surface; a protective insulation layer formed on the first surface of the connection pad and having an opening portion therein, wherein a portion of the first surface of the connection pad is exposed from the opening portion; a metal layer having a lower surface facing the first surface of the connection pad and an upper surface opposite to the lower surface and formed on the first surface of the connection pad which is exposed from the opening portion, the metal layer including a raised portion that extends upward from the upper surface of the metal layer in a peripheral portion thereof; and a bump electrode formed on the upper surface of the metal layer.

A method of thermal decoupling of printed circuits and a printed circuit for use therein

In order to counter heat propagation between adjacent sections of a ribbon-like printed circuit board, the sections being individually exposed to heat between opposed border lines, with printed circuit board including an electrically insulating substrate with electrically conductive pads for mounting components thereon, the adjacent sections are terminated at the opposed border lines with at least one electrically conductive borderline pad, which has a separation gap to the border line, and/or is coupled to an electrically conductive line extending on substrate between a first end at borderline pad and a second end away from borderline pad. The first end and the second end may be located at a first and at a second distances to border line, the second distance being longer than the first distance, and/or the electrically conductive line may have a narrower cross section than the first and the second ends.

METHOD OF FORMING A SOLDER BUMP STRUCTURE

A method of the present invention includes preparing a substrate having a surface on which a electrode pad is formed, forming a resist layer on the substrate, the resist layer having an opening on the electrode pad, filling conductive paste in the opening of the resist layer; sintering the conductive paste in the opening to form a conductive layer which covers a side wall of the resist layer and a surface of the electrode pad in the opening, a space on the conductive layer leading to the upper end of the opening being formed, filling solder in the space on the conductive layer and removing the resist layer. 1. A solder bump structure comprising:a metal pillar formed on an electrode pad, the metal pillar having a cone-shaped surface, a substantially perpendicular outside wall, and a conformal cross-section; anda solder formed on the surface of the metal pillar, the solder having a convex top surface.2. The solder bump structure according to claim 1 , wherein the solder is in contact with the whole of the cone-shaped surface of the metal pillar.3. The solder bump structure according to claim 1 , wherein the metal pillar comprises at least one of copper claim 1 , nickel claim 1 , silver or gold.4. The solder bump structure according to claim 1 , wherein a thickness of a central portion of the metal pillar is in a range of ⅕ to ⅔ of a length from the surface of an electrode pad to the top surface of the solder.5. The solder bump structure according to claim 4 , wherein the electrode pad comprises aluminum.6. The solder bump structure according to claim 1 , wherein a thickness of a central portion of the metal pillar is in a range of 1 to 50 micrometers.7. A solder bump structure comprising:a metal pillar formed on an electrode pad and in an opening of a resist layer, the metal pillar having a cone-shaped surface, a substantially perpendicular outside wall connected to a side wall in the opening of the resist layer, and a conformal cross-section; anda solder formed on ...

METHOD OF FORMING A SOLDER BUMP STRUCTURE

A method of the present invention includes preparing a substrate having a surface on which a electrode pad is formed, forming a resist layer on the substrate, the resist layer having an opening on the electrode pad, filling conductive paste in the opening of the resist layer; sintering the conductive paste in the opening to form a conductive layer which covers a side wall of the resist layer and a surface of the electrode pad in the opening, a space on the conductive layer leading to the upper end of the opening being formed, filling solder in the space on the conductive layer and removing the resist layer. 1. A method of forming a solder bump structure , comprising the steps of:forming a resist layer on a substrate on which an electrode pad is formed, the resist layer having an opening on the electrode pad;filling conductive paste in the opening of the resist layer;sintering the conductive paste in the opening to form a conductive layer which covers a side wall of the resist layer and a surface of the electrode pad in the opening, a space on the conductive layer leading to an upper end of the opening being formed; andfilling solder in the space on the conductive layer.2. The method according to claim 1 , wherein the step of filling conductive paste includes a step of screen-printing conductive paste containing metal nanoparticles in a solvent on the substrate.3. The method according to claim 1 , wherein the step of filling conductive paste includes a step of injecting conductive paste containing metal nanoparticles in a solvent into the opening of the resist layer.4. The method according to claim 1 , wherein the conductive paste includes at least one of copper claim 1 , nickel claim 1 , silver or gold.5. The method according to claim 1 , wherein the conductive layer has a cone-shaped surface.6. The method according to claim 1 , wherein a cross-section of the conductive layer has a conformal shape.7. The method according to claim 1 , wherein a thickness of a central ...

METHOD OF FORMING A SOLDER BUMP STRUCTURE

A solder bump structure includes a pillar formed on an electrode pad. The pillar has a concave curve-shaped surface and a geometry defined at least in part by dimensions including a first height greater than a first width. The solder bump structure further includes solder formed on the concave curve-shaped surface of the pillar. The solder has a convex top surface and having dimensions including a second height greater than a second width due to the geometry of the pillar. 1. A solder bump structure comprising:a pillar formed on an electrode pad, the pillar having a concave curve-shaped surface and a geometry defined at least in part by dimensions including a first height greater than a first width; andsolder formed on the concave curve-shaped surface of the pillar, the solder having a convex top surface and having dimensions including a second height greater than a second width due to the geometry of the pillar.2. The solder bump structure according to claim 1 , wherein the solder is in contact with an entirety of the curve-shaped surface of the pillar.3. The solder bump structure according to claim 1 , wherein the pillar includes at least one material selected from the group consisting of: copper claim 1 , nickel claim 1 , silver and gold.4. The solder bump structure according to claim 1 , wherein a thickness of a central portion of the pillar is in a range of ⅕ to ⅔ of a length from a surface of the electrode pad to the convex top surface of the solder.5. The solder bump structure according to claim 4 , wherein the electrode pad includes aluminum.6. The solder bump structure according to claim 1 , wherein a thickness of a central portion of the pillar is in a range of 1 to 50 micrometers.7. The solder bump structure according to claim 1 , wherein the solder has a non-spherical shape.8. A solder bump structure comprising:a resist layer including an opening;a pillar formed on an electrode pad and in the opening of the resist layer, the pillar having a concave curve ...

Electronic Devices With Carbon Nanotube Printed Circuits

An electronic device has structures such as substrates and internal housing structures. The substrates may be rigid substrates such as rigid printed circuit boards and flexible substrates such as flexible printed circuits, flexible touch sensor substrates, and flexible display substrates. Carbon nanotubes may be patterned to form carbon nanotube signal paths on the substrates. The signal paths may resist cracking when bent. A flexible structure such as a flexible printed circuit may have carbon nanotube signal paths interposed between polymer layers. Openings in a polymer layer may expose metal solder pads on the carbon nanotube signal paths. A stiffener may be provided under the metal solder pads. Polymer materials in the flexible structure may be molded to form bends. Bends may be formed along edges of a touch sensor or display or may be formed in a flexible printed circuit. 1. A carbon nanotube flexible printed circuit , comprising:a first polymer layer;carbon nanotube signal paths on the first polymer layer;metal solder pads on portions of the carbon nanotube signal paths, wherein the metal solder pads are in direct contact with the carbon nanotube signal paths; anda second polymer layer on the first polymer layer.2. The carbon nanotube flexible printed circuit defined in wherein the carbon nanotube signal paths are interposed between the first polymer layer and the second polymer layer.3. The carbon nanotube flexible printed circuit defined in wherein the metal solder pads comprise electroplated metal.4. The carbon nanotube flexible printed circuit defined in wherein the second polymer layer has openings aligned with the metal solder pads.5. The carbon nanotube flexible printed circuit defined in further comprising a stiffener under at least some of the metal solder pads.6. The carbon nanotube flexible printed circuit defined in wherein the stiffener comprises a layer of metal attached to the first polymer layer with a layer of adhesive.7. The carbon nanotube ...

PRINTED WIRING BOARD, METHOD FOR MANUFACTURING THE SAME AND SEMICONDUCTOR DEVICE

A printed wiring board includes a first resin insulating layer, a first conductor pattern including first mounting pads formed on the first resin insulating layer, and a wiring structure positioned on the first resin insulating layer and including a second resin insulating layer and a second conductor pattern such that the second resin insulating layer and second conductor pattern are positioned adjacent to the first conductor pattern and that the second conductor pattern includes second mounting pads. The second mounting pads are embedded in the second resin insulating layer such that the second mounting pads have mounting surfaces exposed on an exposed surface of the second resin insulating layer, and the first mounting pads have mounting surfaces such that the mounting surfaces of the first and second mounting pads are formed on a same plane. 1. A printed wiring board , comprising:a first resin insulating layer;a first conductor pattern comprising a plurality of first mounting pads formed on the first resin insulating layer; anda wiring structure positioned on the first resin insulating layer and comprising a second resin insulating layer and a second conductor pattern such that the second resin insulating layer and second conductor pattern are positioned adjacent to the first conductor pattern and that the second conductor pattern includes a plurality of second mounting pads,wherein the plurality of second mounting pads is embedded in the second resin insulating layer such that the second mounting pads have mounting surfaces exposed on an exposed surface of the second resin insulating layer, and the first mounting pads have mounting surfaces such that the mounting surfaces of the first and second mounting pads are formed on a same plane.2. The printed wiring board according to claim 1 , wherein the plurality of second mounting pads is embedded in the second resin insulating layer such that the mounting surfaces of the second mounting pads and the exposed surface ...