Способ переключения мемристора

Изобретение относится к области нанотехнологий, а именно к способам управления работой запоминающих устройств на основе резистивной энергонезависимой памяти, а также устройств для нейроморфных вычислений, и может быть использовано для разработки оптимальных протоколов переключения резистивной мемристорной памяти и микросхем на ее основе. Способ переключения мемристора из состояния с низким сопротивлением в состояние с высоким сопротивлением включает воздействие на мемристор последовательности положительных и отрицательных прямоугольных импульсов напряжения, при этом к импульсному воздействию добавляют цифровой синтезированный белый шум c амплитудой и интенсивностью шумового сигнала. Изобретение обеспечивает гарантированное переключение мемристора из состояния с низким сопротивлением (СНС) в состояние с высоким сопротивлением (СВС) с сохранением длительного и стабильного отношения токов в состояниях СНС и СВС, а также стабильность параметров резистивного переключения (уменьшение деградации ...

Dynamic random access memory capacitor and preparation method therefor

A Dynamic Random Access Memory (DRAM) capacitor and a preparation method therefor are provided. The DRAM capacitor includes a dielectric layer, and the dielectric layer includes a high dielectric material layer, and low dielectric loss material layers provided on both side surfaces of the high dielectric material layer.

ПОЛУПРОВОДНИКОВАЯ СТРУКТУРА И СПОСОБ ЕЕ ИЗГОТОВЛЕНИЯ

Изобретение относится к микроэлектронике. Полупроводниковая структура включает в себя подложку с множеством канавок линии слов и областей истока/стока, каждая из которых примыкает к каждой канавке линии слов; линию слов, расположенную в канавке линии слов и включающую в себя первый проводящий слой, одиночный соединительный слой и второй проводящий слой, последовательно уложенные друг на друга, при этом первый проводящий слой расположен в нижней части канавки линии слов, а проекция линии слов на боковую стенку канавки линии слов и проекция области истока/стока на боковую стенку канавки линии слов имеют область перекрытия с заданной высотой, и в случае подачи на линию слов напряжения, которое меньше, чем заданное напряжение, сопротивление одиночного соединительного слоя превышает заданное сопротивление, в результате чего первый проводящий слой и второй проводящий слой разъединяются. Также предложен способ изготовления этой структуры. Изобретение обеспечивает возможность увеличения тока возбуждения ...

Semiconductor memory device and method for manufacturing the same

A semiconductor memory device includes a stack structure comprising a plurality of layers vertically stacked on a substrate, each layer including a semiconductor pattern, a gate electrode extending in a first direction on the semiconductor pattern, and a data storage element electrically connected to the semiconductor pattern, a plurality of vertical insulators penetrating the stack structure, the vertical insulators arranged in the first direction, and a bit line provided at a side of the stack structure and extending vertically. The bit line electrically connects the semiconductor patterns which are stacked. Each of the vertical insulators includes first and second vertical insulators adjacent to each other. The gate electrode includes a connection portion disposed between the first and second vertical insulators.

Isolation gap filling process for embedded dram using spacer material

Embodiments disclosed herein include transistors and methods of forming such transistors. In an embodiment, the transistor may comprise a semiconductor channel with a first surface and a second surface opposite the first surface. In an embodiment, a source electrode may contact the first surface of the semiconductor channel and a drain electrode may contact the first surface of the semiconductor channel. In an embodiment, a gate dielectric may be over the second surface of the semiconductor channel and a gate electrode may be separated from the semiconductor channel by the gate dielectric. In an embodiment, an isolation trench may be adjacent to the semiconductor channel. In an embodiment, the isolation trench comprises a spacer lining the surface of the isolation trench, and an isolation fill material.

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

A semiconductor device includes a gate trench formed in a substrate, a gate dielectric layer formed along profile of sidewalls and a bottom surface of the gate trench, first and second gate electrodes that are stacked over the gate dielectric layer to gap-fill a portion of the gate trench, a dipole inducing portion positioned between the second gate electrode and the gate dielectric layer and including a dipole bond and a non-dipole bond, and a capping layer suitable for gap-filling a remaining portion of the gate trench over the dipole inducing portion and the second gate electrode.

MEMORY DEVICE INCLUDING PILLAR-SHAPED SEMICONDUCTOR ELEMENT AND METHOD FOR MANUFACTURING THE SAME

On P layer bases extending in a band shape in a first direction in plan view, N+ layers also extending in a band shape in the first direction and Si pillars are formed. Subsequently, a gate insulating layer and gate conductor layers are formed so as to surround the Si pillars. Subsequently, contact holes whose bottom portions are in contact with the N+ layers are formed in an insulating layer, and first conductor W layers are formed at the bottom portions of the contact holes. Subsequently, insulating layers each having a hole are formed in the contact holes. Subsequently, a second conductor W layer is formed in a second direction perpendicular to the first direction so as to be connected to the gate conductor layers.

Vertical 2-transistor memory cell

Some embodiments include apparatuses and methods of forming the apparatus. One of the apparatuses and methods includes a memory cell having a first transistor and a second transistor located over a substrate. The first transistor includes a channel region. The second transistor includes a channel region located over the channel region of the first transistor and electrically separated from the first channel region. The memory cell includes a memory element located on at least one side of the channel region of the first transistor. The memory element is electrically separated from the channel region of the first transistor, and electrically coupled to the channel of the second transistor.

Applications of back-end-of-line (BEOL) capacitors in compute-in-memory (CIM) circuits

An apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The memory array includes an embedded dynamic random access memory (eDRAM) memory array. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes a switched capacitor circuit. The switched capacitor circuit includes a back-end-of-line (BEOL) capacitor coupled to a thin film transistor within the metal/dielectric layers of the semiconductor chip. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes ...

Laminated capacitor and method for manufacturing the same

A laminated capacitor and a method for manufacturing the same are provided. The method includes operations of providing a substrate; forming a first isolation insulation spacer and a plurality of discrete bottom bonding pads on the substrate; forming a sub-capacitor structure on the bottom bonding pads, which comprises a plurality of discrete bottom electrodes, a plurality of discrete top electrodes, and a dielectric medium located between the bottom electrodes and the top electrodes, wherein the plurality of bottom bonding pads are respectively electrically connected with the plurality of bottom electrodes in one-to-one correspondence; and repeatedly performing an operation of forming a connection structure and the sub-capacitor structure for N times on the sub-capacitor structure, such that N connection structures and N+1 sub-capacitor structures are alternately arranged along a direction perpendicular to the substrate, wherein N is an integer greater than or equal to 1.

MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND A COMMON PLATE

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a data line, a memory cell coupled to the data line, a ground connection, and a conductive line. The memory cell includes a first transistor and a second transistor. The first transistor includes a first region electrically coupled to the data line, and a charge storage structure electrically separated from the first region. The second transistor includes a second region electrically coupled to the charge storage structure and the data line. The ground connection is coupled to the first region of the first transistor. The conductive line is electrically separated from the first and second regions and spans across part of the first region of the first transistor and part of the second region of the second transistor and forming a gate of the first and second transistors.

Design-assisted inspection for DRAM and 3D NAND devices

With the disclosed systems and methods for DRAM and 3D NAND inspection, an image of the wafer is received based on the output for an inspection tool. Geometric measurements of a design of a plurality of memory devices on the wafer are received. A care area with higher inspection sensitivity is determined based on the geometric measurements.

Fuse component, semiconductor device, and method for manufacturing a fuse component

A fuse component, a semiconductor device, and a method of manufacturing a fuse component are provided. The fuse component includes an active region having a surface, a fuse dielectric layer extending from the surface of the active region into the active region, and a gate metal layer surrounded by the fuse dielectric layer.

MEMORY UNIT, SEMICONDUCTOR MODULE, DIMM MODULE, AND MANUFACTURING METHOD FOR SAME

A memory unit having a plurality of memory chips comprises: the memory unit that has a plurality of memory chips that are stacked; and protruding terminals that are disposed protruding from a side surface along the stacking direction of the memory unit, wherein the protruding terminals have surfaces that are positioned in a direction orthogonal to the protrusion direction, and between said surfaces, the surface roughness of a surface facing one way is greater than the surface roughness of a surface facing the other way.

PATTERNING METHOD AND METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE

The present disclosure relates to a patterning method and a method of manufacturing a semiconductor structure. The patterning method includes: providing a base; forming a first patterned mask layer on a surface of the base, where the first patterned mask layer includes a plurality of first mask structures extending along a first direction, and the first mask structures are arranged at intervals; forming a first dielectric layer on the first patterned mask layer, where the first dielectric layer fills up a spacing region between the first mask structures and covers an upper surface of the first patterned mask layer; and etching the first dielectric layer to form a plurality of second mask structures extending along a second direction, where the second mask structures are arranged at intervals, and the second direction intersects with the first direction; and selectively etching the first mask structure and the second mask structure.

Semiconductor device and method of manufacturing the same

In one embodiment, a semiconductor device includes a substrate, transistors on the substrate, and a stacked film provided above the transistors, including electrode layers separated from each other in a first direction, and including first, second and third regions. The device further includes plugs provided to the electrode layers in the first region, a first columnar portion in the second region, and a second columnar portion in the third region. At least one electrode layer among the electrode layers includes a first portion in the first region, a second portion in the second region, and a third portion in the third region, and is a continuous film from the second portion to the third portion via the first portion. The transistors include first, second and third transistors provided right under the first, second and third regions and electrically connected to first, second and third plugs among the plugs, respectively.

Semiconductor structure with capacitor landing pad and method of making the same

A semiconductor structure with a capacitor landing pad includes a substrate. A capacitor contact plug is disposed on the substrate. A capacitor landing pad contacts and electrically connects the capacitor contact plug. A bit line is disposed on the substrate. A dielectric layer surrounds the capacitor landing pad. The dielectric layer includes a bottom surface lower than a top surface of the bit line.

3D MEMORY CELLS AND ARRAY ARCHITECTURES

Various 3D memory cells, array architectures, and processes are disclosed. In an embodiment, a memory cell structure is provided that is formed by a process of alternately depositing multiple semiconductor layers and insulating layers to form a stack, forming vertical bit line holes through the stack using a deep trench process, and forming floating bodies in the semiconductor layers using an isotropic doping process through the bit line holes.

TWO TRANSISTOR MEMORY CELL USING STACKED THIN-FILM TRANSISTORS

Described herein are two transistor (2T) memory cells that use TFTs as access and gain transistors. When one or both transistors of a 2T memory cell are implemented as TFTs, these transistors may be provided in different layers above a substrate, enabling a stacked architecture. An example 2T memory cell includes an access TFT provided in a first layer over a substrate, and a gain TFT provided in a second layer over the substrate, the first layer being between the substrate and the second layer (i.e., the gain TFT is stacked in a layer above the access TFT). Stacked TFT based 2T memory cells allow increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

A semiconductor device with a small variation in transistor characteristics can be provided. A step of forming an opening in a structure body including an oxide semiconductor device to reach the oxide semiconductor device, a step of embedding a first conductor in the opening, a step of forming a second conductor in contact with a top surface of the first conductor, a step of forming a first barrier insulating film by a sputtering method to cover the structure body, the first conductor, and the second conductor, and a step of forming a second barrier insulating film over the first barrier insulating film by an ALD method are included. The first barrier insulating film and the second barrier insulating film each have a function of inhibiting hydrogen diffusion.

SEMICONDUCTOR MEMORY DEVICES AND METHOD OF MANUFACTURING THE SAME

A semiconductor memory device of the present invention is capable of high performance and high integration, and has an effect of configuring a semiconductor die including a vertical volatile memory structure and a vertical nonvolatile memory structure on one peripheral circuit structure. A semiconductor memory device provided includes a semiconductor substrate, a back gate structure having a cylindrical shape and extending in a vertical direction on the semiconductor substrate and including a back gate electrode layer and a back gate insulating layer surrounding the back gate electrode layer, a plurality of semiconductor patterns, each having a ring-shaped horizontal section surrounding the back gate structure, and spaced apart from each other in the vertical direction, and first to third conductive lines surrounding one of the plurality of semiconductor patterns and spaced apart from each other in the vertical direction.

METHODS OF FABRICATING SEMICONDUCTOR DEVICE

A method of fabricating a semiconductor device is provided, which includes forming (S11) a photoresist layer on a lower structure to have a first thickness, exposing (S12) a portion of the photoresist layer to form an exposed portion and a non-exposed portion of the photoresist layer, removing (S13) a part of the photoresist layer to form a photoresist layer having a second thickness that smaller than the first thickness, and removing (S14) the exposed portion or the non-exposed portion of the photoresist layer having the second thickness to form a photoresist pattern.

SEMICONDUCTOR STRUCTURE AND METHOD FOR FABRICATING SAME

Embodiments provide a semiconductor structure and a fabricating method. The method includes: providing a substrate, where a plurality of active areas arranged at intervals are provided in the substrate, and the substrate is covered with an insulating layer and a barrier layer stacked sequentially; forming, in the barrier layer, a plurality of first trenches arranged at intervals and extending along a first direction and penetrating through the barrier layer; forming a filling layer in the first trenches, and forming a first mask layer on the barrier layer and the filling layer; forming, in the first mask layer, a plurality of second trenches arranged at intervals and extending along a second direction and exposing the filling layer; and removing the filling layer exposed in the second trench and the insulating layer corresponding to the filling layer to form contact holes.

SEMICONDUCTOR STRUCTURES HAVING DEEP TRENCH CAPACITOR AND METHODS FOR MANUFACTURING THE SAME

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate having a first surface, a plurality of layers disposed on the first surface of the substrate. The plurality of layers includes a first nitride layer disposed on the first surface of the substrate, a first silicon-containing layer disposed on the first nitride layer, an intermediate nitride layer disposed on the first silicon-containing layer, a second silicon-containing layer disposed on the intermediate nitride layer, and a second nitride layer disposed on the second silicon-containing layer. In addition, the semiconductor structure includes a trench capacitor penetrating the plurality of layers and in contact with the substrate. The trench capacitor has a first portion having a first lateral surface and a second portion having a second lateral surface, and the first lateral surface has a slope different from that of the second lateral surface.

Semiconductor device having a conductive contact with a tapering profile

The present disclosure relates to a semiconductor device including a conductive contact having a tapering profile and a method for preparing the semiconductor device. The semiconductor device includes a conductive layer disposed over a semiconductor substrate, and a conductive contact disposed over the conductive layer. The semiconductor device also includes a conductive line disposed over the conductive contact. An upper portion of the conductive contact has a tapering profile in a first cross-sectional view along a longitudinal axis of the conductive line, and the upper portion of the conductive contact has a non-tapering profile in a second cross-sectional view along a line orthogonal to the longitudinal axis of the conductive line.

Etching method, air-gap dielectric layer, and dynamic random-access memory

An etching method for selectively etching a silicon oxide film on a wafer surface that includes the silicon oxide film and a silicon nitride film includes: a surface layer removal process including: etching the silicon oxide film at a first etching rate and removing a surface modification layer covering on the silicon nitride film; and an etching process including: etching the silicon oxide film at a second etching rate. The first etching rate is smaller than the second etching rate.

Dynamic random access memory and method for manufacturing the same

A semiconductor structure and its manufacturing method are provided. The method includes sequentially forming an insulating layer and a patterned mask layer on a substrate. The patterned cover curtain layer has an opening, and the opening includes a main body portion and two extension portions located at both ends of the main body portion. The method includes sequentially forming a first sacrificial layer, a second sacrificial layer, and a third sacrificial layer on the insulating layer. The first sacrificial layer fills the extension portions and defines a recess in the main body portion. The second sacrificial layer is formed in the recess defined by the first sacrificial layer. The third sacrificial layer is formed on the first sacrificial layer located in the extension portions.

SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND MEMORY

A method for manufacturing a semiconductor device is provided. The method includes: a substrate is provided, the substrate being provided with a first device area and a second device area with different doping types; a gate oxide layer which covers the first device area and the second device area is formed; a gate conductive layer which covers the gate oxide layer is formed; a first gate structure is formed on the first device area, the first gate structure including the gate conductive layer and the gate oxide layer; a second gate structure is formed on the second device area, the second gate structure including the gate conductive layer and the gate oxide layer. In the first device area and the second device area, the gate conductive layer always covers the gate oxide layer.

SEMICONDUCTOR DEVICES

A semiconductor device includes a gate electrode on a substrate, a memory body structure extending through the gate electrode, a source layer at an end portion of the memory body structure and including germanium doped with p-type impurities, and a drain layer at another end portion of the memory body structure and including a metal or a metal alloy. The memory body structure may include a body including undoped polysilicon, a charge storage pattern on a sidewall of the body, and a blocking pattern on an outer sidewall of the charge storage pattern and contacting the gate electrode.

Semiconductor device and method of manufacturing the same

Embodiments provide a semiconductor device and a method of manufacturing the same. The method includes: providing a layer to be etched; forming a patterned first mask layer on the layer to be etched; and forming a patterned second mask layer formed on the layer to be etched, where the second mask layer and the first mask layer jointly define an opening, which exposes the layer to be etched; and etching the layer to be etched using the first mask layer and the second mask layer as masks, thus forming a pattern to be etched. The above-described method of manufacturing the semiconductor device allows the feature size of the first mask layer and the second mask layer to be relatively larger while keeping the device feature size the same, makes it possible to further reduce the feature size of the device.

Semiconductor device and preparation method thereof, and memory apparatus

A semiconductor device, a preparation method thereof and a memory apparatus are provided. The semiconductor device includes a semiconductor substrate on which multiple strip-shaped stacked structures and a sidewall structure covering a periphery of each stacked structure are disposed, and a conductive structure is disposed on a side of the stacked structure far away from the semiconductor substrate. The stacked structure includes a conductor layer disposed on the semiconductor substrate and configured to transmit a data signal, an isolation layer disposed on a side of the conductor layer far away from the semiconductor substrate, a separation layer disposed on a side of the isolation layer far away from the semiconductor substrate and made of a low dielectric constant material, and a dielectric layer disposed on a side of the separation layer far away from the semiconductor substrate and configured to isolate the separation layer from the conductive structure.

Semiconductor device and a method making the same

A method for manufacturing a semiconductor structure includes: providing a substrate, the substrate includes a plurality of first trenches and a first pattern having an array of lines each formed between adjacent two of the plurality of first trenches; forming a first dielectric layer to cover at least the sidewalls of each of the lines in the array of the first pattern; and each of the lines in the array of the first pattern is segmented to form elements of a second pattern.

Semiconductor structure and manufacturing method thereof

A semiconductor structure and a manufacturing method thereof are provided. The method includes: providing a substrate; forming, on the substrate, a first mask layer having a plurality of strip-shaped first patterns arranged in parallel; forming, on the first mask layer, a second mask layer having a plurality of strip-shaped second patterns arranged in parallel; forming, on the second mask layer, a third mask layer having a plurality of strip-shaped third patterns arranged in parallel, the second patterns overlap with the third patterns, and the second patterns and the third patterns are configured to sever the first patterns at predetermined positions; and performing layer-by-layer etching, using the first mask layer, the second mask layer, and the third mask layer as masks to transfer the first patterns, the second patterns, and the third patterns to the substrate to form an array of discrete active areas.

Vertical memory device and method for fabricating vertical memory device

A method for fabricating a vertical memory device includes: forming a memory cell array that includes a vertical thyristor and a word line over a first substrate; forming a peripheral circuit unit in a second substrate; bonding the memory cell array with the peripheral circuit unit; removing the first substrate to expose one side of the vertical thyristor; and forming a bit line that is coupled to the one side of the vertical thyristor and the peripheral circuit unit.

Memory device having 2-transistor vertical memory cell

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell, first, second, and third data lines, and first and second access lines. Each of the first, second, and third data lines includes a length extending in a first direction. Each of the first and second access lines includes a length extending in a second direction. The memory cell includes a first transistor including a charge storage structure, and a first channel region electrically separated from the charge storage structure, and a second transistor including a second channel region electrically coupled to the charge storage structure. The first data line is electrically coupled to the first channel region. The second data line is electrically coupled to the first channel region. The third data line is electrically coupled to the second channel region, the second channel region being between the charge storage structure and the third data line. The first access line ...

MEMORY, MEMORY SUBSTRATE STRUCTURE, AND PREPARATION METHOD FOR MEMORY SUBSTRATE STRUCTURE

Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device includes: forming a lower structure that includes a substrate and conductive lines on the substrate, within a chip region and an edge region of the lower structure; forming data storage structures on the chip region of the lower structure; forming dummy structures on the edge region of the lower structure; forming an interlayer insulating layer covering the data storage structures and the dummy structures on the lower structure, the interlayer insulating layer including high step portions and low step portions, an upper end of the low step portions being lower than an upper end of the high step portions; and planarizing the interlayer insulating layer.

METHOD FOR FORMING SEMICONDUCTOR STRUCTURE

A method for forming a semiconductor structure is provided. The method includes: providing a base, the base including a first area and second areas located outside the first area, the first area including stack structures and isolation trenches alternately arranged in a first direction, the first direction being any direction in a plane where the base is located; performing ion implantation on sidewalls of the stack structure in the first direction, so as to form an active virtual connecting layer extending in the first direction and partially located in the isolation trenches; and forming a gate structure on a surface of the active virtual connecting layer.

MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell, first, second, and third data lines, and first and second access lines. Each of the first, second, and third data lines includes a length extending in a first direction. Each of the first and second access lines includes a length extending in a second direction. The memory cell includes a first transistor including a charge storage structure, and a first channel region electrically separated from the charge storage structure, and a second transistor including a second channel region electrically coupled to the charge storage structure. The first data line is electrically coupled to the first channel region. The second data line is electrically coupled to the first channel region. The third data line is electrically coupled to the second channel region, the second channel region being between the charge storage structure and the third data line. The first access line ...

MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND SHIELD STRUCTURES

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a conductive region, a first data line, a second data line, a first memory cell coupled to the first data line and the conductive region, a second memory cell coupled to the second data line and the conductive region, a conductive structure, and a conductive line. The first memory cell includes a first transistor coupled to a second transistor, the first transistor including a first charge storage structure. The second memory cell includes a third transistor coupled to a fourth transistor, the third transistor including a second charge storage structure. The conductive structure is located between and electrically separated from the first and second charge storage structures. The conductive line forms a gate of each of the first, second, third, and fourth transistors.

METHOD AND A SUBSTRATE PROCESSING APPARATUS FOR FORMING AN EPITAXIAL STACK ON A PLURALITY OF SUBSTRATES

A method for forming an epitaxial stack on a plurality of substrates comprises providing a plurality of substrates to a process chamber and executing deposition cycles, wherein each deposition cycle comprises a first deposition pulse and a second deposition pulse. The epitaxial stack comprises a first epitaxial layer stacked alternatingly and repeatedly with a second epitaxial layer, the second epitaxial layer being different from the first epitaxial layer. The first deposition pulse comprises a provision of a first reaction gas mixture to the process chamber, thereby forming the first epitaxial layer having a first native lattice parameter. The second deposition pulse comprises a provision of a second reaction gas mixture to the process chamber, thereby forming the second epitaxial layer having a second native lattice parameter, wherein the first native lattice parameter lies in a range within 1.5% larger than and 0.9% smaller than the second native lattice parameter.

Thin film transistors with offset source and drain structures and process for forming such

A device is disclosed. The device includes a source contact and a drain contact, a first dielectric between the source contact and the drain contact, a channel under the source contact and the drain contact, and a gate electrode below the channel, the gate electrode in an area under the first dielectric that does not laterally extend under the source contact or the drain contact. A second dielectric is above the gate electrode and underneath the channel.

Method of manufacturing dynamic random-access memory

A method of manufacturing a DRAM includes proving a substrate having active regions. First bit line structures are buried in the substrate. Each of first bit line structures extends along a first direction. Every two of the first bit line structures are disposed between two neighboring ones of the active regions arranged along a second direction. A plurality of pillar structures are formed arranged along the first direction by dividing each of the active regions. Second bit line structures are formed. Each of the second bit line structures is located between the pillar structures of a corresponding one of the active regions and extends through the corresponding one of the active regions along the second direction to be disposed on the first bit line structures at two sides of the corresponding one of the active regions and be electrically connected to the first bit line structures below.

Capacitor structure and method of preparing same

A capacitor structure and a method of preparing the same are provided. The method includes the followings. A substrate is provided. A stacked layer is formed on the substrate. A plurality of first via holes penetrating through the stacked layer are formed. The first via hole is filled with a conductive material to form a conductive pillar. A plurality of second via holes penetrating through the stacked layer are formed at a preset radius with the conductive pillar as an axis. The second via hole surrounds the conductive pillar circumferentially. The second via hole is filled with the conductive material to form an annular top electrode with a second gear.

METHODS FOR MANUFACTURING A PLURALITY OF SEMICONDUCTOR STRUCTURES AND SYSTEM IN PACKAGE

A method for manufacturing a plurality of semiconductor structures is provided. The method includes the operations as follows. A first hybrid bonding layer is formed over a first wafer including a plurality of first memory structures. A second hybrid bonding layer is formed over a second wafer including a plurality of control circuit structures. The memory structures and the control circuit structures are in contact with the first and the second hybrid bonding layers, respectively. The first wafer and the second wafer are bonded through a first hybrid bonding operation to connect the first and the second hybrid bonding layers, thereby obtaining a first bonded wafer. At least the first wafer, the second wafer, the first hybrid bonding structure, and the second hybrid bonding structure are singulated to obtain the plurality of semiconductor structures. A method for manufacturing a system in package (SiP) is also provided.

3D MEMORY CELLS AND ARRAY ARCHITECTURES AND PROCESSES

Various 3D memory cells, array architectures, and processes are disclosed. In an embodiment, a memory cell structure is provided that is formed by a process of alternately depositing multiple semiconductor layers and sacrificial layers to form a stack, forming vertical bit line holes through the stack using a deep trench process, forming floating bodies in the semiconductor layers using an isotropic doping process through the bit line holes, depositing conductor material to fill the bit line holes, removing the sacrificial layers, depositing a gate dielectric layer between the semiconductor layers, and depositing gate material onto the gate dielectric layer.

Widened conductive line structures and staircase structures for semiconductor devices

Systems, methods, and apparatuses for widened conductive line structures and staircase structures for semiconductor devices are described herein. One memory device includes an array of vertically stacked memory cells, the array including a vertical stack of horizontally oriented conductive lines. Each conductive line comprises a first portion extending in a first horizontal direction and a second portion extending in a second horizontal direction, wherein the second portion of each conductive line is of a width greater than the first portion of each conductive line.

Memory device and manufacturing method thereof

The invention provides a memory and a forming method thereof. By connecting two node contact parts filled in two node contact windows at the edge and adjacent to each other, a large-sized combined contact can be formed, so that when preparing the node contact parts, the morphology of the combined contact at the edge position can be effectively ensured, and under the blocking protection of the combined contact with a large width, the rest of the node contact parts can be prevented from being greatly eroded, and the morphology accuracy of the independently arranged node contact parts can be improved, thereby being beneficial to improving the device performance of the formed memory.

3D MEMORY CELLS AND ARRAY ARCHITECTURES AND PROCESSES

Various 3D memory cells, array architectures, and processes are disclosed. In an embodiment, a memory cell structure is provided that is formed by a process of alternately depositing multiple semiconductor layers and sacrificial layers to form a stack, forming vertical bit line holes through the stack using a deep trench process, forming floating bodies in the semiconductor layers using an isotropic doping process through the bit line holes, depositing conductor material to fill the bit line holes, removing the sacrificial layers, depositing a gate dielectric layer between the semiconductor layers, and depositing gate material onto the gate dielectric layer.

Semiconductor structure with embedded capacitor

Techniques for fabricating semiconductor structures and devices with stacked structures having embedded capacitors are disclosed. In one example, a semiconductor structure includes a substrate having a first region and a second region. The semiconductor structure further includes a capacitor structure disposed in the second region of the substrate. The capacitor structure includes a capacitor conductor and a dielectric insulator disposed between the capacitor conductor and the substrate. The semiconductor structure further includes a stacked device disposed on the first region of the substrate. The stacked device includes a first transistor and a second transistor. At least a portion of the second transistor is disposed under at least a portion of the first transistor. The first transistor and the second transistor are each coupled to the capacitor conductor.

A SEMICONDUCTOR DEVICE AND A METHOD MAKING THE SAME

A method for manufacturing a semiconductor structure includes: providing a substrate, the substrate includes a plurality of first trenches and a first pattern having an array of lines each formed between adjacent two of the plurality of first trenches; forming a first dielectric layer to cover at least the sidewalls of each of the lines in the array of the first pattern; and each of the lines in the array of the first pattern is segmented to form elements of a second pattern.

Semiconductor Device and Method of Forming the Same

The present disclosure relates to a semiconductor device and a method of forming the same. The semiconductor device includes: a substrate; a transistor on the substrate, which includes an active cylinder, the active cylinder includes a channel region, a source region and a drain distributed on opposite sides of the channel region, a first doped region located between the source region and the channel region, and a second doped region located between the drain region and the channel region, the first doped impurity region, the source region, the second doped impurity region and the drain region, all these regions include doped ions of the first type, and the doped concentration of the first impurity region is lower than that of the source region impurity concentration, the doped concentration of the second doped region is lower than the doped concentration of the drain region. The present disclosure reduces the band-to-band tunneling effect inside the transistor, thereby reducing the GIDL ...

SEMICONDUCTOR DEVICE

A semiconductor device includes a switching element, and a data storage structure electrically connected to the switching element. The data storage structure includes first electrodes, a second electrode, and a dielectric layer between the first electrodes and the second electrode. The second electrode includes a compound semiconductor layer doped with an impurity element, the compound semiconductor layer includes two or more elements and includes a semiconductor material doped with the impurity element, the two or more elements include a first element and a second element, the first element is silicon (Si), and a concentration of the impurity element in the compound semiconductor layer is in a range of about 0.1 at % to about 5 at %, and a concentration of the first element in the compound semiconductor layer is in a range of about 10 at % to about 15 at %.

Three-dimensional integrated system of dram chip and preparation method thereof

Disclosed is a three-dimensional integrated system for DRAM chips and a fabrication method thereof. A plurality of trench structures are etched on the front and back of a silicon wafer; then, a TSV structure is etched between the two upper and lower trenches opposite to each other for electrical connection; then, DRAM chips are placed in the trenches, and copper-copper bonding is used to make the chips electrically connected to the TSV structure in a vertical direction; finally, redistribution is done to make the chips in a horizontal direction electrically connected. The invention can make full use of silicon materials, and can avoid problems such as warpage and deformation of an interposer. In addition, placing the chips in the trenches will not increase the overall package thickness, while protecting the chips from external impact.

Substrate processing apparatus and monitoring method

A substrate processing apparatus according to an aspect of the present disclosure includes a mounting section on which a substrate is placed, a structure member provided above the mounting section so as to face the mounting section, and an optical sensor. The optical sensor is configured to detect a height of the mounting section, a height of the structure member, and a height of the substrate, by emitting light from above the structure member to a predetermined location of the mounting section, a predetermined location of the structure member, and the substrate, and by receiving reflection light from the mounting section, the structure member, and the substrate.

Multicolor approach to DRAM STI active cut patterning

Apparatuses and methods to provide a patterned substrate are described. A plurality of patterned and spaced first lines and carbon material lines and formed on the substrate surface by selectively depositing and etching films extending in a first direction and films extending in a second direction that crosses the first direction to pattern the underlying structures.

Method for preparing semiconductor device including conductive contact having tapering profile

The present disclosure relates to a method for preparing a semiconductor device including a conductive contact having a tapering profile and a method for preparing the semiconductor device. The method includes forming a conductive layer over a semiconductor substrate, and forming a dielectric layer covering the conductive layer. The method also includes etching the dielectric layer to form an opening exposing the conductive layer, and etching the dielectric layer to form a first recess and a second recess connecting to the opening. A depth of the opening is greater than a depth of the first recess and a depth of the second recess, and the first recess and the second recess have tapering profiles that taper toward the conductive layer. The method further includes forming a conductive contact over the conductive layer. The opening, the first recess and the second recess are filled by the conductive contact.

Memory device having 2-transistor vertical memory cell and shield structures

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a conductive region, a first data line, a second data line, a first memory cell coupled to the first data line and the conductive region, a second memory cell coupled to the second data line and the conductive region, a conductive structure, and a conductive line. The first memory cell includes a first transistor coupled to a second transistor, the first transistor including a first charge storage structure. The second memory cell includes a third transistor coupled to a fourth transistor, the third transistor including a second charge storage structure. The conductive structure is located between and electrically separated from the first and second charge storage structures. The conductive line forms a gate of each of the first, second, third, and fourth transistors.

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREFOR

A semiconductor structure and a manufacturing method therefor are provided. The semiconductor structure includes: a substrate; a plurality of connection pads disposed on a surface of the substrate; and a plurality of electrode pillars, disposed on the substrate and connected to the plurality of connection pads in a one-to-one correspondence. Each electrode pillar includes a first conductor layer and a second conductor layer that are alternately distributed in a direction perpendicular to the substrate. A material of the first conductor layer is different from a material of the second conductor layer. A side surface of the first conductor layer is recessed inward relative to a side surface of the second conductor layer.

Floating body memory cell having gates favoring different conductivity type regions

A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.

Capacitor structure with metal bilayer and method for using the same

A method for using a metal bilayer is disclosed. First, a bottom electrode is provided. Second, a dielectric layer which is disposed on and is in direct contact with the lower electrode is provided. Then, a metal bilayer which serves as a top electrode in a capacitor is provided. The metal bilayer is disposed on and is in direct contact with the dielectric layer. The metal bilayer consists of a noble metal in direct contact with the dielectric layer and a metal nitride in direct contact with the noble metal.

Anti-fuse of semiconductor device, semiconductor module and system each including the semiconductor device, and method for forming the anti-fuse

An anti-fuse based on a Field Nitride Trap (FNT) is disclosed. The anti-fuse includes a first active pillar including a first junction, a second active pillar including a second junction, a selection line buried between the first active pillar and the second active pillar, and a trap layer for electrically coupling the first junction to the second junction by trapping minority carriers according to individual voltages applied to the first junction, the second junction and the selection line. As a result, the fuse can be highly integrated through the above-mentioned structure, and programming of the fuse can be easily achieved.

Method for forming dynamic random access memory structure

The present invention provides a method for forming a dynamic random access memory (DRAM) structure, the method including: firstly, a substrate is provided, a cell region and a peripheral region are defined on the substrate, a plurality of buried word lines is then formed in the cell region of the substrate, next, a shallow trench isolation structure is formed in the peripheral region adjacent to the cell region, wherein a concave top surface is formed on the shallow trench isolation structure, afterwards, a first dummy bit line gate is formed within the shallow trench isolation structure of the peripheral area, and a second dummy bit line gate is formed in the cell region and adjacent to the first dummy bit line gate, wherein a top surface of the first dummy bit line gate is lower than a top surface of the second dummy bit line gate.

Dynamic random access memory

A dynamic random access memory (DRAM) is provided and includes a base substrate. The base substrate includes a semiconductor substrate, a plurality of fins formed on the semiconductor substrate, and an isolation structure formed on the semiconductor substrate and covering portions of side surfaces of the plurality of fins. The dynamic random access memory further includes an interlayer dielectric layer formed over the base substrate and covering top surfaces of the plurality of fins and the isolation structure; and a memory structure, formed in an opening passing through the interlayer dielectric layer and each of the plurality of fins, the opening extending to and exposing a top surface of a portion of the isolation structure. The memory structure includes a first conductive layer, a memory medium layer on the first conductive layer, and a second conductive layer on the memory medium layer.

A 3d semiconductor device and system

A 3D semiconductor device, the device including: a first crystalline silicon layer including a plurality of first transistors; a first metal layer interconnecting the first transistors, a portion of the first transistors forming a plurality of first logic gates; a first array of memory cells including second transistors; a second metal layer overlying the first and second transistors; a second crystalline silicon layer overlaying the second metal layer and the second crystalline silicon layer including a plurality of third transistors; a third metal layer interconnecting the third transistors, a portion of the third transistors forming a plurality of second logic gates; a second array of memory cells including fourth transistors and overlaying the second crystalline silicon layer; a fourth metal layer overlying the third and fourth transistors, where at least one of the fourth transistors is overlaying at least another one of the fourth transistors such that they are self-aligned, having been processed following the same lithography step, where the second array of memory cells include NAND flash type memory cells.

Methods of fabricating fine patterns

Methods of forming fine patterns are provided. The method includes reinforcing a hydrophobic property of a hard mask layer using a surface treatment process to form a neutral layer, forming a block co-polymer layer on the neutral layer, and phase-separating the block co-polymer layer into first domains and second domains.

Insulating structure and method of forming the same

A method of forming insulating structures in a semiconductor device is provided in the present invention, which includes the steps of forming a first mask layer with mandrels and a peripheral portion surrounding the mandrels, forming spacers on sidewalls of first mask layer, filling up the space between spacers with a second mask layer, removing the spacers to form opening patterns, performing an etch process with the first mask layer and the second mask layer as an etch mask to form trenches in the substrate, and filling up the trenches with an insulating material to form insulating structures.

Three-dimensional memory device employing direct source contact and hole current detection and method of making the same

A three-dimensional memory device includes a p-doped source semiconductor layer located over a substrate, a p-doped strap semiconductor layer located over the p-doped source semiconductor layer, an alternating stack of electrically conductive layers and insulating layers located over the p-doped strap semiconductor layer, and memory stack structures that extend through the alternating stack and into an upper portion of the p-doped source semiconductor layer. Each memory stack structure includes a p-doped vertical semiconductor channel and a memory film laterally surrounding the p-doped vertical semiconductor channel. A top surface of each p-doped vertical semiconductor channel contacts a bottom surface of a respective n-doped region. A sidewall of a bottom portion of each p-doped vertical semiconductor channel contacts a respective sidewall of the p-doped strap semiconductor layer.

Three-dimensional nand non-volatile memory devices with buried word line selectors

Three-dimensional NAND stacked memory devices are described that include a stack including alternating word line and dielectric layers and a plurality of NAND strings of memory cells formed in memory holes which extend through the layers. Each memory cell includes a control gate formed by one of the word line layers, and multiple selector devices, each selector device coupled to an end of a corresponding NAND string. The NAND strings are disposed above a substrate, and the selector devices are disposed in the substrate.

Semiconductor device, method of fabricating same and memory

A semiconductor device, a method of fabricating the semiconductor device and a memory are disclosed. In the provided semiconductor device, bit line contact plugs partially reside on insulating material layers in gate trenches in active areas and thus can come into sufficient contact with the active areas. This ensures good electrical transmission between the bit line contact plugs and the active areas even when there are internal voids in the bit line contact plugs. Such bit line contact plugs allowed to contain internal voids can be fabricated in an easier and faster manner, thus allowing a significantly enhanced memory fabrication throughput.

Semiconductor memory devices

A semiconductor memory device includes a substrate having a memory cell region, a peripheral region, and a dam region between the memory cell region and the peripheral region, the memory cell region having a rectangular shape according to a top view and having a plurality of active regions defined therein; a plurality of bit line structures extending on the substrate in the memory cell region to be parallel with each other in a first horizontal direction, each including a bit line; a plurality of buried contacts filling lower portions of spaces among the plurality of bit line structures on the substrate; a plurality of landing pads on the plurality of buried contacts; and a dam structure including a first dam structure and a second dam structure in the dam region and being at the same level as the plurality of landing pads.

Semiconductor devices

A semiconductor memory device includes a semiconductor substrate having active areas and a trench isolation region between the active areas. The active areas extend along a first direction. Buried word lines extend along a second direction in the semiconductor substrate. Two of the buried word lines intersect with each of the active areas, separating each of the active areas into a digit line contact area and two cell contact areas. The second direction is not perpendicular to the first direction. A digit line contact is disposed on the digit line contact area. A storage node contact is disposed on each of the two cell contact areas. The digit line contact and the storage node contact are coplanar. At least one digit line extends along a third direction over a main surface of the semiconductor substrate. The at least one digit line is in direct contact with the digit line contact.

Memory device and semiconductor device including the memory device

A novel memory device is provided. The memory device includes a transistor and a capacitor device. The transistor includes a first oxide semiconductor; a first conductor and a second conductor provided over a top surface of the first oxide semiconductor; a second oxide semiconductor that is formed over the first oxide semiconductor and is provided between the first conductor and the second conductor; a first insulator provided in contact with the second oxide semiconductor; and a third conductor provided in contact with the first insulator. The capacitor device includes the second conductor; a second insulator over the second conductor; and a fourth conductor over the second insulator. The first oxide semiconductor has a groove deeper than a thickness of each of the first conductor and the second conductor.

Semiconductor devices and methods for fabricating the same

A semiconductor device includes a landing pad on a substrate, a lower electrode on the landing pad, the lower electrode being electrically connected to the landing pad, a dielectric layer on the lower electrode, the dielectric layer extending along a profile of the lower electrode, an upper electrode on the dielectric layer, and an upper plate electrode on the upper electrode and including first fluorine (F) therein, wherein the upper plate electrode includes an interface facing the upper electrode, and wherein the upper plate electrode includes a portion in which a concentration of the first fluorine decreases as a distance from the interface of the upper plate electrode increases.

Semiconductor structure and fabrication method thereof

A semiconductor structure includes an active area in a substrate, a device isolation region surrounding the active area, first and second bit line structures on the substrate, a conductive diffusion region in the active area between the first and the second bit line structures, and a contact hole between the first and the second bit line structures. The contact hole partially exposes the conductive diffusion region. A buried plug layer is disposed in the contact hole and in direct contact with the conductive diffusion region. A storage node contact layer is disposed on the buried plug layer within the contact hole. The storage node contact layer has a downwardly protruding portion surrounded by the buried plug layer. The buried plug layer has a U-shaped cross-sectional profile.

Semiconductor memory devices

A semiconductor memory device includes a substrate having a memory cell region, a peripheral region, and a dam region between the memory cell region and the peripheral region, the memory cell region having a rectangular shape according to a top view and having a plurality of active regions defined therein; a plurality of bit line structures extending on the substrate in the memory cell region to be parallel with each other in a first horizontal direction, each including a bit line; a plurality of buried contacts filling lower portions of spaces among the plurality of bit line structures on the substrate; a plurality of landing pads on the plurality of buried contacts; and a dam structure including a first dam structure and a second dam structure in the dam region and being at the same level as the plurality of landing pads.

Semiconductor memory device

A semiconductor memory device which includes a memory cell including two or more sub memory cells is provided. The sub memory cells each including a word line, a bit line, a first capacitor, a second capacitor, and a transistor. In the semiconductor device, the sub memory cells are stacked in the memory cell; a first gate and a second gate are formed with a semiconductor film provided therebetween in the transistor; the first gate and the second gate are connected to the word line; one of a source and a drain of the transistor is connected to the bit line; the other of the source and the drain of the transistor is connected to the first capacitor and the second capacitor; and the first gate and the second gate of the transistor in each sub memory cell overlap with each other and are connected to each other.

Robust nucleation layers for enhanced fluorine protection and stress reduction in 3d nand word lines

A silicon-containing nucleation layer can be employed to provide a self-aligned template for selective deposition of tungsten within backside recesses during formation of a three-dimensional memory device. The silicon-containing nucleation layer may remain as a silicon layer, converted into a tungsten silicide layer, or replaced with a tungsten nucleation layer. Tungsten deposition can proceed only on the surface of the silicon-containing nucleation layer or a layer derived therefrom in a subsequent tungsten deposition process.

Semiconductor isolation structure and method of manufacture

A method of formation of an isolation structure for vertical semiconductor devices, the resulting isolation structure, and a memory device to prevent leakage among adjacent vertical semiconductor devices are described.

Fin-fet gain cells

A FinFET gain cell includes a write port, read port and storage node. The write port includes at least one write FinFET transistor and has write word-line (WWL) and write bit-line (WBL) inputs. The read port includes at least one FinFET read transistor and has a read word-line (RWL) input and a read bit-line (RBL) output. The storage node stores a data level written from said WBL. The storage nodes includes a single layer interconnect which connects the write port output diffusion connection to the read port input gate connection. The height of the single layer interconnect at the write port output diffusion connection is different from the height of the single layer interconnect at the read port input gate connection.

Applications of back-end-of-line (beol) capacitors in compute-in-memory (cim) circuits

An apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The memory array includes an embedded dynamic random access memory (eDRAM) memory array. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes a switched capacitor circuit. The switched capacitor circuit includes a back-end-of-line (BEOL) capacitor coupled to a thin film transistor within the metal/dielectric layers of the semiconductor chip. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes an accumulation circuit. The accumulation circuit includes a ferroelectric BEOL capacitor to store a value to be accumulated with other values stored by other ferroelectric BEOL capacitors.

Functional Blocks Implemented by 3D Stacked Integrated Circuit

A three-dimensional stacked integrated circuit (3D SIC) having a non-volatile memory die having an array of non-volatile memory partitions, a volatile memory die having an array of volatile memory partitions, and a processing logic die having an array of processing logic partitions. The non-volatile memory die, the volatile memory die, and the processing logic die are stacked. The non-volatile memory die, the volatile memory die, and the processing logic die can be arranged to form an array of functional blocks, and at least two functional blocks can each include a different data processing function that reduces the computation load of a controller.

Semiconductor memory device and method of manufacturing the same

A method of manufacturing a semiconductor memory device and a semiconductor memory device, the method including providing a substrate that includes a cell array region and a peripheral circuit region; forming a mask pattern that covers the cell array region and exposes the peripheral circuit region; growing a semiconductor layer on the peripheral circuit region exposed by the mask pattern such that the semiconductor layer has a different lattice constant from the substrate; forming a buffer layer that covers the cell array region and exposes the semiconductor layer; forming a conductive layer that covers the buffer layer and the semiconductor layer; and patterning the conductive layer to form conductive lines on the cell array region and to form a gate electrode on the peripheral circuit region.

Memory devices and methods for manufacturing the same

Memory devices may include a source region, channels, a gate insulation layer pattern, a selection gate pattern, a first gate pattern, a second gate pattern and a drain region. The source region may include first impurities having a first conductivity type at an upper portion of a substrate. The channels may contact the source region. Each of the channels may extend in a vertical direction that is perpendicular to an upper surface of the substrate. The selection gate pattern may be on sidewalls of the channels. The first gate pattern may be on the sidewalls of the channels. The first gate pattern may be a common electrode of all of multiple channels. The second gate patterns may be on the sidewalls of the channels. The drain region may include second impurities having a second conductivity type that is different from the first conductivity type at an upper portion of each of the channels.

Manufacturing method of vertical channel transistor array

A manufacturing method of a vertical channel transistor array is provided. The method includes following steps. A plurality of embedded word lines are formed at bottoms of trenches, and each of the embedded word lines is located at a first side wall of one of the trenches and connected to first sides of the semiconductor pillars in the same row. Each of the embedded word lines is not connected to second sides of the semiconductor pillars in the same row, and the first sides are opposite to the second sides. Only one embedded word line is correspondingly connected to the semiconductor pillars arranged in one row. An isolation structure is formed between a second side wall of each of the trenches and each of the embedded word lines. The first side wall is opposite to the second side wall.

Floating body memory cell having gates favoring different conductivity type regions

A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.

Air-gap gate sidewall spacer and method

Disclosed are integrated circuit (IC) structures and formation methods. In the methods, a gate with a sacrificial gate cap and a sacrificial gate sidewall spacer is formed on a channel region. The cap and sidewall spacer are removed, creating a cavity with a lower portion between the sidewalls of the gate and adjacent metal plugs and with an upper portion above the lower portion and the gate. A first dielectric layer is deposited, forming an air-gap in the lower portion and lining the upper portion. A second dielectric layer is deposited, filling the upper portion. During formation of a gate contact opening (optionally over an active region), the second dielectric layer is removed and the first dielectric layer is anisotropically etched, thereby exposing the gate and creating a dielectric spacer with a lower air-gap segment and an upper solid segment. Metal deposited into the opening forms the gate contact.

Method for fabricating semiconductor device including forming a dielectric layer on a structure having a height difference using ald

A method for fabricating a semiconductor device includes forming a structure with a height difference on a substrate and forming a dielectric layer structure on the structure using an atomic layer deposition (ALD) method. Forming the dielectric layer structure includes forming a first dielectric layer including silicon nitride on the structure with the height difference. Forming the first dielectric layer includes feeding a first gas including pentachlorodisilane (PCDS) or diisopropylamine pentachlorodisilane (DPDC) as a silicon precursor, and a second gas including nitrogen components into a chamber including the substrate such that the first dielectric layer is formed in situ on the structure having the height difference.

Memory device having shared access line for 2-transistor vertical memory cell

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell and first, second, and third data lines located over a substrate. The memory cell includes a first transistor and a second transistor. The first transistor includes a charge storage structure located on a first level of the apparatus, and a first channel region electrically separated from the charge storage structure. The second transistor includes a second channel region located on a second level of the apparatus and electrically coupled to the charge storage structure. The first and second data lines are located on a third level of the apparatus and electrically coupled to the first channel region. The first level is between the substrate and the third level. The third data line is electrically coupled to the second channel region and electrically separated from the first channel region.

Anti-fuse of semiconductor device, semiconductor module and system each including the semiconductor device, and method for forming the anti-fuse

An anti-fuse based on a Field Nitride Trap (FNT) is disclosed. The anti-fuse includes a first active pillar including a first junction, a second active pillar including a second junction, a selection line buried between the first active pillar and the second active pillar, and a trap layer for electrically coupling the first junction to the second junction by trapping minority carriers according to individual voltages applied to the first junction, the second junction and the selection line. As a result, the fuse can be highly integrated through the above-mentioned structure, and programming of the fuse can be easily achieved.

Semiconductor device and method of fabricating the same

A semiconductor device includes a memory cell storing data. The memory cell capacitor includes a plurality of bottom electrodes on a substrate and extending in a vertical direction with respect to a top surface of the substrate, the plurality of bottom electrodes being spaced apart from each other in a first direction parallel to the top surface of the substrate, an upper support pattern on upper lateral surfaces of the plurality of bottom electrodes, and a lower support pattern on lower lateral surfaces of the plurality of bottom electrodes. The lower support pattern is disposed between the substrate and the upper support pattern, and a first bottom electrode of the plurality of bottom electrodes includes a first recess adjacent to a bottom surface of the lower support pattern.

Integrated Circuitry, DRAM Circuitry, Method Used In Forming Integrated Circuitry, And Method Used In Forming Memory Circuitry

A method used in forming integrated circuitry comprises forming conductive line structures having conductive vias laterally between and spaced longitudinally along immediately-adjacent of the conductive line structures. First insulating material is formed laterally between immediately-adjacent of the conductive vias, Second insulating material is formed directly above the first insulating material and directly above the conductive vias. The second insulating material comprises silicon, carbon, nitrogen, and hydrogen. A third material is formed directly above the second insulating material. The third material and the second insulating material comprise different compositions relative one another. The third material is removed from being directly above the second insulating material and the thickness of the second insulating material is reduced thereafter. A fourth insulating material is formed directly above the second insulating material of reduced thickness. A plurality of electronic components is formed above the fourth insulating material and that individually are directly electrically coupled to individual of the conductive vias through the fourth and second insulating materials. Other embodiments, including structure, are disclosed.

Semiconductor structure with capacitor landing pad and method of making the same

A semiconductor structure with a capacitor landing pad includes a substrate. A capacitor contact plug is disposed on the substrate. A capacitor landing pad contacts and electrically connects the capacitor contact plug. A bit line is disposed on the substrate. A dielectric layer surrounds the capacitor landing pad. The dielectric layer includes a bottom surface lower than a top surface of the bit line.

Floating body memory cell apparatus and methods

Some embodiments include apparatus and methods having a base; a memory cell including a body, a source, and a drain; and an insulation material electrically isolating the body, the source, and the drain from the base, where the body is configured to store information. The base and the body include bulk semiconductor material. Additional apparatus and methods are described.

3D Stacked High-Density Memory Cell Arrays and Methods of Manufacture

Integrated circuit devices having multiple level arrays of thyristor memory cells are created using a stack of ONO layers through which NPNPNPN layered silicon pillars are epitaxially grown in-situ. Intermediate conducting lines formed in place of the removed nitride layer of the ONO stack contact the middle P-layer of silicon pillars. The silicon pillars form two arrays of thyristor memory cells, one stacked upon the other, having the intermediate conducting lines as common connections to both arrays. The stacked arrays can also be provided with assist-gates.

Semiconductor memory device

A semiconductor memory device which includes a memory cell including two or more sub memory cells is provided. The sub memory cells each including a word line, a bit line, a first capacitor, a second capacitor, and a transistor. In the semiconductor device, the sub memory cells are stacked in the memory cell; a first gate and a second gate are formed with a semiconductor film provided therebetween in the transistor; the first gate and the second gate are connected to the word line; one of a source and a drain of the transistor is connected to the bit line; the other of the source and the drain of the transistor is connected to the first capacitor and the second capacitor; and the first gate and the second gate of the transistor in each sub memory cell overlap with each other and are connected to each other.

Integrated circuit having memory cell array including barriers, and method of manufacturing same

An integrated circuit device having (i) a memory cell array which includes a plurality of memory cells arranged in a matrix of rows and columns, wherein each memory cell includes at least one transistor having a gate, gate dielectric and first, second and body regions, wherein: (i) the body region of each transistor is electrically floating and (ii) the transistors of adjacent memory cells have a common first region and/or a common second region. Each common first region and/or second regions of transistors of adjacent memory cells includes a barrier disposed therein and/or therebetween, wherein each barrier provides a discontinuity in the common regions and/or includes one or more electrical characteristics that are different from one or more corresponding electrical characteristics of the common regions.

Dram interconnect structure having ferroelectric capacitors

An interconnect structure for use in coupling transistors in an integrated circuit is disclosed, including various configurations in which ferroelectric capacitors exhibiting negative capacitance are coupled in series with dielectric capacitors. In one embodiment, the negative capacitor includes a dielectric/ferroelectric bi-layer. When a negative capacitor is electrically coupled in series with a conventional dielectric capacitor, the series combination behaves like a stable ferroelectric capacitor for which the overall capacitance can be measured experimentally, and tuned to a desired value. The composite capacitance of a dielectric capacitor and a ferroelectric capacitor having negative capacitance coupled in series is, in theory, infinite, and in practice, very large. A series combination of positive and negative capacitors within a microelectronic interconnect structure can be used to make high capacity DRAM memory cells.

Semiconductor memory device and manufacturing method thereof

A semiconductor memory device includes a semiconductor substrate, a first support layer, a first electrode, a capacitor dielectric layer, and a second electrode. The first support layer is disposed on the semiconductor substrate. The first electrode is disposed on the semiconductor substrate and penetrates the first support layer. The capacitor dielectric layer is disposed on the first electrode. The second electrode is disposed on the semiconductor substrate, and at least a part of the capacitor dielectric layer is disposed between the first electrode and the second electrode. The first support layer includes a carbon doped nitride layer, and a carbon concentration of a bottom portion of the first support layer is higher than a carbon concentration of a top portion of the first support layer.

Method for manufacturing semiconductor device

One method includes sequentially forming an insulating film and a first material film on a semiconductor substrate, forming on the first material film a mask film having a rectangular first opening, and dry-etching the first material film using the mask film as a mask to form an ellipsoidal second opening having its shorter side aligned in a first direction of the first material film. Forming the mask film includes forming a second material film having a side surface that faces the first direction of the first opening, and a third material film having side surfaces facing a second direction of the first opening, and the thickness of the third material film is greater than the thickness of the second material film.

Semiconductor memory device, method of driving the same and method of fabricating the same

A semiconductor memory device includes a plurality of memory cell transistors arranged along a common semiconductor layer. Each of the plurality of memory cell transistors comprises a first source/drain region and a second source/drain region formed in the common semiconductor layer; a gate stack formed on a portion of the common semiconductor layer between the first source/drain region and the second source/drain region; and an electrical floating portion in the portion of the common semiconductor layer, a charge state of the electrical floating portion being adapted to adjust a threshold voltage and a channel conductance of the memory cell transistor. The plurality of memory cell transistors connected in series with each other along the common semiconductor layer provide a memory string.

Method for fabricating semiconductor device

A method for fabricating a semiconductor device, the method including forming a mold structure on a substrate such that the mold structure includes alternately and repeatedly stacked interlayer insulating films and sacrificial films; forming a channel hole passing through the mold structure; forming a vertical channel structure within the channel hole; exposing a surface of the interlayer insulating films by removing the sacrificial films; forming an aluminum oxide film along a surface of the interlayer insulating films; forming a continuous film on the aluminum oxide film; and nitriding the continuous film to form a TiN film.

Semiconductor memory device having coplanar digit line contacts and storage node contacts in memory array and method for fabricating the same

A semiconductor memory device includes a semiconductor substrate having active areas and a trench isolation region between the active areas. The active areas extend along a first direction. Buried word lines extend along a second direction in the semiconductor substrate. Two of the buried word lines intersect with each of the active areas, separating each of the active areas into a digit line contact area and two cell contact areas. The second direction is not perpendicular to the first direction. A digit line contact is disposed on the digit line contact area. A storage node contact is disposed on each of the two cell contact areas. The digit line contact and the storage node contact are coplanar. At least one digit line extends along a third direction over a main surface of the semiconductor substrate. The at least one digit line is in direct contact with the digit line contact.

Conductive Interconnects Suitable for Utilization in Integrated Assemblies, and Methods of Forming Conductive Interconnects

Some embodiments include an integrated assembly having an insulative mass over a conductive base structure. A conductive interconnect extends through the insulative mass to an upper surface of the conductive base structure. The conductive interconnect includes a conductive liner extending around an outer lateral periphery of the interconnect. The conductive liner includes nitrogen in combination with a first metal. A container-shaped conductive structure is laterally surrounded by the conductive liner. The container-shaped conductive structure includes a second metal. A conductive plug is within the container-shaped conductive structure. Some embodiments include methods of forming conductive interconnects within integrated assemblies.

Multi-Layer Random Access Memory and Methods of Manufacture

A semiconductor structure for a DRAM is described having multiple layers of arrays of memory cells. Memory cells in a vertical string extending through the layers have an electrical connection to one terminal of the memory cells in that string. Word lines couple the strings together. Each layer of the array also includes bit line connections to memory cells on that layer. Select transistors enable the use of folded bit lines. The memory cells preferably are thyristors. Methods of fabricating the array are described.

Three-dimensional nand non-volatile memory and dram memory devices on a single substrate

A method is provided that includes forming a three-dimensional NAND stacked non-volatile memory array on a substrate, and forming a DRAM memory array on the substrate. The three-dimensional NAND stacked non-volatile memory array and the DRAM memory array are formed using a single integrated circuit fabrication process.

Integrated circuit device and method of manufacturing the same

An integrated circuit device includes: a substrate including active regions; a device isolation film defining the active regions; a word line arranged over the active regions and the device isolation film and extending in a first horizontal direction; and a gate dielectric film arranged between the substrate and the word line and between the device isolation film and the word line, in which, in a second horizontal direction orthogonal to the first horizontal direction, a width of a second portion of the word line over the device isolation film is greater than a width of a first portion of the word line over the active regions. To manufacture the integrated circuit device, an impurity region is formed in the substrate and the device isolation film by implanting dopant ions into the substrate and the device isolation film, and a thickness of a portion of the impurity region is reduced.

Semiconductor device, and method for manufacturing the same

A semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device includes: a substrate: a drain region vertically disposed on the substrate; a body region vertically disposed on the drain region; a source region vertically disposed on the body region; a bit-line connected to the drain region and extending in a first direction; and a word-line connected to the source region and extending in a second direction that is different from the first direction. The drain region, the body region, and the source region together define a pillar extending in a third direction that is perpendicular to the first and second direction.

Method for fabricating low resistance bit line structures, along with bit line structures exhibiting low bit line to bit line coupling capacitance

A process for fabricating a DRAM chip, featuring low resistance bit line structures, in a peripheral region, and a cell array containing bit line structures exhibiting low bit line to bit line coupling capacitance, has been developed. The process features creating a first damascene opening, in insulator layers in the peripheral region of the DRAM cell, in which the top portion of the first damascene opening is comprised of a deep trench shape, allowing for low resistance bit line structures, when filled with a conductive material. The process also features the creation of second damascene openings, in an insulator layer in the cell array region of the DRAM chip, with the top portion of the second damascene openings exhibiting a shallow trench shape, again allowing bit line structures to be created after filling again with a conductive layer, but with low bit line to bit line coupling capacitance, achieved as a result of the thin metal fill, in the shallow trench opening.

반도체 메모리 소자 및 그의 제조 방법

본 발명은 반도체 소자 및 그의 제조 방법에 관한 것으로서, 더욱 상세하게는, 기판 상에 수직하게 적층된 복수개의 층들을 포함하는 적층 구조체, 상기 복수개의 층들 각각은 반도체 패턴, 상기 반도체 패턴 상에서 제1 방향으로 연장되는 게이트 전극, 및 상기 반도체 패턴과 전기적으로 연결된 정보 저장 요소를 포함하고; 상기 적층 구조체를 관통하는 복수개의 수직 절연체들, 상기 수직 절연체들은 상기 제1 방향으로 배열되며; 및 상기 적층 구조체의 일 측에 제공되어 수직하게 연장되는 비트 라인을 포함한다. 상기 비트 라인은, 적층된 상기 반도체 패턴들을 전기적으로 연결하고, 상기 수직 절연체들 각각은, 제1 수직 절연체 및 상기 제1 수직 절연체에 인접하는 제2 수직 절연체를 포함하며, 상기 게이트 전극은, 상기 제1 수직 절연체와 상기 제2 수직 절연체 사이에 개재된 연결부를 포함한다.

制作半导体元件的方法

本发明公开一种制作半导体元件的方法，包括：首先提供一基底，该基底上具有一存储区以及一周边区，然后形成一第一埋入式栅极以及一第二埋入式栅极于存储区的基底内，形成一第一硅层于周边区的基底上，形成一堆叠层于第一硅层上，形成一外延层于第一埋入式栅极与第二埋入式栅极间的基底上以及形成一第二硅层于存储区的外延层上以及周边区的堆叠层上。

半导体存储装置的形成方法

本发明公开一种半导体存储装置的形成方法，其包含以下步骤。首先，在半导体基底上形成介电层，并在介电层内形成接触垫。然后，在介电层上形成堆叠结构，堆叠结构包含依序堆叠在接触垫上的第一层、第二层与第三层。接着，在堆叠结构上形成图案化掩模层，并且，移除堆叠结构的一部分，而在堆叠结构内形成开口，开口在第二层与第一层内具有倾斜侧壁。然后，垂直地蚀刻开口在第二层内的倾斜侧壁，而形成接触孔。最后，移除图案化掩模层。

미세 패턴 형성 방법

필라(pillar)들의 측벽들을 덮는 스페이서(spacer)층의 일부 부분들이 서로 맞닿아 측방향으로 오목한 골(cleavage) 형상들을 가지는 제1사이 공간(interstitial space)들을 필라들 사이의 중앙 부분에 제공하는 스페이서(spacer)층을 형성하고, 스페이서층 상에 제1사이 공간의 골 형상 부분을 메워 제1사이 공간 내에 제2사이 공간을 제공하는 폴리머(polymer) 물질의 힐링(healing)층을 형성하는 미세 패턴 형성 방법을 제시한다.

Method for making semiconductor device incorporating an electrical contact to an internal conductive layer

A semiconductor device and its method of fabrication are provided. The semiconductor device includes a substrate, a patterning stop region, an insulating overlayer, a container region within the insulating overlayer, a charge storage lamina or conductive layer over an interior surface of the container region; a contact region defined by the charge storage lamina or conductive layer; and an electrical contact in the contact region, wherein respective portions of the electrical contact and the charge storage lamina or conductive layer occupy collectively substantially all of the container region. A bit line terminal is coupled to the charge storage lamina through a switching structure. According to one embodiment of the present invention, a central patterning stop region and a pair of lateral patterning stop regions are provided such that the container region defines a container cross section having an upper container portion and a lower container portion, wherein the lower container portion is positioned between the lateral stop regions, and wherein the upper container portion is wider than the lower container portion.

具有金属双层的电容结构及其使用方法

本发明公开了一种使用金属双层的方法。首先，提供一下电极。其次，提供位于下电极之上并与其直接接触的介电层。然后，提供在一电容中作为上电极的金属双层。金属双层位于介电层之上并与介电层直接接触。金属双层由与介电层直接接触的贵金属以及与贵金属直接接触的金属氮化物所组成。

一种沉积薄膜的方法及其应用、形成半导体有源区的方法

本发明涉及一种沉积薄膜的方法及其应用、形成半导体有源区的方法。一种沉积薄膜的方法，包括下列步骤：在载体表面上沉积籽晶层，然后除杂，再沉积薄膜；其中，所述除杂采用氢气气氛下退火处理或远程氢等离子体表面处理。该方法可以除去碳、氮杂质，提高薄膜表面的均匀性。

플로팅 바디 메모리 및 그 제조방법

플로팅 바디 메모리(Floating body memory)를 제공한다. 반도체기판의 셀 영역에 플로팅 바디 메모리 셀(floating body memory cell)이 배치된다. 상기 반도체기판의 주변 영역에 제 1 플로팅 바디(floating body)가 배치된다. 상기 제 1 플로팅 바디 상에 주변 게이트 패턴이 배치된다. 상기 주변 게이트 패턴 양측에 제 1 소스/드레인 영역들이 배치된다. 상기 제 1 소스/드레인 영역들은 상기 제 1 플로팅 바디와 접촉된다. 상기 제 1 플로팅 바디 및 상기 제 1 소스/드레인 영역들 사이에 제 1 누설차폐 패턴들이 배치된다. 상기 제 1 누설차폐 패턴들은 상기 주변 게이트 패턴의 외측에 정렬될 수 있다.

반도체 장치 및 그 제조방법

셀프얼라인 콘택을 이용하는 반도체장치 및 그 제조방법이 제공된다. 반도체기판의 주표면에 형성된 액티브영역들 사이에는 그 측면에 제1스페이서를 갖는 게이트전극이 형성되고, 상기 게이트전극 및 액티브영역상에 절연막을 개재하여 그 측변에 제2스페이서를 갖는 비트라인전극이 형성된다. 상기 액티브영역 상에 셀프얼라인 콘택이 형성되고, 상기 콘택을 통해 액티브영역에 접속되는 제1패트전극이 상기 비트라인전극들 사이에 형성된다. 상기 비트라인전극 상에는 비트라인콘택 및 상기 비트라인 콘택을 통해 상기 비트라인전극에 접속되는 제2패트전극과 상기 제1패드전극에 접속되는 제3패드전극이 각각 형성된다. 따라서, 상기 비트라인 콘택과 이후에 형성될 스토리지노드 콘택의 정렬오차허용도를 극대화시켜서 신뢰성있는 반도체장치를 구현할 수 있다.

소자분리막을 갖는 반도체 소자 및 그 제조 방법

반도체 소자 제조 방법은 활성 영역의 밀도가 서로 다른 셀 영역과 주변 영역을 포함하는 기판을 준비하는 단계; 상기 셀 영역에서 셀 활성 영역을 한정하는 셀 트렌치를 형성하되, 상기 셀 활성 영역을 제1 방향을 따라 제1 폭으로 이격하며 제2 방향을 따라 제2 폭으로 이격하여 형성하는 단계; 상기 주변 영역에서 주변 활성 영역을 한정하는 주변 트렌치를 형성하는 단계; 및 상기 셀 트렌치 내에 상기 셀 활성 영역의 측벽에 접촉하면서 상기 제1 방향과 상기 제2 방향으로 연속적으로 연장되는 제1 절연막을 형성하되, 상기 제1 절연막의 두께를 상기 제1 폭의 1/2과 동일하거나 그보다 두껍고 상기 제2 폭의 1/2보다 얇게 형성하는 단계를 포함할 수 있다.

Method for cleaning high-class fiber

(57)【要約】 【課題】 ウェハに形成されるデバイスの平坦性が確保 され、異物の発生の低減が図られる回路パターンが形成 されたウェハとその製造方法を提供する。 【解決手段】 ゲート電極４Ｍ、データ線６Ｍ、ストレ ージノード８Ｍ、セルプレート１０Ｍ、第１〜第３配線 層１２Ｍ、１４Ｍ、１６Ｍ、パッシベーション膜１７Ｍ をそれぞれ形成するためのドープトポリシリコン膜４ Ｐ、６Ｐ、８Ｐ、１０Ｐ、アルミ銅膜１２Ｐ、１４Ｐ、 １６Ｐ、シリコン窒化膜１７Ｐが、デバイス非形成部Ｐ においては、それぞれパターニングが施されずにデバイ ス非形成部Ｐを覆う膜として形成されている。

Local connection structure and method of bottom of self storage capacitor for DRAM

본 발명은 DRAM 집적회로(50)용 하부 커패시터 전극(67)을 위한 방법 및 구조에 관한 것으로, 폴리실리콘 게이트층(64)은 반도체 기판(49)의 제1영역내의 얇은 옥사이드층위에 형성되고, 다음에 다른 하나의 옥사이드층(62)은 폴리실리콘 게이트 층(64)위에 형성된다. 폴리실리콘층(121)은 소스/드레인 주입에 의해 도프되고 자체 정렬하는 하부 커패시터 전극(131)을 포함하며 반도체 기판(100)의 제2영역 위에 형성하고 폴리실리콘 게이트 층(110)위의 옥사이드층(108)을 덮는다. 질화물층(127)은 제2영역 위에 있는 하부 커패시터 전극(131)부위 위에 형성한다. 다음에 폴리실리콘층(121)의 노광된 부분(132)이 산화된다. 상기 소스/드레인(114,116)은 주입된 제2폴리실리콘층으로 부터 불순물 작용에 의해 형성되었다. 하부 커패시터 전극(131)에 대응하는 질화물층 아래의 폴리실리콘 부분(121)은 폴리실리콘(121)의 노광된 부분보다 낮은 비율로 산화한다. 이와같은 순차적 단계들은 DRAM집적 회로(50)를 위한 자체 정열된 하부 커패시터 전극(67)을 형성한다.

Manufacturing Method of Semiconductor Device

휴즈부를 부주의로 단선시키지 않기 위해 휴즈부 상에 보호막을 형성하는 경우는 보호막 형성을 위한 제조 공정이 필요하게 된다. 층간 절연막(230)을 선택적으로 에칭 제거함으로써, 원통형 캐패시터(125a, 125b)의 셀 플레이트(129) 상의 층간 절연막(230) 영역에 형성된 단차 부분(231)을 제거함과 동시에, 휴즈부(130) 상에 요부(141)를 형성한다. 이때, 셀 플레이트(129)를 노출하지 않을 정도로 에칭을 종료하기 때문에 휴즈부(130)가 노출하는 일없이 휴즈부(130)상에 요부(141)가 형성된다.

Manufacturing method of semi-floating gate memory and semi-floating gate memory

本发明提供了一种半浮栅存储器的制造方法，包括：提供第一掺杂类型的衬底；在所述衬底上生成与所述衬底导电类型相反的第一半导体和第二半导体；同时生成隧穿层和阻挡层，其中所述隧穿层设于所述衬底与所述第一半导体平行邻接，所述第二半导体覆盖所述隧穿层和所述第一半导体，所述阻挡层覆盖所述第二半导体，隧穿层和阻挡层同时生成，减少工艺步骤，降低工艺复杂度，大大提高了生产效率。另外，当第一半导体与衬底构成二极管结构导通时，加快数据的写入，实现了数据的快速存储功能，并且由于二极管结构和隧穿层，使数据的保存时间大大提高。另外，本发明还公开了一种半浮栅存储器。

Semiconductor device fabrication method

휴즈부를 부주의로 단전시키지 않기 위해 휴즈부 상에 보호막을 형성하는 경우는 보호막 형성을 위한 제조 공정이 필요하게 된다. 층간 절연막(230)을 선택적으로 에칭 제거함으로써, 원통형 캐패시터(125a, 125b)의 셀 플레이트(129) 상의 층간 절연막(230) 영역에 형성된 단차 부분(231)을 제거함과 동시에, 휴즈부(130) 상에 요부(141)를 형성한다. 이 때, 셀 플레이트(129)를 노출하지 않을 정도로 에칭을 종료하기 때문에 휴즈부(130)가 노출하는 일 없이 휴즈부(130) 상에 요부(141)가 형성된다.

A memory cell, an array, and a method for manufacturing a memory cell

一种存储器单元(100)包括一晶体管，晶体管包括：一基板(101)；一第一源极/漏极区(102)；一第二源极/漏极区(112)；一栅极(104)；及一栅极绝缘层(103)，设置于基板(101)及栅极(104)之间；其中栅极绝缘层(103)直接接触基板(101)且包括多个电荷陷阱(131)，该多个电荷陷阱(131)分布于栅极绝缘层(101)整个体积。

Semiconductor memory device and method of fabricating the same

반도체 메모리 소자가 제공된다. 이 소자는 기판에 배치되며 서로 이격된 제 1 불순물 영역과 제 2 불순물 영역, 상기 제 2 불순물 영역의 상면은 상기 제 1 불순물 영역의 상면보다 높고; 상기 제 1 불순물 영역과 상기 제 2 불순물 영역 사이에 개재되는 소자분리 패턴; 상기 제 1 불순물 영역과 접하며, 상기 제 2 불순물 영역의 상면보다 낮은 하부면을 가지는 제 1 콘택 플러그; 상기 제 1 콘택 플러그와 상기 제 2 불순물 영역 사이에 개재되는 매립 절연 패턴; 상기 매립 절연 패턴과 상기 제 2 불순물 영역 사이에 개재되는 제 1 보호 스페이서; 상기 제 1 콘택 플러그의 측면 및 상기 소자분리 패턴과 접하며, 상기 제 1 보호 스페이서와 상기 매립 절연 패턴 사이로 개재되는 제 1 스페이서를 포함한다.

Memory device and method of manufacturing the same

반도체 소자 및 이의 제조방법이 개시된다. 반도체 소자는 소자 분리막에 의해 한정되는 다수의 활성영역을 구비하는 기판, 상기 활성영역을 가로질러 제1 방향을 따라 연장하고 제2 방향을 따라 일정한 간격으로 정렬하는 다수의 워드라인들, 상기 활성영역에 배치되어 불순물을 포함하고, 상기 활성영역의 중앙부에 위치하는 제1 접합부 및 상기 활성영역의 양 단부에 위치하고 내부에 매립 반도체막을 구비하는 제2 접합부를 포함하는 접합영역, 상기 제1 방향을 따라 일정한 간격을 갖도록 상기 제2 방향을 따라 연장하고 상기 제1 접합부와 접속하는 다수의 비트라인들 및 상기 제2 접합부와 접속하도록 상기 비트라인 사이에 위치하여 상기 매립 반도체 막과 함께 데이터를 저장하는 전하 저장부와 연결되는 스토리지 콘택 구조물을 형성하는 매립 콘택을 포함한다. 스토리지 콘택 구조물의 접촉면적을 확장하여 접촉저항을 감소시킬 수 있다.

Method for forming semiconductor structure

本发明实施例提供一种半导体结构的形成方法，所述半导体结构包括第一区域以及第二区域，包括：提供依次堆叠设置的基底、绝缘层以及掩膜层，所述第一区域具有贯穿所述掩膜层以及所述绝缘层的至少一个沟槽，所述第二区域的所述掩膜层的上表面高于所述第一区域的所述掩膜层的上表面；形成第一保护层，所述第一保护层覆盖所述第一区域的所述掩膜层的上表面和侧壁；在形成所述第一保护层后，去除所述第二区域的所述掩膜层；在去除所述第二区域的所述掩膜层之后，去除所述第一保护层；去除所述第一区域的所述掩膜层。本发明实施例提供的半导体结构的形成方法，有利于提高半导体结构的平整度。

Semiconductor element and manufacturing method thereof

本发明公开一种半导体元件及其制作方法，该制作半导体元件的方法为，主要先形成一氮化钛层于一硅层上，然后进行一第一处理制作工艺将氮化钛层以及二氯硅甲烷(dichlorosilane,DCS)反应形成一氮化钛硅(TiSiN)层，形成一导电层于氮化钛硅层上，再图案化该导电层、该氮化钛硅层以及该硅层以形成一栅极结构。

Semiconductor structure with capacitance connecting pad and manufacturing method of capacitance connecting pad

本发明公开一种具有电容连接垫的半导体结构与电容连接垫的制作方法，具有电容连接垫的半导体结构包含一基底，一电容接触插塞设置于基底上，一电容连接垫接触并连结电容接触插塞，一位线设置于基底上以及一介电层围绕电容连接垫，介电层具有一底面低于位线的一顶面。

Semiconductor devices

반도체 소자는 기판 상에 상기 기판의 상면에 평행한 제1 방향으로 서로 이격되는 하부 전극들, 상기 하부 전극들의 상부 측면들 상의 상부 지지 패턴, 및 상기 하부 전극들의 하부 측면들 상의 하부 지지 패턴을 포함한다. 상기 하부 지지 패턴은 상기 기판과 상기 상부 지지 패턴 사이에 배치된다. 상기 하부 전극들 중 적어도 하나의 하부 전극은, 상기 하부 지지 패턴의 하면에 인접한 제1 리세스를 포함한다.

Semiconductor structure and forming method thereof

本发明涉及半导体制造技术领域，尤其涉及一种半导体结构及其形成方法。所述半导体结构的形成方法包括如下步骤：形成一衬底，所述衬底内具有多条字线、位于相邻两条字线之间的导电接触区、以及位于每一所述字线与所述导电接触区之间的隔离层；降低所述导电接触区的高度，于相邻所述隔离层之间形成孔；自所述孔刻蚀所述导电接触区，形成与所述孔连通的沟槽，所述沟槽的宽度小于所述孔的宽度；形成填充满所述孔与所述沟槽的接触插塞。本发明增大了接触插塞与导电接触区之间的接触面积，从而降低接触插塞与导电接触区之间的接触电阻，改善了半导体结构的性能，提高了半导体结构的良率。

The production method of semiconductor storage

本发明公开一种半导体存储装置的制作方法，包括下列步骤。在一半导体基底上形成多个位线结构，且在多个位线结构之间形成多个存储节点接触。存储节点接触的方法包括于半导体基底上形成多个导电图案，并对导电图案进行一回蚀刻制作工艺，用以降低导电图案的高度。在多个导电图案之间形成多个隔离图案，且隔离图案于形成导电图案的步骤之后以及回蚀刻制作工艺之前形成。本发明的制作方法是利用先形成导电图案再于导电图案之间形成隔离图案的方式来形成存储节点接触，由此达到制作工艺简化以及制作工艺良率提升的效果。

Manufacture of semiconductor memory device

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Semiconductor memory device and method of fabricating the same

A semiconductor memory device and a method for manufacturing the same are provided to increase the capacitance and the charge retention time by forming an expanded body region. An insulating layer(102) is formed on a substrate(101). A charge storage region(103a) of first conductive type is formed on the insulating layer. An insulating layer(200) is surrounded to the surface except for the surface of the charge storage region. A body region(210) of first conductive type is formed on the charge storage region. A gate stack(430) including a gate insulating layer and a gate electrode is formed on the body region. A source region(220) and a drain region(230) are spaced apart from the body region. The center portion of the body region is contacted with the charge storage region, so that the body region is expanded.

Semiconductor device and method for manufacturing the same

本发明公开了一种半导体装置及其制造方法，所述半导体装置包括基材、第一主动区、第二主动区以及闸极结构。第一主动区和第二主动区设于基材中。闸极结构包括底部、和第一主动区连接的第一侧壁，以及和第二主动区连接的第二侧壁。第一侧壁和底部具有第一交点，从第一交点往基材延伸出第一水平线，而第一侧壁和第一水平线具有第一夹角。第二侧壁和底部具有第二交点，从第二交点往基材延伸出第二水平线，而第二侧壁和第二水平线具有第二夹角。第一夹角与第二夹角不同。根据本发明，即便缩减半导体装置的尺寸，但两相邻闸极堆叠的底部之间的距离可保持固定，因此半导体装置中可以不产生字元线(WL)间干扰，进而增进较小尺寸的半导体装置的效能。

Manufacturing method of semi-floating gate memory and semi-floating gate memory

本发明提供了一种半浮栅存储器的制造方法，包括：提供第一掺杂类型的衬底；在所述衬底上生成与所述衬底导电类型相反的第一半导体和第二半导体；同时生成隧穿层和阻挡层，其中所述隧穿层设于所述衬底与所述第一半导体平行邻接，所述第二半导体覆盖所述隧穿层和所述第一半导体，所述阻挡层覆盖所述第二半导体，隧穿层和阻挡层同时生成，减少工艺步骤，降低工艺复杂度，大大提高了生产效率。另外，当第一半导体与衬底构成二极管结构导通时，加快数据的写入，实现了数据的快速存储功能，并且由于二极管结构和隧穿层，使数据的保存时间大大提高。另外，本发明还公开了一种半浮栅存储器。

Semiconductor device including reservoir capacitor and method for fabricating the same

본 발명은 주변 영역에 포함되는 저장 캐패시터를 정전용량을 증가시키기 위해 수평방향 및 수직방향의 빈 공간에 캐패시터를 형성할 수 있는 반도체 장치의 제조 방법을 제공한다. 본 발명의 일 실시예에 따른 반도체 기억 장치의 제조 방법은 모스 트랜지스터를 이용한 제 1 캐패시터를 형성하는 단계, 셀 캐패시터와 동일한 기둥 형태의 제 2 캐패시터를 형성하는 단계, 및 제 1 캐패시터와 제 2 캐패시터 상부에 제 3 캐패시터를 형성하는 단계를 포함한다.

Semiconductor integrated circuit structure and preparation method thereof

半导体集成电路结构及其制作方法。该半导体集成电路结构包含有其上定义有一记忆胞区域与一周边区域的基底、多个设置于该记忆胞区域内的记忆胞、至少一形成于该周边区域内的主动元件、多个形成于该记忆胞区域内的接触插塞、以及至少一形成于该记忆胞区域内的位线。该等接触插塞与该位线是物理接触以及电性连接，且该等接触插塞的一底部表面低于该基底的一表面。

Semiconductor device

내용 없음. No content.

Semiconductor memory device

본 발명은 반도체 메모리 소자에 관한 것으로서, 더욱 상세하게는, 기판 상에 수직하게 적층된 복수개의 층들을 포함하는 적층 구조체, 상기 복수개의 층들 각각은 제1 방향으로 연장되는 비트 라인 및 상기 비트 라인으로부터 상기 제1 방향과 교차하는 제2 방향으로 연장되는 반도체 패턴을 포함하고; 상기 적층 구조체를 관통하는 홀 내에 제공된 게이트 전극, 상기 게이트 전극은 적층된 상기 반도체 패턴들을 따라 수직하게 연장되며; 상기 게이트를 덮으며 상기 홀을 채우는 수직 절연막; 상기 홀을 채우는 정지막; 및 각각의 상기 반도체 패턴들과 전기적으로 연결된 정보 저장 요소를 포함한다. 상기 정보 저장 요소는: 각각의 상기 반도체 패턴들과 전기적으로 연결되는 제1 전극; 상기 제1 전극 상의 제2 전극; 및 상기 제1 전극과 상기 제2 전극 사이에 개재된 유전막을 포함하고, 상기 정지막은, 상기 수직 절연막과 상기 제2 전극 사이에 개재된다.

Semiconductor device incorporating dram section and logic section and manufacture thereof

DRAM부와 논리 회로부를 합체시킨 반도체 장치를 제조하는 방법에 있어서, 내화 금속층은 DRAM부의 비트 라인(7a), 및 논리 회로부의 게이트 전극(4)와 불순물 확산 영역(5, 9)를 피복하도록 형성된다. 그 다음, 가열 동작은 상기 내화 금속층 상에서 수행되어, 금속 실리사이드층(10a, 10b, 10c)이 DRAM부의 비트 라인, 및 논리 회로부의 게이트 전극과 불순물 확산 영역 내에 형성된다. In a method of manufacturing a semiconductor device incorporating a DRAM portion and a logic circuit portion, the refractory metal layer is formed so as to cover the bit line 7a of the DRAM portion, the gate electrode 4 of the logic circuit portion, and the impurity diffusion regions 5 and 9. do. Then, a heating operation is performed on the refractory metal layer so that metal silicide layers 10a, 10b, and 10c are formed in the bit line of the DRAM portion and the gate electrode and impurity diffusion region of the logic circuit portion.

Method for fabricating Semiconductor device

반도체 장치 제조 방법이 제공된다. 상기 반도체 장치 제조 방법은 기판 상에 층간 절연막 및 희생막들이 교대로 반복 적층된 몰드 구조체를 형성하고, 상기 몰드 구조체를 관통하는 채널 홀을 형성하고, 상기 채널 홀 내에 수직 채널 구조체를 형성하고, 상기 희생막들을 제거하여 상기 층간 절연막의 표면을 노출시키고, 상기 층간 절연막의 표면을 따라서 알루미늄 산화막을 형성하고, 상기 알루미늄 산화막 상에 TiON 연속막을 형성하고, 상기 TiON 연속막을 질화시켜 TiN막을 형성하는 것을 포함한다. A method of manufacturing a semiconductor device is provided. The semiconductor device manufacturing method includes forming a mold structure in which an interlayer insulating film and a sacrificial film are alternately stacked on a substrate, forming a channel hole passing through the mold structure, forming a vertical channel structure in the channel hole, and removing the sacrificial films to expose the surface of the interlayer insulating film, forming an aluminum oxide film along the surface of the interlayer insulating film, forming a TiON continuous film on the aluminum oxide film, and nitriding the TiON continuous film to form a TiN film do.

Methods for fabricating semiconductor device with fine pattenrs

반도체 기판에 활성 라인(active line)들을 형성하고, 활성 라인들을 교차하는 콘택 라인(contact line)들의 배열을 형성한 후, 활성 라인에 교차되는 콘택 라인 부분에 중첩되게 콘택 라인들을 교차하는 라인 패턴(line pattern)들을 포함하는 식각 마스크(mask)를 형성하고, 식각 마스크에 노출되는 상기 콘택 라인 부분들을 선택적으로 식각하여 콘택 패턴들 및 사이의 콘택 분리 홈들을 형성하고, 콘택 분리 홈들에 노출되는 활성 라인 부분들을 선택적으로 식각하여 활성 패턴 분리 홈들을 형성하여 개개의 활성 패턴들을 분리하고, 활성 패턴들을 가로지르는 트랜지스터의 게이트(gate)들을 형성하고, 콘택 패턴들에 연결되는 비트 라인(bit line)들을 형성하는 반도체 소자 제조 방법을 제시한다.

Fabrication of semiconductor element

(57)【要約】 【課題】 全体的平面化およびコンデンサの面積増大を 図りつつ、高密度化を可能にする半導体素子の形成方法 を提供する。 【解決手段】 コンデンサを有する半導体素子の形成方 法であって、コンデンサは、半導体基板内に形成された キャビティ内に配され、高密度メモリの一部となる。一 実施例では、まず、キャビティ内に下側電極を形成し、 次いで犠牲層でキャビティを充填し、コンデンサ電極の 少なくとも一方の化学機械式研摩（ＣＭＰ）を可能にす る。下側電極の部分および犠牲層の部分を除去した後、 誘電体層を形成する。次に、誘電体層上に上側電極を形 成する。こうして形成された誘電体層は、下側電極を上 側電極から分離し、短絡および漏れ電流を防止する。一 実施例では、多数の下側電極に対して単一の上側電極層 を形成することにより、メモリ回路の複雑度を低下させ る。

Semiconductor storage device

(57)【要約】 【課題】 スクライブ線内に特性モニタ用チェックパタ ンを配置することにより製品チップの面積増大を防ぎつ つ、更に製造工程中のゴミの発生を防ぎ、製造歩留まり の良い半導体記憶装置を提供する。 【解決手段】 スクライブ線２４内には従来通りチェッ クパタンが配置されている。しかし、ここに配置されて いるのはメモリセル関係以外のチェックパタン１９であ り、メモリセルに関係するチェックパタン１０はメモリ セル領域２２に隣接して配置されている。このとき、製 品チップ１１上に配置されるチェックパタンはメモリセ ルに関係したチェックパタンに限定されているため、そ の数も１種類又は２種類と極めて少なく、この程度なら 製品チップ１１上に配置する領域を確保することは可能 であるし、これにより製品チップの面積には殆ど影響し ない。

Method for forming contact in semiconductor device

본 발명은 SPE 또는 SEG보다 양산성을 확보하면서 반도체 소자의 콘택저항을 감소시키기 위한 반도체 소자의 콘택 형성방법을 제공하기 위한 것으로, 본 발명은 반도체 기판 상부에 콘택홀을 형성하는 단계, 상기 콘택홀의 바닥부에 실리콘층을 형성하는 단계, 이온주입을 실시하여 상기 반도체 기판의 일부를 비정질화시키는 단계, 열처리하여 상기 비정질화된 반도체 기판의 일부 및 실리콘층을 에피택셜성장시키는 단계, 상기 에피택셜성장된 실리콘층 상에 금속실리사이드와 금속막을 형성하는 단계를 포함하고, 상기한 본 발명은 SPE 또는 SEG보다 양산성을 확보하면서 반도체 소자의 콘택저항 감소, 신뢰성 및 수율 향상에 효과가 있다. The present invention is to provide a method for forming a contact of a semiconductor device for reducing the contact resistance of the semiconductor device while ensuring mass production than SPE or SEG, the present invention is to form a contact hole on the semiconductor substrate, the contact hole Forming a silicon layer on a bottom portion, performing ion implantation to amorphousize a portion of the semiconductor substrate, and heat treating to epitaxially grow a portion of the amorphous semiconductor substrate and a silicon layer, wherein the epitaxially grown Forming a metal silicide and a metal film on the silicon layer, the present invention is effective in reducing the contact resistance, reliability and yield of the semiconductor device while ensuring mass production than SPE or SEG. 에피택셜실리콘, 콘택저항, 폴리실리콘, 고상에피택시, 단결정실리콘층 Epitaxial silicon, contact resistance, polysilicon, solid phase epitaxy, single crystal silicon layer

Semiconductor memory device having minute size contact window and manufacturing method thereof

미세 크기의 접촉창을 가지는 반도체 메모리 장치 및 그 제조 방법에 관하여 개시한다. 본 발명은 반도체 기판의 셀 영역에 형성된 복수 개의 제1 도전층 패턴과, 층간 절연층을 매개로 상기 제1 도전층 패턴과 직교하는 복수 개의 제2 도전층 패턴과 상기 제2 도전층 패턴의 윗면과 측벽을 각각 보호하는 식각 저지층 패턴 및 스페이서를 마스크로 이용하여 사진 식각 공정으로 형성한 접촉창을 포함하는 것을 특징으로 한다. 본 발명에 의해서, 접촉창을 형성하기 위한 상기 포토레지스트 패턴을 라인 모양으로 형성하기 때문에 집적도의 증가에 따라 상기 매몰 접촉창의 크기가 감소하여도 사진 묘화 공정이 용이하고, 상기 식각 저저층 패턴 및 상기 스페이서에 의해서 보호되는 방향은 정렬이 필요없다.

Method for forming capacitor having cylinder type storage electrode and mask for the same

실린더형 캐패시터 형성 후 층간절연막을 형성할 때 심(seam)이 발생하는 것을 방지할 수 있는 반도체 소자의 캐패시터 형성방법은, 셀 영역을 포함하는 반도체기판 상에 층간절연막을 형성하는 단계와, 층간절연막에, 반도체기판과 접속된 스토리지노드 컨택을 형성하는 단계와, 스토리지노드 컨택을 포함하는 층간절연막 상에 몰드층 및 지지층을 형성하는 단계와, 몰드층 및 지지층을 패터닝하여 셀 영역에는 스토리지노드 홀을, 셀 영역의 가장자리에는 더미 스토리지노드 홀을 형성하는 단계와, 스토리지노드 홀 및 더미 스토리지노드 홀의 내벽에, 노드분리된 스토리지 전극 및 더미 스토리지 전극을 형성하는 단계와, 더미 스토리지 전극 외부로 500Å 이내로 잔류하도록 레이아웃된 지지층 마스크를 사용하여 지지층을 패터닝하는 단계와, 몰드층을 제거하여 실린더 구조의 스토리지 전극을 형성하는 단계, 및 스토리지 전극 위에 유전체막 및 플레이트 전극을 형성하는 단계를 포함한다. In the method of forming a capacitor of a semiconductor device capable of preventing a seam from occurring when forming an interlayer insulating film after forming a cylindrical capacitor, the method of forming a capacitor of a semiconductor device includes forming an interlayer insulating film on a semiconductor substrate including a cell region; Forming a storage node contact connected to the semiconductor substrate, forming a mold layer and a support layer on the interlayer insulating layer including the storage node contact, and patterning the mold layer and the support layer to form a storage node hole in the cell region. Forming a dummy storage node hole at an edge of the cell region, forming a node-separated storage electrode and a dummy storage electrode on inner walls of the storage node hole and the dummy storage node hole, and remaining within 500 Å of the dummy storage electrode Patterning the support layer using a support layer mask laid out to support the mold layer; Removed by a step, and the storage electrode to form a dielectric film and a plate electrode on the storage electrode to form a cylindrical structure. 실린더형 스토리지 전극, NFC, 지지층, 심(seam), 브리지(bridge) Cylindrical storage electrode, NFC, support layer, seam, bridge

Semiconductor device and method for fabricating the same

반도체 장치 및 그 제조 방법이 제공된다. 반도체 장치는, 하부 반도체막, 매립 절연막 및 상부 반도체막이 순차적으로 적층된 기판, 상부 반도체막 내의 제1 트렌치, 제1 트렌치의 일부를 채우는 제1 도전 패턴, 하부 반도체막, 매립 절연막 및 상부 반도체막 내의 제2 트렌치, 제2 트렌치의 적어도 일부를 채우는 제2 도전 패턴, 및 제1 도전 패턴 및 제2 도전 패턴 사이에, 상부 반도체막 내의 제1 소스/드레인 영역을 포함한다.

Method of forming patterns for semiconductor device

반도체 소자의 패턴 형성 방법은, 제1 및 제2 영역들을 갖는 식각 대상막 상에 하드 마스크막을 형성한다. 제1 및 제2 영역들의 하드 마스크막 상에 제1 및 제2 예비 마스크 패턴 구조물들 및 이들의 측벽 및 상면을 덮는 스페이서막을 형성한다. 제1 및 제2 예비 마스크 패턴 구조물들, 및 스페이서막을 부분적으로 제거하여, 제1 예비 마스크 패턴 구조물의 측벽을 덮는 제1 스페이서, 및 제1 스페이서의 상면보다 높은 상면을 가지며 제2 예비 마스크 패턴 구조물의 측벽을 덮는 제2 스페이서를 각각 형성한다. 제1 예비 마스크 패턴 구조물을 제거한다. 하드 마스크막을 부분적으로 제거하여, 제1 폭을 갖는 제1 마스크 패턴 구조물, 및 제1 폭보다 넓은 제2 폭을 가지며 제1 마스크 패턴 구조물의 상면보다 높은 상면을 갖는 제2 마스크 패턴 구조물을 각각 형성한다. 식각 대상막을 부분적으로 제거하여, 제3 폭을 갖는 제1 패턴 구조물, 및 제3 폭보다 넓은 제4 폭을 가지며 제1 패턴 구조물의 상면보다 높은 상면을 갖는 제2 패턴 구조물을 각각 형성한다. In a method of forming a pattern of a semiconductor device, a hard mask layer is formed on a layer to be etched having first and second regions. A spacer layer covering first and second preliminary mask pattern structures and sidewalls and upper surfaces thereof is formed on the hard mask layer in the first and second regions. The first and second preliminary mask pattern structures, and the first spacer covering the sidewall of the first preliminary mask pattern structure by partially removing the spacer layer, and a second preliminary mask pattern structure having an upper surface higher than the upper surface of the first spacer Each of the second spacers covering the sidewalls is formed. The first preliminary mask pattern structure is removed. By partially removing the hard mask layer, a first mask pattern structure having a first width and a second mask pattern structure having a second width wider than the first width and having an upper surface higher than the upper surface of the first mask pattern structure are formed, respectively. do. By partially removing the etching target layer, a first pattern structure having a third width and a second pattern structure having a fourth width wider than the third width and having an upper surface higher than the upper surface of the first pattern structure are formed, respectively.

Semiconductor integrated circuit device equipped with power make-up circuit used in burn-in test after packaging and method for testing the same

사용자는 패키징 이후의 반도체 다이나믹 랜덤 억세스 메모리 장치를 번-인 테스트할 수 있고, 외부 핀(21)과 내부 전원선(202) 사이에 전력 전송 회로(6)가 접속되는데, 전력 전송 회로는 외부 고 전원 전압을 다른 저 전압과 구별하여 외부 핀을 내부 전원선에 연결시킴으로써, 사용자가 번-인 테스트를 고속으로 행할 수 있게 해준다.

Semiconductor device and its manufacture

Substrate having a charged zone in an insulating buried layer

본 발명은 베이스 웨이퍼(1), 절연층(2) 및 상부 반도체 층(3)을 연속하여 포함하는 기판에 관한 것으로서, 상기 절연층(2)이 절댓값으로 10 10 전하/cm 2 보다 높은 전하 밀도를 갖는 적어도 하나의 영역을 포함하는 것을 특징으로 한다. 또한, 본 발명은 이러한 기판을 제조하기 위한 방법에 관한 것이다. The present invention relates to a substrate comprising a base wafer (1), an insulating layer (2) and an upper semiconductor layer (3) in series, wherein the insulating layer (2) has an absolute higher charge density than 10 10 charge / cm 2. It characterized in that it comprises at least one region having. The invention also relates to a method for producing such a substrate.

Well Forming Method of Semiconductor Device

본 발명은 반도체 소자의 웰 형성방법에 관한 것으로, 반도체 기판상의 주변회로부에 완충막과, 상기 완충막 위에 산화가능막과, 상기 산화가능막 위에 산화방지막을 형성하는 공정과; 상기 산화가능막의 표면이 일부 드러나도록 산화방지막을 소정 부분 식각하는 공정과; 열산화를 실시하여 주변회로부의 산화가능막이 노출된 부분과, 기판 표면이 노출된 셀 형성부에 필드 산화막을 형성하는 공정과; 상기 산화방지막과 산화가능막 및 완충막을 제거하는 공정과; 고 에너지로 제1도전형 불순물을 이온주입하는 공정과; 상기 필드 산화막을 마스크로 하여 저 에너지로 제2도전형 불순물을 이온주입하는 공정 및; 상기 필드 산화막을 제거하고, 확산을 실시하여 제1및 제2도전형 웰을 형성하는 공정을 포함하여 소자 제조를 완료하므로써, 1) 공정단순화를 기할 수 있게 되어 공정 시간 단축 및 생산성 향상을 이룰 수 있으며, 2) 고 에너지 이온주입시 필수적으로 이용되는 4㎛ 이상의 두꺼운 감광막을 사용할 필요가 없어 고에너지 이온주입 과정에서 감광막 입자에 의해 발생되는 실리콘 기판의 격자 손상(defect)을 방지할 수 있고, 3) 래치-업 내성(immunity)을 향상시킬 수 있는 고신뢰성의 반도체 소자를 구현할 수 있게 된다.

Semiconductor memory device and method of fabricating the same

Disclosed are a semiconductor memory device and a method of fabricating the same. The device may include a first substrate comprising a cell array region, a first interlayer insulating layer covering the first substrate, a second substrate disposed on the first interlayer insulating layer, the second substrate including a core region electrically connected to the cell array region, a first adhesive insulating layer interposed between the first interlayer insulating layer and the second substrate, and contact plugs penetrating the second substrate, the first adhesive insulating layer, and the first interlayer insulating layer and electrically connecting the cell array region with the core region.

Planarization method

本发明公开一种平坦化方法，包含提供一基底，具有一主表面。一凸起结构，位于主表面上。形成一绝缘层，共型地覆盖主表面以及凸起结构的顶面及侧壁。形成一停止层，位于绝缘层上并且至少覆盖凸起结构的顶面。然后全面性地形成一第一介电层，并以一化学机械研磨制作工艺移除部分第一介电层直到暴露出停止层，得到一上表面。形成一预定厚度的第二介电层，覆盖上表面。

Manufacture of semiconductor device

提供一种不使位线与字线连接而以自行调整的方式连接在半导体衬底上且不产生成结晶缺陷的半导体装置。在半导体(例如Si)衬底1上依次分别形成元件分离绝缘膜2、栅氧化膜3、栅极4(字线)、绝缘膜5之后，形成侧壁6a～6f。此时，形成衬底保护氧化膜6g～6i，从而不使半导体衬底1露出。在形成源/漏区261～263之后，淀积由Si 3 N 4 或SiON等构成的绝缘膜7，此后在全部表面上形成层间绝缘膜8。绝缘膜7与层间绝缘膜8相比刻蚀速度慢。

Dual-gate mosfet based memory device and manufacturing method thereof

Disclosed are a dual-gate metal-oxide-semiconductor field-effect transistor (MOSFET) based memory element and a manufacturing method thereof. The manufacturing method of the dual-gate MOSFET based memory element comprises the following steps of: forming an oxide film on a bulk silicon substrate; depositing polysilicon on the oxide film; heat-treating and crystallizing the polysilicon; depositing a plurality of gate insulating films spaced apart from each other on the polysilicon; forming a floating gate and a control gate by depositing a gate metal on the plurality of gate insulating films; and doping impurities in a first region and a second region of the polysilicon in which the gate insulating films are not deposited to form a source region and a drain region, respectively.

Method for forming the pattern of honeycomb array

一种用于形成图案的方法包括在底层上形成椭圆形柱体。椭圆形柱体具有细长的特征，并且包括突出侧以及与突出侧连接的长侧，并且四个椭圆形柱体在分离空间的周围形成菱形阵列。附接至椭圆形柱体的侧面的引导晶格形成为在分离空间内打开第一窗口。通过选择性地去除椭圆形柱体，而在引导晶格内形成第二窗口。嵌段共聚物层形成为填充第一窗口和第二窗口。将嵌段共聚物层相分离，以在第一窗口内形成第一区域和第一矩阵以及在第二窗口内形成多个第二区域和第二矩阵。选择性地去除第一区域和第二区域，以形成第一开口和第二开口。