CONDUCTIVE BUMP FOR SEMICONDUCTOR SUBSTRATE AND METHOD OF MANUFACTURE

An embodiment of the disclosure includes a conductive bump on a semiconductor die. A substrate is provided. A bond pad is over the substrate. An under bump metallurgy (UBM) layer is over the bond pad. A copper pillar is over the UBM layer. The copper pillar has a top surface with a first width and sidewalls with a concave shape. A nickel layer having a top surface and a bottom surface is over the top surface of the copper pillar. The bottom surface of the nickel layer has a second width. A ratio of the second width to the first width is between about 0.93 to about 1.07. A solder material is over the top surface of the cap layer. 1. A semiconductor die comprising:a substrate;a bond pad over the substrate;an under bump metallurgy (UBM) layer over the bond pad;a copper pillar over the UBM layer, the copper pillar having a top surface with a first width and sidewalls with a concave shape;a nickel cap layer having a top surface and a bottom surface over the top surface of the copper pillar, the bottom surface of the nickel cap layer having a second width, wherein a ratio of the second width to the first width is between about 0.93 to about 1.07; anda solder material over the top surface of the nickel cap layer.2. The semiconductor die of claim 1 , wherein the solder material comprises lead free solder.3. The semiconductor die of claim 1 , further comprising a smooth interface between the conductive pillar and the nickel cap layer.4. The semiconductor die of claim 1 , wherein the ratio of the second width to the first width is between about 0.93 to about 0.99.5. A method of forming a semiconductor die comprising:providing a substrate;forming a bond pad over the substrate;depositing an under bump metallurgy (UBM) layer over the bond pad;forming a copper pillar over the UBM layer;depositing a nickel layer over the copper pillar, wherein an interface is defined between the nickel layer and the copper pillar;depositing a solder material over the nickel layer;{'sub': 3', '4, ' ...

Doping Minor Elements into Metal Bumps

A method of forming a device includes providing a substrate, and forming a solder bump over the substrate. A minor element is introduced to a region adjacent a top surface of the solder bump. A re-flow process is then performed to the solder bump to drive the minor element into the solder bump. 1. A method of forming a device , the method comprising:providing a substrate;forming a solder bump over the substrate;introducing a minor element to a region adjacent a top surface of the solder bump; andperforming a re-flow process to the solder bump to drive the minor element into the solder bump.2. The method of claim 1 , wherein the step of introducing the minor element comprises:pre-mixing the minor element into a flux; andcoating the flux over the top surface of the solder bump.3. The method of claim 1 , wherein the step of introducing the minor element comprises performing an electroless plating to form a minor element containing layer comprising the minor element on a surface of the solder bump.4. The method of claim 3 , wherein the step of performing the electroless plating comprising sequentially plating the minor element containing layer selected from the group consisting essentially of a cobalt layer claim 3 , a nickel layer claim 3 , a copper layer claim 3 , and combinations thereof.5. The method of further comprising performing an immersion to form a gold layer on the minor element containing layer.6. The method of claim 3 , wherein the minor element comprises cobalt.7. The method of claim 1 , wherein the step of introducing the minor element comprises implanting the minor element into a surface layer of the solder bump.8. The method of further comprising claim 7 , after the step of implanting the minor element and before the step of performing the re-flow process claim 7 , coating a flux on the top surface of the solder bump.9. The method of claim 7 , wherein after the step of implanting the minor element claim 7 , a bottom portion of the solder bump is ...

Pillar Bumps and Process for Making Same

Apparatus and methods for providing solder pillar bumps. Pillar bump connections are formed on input/output terminals for integrated circuits by forming a pillar of conductive material using plating of a conductive material over terminals of an integrated circuit. A base portion of the pillar bump has a greater width than an upper portion. A cross-section of the base portion of the pillar bump may make a trapezoidal, rectangular or sloping shape. Solder material may be formed on the top surface of the pillar. The resulting solder pillar bumps form fine pitch package solder connections that are more reliable than those of the prior art. 1. An apparatus , comprising:a semiconductor substrate having at least one input/output terminal on a surface thereon; a bottom portion contacting the input/output terminal;', 'an upper portion having a first width; and', 'a base portion over the bottom portion having a second width greater than the first width., 'a pillar disposed over the at least one input/output terminal comprising2. The apparatus of claim 1 , wherein the base portion has a shape claim 1 , in cross-section claim 1 , which is a trapezoidal shape.3. The apparatus of claim 1 , further comprising an under bump metallization layer underlying the pillar claim 1 , the under bump metallization layer comprising a seed layer and a barrier layer.4. The apparatus of claim 3 , wherein the seed layer comprises copper.5. The apparatus of wherein the barrier layer comprises titanium.6. The apparatus of claim 1 , wherein the pillar comprises copper.7. The apparatus of claim 1 , wherein the pillar further comprises the upper portion having vertical sides and disposed over the base portion claim 1 , the base portion having sides with non vertical portions further comprising sloping sides that extend from the bottom of the base portion and that intersect the vertical sides of the upper portion at an angle greater than 90 degrees.8. The apparatus of claim 1 , wherein the base portion ...

Thermal Compressive Bonding with Separate Die-Attach and Reflow Processes

A method of bonding includes providing a first work piece, and attaching a second work piece on the first work piece, with a solder bump disposed between the first and the second work pieces. The second work piece is heated using a heating head of a heating tool to melt the solder bump. After the step of heating the second work piece, one of the first and the second work pieces is allowed to move freely in a horizontal direction to self-align the first and the second work pieces. After the step of allowing one of the first and the second work pieces to move, a temperature of the heating head is lowed until the first solder bump solidifies to form a second solder bump. 1. An apparatus for bonding a plurality of dies , the apparatus comprising:a multi-head heating tool comprising a plurality of heating heads configured to heat the plurality of dies simultaneously to a temperature higher than a melting temperature of solder regions of the plurality of dies.2. The apparatus of claim 1 , wherein the plurality of heating heads is configured to pick up the plurality of dies through vacuuming.3. The apparatus of claim 2 , wherein the plurality of heating heads is configured to heat and to melt solder regions at a same time of the vacuuming.4. The apparatus of claim 2 , wherein the plurality of heating heads is configured to release the vacuum.5. The apparatus of claim 1 , wherein the plurality of heating heads is arranged as an array.6. The apparatus of further comprising a jig-type substrate carrier comprising a body claim 1 , wherein the body comprises a plurality of work piece holders configured to hold dies claim 1 , and wherein the plurality of heating heads is configured to be aligned to the plurality of work piece holders with a one-to-one correspondence.7. The apparatus of claim 6 , wherein the jig-type substrate carrier further comprises a cover comprising a plurality of through openings claim 6 , wherein the plurality of through openings is configured to be ...

Interface Structure for Copper-Copper Peeling Integrity

An integrated circuit device is disclosed. An exemplary integrated circuit device includes a first copper layer, a second copper layer, and an interface between the first and second copper layers. The interface includes a flat zone interface region and an intergrowth interface region, wherein the flat zone interface region is less than or equal to 50% of the interface.

System and Method for Fine Pitch PoP Structure

A fine pitch package-on-package (PoP), and a method of forming, are provided. The PoP may be formed by placing connections, e.g., solder balls, on a first substrate having a semiconductor die attached thereto. A first reflow process is performed to elongate the solder balls. Thereafter, a second substrate having another semiconductor die attached thereto is connected to the solder balls. A second reflow process is performed to form an hourglass connection.

Fine-Pitch Package-on-Package Structures and Methods for Forming the Same

A method includes laminating a Non-Conductive Film (NCF) over a first package component, and bonding a second package component on the first package component. The NCF and the second package component are on a same side of the first package component. Pillars of a mold tool are then forced into the NCF to form openings in the NCF. The connectors of the first package component are exposed through the openings. 1. A method comprising:laminating a Non-Conductive Film (NCF) over a first package component;bonding a second package component on the first package component, wherein the NCF and the second package component are on a same side of the first package component; andforcing pillars of a mold tool into the NCF to form openings in the NCF, wherein connectors of the first package component are exposed through the openings.2. The method of further comprising:placing solder balls into the openings; andreflowing the solder balls to form solder regions on the connectors.3. The method of further comprising bonding a top package to the first package component claim 1 , wherein the top package is bonded to the first package component through solder regions in the openings.4. The method of claim 1 , wherein the step of laminating the NCF over the first package component is performed before the step of bonding the second package component on the first package component.5. The method of claim 1 , wherein the step of laminating the NCF over the first package component is performed after the step of bonding the second package component on the first package component.6. The method of claim 5 , wherein the NCF is laminated over the first package component and the second package component claim 5 , and wherein the method further comprises:laminating an additional NCF film on a wafer; andsawing the wafer and the additional NCF film into a plurality of pieces, wherein one of the plurality of pieces comprises a piece of the additional NCF and the second package component, wherein after ...

Catalyst composition

The disclosure provides a catalyst composition, including: a metal or metal compound; and an organic diacid metal salt. The metal includes titanium (Ti), stibium (Sb) or combinations thereof and the metal compound includes antimony oxide (Sb 2 O 3 ) or tetra-n-butoxy titanium (TBT). The catalyst composition includes about 0.3-6 wt % of the metal or metal compound and about 94-99.7 wt % of the organic diacid metal salt.

MASTERBATCH, METHOD FOR FABRICATING THE SAME, AND A FILM FABRICATED FROM THE MASTERBATCH

The disclosure provides a masterbatch, a method for fabricating the same and a film formed from the masterbatch. The masterbatch includes a product prepared from a composition via polymerization and granulation. The composition includes: terephthalic acid; and a silicon dioxide dispersion, wherein the silicon dioxide dispersion includes surface-modified silicon dioxide particles disposed within ethylene glycol, and the surface-modified silicon dioxide particle has first functional groups and second functional groups bonded on the surface of the silicon dioxide particles, wherein the first functional groups have a structure represented by 2. The masterbatch as claimed in claim 1 , wherein the weight ratio of the first functional groups and second functional groups are 10-50 wt % claim 1 , based on the weight of the surface-modified silicon dioxide particles.3. The masterbatch as claimed in claim 1 , wherein the silicon dioxide dispersion has a solid content of 5-20 wt %.4. The masterbatch as claimed in claim 1 , wherein the masterbatch has an absolute viscosity of 0.55-0.7.5. The masterbatch as claimed in claim 1 , wherein the surface-modified silicon dioxide particle has a weight percentage of 1-50 wt % claim 1 , based on the weight of the masterbatch.6. The masterbatch as claimed in claim 1 , wherein the surface-modified silicon dioxide particle has a particle size of 1-100 nm.8. The method as claimed in claim 7 , wherein the weight ratio of the first functional groups and second functional groups are 10-50 wt % claim 7 , based on the weight of the surface-modified silicon dioxide particles.9. The method as claimed in claim 7 , wherein the silicon dioxide dispersion has a solid content of 5-20 wt %.10. The method as claimed in claim 7 , wherein the masterbatch has an absolute viscosity of 0.55-0.7.11. The method as claimed in claim 7 , wherein the surface-modified silicon dioxide particle has a weight percentage of 1-50 wt % claim 7 , based on the weight of the ...

MEMORY CIRCUIT FOR PRE-CHARGING AND WRITE DRIVING

A memory includes a word line, a bit line and a complementary bit line. A memory cell has a data node coupled to the bit line and a complementary data node coupled to the complementary bit line. The word line controls access to the memory cell. A circuit is coupled to the bit line and the complementary bit line. The circuit is configured to pull up to a high voltage, pull down to a low voltage, or float the bit line and the complementary bit line based on a first timing of pre-charging and a second timing of write driving. The first timing and the second timing are synchronized. 1. A memory , comprising:a word line;a bit line and a complementary bit line;a memory cell having a data node coupled to the bit line and a complementary data node coupled to the complementary bit line, wherein the word line controls access to the memory cell; anda circuit coupled to the bit line and the complementary bit line, wherein the circuit is configured to pull up to a high voltage, pull down to a low voltage, or float the bit line and the complementary bit line based on a first timing of pre-charging and a second timing of write driving, wherein the first timing and the second timing are synchronized by control signals and further wherein the circuit comprises a first PMOS transistor coupled between a high voltage node and the bit line, a second PMOS transistor coupled between the high voltage node and the complementary bit line, a first NMOS transistor coupled between a low voltage node and the bit line, a second NMOS transistor coupled between the low voltage node and the complementary bit line, and wherein the circuit is configured to turn on the first PMOS transistor and the second PMOS transistor for pre-charging.2. The memory of claim 1 , wherein ending of the first timing of pre-charging and starting of the second timing of write driving are performed simultaneously.3. (canceled)4. The memory of claim 14 , wherein the first PMOS transistor and the second NMOS transistor are ...

System and Method for Fine Pitch PoP Structure

A fine pitch package-on-package (PoP), and a method of forming, are provided. The PoP may be formed by placing connections, e.g., solder balls, on a first substrate having a semiconductor die attached thereto. A first reflow process is performed to elongate the solder balls. Thereafter, a second substrate having another semiconductor die attached thereto is connected to the solder balls. A second reflow process is performed to form an hourglass connection. 1. A semiconductor device comprising:a first substrate, the first substrate having a first semiconductor die coupled thereto;a second substrate, the second substrate having a second semiconductor die coupled thereto; anda plurality of electrical connections electrically coupling the first substrate to the second substrate, each of the electrical connections having a height-to-width ratio of between about 1 to about 4.2. The semiconductor device of claim 1 , wherein each of the electrical connections have a width smaller in a middle region than regions adjacent the first substrate and the second substrate.3. The semiconductor device of claim 1 , wherein each of the electrical connections has an interior core different from an exterior portion.4. The semiconductor device of claim 3 , wherein the exterior portion has a lower melting temperature than the interior core.5. The semiconductor device of claim 3 , wherein the interior core comprises a Cu core.6. The semiconductor device of claim 3 , wherein the interior core comprises a plastic core.7. The semiconductor device of claim 1 , further comprising a molding underfill positioned between the first substrate and the second substrate.8. A semiconductor device comprising:a first substrate, the first substrate having a first semiconductor die coupled thereto;a second substrate, the second substrate having a second semiconductor die coupled thereto; anda plurality of electrical connections electrically coupling the first substrate to the second substrate, each of ...

Infrared thermal emitter

An infrared thermal emitter includes a substrate, a light-emitting unit and an infrared-emitting unit. The light-emitting unit is disposed on the substrate in a laminating direction and has a light-exiting surface away from the substrate. The infrared-emitting unit is disposed on the substrate in the laminating direction to cover the light-emitting unit and includes a layered structure having a light-absorbing layer that is aligned with the light-emitting unit in the laminating direction. The light-absorbing layer absorbs light emitted from the light-emitting unit so as to be heated up and to generate infrared radiation.

System and method of timing characterization for semiconductor circuit

A method is provided. A library associated with a cell is received. A minimum setup time of the cell is acquired in response to an ideal hold time according to the library and a reference clock. A maximum hold time of the cell is acquired in response to the minimum setup time according to the library and the reference clock. A plurality of candidate hold times are determined. A plurality of candidate setup times are acquired corresponding to the plurality of candidate hold times according to the library and the reference clock. The plurality of candidate setup times are added to the plurality of candidate hold times, respectively, to obtain a plurality of candidate time windows. A target time window is selected that has a minimal time span among the candidate time windows.

Electron beam lithography methods including time division multiplex loading

An embodiment of a method of lithography includes generating a beam of electrons. A first pixel and a second pixel are each configured to pattern the beam. Using time domain multiplex loading, the first and second pixels are controlled such that the beam is patterned. The patterning includes receiving a first clock signal and using the first clock signal to generate a second clock signal and a third clock signal. The second clock signal is sent to the first pixel and sending the third clock signal is sent to the second pixel.

THERMOPLASTIC POLYESTER ELASTOMER AND METHOD FOR MANUFACTURING THE SAME

Disclosed is a thermoplastic polyester elastomer, which is formed by reacting 100 parts by weight of ester and 0.01 to 2 parts by weight of an epoxy resin with two epoxy groups, wherein the ester is formed by reacting a parts by mole of a hard-segment diol, b parts by mole of a soft-segment diol, and 1 part by mole of a diacid, wherein 1≦a≦3 and 0.005≦b≦1.5. 1. A thermoplastic polyester elastomer , being formed by:reacting 100 parts by weight of an ester and 0.01 to 2 parts by weight of an epoxy resin with two epoxy groups,wherein the ester is formed by reacting a parts by mole of a hard-segment diol, b parts by mole of a soft-segment diol, and 1 part by mole of a diacid, wherein 1≦a≦3 and 0.005≦b≦1.5.2. The thermoplastic polyester elastomer as claimed in claim 1 , wherein the diacid comprises terephthalic acid claim 1 , dialkyl terephthalate claim 1 , or a combination thereof claim 1 , the hard-segment diol comprises ethylene glycol claim 1 , butylene glycol claim 1 , or a combination thereof claim 1 , and the soft-segment diol comprises polytetramethylene glycol.3. The thermoplastic polyester elastomer as claimed in claim 1 , wherein the ester has a molecular weight of 200 to 5000.4. The thermoplastic polyester elastomer as claimed in claim 1 , wherein the epoxy resin with two epoxy groups comprises bisphenol A diglycidyl ether epoxy resin claim 1 , novolac epoxy resin claim 1 , or a combination thereof.5. The thermoplastic polyester elastomer as claimed in claim 1 , wherein the epoxy resin with two epoxy groups has a number average molecular weight of 300 to 5000.6. A method of forming a thermoplastic polyester elastomer claim 1 , comprising:(a) reacting a parts by mole of a hard-segment diol, b parts by mole of a soft-segment diol, and 1 part by mole of a diacid to form an ester, wherein 1≦a≦3 and 0.005≦b≦1.5; and(b) reacting 100 parts by weight of the ester and 0.01 to 2 parts by weight of an epoxy resin with two epoxy groups to form a thermoplastic polyester ...

Charged Particle Lithography System With a Long Shape Illumination Beam

A system includes an integrated circuit (IC) design data base having a feature, a source configured to generate a radiation beam, a pattern generator (PG) including a mirror array plate and an electrode plate disposed over the mirror array plate, wherein the electrode plate includes a lens let having a first dimension and a second dimension perpendicular to the first dimension with the first dimension larger than the second dimension so that the lens let modifies the radiation beam to form the long shaped radiation beam, and a stage configured secured the substrate. The system further includes an electric field generator connecting the minor array plate. The mirror array plate includes a mirror. The mirror absorbs or reflects the radiation beam. The radiation beam includes electron beam or ion beam. The second dimension is equal to a minimum dimension of the feature. 1. An exposure system comprising:a source configured to generate a radiation beam; anda pattern generator (PG) including a mirror array plate and an electrode plate disposed over the mirror array plate, wherein the electrode plate includes a lens let having a first dimension and a second dimension perpendicular to the first dimension with the first dimension being larger than the second dimension so that the lens let modifies the radiation beam to form a long shaped radiation beam.2. The system of claim 1 , further comprisingan integrated circuit (IC) design data base having a feature; andan electric field generator connected to the PG for controlling whether the lens let modifies the radiation beam to form the long shaped radiation beam, in response to the feature.3. The system of claim 2 , wherein the mirror array plate includes a mirror.4. The system of claim 3 , wherein the mirror reflects the radiation beam.5. The system of claim 1 , wherein the radiation beam includes an electron beam.6. The system of claim 1 , wherein the second dimension is equal to a minimum dimension of the feature.7. A ...

ANTIMICROBIAL COMPLEX SURFACE AND METHOD FOR FORMING THE SAME

Method for forming antimicrobial complex surface, being performed during processes of an anodic treatment including the following steps being worked on a workpiece: pretreatment, anodization, acid pickling, staining and pole sealing, at least comprising the following steps: providing an silver containing solution; introducing the silver solution during the processes of the anodic treatment; and providing silver particles based on the silver solution as an silver particle source, so as to form an antimicrobial complex surface on the workpiece. 1. A method to form an antimicrobial complex surface on a workpiece during an anodic treatment , and the process including the steps comprising:pretreating the workpiece;anodizing the workpiece;acid pickling the workpiece;staining the workpiece;pole sealing the workpiece;providing a silver containing solution;adding the silver containing solution during the anodic treatment; andproviding a plurality of silver particles with the silver solution as a source of silver particles so that at least an outer surface of the workpiece has the silver particles to form the antimicrobial complex surface.2. The method as recited in claim 1 , wherein in the step of adding the silver containing solution during the anodic treatment claim 1 , the silver containing solution is added into an electrolyte.3. The method as recited in claim 1 , wherein the silver containing solution is a salt solution containing silver.4. The method as recited in claim 3 , wherein the salt solution containing silver is selected from the group consisting of silver acetate claim 3 , silver chloride claim 3 , silver nitrate claim 3 , and the combination thereof.5. The method as recited in claim 2 , wherein the electrolyte is selected from the group consisting of aqueous oxalic acid solution claim 2 , aqueous phosphoric acid solution claim 2 , aqueous sulfuric acid solution claim 2 , and the combination thereof.6. The method as recited in claim 2 , wherein the anodizing ...

Connection interface conversion chip, connection interface conversion device and operation method

A connection interface conversion chip, a connection interface conversion device and an operation method are provided. The connection interface conversion chip includes a USB interface circuit, a DP interface circuit, a USB core circuit and a switching circuit. The USB interface circuit is suitable for coupling to a USB connector. The DP interface circuit is coupled to a DP sink device through a DP connector. The USB core circuit is coupled to both the USB interface circuit and the DP interface circuit. The switching circuit is coupled to both the USB interface circuit and the DP interface circuit. The switching circuit supports only one specific conduction mode that only allows transmitting DP signals between the USB interface circuit and the DP interface circuit.

AQUEOUS-PHASE CATALYST COMPOSITIONS AND METHOD FOR PREPARING POLYPHENYLENE ETHER

An aqueous-phase catalyst composition including a metal ion including copper, nickel, manganese or iron and a water-soluble linear polymer having a molecular weight ranging from 1,000 to 20,000 is provided. The metal ion and the water-soluble linear polymer have a weight ratio of 1:1 to 1:5. A method for preparing polyphenylene ether including providing the disclosed aqueous-phase catalyst composition and adding phenolic monomers to the aqueous-phase catalyst composition to proceed to a polymerization reaction to prepare polyphenylene ether is also provided. 1. An aqueous-phase catalyst composition , comprising:a metal ion comprising copper, nickel, manganese or iron; anda water-soluble linear polymer having a molecular weight ranging from 1,000 to 20,000, wherein the metal ion and the water-soluble linear polymer have a weight ratio of 1:1 to 1:5.2. The aqueous-phase catalyst composition as claimed in claim 1 , wherein the water-soluble linear polymer comprises polyethylene glycol (PEG) claim 1 , polyvinyl alcohol (PVA) or polyitaconic acid (PIA).3. The aqueous-phase catalyst composition as claimed in claim 1 , wherein the water-soluble linear polymer comprises poly(itaconic acid-co-acrylamide) claim 1 , poly(Ita-HEAMOBA-co-acrylic acid) or poly(Ita-HEAMOBA-co-acrylamide).4. The aqueous-phase catalyst composition as claimed in claim 1 , wherein the water-soluble linear polymer is represented by the following structural formula:{'br': None, 'sub': x', 'y, '\ue8a0A\ue8a0\ue8a0B\ue8a0'}wherein A comprises at least one carboxyl group or amide group, II comprises at least one of at least one carboxyl group and carboxyl group and amide group, x ranges from 1 to 100, and y ranges from 1 to 100.5. The aqueous-phase catalyst composition as claimed in claim 4 , wherein the water-soluble linear polymer has a molecular weight ranging from 4 claim 4 ,000 to 8 claim 4 ,500.6. The aqueous-phase catalyst composition as claimed in claim 4 , wherein the water-soluble linear polymer ...

CLOCK REGENERATOR

A clock regenerator includes a pulse generating module, a control logic module, a gating module and an output module. The pulse generating module is configured to receive a global clock signal and produce a periodic pulse signal triggered by a rising edge of the global clock signal. The control logic module is configured to receive a plurality of control signals and produce a pulse-type setting signal and a gating signal according to the periodic pulse signal and the control signals. The gating module is configured to produce an intermediate clock signal according to the pulse-type setting signal and the gating signal. The output module is configured to provide a local clock signal according to the intermediate clock signal. 1. A clock regenerator , comprising:a pulse generating module, configured to receive a global clock signal and produce a periodic pulse signal triggered by a rising edge of the global clock signal;a control logic module, configured to receive a plurality of control signals and produce a pulse-type setting signal and a gating signal according to the periodic pulse signal and the control signals;a gating module, configured to produce an intermediate clock signal according to the pulse-type setting signal and the gating signal; andan output module, configured to provide a local clock signal according to the intermediate clock signal.2. The clock regenerator of claim 1 , wherein each of the pulse generating module claim 1 , the control logic module claim 1 , the gating module and the output module substantially induces one unit of delay time in sequence claim 1 , the local clock signal is launched by four units of delay time after the rising edge of the global clock signal.3. The clock regenerator of claim 2 , wherein the control signals are required by one unit of delay time after the rising edge of the global clock signal.4. The clock regenerator of claim 1 , wherein the gating module produces the intermediate clock signal in pulse-type according ...

SYSTEM FOR TREATING WASTEWATER CONTAINING BORON AND IODINE

A system for treating wastewater containing boron and iodine is provided. The system comprises a membrane filter, an electrodeionization filter and a resin adsorption column. The membrane filter is provided for removing iodine from the wastewater. The electrodeionization filter is connected to the membrane filter via lines for removing boron from the wastewater. The resin adsorption column is connected to the electrodeionization filter via lines for removing the residual boron from the wastewater. The boron and iodine can be removed efficiently to meet the wastewater discharging standard by using the system for treating wastewater containing boron and iodine. 1. A system for treating wastewater containing boron and iodine comprising:a membrane filter for removing iodine from the wastewater;an electrodeionization filter connected to the membrane filter via lines for removing boron from the wastewater; anda resin adsorption column connected to the electrodeionization filter via lines for removing the residual boron from the wastewater.2. The system for treating wastewater containing boron and iodine according to further comprising a mixing reaction tank connected to the electrodeionization filter and the resin adsorption column respectively via lines.3. The system for treating wastewater containing boron and iodine according to further comprising a sludge press connected to the mixing reaction tank via lines.4. The system for treating wastewater containing boron and iodine according to claim 1 , wherein the membrane filter is a reverse osmosis membrane filter.5. The system for treating wastewater containing boron and iodine according to claim 1 , wherein the electrodeionization filter is a continuous electrodeionization filter.6. The system for treating wastewater containing boron and iodine according to claim 1 , wherein the resin adsorption column is a chelating resin adsorption column.7. The system for treating wastewater containing boron and iodine according to ...

Electron beam lithography systems and methods including time division multiplex loading

The present disclosure provides a systems and methods for e-beam lithography. One system includes an electron source operable to produce a beam and an array of pixels operable to pattern the beam. Control circuitry is spaced a distance from and coupled to the array of pixels. The control circuitry uses time domain multiplex loading (TMDL) to control the array of pixels.

ANTIMICROBIAL COMPLEX SURFACE AND METHOD OF FABRICATING THE SAME

An antimicrobial metal complex surface and a method of fabricating the same, and the method includes providing an article, and the article has a first metal complex surface treated by anodization. The first metal complex surface is formed with a first pore. Secondly a silver suspension is provided. The silver suspension also has pore sealing agent. The article is soaked in the suspension to form a pore sealing layer having silver particles on the first metal complex surface such that the silver particles are distributed in the pore sealing layer. The antimicrobial metal complex surface fabricated by the method inhibits microorganism growth on the anodized metal surface. 1. A method of fabricating antimicrobial complex surface comprising:providing an article, the article having a first metal complex surface treated by anodization, the first metal complex surface formed with a first pore; andproviding a suspension having silver and pore sealing agent, the article soaked in the suspension to form a pore sealing layer having silver particles on the first metal complex surface such that the silver particles are distributed in the pore sealing layer.2. The method of fabricating antimicrobial complex surface according to claim 1 , wherein the suspension having silver further includes an anionic surfactant claim 1 , the anionic surfactant has a first percentage by weight in the silver suspension claim 1 , and the first percentage by weight ranges between 0 to 8%.3. The method of fabricating antimicrobial complex surface according to claim 2 , wherein the anionic surfactant is sodium dodecylbenzene sulfonate or sodium dodecyl sulfate.4. The method of fabricating antimicrobial complex surface according to claim 1 , wherein the pore sealing agent is a nickel acetate pore sealing agent claim 1 , such that the pore sealing layer is formed with a pore sealing nickel layer claim 1 , the silver particles are distributed in the pore sealing nickel layer.5. The method of fabricating ...

POLYESTER FILMS AND METHODS FOR MANUFACTURING THE SAME

A polyester film is provided. The polyester film is produced from a composition that includes the following monomers: terephthalic acid, ethylene glycol, and a branched monomer having a structure represented by formula (I), formula (II) or formula (III): 2. The polyester film as claimed in claim 1 , wherein the molar percentage of the branched monomer is between 1 mol % to 3 mol % claim 1 , based on the total mole of the terephthalic acid monomer and the ethylene glycol monomer.3. The polyester film as claimed in claim 1 , wherein the polyester film has an acid value equal to or less than 33 eq/106 g.4. The polyester film as claimed in claim 1 , wherein the polyester film has an acid value between 5 eq/10g and 33 eq/10g.5. The polyester film as claimed in claim 1 , wherein the polyester film has an acid value between 10 eq/10g and 25 eq/10g.6. The polyester film as claimed in claim 1 , wherein the polyester film has a polyester oligomer weight percentage not more than 1.2 wt % claim 1 , based on the weight of the polyester film.7. The polyester film as claimed in claim 1 , wherein the polyester film has a polyester oligomer weight percentage between 0.6 wt % and 1.2 wt % claim 1 , based on the weight of the polyester film.8. The polyester film as claimed in claim 1 , wherein the polyester film has a glass transition temperature (Tg) between 77° C. and 100° C.9. The polyester film as claimed in claim 1 , wherein the polyester film has a glass transition temperature (Tg) between 77° C. and 90° C.10. The polyester film as claimed in claim 1 , wherein the polyester film has a water-resistance time longer than 40 hrs.11. The polyester film as claimed in claim 1 , wherein the polyester film has a water-resistance time longer than 69 hrs.13. The method for preparing a polyester film as claimed in claim 12 , wherein the molar percentage of the branched monomer is between 1.5 mol % to 3 mol % claim 12 , based on the total mole of the terephthalic acid monomer and the ...

RESIN COMPOSITION, PREPREG, AND SUBSTRATE EMPLOYING THE SAME

A disclosure provides a resin composition, a prepreg, and a substrate employing the same. According to an embodiment of the disclosure, the resin composition includes a polyphenylene ether compound, and a bismaleimide. The prepreg includes a cured product of the resin composition. The substrate includes a product fabricated by the resin composition or the prepreg. 2. The resin composition as claimed in claim 1 , further comprising a polybutadiene.3. The resin composition as claimed in claim 2 , wherein the polybutadiene has a repeat unit with a terminal reactive functional group claim 2 , wherein the terminal reactive functional group is carboxyl group claim 2 , acryloyl group claim 2 , vinyl group claim 2 , allyl group claim 2 , or styryl group.5. The resin composition as claimed in claim 1 , wherein the polybutadiene has a weight percentage of between 1-94 wt % claim 1 , the polyphenylene ether compound has a weight percentage of between 5 and 98 wt % claim 1 , and the bismaleimide compound has a weight percentage of between 1 and 30 wt % claim 1 , based on the total weight of the polybutadiene claim 1 , the polyphenylene ether compound claim 1 , and the bismaleimide compound.7. The resin composition as claimed in claim 1 , further comprising:a triallyl isocyanurate, wherein the ratio between the weight of the triallyl isocyanurate and the total weight of the polybutadiene, the polyphenylene ether compound, and the bismaleimide compound is between 0.01-0.25.8. The resin composition as claimed in claim 1 , further comprising:{'sub': 3', '2', '3', '2', '2', '2, 'an inorganic powder, wherein the inorganic powder is Al(OH), AlO, Mg(OH), MnO, SiO, or polyimide.'}9. The resin composition as claimed in claim 1 , wherein the at least two different phenols respectively have at least one functional group claim 1 , wherein the functional group is methyl group claim 1 , or allyl group.10. The resin composition as claimed in claim 1 , wherein Y is a moiety prepared by ...

POLYPHENYLENE ETHER OLIGOMER AND ARTICLE EMPLOYING THE SAME

A polyphenylene ether oligomer is provided. The polyphenylene ether oligomer has the following formula (I): 2. The polyphenylene ether oligomer as claimed in claim 1 , wherein each of the at least two different phenol-based compounds independently has a substituted group claim 1 , and the substituted group is a methyl group or an allyl group independently.3. The polyphenylene ether oligomer as claimed in claim 1 , wherein Y is a moiety polymerized by 2 claim 1 ,6-dimethylphenol and 2-allyl-6-methylphenol.5. The polyphenylene ether oligomer as claimed in claim 1 , wherein Z is H claim 1 , epoxypropyl group claim 1 , vinylbenzyl group claim 1 , or methylacryloyl group.6. The polyphenylene ether oligomer as claimed in claim 1 , wherein a number-average molecular weight of the polyphenylene ether oligomer is larger than 600.7. The polyphenylene ether oligomer as claimed in claim 1 , wherein a number-average molecular weight of the polyphenylene ether oligomer is in a range from 1200 to 12000.10. An article claim 1 , which comprises the polyphenylene ether oligomer as claimed in .11. The article as claimed in claim 10 , wherein the article is a high frequency substrate claim 10 , high temperature additive claim 10 , coating material claim 10 , or adhesive. The present application is based on, and claims priorities from, Taiwan Application Serial Number 102115366, filed on Apr. 30, 2013, and Taiwan Application Serial Number 102144177, filed on Dec. 3, 2013 the disclosure of which is hereby incorporated by reference herein in its entirety.The technical field relates to polyphenylene ether oligomers.Communication electronic industry has grown rapidly, and development of polymer with high thermal resistance, low dielectric coefficient, and high toughness is desired such that these materials can be used in next-generation electronic packages or high frequency substrates. Polyphenylene ether (PPE), also called polyphenylene oxide (PPO), is a high performance material. However, ...

METHOD OF MAKING A CONDUCTIVE PILLAR BUMP WITH NON-METAL SIDEWALL PROTECTION STRUCTURE

A method of making a semiconductor device includes forming an under bump metallurgy (UBM) layer over a substrate, the UBM layer comprising sidewalls and a surface region. The method further includes forming a conductive pillar over the UBM layer, the conductive pillar includes sidewalls, wherein the conductive pillar exposes the surface region of the UBM layer. The method further includes forming a non-metal protective structure over the sidewalls of the conductive pillar, wherein the non-metal protective structure contacts the surface region of the UBM layer, and the non-metal protective structure exposes the sidewalls of the UBM layer. 1. A method of making a semiconductor device , the method comprising:forming an under bump metallurgy (UBM) layer over a substrate, the UBM layer comprising sidewalls and a surface region;forming a conductive pillar over the UBM layer, the conductive pillar comprising sidewalls, wherein the conductive pillar exposes the surface region of the UBM layer; andforming a non-metal protective structure over the sidewalls of the conductive pillar, wherein the non-metal protective structure contacts the surface region of the UBM layer, and the non-metal protective structure exposes the sidewalls of the UBM layer.2. The method of claim 1 , further comprising forming a plurality of cap layers over a top surface of the conductive pillar.3. The method of claim 2 , further comprising forming a solder layer formed on the plurality of cap layers claim 2 , wherein the protection structure covers at least a portion of a sidewall surface of the plurality of cap layers and a sidewall surface of the solder layer.4. The method of claim 2 , wherein forming the plurality of cap layers comprises forming a first metal film and forming a second metal film claim 2 , and the first metal film and the second metal film independently comprise Ni claim 2 , Au claim 2 , Pd claim 2 , or alloys thereof.5. The method of claim 1 , further comprising forming a barrier ...

Pillar Bumps and Process for Making Same

Apparatus and methods for providing solder pillar bumps. Pillar bump connections are formed on input/output terminals for integrated circuits by forming a pillar of conductive material using plating of a conductive material over terminals of an integrated circuit. A base portion of the pillar bump has a greater width than an upper portion. A cross-section of the base portion of the pillar bump may make a trapezoidal, rectangular, or sloping shape. Solder material may be formed on the top surface of the pillar. The resulting solder pillar bumps form fine pitch package solder connections that are more reliable than those of the prior art. 1. A method comprising:forming input/output terminals for external connectors on one surface of a semiconductor substrate;depositing a passivation layer over the input/output terminals;patterning the passivation layer to form openings exposing a portion of the input/output terminals;depositing a seed layer over the passivation layer;depositing a photoresist layer over the seed layer;developing the photoresist layer to form photoresist openings in the photoresist layer over the input/output terminals;patterning a bottom portion of the photoresist openings to form bird's beak patterns at a bottom of the openings, the bird's beak patterns extending outwardly from the openings; andforming a conductive material in the photoresist openings;wherein the conductive material forms a pillar extending upwardly from the seed layer having an upper portion with a first width and a base portion with a second width that is greater than the first width.2. The method of claim 1 , wherein forming the conductive material comprises electroplating a conductive material using a low initial deposition rate to fill the bird's beak openings with the conductive material.3. The method of claim 2 , wherein the low initial deposition rate comprises a rate between 0.1 and 0.5 amperes per decimeter squared.4. The method of claim 1 , wherein patterning the bottom ...

SCAN CELL ASSIGNMENT

One or more systems and methods for scan cell assignment for a design layout of a semiconductor arrangement are provided. The design layout is evaluated to identify a set of sequential cells, such as flip flops connected to circuitry by data paths. Sequential cells within the set of sequential cells are assigned to either a scan cell assignment or a non-scan cell assignment based upon a control path criterion, a register bank criterion, a pipeline depth criterion, a sequential loop criterion, or other criteria to create a cell assignment list. Scan paths are connected to sequential cells assigned to the scan cell assignment so that test patterns can be sent to and received from such sequential cells during testing of the semiconductor arrangement for defects. Power, performance, and area utilization are improved because at least some sequential cells are assigned to the non-scan cell assignment. 1. A method for scan cell assignment for a design layout , comprising:evaluating a design layout for a semiconductor arrangement to identify a set of sequential cells associated with the semiconductor arrangement;assigning control signal sequential cells within the set of sequential cells to a scan cell assignment based upon a control path criterion to generate an initial cell assignment list; andassigning unassigned sequential cells within the set of sequential cells to either the scan cell assignment or a non-scan cell assignment based upon at least one of a register bank criterion, a pipeline depth criterion, or a sequential loop criterion to update the initial cell assignment list to create a cell assignment list.2. The method of claim 1 , the assigning unassigned sequential cells comprising:identifying a register bank comprising a sequential cell grouping of the set of sequential cells; andresponsive to identifying at least one sequential cell within the sequential cell grouping as being a non-scan cell assignment candidate, assigning unassigned sequential cells within ...

POLYESTER COMPOSITION, AND POLYESTER ARTICLE PREPARED THEREFROM

The disclosure provides a polyester composition and a polyester article. According to an embodiment, the polyester composition includes a polyester and a branched monomer. The branched monomer has a structure represented by formula (I) or formula (H): 2. The polyester composition as claimed in claim 1 , wherein the polyester comprises a thermoplastic polyester.3. The polyester composition as claimed in claim 2 , wherein the thermoplastic polyester comprises a polyethylene terephthalate claim 2 , a polyethylene naphthalate claim 2 , or polybutylene terephthalate.4. The polyester composition as claimed in claim 1 , wherein the polyester composition comprises 80-99.9 parts by weight of polyester claim 1 , and 0.1-20 parts by weight of branched monomer claim 1 , wherein a sum of the weight of the polyester and the branched monomer is equal to 100 parts by weight.5. A polyester article claim 1 , comprising:{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'a product made by polymerizing the composition as claimed in .'}6. The polyester article as claimed in claim 5 , wherein the polyester article has an acid number of between 5 eq/10g and 20 eq/10g.7. The polyester article as claimed in claim 5 , wherein the polyester article has an inherent viscosity of between 0.1 ln ηr/C and 0.9 ln ηr/C.8. The polyester article as claimed in claim 5 , wherein the polyester article is a film claim 5 , and the hydrolysis resistance of the film is more than 40 hours. The present application is based on, and claims priority from, Taiwan Application Serial Number 102122475, filed on Jun. 25, 2013, the disclosure of which is hereby incorporated by reference herein in its entirety.The technical field relates to a polyester composition and an article prepared therefrom.Polyester films can be used in a variety of applications. In order to be suitable for various applications, the polyester materials should have corresponding functional requirements. For example, an upper layer and a lower ...

Method for cell placement in semiconductor layout and system thereof

According to an embodiment, a method for cell placement in a semiconductor layout is provided. The method includes: providing a first cell having two sides, each side configured as at least one of a source side and a drain side; providing a place-and-route boundary (prBoundary) of the first cell based on the configuration of the two sides of the first cell; providing a second cell having two sides, each side configured as at least one of a source side and a drain side; providing a prBoundary of the second cell based on the configuration of the two sides of the second cell; and placing the first cell and the second cell based on the prBoundary of the first cell and the prBoundary of the second cell.

Integrated circuit with well and substrate contacts

An integrated circuit comprises standard cells arranged in rows and columns. The integrated circuit also comprises tap cells arranged in rows and columns. The tap cells each comprise a substrate having a first dopant type and a thickness from a first surface of the substrate to a second surface of the substrate. The integrated circuit further comprises a well region in the substrate having a second dopant type different from the first dopant type and a depth from the first surface of the substrate less than the thickness of the substrate. The integrated circuit additionally comprises a first quantity of rows of tap cells and a second quantity of rows of tap cells less than the first quantity. Each row of the first quantity of rows of tap cells comprises at least one well contact, and each row of tap cells of the second quantity of tap cells comprises at least one substrate contact.

Method of fabricating antimicrobial complex surface

A method of fabricating an antimicrobial metal complex surface, and the method includes providing an article, and the article has a first metal complex surface treated by anodization. The first metal complex surface is formed with a first pore. Secondly a silver suspension is provided. The silver suspension also has pore sealing agent. The article is soaked in the suspension to form a pore sealing layer having silver particles on the first metal complex surface such that the silver particles are distributed in the pore sealing layer. The antimicrobial metal complex surface fabricated by the method inhibits microorganism growth on the anodized metal surface.

System and method of timing characterization for semiconductor circuit

A method includes: receiving a library associated with a cell; determining a plurality of candidate hold times for the cell; acquiring a plurality of candidate setup times corresponding to the plurality of candidate hold times, wherein a data delay associated with each of the candidate setup time fulfills a data delay constraint for the cell; adding the plurality of candidate setup times to the plurality of candidate hold times, respectively, to obtain a plurality of candidate time windows; and selecting a target time window having a minimal time span among the candidate time windows. At least one of the receiving, determining, acquiring, adding and selecting steps is conducted by at least one processor.

Display device and display system thereof

A display device (1) includes a RFID tag unit (11), a display unit (13), a processing unit (12) and a power supply unit (14). The RFID tag unit follows a wireless communication standard of a RFID system to receive a wireless signal and outputs identification information. The processing unit electrically connected with the RFID tag unit and the display unit receives the identification information and outputs to the display unit for displaying. The power supply unit supplies operation power required to the processing unit and the display unit. The required power while the above-mentioned display device refreshes the information is supplied by the power supply unit, so that the information can be refreshed with longer communication distance and power saving is achieved. A display system including the above-mentioned display device and a reader/writer device (2) is also disclosed.

Resin composition, prepreg, and substrate employing the same

Electrical stapler

An electrical stapler wherein when papers to be stapled are inserted into a stapling groove, a fine switch is touched to activate a motor for driving a gear set, the gear set being provided with two biasing rods which can bias a Y-shaped linkage of a stapling mechanism, a fixing rod being pivotably connected with front end of the Y-shaped linkage, two ends of the fixing rod being respectively connected to two springs, a pressing plate being disposed on the fixing rod whereby when operated, the pressing plate is bounded by the springs to strike out a staple from a staple magazine, a controlling circuit being used to control the stapling operation for saving labor and enhancing working efficiency.

High-speed sense amplifier with auto-shutdown precharge path

A sense amplifier inverts the output from the pass transistor to control a pre-charge transistor. The combination of the inverter and pre-charge transistor pre-charges the output to a level just below the flip level of the following data latch circuit. If the data cell read is a low threshold cell (conductive or “1”), the output level does not significantly change, and the data is rapidly latched and read. If the data cell is a high threshold cell (non-conductive or “0”), the pass transistor shuts off and the output is pulled up above the flip level of the data latch circuit through a pull-up path. The pre-charge level is near the flip level, so the output does not have to be pulled up very far, thus reading a “0” is also fast. In one embodiment, the pull-up transistor is a p-channel MOSFET with the gate grounded, thus providing more constant current than a diode-connected configuration. In another embodiment, the pull-up transistor is operated as a current mirror using a cell in a mini array. The first inverter of the data latch circuit can be used in the feedback path to the precharge transistor, or a separate feedback inverter can be provided.

Method of making a conductive pillar bump with non-metal sidewall protection structure

A method of making a semiconductor device includes forming an under bump metallurgy (UBM) layer over a substrate, the UBM layer comprising sidewalls and a surface region. The method further includes forming a conductive pillar over the UBM layer, the conductive pillar includes sidewalls, wherein the conductive pillar exposes the surface region of the UBM layer. The method further includes forming a non-metal protective structure over the sidewalls of the conductive pillar, wherein the non-metal protective structure contacts the surface region of the UBM layer, and the non-metal protective structure exposes the sidewalls of the UBM layer.

Integrated circuit devices and packaging assembly

Method for forming multiple spacer widths

A method of forming pluralities of gate sidewall spacers each plurality comprising different associated gate sidewall spacer widths including providing a plurality of gate structures formed overlying a substrate and a plurality of dielectric layers formed substantially conformally overlying the gate structures; exposing a first selected portion of the plurality followed by anisotropically etching through a thickness portion comprising at least the uppermost dielectric layer to form a first sidewall spacer width; exposing a first subsequent selected portion of the plurality followed by etching through at least a thickness portion of the uppermost dielectric layer; and, exposing a second subsequent selected portion of the plurality followed by anisotropically etching through at least a thickness portion of the uppermost dielectric layer to form a subsequent sidewall spacer width.

Surface treatment of metal interconnect lines

Apparatus for forming a semiconductor structure comprising a first layer on top of a substrate wherein the first layer defines conductive regions such as copper interconnect lines and non-conductive regions such as dielectric materials. The conductive regions are covered by a second layer of a material different than the first layer such as for example nickel and then the structure is heat treated such that the interconnect lines and second metal, such as a copper interconnect line and a nickel second layer, interact with each other to form an alloy layer. The alloy layer has superior qualities for adhering to both the copper interconnect lines and a subsequently deposited dielectric material.

Power supply circuit for pci-e slot

Surface treatment of metal interconnect lines

Apparatus for forming a semiconductor structure comprising a first layer on top of a substrate wherein the first layer defines conductive regions such as copper interconnect lines and non-conductive regions such as dielectric materials. The conductive regions are covered by a second layer of a material different than the first layer such as for example nickel and then the structure is heat treated such that the interconnect lines and second metal, such as a copper interconnect line and a nickel second layer, interact with each other to form an alloy layer. The alloy layer has superior qualities for adhering to both the copper interconnect lines and a subsequently deposited dielectric material.

Power supply circuit for PCI-E slot

Display device and display system thereof

A display device includes a RFID tag unit, a display unit, a processing unit and a power supply unit. The RFID tag unit follows a wireless communication standard of a RFID system to receive a wireless signal and outputs identification information. The processing unit electrically connected with the RFID tag unit and the display unit receives the identification information and outputs to the display unit for displaying. The power supply unit supplies operation power required to the processing unit and the display unit. The required power while the above-mentioned display device refreshes the information is supplied by the power supply unit, so that the information can be refreshed with longer communication distance and power saving is achieved. A display system including the above-mentioned display device and a reader/writer device is also disclosed.

Detecting system and method

A detecting system and method is applied in an intellectual information device comprising a read only memory and a flash access memory. The intellectual information device is connected to a server and is used for downloading development programs from sever into the flash access memory, executing the development programs and performing detection. The process of detecting a newly developed product comprises the steps. The development programs are downloaded from server and stored in flash access memory. If a user chooses to execute the development programs in flash access memory to enable the intellectual information device perform a booting-up operation, the intellectual information device will execute the development programs in flash access memory rather than the original software programs in read only memory. If the flash access memory does not comprise the development programs, the intellectual information device will execute the original software programs in read only memory.

Percussion-insertion machines

Polyester composition, and polyester article prepared therefrom

The disclosure provides a polyester composition and a polyester article. According to an embodiment, the polyester composition includes a polyester and a branched monomer. The branched monomer has a structure represented by formula (I) or formula (II): wherein R is independently hydrogen, fluorine, chlorine, bromine, or C 1-6 alkyl.

Preventing UBM Oxidation in Bump Formation Processes

A method of forming an integrated circuit structure includes forming a copper-containing seed layer on a wafer, and performing a descum step on an exposed surface of the copper-containing seed layer. The descum step is performed using a process gas including fluorine and oxygen. A reduction/purge step is then performed on the exposed surface of the copper-containing seed layer using a nitrogen-containing gas. A copper-containing layer is plated on the copper-containing seed layer.

Method for multiple spacer width control

A method of forming pluralities of gate sidewall spacers each plurality comprising different associated gate sidewall spacer widths including providing a first plurality of gate structures; blanket depositing a first dielectric layer over the first plurality of gate structures; blanket depositing a second dielectric layer over the first dielectric layer; etching back through a thickness of the first and second dielectric layers; blanket depositing a first photoresist layer to cover the first plurality and patterning to selectively expose at least a second plurality of gate structures; isotropically etching the at least a second plurality of gate structures for a predetermined time period to selectively etch away a predetermined portion of the first dielectric layer; and, selectively etching away the second dielectric layer to leave gate structures comprising a plurality of associated sidewall spacer widths.

In-situ pad and wafer cleaning during chemical mechanical polishing

A method for in-situ cleaning a polishing pad and a wafer surface simultaneously during copper chemical mechanical polishing and an apparatus for carrying out such method are disclosed. The method is carried out by dispensing an acid-containing solution onto a top surface of a polishing pad while the wafer is rotated against the polishing pad without any slurry solution being dispensed. The acid-containing solution may be advantageously formed by diluting an acid such as citric acid, HCOOH, CH 3 COOH, HNO 3 , H 2 SO 4 and HF to a concentration of less than 10 wt. % acid, preferably less than 5 wt. % acid, and more preferably less than 1 wt. % acid. The acid-containing solution may be dispensed onto a top surface of the polishing pad for a time period between about 30 sec. and about 300 sec.

Selective spacer layer deposition method for forming spacers with different widths

A method of forming spacers with different widths on a semiconductor substrate, includes the steps of disposing a first spacer layer over the substrate, defining the first spacer layer into a plurality of spacers of a first width, and disposing a second spacer layer selectively over the first spacer layer of a number of the spacers preselected for the second spacer layer, the predetermined number of the spacers with the second spacer layer each having a second width which is different from the first width.

Method for forming multiple spacer widths

A method of forming pluralities of gate sidewall spacers each plurality comprising different associated gate sidewall spacer widths including providing a plurality of gate structures formed overlying a substrate and a plurality of dielectric layers formed substantially conformally overlying the gate structures; exposing a first selected portion of the plurality followed by anisotropically etching through a thickness portion comprising at least the uppermost dielectric layer to form a first sidewall spacer width; exposing a first subsequent selected portion of the plurality followed by etching through at least a thickness portion of the uppermost dielectric layer; and, exposing a second subsequent selected portion of the plurality followed by anisotropically etching through at least a thickness portion of the uppermost dielectric layer to form a subsequent sidewall spacer width.

觸媒組合物

本發明提供一種觸媒組合物，包括：一金屬或金屬化合物；以及一有機雙酸金屬鹽(organic diacid metal salt)。

半導體元件及其形成方法

本發明之實施例提供細微間距的層疊封裝及其形成方法，此層疊封裝可藉由在具有半導體晶粒附著於其上的第一基底上放置連接器例如焊球，進行第一回焊製程將焊球拉長，之後將具有另一半導體晶粒附著於其上的第二基底連接至焊球，進行第二回焊製程，形成沙漏形狀的連接器。

半導體元件及其形成方法

Bonding methods

Method for manufacturing multiple spacer widths of semiconductor device

Connection interface conversion chip, connection interface conversion device and operation method

A connection interface conversion chip, a connection interface conversion device and an operation method are provided. The connection interface conversion chip includes a USB interface circuit, a DP interface circuit, a USB core circuit and a switching circuit. The USB interface circuit is suitable for coupling to a USB connector. The DP interface circuit is coupled to a DP sink device through a DP connector. The USB core circuit is coupled to both the USB interface circuit and the DP interface circuit. The switching circuit is coupled to both the USB interface circuit and the DP interface circuit. The switching circuit supports only one specific conduction mode that only allows transmitting DP signals between the USB interface circuit and the DP interface circuit.

Connection interface conversion chip, connection interface conversion device and operation method

A connection interface conversion chip, a connection interface conversion device and an operation method are provided. The connection interface conversion chip includes a USB interface circuit, a DP interface circuit, a USB core circuit and a switching circuit. The USB interface circuit is suitable for coupling to a USB connector. The DP interface circuit is suitable for coupling to a DP connector. In a first operation mode, at least one USB signal pair received by the USB connector is transmitted to the USB core circuit through the USB interface circuit. The USB core circuit decodes the USB signal pair and generates DP data. The DP data is transmitted to the DP connector by the DP interface circuit. In a second operation mode, the DP data received by the USB connector is transmitted to the DP connector through the USB interface circuit, the switching circuit and the DP interface circuit.

樹脂母粒及其製造方法、以及由其所形成的膜層

本發明揭露一種樹脂母粒及其製造方法，以及由該樹脂母粒所製備出之膜層。該樹脂母粒係為一組合物經聚合及熱熔造粒後所得產物，其中該組合物包含：對苯二甲酸；以及一二氧化矽分散液，其中該二氧化矽分散液包含一表面改質二氧化矽粒子分散於乙二醇中，其中該表面改質二氧化矽粒子係為具有第一官能基及第二官能基鍵結於表面之二氧化矽粒子，其中該第一官能基係□，而該第二官能基係C1-8之鹵烷基、C1-8之烷氧基、C1-8之烷氨基(aminoalkyl)、C2-8之烷烯基、或環氧基，其中R1係為氫、或C1-3之烷基，n係為1-4。

Interface structure for copper-copper peeling integrity

An integrated circuit device is disclosed. An exemplary integrated circuit device includes a first copper layer, a second copper layer, and an interface between the first and second copper layers. The interface includes a flat zone interface region and an intergrowth interface region, wherein the flat zone interface region is less than or equal to 50% of the interface.

Package structure of a stack-type light-sensing element and package method thereof

The present invention discloses a package structure of a stack-type light-sensing element and a package method thereof, wherein firstly, a substrate is provided; next, a signal-processing IC chip and a light-sensing chip are sequentially stacked above the substrate in bottom-up sequence; next, lead lines are used to electrically connect the substrate with the signal-processing IC chip and the light-sensing chip in order to form a unitary light-sensing element. The present invention has the advantages that light-sensor signals are directly processed and then output to a display device, and that the volume of a light-sensing element can be reduced to such an extent that it can be easily applied to miniature electronic products. In contrast with the conventional light-sensing element needing massive volume of electronic circuits to process signal and also needing minute and complicated assemblage, the present invention has superior novelty and futurity.

Doping minor elements into metal bumps

Integrated circuit device and method of forming the same

積體電路裝置及其形成方法

Picking system

A picking system comprises a radio frequency identification (RFID) tag, a case, a two-wire conductive strip, at least one identifying unit and a processing unit. The two-wire conductive strip is electrically connected between the identifying unit and the processing unit. The identifying unit reads tag information within the RFID tag for actively and instantly controlling the authorization of an operating staff assigned for particular items thereby improving the accuracy of picking items.

Biomedical detection photoelectric module and manufacturing method thereof

The invention provides a biomedical detection photoelectric module, which includes a circuit substrate, a plurality of isolating barriers, a light-emitting unit, a photosensitive unit, and a light-guiding assembly. The light-guiding assembly provides a first optical element and a second optical element, respectively, corresponding to a light-emitting unit and a light-sensing unit. The first optical element has a first pattern layer to alter the emitting angle of the first light generated by the light-emitting unit. The second optical element has a second pattern layer to alter the incident angle of a second optical element entering the light-sensing unit. The first light is guided by the first optical element so that the energy of the first light is concentrated and incident on a predetermined area of a human's skin layer. The second light in the predetermined area is guided by the second optical element to enter the light-sensing unit. The present invention further provides a process method for the biomedical detection photoelectric module.

Method for manufacturing semiconductor structure

Picking system

A picking system comprises a radio frequency identification (RFID) tag, a case, a two-wire conductive strip, at least one identifying unit and a processing unit. The two-wire conductive strip is electrically connected between the identifying unit and the processing unit. The identifying unit reads tag information within the RFID tag for actively and instantly controlling the authorization of an operating staff assigned for particular items thereby improving the accuracy of picking items.

Display apparatus

A display apparatus including a circuit board, a plurality of light-emitting devices and a display panel is provided. The light-emitting devices are disposed on the circuit board and electrically connected to the circuit board. The display panel is disposed on the light-emitting devices. The display panel includes a peripheral light-shielding pattern. An opening portion of the peripheral light-shielding pattern defines an active area of the display panel. A physical portion of the peripheral light-shielding pattern defines a non-active area of the display panel. An optical axis of a light-emitting surface of at least one of the light-emitting devices is located at a junction of the active area and the non-active area, at the non-active area, or at the active area and a side wall of the at least one of the light-emitting devices is located at the junction of the active area and the non-active area.

Method of forming integrated circuit structures

Doping Minor Elements into Metal Bumps

A method of forming a device includes providing a substrate, and forming a solder bump over the substrate. A minor element is introduced to a region adjacent a top surface of the solder bump. A re-flow process is then performed to the solder bump to drive the minor element into the solder bump.

Connection interface conversion chip, connection interface conversion device and operation method

A connection interface conversion chip, a connection interface conversion device and an operation method are provided. The connection interface conversion chip includes a USB interface circuit, a DP interface circuit, a USB core circuit and a switching circuit. The USB interface circuit is suitable for coupling to a USB connector. The DP interface circuit is suitable for coupling to a DP connector. In a first operation mode, at least one USB signal pair received by the USB connector is transmitted to the USB core circuit through the USB interface circuit. The USB core circuit decodes the USB signal pair and generates DP data. The DP data is transmitted to the DP connector by the DP interface circuit. In a second operation mode, the DP data received by the USB connector is transmitted to the DP connector through the USB interface circuit, the switching circuit and the DP interface circuit.

靜電放電保護電路

Method of fabricating antimicrobial complex surface

A method of fabricating an antimicrobial metal complex surface, and the method includes providing an article, and the article has a first metal complex surface treated by anodization. The first metal complex surface is formed with a first pore. Secondly a silver suspension is provided. The silver suspension also has pore sealing agent. The article is soaked in the suspension to form a pore sealing layer having silver particles on the first metal complex surface such that the silver particles are distributed in the pore sealing layer. The antimicrobial metal complex surface fabricated by the method inhibits microorganism growth on the anodized metal surface.

Method for cell placement in semiconductor layout and system thereof

According to an embodiment, a method for cell placement in a semiconductor layout is provided. The method includes: providing a first cell having two sides, each side configured as at least one of a source side and a drain side; providing a place-and-route boundary (prBoundary) of the first cell based on the configuration of the two sides of the first cell; providing a second cell having two sides, each side configured as at least one of a source side and a drain side; providing a prBoundary of the second cell based on the configuration of the two sides of the second cell; and placing the first cell and the second cell based on the prBoundary of the first cell and the prBoundary of the second cell.

Glove

Thermoplastic polyester elastomer and method for manufacturing the same

Disclosed is a thermoplastic polyester elastomer, which is formed by reacting 100 parts by weight of polyester and 0.01 to 2 parts by weight of an epoxy resin with two epoxy groups, wherein the polyester is formed by reacting a parts by mole of a hard-segment diol, b parts by mole of a soft-segment diol, and 1 part by mole of a diacid, wherein 1≦a≦3 and 0.005≦b≦1.5.

Integrated circuit with well and substrate contacts

An integrated circuit comprises standard cells arranged in rows and columns. The integrated circuit also comprises tap cells arranged in rows and columns. The tap cells each comprise a substrate having a first dopant type and a thickness from a first surface of the substrate to a second surface of the substrate. The integrated circuit further comprises a well region in the substrate having a second dopant type different from the first dopant type and a depth from the first surface of the substrate less than the thickness of the substrate. The integrated circuit additionally comprises a first quantity of rows of tap cells and a second quantity of rows of tap cells less than the first quantity. Each row of the first quantity of rows of tap cells comprises at least one well contact, and each row of tap cells of the second quantity of tap cells comprises at least one substrate contact.

Resin composition, prepreg, and substrate employing the same

A disclosure provides a resin composition, a prepreg, and a substrate employing the same. According to an embodiment of the disclosure, the resin composition includes a polyphenylene ether compound, and a bismaleimide. The prepreg includes a cured product of the resin composition. The substrate includes a product fabricated by the resin composition or the prepreg.

Scan cell assignment

One or more systems and methods for scan cell assignment for a design layout of a semiconductor arrangement are provided. The design layout is evaluated to identify a set of sequential cells, such as flip flops connected to circuitry by data paths. Sequential cells within the set of sequential cells are assigned to either a scan cell assignment or a non-scan cell assignment based upon a control path criterion, a register bank criterion, a pipeline depth criterion, a sequential loop criterion, or other criteria to create a cell assignment list. Scan paths are connected to sequential cells assigned to the scan cell assignment so that test patterns can be sent to and received from such sequential cells during testing of the semiconductor arrangement for defects. Power, performance, and area utilization are improved because at least some sequential cells are assigned to the non-scan cell assignment.

Pillar bumps and process for making same

Apparatus and methods for providing solder pillar bumps. Pillar bump connections are formed on input/output terminals for integrated circuits by forming a pillar of conductive material using plating of a conductive material over terminals of an integrated circuit. A base portion of the pillar bump has a greater width than an upper portion. A cross-section of the base portion of the pillar bump may make a trapezoidal, rectangular, or sloping shape. Solder material may be formed on the top surface of the pillar. The resulting solder pillar bumps form fine pitch package solder connections that are more reliable than those of the prior art.