BUS TRANSCEIVER WITH RING SUPPRESSION

Реферат: A transceiver includes a driver stage and a transient-triggered ring suppression circuit. The driver stage has a first transistor coupled between a supply voltage terminal and a first bus terminal and a second transistor coupled between a ground and a second bus terminal. The transient-triggered ring suppression circuit is coupled to the first and second transistors. The transient-triggered ring suppression circuit is configured to be enabled upon transition of the transceiver from a dominant state to a recessive state. Further, while the transceiver is in the recessive state, the transient-triggered ring suppression circuit is configured to attenuate ringing on at least one of the first or second bus terminals.

Заявка: 1. A transceiver , comprising:a driver stage having a first transistor coupled between a supply voltage terminal and a first bus terminal and a second transistor coupled between a ground and a second bus terminal;a third transistor coupled between a common voltage terminal and a terminal of the first transistor, the first transistor having a control input and first and second current terminals;a first capacitor coupled between the first current terminal and the control input of the third transistor;a first resistor coupled between the supply voltage terminal and the control input of the third transistor; anda first switch coupled between the supply voltage terminal and the control input of the third transistor.2. The transceiver of claim 1 , wherein the third switch is configured to be on during a first state of the transceiver claim 1 , and off during a second state of the transceiver.3. The transceiver of claim 2 , wherein the transceiver is a controller area network (CAN) bus transceiver claim 2 , and the first state is a dominant state and the second state is a recessive state.4. The transceiver of claim 1 , further including a voltage buffer having an output coupled to the common voltage terminal.5. The transceiver of claim 1 , further including:a fourth transistor coupled between a terminal of the second transistor and the common voltage terminal, the fourth transistor having a control input and first and second current terminals;a second capacitor coupled between the first current terminal of the fourth transistor and the control input of the fourth transistor;a second resistor coupled between the ground and the control input of the fourth transistor; anda second switch coupled between the ground and the control input of the fourth transistor.6. The transceiver of claim 5 , wherein the first transistor has a control input and the second transistor includes a control input claim 5 , and the transceiver further includes a transmitter driver having a driver input claim 5 , a first output claim 5 , and a second output claim 5 , the driver input configured to receive a transmit signal claim 5 , the first output is coupled to the control input of the first transistor claim 5 , and the second output is coupled to the control input of the second transistor.7. The transceiver of claim 5 , wherein:the third switch is configured to be on during a first state of the transceiver, and off during a second state of the transceiver; andthe fourth switch is configured to be on during the first state of the transceiver, and off during the second state of the transceiver.8. The transceiver of claim 7 , wherein:the transceiver is a controller area network (CAN) bus transceiver, and the first state is a dominant state and the second state is a recessive state; andthe transceiver includes a voltage buffer having an output providing the common voltage terminal.9. The transceiver of claim 1 , wherein the first transistor has a current terminal and the second transistor has a current terminal claim 1 , and the transceiver further includes a recessive nulling circuit coupled to the common voltage terminal claim 1 , the current terminal of the first transistor claim 1 , and the current terminal of the second transistor claim 1 , and the recessive nulling circuit is configured to force the current terminals of the first and second transistors to a voltage on the common voltage terminal for a period of time upon transition of the transceiver from a dominant state to a recessive state.10. A transceiver claim 1 , comprising:a driver stage having a first transistor coupled between a supply voltage terminal and a first bus terminal and a second transistor coupled between a ground and a second bus terminal; anda transient-triggered ring suppression circuit coupled to the first and second transistors, the transient-triggered ring suppression circuit is configured to be enabled upon transition of the transceiver from a dominant state to a recessive state and, while the transceiver is in the recessive state, to attenuate ringing on at least one of the first or second bus terminals.11. The transceiver of claim 10 , wherein the transient-triggered ring suppression circuit includes:a third transistor coupled between a terminal of the second transistor and a common voltage terminal, the third transistor having a control input and first and second current terminals;a first capacitor coupled between the second current terminal of the third transistor and the control input of the third transistor;a first resistor coupled between the ground and the control input of the third transistor; anda first switch coupled between the ground and the control input of the third transistor.12. The transceiver of claim 11 , wherein the transient-triggered ring suppression circuit includes:a fourth transistor coupled between a common voltage terminal and a terminal of the first transistor, the fourth transistor having a control input and first and second current terminals;a second capacitor coupled between the first current terminal and the control input of the fourth transistor;a second resistor coupled between the supply voltage terminal and the control input of the fourth transistor; anda second switch coupled between the supply voltage terminal and the control input of the fourth transistor.13. The transceiver of claim 11 , wherein the first switch is configured to be on during the dominant state claim 11 , and off the recessive state.14. The transceiver of claim 11 , further including a voltage buffer having an output coupled to the common voltage terminal.15. The transceiver of claim 10 , wherein the transient-triggered ring suppression circuit includes:a third transistor coupled between a common voltage terminal and a terminal of the first transistor, the first transistor having a control input and first and second current terminals;a first capacitor coupled between the first current terminal and the control input of the third transistor;a first resistor coupled between the supply voltage terminal and the control input of the third transistor; anda first switch coupled between the supply voltage terminal and the control input of the third transistor.16. The transceiver of claim 10 , wherein the first transistor has a control input and the second transistor includes a control input claim 10 , and the transceiver further includes a transmitter driver having a driver input claim 10 , a first output claim 10 , and a second output claim 10 , the driver input configured to receive a transmit signal claim 10 , the first output is coupled to the control input of the first transistor claim 10 , and the second output is coupled to the control input of the second transistor.17. A transceiver claim 10 , comprising:a driver stage having a first transistor coupled between a supply voltage terminal and a first bus terminal and a second transistor coupled between a ground and a second bus terminal;a third transistor coupled between a common voltage terminal and a terminal of the first transistor, the first transistor having a control input and first and second current terminals;a first capacitor coupled between the first current terminal and the control input of the third transistor;a first resistor coupled between the supply voltage terminal and the control input of the third transistor;a first switch coupled between the supply voltage terminal and the control input of the third transistor;a fourth transistor coupled between a terminal of the second transistor and the common voltage terminal, the fourth transistor having a control input and first and second current terminals;a second capacitor coupled between the first current terminal of the fourth transistor and the control input of the fourth transistor;a second resistor coupled between the ground and the control input of the fourth transistor; anda second switch coupled between the ground and the control input of the fourth transistor.18. The transceiver of claim 17 , further including a voltage buffer having an output coupled to the second current terminals of the third and fourth transistors claim 17 , the voltage buffer configured to generate a common voltage on the common voltage terminal.19. The transceiver of claim 18 , wherein the first transistor has a current terminal and the second transistor has a current terminal claim 18 , and the transceiver further includes a recessive nulling circuit coupled to the common voltage terminal claim 18 , the current terminal of the first transistor claim 18 , and the current terminal of the second transistor claim 18 , and the recessive nulling circuit is configured to force the current terminals of the first and second transistors to the common voltage terminal for a period of time upon transition of the transceiver from a first state to a second state.20. The transceiver of claim 17 , wherein the transceiver is a controller area network (CAN) bus transceiver.

Описание: This application claims priority to U.S. Provisional Application 62/942,763, filed Dec. 3, 2019, titled “Circuit Technique to Absorb RF Energy and Improve Immunity in CAN Transceivers,” which is hereby incorporated by reference in its entirety.The controller area network (CAN) is a bus standard designed to allow microcontrollers and devices to communicate with one another in applications without a host computer. The CAN bus protocol is a message-based protocol, particularly suitable for multiplexed electrical wiring within automobiles but has usefulness in other applications,In one example, a transceiver includes a driver stage and a transient-triggered ring suppression circuit. The driver stage has a first transistor coupled between a supply voltage terminal and a first bus terminal and a second transistor coupled between a ground and a second bus terminal. The transient-triggered ring suppression circuit is coupled to the first and second transistors. The transient-triggered ring suppression circuit is configured to be enabled upon transition of the transceiver from a dominant state to a recessive state. Further, while the transceiver is in the recessive state, the transient-triggered ring suppression circuit is configured to attenuate ringing on at least one of the first or second bus terminals.As CAN bus speeds have increased, ringing on the bus due to improper electrical termination has also increased. As a CAN bus transceiver transitions from a “dominant” state to a “recessive” state, reflections from improperly terminated stubs may cause ringing on the transceiver. If the magnitude of the ringing is high enough, a transceiver will misinterpret the ring as a dominant bit. As such, ringing can cause bit errors. The examples described herein include a CAN bus transceiver that includes a transient-triggered ring suppression circuit which is enabled upon transition of the transceiver to the recessive state. Any ringing on the bus is attenuated through the transient-triggered ring suppression circuit thereby resulting in a smaller amplitude and shorter duration ringing signal thereby resulting in fewer bit errors. The transient-triggered ring suppression circuit described herein may have applicability to other bus protocols besides CAN.shows an example of at least a portion of a CAN bus transceiver . The CAN bus transceiver includes a transmitter and a receiver . The CAN BUS terminals are shown as CANH and CANL. The receiver is coupled to CANH and CANL and receives signals transmitted by another transceiver on the bus and outputs a receive signal, RxD, to other logic (not shown). Receiver includes a differential resistance Rid between CANH and CANL. The transmitter includes a pulse generator , a voltage buffer , a transient-triggered ring suppression circuit , a recessive nulling circuit , and a driver stage . The voltage buffer produces a voltage equal to, in one example, one-half of the supply voltage on a common voltage terminal (VCM).The driver stage includes transistors M-M and a driver . M, M, and M are p-type metal oxide semiconductor field effect transistors (PMOS) and M, M, and M are n-type metal oxide semiconductor field effect transistors (NMOS). As PMOS or NMOS devices, each such transistor includes a control input (gate) and current terminals (source and drain). Other types of transistors can be used as well, such as bipolar junction transistors, which also have control inputs (base) and current terminals (collector and emitter).M-M are connected in series between the supply voltage terminal (VCC) and CANH, with the source of M coupled to VCC, the drain of M connected to the source of M at node N, the drain of M connected to the source of M at node N, and CANH taken from the drain of M. Similarly, M-M are connected in series between ground and CANL, with the source of M coupled to ground, the drain of M connected to the source of M at node N, the drain of M connected to the source of M at node N, and CANL taken from the drain of M. A termination resistor Rterm (e.g., 120 ohms) is connected between CANH and CANL, but the transceiver can be terminated in other ways as well (e.g., with a series-connected 60-ohm resistors between CANH and CANL and capacitor connected between the node between the resistors and ground).The gates of PMOS transistors M and M are connected to ground and thus M and M remain on continuously. The sources of M and M remain fixed at the transistor's threshold voltage above ground (e.g., 0.7 V). M and M operate to block large negative voltages from the respective bus terminal CANH or CANL from damaging the transceiver. The gates of M and M are connected to VCC and block large positive voltages from the respective bus terminal CANH or CANL from damaging the transceiver.The driver receives the transmit signal TxD on its input and drives complementary outputs and which are connected to the gates of M and M, respectively. CANH and CANL are either driven to the dominant state with CANH voltage being higher than the CANL voltage, or not driven and pulled by passive resistors to the recessive state with the CANH voltage being below or equal to the CANL voltage. A “0” data bit encodes the dominant state, while a “1” data bit encodes the recessive state. For the dominant state, TxD is set equal to 0 and for the recessive state, TxD is set equal to 1. With TxD being 0 (dominant state), output of driver is 0 (low) and output is 1 (high). With output being a 0 and output being a 0, PMOS transistor M and NMOS transistor M are both turned on, thereby pulling CANH up towards VCC and CANL down toward ground. In accordance with the CAN bus protocol, in the dominant state the CAN bus differential voltage is nominally 2V. In the recessive state, TxD is a 1 and thus driver output is a 1 and output is a 0 and both M and M are turned off. With M and M being off, the voltages on CANH and CANL passively become approximately equal to VCM through resistors Rterm and Rid. In the example provided above, VCM is equal to VCC/2. In an application in which VCC is 5V, VCM is 2.5V and, in the recessive state, CANH and CANL are both approximately equal to 2.5V (approximately zero differential voltage).The recessive nulling circuit includes NMOS transistors M-M. The gates of M and M are connected together and to pulse generator . The drain of M is connected to the drain of M and source of M (node N). M is connected between the drain of M and the drain of M and source of M (node N). M is biased on and is operative to block large positive voltages on N from damaging the transceiver. The sources of M and M are connected together and to the sources of M and M. The gates of M and M are connected together and to pulse generator . The drain of M is connected to the drain of M and to the source of M (node N). M is connected between the drain of M and the drain of M and source of M (node N). M is biased on and is operative to block large positive voltages on N from damaging the transceiver.The pulse generator generates pulses and on outputs and , respectively, responsive to 0-to-1 transition of TxD. The width of the pulses can be fixed or programmable. In one example, the width is 200 nanoseconds. During the pulses, M, M, M, and M are on. The recessive nulling circuit functions to force each of nodes N-N to be equal to VCM for a short period of time (e.g., 200 ns) upon transition into the recessive node to help force the voltages on CANH and CANL to be equal to each other and to VCM. Once the pulses and end, CAN and CANL remain at VCM.The transient-triggered ring suppression circuit helps to suppress ringing on the CAN bus upon the transition from the dominant state into the recessive state. The transient-triggered ring suppression circuit includes switches SW and SW, resistors R and R, capacitors C and C, and NMOS transistors M and M. SW is coupled between VCC and the gate of M. In one example, SW may be a PMOS transistor. R also is coupled between VCC and the gate of M. C is coupled between the source and gate of M. SW is coupled between ground and the gate of M. In one example, SW may be an NMOS transistor. R also is coupled between ground and the gate of M. C is coupled between the gate and drain of M.During the dominant state (TxD is 0), M is on. With M on, node N is pulled up to VCC and thus source of M is VCC. The source of M is coupled to VCM. During the dominant state, control signals and cause switches SW and SW to be closed. In this example, control signals and are generated by the pulse generator . If SW is implemented as a PMOS transistor, control signal may be asserted by the pulse generator to track the logic state of TXD (i.e., when TXD is high, control signal is forced high, and vice versa). If SW is implemented as an NMOS transistor, control signal may be asserted by the pulse generator to track the logical inverse of the logic state of TXD (i.e., when TXD is high, control signal is forced low, and vice versa). In one example, the pulse generator includes a buffer to generate control signals and (the buffer having a positive and negative outputs). With SW closed, the gate of M is pulled up to VCC. As such, the gate-to-source voltage across M is insufficient to turn on M and thus M is off. With SVV closed, the gate of M is pulled maintaining M in an off state.Upon entry into the recessive state, control signals and change logic state and cause switches SW and SW to be open to thereby enable the transient-triggered ring suppression circuit. R pulls the gate of M high thereby maintaining M in an off state. However, any ringing signal on CANH propagates through M and M to capacitor C. C becomes charged due to the ringing signal and if the magnitude of the ringing signal is large enough, C will charge to a sufficiently large voltage (at least a threshold voltage above VCM) to turn on M. The resistor R, which is connected between VCC and the gate of M, discharges the gate of M thereby eventually turning of M. As such, the ringing signal on CANH is dissipated through that portion of the transient-triggered ring suppression circuit coupled to CANH (i.e., R, C, and M).In the recessive state and on the CANL side of the bus, R pulls the gate of M low thereby maintaining M in an off state. Any ringing signal on CANL propagates through M and M to capacitor C. C becomes charged due to the ringing signal and if the magnitude of the ringing signal is large enough, C will charge to a sufficiently large voltage (at least a threshold voltage above M's source which is connected to VCM) to turn on M. The resistor R, which is connected between ground and the gate of M, discharges the gate of M thereby eventually turning of M. As such, the ringing signal on CANL is dissipated through that portion of the transient-triggered ring suppression circuit coupled to CANL (i.e., R, C, and M).illustrates voltage levels of CANH and CANL during the dominant state and upon transition into the recessive state for a CAN bus transceiver that does not have the transient-triggered ring suppression circuit . The upper curves show the CANH and CANL signals and the lower curve is the differential voltage (i.e., CANH-CANL). During the dominant state, CANH is 3.5V and CANL is 1.5V and thus differential voltage is 2V. Upon entry into the recessive state, CANH and CANL voltage levels are brought close together at approximately VCM, which is 2.5V in this example, However, in the example of , ringing occurs upon entry into the recessive state. The ringing signal magnitude decreases over time. The initial ringing peak shown at is high enough so as to cause a bit error in the transceiver (misinterpretation of ringing as a new dominant state).illustrates CANH and CANL during the dominant state and upon transition into the recessive state for a CAN bus transceiver that has the transient-triggered ring suppression circuit described above. As can be seen, the magnitude of the ringing is attenuated compared to the ringing in , and the peak ringing level is not large enough to cause a bit error. Further, ringing dissipates much more quickly than ringing .The term “couple” is used throughout the specification. The term may cover connections, communications, or signal paths that enable a functional relationship consistent with the description of the present disclosure. For example, if device A generates a signal to control device B to perform an action, in a first example device A is coupled to device B, or in a second example device A is coupled to device B through intervening component C if intervening component C does not substantially alter the functional relationship between device A and device B such that device B is controlled by device A via the control signal generated by device A.Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.