Reduction of the effects of magnification errors and reticle rotation errors on overlay errors
Номер патента: EP1161707A1
Опубликовано: 12-12-2001
Автор(ы): Bharath Rangarajan, Kathleen R. Early, Michael K. Templeton, Terry Manchester
Принадлежит: Advanced Micro Devices Inc
Опубликовано: 12-12-2001
Автор(ы): Bharath Rangarajan, Kathleen R. Early, Michael K. Templeton, Terry Manchester
Принадлежит: Advanced Micro Devices Inc
Реферат: The present invention relates to wafer alignment. A reticle (50) is employed which includes, a design (54) and first and second alignment marks (60, 62). The second alignment mark is symmetric to the first alignment mark such that a reticle center point (70) is a midpoint of the first and second alignment marks. The first alignment mark is printed on a surface layer of the wafer. The second alignment mark is printed on the surface layer at an offset from the first alignment mark. A virtual alignment mark is determined, the virtual alignment mark being a midpoint of the printed first and second alignment marks. The virtual alignment mark is employed to facilitate aligning the wafer. The symmetric relationship between the first and second alignment mark results in the negation of print errors of the marks due to reticle rotation and/or lens magnification with respect to the virtual alignment mark. The employment of the virtual alignment mark substantially facilitates mitigation of overlay error.
Reduction of the effects of magnification errors and reticle rotation errors on overlay errors
Номер патента: WO2000054108A1. Автор: Bharath Rangarajan,Michael K. Templeton,Kathleen R. Early,Terry Manchester. Владелец: Advanced Micro Devices, Inc.. Дата публикации: 2000-09-14.