A system and method for residue entrapment utilizing a polish and sacrificial fill for semiconductor fabrication
Номер патента: WO2000052746A9
Опубликовано: 14-03-2002
Автор(ы): David Ziger, Hunter Brugge
Принадлежит: Koninkl Philips Electronics Nv
Опубликовано: 14-03-2002
Автор(ы): David Ziger, Hunter Brugge
Принадлежит: Koninkl Philips Electronics Nv
Реферат: One limited aspect of CMP is that the deposition of the layer (110) being planarized generally has an effective distance over which gaps (112) can be filled. These gaps can fill with a residue that adversely effects the resultant semiconductor. A technique that inhibits the accumulation of residue deposits a sacrificial layer of material after deposition of a planarizing layer (110), but before CMP. This layer is selected so that it fills the gaps (112) from the manufacturing process. CMP is performed after the sacrificial layer is formed. However, since the gaps (112) are filled, residues cannot collet. Then, after the CMP is performed, the sacrificial layer is removed by applying a solvent to the sacrificial layer. The sacrificial material must fill the gaps (112) yet be soluble for removal after the CMP processing is performed.
Methods for forming features in a material layer utilizing a combination of a main etching and a cyclical etching process
Номер патента: US09543163B2. Автор: Srinivas D. Nemani,Sean S. Kang,Mang-Mang Ling,Jungmin Ko,Bradley Howard,Jeremiah T. Pender. Владелец: Applied Materials Inc. Дата публикации: 2017-01-10.