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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 11382. Отображено 100.
12-01-2012 дата публикации

Method for molecular adhesion bonding with compensation for radial misalignment

Номер: US20120006463A1
Автор: Gweltaz Gaudin
Принадлежит: Soitec SA

A method for bonding a first wafer on a second wafer by molecular adhesion, where the wafers have an initial radial misalignment between them. The method includes bringing the two wafers into contact so as to initiate the propagation of a bonding wave between the two wafers while a predefined bonding curvature is imposed on at least one of the two wafers during the contacting step as a function of the initial radial misalignment.

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Номер записи: 1
12-01-2012 дата публикации

Method of manufacturing diode, and diode

Номер: US20120007222A1
Автор: Kimimori Hamada, Tadashi Misumi
Принадлежит: Toyota Motor Corp

The present specification provides a method of efficiently manufacturing diodes in which recovery surge voltage is hardly generated. The method manufactures a diode including a high concentration n-type semiconductor layer, a medium concentration n-type semiconductor layer formed on the high concentration n-type semiconductor layer, a low concentration n-type semiconductor layer formed on the medium concentration n-type semiconductor layer, and a p-type semiconductor layer formed on the low concentration n-type semiconductor layer. This manufacturing method includes growing the low concentration n-type semiconductor layer on an n-type semiconductor substrate by epitaxial growth, wherein a concentration of n-type impurities in the low concentration n-type semiconductor layer is lower than that in the n-type semiconductor substrate, and forming the high concentration n-type semiconductor layer by injecting n-type impurities to a lower surface of the n-type semiconductor substrate.

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Номер записи: 2
02-02-2012 дата публикации

Semiconductor wafer, method of producing semiconductor wafer, method of judging quality of semiconductor wafer, and electronic device

Номер: US20120025271A1
Автор: Tsuyoshi Nakano
Принадлежит: Sumitomo Chemical Co Ltd

There is provided a high-performance compound semiconductor epitaxial wafer that has an improved linearity of the voltage-current characteristic, a producing method thereof, and a judging method thereof. Provided is a semiconductor wafer including a compound semiconductor that produces a two-dimensional carrier gas, a carrier supply semiconductor that supplies a carrier to the compound semiconductor, and a mobility lowering semiconductor that is disposed between the compound semiconductor and the carrier supply semiconductor and that has a mobility lowering factor that makes the mobility of the carrier in the mobility lowering semiconductor lower than the mobility of the carrier in the compound semiconductor.

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Номер записи: 3
09-02-2012 дата публикации

Diamond semiconductor element and process for producing the same

Номер: US20120034737A1
Автор: Kenji Ueda, Makoto Kasu, Toshiki Makimoto, Yoshiharu Yamauchi
Принадлежит: Nippon Telegraph and Telephone Corp

A process of producing a diamond thin-film includes implanting dopant into a diamond by an ion implantation technique, forming a protective layer on at least part of the surface of the ion-implanted diamond, and firing the protected ion-implanted diamond at a firing pressure of no less than 3.5 GPa and a firing temperature of no less than 600° C. A process of producing a diamond semiconductor includes implanting dopant into each of two diamonds by an ion implantation technique and superimposing the two ion-implanted diamonds on each other such that at least part of the surfaces of each of the ion-implanted diamonds makes contact with each other, and firing the ion implanted diamonds at a firing pressure of no less than 3.5 GPa and a firing temperature of no less than 600° C.

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Номер записи: 4
12-04-2012 дата публикации

Method of manufacturing vertical semiconductor device

Номер: US20120088343A1
Автор: Jong-Hyuk Kang, Jong-wook Lee, Yong-Hoon Son
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A vertical semiconductor device, a DRAM device, and associated methods, the vertical semiconductor device including single crystalline active bodies vertically disposed on an upper surface of a single crystalline substrate, each of the single crystalline active bodies having a first active portion on the substrate and a second active portion on the first active portion, and the first active portion having a first width smaller than a second width of the second active portion, a gate insulating layer on a sidewall of the first active portion and the upper surface of the substrate, a gate electrode on the gate insulating layer, the gate electrode having a linear shape surrounding the active bodies, a first impurity region in the upper surface of the substrate under the active bodies, and a second impurity region in the second active portion.

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Номер записи: 5
12-04-2012 дата публикации

Method for molecular bonding of silicon and glass substrates

Номер: US20120088350A1
Автор: Daniel Delprat, Sebastien Kerdiles
Принадлежит: Soitec SA

The present invention concerns a method for bonding a first substrate having a first surface to a second substrate having a second surface. This method includes the steps of holding the first substrate by at least two support points, positioning the first substrate and the second substrate so that the first surface and the second surface face each other, deforming the first substrate by applying between at least one pressure point and the two support points a strain toward the second substrate, bringing the deformed first surface and the second surface into contact, and progressively releasing the strain to facilitate bonding of the substrates while minimizing or avoiding the trapping of air bubbles between the substrates.

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Номер записи: 6
19-04-2012 дата публикации

Programmable Gate III-Nitride Power Transistor

Номер: US20120091470A1
Автор: Michael A. Briere
Принадлежит: International Rectifier Corp USA

A III-nitride semiconductor device which includes a charged floating gate electrode.

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Номер записи: 7
19-04-2012 дата публикации

Gas injection device and solar cell manufacturing method using the same

Номер: US20120094424A1
Автор: In-Ki Kim, Jung-Gyu Nam, Sang-Cheol Park, Seong-Ryong HWANG, Seoung-Jin SEO, Woo-Su Lee
Принадлежит: SAMSUNG ELECTRONICS CO LTD, Samsung SDI Co Ltd

A solar cell manufacturing method includes forming a first electrode on a substrate, forming a mixed metal layer on the first electrode, forming a light absorbing layer by injecting hydrogen selenide on the entire surface of the mixed metal layer using a gas injection device, and forming a second electrode on the light absorbing layer. Further, the gas injection device includes a gas pipeline, an inner gas pipe positioned in the gas pipeline and having an opening, and a plurality of injection nozzles disposed below the gas pipeline.

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Номер записи: 8
19-04-2012 дата публикации

Method for forming integrated circuits on a strained semiconductor substrate

Номер: US20120094470A1
Автор: Aomar Halimaoui, Daniel Bensahel
Принадлежит: STMicroelectronics Crolles 2 SAS

A method for forming an electronic circuit on a strained semiconductor substrate, including the steps of: forming, on a first surface of a semiconductor substrate, electronic components defining electronic chips to be sawn; and forming at least portions of a layer of a porous semiconductor material on the side of a second surface of the semiconductor substrate, opposite to the first surface, to bend the semiconductor substrate.

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Номер записи: 9
26-04-2012 дата публикации

Semiconductor integrated circuit device and a method of fabricating the same

Номер: US20120097950A1
Автор: Jong-wook Lee, Si-Young Choi, Yong-Hoon Son
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A method of fabricating a semiconductor integrated circuit includes forming a first dielectric layer on a semiconductor substrate, patterning the first dielectric layer to form a first patterned dielectric layer, forming a non-single crystal seed layer on the first patterned dielectric layer, removing a portion of the seed layer to form a patterned seed layer, forming a second dielectric layer on the first patterned dielectric layer and the patterned seed layer, removing portions of the second dielectric layer to form a second patterned dielectric layer, irradiating the patterned seed layer to single-crystallize the patterned seed layer, removing portions of the first patterned dielectric layer and the second patterned dielectric layer such that the single-crystallized seed layer protrudes in the vertical direction with respect to the first and/or the second patterned dielectric layer, and forming a gate electrode in contact with the single-crystal active pattern.

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Номер записи: 10
26-04-2012 дата публикации

Schottky rectifier

Номер: US20120098082A1
Автор: Chih-Wei Hsu, Florin Udrea, Yih-Yin Lin
Принадлежит: VISHAY GENERAL SEMICONDUCTOR LLC

A semiconductor rectifier includes a semiconductor substrate having a first type of conductivity. A first layer, which is formed on the substrate, has the first type of conductivity and is more lightly doped than the substrate. A second layer having a second type of conductivity is formed on the substrate and a metal layer is disposed over the second layer. The second layer is lightly doped so that a Schottky contact is formed between the metal layer and the second layer. A first electrode is formed over the metal layer and a second electrode is formed on a backside of the substrate.

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Номер записи: 11
26-04-2012 дата публикации

Laser assisted direct bonding

Номер: US20120100318A1
Автор: David A. Ruben, Michael S. Sandlin, Ralph B. Danzl
Принадлежит: MEDTRONIC INC

Techniques are described for directly bonding different substrates together. In some examples, a technique includes placing a first surface of a first substrate in contact with a second surface of a second substrate to directly bond the first substrate to the second substrate at a contact location. The contact location is defined where at least a portion of the first surface of the first substrate contacts at least a portion of the second surface of the second substrate. The technique may also include directing a laser beam on at least a portion of the contact location to strengthen the direct bond between the first substrate and the second substrate. In this manner, a direct bond may be heated with localized laser energy to strengthen the direct bond. Localized laser energy may create a strong direct bond while minimizing thermal defects in regions proximate the direct bond.

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Номер записи: 12
14-06-2012 дата публикации

High-voltage transistor device with integrated resistor

Номер: US20120146105A1
Автор: Sujit Banerjee, Vijay Parthasarathy
Принадлежит: Power Integrations Inc

A high-voltage device structure comprises a resistor coupled to a tap transistor that includes a JFET in a configuration wherein a voltage provided at a terminal of the JFET is substantially proportional to an external voltage when the external voltage is less than a pinch-off voltage of the JFET. The voltage provided at the terminal being substantially constant when the external voltage is greater than the pinch-off voltage. One end of the resistor is substantially at the external voltage when the external voltage is greater than the pinch-off voltage. When the external voltage is negative, the resistor limits current injected into the substrate. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.

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Номер записи: 13
19-07-2012 дата публикации

Method of manufacturing silicon carbide semiconductor device

Номер: US20120184094A1
Автор: Shunsuke Yamada
Принадлежит: Sumitomo Electric Industries Ltd

A silicon carbide substrate having a substrate surface is prepared. An insulating film is formed to cover a part of the substrate surface. A contact electrode is formed on the substrate surface, so as to be in contact with the insulating film. The contact electrode contains Al, Ti, and Si atoms. The contact electrode includes an alloy film made of an alloy containing Al atoms and at least any of Si atoms and Ti atoms. The contact electrode is annealed such that the silicon carbide substrate and the contact electrode establish ohmic connection with each other. Thus, in a case where a contact electrode having Al atoms is employed, insulation reliability of the insulating film can be improved.

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Номер записи: 14
09-08-2012 дата публикации

Integrated Transistor and Anti-Fuse Programming Element for a High-Voltage Integrated Circuit

Номер: US20120199885A1
Автор: Martin H. Manley, Sujit Banerjee
Принадлежит: Power Integrations Inc

A semiconductor device includes an N type well region in a P type substrate. A source region of a MOSFET is laterally separated from a boundary of the well region, which includes the drain of the MOSFET. An insulated gate of the MOSFET extends laterally from the source region to at least just past the boundary of the well region. A polysilicon layer, which forms a first plate of a capacitive anti-fuse, is insulated from an area of the well region, which forms the second plate of the anti-fuse. The anti-fuse is programmed by application of a voltage across the first and second capacitive plates sufficient to destroy at least a portion of the second dielectric layer, thereby electrically shorting the polysilicon layer to the drain of the HVFET.

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Номер записи: 15
23-08-2012 дата публикации

Method of forming an integrated power device and structure

Номер: US20120211827A1
Автор: Francine Y. Robb, Prasad Venkatraman, Stephen P. Robb, Zia Hossain
Принадлежит: Individual

In one embodiment, a vertical power transistor is formed on a semiconductor substrate with other transistors. A portion of the semiconductor layer underlying the vertical power transistor is doped to provide a low on-resistance for the vertical power transistor.

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Номер записи: 16
30-08-2012 дата публикации

Polymer compound and method for producing the same

Номер: US20120217445A1
Автор: Daisuke Fukushima, Kazuei Ohuchi, Mari Seto, Yusuke Ishii
Принадлежит: Sumitomo Chemical Co Ltd

A polymer compound comprising a first constitutional unit represented by formula (1), a second constitutional unit represented by formula (2), and at least one constitutional unit selected from the group consisting of a third constitutional unit represented by formula (3) and a fourth constitutional unit represented by formula (4).

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Номер записи: 17
27-09-2012 дата публикации

Heterostructure for electronic power components, optoelectronic or photovoltaic components

Номер: US20120241821A1
Автор: Chris Werkhoven, Fabrice Letertre, Ionut Radu, Jean-Marc Bethoux, Oleg Kononchuck
Принадлежит: Soitec SA

A heterostructure that includes, successively, a support substrate of a material having an electrical resistivity of less than 10 −3 ohm·cm and a thermal conductivity of greater than 100 W·m −1 ·K −1 , a bonding layer, a first seed layer of a monocrystalline material of composition Al x In y Ga (1-x-y) N, a second seed layer of a monocrystalline material of composition Al x In y Ga (1-x-y) N, and an active layer of a monocrystalline material of composition Al x In y Ga (1-x-y) N, and being present in a thickness of between 3 and 100 micrometers. The materials of the support substrate, the bonding layer and the first seed layer are refractory at a temperature of greater than 750° C., the active layer and second seed layer have a difference in lattice parameter of less than 0.005 Å, the active layer is crack-free, and the heterostructure has a specific contact resistance between the bonding layer and the first seed layer that is less than or equal to 0.1 ohm·cm 2 .

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Номер записи: 18
08-11-2012 дата публикации

Semiconductor device with seg film active region

Номер: US20120280394A1
Автор: Young Bog Kim
Принадлежит: Hynix Semiconductor Inc

A semiconductor device and a method for manufacturing the same are provided. A barrier film is formed in a device separating structure, and the device separating structure is etched at a predetermined thickness to expose a semiconductor substrate. Then, a SEG film is grown to form an active region whose area is increased. As a result, a current driving power of a transistor located at a cell region and peripheral circuit regions is improved.

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Номер записи: 19
22-11-2012 дата публикации

Functional element and manufacturing method of same

Номер: US20120292642A1
Автор: Akihiro Urata, Masahiro Araki, Masahiro Shiota, Takaaki Utsumi
Принадлежит: Sharp Corp

Provided is a functional element which is obtained by forming a lamination film on a substrate and then dividing the substrate and the lamination film into a desired shape. The functional element has a hexagonal substrate, a lamination film formed on a C surface of the substrate, and a plurality of divided surfaces which are exposed by dividing the substrate into quadrilaterals. At least one line of division lines in the case of dividing the substrate into quadrilaterals is perpendicular to any one of equivalent directions of [ 1 - 100], [ - 1010], and [ 01 - 01] of the substrate from a [ 0001 ] direction of the substrate, and the divided surfaces formed by the division lines are inclined in a direction of other divided surfaces to which at least a part thereof is opposed.

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Номер записи: 20
29-11-2012 дата публикации

Intermediate structure, method and substrate for fabricating flexible display device

Номер: US20120300419A1
Автор: Fang-An Shu, Ted-Hong Shinn, Wen-Chung Tang, Yao-Chou Tsai
Принадлежит: E Ink Holdings Inc

An intermediate structure of a flexible display device includes a substrate, an etching layer, a flexible substrate, and a display module. A trench structure is formed in a surface of the substrate. The etching layer is formed on the surface and covers the substrate. The flexible substrate is disposed on the etching layer. The flexible substrate and the substrate are spaced apart from each other by the etching layer. The display module is disposed on the flexible substrate. The flexible substrate can be peeled from the substrate without applying a mechanical force and thus the yield is improved, and the process time and the fabricating cost are also reduced. In addition, the present invention also provides a substrate for fabricating a flexible display device and a method for fabricating a flexible display device.

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Номер записи: 21
06-12-2012 дата публикации

Process for preparing substituted pentacenes

Номер: US20120305854A1
Автор: Clare Bailey, Martin Heeney, Steven Tierney, Weimin Zhang
Принадлежит: Merck Patent GmBH

The invention relates to a process of preparing substituted pentacenes, to novel pentacenes prepared by this process, to the use of the novel pentacenes as semiconductors or charge transport materials in optical, electrooptical or electronic devices including field effect transistors (FETs), electroluminescent, photovoltaic and sensor devices, and to FETs and other semiconducting components or materials comprising the novel pentacenes.

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Номер записи: 22
03-01-2013 дата публикации

Method for controlled removal of a semiconductor device layer from a base substrate

Номер: US20130005119A1
Автор: Cheng-Wei Cheng, Devendra K. Sadana, Kuen-Ting Shiu, Norma E. Sosa Cortes, Stephen W. Bedell
Принадлежит: International Business Machines Corp

A method of removing a semiconductor device layer from a base substrate is provided that includes providing a crack propagation layer on an upper surface of a base substrate. A semiconductor device layer including at least one semiconductor device is formed on the crack propagation layer. Next, end portions of the crack propagation layer are etched to initiate a crack in the crack propagation layer. The etched crack propagation layer is then cleaved to provide a cleaved crack propagation layer portion to a surface of the semiconductor device layer and another cleaved crack propagation layer portion to the upper surface of the base substrate. The cleaved crack propagation layer portion is removed from the surface of the semiconductor device layer and the another cleaved crack propagation layer portion is removed from the upper surface of the base substrate.

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Номер записи: 23
21-03-2013 дата публикации

Compound semiconductor device and method of manufacturing the same

Номер: US20130069113A1
Автор: Atsushi Yamada
Принадлежит: Fujitsu Ltd

An embodiment of a compound semiconductor device includes: a Si substrate; a Si oxide layer formed over a surface of the Si substrate; a nucleation layer formed over the Si oxide layer, the nucleation layer exposing a part of the Si oxide layer; and a compound semiconductor stacked structure formed over the Si oxide layer and the nucleation layer.

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Номер записи: 24
21-03-2013 дата публикации

METHOD FOR REDUCING IRREGULARITIES AT THE SURFACE OF A LAYER TRANSFERRED FROM A SOURCE SUBSTRATE TO A GLASS-BASED SUPPORT SUBSTRATE

Номер: US20130071997A1
Автор: Ben-Mohamed Nadia, Delprat Daniel, Duret Carine, Lallement Fabrice
Принадлежит: SOITEC

A method for reducing irregularities at the surface of a layer transferred from a source substrate to a glass-based support substrate, by generating a weakening zone in the source substrate; contacting the source substrate and the glass-based support substrate; and splitting the source substrate at the weakening zone; wherein the glass-based substrate has a thickness of between 300 μm and 600 μm. 114.-. (canceled)15. A method for reducing irregularities at the surface of a layer transferred from a source substrate to a glass-based support substrate , which comprises:generating a weakening zone in the source substrate with the weakening zone defining the thickness of the layer to be transferred;contacting the source substrate and a glass-based support substrate that has a thickness of between 300 μm and 600 μm; andsplitting the source substrate at the weakening zone to transfer the layer to the glass-based support substrate.16. The method according to claim 15 , wherein the thickness of the glass-based substrate is comprised between 300 μm and 500 μm.17. The method according to claim 15 , wherein the thickness of the glass-based substrate is 300 μm to less than 500 μm.18. The method according to claim 17 , wherein the thickness of the glass-based substrate is between 350 μm and 450 μm.19. The method according to claim 15 , wherein the source substrate has a bonding surface and the glass-based support substrate has a bonding surface claim 15 , and with the layer to be transferred from the source substrate to the glass-based support substrate being defined between the bonding surface and the weakening zone of the source substrate20. The method according to claim 19 , the contacting includes contacting the bonding surfaces of the source and glass-based support substrates.21. The method according to claim 15 , wherein the glass-based support substrate is entirely made of glass.22. The method according to claim 15 , which further comprises providing at least one ...

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Номер записи: 25
28-03-2013 дата публикации

Semiconductor device

Номер: US20130075750A1
Автор: Yuichi Minoura
Принадлежит: Fujitsu Ltd

A semiconductor device includes a first semiconductor layer formed on a substrate; a second semiconductor layer formed on the first semiconductor layer; a third semiconductor layer formed on the second semiconductor layer; a gate electrode formed on the third semiconductor layer; and a source electrode and a drain electrode formed on the second semiconductor layer. The third semiconductor layer is formed with a semiconductor material doped with a p-type impurity element. In the third semiconductor layer, a p-type area is formed immediately below the gate electrode, and a high resistance area having a higher resistance than the p-type area is formed in an area other than the p-type area.

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Номер записи: 26
28-03-2013 дата публикации

Compound semiconductor device and method of manufacturing the same

Номер: US20130075751A1
Автор: Kenji Imanishi
Принадлежит: Fujitsu Ltd

An embodiment of a compound semiconductor device includes: a substrate; an electron channel layer and an electron supply layer formed over the substrate; a gate electrode, a source electrode and a drain electrode formed on or above the electron supply layer; a p-type semiconductor layer formed between the electron supply layer and the gate electrode; and a hole barrier layer formed between the electron supply layer and the p-type semiconductor layer, a band gap of the hole barrier layer being larger than that of the electron supply layer.

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Номер записи: 27
28-03-2013 дата публикации

Semiconductor device

Номер: US20130075786A1
Автор: Tetsuro ISHIGURO
Принадлежит: Fujitsu Ltd

A semiconductor device including a high resistance layer formed on a substrate, the high resistance layer being formed with a semiconductor material doped with an impurity element that makes the semiconductor material highly resistant; a multilayer intermediate layer formed on the high resistance layer; an electron transit layer formed with a semiconductor material on the multilayer intermediate layer; and an electron supply layer formed with a semiconductor material on the electron transit layer, wherein the multilayer intermediate layer is formed with a multilayer film in which a GaN layer and an AlN layer are alternately laminated.

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Номер записи: 28
04-04-2013 дата публикации

Nitride semiconductor device and manufacturing method thereof

Номер: US20130082277A1
Автор: Ki Yeol Park, Seok Yoon HONG, Woo Chul Jeon, Young Hwan Park
Принадлежит: Samsung Electro Mechanics Co Ltd

The present invention relates to a nitride semiconductor device and a manufacturing method thereof. According to one aspect of the present invention, a nitride semiconductor device including: a nitride semiconductor layer having a 2DEG channel; a source electrode in ohmic contact with the nitride semiconductor layer; a drain electrode in ohmic contact with the nitride semiconductor layer; a plurality of p-type nitride semiconductor segments formed on the nitride semiconductor layer and each formed lengthways from a first sidewall thereof, which is spaced apart from the source electrode, to a drain side; and a gate electrode formed to be close to the source electrode and in contact with the nitride semiconductor layer between the plurality of p-type semiconductor segments and portions of the p-type semiconductor segments extending in the direction of a source-side sidewall of the gate electrode aligned with the first sidewalls of the p-type nitride semiconductor segments is provided.

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Номер записи: 29
04-04-2013 дата публикации

Compound semiconductor device and method for fabricating the same

Номер: US20130082360A1
Автор: Atsushi Yamada, Kenji Imanishi, Norikazu Nakamura, Toyoo Miyajima
Принадлежит: Fujitsu Ltd

A compound semiconductor multilayer structure is formed on a Si substrate. The compound semiconductor multilayer structure includes an electrode transit layer, an electrode donor layer formed above the electron transit layer, and a cap layer formed above the electron donor layer. The cap layer contains a first crystal polarized in the same direction as the electron transit layer and the electron donor layer and a second crystal polarized in the direction opposite to the polarization direction of the electron transit layer and the electron donor layer.

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Номер записи: 30
18-04-2013 дата публикации

Bonded substrate and method of manufacturing the same

Номер: US20130093063A1
Автор: Bohyun Lee, Bonghee Jang, Dong-Woon Kim, Donghyun Kim, Joong Won Shur, Mikyoung Kim, Minju Kim, Seung Yong Park
Принадлежит: Samsung Corning Precision Materials Co Ltd

A bonded substrate having a plurality of grooves and a method of manufacturing the same. The method includes the following steps of implanting ions into a first substrate, thereby forming an ion implantation layer, bonding the first substrate to a second substrate having a plurality of grooves in one surface thereof such that the first substrate is bonded to the one surface, and cleaving the first substrate along the ion implantation layer.

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Номер записи: 31
23-05-2013 дата публикации

Silicon carbide bipolar junction transistor

Номер: US20130126910A1
Автор: Martin Domeij
Принадлежит: Fairchild Semiconductor Corp

In at least one aspect, an apparatus can include a silicon carbide material, a base contact disposed on a first portion of the silicon carbide material, and an emitter contact disposed on a second portion of the silicon carbide material. The apparatus can also include a dielectric layer disposed on the silicon carbide material and disposed between the base contact and the emitter contact, and a surface electrode disposed on the dielectric layer and separate from the base contact and the emitter contact.

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Номер записи: 32
23-05-2013 дата публикации

ELECTROMECHANICAL TRANSDUCER AND METHOD OF PRODUCING THE SAME

Номер: US20130126993A1
Автор: Akiyama Takahiro, Torashima Kazutoshi
Принадлежит: CANON KABUSHIKI KAISHA

The present invention relates to an electromechanical transducer and a method of producing it, in which the substrate rigidity is maintained to prevent the substrate from being broken during formation of dividing grooves or a film. 1. A method of producing an electromechanical transducer including a plurality of elements each having at least one cell , the method comprising:forming an insulating layer on a first substrate and forming gaps in the insulating layer;bonding a second substrate to the insulating layer provided with the gaps;reducing the thickness of the second substrate;forming dividing grooves in the first substrate to form a plurality of elements on the opposite side to the side of the insulating layer provided with the gaps; andfilling at least partially the dividing grooves of the first substrate with an insulating member, whereinthe step of forming dividing grooves in the first substrate to form a plurality of elements and the step of filling at least partially the dividing grooves of the first substrate with an insulating member are conducted after the step of bonding the second substrate to the insulating layer; andthe step of reducing the thickness of the second substrate is conducted after the step of filling at least partially the dividing grooves of the first substrate with an insulating member.2. The method according to claim 1 , wherein the first substrate and the second substrate are a first silicon substrate and a second silicon substrate claim 1 , respectively.3. The method according to claim 1 , wherein the insulating member is silicon oxide formed from tetraethoxysilane.4. The method according to claim 1 , wherein the widths of the dividing grooves at the surface side claim 1 , on which the gaps are formed claim 1 , of the first substrate are smaller than those of the dividing grooves at the other surface side of the first substrate.5. The method according to claim 1 , wherein the widths of the dividing grooves at the inner of the first ...

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Номер записи: 33
30-05-2013 дата публикации

METHOD OF MANUFACTURING GaN-BASED SEMICONDUCTOR DEVICE

Номер: US20130137220A1
Автор: Hideki Matsubara, Kuniaki Ishihara
Принадлежит: Sumitomo Electric Industries Ltd

A method of manufacturing a GaN-based semiconductor device includes the steps of: preparing a composite substrate including: a support substrate having a thermal expansion coefficient at a ratio of not less than 0.8 and not more than 1.2 relative to a thermal expansion coefficient of GaN; and a GaN layer bonded to the support substrate, using an ion implantation separation method; growing at least one GaN-based semiconductor layer on the GaN layer of the composite substrate; and removing the support substrate of the composite substrate by dissolving the support substrate. Thus, the method of manufacturing a GaN-based semiconductor device is provided by which GaN-based semiconductor devices having excellent characteristics can be manufactured at a high yield ratio.

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Номер записи: 34
06-06-2013 дата публикации

PROCESS FOR BONDING TWO SUBSTRATES

Номер: US20130139946A1
Автор: Colnat Cyrille, Gaudin Gweltaz, Giard Pascale, Lallement Fabrice
Принадлежит: SOITEC

The invention relates to a method for bonding two substrates, in particular two semiconductor substrates which, in order to be able to improve the reliability of the process, provides the step of providing a gaseous flow over the bonding surfaces of the substrates. The gaseous flow is preferably a laminar flow that is essentially parallel to the bonding surfaces of the substrates, and has a temperature in a range of from room temperature up to 100° C. 1. A method for bonding two substrates to one another , which comprises , prior to bonding , providing a gaseous flow over bonding surfaces between the substrates until the substrates come into contact , wherein the gaseous flow is a laminar flow that is essentially parallel to the bonding surfaces of the substrates , and the gaseous flow has a temperature in a range of from room temperature up to 100° C.2. The method according to claim 1 , wherein the gaseous flow is provided during a heat treatment of the two substrates.3. The method according to claim 2 , wherein the gaseous flow is heated such that the heat treatment is at least partially carried out using the heated gaseous flow.4. The method according to claim 3 , wherein the heat treatment is completely carried out using the heated gaseous flow.5. The method according to claim 1 , wherein the gaseous flow comprises a gas having a thermal conductivity of 10*10−3 W/m.K.6. The method according to claim 1 , wherein the gaseous flow comprises an inert gas.7. The method according to claim 6 , wherein the inert gas is nitrogen or argon.8. The method according to claim 1 , wherein the gaseous flow is provided in an oxidizing atmosphere.9. The method according to claim 8 , wherein the oxidizing atmosphere is air or 20% oxygen in nitrogen.10. The method according to claim 1 , wherein the gaseous flow is provided in a dry atmosphere or an atmosphere having a low humidity rate.11. The method according to claim 1 , wherein the gaseous flow treatment is carried out over a ...

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Номер записи: 35
13-06-2013 дата публикации

Semiconductor device including stepped gate electrode and fabrication method thereof

Номер: US20130146944A1
Автор: Byoung-Gue Min, Dong Min Kang, Eun Soo Nam, Ho Kyun Ahn, Hyung Sup Yoon, Jae Kyoung Mun, Jong Min Lee, Jong-Won Lim, Seong-II Kim
Принадлежит: Electronics and Telecommunications Research Institute ETRI

Disclosed are a semiconductor device including a stepped gate electrode and a method of fabricating the semiconductor device. The semiconductor device according to an exemplary embodiment of the present disclosure includes: a semiconductor substrate having a structure including a plurality of epitaxial layers and including an under-cut region formed in a part of a Schottky layer in an upper most part thereof; a cap layer, a first nitride layer and a second nitride layer sequentially formed on the semiconductor substrate to form a stepped gate insulating layer pattern; and a stepped gate electrode formed by depositing a heat-resistant metal through the gate insulating layer pattern, wherein the under-cut region includes an air-cavity formed between the gate electrode and the Schottky layer.

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Номер записи: 36
20-06-2013 дата публикации

Method for Forming Isolation Trenches in Micro-Bump Interconnect Structures and Devices Obtained Thereof

Номер: US20130154112A1
Автор: Beyne Eric, Eneman Geert, Ivankovic Andrej, Wang Wei-E, Zhang Wenqi
Принадлежит:

The disclosure is related to a substrate suitable for use in a stack of interconnected substrates, comprising: a base layer having a front side and a back side surface parallel to the plane of the base layer; one or more interconnect structures, each of said structures comprising: a via filled with an electrically conductive material, said via running through the complete thickness of the base layer, thereby forming an electrical connection between said front side and back side surfaces of the base layer, and on the back side surface of the base layer: a landing pad and a micro-bump in electrical connection with said filled via; characterized in that the backside surface of said base layer comprises one or more isolation ring trenches each of said trenches surrounding one or more of said interconnect structures. The disclosure is equally related to methods for producing said substrates and stacks of substrates. 1. A substrate suitable for use in a stack of interconnected substrates , comprising:a base layer, having a front side surface and a back side surface parallel to a plane of the base layer; and a via filled with an electrically conductive material, said via running through a complete thickness of the base layer, thereby forming an electrical connection between said front side surface and said back side surface of the base layer, and', 'on the back side surface of the base layer: a landing pad and a micro-bump in electrical connection with said filled via;, 'one or more interconnect structures, each of said interconnect structures comprisingcharacterized in that the back side surface of said base layer comprises one or more isolation ring trenches, each of said isolation ring trenches surrounding one or more of said interconnect structures.2. The substrate according to claim 1 , wherein said isolation ring trenches are filled with a material that has a suitably low Young's modulus and a suitably low Coefficient of Thermal expansion claim 1 , so as to be able ...

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Номер записи: 37
04-07-2013 дата публикации

Semiconductor wafer and insulated gate field effect transistor

Номер: US20130168735A1
Автор: Noboru Fukuhara
Принадлежит: Sumitomo Chemical Co Ltd

Provided is a technique capable of realizing an insulated gate (MIS-type) P-HEMT structure with good transistor characteristics such as an improved carrier mobility of a channel layer and a reduced influence from interface states. A semiconductor wafer includes a base wafer, a first crystalline layer, and an insulating layer. The base wafer, the first crystalline layer, and the insulating layer are stacked in the order of the base wafer, the first crystalline layer, and the insulating layer. The first crystalline layer is made of In x Ga 1-x As (0.35≦x≦0.43) that can pseudo-lattice-match with GaAs or AlGaAs. The first crystalline layer is usable as a channel layer of a field effect transistor, and the insulating layer is usable as a gate insulating layer of the field effect transistor.

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Номер записи: 38
11-07-2013 дата публикации

ANISOTROPIC AMBIPOLAR TRANSVERSE THERMOELECTRICS AND METHODS FOR MANUFACTURING THE SAME

Номер: US20130174884A1
Автор: Grayson Matthew, Zhou Chuanle
Принадлежит: Northwestern University

A transverse thermoelectric device includes a superlattice body, electrically conductive first and second contacts, and first and second thermal contacts. The superlattice body extends between opposite first and second ends along a first direction and between opposite first and second sides along a different, second direction. The superlattice body includes alternating first and second layers of crystalline materials oriented at an oblique angle relative to the first direction. The electrically conductive first contact is coupled with the first end of the superlattice and the electrically conductive second contact is coupled with the second end of the superlattice. The first thermal contact is thermally coupled to the first side of the superlattice and the second thermal contact is thermally coupled to the second side of the superlattice. A Seebeck tensor of the superlattice body is ambipolar. 1. A transverse thermoelectric device comprising:a superlattice body extending between opposite first and second ends along a first direction and between opposite first and second sides along a different, second direction, the superlattice body comprising alternating first and second layers of crystalline materials oriented at an oblique angle relative to the first direction;an electrically conductive first contact coupled with the first end of the superlattice;an electrically conductive second contact coupled with the second end of the superlattice;a first thermal contact thermally coupled to the first side of the superlattice; anda second thermal contact thermally coupled to the second side of the superlattice;wherein a Seebeck tensor of the superlattice body is ambipolar.2. The transverse thermoelectric device of claim 1 , wherein the superlattice body generates a voltage difference between the electrically conductive first contact and the electrically conductive second contact when the superlattice body is exposed to an applied temperature difference between the first ...

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Номер записи: 39
15-08-2013 дата публикации

METHOD FOR MOLECULAR ADHESION BONDING WITH COMPENSATION FOR RADIAL MISALIGNMENT

Номер: US20130210171A1
Автор: Gaudin Gweltaz
Принадлежит: SOITEC

A method for bonding a first wafer on a second wafer by molecular adhesion, where the wafers have an initial radial misalignment between them. The method includes bringing the two wafers into contact so as to initiate the propagation of a bonding wave between the two wafers while a predefined bonding curvature is imposed on at least one of the two wafers during the contacting step as a function of the initial radial misalignment. 1. A method for bonding a first wafer on a second wafer by molecular adhesion , the wafers comprising microcomponents on their respective bonding faces wherein at least some of the microcomponents of one of the wafers being intended to be aligned with at least some of the microcomponents of the other wafer , and with the microcomponents on each respective wafer having an initial radial misalignment between them , which method comprises:calculating a predefined bonding curvature as a function of the initial radial misalignment; andbringing the two wafers into contact so as to initiate the propagation of a bonding wave between the two wafers, wherein the predefined bonding curvature is imposed on at least one of the two wafers during the contacting step in order to compensate for the initial radial misalignment.2. The method according to claim 1 , wherein the second wafer is free to adapt to the predefined bonding curvature imposed on the first wafer during the propagation of the bonding wave.3. The method according to claim 1 , wherein the wafers are circular wafers of silicon with a diameter of 300 mm claim 1 , with each comprising microcomponents.4. The method according to claim 1 , which further comprises: measuring the initial radial misalignment between the two wafers to be compensated; and', 'determining a compensation radial misalignment in dependence at least in part on the initial radial misalignment between the two wafers., 'calculating the predefined bonding curvature by5. The method according to claim 1 , which further comprises; ...

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Номер записи: 40
29-08-2013 дата публикации

Method of Manufacturing a Semiconductor Device

Номер: US20130224925A1
Автор: Chang-Woo Oh, Dong-gun Park, Dong-won Kim, Ming Li, Sung-Hwan Kim
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

Semiconductor devices include a semiconductor substrate with a stack structure protruding from the semiconductor substrate and surrounded by an isolation structure. The stack structure includes an active layer pattern and a gap-filling insulation layer between the semiconductor substrate and the active layer pattern. A gate electrode extends from the isolation structure around the stack structure. The gate electrode is configured to provide a support structure for the active layer pattern. The gate electrode may be a gate electrode of a silicon on insulator (SOI) device formed on the semiconductor wafer and the semiconductor device may further include a bulk silicon device formed on the semiconductor substrate in a region of the semiconductor substrate not including the gap-filing insulation layer.

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Номер записи: 41
19-09-2013 дата публикации

Compound semiconductor device and method for manufacturing the same

Номер: US20130242618A1
Автор: Atsushi Yamada
Принадлежит: Fujitsu Ltd

The AlGaN/GaN HEMT includes, on an SiC substrate, a laminated compound semiconductor structure and a gate electrode formed on the laminated compound semiconductor structure, wherein a p-type impurity (Mg) and oxygen (O) localize in a lower region of the laminated compound semiconductor structure aligned with the gate electrode, to such a depth as to cause part of a two-dimensional electron gas generated in the laminated compound semiconductor structure to disappear.

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Номер записи: 42
26-09-2013 дата публикации

Silicon polymers, methods of polymerizing silicon compounds, and methods of forming thin films from such silicon polymers

Номер: US20130252407A1
Автор: Brent Ridley, Dmitry Karshtedt, Erik Scher, Fabio Zurcher, Joerg Rockenberger
Принадлежит: Individual

Compositions and methods for controlled polymerization and/or oligomerization of hydrosilanes compounds including those of the general formulae Si n H 2n and Si n H 2n+2 as well as alkyl- and arylsilanes, to produce soluble silicon polymers as a precursor to silicon films having low carbon content.

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Номер записи: 43
03-10-2013 дата публикации

Compound semiconductor device and method of manufacturing the same

Номер: US20130256682A1
Автор: Atsushi Yamada, Kenji Imanishi, Norikazu Nakamura, Tetsuro ISHIGURO
Принадлежит: Fujitsu Ltd

An embodiment of a method of manufacturing a compound semiconductor device includes: forming an initial layer over a substrate; forming a buffer layer over the initial layer; forming an electron transport layer and an electron supply layer over the buffer layer; and forming a gate electrode, a source electrode and a gate electrode over the electron supply layer. The forming an initial layer includes: forming a first compound semiconductor film with a flow rate ratio being a first value, the flow rate ratio being a ratio of a flow rate of a V-group element source gas to a flow rate of a III-group element source gas; and forming a second compound semiconductor film with the flow rate ratio being a second value different from the first value over the first compound semiconductor film. The method further includes forming an Fe-doped region between the buffer layer and the electron transport layer.

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Номер записи: 44
03-10-2013 дата публикации

Compound semiconductor device and method for manufacturing the same

Номер: US20130256754A1
Автор: Youichi Kamada
Принадлежит: Fujitsu Ltd

A compound semiconductor device includes: a substrate; an electron transit layer and electron supply layer formed over the substrate; a gate electrode, source electrode, and drain electrode formed over the electron supply layer; and a first Fe-doped layer provided between the substrate and the electron transit layer in a region corresponding to the position of the gate electrode in plan view, the first Fe-doped layer being doped with Fe to reduce two dimensional electron gas generated below the gate electrode.

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Номер записи: 45
03-10-2013 дата публикации

Substrate and semiconductor device

Номер: US20130256889A1
Автор: Chihiro Migita, Hiroshi Kikuchi, Yoshiaki Takemoto, Yuichi Gomi
Принадлежит: Olympus Corp

A substrate includes a base member having a predetermined thickness, and an electrode array provided in one surface in a thickness direction of the base member and having a plurality of electrodes arranged two-dimensionally in a plan view, and the electrode array includes a central portion and an incremental region provided around the central portion in the planar view and is formed so that a height of the electrodes in the incremental region gradually increase as approaching toward the central portion.

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Номер записи: 46
10-10-2013 дата публикации

Semiconductor device having vertical-type channel

Номер: US20130264635A1
Автор: Jung Woo Park
Принадлежит: SK hynix Inc

A semiconductor device includes an active region including a surface region and a first recess formed on both sides of the surface region, the active region extending along a first direction; a device isolation structure surrounding the active region; a pair of gate lines extending along the surface region of the active region in a second direction perpendicular to the first direction; a plurality of second recesses formed in the device isolation structure beneath the gate lines and including given portions of the gate lines filled into the second recesses; a plurality of first junction regions formed in the active region beneath the first recesses; and a second junction region formed in the surface region between the gate lines, wherein the second junction region defines at least two vertical-type channels below the gate line with the plurality of first junction regions.

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Номер записи: 47
17-10-2013 дата публикации

Method for Creating Semiconductor Junctions with Reduced Contact Resistance

Номер: US20130270692A1
Автор: Ballinger Clinton T., Peng Adam Z., Perera Susanthri
Принадлежит: EVIDENT TECHNOLOGIES

Embodiments of the invention relate generally to creating semiconductor junctions with reduced contact resistance. In one embodiment, the invention provides a method of forming a composition of material, the method comprising: providing at least two populations of semiconducting materials; layering the at least two populations of semiconducting materials to form at least two layers; and consolidating the at least two populations of semiconducting materials, wherein the consolidating creates an electrical connection between the at least two layers. 1. A method of forming a composition of material , the method comprising:providing at least two populations of semiconducting materials;layering the at least two populations of semiconducting materials to form at least two layers; andconsolidating the at least two populations of semiconducting materials, wherein the consolidating creates an electrical connection between the at least two layers.2. The method of claim 1 , wherein each of the at least two populations of semiconducting materials is chosen from the group consisting of: semiconductor powders claim 1 , semiconducting nanomaterials claim 1 , and solid semiconductor materials.4. The method of claim 1 , wherein at least two populations of semiconducting materials includes a population of a P type semiconductor material and a population of an N type semiconductor material.5. The method of claim 1 , wherein a single junction is created between the at least two layers of the at least two populations of semiconducting materials.6. The method of claim 1 , wherein a plurality of junctions is created between the at least two layers of the at least two populations of semiconducting materials.7. The method of claim 1 , further comprising adding at least one other material between the at least two layers of the at least two populations of semiconducting materials claim 1 , the at least one other material being chosen from the group consisting of: a metal claim 1 , a conductor ...

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Номер записи: 48
17-10-2013 дата публикации

Self-aligned wafer bonding

Номер: US20130273328A1
Автор: Dadi Setiadi, Jun Zheng
Принадлежит: SEAGATE TECHNOLOGY LLC

A wafer article includes a substrate, two or more hydrophilic areas disposed on the substrate, hydrophobic areas surrounding the hydrophilic areas, and a eutectic bonding material disposed on the substrate. A wafer apparatus including two wafers having complimentary hydrophilic regions and eutectic bonding material is disclosed and a method of forming a bonded wafer articles is disclosed.

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Номер записи: 49
17-10-2013 дата публикации

SILICON-ON-INSULATOR SUBSTRATE WITH BUILT-IN SUBSTRATE JUNCTION

Номер: US20130273715A1
Автор: Dyer Thomas W., LEE Junedong, Schepis Dominic J.
Принадлежит:

A method of forming a SOI substrate, diodes in the SOI substrate and electronic devices in the SOI substrate and an electronic device formed using the SOI substrate. The method of forming the SOI substrate includes forming an oxide layer on a silicon first substrate; ion-implanting hydrogen through the oxide layer into the first substrate, to form a fracture zone in the substrate; forming a doped dielectric bonding layer on a silicon second substrate; bonding a top surface of the bonding layer to a top surface of the oxide layer; thinning the first substrate by thermal cleaving of the first substrate along the fracture zone to form a silicon layer on the oxide layer to formed a bonded substrate; and heating the bonded substrate to drive dopant from the bonding layer into the second substrate to form a doped layer in the second substrate adjacent to the bonding layer. 1. A method , comprising:providing a silicon-on-insulator substrate, said silicon-on-insulator substrate comprising a silicon layer separated from a silicon substrate by a buried dielectric layer and including a doped layer in said substrate, said doped layer adjacent to said dielectric layer, said doped layer not formed by ion-implantation of a dopant species through said silicon layer;forming a photoresist layer on a top surface of said silicon layer;forming an opening in said photoresist layer, a region of said top surface of said silicon layer exposed in a bottom of said opening;ion implanting a dopant species into a portion of said doped layer under said opening to form an ion-implanted region in said doped layer, said photoresist layer blocking ion-implantation of said dopant species into said silicon layer, said dopant species of an opposite type than dopant in said doped layer;after said ion-implanting, removing said photoresist layer; andheating said silicon-on-insulator substrate to activate said dopant species in said ion-implanted region of said doped layer to form a doped region in said ...

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Номер записи: 50
24-10-2013 дата публикации

LASER-INITIATED EXFOLIATION OF GROUP III-NITRIDE FILMS AND APPLICATIONS FOR LAYER TRANSFER AND PATTERNING

Номер: US20130280885A1
Автор: Bayram Can, Bedell Stephen W., Sadana Devendra K., Saenger Katherine L.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A pulsed laser-initiated exfoliation method for patterning a Group III-nitride film on a growth substrate is provided. This method includes providing a Group III-nitride film a growth substrate, wherein a growth substrate/Group III-nitride film interface is present between the Group III-nitride film and the growth substrate. Next, a laser is selected that provides radiation at a wavelength at which the Group III-nitride film is transparent and the growth substrate is absorbing. The interface is then irradiated with pulsed laser radiation from the Group III-nitride film side of the growth substrate/Group III-nitride film interface to exfoliate a region of the Group III-nitride from the growth substrate. A method for transfer a Group-III nitride film from a growth substrate to a handle substrate is also provided. 1. A pulsed laser-initiated exfoliation method for patterning a Group III-nitride film on a substrate , said method comprisingproviding a Group III-nitride film on a growth substrate, wherein a growth substrate/Group III-nitride film interface is present between the Group III-nitride film and the growth substrate;selecting a laser that provides radiation at a wavelength at which the Group III-nitride film is transparent and the growth substrate is absorbing; andirradiating the interface with pulsed laser radiation from the Group III-nitride film side of the growth substrate/Group III-nitride film interface to exfoliate a region of the Group III-nitride from the growth substrate.2. The method of further comprising:forming a sacrificial protection layer on the Group III-nitride film prior to laser irradiation; andremoving said sacrificial layer after said laser irradiation.3. The method of claim 2 , wherein said sacrificial protection layer is a blanket layer covering an entirety of the Group III-nitride film.4. The method of claim 2 , wherein said sacrificial protection layer is a patterned layer disposed at least over the Group III-nitride film in areas not ...

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Номер записи: 51
07-11-2013 дата публикации

Semiconductor device and method for manufacturing semiconductor device

Номер: US20130295741A1
Автор: Takuji Matsumoto
Принадлежит: Sony Corp

A semiconductor device including a gate electrode disposed on a semiconductor substrate and source/drain regions disposed at both sides of the gate electrode, the source/drain regions being formed by implanting impurities. The source/drain regions include an epitaxial layer formed by epitaxially growing a semiconductor material having a different lattice constant from that of the semiconductor substrate in a recessed position at a side of the gate electrode, and a diffusion layer disposed in a surface layer of the semiconductor substrate.

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Номер записи: 52
21-11-2013 дата публикации

METHOD FOR MANUFACTURING SOI WAFER

Номер: US20130309842A1
Автор: Akiyama Shoji
Принадлежит: SHIN-ETSU CHEMICAL CO., LTD.

The object of the present invention is to provide a method for reducing defects, which are incurred on a surface of and inside a single-crystal silicon layer by a bonding method, by a treatment at a relatively low temperature over a relatively short duration. More specifically, the present invention relates to a method for manufacturing an SOI wafer, the method comprising the steps of forming a single-crystal silicon layer by a bonding method on a handle substrate selected from a material having a heat-resistant temperature of 800° C. or above to obtain a bonded substrate; depositing amorphous silicon on the single-crystal silicon layer of the bonded substrate; and heating the bonded substrate after the depositing at 800° C. or above. 1. A method for manufacturing an SOI wafer , comprising the steps offorming a single-crystal silicon layer by a bonding method on a handle substrate selected from a material having a heat-resistant temperature of 800° C. or above to obtain a bonded substrate;depositing amorphous silicon on the single-crystal silicon layer of the bonded substrate; andheating the bonded substrate after the depositing at 800° C. or above.2. The method for manufacturing an SOI wafer according to claim 1 , wherein the handle substrate is a quartz substrate claim 1 , and the heating temperature is below 1200° C.3. The method for manufacturing an SOI wafer according to claim 1 , wherein the handle substrate is a sapphire substrate claim 1 , and the heating temperature is below 1300° C.4. The method for manufacturing an SOI wafer according to claim 1 , wherein a material of the handle substrate is silicon claim 1 , silicon with an oxide film claim 1 , silicon carbide claim 1 , or aluminum nitride.5. The method for manufacturing an SOI wafer according to any one of to claim 1 , wherein the step of depositing comprises low pressure chemical vapor deposition claim 1 , physical vapor deposition claim 1 , or plasma-enhanced chemical vapor deposition. The present ...

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Номер записи: 53
28-11-2013 дата публикации

BONDING SYSTEM AND BONDING METHOD

Номер: US20130316516A1
Автор: DEGUCHI Masatoshi
Принадлежит:

Disclosed is a bonding system which efficiently performs a bonding of a substrate to a support substrate, thereby improving the throughput in a bonding processing. The disclosed bonding system includes a loading/unloading station and a processing station. The processing station includes: an adhesive applying device configured to apply an adhesive to the wafer; a protective agent applying device configured to apply a protective agent to the wafer, a remover applying device configured to apply a remover to the support wafer, a heat processing device configured to heat the wafer or the support wafer which is applied with at least the adhesive, the protective agent or the remover, at a predetermined temperature, a bonding device configured to bond the wafer to the support wafer through the adhesive, the protective agent and the remover, and a wafer transfer area configured to transfer the wafer, the support wafer or the bonded wafer. 1. A bonding system configured to bond a substrate to be processed to a support substrate , comprising:a processing station configured to perform a series of predetermined processing on the substrate and the support substrate, anda loading/unloading station configured to load or unload the substrate, the support substrate, or a bonded substrate comprising the substrate bonded to the support substrate to/from the processing station,wherein the processing station comprises:an adhesive supply part configured to apply an adhesive to the substrate or the support substrate;a protective agent supply part configured to apply a protective agent having a lower viscosity than the adhesive to the substrate so that the protective agent is applied to a side of the substrate rather than to the adhesive, between the substrate and the support substrate;a remover supply part configured to apply a remover having a lower viscosity than the adhesive to the substrate or the support substrate so that the remover is applied to a side of the support substrate ...

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Номер записи: 54
05-12-2013 дата публикации

Semiconductor device and method of fabricating the same

Номер: US20130320461A1
Автор: Hun-Hyeoung Leam, Hyun Namkoong, Jung-Hwan Kim, Seok-Woo Nam, Tae-hyun Kim, Tea-kwang Yu, Yong-Seok Kim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.

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Номер записи: 55
12-12-2013 дата публикации

Chemically Linked Colloidal Crystals and Methods Related Thereto

Номер: US20130327392A1
Автор: Atwater Harry A., GRUBBS Robert H., Weitekamp Raymond
Принадлежит:

Nanoparticles may be formed into colloidal crystals that are chemically linked to a substrate. In certain implementations, the nanoparticles are formed into a colloidal crystal on an initial substrate, and then brought into contact with a binding precursor capable of chemically linking the colloidal crystal to a final substrate. Reacting the binding precursor to chemically link the colloidal crystal to the final substrate chemically links the colloidal crystal to the final substrate via functional groups linked to the nanoparticles and the final substrate respectively. 1. A chemically linked colloidal crystal , comprising:a substrate bearing a first plurality of functional groups; and 'wherein the plurality of nanoparticles are arranged in a contiguous, periodic array and are chemically linked to the substrate via the first and the second plurality of functional groups.', 'a plurality of nanoparticles bearing a second plurality of functional groups,'}2. The colloidal crystal of claim 1 , wherein a functional group of the first plurality is chemically linked to a polymer matrix.3. The colloidal crystal of claim 2 , wherein the polymer matrix is an adhesion layer.4. The colloidal crystal of claim 1 , wherein the nanoparticles are disposed as a monolayer.5. The colloidal crystal of claim 1 , wherein the substrate is coated with a layer of brush polymers bearing the first plurality of functional groups.6. The colloidal crystal of claim 5 , wherein the plurality of nanoparticles are covalently bonded to the substrate through backbone bonding to the brush polymers.7. The colloidal crystal of claim 5 , wherein the brush polymers have tunable anisotropic dielectric constants.8. The colloidal crystal of claim 1 , wherein the plurality of nanoparticles are silica nanoparticles.9. The colloidal crystal of claim 1 , wherein the substrate is a solar cell.10. A method of chemically linking a colloidal crystal to a substrate claim 1 , comprising:forming a colloidal crystal on an ...

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Номер записи: 56
26-12-2013 дата публикации

Soi substrate, method for manufacturing soi substrate, and method for manufacturing semiconductor device

Номер: US20130341755A1
Автор: Kazuo Kokumai
Принадлежит: Canon Inc

An insulating portion has a first region, a second region, and a third region in the stated order from the silicon portion side, the nitrogen concentration of the first region is lower than the nitrogen concentration of the second region and the oxygen concentration of the first region, the nitrogen concentration of the third region is lower than the nitrogen concentration of the second region and the oxygen concentration of the third region, and the thickness of the first region is larger than the thickness of the third region.

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Номер записи: 57
02-01-2014 дата публикации

Integrated Circuit Having FinFETS with Different Fin Profiles

Номер: US20140001562A1
Автор: Jhon-Jhy Liaw
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

An integrated circuit is provided. The integrated circuit includes a substrate, a first FinFET device supported by the substrate, the first FinFET device having a first fin with a non-tiered fin profile, and a second FinFET supported by the substrate, the second FinFET having a second fin with a tiered fin profile.

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Номер записи: 58
02-01-2014 дата публикации

Semiconductor devices and methods of forming the same

Номер: US20140001606A1
Автор: Ha-Jin Lim, Hyung-Suk Jung, Yun-Ki Choi
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Semiconductor devices and methods of forming the semiconductor device are provided, the semiconductor devices including a first dielectric layer on a substrate, and a second dielectric layer on the first dielectric layer. The first dielectric layer has a carbon concentration lower than the second dielectric layer.

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Номер записи: 59
09-01-2014 дата публикации

Semiconductor device

Номер: US20140008615A1
Автор: Makoto Utsumi, Masayuki Iwami, Sadahiro KATOU, Takuya Kokawa
Принадлежит: ADVANCED POWER DEVICE RESEARCH ASSOCIATION

A semiconductor device includes a substrate, a channel layer that is formed above the substrate, where the channel layer is made of a first nitride series compound semiconductor, a barrier layer that is formed on the channel layer, a first electrode that is formed on the barrier layer, and a second electrode that is formed above the channel layer. Here, the barrier layer includes a block layers and a quantum level layer. The block layer is formed on the channel layer and made of a second nitride series compound semiconductor having a larger band gap energy than the first nitride series compound semiconductor, and the quantum level layer is made of a third nitride series compound semiconductor having a smaller band gap energy than the second nitride series compound semiconductor, and has a quantum level formed therein.

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Номер записи: 60
16-01-2014 дата публикации

Vertical tunneling negative differential resistance devices

Номер: US20140014903A1
Автор: Ravi Pillarisetty
Принадлежит: Individual

The present disclosure relates to the fabrication of microelectronic devices having at least one negative differential resistance device formed therein. In at least one embodiment, the negative differential resistance devices may be formed utilizing quantum wells. Embodiments of negative differential resistance devices of present description may achieve high peak drive current to enable high performance and a high peak-to-valley current ratio to enable low power dissipation and noise margins, which allows for their use in logic and/or memory integrated circuitry.

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Номер записи: 61
16-01-2014 дата публикации

METHOD FOR PERMANENTLY BONDING WAFERS

Номер: US20140017877A1
Автор: Flötgen Christoph, Hingerl Kurt, Plach Thomas, Wimplinger Markus
Принадлежит:

This invention relates to a method for bonding of a first contact surface of a first substrate to a second contact surface of a second substrate with the following steps, especially the following sequence: 1. A method for bonding of a first contact surface of a first substrate to a second contact surface of a second substrate comprising the following steps:forming a first reservoir in a surface layer on the first contact surface and a second reservoir in a surface layer on the second contact surface, the surface layers of said first and second contact surfaces comprised largely of a native oxide material,partially filling of the first and second reservoirs with a first educt or a first group of educts,forming a prebond connection by bringing the first contact surface into contact with the second contact surface for forming a prebond connection,forming a permanent bond between the first and second contact surface, said permanent bond being at least partially strengthened by a reaction of the first educt with a second educt contained in a reaction layer of the second substrate.2. The method as claimed in claim 1 , wherein formation and/or strengthening of the permanent bond takes place by diffusion of the first educt into the reaction layer.3. The method as claimed in claim 1 , wherein the formation of the permanent bond takes place at a temperature between room temperature and 200° C. claim 1 , during a maximum 12 day period.4. The method as claimed in claim 1 , wherein the permanent bond has a bond strength of greater than 1.5 J/m.5. The method as claimed in claim 1 , wherein a reaction product is formed in the reaction layer during the reaction claim 1 , said reaction product having a greater molar volume than the molar volume of the second educt.6. The method as claimed in claim 1 , wherein the reservoir is formed by plasma activation.7. The method as claimed in claim 1 , wherein the surface layer of said first contact surface is comprised of essentially of an ...

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Номер записи: 62
23-01-2014 дата публикации

High electron mobility transistors and methods of manufacturing the same

Номер: US20140021480A1
Автор: Woo-Chul JEON
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A HEMT according to example embodiments may include a first semiconductor layer, a second semiconductor layer configured to induce a 2-dimensional electron gas (2DEG) in the second semiconductor layer, an insulating mask layer on the second semiconductor layer, a depletion forming layer on one of a portion of the first semiconductor layer and a portion of the second semiconductor layer that is exposed by an opening defined by the insulating mask layer, a gate on the depletion forming layer, and a source and a drain on at least one of the first semiconductor layer and the second semiconductor layer. The source and drain may be spaced apart from the gate. The depleting forming layer may be configured to form a depletion region in the 2DEG.

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Номер записи: 63
06-02-2014 дата публикации

SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND BASE MEMBER FOR SEMICONDUCTOR DEVICE FORMATION

Номер: US20140035105A1
Автор: FUSE Kaori, KOMATSU Akira, MISAWA Hiroto
Принадлежит: KABUSHIKI KAISHA TOSHIBA

According to one embodiment, a method for manufacturing a semiconductor device includes forming semiconductor layers in a plurality of first regions on a semiconductor wafer. The plurality of first regions are separated from each other. The method includes forming elements in the semiconductor layers. The method includes bonding an insulating plate made of an inorganic material in a second region on the semiconductor wafer. The second region excludes the first regions. The method includes performing singulation for each of the semiconductor layers by cutting the semiconductor wafer and the insulating plate along a dicing line configured to pass through only the second region. 1. A method for manufacturing a semiconductor device , comprising:forming semiconductor layers in a plurality of first regions on a semiconductor wafer, the plurality of first regions being separated from each other;forming elements in the semiconductor layers;bonding an insulating plate made of an inorganic material in a second region on the semiconductor wafer, the second region excluding the first regions; andperforming singulation for each of the semiconductor layers by cutting the semiconductor wafer and the insulating plate along a dicing line configured to pass through only the second region.2. The method according to claim 1 , whereinthe semiconductor wafer is a silicon wafer,the insulating plate is a glass plate, andthe insulating plate is bonded to the semiconductor wafer by anodic bonding.3. The method according to claim 1 , wherein the semiconductor layers are formed by being epitaxially grown on the semiconductor wafer.4. A method for manufacturing a semiconductor device claim 1 , comprising:bonding an insulating plate made of an inorganic material to a semiconductor wafer;making a plurality of openings in the insulating plate;forming semiconductor layers in interiors of the openings;forming elements in the semiconductor layers; andperforming singulation for each of the ...

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Номер записи: 64
13-02-2014 дата публикации

High electron mobility transistor

Номер: US20140042449A1
Автор: Jae-joon Oh, Jai-Kwang Shin, Jong-Bong Ha, Jong-Seob Kim, Ki-Yeol Park, Sun-Kyu Hwang, Woo-Chul JEON, Young-Hwan Park
Принадлежит: SAMSUNG ELECTRONICS CO LTD

According to example embodiments, a high electron mobility transistor (HEMT) includes a channel supply layer that induces a two-dimensional electron gas (2DEG) in a channel layer, a source electrode and a drain electrode that are at sides of the channel supply layer, a depletion-forming layer that is on the channel supply layer and contacts the source electrode, a gate insulating layer on the depletion-forming layer, and a gate electrode on the gate insulating layer. The depletion-forming layer forms a depletion region in the 2DEG.

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Номер записи: 65
20-02-2014 дата публикации

Compressive stress transfer in an interlayer dielectric of a semiconductor device by providing a bi-layer of superior adhesion and internal stress

Номер: US20140048912A1
Автор: Hartmut Ruelke, Joerg Hohage, Ralf Richter
Принадлежит: Globalfoundries Inc

The present disclosure provides manufacturing techniques and semiconductor devices in which performance of P-channel transistors may be enhanced on the basis of a stress mechanism that involves the deposition of a dielectric bi-layer system. Contrary to conventional strategies, an additional pre-treatment may be performed prior to the deposition of an adhesion layer in a plasma-free process atmosphere, thereby enabling a reduced thickness of the adhesion layer and a higher internal stress level of the subsequent top layer.

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Номер записи: 66
06-03-2014 дата публикации

GAS INJECTION DEVICE AND SOLAR CELL MANUFACTURING METHOD USING THE SAME

Номер: US20140061338A1
Автор: Hwang Seong-Ryong, Kim In-ki, Lee Woo-Su, Nam Jung-Gyu, Park Sang-Cheol, Seo Seoung-Jin
Принадлежит:

A solar cell manufacturing method includes forming a first electrode on a substrate, forming a mixed metal layer on the first electrode, forming a light absorbing layer by injecting hydrogen selenide on the entire surface of the mixed metal layer using a gas injection device, and forming a second electrode on the light absorbing layer. Further, the gas injection device includes a gas pipeline, an inner gas pipe positioned in the gas pipeline and having an opening, and a plurality of injection nozzles disposed below the gas pipeline. 1. A gas injection device , comprising:a gas pipeline,an inner gas pipe within the gas pipeline, and including an opening extended through a wall of the inner gas pipe and disposed between opposing longitudinal ends of the inner gas pipe, anda plurality of injection nozzles disposed below the gas pipeline.2. The device of claim 1 , wherein:a cross-section of the inner gas pipe includes a first portion of the wall separated from a second portion of the wall, andthe opening of the inner gas pipe is formed in the first portion of the wall opposite to the injection nozzles with respect to the second portion of the wall.3. The device of claim 2 , wherein:the opening has a planar quadrangle shape,a length of the opening in a longitudinal direction of the inner gas pipe is about 20% to about 30% of an interval between a first injection nozzle adjacent to an inlet of the gas injection device, and a last injection nozzle furthest away from the inlet, anda width of the opening taken perpendicular to the longitudinal direction of the inner gas pipe is about 40% to about 45% of a diameter of the inner gas pipe.4. The device of claim 3 , wherein:the opening is positioned apart from the first injection nozzle and in a direction towards the last injection nozzle by about 40% to about 45% of the interval between the first injection nozzle and the last injection nozzle.5. The device of claim 4 , wherein:the diameter of the inner gas pipe is half of a ...

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Номер записи: 67
06-03-2014 дата публикации

Method of manufacturing vertical pin diodes

Номер: US20140061876A1
Автор: Alessio Pantellini, Marco Peroni
Принадлежит: Selex Sistemi Integrati SpA

Disclosed is a vertical PIN diode having: an N-type layer; a cathode contact formed on a first portion of the N-type layer defining a cathode region; an intrinsic layer formed on a second portion of the N-type layer; a portion of a P-type layer formed on a first portion of the intrinsic layer and defining an anode region; an anode contact formed on the portion of the P-type layer defining the anode region; and a protection structure formed on a second portion of the intrinsic layer to laterally protect the portion of the P-type layer defining the anode region from an etching intended to expose the first portion of the N-type layer defining the cathode region, wherein the protection structure is formed by implanting ions in a further portion of the P-type layer, which laterally surrounds the portion of the P-type layer defining the anode region.

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Номер записи: 68
06-03-2014 дата публикации

Method of forming a material layer in a semiconductor structure

Номер: US20140065808A1
Автор: Boris Bayha, Carsten Grass, Martin Trentzsch, Peter Krottenthaler
Принадлежит: Globalfoundries Inc

A method comprises depositing a first portion of a first material layer on a semiconductor structure. A first run of a post-treatment process is performed for modifying at least the first portion of the first material layer. After the first run of the post-treatment process, a second portion of the first material layer is deposited. The second portion is formed of substantially the same material as the first portion. After the deposition of the second portion of the first material layer, a second run of the post-treatment process is performed for modifying at least the second portion of the first material layer.

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Номер записи: 69
27-03-2014 дата публикации

Semiconductor device and method for fabricating the same

Номер: US20140084332A1
Автор: Nam-young Lee
Принадлежит: SAMSUNG ELECTRONICS CO LTD

According to example embodiments of inventive concepts: a semiconductor device includes: first and second trench gates extending long in one direction in a substrate; third and fourth trench gates in the substrate, the third and fourth trench gates connecting the first and second trench gates with each other; a first region defined in the substrate by the first to fourth trench gates and surrounded by the first to fourth trench gates; and a second region and a third region defined in the substrate. The second region is in surface contact with the first region. The third region is in point contact with the first region. The first region includes a first high-voltage semiconductor device including a body of a first conduction type and an emitter of a second conduction type in the body. Floating wells of the first conduction type are in the second region and the third region.

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Номер записи: 70
27-03-2014 дата публикации

Compound semiconductor device and method of manufacturing the same

Номер: US20140084339A1
Автор: Masato Nishimori, Tadahiro Imada, Toshihiro Ohki
Принадлежит: Fujitsu Ltd

A compound semiconductor device includes as compound semiconductor layers: a first layer; a second layer larger in band gap than the first layer, formed above the first layer; a third layer having a p-type conductivity type, formed above the second layer; a gate electrode formed above the second layer via the third layer; a fourth layer larger in band gap than the second layer, formed to be in contact with the third layer above the second layer; and a fifth layer smaller in band gap than the fourth layer, formed to be in contact with the third layer above the fourth layer.

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Номер записи: 71
27-03-2014 дата публикации

Power device and method for manufacturing the same

Номер: US20140087529A1
Автор: Jae Hoon Lee
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Provided is a power device. The power device may include a two-dimensional electron gas (2-DEG) layer in a portion corresponding to a gate electrode pattern since a second nitride layer is further formed on a lower portion of the gate electrode pattern after a first nitride layer is formed and thus, may be capable of performing a normally-OFF operation. Accordingly, the power device may adjust generation of the 2-DEG layer based on a voltage of a gate, and may reduce power consumption. The power device may regrow only the portion corresponding to the gate electrode pattern or may etch a portion excluding the portion corresponding to the gate electrode pattern and thus, a recess process may be omissible, a reproducibility of the power device may be secured, and a manufacturing process may be simplified.

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Номер записи: 72
03-04-2014 дата публикации

Semiconductor device and method for manufacturing a semiconductor device

Номер: US20140091320A1
Автор: Atsushi Yamada, Junji Kotani, Kenji Imanishi, Norikazu Nakamura, Tetsuro ISHIGURO
Принадлежит: Fujitsu Ltd

A semiconductor device includes a first semiconductor layer formed on a substrate, a second semiconductor layer formed on the first semiconductor layer, a third semiconductor layer and a fourth semiconductor layer formed on the second semiconductor layer, a gate electrode formed on the third semiconductor layer, and a source electrode and a drain electrode contacting and formed on the fourth semiconductor layer, wherein the third semiconductor layer is formed of a semiconductor material for attaining p-type on an area just under the gate electrode, and a concentration of silicon in the fourth semiconductor layer is higher than that in the second semiconductor layer.

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Номер записи: 73
03-04-2014 дата публикации

Semiconductor device

Номер: US20140091359A1
Автор: Eiko OTSUKI, Koji Sadamatsu, Yasuhiro Yoshiura
Принадлежит: Mitsubishi Electric Corp

A semiconductor device includes a semiconductor substrate having one main surface in which an anode of a diode is formed. At a distance from the outer periphery of the anode, a guard ring is formed to surround the anode. The anode includes a p + -type diffusion region, a p − -type region, and an anode electrode. The p − -type region is formed as a region of relatively high electrical resistance sandwiched between the p + -type diffusion regions.

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Номер записи: 74
10-04-2014 дата публикации

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

Номер: US20140097519A1
Автор: CHO Heung-Jae, HWANG Eui-Seong, KIM Tae-Yoon, YOON Kyu-Hyung
Принадлежит: SK HYNIX INC.

A method for fabricating a semiconductor device includes forming a first semiconductor wafer, in which a circuit part and a first bonding layer are stacked, on a first semiconductor substrate, forming a second semiconductor wafer, which includes structures and an insulating layer for gap-filling between the structures, on a second semiconductor substrate, the structures including a pillar and bit lines stacked therein, bonding the first semiconductor wafer with the second semiconductor wafer so that the first bonding layer faces the insulating layer, and separating the second semiconductor substrate from the bonded second semiconductor wafer. 1. A method for fabricating a semiconductor device , comprising:forming a first semiconductor wafer, in which a circuit part and a first bonding layer are stacked, on a first semiconductor substrate;forming a second semiconductor wafer, which includes structures and an insulating layer for gap-filling between the structures, on a second semiconductor substrate, the structures including a pillar and bit lines stacked therein;bonding the first semiconductor wafer with the second semiconductor wafer so that the first bonding layer faces the insulating layer; andseparating the second semiconductor substrate from the bonded second semiconductor wafer.2. The method of claim 1 , wherein claim 1 , in the forming of the second semiconductor wafer claim 1 , forming of the structures including the pillar and the bit lines stacked therein comprises:stacking a first silicon layer and a second silicon layer on the second semiconductor substrate;stacking a conductive layer and a hard mask layer on the second silicon layer;forming the bit lines by etching the hard mask layer and the conductive layer;etching the second silicon layer and the first silicon layer below the bit lines;forming a spacer at sidewalls of the etched second silicon layer, the etched first silicon layer and the bit lines;etching the second semiconductor substrate by a ...

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Номер записи: 75
10-04-2014 дата публикации

COMPRESSIVELY STRAINED SOI SUBSTRATE

Номер: US20140099776A1
Автор: Cheng Kangguo, Doris Bruce B., Khakifirooz Ali, SHAHIDI Ghavam
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A method of forming a strained silicon-on-insulator includes forming a first wafer having a compressively strained active semiconductor layer, forming a second wafer having an insulation layer formed above a bulk semiconductor layer, and bonding the compressively strained active semiconductor layer of the first wafer to the insulation layer of the second wafer. 1. A method of forming a strained silicon-on-insulator (SOI) substrate , comprising:forming a first wafer having a compressively strained active semiconductor layer, a relaxed silicon carbon (Si:C), and a compressed etch stop layer interposed between the compressively strained active semiconductor layer and the relaxed silicon carbon (Si:C) layer;forming a second wafer having an insulation layer formed above a bulk semiconductor layer;bonding the compressively strained active semiconductor layer to the insulation layer; andselectively removing the bulk semiconductor layer, the relaxed silicon carbon (Si:C) layer and the etch stop layer after the bonding operation to expose the compressively strained active layer such that the compressively strained active semiconductor layer is formed directly on the insulation layer,wherein the compressively strained active semiconductor layer is silicon.2. The method of claim 1 , wherein the forming the first wafer further comprises forming the relaxed silicon carbon (Si:C) layer having a first lattice constant on a semiconductor substrate layer.3. The method of claim 2 , wherein forming the relaxed silicon carbon (Si:C) layer further comprises forming the relaxed silicon carbon (Si:C) layer on the semiconductor substrate layer having a second lattice constant greater than the first lattice constant.4. The method of claim 2 , wherein the forming the first wafer further comprises forming the etch stop layer having a third lattice constant on an upper surface of the relaxed silicon carbon (Si:C) layer to lattice match the third lattice constant to the first lattice constant.5 ...

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Номер записи: 76
13-01-2022 дата публикации

Apparatus and Methods for Wafer to Wafer Bonding

Номер: US20220013416A1
Автор: Ip Nathan
Принадлежит:

A method includes having a first wafer bonding recipe and a model of a wafer bonding process, the model comprising an input indicative of a physical parameter of a first wafer to be bonded to a second wafer and configured to output a wafer bonding recipe based on the physical parameter of the first wafer; obtaining measurements of the first wafer to obtain the physical parameter of the first wafer; generating, by the model, the first wafer bonding recipe based on the physical parameter of the first wafer; and bonding the first wafer to the second wafer in accordance with the first wafer bonding recipe to produce a first post-bond wafer. 1. A method comprising:having a first wafer bonding recipe and a model of a wafer bonding process, the model comprising an input indicative of a physical parameter of a first wafer to be bonded to a second wafer and configured to output a wafer bonding recipe based, at least in part, on the physical parameter of the first wafer, the physical parameter of the first wafer representing information relating to topographical features of the first wafer;obtaining measurements of the first wafer to obtain the physical parameter of the first wafer;generating, by the model, the first wafer bonding recipe based, at least in part, on the physical parameter of the first wafer; andbonding the first wafer to the second wafer in accordance with the first wafer bonding recipe to produce a first post-bond wafer.2. The method of claim 1 , further comprising annealing the first post-bond wafer to produce a fusion bonded wafer.3. The method of claim 1 , wherein the physical parameter of the first wafer comprises out-of-plane distortions of the first wafer.4. The method of claim 1 , further comprising deriving the model of the wafer bonding process comprising:obtaining measurements of a third wafer and a fourth wafer to obtain a physical parameter of the third wafer and a physical parameter of the fourth wafer;simulating wafer bonding of the third wafer ...

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Номер записи: 77
07-01-2016 дата публикации

High electron mobility transistor structure and method of making the same

Номер: US20160005823A1
Автор: Chen-Ju YU, Chih-Wen Hsiung, Chun-Wei Hsu, Fu-Chih Yang, Fu-Wei YAO, Jiun-Lei Jerry Yu, King-Yuen Wong
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A transistor includes a first layer over a substrate. The transistor also includes a second layer over the first layer. The transistor further includes a carrier channel layer at an interface of the first layer and the second layer. The transistor additionally includes a gate structure, a drain, and a source over the second layer. The transistor also includes a passivation material in the second layer between an edge of the gate structure and an edge of the drain in a top-side view. The carrier channel layer has a smaller surface area than the first layer between the edge of the gate structure and the edge of the drain in the top-side view.

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Номер записи: 78
07-01-2021 дата публикации

Method of forming and transferring thin film using soi wafer and heat treatment process

Номер: US20210005457A1
Автор: Chang Hwan Choi, Hoon Hee HAN, Yu Rim JEON
Принадлежит: Industry University Cooperation Foundation IUCF HYU

The present invention relates to a method of forming and transferring a thin film. The method of forming and transferring a thin film according to one embodiment may include a step of bonding a carrier wafer coated with a polymer bonding material to the top of a silicon-on-insulator (SOI) wafer formed by sequentially laminating a backside silicon layer, a buried oxide layer, and a silicon layer; a step of etching the backside silicon layer using the buried oxide layer as an etching barrier, and then selectively etching the buried oxide layer; a step of separating the carrier wafer from the polymer bonding material, and bonding a target wafer including an oxide layer to the bottom of the silicon layer through direct bonding; and a step of transferring the silicon layer to the top of the target wafer including the oxide layer by removing the polymer bonding material.

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Номер записи: 79
03-01-2019 дата публикации

Power semiconductor device and method for manufacturing power semiconductor device

Номер: US20190006265A1
Автор: Dai Nakajima, Masaru Fuku, Noriyuki Besshi, Takayuki Yamada, Yuya Muramatsu
Принадлежит: Mitsubishi Electric Corp

This power semiconductor device is provided with: a substrate; and a semiconductor element which is bonded onto the substrate using a sinterable metal bonding material. The semiconductor element comprises: a base; a first conductive layer that is provided on a first surface of the base, said first surface being on the substrate side; and a second conductive layer that is provided on a second surface of the base, said second surface being on the reverse side of the first surface. The thickness of the first conductive layer is from 0.5 times to 2.0 times (inclusive) the thickness of the second conductive layer.

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Номер записи: 80
03-01-2019 дата публикации

METHOD FOR PERMANENT BONDING OF WAFERS

Номер: US20190006313A1
Автор: Flötgen Christoph, Hingerl Kurt, Plach Thomas, Wimplinger Markus
Принадлежит: EV Group E. Thallner GmbH

A method for bonding of a first contact surface of a first substrate to a second contact surface of a second substrate according to the following steps: forming a reservoir in a surface layer on the first contact surface, at least partially filling the reservoir with a first educt or a first group of educts, contacting the first contact surface with the second contact surface for formation of a prebond connection, and forming a permanent bond between the first and second contact surface, at least partially strengthened by the reaction of the first educt with a second educt contained in a reaction layer of the second substrate. 1. A method for bonding of a first contact surface of a first substrate to a second contact surface of a second substrate , said method comprising:{'sub': 2', '2', '2, 'forming a reservoir in a surface layer of the first contact surface by exposing the first contact surface to Ngas and/or Ogas and/or Are gas and/or a forming gas comprising 95% Ar and 5% H;'}at least partially filling the reservoir with one or more first educts;forming a prebond connection by contacting the first contact surface with the second contact surface; andforming a permanent bond between the first and second contact surface, said permanent bond being at least partially strengthened by reaction of the first educt with a second educt contained in a reaction layer of the second substrate.2. The method as claimed in claim 1 , wherein the formation and/or the strengthening of the permanent bond takes place by diffusion of the first educt into the reaction layer of the second substrate.3. The method as claimed in claim 1 , wherein the formation of the permanent bond takes place at a temperature between room temperature and 200° C. in an hour or less.4. The method as claimed in claim 1 , wherein the permanent bond is an irreversible bond having a bond strength of greater than 1.5 J/m.5. The method as claimed in claim 1 , wherein claim 1 , during the reaction of the first ...

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Номер записи: 81
27-01-2022 дата публикации

Bonding wafer structure and method of manufacturing the same

Номер: US20220028977A1
Автор: Hung-Chang Lo, Wei Li Wu, Ying-Ru Shih
Принадлежит: GlobalWafers Co Ltd

A bonding wafer structure includes a support substrate, a bonding layer, and a silicon carbide (SiC) layer. The bonding layer is formed on a surface of the support substrate, and the SiC layer is bonded onto the bonding layer, in which a carbon surface of the SiC layer is in direct contact with the bonding layer. The SiC layer has a basal plane dislocation (BPD) of 1,000 ea/cm 2 to 20,000 ea/cm 2 , a total thickness variation (TTV) greater than that of the support substrate, and a diameter equal to or less than that of the support substrate. The bonding wafer structure has a TTV of less than 10 μm, a bow of less than 30 μm, and a warp of less than 60 μm.

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Номер записи: 82
09-01-2020 дата публикации

Wafer bonding apparatus and wafer bonding system using the same

Номер: US20200013643A1
Автор: Jun-Hyung Kim, Sung-Hyup Kim, Tae-Yeong Kim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A wafer bonding apparatus includes a first bonding chuck to fix a first wafer on a first surface thereof, a second bonding chuck to fix a second wafer on a second surface thereof facing the first surface, a bonding initiation member at a center of the first bonding chuck to push the first wafer towards the second surface, and a membrane member including a protrusion protruding from a center portion of the second surface towards the first surface, and a planar portion defining the protrusion on an outer region surrounding the center portion.

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Номер записи: 83
18-01-2018 дата публикации

METAL-METAL DIRECT BONDING METHOD

Номер: US20180019124A1
Автор: GONDCHARTON Paul, Imbert Bruno, Moriceau Hubert
Принадлежит:

A method for assembling a first substrate and a second substrate by metal-metal direct bonding, includes providing a first layer of a metal at the surface of the first substrate and a second layer of the metal at the surface of the second substrate, the first and second metal layers having a tensile stress (σ) between 30% and 100% of the tensile yield strength (σ) of the metal; assembling the first and second substrates at a bonding interface by directly contacting the first and second tensile stressed metal layers; and subjecting the assembly of the first and second substrates to a stabilization annealing at a temperature lower than or equal to a temperature threshold beyond which the first and second tensile stressed metal layers are plastically compressively deformed. 1. A method for assembling a first substrate and a second substrate by a metal-metal direct bonding , comprising:providing a first layer of a metal at a surface of the first substrate and a second layer of said metal at a surface of the second substrate, the first and second metal layers having a tensile stress comprised between 30% and 100% of the tensile yield strength of said metal;assembling the first and second substrates at a bonding interface by directly contacting the first and second metal layers;subjecting the assembly of the first and second substrates to a stabilization annealing at a temperature lower than or equal to a temperature threshold beyond which the first and second tensile stressed metal layers are plastically compressively deformed.2. The method according to claim 1 , comprising calculating said temperature threshold from the tensile stress of the first and second metal layers and the thermo-elastic coefficient of said metal.3. The method according to claim 1 , wherein the providing comprises depositing the first metal layer onto a face of the first substrate and the second metal layer onto a face of the second substrate.4. The method according to claim 3 , wherein the ...

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Номер записи: 84
18-01-2018 дата публикации

Display driver semiconductor device and manufacturing method thereof

Номер: US20180019262A1
Автор: Bo Seok OH, Hee Hwan JI, Jeong Hyeon Park
Принадлежит: MagnaChip Semiconductor Ltd

A display driver semiconductor device includes a high voltage well region being formed on a substrate, a first semiconductor device, a second semiconductor device, and a third semiconductor device. The first semiconductor device is formed on the high voltage well region and includes a first gate insulating layer. The second semiconductor device is formed adjacent to the first semiconductor device and includes a second gate insulating layer. The third semiconductor device is formed adjacent to the second semiconductor device and includes a third gate insulating layer. The first insulating layer may be formed using a chemical vapor deposition (CVD) process and the second insulating layer is formed using a thermal oxide process.

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Номер записи: 85
17-01-2019 дата публикации

DEVICE AND METHOD FOR BONDING OF SUBSTRATES

Номер: US20190019677A1
Автор: Kurz Florian, Plach Thomas, SÜSS Jürgen Markus, Wagenleitner Thomas
Принадлежит: EV Group E. Thallner GmbH

A method for bonding a first substrate with a second substrate at respective contact faces of the substrates with the following steps: holding the first substrate to a first sample holder surface of a first sample holder with a holding force Fand holding the second substrate to a second sample holder surface of a second sample holder with a holding force F; contacting the contact faces at a bond initiation point and heating at least the second sample holder surface to a heating temperature T; bonding of the first substrate with the second substrate along a bonding wave running from the bond initiation point to the side edges of the substrates, wherein the heating temperature Tis reduced at the second sample holder surface during the bonding. 1. A device for bonding a first substrate with a second substrate , comprising:a measuring means configured to detect a bonding wave to enable control of the bonding wave.2. The device according to claim 1 , wherein the measuring means is further configured to detect a back side of the first substrate.3. The device according to claim 1 , wherein the measuring means is further configured to measure the bonding wave.4. The device according to claim 1 , further comprising:{'sub': 'H1', 'a first substrate holder configured to hold the first substrate with a first holding force F; and'}{'sub': 'H2', 'a second substrate holder configured to hold the second substrate with a second holding force F,'}{'sub': H1', 'H2, 'wherein at least one of the first and second holding forces Fand Fis reduced to 0 to control the bonding wave.'}5. The device according to claim 1 , wherein the measuring means is further configured to detect a state of the bonding wave and an advance of the bonding wave.6. The device according to claim 1 , wherein the measuring means is further configured to detect at least one of a position of the bonding wave and a size of a bonded area.7. The device according to claim 1 , wherein the measuring means comprises at least ...

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Номер записи: 86
17-01-2019 дата публикации

Device and method for bonding of substrates

Номер: US20190019678A1
Автор: Jürgen Markus SÜSS, Thomas PLACH, Thomas Wagenleitner
Принадлежит: EV Group E Thallner GmbH

A method and a corresponding device for bonding a first substrate with a second substrate at mutually facing contact faces of the substrates. The method includes holding of the first substrate to a first holding surface of a first holding device and holding of the second substrate to a second holding surface of a second holding device. A change in curvature of the contact face of the first substrate and/or a change in curvature of the contact face of the second substrate are controlled during the bonding.

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Номер записи: 87
16-01-2020 дата публикации

ELECTRONIC DEVICES FORMED IN A CAVITY BETWEEN SUBSTRATES

Номер: US20200021269A1
Автор: Takano Atsushi
Принадлежит:

An electronic device includes a first substrate and a second substrate. A side wall joins the first substrate to the second substrate. The side wall includes a first alloy layer of a first metal and a second metal bonded directly to an upper surface of the first substrate and a second alloy layer of the first metal and a third metal disposed on top of the first alloy layer and bonded directly to a lower surface of the second substrate, the second metal and the third metal being different from each other and from the first metal. An electronic circuit is disposed on the lower surface of the second substrate within a cavity defined by the lower surface of the first substrate, the upper surface of the second substrate, and the side wall. 1. An electronic device comprising:a first substrate and a second substrate;a side wall joining the first substrate to the second substrate, the side wall including a first alloy layer of a first metal and a second metal bonded directly to an upper surface of the first substrate and a second alloy layer of the first metal and a third metal disposed on top of the first alloy layer and bonded directly to a lower surface of the second substrate, the second metal and the third metal being different from each other and from the first metal; andan electronic circuit disposed on the lower surface of the second substrate within a cavity defined by the lower surface of the first substrate, the upper surface of the second substrate, and the side wall.2. The electronic device of wherein the side wall is disposed about peripheries of the first and second substrates.3. The electronic device of wherein the second substrate includes a piezoelectric body.4. The electronic device of wherein the electronic circuit includes at least one of a film bulk acoustic resonator claim 3 , a bulk acoustic wave element claim 3 , a solidly mounted resonator claim 3 , and a surface acoustic wave element.5. The electronic device of wherein the first metal has a ...

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Номер записи: 88
25-01-2018 дата публикации

Monolithic Integration of Semiconductor Materials

Номер: US20180025911A1
Автор: Collaert Nadine, Rooyackers Rita, Walke Amey Mahadev
Принадлежит: IMEC VZW

A method for forming a semiconductor structure by bonding a donor substrate to a carrier substrate is disclosed herein. The donor substrate may include a plurality of semiconductor layers epitaxially grown on top of one another in, and optionally above, a trench of the donor substrate. The carrier substrate may include a first semiconductor device thereon. The method may include removing at least part of the donor substrate in such a way as to expose a semiconductor layer grown on the bottom of the trench, removing at least part of the exposed semiconductor layer, thereby modifying the plurality of semiconductor layers, and forming a second semiconductor device from the modified plurality of semiconductor layers. 1. A method for forming a semiconductor structure , comprising: (i) opens toward a top of the donor substrate,', '(ii) is defined by a monocrystalline bottom and non-crystalline sidewalls, and', '(iii) comprises a width in the range of 10 nm to 10 μm;, 'providing a donor substrate having a trench therein and having a plurality of semiconductor layers epitaxially grown on top of one another on the donor substrate in such a way that at least a first semiconductor layer of the plurality of semiconductor layers is present in the trench, wherein the trench (i) a semiconductor substrate at a bottom of the carrier substrate,', '(ii) a first semiconductor device on the semiconductor substrate, and', '(iii) electrical contacts to the first semiconductor device at a top of the carrier substrate;, 'providing a carrier substrate comprisingbonding the donor substrate to the carrier substrate with the top of the donor substrate and the top of the carrier substrate facing each other;removing at least part of the donor substrate in such a way as to expose the first semiconductor layer, wherein the first semiconductor layer is grown on the monocrystalline bottom of the trench; andremoving at least part of the exposed first semiconductor layer, thereby modifying the ...

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Номер записи: 89
25-01-2018 дата публикации

METHOD FOR MANUFACTURING TRANSISTOR AND DISPLAY DEVICE

Номер: US20180025918A1
Автор: HAMOCHI Takashi, HOSAKA Yasuharu, OBONAI Toshimitsu, Yamazaki Shunpei
Принадлежит:

A transistor with high productivity and a method for manufacturing the transistor are provided. In the formation of a bottom-gate transistor using a metal oxide layer as a semiconductor layer where a channel is formed, a gate insulating layer including silicon nitride is formed, and then plasma treatment is successively performed in the same treatment chamber under an atmosphere containing oxygen. After that, the metal oxide layer is formed. 1. A method for manufacturing a transistor , comprising:a first step comprising a step of forming a gate electrode;a second step comprising a step of forming a gate insulating layer over the gate electrode;a third step comprising a step of exposing a surface of the gate insulating layer to an atmosphere containing an oxygen ion or an oxygen radical;a fourth step comprising a step of forming a metal oxide layer over the gate insulating layer; anda fifth step comprising a step of forming a source electrode and a drain electrode over the metal oxide layer,wherein the gate insulating layer comprises silicon and nitrogen, andwherein the second step and the third step are performed in one treatment chamber.2. The method for manufacturing a transistor according to claim 1 , wherein the third step is plasma treatment performed under an atmosphere containing oxygen.3. The method for manufacturing a transistor according to claim 1 , wherein the metal oxide layer comprises an oxide semiconductor.4. The method for manufacturing a transistor according to claim 1 , wherein the metal oxide layer comprises at least one of indium and zinc.5. The method for manufacturing a transistor according to claim 1 , wherein the metal oxide layer comprises a metal matrix composite.6. A method for manufacturing a transistor claim 1 , comprising:a first step comprising a step of forming a gate electrode;a second step comprising a step of forming a gate insulating layer over the gate electrode;a third step comprising a step of exposing a surface of the gate ...

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Номер записи: 90
10-02-2022 дата публикации

Substrate processing apparatus and substrate processing method

Номер: US20220044935A1
Автор: Hirotoshi Mori, Takeshi Tamura
Принадлежит: Tokyo Electron Ltd

A substrate processing apparatus configured to process a substrate includes a holder configured to hold, in a combined substrate in which a first substrate and a second substrate are bonded to each other, the second substrate; and a modifying device configured to form, to an inside of the first substrate held by the holder, a peripheral modification layer by radiating laser light for periphery along a boundary between a peripheral portion of the first substrate as a removing target and a central portion thereof, and, also, configured to form an internal modification layer by radiating laser light for internal surface along a plane direction of the first substrate. The modifying device switches the laser light for periphery and the laser light for internal surface by adjusting at least a shape or a number of the laser light for periphery and the laser light for internal surface.

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Номер записи: 91
10-02-2022 дата публикации

SEMICONDUCTOR DEVICES

Номер: US20220045055A1
Автор: JUNG Soonmoon, Kim Sungmin
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A semiconductor device includes a first transistor, a division pattern, and a second transistor sequentially stacked on a substrate. The first transistor includes a first gate structure, a first source/drain layer at each of opposite sides of the first gate structure, and first semiconductor patterns spaced apart from each other in a vertical direction. Each of the first semiconductor patterns extends through the first gate structure and contacts the first source/drain layer. The division pattern includes an insulating material. The second transistor includes a second gate structure, a second source/drain layer at each of opposite sides of the second gate structure, and second semiconductor patterns spaced apart from each other in the vertical direction. Each of the second semiconductor patterns extends through the second gate structure and contacts the second source/drain layer. The first source/drain layer does not directly contact the second source/drain layer. 1. A method of manufacturing a semiconductor device , the method comprising:forming a line stack structure on a first substrate, the line stack structure including a first line, a division pattern and a second line sequentially stacked in a vertical direction perpendicular to an upper surface of the first substrate, the first line including a first sacrificial line and a first semiconductor line alternately slacked in the vertical direction, and the second line including a second sacrificial line and a semiconductor line alternately stacked in the vertical direction;forming a first dummy gate structure on the first substrate to partially cover the line stack structure;forming a first source/drain laver on a portion of the division pattern adjacent to the first dummy gate structure;forming a first insulating interlayer on the first substrate to cover the first dummy gate structure, the line stack structure and the first source/drain layer;overturning the first substrate and bonding the first insulating ...

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Номер записи: 92
29-01-2015 дата публикации

MECHANISMS FOR CLEANING SUBSTRATE SURFACE FOR HYBRID BONDING

Номер: US20150031189A1
Автор: Chen Sheng-Chau, Chen Xiao-Meng, HUANG Chih-Hui, Tsai Chia-Shiung, Tu Yeur-Luen, Wu Cheng-Ta
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

Embodiments of mechanisms for cleaning a surface of a semiconductor wafer for a hybrid bonding are provided. The method for cleaning a surface of a semiconductor wafer for a hybrid bonding includes providing a semiconductor wafer, and the semiconductor wafer has a conductive pad embedded in an insulating layer. The method also includes performing a plasma process to a surface of the semiconductor wafer, and metal oxide is formed on a surface of the conductive structure. The method further includes performing a cleaning process using a cleaning solution to perform a reduction reaction with the metal oxide, such that metal-hydrogen bonds are formed on the surface of the conductive structure. The method further includes transferring the semiconductor wafer to a bonding chamber under vacuum for hybrid bonding. Embodiments of mechanisms for a hybrid bonding and a integrated system are also provided. 1. A method for cleaning a surface of a semiconductor wafer for hybrid bonding , comprising:providing a semiconductor wafer, wherein the semiconductor wafer has a conductive pad embedded in an insulating layer and a metal oxide layer formed on a surface of the conductive pad;performing a plasma process to a surface of the semiconductor wafer;performing a cleaning process using a cleaning solution to the surface of the semiconductor wafer after the plasma process, wherein the metal oxide layer is reduced and metal-hydrogen bonds are formed on the surface of the conductive pad; andtransferring the semiconductor wafer to a bonding chamber under vacuum for hybrid bonding.2. The method as claimed in claim 1 , wherein the cleaning solution comprises citric acid claim 1 , hydrofluoric acid (HF) claim 1 , or tetramethylammonium hydroxide (TMAH).3. The method as claimed in claim 2 , wherein the citric acid has a concentration in a range from about 0.25% to about 10%.4. The method as claimed in claim 2 , wherein the hydrofluoric acid (HF) has a concentration in a range from about 0.1% ...

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Номер записи: 93
05-02-2015 дата публикации

Electronic modules and methods of making electronic modules

Номер: US20150035133A1
Автор: Wing Shenq Wong
Принадлежит: STMICROELECTRONICS PTE LTD

A method is described for making electronic modules includes molding onto a substrate panel a matrix panel defining a plurality of cavities, attaching semiconductor die to the substrate panel in respective cavities of the molded matrix panel, electrically connecting the semiconductor die to the substrate panel, affixing a cover to the molded matrix panel to form an electronic module assembly, mounting the electronic module assembly on a carrier tape, and separating the electronic module assembly into individual electronic modules. An electronic module is described which includes a substrate, a wall member molded onto the substrate, the molded wall member defining a cavity, at least one semiconductor die attached to the substrate in the cavity and electrically connected to the substrate, and a cover affixed to the molded wall member over the cavity.

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Номер записи: 94
02-02-2017 дата публикации

Semiconductor device and method of fabricating the same

Номер: US20170033225A1
Автор: Hun-Hyeoung Leam, Hyun Namkoong, Jung-Hwan Kim, Seok-Woo Nam, Tae-hyun Kim, Tea-kwang Yu, Yong-Seok Kim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.

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Номер записи: 95
01-02-2018 дата публикации

SEMICONDUCTOR DEVICE, RELATED MANUFACTURING METHOD, AND RELATED ELECTRONIC DEVICE

Номер: US20180033624A1
Автор: LIU GUOAN, XU WEI
Принадлежит:

A method for manufacturing a semiconductor device may include the following steps: preparing a first substrate; providing a first conductor, which is configured to electrically connect two elements associated with the first substrate; providing a second conductor on the first substrate, wherein the second conductor is electrically connected to the first conductor; preparing a second substrate; providing a third conductor, which is configured to electrically connect two elements associated with the second substrate; providing a fourth conductor on the second substrate, wherein the fourth conductor is electrically connected to the third conductor; providing a fifth conductor on the fourth conductor; and combining the fifth conductor with the second conductor through eutectic bonding. 1. A semiconductor device comprising:a first substrate;a second substrate, which overlaps the first substrate;a first conductor, which is configured to electrically connect two elements associated with the first substrate;a second conductor, which is positioned on the first substrate and is electrically connected to the first conductor;a third conductor, which is configured to electrically connect two elements associated with the second substrate;a fourth conductor which is positioned on the second substrate and is electrically connected to the third conductor; anda fifth conductor, which directly contacts each of the second conductor and the fourth conductor and is positioned between the second conductor and the fourth conductor.2. The semiconductor device of claim 1 , wherein a material of the fifth conductor is different from each of a material of the second conductor and a material of the fourth conductor.3. The semiconductor device of claim 2 , wherein the material of the second conductor is identical to the material of the fourth conductor.4. The semiconductor device of comprising:a sixth conductor, which is positioned on the first substrate, wherein a material of the sixth ...

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Номер записи: 96
01-02-2018 дата публикации

FINFETs WITH HIGH QUALITY SOURCE/DRAIN STRUCTURES

Номер: US20180033857A1
Автор: Cheng Kangguo, Khakifirooz Ali, Reznicek Alexander, Surisetty Charan V. V. S.
Принадлежит:

A semiconductor structure is provided that includes a silicon germanium alloy fin located on a portion of a topmost surface of an insulator layer. A functional gate structure straddles a portion of the silicon germanium alloy fin and is located on other portions of the topmost surface of the insulator layer. A source structure is located on one side of the functional gate structure and a drain structure is located on another side of the functional gate structure. The source structure and the drain structure surround the other portions of the silicon germanium alloy fin and are located on a germanium graded silicon-containing region that is present at a footprint of the other portions of the silicon germanium alloy fin. 1. A method of forming a semiconductor structure , the method comprising:providing a silicon germanium alloy structure extending upwards from a surface of a silicon layer, the silicon layer is present on a topmost surface of an insulator layer;diffusing germanium from the silicon germanium alloy structure into the silicon layer to convert a portion of the silicon layer that is located directly beneath the silicon germanium alloy structure into a silicon germanium alloy base portion, while also converting other portions of the silicon layer that are located adjacent the silicon germanium alloy base portion into a germanium graded silicon-containing region;forming a fin protective structure on a portion of the silicon germanium alloy structure;epitaxially growing a source structure on one side of the fin protective structure and a drain structure on another side of the fin protective structure, wherein the source structure and the drain structure surround exposed portions of the silicon germanium alloy structure and are located on each germanium graded silicon-containing region that is present at the footprint of the silicon germanium alloy structure;removing a portion of the fin protective structure to expose a gate region;removing each of the ...

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Номер записи: 97
04-02-2021 дата публикации

Adhesive sheet for temporary attachment and method for producing semiconductor device using the same

Номер: US20210032501A1
Автор: Ji Ho HAN, Kwang Joo Lee, Mi Jang, Sera Kim
Принадлежит: LG Chem Ltd

The present disclosure relates to an adhesive sheet for temporary attachment which is excellent in heat resistance and can realize sufficient adhesive strength even when being subjected to a high temperature process during the semiconductor production process, and can exhibit a sufficient reduction in adhesive strength due to photocuring in a peeling step, and a method for producing a semiconductor device using the same.

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Номер записи: 98
31-01-2019 дата публикации

Source and drain stressors with recessed top surfaces

Номер: US20190035931A1
Автор: Chii-Horng Li, Hsueh-Chang Sung, Kun-Mu Li, Tsz-Mei Kwok, Tze-Liang Lee
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

An integrated circuit structure includes a gate stack over a semiconductor substrate, and a silicon germanium region extending into the semiconductor substrate and adjacent to the gate stack. The silicon germanium region has a top surface, with a center portion of the top surface recessed from edge portions of the top surface to form a recess. The edge portions are on opposite sides of the center portion.

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Номер записи: 99
04-02-2021 дата публикации

Semiconductor devices

Номер: US20210035975A1
Автор: Soonmoon JUNG, Sungmin Kim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor device includes a first transistor, a division pattern, and a second transistor sequentially stacked on a substrate. The first transistor includes a first gate structure, a first source/drain layer at each of opposite sides of the first gate structure, and first semiconductor patterns spaced apart from each other in a vertical direction. Each of the first semiconductor patterns extends through the first gate structure and contacts the first source/drain layer. The division pattern includes an insulating material. The second transistor includes a second gate structure, a second source/drain layer at each of opposite sides of the second gate structure, and second semiconductor patterns spaced apart from each other in the vertical direction. Each of the second semiconductor patterns extends through the second gate structure and contacts the second source/drain layer. The first source/drain layer does not directly contact the second source/drain layer.

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Номер записи: 100