Semiconductor device having semiconductor substrate, and method of manufacturing the same

A semiconductor device includes a semiconductor substrate having a plurality of electrode pads, a protective film covering the upper surface of the semiconductor substrate and having an opening so that the electrode pad is exposed therethrough, a metal film formed on the electrode pad exposed through the opening, and a bump formed on the metal film. The metal film includes a plurality of grooves radially formed from the center thereof toward the periphery thereof.

Method for Aligning Micro-Electronic Components

Alignment of a first micro-electronic component to a receiving surface of a second micro-electronic component is realized by a capillary force-induced self-alignment, combined with an electrostatic alignment. The latter is accomplished by providing at least one first electrical conductor line along the periphery of the first component, and at least one second electrical conductor along the periphery of the location on the receiving surface of the second component onto which the component is to be placed. The contact areas surrounded by the conductor lines are covered with a wetting layer. The electrical conductor lines may be embedded in a strip of anti-wetting material that runs along the peripheries to create a wettability contrast. The wettability contrast helps to maintain a drop of alignment liquid between the contact areas so as to obtain self-alignment by capillary force. By applying appropriate charges on the conductor lines, electrostatic self-alignment is realized, which improves ...

CHIP PACKAGING METHOD AND CHIP PACKAGE USING HYDROPHOBIC SURFACE

소수성 표면(hydrophobic surface)을 이용한 칩 패키징 방법은 제1 칩 또는 제1 보드 중 어느 하나 및 제2 칩 또는 제2 보드 중 어느 하나 각각의 표면에 미리 설정된 크기의 초소수성 표면을 형성하는 단계; 상기 제1 칩 또는 상기 제1 보드 중 어느 하나 및 상기 제2 칩 또는 상기 제2 보드 중 어느 하나 각각에 형성된 초소수성 표면 상의 미리 설정된 위치에 친수성 표면(hydrophilic surface)을 형성하는 단계; 상기 제1 칩 또는 상기 제1 보드 중 어느 하나 및 상기 제2 칩 또는 상기 제2 보드 중 어느 하나 각각에 형성된 친수성 표면에 액체 금속 볼(liquid metal ball)을 생성하는 단계; 및 상기 제1 칩 또는 상기 제1 보드 중 어느 하나의 액체 금속 볼 및 상기 제2 칩 또는 상기 제2 보드 중 어느 하나의 액체 금속 볼을 결합시킴으로써, 상기 제1 칩 또는 상기 제1 보드 중 어느 하나 및 상기 제2 칩 또는 상기 제2 보드 중 어느 하나를 패키징 하는 단계를 포함한다. A method of chip packaging using a hydrophobic surface includes forming a super-hydrophobic surface of a predetermined size on a surface of either the first chip or the first board and the second chip or the second board, respectively; Forming a hydrophilic surface at a predetermined position on a super-hydrophobic surface formed on either the first chip or the first board and on either the second chip or the second board; Forming a liquid metal ball on a hydrophilic surface formed on either the first chip or the first board and on either the second chip or the second board; And either one of the liquid metal ball of the first chip or the first board and the liquid metal ball of either the second chip or the second board, And packaging either the second chip or the second board.

Interposer, method for fabricating the same, and semiconductor package having the same

An interposer according to an embodiment of the present invention includes a base layer having opposite first and second surfaces, a wiring structure on the first surface of the base layer, an interposer protective layer disposed on the second surface of the base layer and having a pad recess with a lower surface of the interposer protective layer positioned at a first vertical level and a bottom surface of the pad recess positioned at a second vertical level that is higher than the first vertical level, an interposer pad of which a portion fills the pad recess of the interposer protective layer and the remaining portion protrudes from the interposer protective layer, and an interposer through electrode extending through the base layer and the interposer protective layer to the interposer pad, the interposer through electrode electrically connecting the wiring structure to the interposer pad.

Semiconductor device and method of forming the same

Semiconductor package device and forming the same

In some embodiments in accordance with the present disclosure, a semiconductor device having a semiconductor substrate is provided. A metal structure is disposed over the semiconductor substrate, and a post-passivation interconnect (PPI) is disposed over the metal structure. In addition, the upper surface of the PPI is configured to receive a bump thereon. In certain embodiments, the upper surface of the PPI for receiving the bump is substantially flat. A positioning member is formed over the PPI and configured to accommodate the bump. In some embodiments, the positioning member is configured to limit bump movement after the bump is disposed over the PPI so as to retain the bump at a predetermined position.

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING SAME

A semiconductor package includes; a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first semiconductor chip includes; a first substrate, a first bonding pad on a first surface of the first substrate, and a first passivation layer on the first surface of the first substrate exposing at least a portion of the first bonding pad. The second semiconductor chip includes; a second substrate, a second insulation layer on a front surface of the second substrate, a second bonding pad on the second insulation layer, a first alignment key pattern on the second insulation layer, and a second passivation layer on the second insulation layer, covering at least a portion of the first alignment key pattern, and exposing at least a portion of the second bonding pad, wherein the first bonding pad and the second bonding pad are directly bonded, and the first passivation layer and the second passivation layer are directly bonded.

Patterns of passivation material on bond pads and methods of manufacture thereof

Pattern structure for display device and manufacturing method thereof

A pattern structure for a display device includes a substrate, a protrusion pattern on the substrate, a first conductive pattern covering an upper surface of the protrusion pattern, an interlayer insulating layer on the first conductive pattern and including a contact hole, and a second conductive pattern on the interlayer insulating layer and connected to the first conductive pattern. The contact hole overlaps the protrusion pattern and the first conductive pattern.

PATTERNS OF PASSIVATION MATERIAL ON BOND PADS AND METHODS OF MANUFACTURE THEREOF

A method includes forming a pad on an electronic component. The pad comprises conductive material. The method further includes providing passivation material on a surface of the conductive material and removing passivation material from the surface to expose portions of the conductive material to form a bond pad comprising conductive material and passivation material.

SEMICONDUCTOR DEVICE AND METHOD OF UNIT SPECIFIC PROGRESSIVE ALIGNMENT

A semiconductor device may include a semiconductor die disposed within an encapsulant, the semiconductor die being misaligned with a package edge formed by the encapsulant. A total radial shift of the semiconductor die may account for the misalignment between semiconductor die and the package edge. A build-up interconnect structure may comprise two or more layers formed over the semiconductor die and the encapsulant, the two or more layers comprising at least one redistribution layer (RDL). The total radial shift may be distributed over the two or more layers of the build-up interconnect structure to form a unit specific pattern for each of the two or more layers. An average misalignment of the semiconductor die and the package edge may be greater than the average misalignment of the at least one unit specific pattern with respect to the package edge. 1. A plurality of semiconductor devices , comprising:a sample of semiconductor die singulated from one or more embedded die panels formed of encapsulant disposed around the sample of semiconductor die, the sample of semiconductor die being misaligned with a package edge formed by the encapsulant for each of the sample of semiconductor die;a total radial shift for each of the plurality of semiconductor die being defined at a limiting feature for each of the plurality of semiconductor die relative to a semiconductor die center for each of the plurality of semiconductor die, respectively, the total radial shift for each of the plurality of semiconductor die accounting for the misalignment between the plurality of semiconductor die and the package edge formed by the encapsulant for each of the sample of semiconductor die;a build-up interconnect structure comprising two or more layers formed over each of the plurality of semiconductor die and the encapsulant, the two or more layers comprising at least one redistribution layer (RDL); andthe total radial shift is distributed over the two or more layers of the build-up ...

Package structure

本發明實施例提供封裝結構及其製造方法。所述封裝結構包含第一內連線結構形成於第一基板之上，且所述第一內連線結構包含第一金屬層。所述封裝結構也包含第二內連線結構形成於第二基板之上。所述封裝結構包含接合結構位於所述第一內連線結構和所述第二內連線結構之間。所述接合結構包含第一金屬間化合物和第二金屬間化合物，所述第一金屬間化合物的一部分從所述第二金屬間化合物的複數個側壁表面突出，且所述第一金屬間化合物和所述第二金屬間化合物之間存在晶界。

Method for aligning micro-electronic components

Alignment of a first micro-electronic component to a receiving surface of a second micro-electronic component is realized by a capillary force-induced self-alignment, combined with an electrostatic alignment. The latter is accomplished by providing at least one first electrical conductor line along the periphery of the first component, and at least one second electrical conductor along the periphery of the location on the receiving surface of the second component onto which the component is to be placed. The contact areas surrounded by the conductor lines are covered with a wetting layer. The electrical conductor lines may be embedded in a strip of anti-wetting material that runs along the peripheries to create a wettability contrast. The wettability contrast helps to maintain a drop of alignment liquid between the contact areas so as to obtain self-alignment by capillary force. By applying appropriate charges on the conductor lines, electrostatic self-alignment is realized, which improves the alignment obtained through capillary force and maintains the alignment during evaporation of the liquid.

Semiconductor device and method of forming the same

根據本申請案揭示內容，在一些實施方式中，提供具有一半導體基板的一半導體裝置。一金屬結構係位於該半導體基板上方，以及一鈍化後互連(PPI)係位於該金屬結構上方。此外，該PPI的上表面係用以接收一凸塊於其上。在一些實施方式中，用於接收該凸塊之該PPI的上表面係實質平坦。在該PPI上方形成一定位件，用以容納該凸塊。在一些實施方式中，在該凸塊位於該PPI上方之後，該定位件係用以限制凸塊移動，因而維持該凸塊於一預定位置。

SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE

A semiconductor package includes a first semiconductor chip including a first substrate and a first bonding layer disposed on the first substrate, and having a flat first outer surface provided by the first bonding layer; and a second semiconductor chip disposed on the first outer surface of the first semiconductor chip, including a second substrate and a second bonding layer disposed on the second substrate, and having a flat second outer surface provided by the second bonding layer and contacting the first outer surface of the first semiconductor chip. The first bonding layer includes a first outermost insulating layer providing the first outer surface, a first internal insulating layer stacked between the first outermost insulating layer and the first substrate, first external marks disposed in the first outermost insulating layer and spaced apart from each other, and first internal marks interlaced with the first external marks within the first internal insulating layer.

For aligning a microelectronic assembly

Package-on-package (POP) type semiconductor packages

Provided are package-on-package (POP)-type semiconductor packages including a lower package having a first size and including a lower package substrate in which a lower semiconductor chip is, an upper redistribution structure on the lower package substrate and the lower semiconductor chip, and alignment marks. The packages may also include an upper package having a second size smaller than the first size and including an upper package substrate and an upper semiconductor chip. The upper package substrate may be mounted on the upper redistribution structure of the lower package and electrically connected to the lower package, and the upper semiconductor chip may be on the upper package substrate. The alignment marks may be used for identifying the upper package, and the alignment marks may be below and near outer boundaries of the upper package on the lower package.

SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME

In some embodiments in accordance with the present disclosure, a semiconductor device having a semiconductor substrate is provided. A metal structure is disposed over the semiconductor substrate, and a post-passivation interconnect (PPI) is disposed over the metal structure. In addition, the upper surface of the PPI is configured to receive a bump thereon. In certain embodiments, the upper surface of the PPI for receiving the bump is substantially flat. A positioning member is formed over the PPI and configured to accommodate the bump. In some embodiments, the positioning member is configured to limit bump movement after the bump is disposed over the PPI so as to retain the bump at a predetermined position. 1. A semiconductor device , comprising:a semiconductor substrate;a metal structure over the semiconductor substrate;a post-passivation interconnect (PPI) over the metal structure and configured to receive a bump; anda positioning member over the PPI and configured to accommodate the bump,wherein the positioning member at least partially encloses the bump and contacts with an outer surface of the bump so as to retain the bump at a predetermined position.2. The semiconductor device according to claim 1 , wherein the PPI includes an upper surface for receiving the bump.3. The semiconductor device according to claim 1 , wherein the PPI is a portion of a redistribution layer (RDL).4. The semiconductor device according to claim 1 , wherein the positioning member includes at least two protruding portions clipping the bump so as to retain the bump at the predetermined position.5. The semiconductor device according to claim 1 , wherein the positioning member includes a cavity for accommodating the bump so as to retain the bump at the predetermined position.6. The semiconductor device according to claim 1 , wherein the bump is configured to be aligned with a substantially central point of the positioning member.7. The semiconductor device according to claim 1 , wherein the ...

SEMICONDUCTOR DEVICE HAVING SEMICONDUCTOR SUBSTRATE, AND METHOD OF MANUFACTURING THE SAME

A semiconductor device includes a semiconductor substrate having a plurality of electrode pads, a protective film covering the upper surface of the semiconductor substrate and having an opening so that the electrode pad is exposed therethrough, a metal film formed on the electrode pad exposed through the opening, and a bump formed on the metal film. The metal film includes a plurality of grooves radially formed from the center thereof toward the periphery thereof.

Semiconductor device and method of unit specific progressive alignment

A semiconductor device may include a semiconductor die disposed within an encapsulant, the semiconductor die being misaligned with a package edge formed by the encapsulant. A total radial shift of the semiconductor die may account for the misalignment between semiconductor die and the package edge. A build-up interconnect structure may comprise two or more layers formed over the semiconductor die and the encapsulant, the two or more layers comprising at least one redistribution layer (RDL). The total radial shift may be distributed over the two or more layers of the build-up interconnect structure to form a unit specific pattern for each of the two or more layers. An average misalignment of the semiconductor die and the package edge may be greater than the average misalignment of the at least one unit specific pattern with respect to the package edge.

Package structure and method for forming the same

A package structure and method for forming the same are provided. The package structure includes a first interconnect structure formed over a first substrate, and the first interconnect structure includes a first metal layer. The package structure further includes a second interconnect structure formed over a second substrate. The package structure includes a bonding structure between the first interconnect structure and the second interconnect structure. The bonding structure includes a first intermetallic compound (IMC) and a second intermetallic compound (IMC), a portion of the first IMC protrudes from the sidewall surfaces of the second IMC, and there could be a grain boundary between the first IMC and the second IMC.

PATTERN STRUCTURE FOR DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF

A pattern structure for a display device includes a substrate, a protrusion pattern on the substrate, a first conductive pattern covering an upper surface of the protrusion pattern, an interlayer insulating layer on the first conductive pattern and including a contact hole, and a second conductive pattern on the interlayer insulating layer and connected to the first conductive pattern. The contact hole overlaps the protrusion pattern and the first conductive pattern.

Patterns of passivation material on bond pads and methods of manufacture thereof

本发明的实施例涉及键合焊盘上的钝化材料的图案及其制造方法。一种方法包括在电子组件上形成焊盘。该焊盘包括导电材料。该方法进一步包括在导电材料的表面上提供钝化材料，以及从该表面去除钝化材料以暴露导电材料的部分从而形成包括导电材料和钝化材料的键合焊盘。

PACKAGE-ON-PACKAGE (POP) TYPE SEMICONDUCTOR PACKAGES

Provided are package-on-package (POP)-type semiconductor packages including a lower package having a first size and including a lower package substrate in which a lower semiconductor chip is, an upper redistribution structure on the lower package substrate and the lower semiconductor chip, and alignment marks. The packages may also include an upper package having a second size smaller than the first size and including an upper package substrate and an upper semiconductor chip. The upper package substrate may be mounted on the upper redistribution structure of the lower package and electrically connected to the lower package, and the upper semiconductor chip may be on the upper package substrate. The alignment marks may be used for identifying the upper package, and the alignment marks may be below and near outer boundaries of the upper package on the lower package.

Patterns of passivation material on bond pads and methods of manufacture thereof

A method includes forming a pad on an electronic component. The pad comprises conductive material. The method further includes providing passivation material on a surface of the conductive material and removing passivation material from the surface to expose portions of the conductive material to form a bond pad comprising conductive material and passivation material.

Electronic package structure, electronic substrate and method of manufacturing electronic package structure

An electronic package structure, an electronic substrate, and a method of manufacturing an electronic package structure are provided. The electronic package structure includes a substrate. The substrate includes a bonding region and an alignment structure. The bonding region is located at a side of the substrate and configured to bond with an electronic component. The alignment structure is located at the side of the substrate and out of the bonding region and configured to providing a fiducial mark for position-aligning, wherein the alignment structure comprises a first region and a second region visually distinct from the first region.

DIE BONDING SYSTEMS, AND METHODS OF USING THE SAME

A die bonding system including a bond head assembly for bonding a die to a substrate is provided. The die includes a first plurality of fiducial markings, and the substrate includes a second plurality of fiducial markings. The die bonding system also includes an imaging system configured for simultaneously imaging one of the first plurality of fiducial markings and one of the second plurality of fiducial markings along a first optical path while the die is carried by the bond head assembly. The imaging system is also configured for simultaneously imaging another of the first plurality of fiducial markings and another of the second plurality of fiducial markings along a second optical path while the die is carried by the bond head assembly. Each of the first and second optical paths are independently configurable to image any area of the die including one of the first plurality of fiducial markings.

PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME

A package structure and method for forming the same are provided. The package structure includes a first interconnect structure formed over a first substrate, and the first interconnect structure includes a first metal layer. The package structure further includes a second interconnect structure formed over a second substrate. The package structure includes a bonding structure between the first interconnect structure and the second interconnect structure. The bonding structure includes a first intermetallic compound (IMC) and a second intermetallic compound (IMC), a portion of the first IMC protrudes from the sidewall surfaces of the second IMC, and there could be a grain boundary between the first IMC and the second IMC.

Wafer Bonding Method and Bonded Device Structure

In an embodiment, a method includes: receiving a first wafer and a second wafer, the first wafer including a first alignment mark, the first alignment mark including a first grid of first magnetic features, the second wafer including a second alignment mark, the second alignment mark including a second grid of second magnetic features; aligning the first alignment mark with the second alignment mark in an optical alignment process; after the optical alignment process, aligning the first alignment mark with the second alignment mark in a magnetic alignment process, north poles of the first magnetic features being aligned with south poles of the second magnetic features, south poles of the first magnetic features being aligned with north poles of the second magnetic features; and forming bonds between the first wafer and the second wafer.

Chip packaging method and chip package using hydrophobic surface

A chip packaging method using a hydrophobic surface includes forming superhydrophobic surfaces forming hydrophilic surfaces on predetermined positions of the superhydrophobic surfaces formed on the one of a first chip or the first board and the one of a second chip or a second board, respectively, generating liquid metal balls on the hydrophilic surfaces formed on the one of the first chip or the first board and the one of the second chip or the second board, respectively, and packaging the one of the first chip or the first board and the one of the second chip or the second board by combing the liquid metal ball of the one of the first chip or the first board and the liquid metal ball of the one of the second chip or the second board with each other.

DISPLAY DEVICE

A display device includes a lower substrate, a sub-pixel structure, an optical filter layer, a color filter layer, an upper substrate, and an alignment structure. The lower substrate has a display area and a peripheral area surrounding the display area. The sub-pixel structure is disposed in the display area on the lower substrate. The optical filter layer is disposed on the sub-pixel structure. The color filter layer is disposed on the optical filter layer. The upper substrate is disposed on the color filter layer. The alignment structure is disposed in the peripheral area on a bottom surface of the upper substrate, and contains a material equal to a material forming the optical filter layer and the color filter layer.

Display device having an alignment structure

A display device includes a lower substrate, a sub-pixel structure, an optical filter layer, a color filter layer, an upper substrate, and an alignment structure. The lower substrate has a display area and a peripheral area surrounding the display area. The sub-pixel structure is disposed in the display area on the lower substrate. The optical filter layer is disposed on the sub-pixel structure. The color filter layer is disposed on the optical filter layer. The upper substrate is disposed on the color filter layer. The alignment structure is disposed in the peripheral area on a bottom surface of the upper substrate, and contains a material equal to a material forming the optical filter layer and the color filter layer.

Method for aligning micro-electronic components

Alignment of a first micro-electronic component to a receiving surface of a second micro-electronic component is realized by a capillary force-induced self-alignment, combined with an electrostatic alignment. The latter is accomplished by providing at least one first electrical conductor line along the periphery of the first component, and at least one second electrical conductor along the periphery of the location on the receiving surface of the second component onto which the component is to be placed. The contact areas surrounded by the conductor lines are covered with a wetting layer. The electrical conductor lines may be embedded in a strip of anti-wetting material that runs along the peripheries to create a wettability contrast. The wettability contrast helps to maintain a drop of alignment liquid between the contact areas so as to obtain self-alignment by capillary force. By applying appropriate charges on the conductor lines, electrostatic self-alignment is realized, which improves the alignment obtained through capillary force and maintains the alignment during evaporation of the liquid.

Methods and Apparatus for Package with Interposers

Methods and apparatus for an interposer with dams used in packaging dies are disclosed. An interposer may comprise a metal layer above a substrate. A plurality of dams may be formed above the metal layer around each corner of the metal layer. Dams may be formed on both sides of the interposer substrate. A dam surrounds an area where connectors such as solder balls may be located to connect to other packages. A non-conductive dam may be formed above the dam. An underfill may be formed under the package connected to the connector, above the metal layer, and contained within the area surrounded by the dams at the corner, so that the connectors are well protected by the underfill. Such dams may be further formed on a printed circuit board as well.

Packaged Semiconductor Devices and Methods of Packaging Thereof

Packaging methods for semiconductor devices and methods of packaging thereof are disclosed. In some embodiments, a device includes a packaging apparatus and contact pads disposed on the packaging apparatus. The contact pads are arranged in an array of rows and columns. The contact pads include first contact pads proximate a perimeter region of the packaging apparatus and second contact pads disposed in an interior region of the packaging apparatus. A dam structure that is continuous is disposed around the second contact pads. The contact pads comprise a mounting region for a semiconductor device.

用于凸块下金属结构的套环及相关联的系统及方法

本发明涉及用于裸片间及/或封装间互连件的凸块下金属UBM结构环的制造及相关联的系统。一种半导体裸片包含：半导体材料，其具有固态组件；及互连件，其至少部分延伸穿过所述半导体材料。凸块下金属UBM结构形成于所述半导体材料上方且电耦合到对应互连件。套环包围所述UBM结构的侧表面的至少一部分，且焊接材料安置于所述UBM结构的顶面上方。

Semiconductor device

Collar for under-bump metal structures and related systems and methods

본 기술은 다이-다이 및/또는 패키지-패키지 간의 인터커넥트 및 관련 시스템을 위한 언더-범프 금속(UBM) 구조체용 칼라의 제조에 관한 것이다. 반도체 다이는 반도체 고체 상태 구성요소를 가진 반도체 재료와, 반도체 재료를 통해 적어도 부분적으로 연장되는 인터커넥트를 포함한다. 언더-범프 금속(UBM) 구조체는 반도체 재료 위에 형성되고 대응하는 인터커넥트에 전기적으로 결합된다. 칼라는 UBM 구조체의 측면의 적어도 일부를 둘러싸고, 솔더 재료는 UBM 구조체의 상부면 위에 배치된다. The present technology relates to the manufacture of collars for under-bump metal (UBM) structures for interconnect and related systems between die-die and/or package-package. The semiconductor die includes a semiconductor material having a semiconductor solid state component and an interconnect extending at least partially through the semiconductor material. An under-bump metal (UBM) structure is formed over the semiconductor material and is electrically coupled to a corresponding interconnect. The collar surrounds at least a portion of the side of the UBM structure, and the solder material is disposed over the top surface of the UBM structure.

Collar for under bump metal structure and associated systems and methods

本发明涉及用于裸片间及/或封装间互连件的凸块下金属UBM结构环的制造及相关联的系统。一种半导体裸片包含：半导体材料，其具有固态组件；及互连件，其至少部分延伸穿过所述半导体材料。凸块下金属UBM结构形成于所述半导体材料上方且电耦合到对应互连件。套环包围所述UBM结构的侧表面的至少一部分，且焊接材料安置于所述UBM结构的顶面上方。

Electronic component and electronic device

An electronic component to be mounted on a substrate comprises an electronic component-side land that faces a substrate-side land provided on the substrate when the electronic component is mounted on the substrate. A non-soldered region is provided on a surface of the electronic component-side land, facing the substrate-side land, so that a shape of the substrate-side land is different from a shape of the electronic component-side land facing the substrate-side land.

Electrical apparatus having electrical pattern capable of preventing solder bridge

본 발명은 솔더 브릿지를 억제할 수 있는 전기적 패턴을 갖는 전기적 장치에 관한 것으로, 기판 상에 배열된 복수개의 전기적 패턴을 포함한다. 상기 전기적 패턴은, 솔더볼이 접속되는 패드; 상기 패드의 일측으로부터 연장되어 전기적 신호를 상기 패드로 전달하는 전기적 트레이스, 상기 패드의 다른 일측으로부터 연장된 제1 더미 트레이스, 및 상기 제1 더미 트레이스를 상기 전기적 트레이스를 연결하는 제1 연결선을 포함한다. 상기 제1 더미 트레이스는 상기 패드를 사이에 두고 상기 전기적 트레이스를 일직선상으로 마주보지 않는다. The present invention relates to an electrical device having an electrical pattern capable of suppressing solder bridges, comprising a plurality of electrical patterns arranged on a substrate. The electrical pattern may include a pad to which a solder ball is connected; an electrical trace extending from one side of the pad to transmit an electrical signal to the pad, a first dummy trace extending from the other side of the pad, and a first connection line connecting the first dummy trace to the electrical trace . The first dummy trace does not face the electrical trace in a straight line with the pad interposed therebetween.

Chip packaging method and chip package using hydrophobic surface

소수성 표면(hydrophobic surface)을 이용한 칩 패키징 방법은 제1 칩 또는 제1 보드 중 어느 하나 및 제2 칩 또는 제2 보드 중 어느 하나 각각의 표면에 미리 설정된 크기의 초소수성 표면을 형성하는 단계; 상기 제1 칩 또는 상기 제1 보드 중 어느 하나 및 상기 제2 칩 또는 상기 제2 보드 중 어느 하나 각각에 형성된 초소수성 표면 상의 미리 설정된 위치에 친수성 표면(hydrophilic surface)을 형성하는 단계; 상기 제1 칩 또는 상기 제1 보드 중 어느 하나 및 상기 제2 칩 또는 상기 제2 보드 중 어느 하나 각각에 형성된 친수성 표면에 액체 금속 볼(liquid metal ball)을 생성하는 단계; 및 상기 제1 칩 또는 상기 제1 보드 중 어느 하나의 액체 금속 볼 및 상기 제2 칩 또는 상기 제2 보드 중 어느 하나의 액체 금속 볼을 결합시킴으로써, 상기 제1 칩 또는 상기 제1 보드 중 어느 하나 및 상기 제2 칩 또는 상기 제2 보드 중 어느 하나를 패키징 하는 단계를 포함한다.

Flip-chip type electronic device and method for manufacturing flip-chip type electronic device

Electronic component and electronic device

An electronic component to be mounted on a substrate comprises an electronic component-side land that faces a substrate-side land provided on the substrate when the electronic component is mounted on the substrate. A non-soldered region is provided on a surface of the electronic component-side land, facing the substrate-side land, so that a shape of the substrate-side land is different from a shape of the electronic component-side land facing the substrate-side land.

Semiconductor device, semiconductor substrate, and semiconductor device manufacturing method

显示面板以及包括其的显示装置

本发明公开一种显示面板以及包括其的显示装置。显示面板可以包括：基板，包括显示区域以及位于显示区域的周边的焊盘区域；多个像素，配置于基板上的显示区域；以及多个焊盘，配置于基板上的焊盘区域并与多个像素电连接。多个焊盘各自可以包括：第一导电层；第一凸出部，配置于第一导电层上；第二凸出部，配置于第一导电层上并具有小于第一凸出部的厚度的厚度；以及第二导电层，配置于第一导电层上并覆盖第一凸出部以及第二凸出部各自的上面。

Display device

一种集成电路与微机电系统的直接键合装置及制备工艺

一种集成电路与微机电系统的直接键合装置，包括太阳能电池，平坦化氧化层，对准金属接触部分，金属互连部分，焊点；平坦化氧化层与带有导电连接和密封的对准金属接触部分在低温直接键合，实现金属互连部分与高气密性的结合，金属互连部分和太能电池通过深硅刻蚀技术进行填充，焊点位于金属互连部分上。一种集成电路与微机电系统的直接键合装置制备工艺，平坦化氧化层表面上带有用于导电连接和密封的校准金属层，表面清洗或活化，校准，然后低温键合；金属能是合金、焊料或纯金属键合在一起。本发明的优点：本发明所述的集成电路与微机电系统的直接键合装置及制备工艺，原理结构简单，工艺稳定，提高了产品可靠性。

인터포저, 이의 제조 방법, 및 이를 가지는 반도체 패키지

본 발명에 따른 인터포저는, 서로 반대되는 제1 면과 제2 면을 가지는 베이스층, 베이스층의 제1 면 상의 배선 구조물, 베이스층의 제2 면 상에 배치되고 제1 수직 레벨에 위치하는 하면 및 제1 수직 레벨보다 높은 제2 수직 레벨에 위치하는 저면을 가지는 패드 리세스를 가지는 인터포저 보호층, 일부분이 인터포저 보호층의 패드 리세스를 채우고 나머지 부분이 인터포저 보호층의 외측으로 돌출되는 인터포저 패드, 및 베이스층 및 인터포저 보호층을 관통하여 인터포저 패드 내로 연장되고 배선 구조물과 인터포저 패드를 전기적으로 연결하는 인터포저 관통 전극을 포함한다.

Packaged Semiconductor Devices And Methods of Packaging Thereof

Packaging methods for semiconductor devices and methods of packaging thereof are disclosed. In some embodiments, a device includes a packaging apparatus and contact pads disposed on the packaging apparatus. The contact pads are arranged in an array of rows and columns. The contact pads include first contact pads proximate a perimeter region of the packaging apparatus and second contact pads disposed in an interior region of the packaging apparatus. A dam structure that is continuous is disposed around the second contact pads. The contact pads comprise a mounting region for a semiconductor device.

Semiconductor chip and method of manufacturing the same

A chip includes a substrate and a dielectric layer disposed on the substrate. The dielectric layer includes a first dielectric region and a second dielectric region surrounding an outer periphery of the first dielectric region. A top surface of the first dielectric region is disposed below a top surface of the second dielectric region. The chip further includes a metal pad disposed in a through-hole in the first dielectric region and contacting a portion of the substrate.

Semiconductor package

A semiconductor package includes a substrate including a first semiconductor chip including a first wiring structure, a first bonding pad, and a first alignment key on the first wiring structure to be spaced apart in a first direction, a second semiconductor chip including a second wiring structure, a second bonding pad on the second wiring structure and connected to the first bonding pad, and a second alignment key on the second wiring structure to be spaced apart from the second bonding pad and not overlapping the first alignment key in the second direction, the first wiring structure including a first wiring pattern connected to the first bonding pad and not overlapping the first and second alignment keys in the second direction, and the second wiring structure including a second wiring pattern connected to the second bonding pad and not overlapping the first and second alignment keys in the second direction.

晶圓鍵合方法以及經鍵合的晶圓結構

在一實施例中，一種方法包含：接收第一晶圓以及第二晶圓，第一晶圓包含第一對準標記，第一對準標記包含第一磁性特徵件的第一網格，第二晶圓包含第二對準標記，第二對準標記包含第二磁性特徵件的第二網格；在光學對準製程中，對準第一對準標記與第二對準標記；在光學對準製程之後，在磁性對準製程中，對準第一對準標記與第二對準標記，第一磁性特徵件的N極對準第二磁性特徵件的S極，第一磁性特徵件的S極對準第二磁性特徵件的N極；以及形成鍵合在第一晶圓以及第二晶圓之間。

웨이퍼 접합 방법 및 접합된 디바이스 구조물

실시예에서, 방법은, 제1 웨이퍼 및 제2 웨이퍼를 수용하는 단계 - 제1 웨이퍼는 제1 정렬 마크를 포함하고, 제1 정렬 마크는 제1 자기 피처의 제1 그리드를 포함하고, 제2 웨이퍼는 제2 정렬 마크를 포함하고, 제2 정렬 마크는 제2 자기 피처의 제2 그리드를 포함함 - ; 광학 정렬 공정에서 제1 정렬 마크를 제2 정렬 마크와 정렬시키는 단계; 광학 정렬 공정 후, 자기 정렬 공정에서 제1 정렬 마크를 제2 정렬 마크와 정렬시키는 단계 - 제1 자기 피처의 북극은 제2 자기 피처의 남극과 정렬되고, 제1 자기 피처의 남극은 제2 자기 피처의 북극과 정렬됨 - ; 및 제1 웨이퍼와 제2 웨이퍼 사이에 접합부를 형성하는 단계를 포함한다.

半导体装置

实施方式提供一种能够确保各晶片间的接合强度及导通性的半导体装置。实施方式的半导体装置具有第1晶片、第1配线层、第1绝缘层、第1电极、第2晶片、第2配线层、第2绝缘层、第2电极和第1层。第1电极具有第1面、第2面、第3面及第4面。第2电极具有第5面、第6面、第7面、第2侧面及第8面。第1层设于第4面与第1绝缘层中的将第4面包围的部分之间，从第3面在第1方向上远离而设置。

Semiconductor structure and method for fabricating same

A semiconductor structure includes a base and a re-distribution layer. The re-distribution layer is disposed on the base and includes a bond pad and a probe pad, the bond pad and the probe pad are disposed adjacent to each other, and a recess is formed in the re-distribution layer and is disposed between the bond pad and the probe pad.

用于显示装置的图案结构

提供一种用于显示装置的图案结构，所述图案结构包括：基底；突起图案，位于基底上；第一导电图案，覆盖突起图案的上表面；层间绝缘层，位于第一导电图案上，并包括接触孔；以及第二导电图案，位于层间绝缘层上，并连接到第一导电图案。接触孔与突起图案和第一导电图案叠置。

반도체 패키지 및 반도체 패키지의 제조 방법

반도체 패키지는 제1 기판, 상기 제1 기판의 일면 상에 구비되는 제1 본딩 패드 및 상기 제1 기판의 일면 상에 형성되며 상기 제1 본딩 패드의 적어도 일부를 노출시키는 제1 패시베이션 막을 포함하는 제1 반도체 칩, 및 상기 제1 반도체 칩 상에 적층되며, 제2 기판, 상기 제2 기판의 전면 상에 구비되는 제2 절연막, 상기 제2 절연막 상에 구비되는 제2 본딩 패드, 상기 제2 절연막 상에 구비되는 복수 개의 제1 얼라인 키 패턴들, 상기 제2 절연막 상에 형성되며 상기 제1 얼라인 키 패턴들을 커버하며 상기 제2 본딩 패드의 적어도 일부를 노출시키는 제2 패시베이션 막을 포함하는 제2 반도체 칩을 포함한다. 상기 제1 본딩 패드와 상기 제2 본딩 패드는 서로 직접 접합되고, 상기 제1 패시베이션 막과 상기 제2 패시베이션 막을 서로 직접 접합된다.

Electronic package structure, electronic substrate and method of manufacturing electronic package structure

An electronic package structure, an electronic substrate, and a method of manufacturing an electronic package structure are provided. The electronic package structure includes a substrate. The substrate includes a bonding region and an alignment structure. The bonding region is located at a side of the substrate and configured to bond with an electronic component. The alignment structure is located at the side of the substrate and out of the bonding region and configured to providing a fiducial mark for position-aligning, wherein the alignment structure comprises a first region and a second region visually distinct from the first region.

반도체 패키지 및 반도체 패키지의 제조 방법

반도체 패키지는, 서로 반대하는 제1 상면 및 제1 하면을 가지며 중앙 영역 및 상기 중앙 영역 둘레의 코너 영역들을 갖는 기판, 상기 기판의 상기 중앙 영역을 관통하는 복수 개의 관통 전극들, 상기 관통 전극과 전기적으로 연결되며 상기 제1 상면으로부터 제1 높이를 갖도록 구비되는 본딩 패드, 및 상기 기판의 코너 영역들 상에서 상기 제1 상면으로부터 상기 제1 높이보다 높은 제2 높이를 갖도록 각각 연장하는 복수 개의 더미 패드들을 구비하는 제1 반도체 칩, 및 서로 반대하는 제2 상면 및 제2 하면을 갖고, 상기 제2 하면에 구비되며 상기 본딩 패드들과 전기적으로 연결되는 도전성 범프들을 통해 상기 제1 반도체 칩 상에 배치되는 제2 반도체 칩을 포함한다.

显示设备

显示设备包括下基板、子像素结构、滤光器层、滤色器层、上基板和对齐结构。下基板具有显示区域和围绕显示区域的外围区域。子像素结构被布置在下基板上的显示区域中。滤光器层被布置在子像素结构上。滤色器层被布置在滤光器层上。上基板被布置在滤色器层上。对齐结构被布置在上基板的底表面上的外围区域中，并且对齐结构包含与形成滤光器层和滤色器层的材料相同的材料。

封装结构

本公开实施例提供一种封装结构，包含：第一内连线结构，形成于第一基板之上，其中所述第一内连线结构包含第一金属层；第二内连线结构，形成于所述第二基板之下；以及接合结构，位于所述第一内连线结构和所述第二内连线结构之间，其中所述接合结构包含第一金属间化合物和第二金属间化合物，所述第一金属间化合物的一部分从所述第二金属间化合物的复数个侧壁表面突出，且所述第一金属间化合物和所述第二金属间化合物之间存在晶界。本公开实施例也提供一种封装结构的形成方法。

半导体封装

一种半导体封装包括：第一半导体芯片，包括第一布线结构；在第一布线结构上以在第一方向上间隔开的第一接合焊盘和第一对准标记；第二半导体芯片，包括第二布线结构；在第二布线结构上并与第一接合焊盘连接的第二接合焊盘；以及在第二布线结构上以与第二接合焊盘间隔开并且在第二方向上不与第一对准标记重叠的第二对准标记，第一布线结构包括第一布线图案，第一布线图案连接到第一接合焊盘，并且在第二方向上不与第一对准标记和第二对准标记重叠，以及第二布线结构包括第二布线图案，第二布线图案连接到第二接合焊盘，并且在第二方向上不与第一对准标记和第二对准标记重叠。

半導體封裝

本發明提供一種半導體封裝，包含基底，半導體封裝包含：第一半導體晶片，第一半導體晶片包含第一佈線結構；第一接合墊及第一對準鍵，位於第一佈線結構上以在第一方向上間隔開；第二半導體晶片，包含第二佈線結構；第二接合墊，位於第二佈線結構上且連接至第一接合墊；以及第二對準鍵，位於第二佈線結構上以與第二接合墊間隔開且在第二方向上不與第一對準鍵交疊，第一佈線結構包含連接至第一接合墊且在第二方向上不與第一對準鍵及第二對準鍵交疊的第一佈線圖案，且第二佈線結構包含連接至第二接合墊且在第二方向上不與第一對準鍵及第二對準鍵交疊的第二佈線圖案。

Semiconductor package

A semiconductor package includes a substrate including a first semiconductor chip including a first wiring structure, a first bonding pad, and a first alignment key on the first wiring structure to be spaced apart in a first direction, a second semiconductor chip including a second wiring structure, a second bonding pad on the second wiring structure and connected to the first bonding pad, and a second alignment key on the second wiring structure to be spaced apart from the second bonding pad and not overlapping the first alignment key in the second direction, the first wiring structure including a first wiring pattern connected to the first bonding pad and not overlapping the first and second alignment keys in the second direction, and the second wiring structure including a second wiring pattern connected to the second bonding pad and not overlapping the first and second alignment keys in the second direction.

Waferbondingverfahren und gebondete bauelementstruktur

In einer Ausführungsform umfasst ein Verfahren Folgendes: Empfangen eines ersten Wafers und eines zweiten Wafers, wobei der erste Wafer eine erste Ausrichtungsmarkierung aufweist, die erste Ausrichtungsmarkierung ein erstes Gitter von ersten magnetischen Strukturelementen aufweist, der zweite Wafer eine zweite Ausrichtungsmarkierung aufweist, die zweite Ausrichtungsmarkierung ein zweites Gitter von zweiten magnetischen Strukturelementen aufweist; Ausrichten der ersten Ausrichtungsmarkierung mit der zweiten Ausrichtungsmarkierung in einem optischen Ausrichtungsprozess; nach dem optischen Ausrichtungsprozess, Ausrichten der ersten Ausrichtungsmarkierung mit der zweiten Ausrichtungsmarkierung in einem magnetischen Ausrichtungsprozess, wobei Nordpole der ersten magnetischen Strukturelemente mit Südpolen der zweiten magnetischen Strukturelemente ausgerichtet sind, Südpole der ersten magnetischen Strukturelemente mit Nordpolen der zweiten magnetischen Strukturelemente ausgerichtet sind; und Bilden von Bonds zwischen dem ersten Wafer und dem zweiten Wafer.

Package substrates and semiconductor packages having the same

A package substrate includes at least one substrate base, a plurality of wiring patterns disposed on an upper surface and a lower surface of the at least one substrate base and extending in a horizontal direction, a plurality of wiring vias extending in a vertical direction through the at least one substrate base and electrically connecting two wiring patterns positioned at different vertical levels among the plurality of wiring patterns, to each other, and an upper surface solder resist layer having a plurality of first upper surface openings extending from the upper surface to the lower surface, and at least two upper surface openings having a second opening width as a horizontal width that is greater than a first opening width which is a horizontal width of the plurality of first upper surface openings, the upper surface solder resist layer covering an upper surface of the at least one substrate base.

다이 본딩 시스템, 및 이를 사용한 방법

다이를 기판에 본딩하기 위한 본드 헤드 어셈블리를 포함하는 다이 본딩 시스템이 제공된다. 다이는 복수의 제1 기준 마킹을 포함하고, 기판은 복수의 제2 기준 마킹을 포함한다. 또한 다이 본딩 시스템은, 다이가 본드 헤드 어셈블리에 의해 운반되는 동안 제1 광 경로를 따라 복수의 제1 기준 마킹 중 하나 및 복수의 제2 기준 마킹 중 하나를 동시에 이미지화하도록 구성된 이미징 시스템을 포함한다. 또한 이미징 시스템은, 다이가 본드 헤드 어셈블리에 의해 운반되는 동안 제2 광 경로를 따라 복수의 제1 기준 마킹 중 다른 하나 및 복수의 제2 기준 마킹 중 다른 하나를 동시에 이미지화하도록 구성된다. 제1 및 제2 광 경로 각각은, 복수의 제1 기준 마킹 중 하나를 포함하는 다이의 임의의 영역을 이미지화하도록 독립적으로 구성 가능하다.

具有用于有源管芯中的无金属缩减的街道中的基准的hbi管芯架构

本文公开的实施例包括半导体装置。在一个实施例中，管芯包括衬底，其中，衬底包括半导体材料。在实施例中，后端层在衬底之上，其中，后端层包括导电布线。在实施例中，管芯还包括从后端层和衬底的边缘延伸出的突起。在实施例中，基准在突起的表面上。

半導體裝置

實施形態是提供一種可確保各晶圓間的接合強度及導通性之半導體裝置。實施形態的半導體裝置是具有：第1晶圓、第1配線層、第1絕緣層、第1電極、第2晶圓、第2配線層、第2絕緣層、第2電極及第1層。第1電極是具有第1面、第2面、第3面及第4面。第2電極是具有第5面、第6面、第7面、第2側面及第8面。第1層是被設在第4面與第1絕緣層之中包圍第4面的部分之間，從第3面離開至第1方向而設。

Semiconductor device

According to one embodiment, a semiconductor device includes a first wafer, a first wiring layer, a first insulating layer, a first electrode, a second wafer, a second wiring layer, a second insulating layer, a second electrode, and a first layer. The first electrode includes a first surface, a second surface, a third surface, and a fourth surface. The second electrode includes a fifth surface, a sixth surface, a seventh surface, a second side surface, and an eighth surface. The first layer is provided between the fourth surface and a portion of the first insulating layer that surrounds the fourth surface, and is provided away from the third surface in the first direction.

표시 패널 및 이를 포함하는 표시 장치

표시 패널은 표시 영역 및 표시 영역의 주변에 위치하는 패드 영역을 포함하는 기판, 기판 상의 표시 영역에 배치되는 화소들 및 기판 상의 패드 영역에 배치되며 화소들과 전기적으로 연결되는 패드들을 포함할 수 있다. 패드들 각각은 제1 도전층, 제1 도전층 상에 배치되는 제1 돌출부, 제1 도전층 상에 배치되며 제1 돌출부의 두께보다 작은 두께를 갖는 제2 돌출부 및 제1 도전층 상에 배치되며 제1 돌출부 및 제2 돌출부 각각의 상면을 커버하는 제2 도전층을 포함할 수 있다.

패키지 기판, 및 패키지 기판을 포함하는 반도체 패키지

본 발명은 다음과 같은 패키지 기판 및 패키지 기판을 포함하는 반도체 패키지를 제공한다. 본 발명에 따른 패키지 기판은, 적어도 하나의 기판 베이스; 상기 적어도 하나의 기판 베이스의 상면 및 하면에 배치되며 수평 방향으로 연장되는 복수의 배선 패턴; 상기 복수의 배선 패턴 중 다른 수직 레벨에 위치하는 2개의 배선 패턴 사이를 전기적으로 연결하도록 상기 기판 베이스를 관통하여 수직 방향으로 연장되는 복수의 배선 비아; 및 상면으로부터 하면까지 연장되는 복수의 제1 상면 오프닝, 및 상기 복수의 제1 상면 오프닝의 수평 폭인 제1 오프닝 폭보다 큰 제2 오프닝 폭을 수평 폭으로 가지는 적어도 2개의 상면 오프닝을 가지며, 상기 적어도 하나의 기판 베이스의 상면을 덮는 상면 솔더 레지스트층;을 포함하되, 상기 복수의 배선 패턴은, 상기 적어도 하나의 기판 베이스의 상면에서 상기 복수의 제1 상면 오프닝 내에 배치되며 원형 또는 타원형의 평면 형상을 가지는 복수의 상면 연결 패드, 및 상기 적어도 하나의 기판 베이스의 상면에서 상기 적어도 2개의 제2 상면 오프닝 내에 배치되며 꼭짓점이 있는 평면 형상을 가지는 적어도 2개의 정렬 패턴을 포함한다.

Semiconductor package including stacked chips and method of manufacturing the semiconductor package

A semiconductor package includes a first semiconductor chip including a substrate having a first upper surface and a first lower surface opposite thereto. The substrate has a central region and corner regions surrounding the central region. A plurality of through electrodes passes through the central region. A bonding pad is electrically connected to the through electrode and has a first height. A plurality of dummy pads respectively extend from the first upper surface on the corner regions of the substrate and have a second height that is higher than the first height. A second semiconductor chip has a second upper surface and a second lower surface opposite thereto. The second semiconductor chip is disposed on the first semiconductor chip through conductive bumps disposed on the second lower surface and electrically connected to the bonding pads.

晶粒接合系統及其使用方法

本發明提供了一種晶粒接合系統，包括用於將晶粒接合到基板的接合頭組件。晶粒包括第一複數個基準標記，基板包括第二複數個基準標記。晶粒接合系統還包括成像系統，配置為當晶粒由接合頭組件承載時，沿著第一光程對第一複數個基準標記中的一個和第二複數個基準標記中的一個同時成像。成像系統還配置為當晶粒由接合頭組件承載時，沿著第二光程對第一複數個基準標記中的另一個和第二複數個基準標記中的另一個同時成像。第一光程和第二光程中的每一個可獨立地配置為對包括第一複數個基準標記中的一個的晶粒的任何區域進行成像。

堆疊封裝(pop)式半導體封裝

本發明提供堆疊封裝（POP）式半導體封裝，所述堆疊封裝式半導體封裝包括下封裝，下封裝具有第一大小且包括下封裝基板、上重佈線結構、及對準標記，在下封裝基板中具有下半導體晶片，上重佈線結構位於下封裝基板及下半導體晶片上。所述封裝亦可包括上封裝，上封裝具有較第一大小小的第二大小且包括上封裝基板及上半導體晶片。上封裝基板可安裝於下封裝的上重佈線結構上且電性連接至下封裝，且上半導體晶片可位於上封裝基板上。對準標記可用於辨識上封裝，且對準標記可在下封裝上位於上封裝的外邊界下方且靠近上封裝的外邊界。

Hbi die architecture with fiducial in street for no metal depopulation in active die

Embodiments disclosed herein include semiconductor devices. In one embodiment, a die comprises a substrate, where the substrate comprises a semiconductor material. In an embodiment, a backend layer is over the substrate, where the backend layer comprises conductive routing. In an embodiment, the die further comprises a protrusion extending out from an edge of the substrate and the backend layer. In an embodiment, a fiducial is on a surface of the protrusion.

Manufacturing of flip-chip electronic device with carrier having heat dissipation elements free of solder mask

Manufacturing of flip-chip type assemblies is provided, and includes forming one or more contact elements of electrically conductive material on a carrier surface of at least one chip carrier, providing a restrain structure around the contact elements, depositing solder material on the contact elements and/or on one or more terminals of electrically conductive material on a chip surface of at least one integrated circuit chip, and placing the chip with each terminal facing corresponding contact elements. Further, the method includes soldering each terminal to the corresponding contact element by a soldering material, the soldering material being restrained during a soldering of the terminals to the contact elements by the restrain structure, and forming one or more heat dissipation elements of thermally conductive material on the carrier surface for facing the chip surface displaced from the terminals, where the one or more heat dissipation elements are free of any solder mask.

具有不含焊接掩模的热消散元件的载体的倒装芯片电子装置

提出了一种涉及倒装芯片类型的电子装置的技术方案。特别是，一种倒装芯片类型的电子装置(200,300；400；700；800)，包括：具有载体表面(135；835)的至少一个芯片载体(110；805)，该载体包括在该载体表面上的导电材料的一个或多个接触元件(140s,140p；740s,740p；840s,840p)，具有芯片表面(120；720)的至少一个集成电路芯片(105；705)，该芯片包括在该芯片表面上的导电材料的一个或多个端子(125s,125p；725s,725p)，每个芯片端子面对对应的接触元件，将每个端子焊接到该对应的接触元件的焊料材料(150；750)，以及围绕该接触元件的限制装置(210s,210p,310；410sl,410sd,410p；790s,790p；890s,890p)，用于在将该端子焊接到该接触元件期间限制该焊料材料，其中，该载体包括在该载体表面上的导热材料的一个或多个热消散元件(205s,205p；785s,785p；885s,885p)，一个或多个热消散元件从该端子移位，该载体表面面对该芯片表面，该消散元件不含任何焊接掩模。

Flip-chip electronic device with carrier having heat dissipation elements free of solder mask

A solution relating to electronic devices of flip-chip type is proposed. Particularly, an electronic device (200,300;400;700;800) of flip-chip type comprises at least one chip carrier (110;805) having a carrier surface (135;835), the carrier comprising one or more contact elements (140s,140p;740s,740p;840s,840p) of electrically conductive material on the carrier surface, at least one integrated circuit chip (105;705) having a chip surface (120;720), the chip comprising one or more terminals (125s,125p;725s,725p) of electrically conductive material on the chip surface each one facing a corresponding contact element, solder material (150;750) soldering each terminal to the corresponding contact element, and restrain means (210s,210p,310;410sl,410sd,410p;790s,790p;890s,890p) around the contact elements for restraining the solder material during a soldering of the terminals to the contact elements, wherein the carrier comprises one or more heat dissipation elements (205s,205p;785s,785p;885s,885p) of thermally conductive material on the carrier surface facing the chip surface displaced from the terminals, the dissipation elements being free of any solder mask.

フリップチップ・タイプの電子デバイス、およびフリップチップ・タイプの電子デバイスを製造するための方法

【課題】フリップチップ・タイプの電子デバイスに関する解決策を提供する。【解決手段】詳細には、フリップチップ・タイプの電子デバイス（２００、３００、４００、７００、８００）が、キャリア面（１３５、８３５）を有する少なくとも１つのチップ・キャリア（１１０、８０５）であって、キャリア面上に導電性材料の１つまたは複数の接点要素（１４０ｓ、１４０ｐ、７４０ｓ、７４０ｐ、８４０ｓ、８４０ｐ）を備えるチップ・キャリア（１１０、８０５）と、チップ面（１２０、７２０）を有する少なくとも１つの集積回路チップ（１０５、７０５）であって、対応する接点要素に各々が向く、チップ面上の導電性材料の１つまたは複数の端子（１２５ｓ、１２５ｐ、７２５ｓ、７２５ｐ）を備える集積回路チップ（１０５、７０５）と、各端子を対応する接点要素にはんだ付けするはんだ材料（１５０、７５０）と、接点要素への端子のはんだ付けの期間にはんだ材料を制限するための接点要素の周りの制限手段（２１０ｓ、２１０ｐ、３１０、４１０ｓｌ、４１０ｓｄ、４１０ｐ、７９０ｓ、７９０ｐ、８９０ｓ、８９０ｐ）とを備え、キャリアが、端子からずれたチップ面に向くキャリア面上の熱的に伝導性の材料の１つまたは複数の熱放散要素（２０５ｓ、２０５ｐ、７８５ｓ、７８５ｐ、８８５ｓ、８８５ｐ）を備え、放散要素には何らはんだマスクがない。【選択図】図２

Hbi die architecture with fiducial in street for no metal depopulation in active die

Embodiments disclosed herein include semiconductor devices. In one embodiment, a die comprises a substrate, where the substrate comprises a semiconductor material. In an embodiment, a backend layer is over the substrate, where the backend layer comprises conductive routing. In an embodiment, the die further comprises a protrusion extending out from an edge of the substrate and the backend layer. In an embodiment, a fiducial is on a surface of the protrusion.

Method for disposing a component

A method for disposing a component comprises: a step of preparing a substrate and a first liquid; a step of preparing a component-containing liquid containing the components and a second liquid; a step of disposing the first liquid in a hydrophilic region; a step of bringing the component-containing liquid into contact with the first liquid disposed on the hydrophilic region; a step of removing the first liquid and the second liquid to dispose the component on the hydrophilic region. The hydrophilic region is composed of a component-disposing region and a liquid-capturing region formed on the periphery of the component-disposing region. The liquid-capturing region comprises a surface represented by X—(CH 2 ) n S-(substrate) or Y—(CH 2 ) n —S-(substrate), where X represents N + R 3 Q − (Q represents Cl, Br, or I), OR, or halogen atom, R represents lower alkyl group, n represents a natural number of not less than 1 and not more than 3, Y represents COOH or OH, and m represents a natural number of not less than 1 and not more than 22.

Semiconductor package

A semiconductor package includes a substrate including a first semiconductor chip including a first wiring structure, a first bonding pad, and a first alignment key on the first wiring structure to be spaced apart in a first direction, a second semiconductor chip including a second wiring structure, a second bonding pad on the second wiring structure and connected to the first bonding pad, and a second alignment key on the second wiring structure to be spaced apart from the second bonding pad and not overlapping the first alignment key in the second direction, the first wiring structure including a first wiring pattern connected to the first bonding pad and not overlapping the first and second alignment keys in the second direction, and the second wiring structure including a second wiring pattern connected to the second bonding pad and not overlapping the first and second alignment keys in the second direction.

半導体装置および半導体基板、並びに半導体装置の製造方法

【課題】半導体基板の電極部金属層上にバンプを形成する際、はんだボールが金属層中心部から大きくずれて搭載された場合に、熱処理でリフローをかけてもはんだボールが金属層の中心部にセンタリングされない問題があった。 【解決手段】半導体基板１の電極パッド２上に金属層４１を形成する際、金属層４１の中心部から外周部に向かって放射状に、加えてその幅を外周部に向かうほど狭くなるような溝部４２を複数形成する。この金属層４１に形成された溝部４２をガイドとして利用することで、はんだボール６が金属層４１の中心部から大きくずれて搭載された場合でも熱処理でリフローをかければ、はんだボール６を金属層４１の中心部に確実にセンタリングすることが可能となる。 【選択図】図１

Packaged semiconductor devices and methods of packaging thereof

Packaging methods for semiconductor devices and methods of packaging thereof are disclosed. In some embodiments, a device includes a packaging apparatus and contact pads disposed on the packaging apparatus. The contact pads are arranged in an array of rows and columns. The contact pads include first contact pads proximate a perimeter region of the packaging apparatus and second contact pads disposed in an interior region of the packaging apparatus. A dam structure that is continuous is disposed around the second contact pads. The contact pads comprise a mounting region for a semiconductor device.

System and method for aligning micro light-emitting diodes

A method is provided for aligning micro light-emitting diodes. A platform is provided with arrays. Each of the arrays includes grooves. The platform is used to receive magnetic micro light-emitting diodes. Magnetic attraction and vibration are alternately exerted on the platform to cause the magnetic micro light-emitting diodes to fall into the grooves in a correct orientation. It is determined whether the magnetic micro light-emitting diodes fill the platform. Mass transfer is executed if the magnetic micro light-emitting diodes fill the platform.

Interposer, method for fabricating the same, and semiconductor package having the same

An interposer according to an embodiment of the present invention includes a base layer having opposite first and second surfaces, a wiring structure on the first surface of the base layer, an interposer protective layer disposed on the second surface of the base layer and having a pad recess with a lower surface of the interposer protective layer positioned at a first vertical level and a bottom surface of the pad recess positioned at a second vertical level that is higher than the first vertical level, an interposer pad of which a portion fills the pad recess of the interposer protective layer and the remaining portion protrudes from the interposer protective layer, and an interposer through electrode extending through the base layer and the interposer protective layer to the interposer pad, the interposer through electrode electrically connecting the wiring structure to the interposer pad.

具有用于有源管芯中的无金属缩减的街道中的基准的hbi管芯架构

本文公开的实施例包括半导体装置。在一个实施例中，管芯包括衬底，其中，衬底包括半导体材料。在实施例中，后端层在衬底之上，其中，后端层包括导电布线。在实施例中，管芯还包括从后端层和衬底的边缘延伸出的突起。在实施例中，基准在突起的表面上。

显示面板以及包括其的显示装置

本发明公开一种显示面板以及包括其的显示装置。显示面板可以包括：基板，包括显示区域以及位于显示区域的周边的焊盘区域；多个像素，配置于基板上的显示区域；以及多个焊盘，配置于基板上的焊盘区域并与多个像素电连接。多个焊盘各自可以包括：第一导电层；第一凸出部，配置于第一导电层上；第二凸出部，配置于第一导电层上并具有小于第一凸出部的厚度的厚度；以及第二导电层，配置于第一导电层上并覆盖第一凸出部以及第二凸出部各自的上面。

半导体封装

一种半导体封装包括：第一半导体芯片，包括第一布线结构；在第一布线结构上以在第一方向上间隔开的第一接合焊盘和第一对准标记；第二半导体芯片，包括第二布线结构；在第二布线结构上并与第一接合焊盘连接的第二接合焊盘；以及在第二布线结构上以与第二接合焊盘间隔开并且在第二方向上不与第一对准标记重叠的第二对准标记，第一布线结构包括第一布线图案，第一布线图案连接到第一接合焊盘，并且在第二方向上不与第一对准标记和第二对准标记重叠，以及第二布线结构包括第二布线图案，第二布线图案连接到第二接合焊盘，并且在第二方向上不与第一对准标记和第二对准标记重叠。

用于凸块下金属结构的套环及相关联的系统及方法

本申请涉及用于凸块下金属结构的套环及相关联的系统和方法。一种半导体裸片包含：半导体材料，其具有固态组件；及互连件，其至少部分延伸穿过所述半导体材料。凸块下金属UBM结构形成于所述半导体材料上方且电耦合到对应互连件。套环包围所述UBM结构的侧表面的至少一部分，且焊接材料安置于所述UBM结构的顶面上方。

본딩 구조체, 이것의 제조방법 및 이를 제조하기 위한 본딩 장치

본딩 구조체, 이것의 제조방법 및 이를 제조하기 위한 본딩 장치에 관한 기술이다. 본딩 구조체는 제 1 본딩 패드들을 포함하는 제 1 웨이퍼, 상기 제 1 본딩 패드들과 본딩될 제 2 본딩 패드들을 포함하는 제 2 웨이퍼. 상기 제 1 웨이퍼의 소정 부분에 위치되고, 유도 전류에 의해 일시적으로 자성을 갖는 적어도 하나의 제 1 얼라인먼트 키, 및 상기 제 1 얼라인먼트 키와 대응되도록 상기 제 2 웨이퍼의 소정 부분에 위치되는 제 2 얼라인먼트 키를 포함할 수 있다.

层叠封装型半导体封装

提供了一种层叠封装(POP)型半导体封装，该POP型半导体封装包括下封装，该下封装具有第一尺寸并且包括下半导体芯片在其中的下封装基板、在下封装基板和下半导体芯片上的上再分布结构、和对准标记。该POP型半导体封装还可以包括上封装，该上封装具有小于第一尺寸的第二尺寸并且包括上封装基板和上半导体芯片。上封装基板可以安装在下封装的上再分布结构上并且电连接到下封装，并且上半导体芯片可以在上封装基板上。对准标记可以用于识别上封装，并且对准标记可以在下封装上在上封装的外边界下方和附近。

半导体装置

实施方式提供一种能够确保各晶片间的接合强度及导通性的半导体装置。实施方式的半导体装置具有第1晶片、第1配线层、第1绝缘层、第1电极、第2晶片、第2配线层、第2绝缘层、第2电极和第1层。第1电极具有第1面、第2面、第3面及第4面。第2电极具有第5面、第6面、第7面、第2侧面及第8面。第1层设于第4面与第1绝缘层中的将第4面包围的部分之间，从第3面在第1方向上远离而设置。

显示设备

显示设备包括下基板、子像素结构、滤光器层、滤色器层、上基板和对齐结构。下基板具有显示区域和围绕显示区域的外围区域。子像素结构被布置在下基板上的显示区域中。滤光器层被布置在子像素结构上。滤色器层被布置在滤光器层上。上基板被布置在滤色器层上。对齐结构被布置在上基板的底表面上的外围区域中，并且对齐结构包含与形成滤光器层和滤色器层的材料相同的材料。

键合结构、制造其的方法以及用于制造其的键合装置

本公开涉及键合结构、制造其的方法以及用于制造其的键合装置。键合结构可以包括第一晶片、第二晶片、至少一个第一对准键和第二对准键。第一晶片可以包括第一键合焊盘。第二晶片可以包括键合到第一键合焊盘的第二键合焊盘。第一对准键可以设置到第一晶片。第一对准键可以通过感应电流而具有暂时磁性。第二对准键可以设置到第二晶片。第二对准键可以对应于第一对准键。

封装结构

本公开实施例提供一种封装结构，包含：第一内连线结构，形成于第一基板之上，其中所述第一内连线结构包含第一金属层；第二内连线结构，形成于所述第二基板之下；以及接合结构，位于所述第一内连线结构和所述第二内连线结构之间，其中所述接合结构包含第一金属间化合物和第二金属间化合物，所述第一金属间化合物的一部分从所述第二金属间化合物的复数个侧壁表面突出，且所述第一金属间化合物和所述第二金属间化合物之间存在晶界。本公开实施例也提供一种封装结构的形成方法。

一种集成电路与微机电系统的直接键合装置及制备工艺

一种集成电路与微机电系统的直接键合装置，包括太阳能电池，平坦化氧化层，对准金属接触部分，金属互连部分，焊点；平坦化氧化层与带有导电连接和密封的对准金属接触部分在低温直接键合，实现金属互连部分与高气密性的结合，金属互连部分和太能电池通过深硅刻蚀技术进行填充，焊点位于金属互连部分上。一种集成电路与微机电系统的直接键合装置制备工艺，平坦化氧化层表面上带有用于导电连接和密封的校准金属层，表面清洗或活化，校准，然后低温键合；金属能是合金、焊料或纯金属键合在一起。本发明的优点：本发明所述的集成电路与微机电系统的直接键合装置及制备工艺，原理结构简单，工艺稳定，提高了产品可靠性。

Collars for under-bump metal structures and associated systems and methods

The present technology is directed to manufacturing collars for under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects and associated systems. A semiconductor die includes a semiconductor material having solid-state components and an interconnect extending at least partially through the semiconductor material. An under-bump metal (UBM) structure is formed over the semiconductor material and is electrically coupled to corresponding interconnects. A collar surrounds at least a portion of the side surface of the UBM structure, and a solder material is disposed over the top surface of the UBM structure.

Electric apparatus including electric patterns for suppressing solder bridges

An electric apparatus may include a plurality of electric patterns arranged on a substrate. Each of the electric patterns may include a pad for connection with a solder ball, an electrical trace laterally extending from a portion of the pad to allow an electrical signal to be transmitted from or to the pad, a first dummy trace laterally extending from other portion of the pad, and a first connection line connecting the first dummy trace to the electrical trace. The first dummy trace may be provided at a position deviated from a straight line connecting the pad to the electrical trace.

Methods and apparatus for package with interposers

Methods and apparatus for an interposer with dams used in packaging dies are disclosed. An interposer may comprise a metal layer above a substrate. A plurality of dams may be formed above the metal layer around each corner of the metal layer. Dams may be formed on both sides of the interposer substrate. A dam surrounds an area where connectors such as solder balls may be located to connect to other packages. A non-conductive dam may be formed above the dam. An underfill may be formed under the package connected to the connector, above the metal layer, and contained within the area surrounded by the dams at the corner, so that the connectors are well protected by the underfill. Such dams may be further formed on a printed circuit board as well.