BACKSIDE CMOS COMPATIBLE BIOFET WITH NO PLASMA INDUCED DAMAGE

A subsequent disclosure different features of the present invention for implementing number of different embodiment examples or examples found to provide is appreciated. Examples of unique components and arranged of the present disclosure to simplify hereinafter. described. As well as these are examples only and the user makes a involves limiting the is not intended. Furthermore, subsequent in the description on or characterized number 2 number 1 number 2 characterized on number 1 and number 2 characterized the formation of features are directly formed in contact may include a in the embodiment, number 1 and number 2 features are direct contact may not be added to features are placed between the number 1 and number 2 features that can be formed may include in addition are in the embodiment. Further more, "upper", "front", "rear view" and "lower" and terms such relative a reference to the relative elements utilized to provide relationships any absolute direction and is intended to suggest is not. Various features are simple and clear different for any accumulation can be to be drawn and.

In biological field-effect transistor (BioFET), semiconductor between contacts source and drain thereof conductivity of controlling metal-oxide-semiconductor field-effect transistor (metal-oxide-semiconductor field-effect transistor; MOSFET) act as a surface receptor (receptor) gate of a immobilized probe molecules (immobilized probe molecules) of producing the same and to the layer (biofunctionalized layer) or or biochemical-compatible layer is replaced by. Essentially, the semiconductor BioFET biosensor field-effect transducer is. The revenue for determining BioFET (label-free) no-label are is possibility of operation. In particular, BioFET, e.g. a, fluorescent type or radioactive probe having analyte (analyte) in label such as a label-consuming that the time-layers are of operation enables preventing.

Traditional BioFET to a token detection BioFET of sensitive surface that is attached to is targeted to the sensitive surface molecules or receptor biomolecules or bio-entity binds (binding) of the transducer and cause a conductivity modulation is. Target biomolecules or bio-entity coupled to receptor or a fixed sensitive surface BioFET when the drain current of circuit element which may vary by potential from sensitive surface is. This change in drain current can be measured and the pressure, receptor and target biomolecules or bio-entity of bonding (bonding) can be identified. Wide variety of biomolecules, and a bio-entity (enzymes) enzymes ions, antibodies, ligands (enzymes), receptor are, peptides (peptides), oligonucleotides (Oligonucleotides) nucleotides, of cells, organisms, and tissue fragments (pieces of tissue), such as the BioFET of sensitive surface function can be used. For example, to detect ssDNA (single-stranded deoxyribonucleic acid), BioFET sensitive surface of a fixed complementary ssDNA strand can be functioning at (strand). Furthermore, diverse debris, such as tumor indicators (tumor markers) to detect protein, the sensitive surface of BioFET functions as single cell antibodies (monoclonal antibodies) can be.

One example of a biosensor BioFET a is connected to a gate of the has sensitive surface to top of the floating gate. The floating gate a metal interconnect line stack of the stop layer (or multi-layer interconnection (MLI) connected) through is connected to gate structure of BioFET. Onto a gate electrode of MLI layers are variety of metal during formation process in addition to damage due to an effect antenna included in a weight percent. In such BioFET, shift-modulation reaction (potential-modulating reaction) the final (upper) external surface or metal layer formed on top of one MLI take place in a dielectric surface, is sensed indirectly by means of to BioFET. Sensitivity of device relate embodiment but associated MLI is due to the presence of parasitic capacitances is detrimental in is reduced can be. As a result, dimensions plate minimized perceived generally sufficiently detectable positive potential-modulated reaction to occur is purpose :. Minimized perceived BioFET density limiting the ultimately dimension plate.

In another, BioFET of biomolecules, the gate or on the gate dielectric directly or receptor is voltage and resetting a binding through. These "directly sensing" the MLI BioFET without parasitic capacitance associated with a target biomolecules, for directly sensing the.. In terms of its constituent the sensing to form a well to for removing liquid substance MLI BioFET on requests a shift-modulation surface reactions are generated (fluidic environment) a fluid environment a exposed in the gate dielectric or gate electrode. The floating gate type than these BioFET more sensitive but for reasons of several is conductive to construct a into. Etched sensing well for example, in having a high aspect ratio than 30, a high energy plasma etching is carried out through. Sensing well etched in addition the aspect ratio high limit a sensing well profile. A high energy plasma etching due to charge-induced damage is able to damage the gate electrode. Sensed so that it is easier to etching to reduce the aspect ratio well in one attempt a of the metal layers one or restricted by the number of and generates a foot spot welder layers and SiO 2. Metal layer of the device of interconnected routing and integrated options, for example, BioFET circuit for controlling a limit the type and the number of the. Process for an arrangement highly sensitive to the driving direction and speed of in addition, the misalignment to expose metal well sensing peripheral MLI or sensing surface area design is less is because it can be.

In yet another version, biomolecules, rear view of the substrate is disposed adjacent to gate from the side. In this example, sensitive surface of the substrate rear view of rear view through the light emitting transistor gate is formed on one side thereof. Interconnected this example etched through the plurality of layers of to the floating gate biosensor is substantially greater than the that are sensitive the gate close enough to the a difficulty to have to be placed in a.. In Figure 1 has a bio-organic field effect transistor (BioFET) is the exemplary method for producing. Method (100) of complementary metal-oxide-semiconductor (complementary metal-oxide-semiconductor; CMOS) processes or conventional at least one compatible with using process steps to form a BioFET may include a. Method (100) are the additional step of prior to, its intermediate to, and may be ground to provide the media at a later time from, and certain of the below described steps that at additional method either replace for in the embodiment can be removed is appreciated that. Furthermore, method (100) by means of conventional CMOS techniques having characteristics of process includes the steps of and, described only briefly wherein the is appreciated that.

Method (100) block is provided a substrate (102). starting at. Substrate can be a semiconductor substrate. Semiconductor substrate can be a silicon substrate. Alternatively, another element such as germanium substrate semiconductor; a silicon carbide compound semiconductor including; and semiconductor or alloy including silicon germanium may include a combinations thereof. In some in the embodiment, semiconductor-on-insulator substrate (semiconductor on insulator; SOI) substrate has. As shown in Figure 2, be infused substrate SOI oxygen (SIMOX) and/or other suitable processes for the separation by formed by the process such as buried oxide (BOX) layer (203) may include a. In addition BOX layer SOI substrate (203) on the two opposite sides of a semiconductor layer number 1 (201) and number 2 semiconductor layer (205) includes. SOI substrate side surface or number 1 number 1 (207) the FET. side device in which the transfer gate is formed. SOI of surface or number 2 number 2 side (209) thinned in subsequent operation the substrate is a rear view side. Substrate n-well such as p-wells and may include doped regions. The present disclosure in, wafer attached to and conductive heating element and and in and uniformly formed is workpiece including these various features. Various wafer that can be used on stages CMOS process is used to is processed. Various stages determined, lower an integrated wafer is separated in individual die packaged.

Also 1a again a, method is then field effect transistor (FET) (210) of the substrate number 1 side (207) block formed on (104) advances to. FET (210) has a gate structure (dielectric (215) and electrode (217) includes), source region (211 or 213), drain region (211 or 213) and source and drain regions (211 and 213) a channel region is interposed between the (219) may include a. Source, drain and/or channel region is formed on the active region of the semiconductor substrate. The semiconductor layer active region (201). is part of. FET (210) the n-type FET (nFET) or p-type FET (pFET) can be. For example, depending upon the configuration FET source/drain regions are the n-type dopants or p-type dopants may include a. The gate dielectric layer gate structure (215), gate electrode layer (217) and/or other suitable may include layers. In in the embodiment, gate electrode (217) is polysilicon. Another exemplary cu a gate electrodes, W, Ti, Ta, Cr, Pt, Ag, metal such as Au; TiN, TaN, NiSi, CoSi, such as metal compounds, suitable; their combinations; and/or other suitable including a conductive material including metal gate electrode. In in the embodiment, is a silicon oxide gate dielectric. Another exemplary the gate dielectric the silicon nitride, silicon oxynitride, high dielectric constants (high k) dielectric material and/or having includes the combinations thereof. K of materials high examples hafnium silicate, hafnium oxide, zirconium oxide, aluminum oxide, tantalum 5 oxide (pentoxide), hafnium dioxide-alumina (HfO₂-Al₂ O₃) alloy, includes the or a combination thereof. FET a photo lithography; ion implantation; diffusion ; physical vapor deposition (physical vapor deposition; PVD), metal vaporizing (metal evaporation) or sputtering, chemical vapor deposition (chemical vapor deposition; CVD), plasma-enhanced chemical vapor deposition (plasma-enhanced chemical vapor deposition; PECVD), atmospheric chemical vapor deposition (atmospheric pressure chemical vapor deposition; APCVD), marking multi-page facsimile CVD (LPCVD), high density plasma CVD (high density plasma CVD; HDPCVD), atomic layer CVD (atomic layer CVD; ALCVD), spin on coating (spin on coating) such as deposition; wet etching, dry etching, including etching and plasma etching; and/or other suitable CMOS processes conventional processing modules, such as using a CMOS process can be formed.

Method (100) the a metal interconnect layers, dielectric layers, passivation layers, bonding metal layers, ; and a perfect semiconductor device typically formed with core or any other material layers including additional layers formed on the on FET may include a. In Figure 3, layer (303) the FET and the carrier substrate (301) between is arranged on FET. Layer (303) a multi-layer interconnection connected (multi-layer interconnect; MLI) may comprise an structure. MLI structure conductive lines, conductive vias and/or interposed dielectric layers (for example, interlayer dielectric (interlayer dielectric; ILD)) may include a. MLI source and drain structure (211 and 213) and gate electrode (217) FET (210) in physical and electrical connection. provided received event can be provided to. Data communication operating the copper, aluminum, tungsten, tantalum, titanium, nickel, cobalt, metal silicide, metal nitride, polysilicon, combinations thereof and/or possibly also one or more layers or lining to including, of dissimilar materials may include a. Interposed or interlayer dielectric layers (for example, (are) ILD layer) silicon dioxide, fluorine-containing silicon glass (fluorinated silicon glass; FGS), (product Dow Chemical of lake Michigan) SILK, BLACK DIAMOND (California, Applied Materials it will grow, of the knitted sheet of product), and/or other insulating materials in may include a. The MLI CVD, PVD, ALD, plating, spin-on coating and/or to other entities such as process CMOS manufacturing conventional suitable processes can be formed by.

When the, carrier substrate (301) structural integrity of a semiconductor substrate without affecting the rear view side of semiconductor substrate (209) under allows subsequent operations. Carrier substrate (301) by the bonding attached semiconductor substrate. In some in the embodiment, carrier substrate is then bonded to layer MLI includes a multiple input signature register. In one in the embodiment, of the substrate carrier substrate ILD MLI layers and/or is bonded to a passivation layer formed on a. Carrier substrate including dissolved, diffusion, reel tic reason (eutectic), and/or other suitable bonding method using the device. can be attached to. An exemplary carrier substrate compositions contain silicon, glass and quartz includes. In some in the embodiment, carrier substrate (301) the interconnecting features, bonding sites, defined cavities and/or other suitable features and other functions, such as may include a. The carrier substrate, being subsequent processing (for example, after thinned (thining)) can be removed during.

Method (100) is then active region of FET the side rear view of the substrate block (106) advances to. The dependent on the type of substrate, plurality of method are usually FET the provision of a channel region including the active region is exposed can be used. According to various in the embodiment, substrate is thinned from rear view. Number 1 (grinding) for green S30, wet etching, dry etching, plasma etching and/or other suitable processes can be achieved by. FET through charge on the active region of a plasma induced damage (plasma induced damage; PID) to prevent, this plasma etching non-thinned last or at least are stored in the frame buffer may be used as a step in. In along parts in the embodiment, wet etching or non-plasma dry etching from rear view fully active region thinned region is used. In other in the embodiment, plasma etching, which may include number 1 to reduce the thickness of the wafer for a S30 and finally lands etching operation a first active region of side rear view of the substrate to expose use of non-plasma etching.

Also the substrate 1b is silicon-on-insulator (silicon-on-insulator; SOI) substrate associated with when the present disclosure of a variety of in the embodiment according to method (100) of blocks (106) the flow is shown that features. 2 substrate SOI buried oxide sometimes between layers test for the packages include unique referred to as the layer (BOX) has dielectric film. FET has the ordinary unique number 2 on an opposing side of the dielectric film thinner than semiconductor layer is formed on semiconductor layer number 1. Number 2. is removed semiconductor layer. Also blocks of 1b (152) in, SOI substrate is removed from the semiconductor layer. Removing the block semiconductor layers (104) that is formed in a semiconductor layer is opposite from FET. Mechanical or chemical connection to the pleats removal can be achieved by means of a non-. For example, mechanical means a chemical mechanical polishing (chemical mechanical polishing; CMP), such as the polishing or include green.. TMAH or HNA the chemical means, which is intended, such as wet etching or plasma and non-plasma etching includes dry etching including. 3 also also Figure 4 shows a semiconductor layer from (205) wafer after to the removal of (400) is in a. Wafer (400) the FET (210) on both sides of unique dielectric layer (203) and carrier substrate (301) includes.

Also blocks of 1b (154) in, is thinned is dielectric film unique. Unique dielectric membrane is about coated with a silicon oxide layer of nanometer to hundreds are can be. In some in the embodiment, unique the dielectric layer buffered oxide etch (buffered oxide etch; BOE) or non-plasma dry etching such as wet etching is thinned using. Also the dielectric layer unique 5a depicted at unique dielectric layer (503), such as or may be partially removed, or also such as examples of the embodiment depicted at 5b is completely removed. Unique dielectric layer is partially removed, the etching solution of the etching plasma- pak can be used for. In some in the embodiment, unique dielectric layer is thinned less than or about 2000 angstroms.

According to various in the embodiment, block (154) unique dielectric layer after thinned partial, a photoresist pattern is block (154) remaining portion of unique dielectric layer is formed on. A photoresist pattern is block (158) in activity of FET to the subsequent non-plasma from being etched protects parts a unique dielectric layer. Non-plasma etching a plasma without complicating steps of a dry etch, or can be wet etching. FET (210) non-plasma etching channel region of (219) having the trench to overlap with the lower (bottom) (505) to form a. Non-plasma etching the channel region (219) the exposed surface of (509) plasma-induced damage is used to prevent. Unique dielectric layer (203) for thinned by, trench (505) has a low aspect ratio, for example, about 5 or even has about 1 or less. During etching a low-aspect ratio allows for fine profile control can compromise the accuracy of the temperature uniformity surface a sharp edge which are prevents form a (sharp corners). In some in the embodiment, trench (505) sidewall of profile has a substantially. straight.

Also as shown in 5b of the curve, of several in the embodiment according to, unique dielectric layer (203) is removed is completely number 1 semiconductor layer (201) the surface (507) is exposed. Blocks of complete removal Figure 1b (154 and 158) generated from one or more operations such as can be. However surface (507) last operation that exposes a surface (507) for a plasma-induced damage (PID) plasma to prevent the capacity ratio thereof can reach without complicating steps.

Structure in which the photoresist pattern is block (156) provided with a in, block (160) in, is photoresist is removed. Striping (stripping) such as ozone ashing and less-PID (ozone ashing) process is removing photoresist can be used. Trench (505) the exposed surface of (509) and number 1 semiconductor layer (201) the exposed surface of (507) the plasma-induced damage (PID) is strong susceptibility to, some plasma ashing processes photoresist pattern is removed. may or may not be used.

Also 1a again a, block (108) is formed opening in non-oxidizing. The 1c also in the embodiment of a variety of disclosure according to method (100) of blocks (108) the flow is shown that features. Also blocks of 1c (182) in, sensing layer are deposited over a wafer. Detecting film trench (505) the exposed surface of (509) and number 1 semiconductor layer (201) the exposed surface of (507) can be formed on. In addition circuit wherein the interfacial layer, which are referred to biomolecules, detecting film to binding entities or bio-compatible (for example, friendly).. For example, detecting film for biomolecules, or bio-entity binding interface by using the mask pattern.. Detecting film dielectric material, conductive material and/or receptors for holding other suitable material may include a. Exemplary surface materials high-k dielectric films, metals, metal oxides, dielectric and/or other a material that is suitable including. As an example of additional, an exemplary surface materials HfO₂, Ta₂ O₅, Pt, Au, W, Ti, Al, cu, such oxides of metals, SiO₂, Si₃ N₄, Al₂ O₃, TiO₂, TiN, ZrO₂, SnO, SnO₂; and/or other a material that is suitable including. Detecting film for example, physical vapor deposition (PVD) (sputtering), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atmospheric chemical vapor deposition (APCFD), low pressure CVD (LPCVD), high density plasma CVD (HDPCVD), or atomic layer CVD (ALCVD) such as using CMOS process can be formed. In in the embodiment, detecting film includes the plurality of layers.

Also 6a and 6b trenches (505) the exposed surface of (509) (also 6a) and number 1 semiconductor layer (201) the exposed surface of (507) (also 6b) detection film formed on a. shown. In 6a also, unique residual detecting film dielectric layer (503) and trench-type capacitor and (505) surface of the proximal stomach, and sidewalls of are deposited over a wafer on. In 6b also, detecting film entire surface of the semiconductor layer (507) are deposited over a wafer on.

Also 1c again a, block (184) in, a photoresist pattern is to protect portions of sensing 64 are formed on surface. Overlies a channel area of FET is is part of. Support layer that is unprotected portions that the block (186) is removed from of etch processes. A PID is apt to become a etching process since a portion having a protected under a plasma etching including any of a known etching process may involve. Also 7a and 7b each surfaces remaining on the surface (701) is shown that.. In also 7a, surface (701) the trench (505) but viewed only lower surface of, in some in the embodiment, trench (505) at least one surface (701) can be covered in addition in. Surface (701) the channel region (219) and completely overlying a, source and drain regions (211 and 213) covers part. Partial source and drain regions (coverage) the FET design and surface covered with a planarizing layer (701) with area requirements adjusted based on the of can be. In 7b also, surface (701) the channel region (219) the source and drain regions completely overlying a (213 and 211) covers part. Surfaces of biofilm on-molecules not certain to prevent surface opposite, barrier layer or passivation layer (702) other than those can be is deposited. Passivation layer (702) the silicon nitride, silicon oxide, or other. may be solid-state dielectric layer. Blockers (702) has a bio-molecules binding cannot be or low affinity (low affinity) drug in a liquid or solid can be. One example is a HMDS (hexamethyldisiloxane). In another, a protein, such as BSA (Bovine Serum Albumin) may be used as blocker. Barrier layer/passivation layer (702) the surface (701) may be thicker than or thin.

Etching and a cluster anion or heteroborate cluster anion (passivating) or after optionally additional blocker, photoresist block (188) in PID-free is removed at removing photoresist. In some in the embodiment, surface (601) without being and etching a patterned surfaces each FET is left behind.

Also 1a again a, block (110) in, membrane treatment or enzyme, antibodies, ligands, peptide, nucleotide (nucleotide), cells of the target tissues or organs, organism or tissue fragments such biomolecules or target is provided with or the receptacle for the detection of is binding on fuse using interfacial layer. For example, to detect ssDNA (single-stranded deoxyribonucleic acid), ssDNA complementary fixed detecting film can be functioning at strand. Furthermore, various such as indicator tumor to detect protein, single cell detecting film can be functioning at antibodies. Receptor molecules are self-assembled single layer (self-assembled monolayer; SAM) .may specifically be part of a peer. SAM the silane groups, silyl (silyl) groups, silanol groups, organophosphate (phosphonate) groups, amine groups, thiol (thiol) groups, groups [...] , alkene groups, alkyne groups, azido (azido) groups, or cusyody (expoxy) in the head of a group can take the groups. Receptor are SAM head of attached groups.

In some in the embodiment, as a general method for their chemical detecting film to influence the function (chemistry) or chemical substance coating treated with. or modified. For example, hydrophilic or detecting film having hydrophobic surface, .can be processed to. Other examples, a particular detecting film to have characteristics or magnetic conductive can be modified. Stamping receptor or membrane treatment (stamping) or wet from the storage tank from solution by absorption, and sputtering or gas deposition and induced by such a specific deposition of types can be produced by. Receptor a-contact printing (micro-contact printing), deep-pentanoic nano lithography after attachment or by using (dip-pen nanolithography), symmetrical with respect to receptor may be patterned by. Receptor attached to surface, surface biological agents on the channel region of biological materials are the electrical characteristic a by the presence can be detected by BioFET.

Also 1a again a, block (112) in, micro fluid channel or micro fluid well (microfluidic well) is formed on the fluorine-added carbon is sensed. Block (112) processing or materials and used dependent on the type of receptor 1a also the method (100) of blocks of (110) prior to or can be performed after. For example, some receptor a fluid channel or well forming structure can be corrupted during. In some in the embodiment, micro fluid channel or on well from the signal determining unit deposition polysilicon layer is formed there by means of an explosive. Also formed on the fluorine-added carbon a sense 9a/9b and 8a/8b microfluidic of cross-sectional drawing their. Also 8a trenches (505) is surface (601) provided on the. example. Also 8b has a unique dielectric layer completely removed and no trench (505) is example is formed. Both cases, bio compatibility material a substantially planar surface are deposited over a the wafer to form. Various examples, a bio compatible material and bio is photoresist compatibility. Photo-resist can be used, the reason is that photoresist layers surface without affecting the surface through a photolithography method is on the key are displayed by since correspondingly shaped. One example [...] epoxy-based resist lotto so as to activate SU-8^TM is. Such transparent photoresist isomorphic micro fluid externally during the operation thereof is that it is possible for is observed. Spin-on photoresist is deposited using tool by exposure to the ultra-violet is patterned to also 9a and 9b as depicted at to remove the well pixel cells are can be development. The bio compatible material and also 9a and 9b (801) is formed a microfluidic wells (901) includes. As shown, micro fluid wells (901) during the operation thereof biological fluid material surface (601) (, and any coating or receptor are) expose to.

In some in the embodiment, bio compatible material and photoresist is not. Bio compatible material and an epoxy, silicon, for example, PDMS (polydimethylsiloxane), or different PEG (Polyethylene glycol) can be organic polymer. Bio compatible material and mass may be deposited by e.g., by etching may be molded, for on BioFET. Bio compatibility material for example by molding, thereby enabling in addition, compression molding (compression molding) or molds (mold) contact process with electrochemical deposition, followed by hardening the injection molding through BioFET shape is selected by. can be deposited onto. Bio compatible material and (801) the near BioFET between surface and surface of the semiconductor layer (601) it possible to ensure a good adhesion with portions of is.

In another in the embodiment, micro fluid channel or well BioFET and a separate operation is formed separately from the. is attached at. Also 8c and 8d a sense film unit of carry/save adder/barrier layer (804) on pre-attached to later applied to wafer to reduce corner rounding of a micro fluid structures (803) a including cross-sectional drawing their. Micro fluid structures (803) BioFET the is formed separately from the wafer before the (diced) dicing device is individually attached. Micro fluid structures (803) the in addition BioFET device wafer level to allow the formation to devices on the wafer with 1 to 1 in mapping the package substrate can be formed as. Micro fluid structures (803) an anode bonding (anodic bonding) or adhesive. may be attached by bonding. Micro fluid structures (803) to surround the longitudinal central inlet/the, wells, channels, and a fluid operable to hold a may include a repository based on the. Micro fluid structures (803) biological flow directing (flow biological matter) material assist in processing analysis substance which may include further. For example, micro fluid structures (803) a micro pumps and valves, , electrophoretic or magnetic (magnetophoresis) for magnetic material or ferromagnetic-magnetic material, a combination of a winding vibration electrophoresis for the dielectric phoretic metals, or for specific genetic material may include a.

Micro fluid structures (803) production and/or in the CMOS processes it further BioFET is coupled to or can be bonding device, for example, micro fluid structures a standard conventional CMOS production furnace the possible out-of-the above manufactured using process and/or can be coupled to the device. In some in the embodiment, transistor of manufacturing entity separate BioFET entity number 2 main valve 23 and connected to fluid structures micro device. The formation of distinct fluid structures micro much more variety of materials to be used in a receiving node to permit a BioFET easily-damaged is not formed on allows when a larger process window. Micro fluid structures of attaching a heat discharging equipment a photoresist-based micro BioFET surface uniformity of surface fluid structures better variations may accommodate to may be important.

In another in the embodiment, micro fluid structures using a combination of actions can be formed. Also the 9c two portions of fluid structures 2 ; deposition and patterning sensed by a microfluidic well structure formed on the fluorine-added carbon (1001) and micro fluid well structure (1001) microstructures adhered to the fluid channels structures (1003) is having cross-sectional drawing of BioFET.

The present disclosure one aspect of biological field-effect transistor (biological field-effect transistor; BioFET) for producing method relates to, is the method, device and FET on a semiconductor substrate of the semiconductor substrate device developmental stage-said FET gate structure formed with number 1 on the surface including from the gate line, and applied; of semiconductor substrate surface number 2 developmental stage-a channel from the surface of the channel region exposed by non-plasma etching, each of which is; number 2 of semiconductor substrate in the aperture and formed on the channel regions of the surface includes forming a detection film. The method is in addition number 2 (thining) thinned semiconductor substrate from the surface and not on surface includes forming the new double hull, to the receptor (receptor) may further comprise a pump, wherein an enzyme receptor, antibodies, ligands, peptides, nucleotides (nucleotides), self-assembling molecules is selected from. Detecting film Si₃ N₄, Al₂ O₃, TiO₂, HfO₂, Ta₂ O₅, SnO, SnO₂ ,BaxSr_1-x TiO₃ can be and combinations thereof.

The present disclosure on the substrate SOI another aspect of method for producing BioFET relates to. The method on a semiconductor substrate is SOI FET device and developmental stage-said FET device of the semiconductor substrate formed on the surface number 1 and structure of gate gate structure the provision of a channel region in the semiconductor substrate under the sacrificial including; number 1 of semiconductor substrate then attaching a carrier substrate surface; semiconductor substrate remove a portion of from the surface of semiconductor substrate by exposing the channel region number 2 ; number 2 in the aperture formed on the channel regions of the surface of semiconductor substrate form a detection film; and fluid microstructures on a surface to form a well micro fluid channel or (microfluidic) includes.

In yet another aspect, the present disclosure a carrier substrate; number 1 BioFET device attached to a carrier substrate; and number 1 BioFET on devices disposed above the surface a microfluidic channel or micro fluid well is relates to a device having. Number 1 side of the semiconductor substrate device number 1 BioFET gate structure; gate structure close to the source region and the drain region in semiconductor substrate; source and drain regions is interposed between the channel region below the gate structure; and semiconductor substrate number 2 side channel region covering at least part of the right on includes detection film.

At least one of the in the embodiment these in describes in the embodiment, the present disclosure several than devices known in the art by using the mask pattern. advantages of. In subsequent advantages or benefits of discussed, in the embodiment these benefits in some results are and/or each may be present in an in the embodiment is not required in should is attention. Furthermore, different disclosure wherein characteristics and different in the embodiment provides advantages, various that, replacement concept and of exclusive cement chemistries and adapted without range disclosure can be carried out is appreciated that.