ЭЛЕКТРОННОЕ УСТРОЙСТВО, СОДЕРЖАЩЕЕ ОРГАНИЧЕСКИЕ МАТЕРИАЛЫ

ПЕРЕКЛЮЧАЮЩИЙ ЭЛЕМЕНТ И СПОСОБ ИЗГОТОВЛЕНИЯ ПЕРЕКЛЮЧАЮЩЕГО ЭЛЕМЕНТА

Переключающий элемент включает в себя полупроводниковую подложку, которая включает в себя первый слой полупроводника n-типа, базовый слой р-типа, образованный эпитаксиальным слоем, и второй слой полупроводника n-типа, отделенный от первого слоя полупроводника n-типа базовым слоем, изолирующую пленку затвора, которая покрывает зону, перекрывающую поверхность первого слоя полупроводника n-типа, поверхность базового слоя и поверхность второго слоя полупроводника n-типа, а также электрод затвора, который расположен напротив базового слоя в пределах изолирующей пленки затвора. Граница раздела между первым слоем полупроводника n-типа и базовым слоем включает в себя наклонную поверхность. Наклонная поверхность наклонена таким образом, что глубина базового слоя увеличивается при увеличении расстояния в горизонтальном направлении от края базового слоя. Наклонная поверхность расположена под электродом затвора. Изобретение обеспечивает более эффективное ослабление электрического поля, воздействующего ...

Lokalverbindungen für integrierte Schaltungen

Kontaktbildungsverfahren und zugehörige Struktur

Ein Verfahren und eine Struktur zum Bilden eines Via-First-Metall-Gate-Kontakts umfasst das Abscheiden einer ersten dielektrischen Schicht über einem Substrat, das eine Gate-Struktur mit einer Metall-Gate-Schicht aufweist. Eine Öffnung wird innerhalb der ersten dielektrischen Schicht gebildet, um einen Abschnitt des Substrats freizulegen, und eine erste Metallschicht wird innerhalb der Öffnung abgeschieden. Eine zweite dielektrische Schicht wird über der ersten dielektrischen Schicht und über der ersten Metallschicht abgeschieden. Die erste und die zweite dielektrische Schicht werden geätzt, um eine Gate-Durchkontaktierungsöffnung zu bilden. Die Gate-Durchkontaktierungsöffnung legt die Metall-Gate-Schicht frei. Ein Abschnitt der zweiten dielektrischen Schicht wird entfernt, um eine Kontaktöffnung zu bilden, welche die erste Metallschicht frei legt. Die Gate-Durchkontaktierungs- und Kontaktöffnungen verschmelzen, um eine Verbundöffnung zu bilden. Eine zweite Metallschicht wird innerhalb ...

Verfahren und Struktur für eine Halbleitervorrichtung mit einer Gatespacer-Schutzschicht

Ein Verfahren zum Ausbilden einer Halbleitervorrichtung umfasst ein Bereitstellen einer Vorstufe. Die Vorstufe umfasst ein Substrat, einen Gatestapel über dem Substrat, eine erste dielektrische Schicht über dem Gatestapel, einen Gatespacer auf Seitenwänden des Gatestapels und auf Seitenwänden der ersten dielektrischen Schicht, und Source- und Drainkontakte (S/D-Kontakte) auf gegenüberliegenden Seiten des Gatestapels. Das Verfahren umfasst ferner ein Aussparen des Gatespacers, um die Seitenwände der ersten dielektrischen Schicht zumindest teilweise freizulegen, aber nicht die Seitenwände des Gatestapels freizulegen. Das Verfahren umfasst ferner ein Ausbilden einer Spacerschutzschicht über dem Gatespacer, der ersten dielektrischen Schicht und den S/D-Kontakten.

Halbleiterstruktur mit lokaler zu einer Gate-Struktur selbstjustierten Zwischenverbindungsstruktur und statische Speicherzelle diese beinhaltend und Verfahren diese zu bilden

Halbleiterstruktur, die eine Vielzahl von parallelen, ein leitfähiges Material beinhaltenden Strukturen aufweist, die parallele Seitenwände aufweisen und sich auf einem Halbleitersubstrat 8 befinden und ein konstantes Rastermaß in einer horizontalen Richtung senkrecht zu den parallelen Seitenwänden aufweisen, wobei: eine der Vielzahl von parallelen, ein leitfähiges Material beinhaltenden Strukturen (76, 80, 36, 38, 73) ein U-förmiges Gate-Dielektrikum 80 und einen metallischen Gate-Leiter-Elektroden-Anteil 76 beinhaltet, der ein metallisches Material aufweist; und eine weitere der Vielzahl von parallelen, ein leitfähiges Material beinhaltenden Strukturen eine Kontakt-Durchkontakt-Struktur 73 beinhaltet, die das metallische Material aufweist und mit einem von einem Source-Bereich und einem Drain-Bereich 34 eines Transistors leitfähig verbunden ist, der sich auf dem Halbleitersubstrat befindet; und ein Abstand zwischen einer Außenwand des U-förmigen Gate-Dielektrikums und einer Seitenwand ...

Halbleitervorrichtung und Verfahren zur Herstellung einer Halbleitervorrichtung

... [Aufgabe] Bereitstellen einer Halbleitervorrichtung, bei der die Erzeugung einer Verzerrung eines Signals unterdrückt wird, und eines Verfahrens zur Herstellung der Halbleitervorrichtung.[Lösung] Eine Halbleitervorrichtung, die Folgendes beinhaltet: ein Transistorgebiet, in dem ein Feldeffekttransistor bereitgestellt ist, und ein Verbindungsgebiet, in dem eine Metallschicht bereitgestellt ist, die elektrisch mit dem Feldeffekttransistor verbunden ist. Das Verbindungsgebiet beinhaltet eine Isolierschicht, die zwischen der Metallschicht und einem Substrat bereitgestellt ist, und eine Schicht mit niedriger Permittivität, die in der Isolierschicht unter der Metallschicht bereitgestellt ist und eine niedrigere Permittivität als die Isolierschicht aufweist.

Halbleiterprodukt und Verfahren zur Herstellung eines Halbleiterprodukts

Halbleiterprodukt (1) mit DOLLAR A - einem Substrat (2), das eine Substratfläche (22) aufweist, DOLLAR A - einer Vielzahl von Wortleitungen, die in einem Abstand voneinander angeordnet sind und entlang einer ersten Richtung (x) verlaufen, DOLLAR A - einer Vielzahl von leitfähigen Kontaktstrukturen (24), die zwischen den Wortleitungen vorgesehen sind, und DOLLAR A - einer Vielzahl von Füllstrukturen (30), wobei jede Füllstruktur (30) zwei jeweilige Kontaktstrukturen (24) voneinander trennt, die zwischen zwei jeweiligen Wortleitungen (10) angeordnet sind, wobei die jeweiligen zwei Kontaktstrukturen (24) in einem Abstand voneinander entlang der ersten Richtung (x) angeordnet sind, DOLLAR A wobei die Kontaktstrukturen (24) eine Oberseite (24a) besitzen, die in einem Abstand von der Substratfläche (22) angeordnet ist, und bis zur Substratfläche (22) reichen und DOLLAR A wobei die Kontaktstrukturen (24) an der Substratfläche (22) eine Breite (W) entlang der ersten Richtung (x) besitzen, die größer ...

REDUZIERUNG VON LADUNGSVERLUSTEN IN NICHTFLÜCHTIGEN SPEICHERZELLEN DURCH PHOSPHORIMPLANTATION IN PECVD-NITRID/OXYNITRID-FILMEN

Verbindungsstruktur einer Halbleitereinrichtung und ihr Herstellungsverfahren

Verfahren zur Bearbeitung eines Trägers, Verfahren zur Herstellung einer Ladungsspeicherzelle, Verfahren zur Bearbeitung eines Chips und Verfahren zum elektrischen Kontaktieren einer Abstandhalterstruktur

Ein Verfahren (100) zur Bearbeitung eines Trägers gemäß verschiedenen Ausführungsformen kann enthalten: Bilden einer Struktur über dem Träger, wobei die Struktur mindestens zwei benachbarte Bauelemente aufweist, die mit einem ersten Abstand zueinander angeordnet sind (110); Abscheiden einer Abstandhalterschicht über der Struktur, wobei die Abstandhalterschicht mit einer Dicke größer als eine Hälfte des ersten Abstandes abgeschieden werden kann, wobei die Abstandhalterschicht elektrisch leitendes Abstandhaltermaterial enthalten kann (120); Entfernen eines Teils der Abstandhalterschicht, wobei Abstandhaltermaterial der Abstandhalterschicht in einem Bereich zwischen den mindestens zwei benachbarten Bauelementen verbleiben kann (130); und elektrische Kontaktierung des verbleibenden Abstandhaltermaterials (140).

Integrierter Transistor

Es ist ein integrierter Transistor für eine elektrische Vorrichtung, etwa eine DRAM-Speicherzelle, und ein Verfahren zur Herstellung desselben vorgesehen. Ein Graben wird in einem Substrat ausgebildet und ein Gate-Dielektrikum und eine Gate-Elektrode werden in dem Graben des Substrats ausgebildet. Source/Drain-Bereiche werden in dem Substrat auf gegenüberliegenden Seiten des Grabens ausgebildet. In einer Ausführungsform wird der Source- oder der Drain-Bereich mit einem Speicherknoten verbunden und der andere des Sourüce- und des Drain-Bereichs wird mit einer Bitleitung verbunden. In dieser Ausführungsform kann die Gate-Elektrode mit einer Wortleitung verbunden werden, um eine DRAM-Speicherzelle auszubilden. Ein dielektrischer Wachstumsmodifikator kann in Seitenwände des Grabens implantiert werden, um die Dicke des Gate-Dielektrikums einzustellen.

Verfahren zum Herstellen von Speicherzellen, die durch eine hohlraumfreie dielektrische Struktur getrennt sind

Verschiedene Ausführungsformen der vorliegenden Anmeldung sind auf einen integrierten Chip mit Speicherzellen gerichtet, die durch eine hohlraumfreie dielektrische Struktur getrennt sind. Bei einigen Ausführungsformen wird ein Paar Speicherzellenstrukturen auf einer dielektrischen Durchkontaktierungsschicht hergestellt, wobei die Speicherzellenstrukturen durch einen Zwischenzellenbereich getrennt sind. Eine Zwischenzellen-Füllschicht wird so hergestellt, dass sie die Speicherzellenstrukturen und die dielektrische Durchkontaktierungsschicht bedeckt und außerdem den Zwischenzellenbereich füllt. Die Zwischenzellen-Füllschicht wird ausgespart, bis sich eine Oberseite der Zwischenzellen-Füllschicht unter einer Oberseite des Paars Speicherzellenstrukturen befindet und der Zwischenzellenbereich teilweise geleert ist. Eine dielektrische Verbindungsschicht wird so hergestellt, dass sie die Speicherzellenstrukturen und die Zwischenzellen-Füllschicht bedeckt und außerdem einen geleerten Teil des Zwischenzellenbereichs ...

VERWENDUNG VON ORGANISCHEN SPIN-ON-MATERIALIEN ALS BEGRENZUNGSSCHICHT FÜR LOKALE VERBINDUNGSSTRUKTUREN, KONTAKT- UND DURCHKONTAKTSCHICHTEN

Verfahren zur Bildung eines Source-Kontakts eines Flash-Speicherbauelements

Verfahren zur Bildung eines Source-Kontakts eines Flash-Speicherbauelements mit den Schritten: Bilden einer ersten Zwischenschichtisolationsschicht auf einem Halbleitersubstrat, in welchem eine Verbindungsregion und eine Gate-Elektrodenstruktur für SSL einer Zellenregion gebildet werden; Strukturieren der ersten Zwischenschichtisolationsschicht, um ein Source-Kontaktloch zu bilden, durch welches die Verbindungsregion für die SSL auf einer Seite der Gate-Elektrodenstruktur für SSL exponiert wird; Bilden einer Schicht auf der gesamten Oberfläche, einschließlich des Source-Kontaktlochs; Ausführen eines Polierprozesses bis die erste Zwischenschichtisolationsschicht exponiert ist, um einen Source-Kontakt zu bilden; Bilden einer zweiten Zwischenschichtisolationsschicht auf der gesamten Oberfläche einschließlich des Source-Kontakts; Strukturieren der zweiten Zwischenschichtisolationsschicht, um die in einer peripheren Region des Halbleitersubstrats gebildeten ersten Verbindungsregionen zu exponieren ...

SEMICONDUCTOR DEVICE INCORPORATING A CONTACT AND MANUFACTURE THEREOF

Display apparatus and multi display apparatus including the same

Display apparatus 10 has a first substrate 100, including pixels in a display portion, coupled to a second substrate 200, and a routing portion 400 on outer surfaces of the first and second substrates. The second substrate 200 has a metal pattern layer connected to the routing portion and a rear insulation layer comprising an isolation pattern area. The rear insulation layer may be inorganic and include a thicker non-isolation pattern area. A pad 110 may connect the routing portion and each outermost pixel of the first substrate 100 at the end of the display portion. Pad parts may be on an edge and rear of the second substrate 200, electrically connected by a link line. The display apparatus, without bezel, may reduce image discontinuity between adjacent modules of a lattice type multi-display. A panel support may include a plate with magnetised fastening members connected to the second substrate 200.

Embedded bottom metal contact formed by a self-aligned contact process for vertical transistors

Embodiments are directed to a method and resulting structures for a vertical field effect transistor (VFET) having an embedded bottom metal contact. A semiconductor fin is formed on a doped region of a substrate. A portion of the doped region adjacent to the semiconductor fin is recessed and an embedded contact is formed on the recessed portion. A material of the conductive rail is selected such that a conductivity of the embedded contact is higher than a conductivity of the doped region.

Method for forming contact holes in semiconductor device

Method fabricating local interconnect

ADJACENT CONTACT STRUCTURE WITH DECREASED AREA REQUIREMENTS.

SEMICONDUCTOR ARRANGEMENT WITH SELFADJUSTED CONTACTS AND PROCEDURE FOR YOUR PRODUCTION

Semiconductor processing methods of forming contact openings, methods of formingelectrical connections and interconnections, and integrated circuitry

Integrated circuit having interconnect to a substrate and method therefor

Self-aligned non-volatile memory cell

Method and apparatus using silicide layer for protecting integrated circuits from reverse engineering

SEMICONDUCTOR INTERCONNECTION STRUCTURE

... 4157-221 An improved field effect transistor utilizes a selfaligned contact structure in which a layer of metal capable of forming silicide is deposited on the source and drain regions as well as external to them. The metal forms metal silicide on the source and drain and, where it extends onto surrounding insulating regions, forms an interconnecting metal contact. In addition, bipolar devices may be formed on the same integrated circuit by employing insulating spacer regions around the edges of polysilicon electrodes to the bipolar devices. Also described are static and dynamic random access memory cells employing the technology.

METHOD OF FABRICATING A SELF-ALIGNED NON-VOLATILE MEMORY CELL

Disclosed is a self-aligned non-volatile memory cell (200) comprising a small sidewall spacer (239) electrically coupled and being located next to a main floating gate region (212). Both the small sidewall spacer and the main floating gate region are formed on a substrate (204) and both form the floating gate of the non-volatile memory cell. Both are isolated electrically from the substrate by oxide layers (208, 232, 242) which are thinner (260; 232, 242) between the small sidewall spacer and the substrate; and is thicker (263; 208) between the main floating gate region and the substrate. The small sidewall spacer can be made small; therefore, the thin oxide layer area can also be made small to create a small pathway for electrons to tunnel into the floating gate.

SWITCHING ELEMENT AND METHOD OF MANUFACTURING SWITCHING ELEMENT

A switching element includes a semiconductor substrate that includes a first n- type semiconductor layer, a p-type body layer constituted by an epitaxial layer, and a second n-type semiconductor layer separated from the first n-type semiconductor layer by the body layer, a gate insulating film that covers a range across the surface of the first n-type semiconductor layer, the surface of the body layer, and the surface of the second n-type semiconductor layer, and a gate electrode that faces the body layer through the gate insulating film. An interface between the first n-type semiconductor layer and the body layer includes an inclined surface. The inclined surface is inclined such that the depth of the body layer increases as a distance from an end of the body layer increases in a horizontal direction. The inclined surface is disposed below the gate electrode.

SEMICONDUCTOR INTERCONNECTION STRUCTURE

SEMICONDUCTOR DEVICE AND A METHOD FOR FABRICATING THE SAME

Self-aligned non-volatile memory cell

Contact scheme for landing on different contact area levels

Semiconductor device and a method of manufacturing the same

For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.

A memory structure and a method for manufacture that same

Buried metal double mosaic board capacitor

Memory

Semiconductor device layout, memory device layout, and method of manufacturing semiconductor device

Trench isolated capacitor

Fabrication of self-assembled nanowire-type interconnects on a semiconductor device

The present invention relates to a semiconductor device with nanowire-type interconnect elements and a method for fabricating the same. The device comprises a metal structure with at least one self-assembled metal dendrite and forming an interconnect element (424) between a first and a second metal structure. The fabrication comprises providing an ambient environment adjacent to an interconnect surface region of a substrate that is suitable for allowing growth of at least one metal dendrite between the first and second metal structures, and initiating and sustaining self-assembly of a metal structure comprising at least one metal dendrite in the interconnect surface region between the first and second metal structures by irradiating the pn junction with photons of an energy suitable for creating free charge carriers in the first and second doped substrate regions and thus creating an electric potential difference between the first and second metal structures, which is suitable for electrolysis ...

Semiconductor device and a method of manufacturing the same

METHOD OF MANUFACTURING A FIELD EFFECT TRANSISTOR WITH REDUCED PARASITIC CAPACITANCE

INTERNAL VIA WITH IMPROVED CONTACT FOR UPPER SEMICONDUCTOR LAYER OF 3D CIRCUIT

A METHOD FOR INTER-CONNECTING THE ACTIVE ZONES AND/OR THE GRIDS OF JUST CIRCUITS CMOS

AN INTEGRATED CIRCUIT HAVING A SHARED CONTACT MASK

Multiple short local electrical connections for selective linkage of integrated circuit elements comprise masked selective humid attack of deposited metal

L'invention permet la réalisation d'au moins une connexion électriquement conductrice reliant sélectivement des éléments (2, 4, 10, 12) sur un substrat (28) de circuit intégré (8), par les étapes de : - réaliser lesdits éléments (2, 4, 10, 12) sur un substrat dont au moins une portion de la surface est constituée d'un premier matériau, - déposer, sur le substrat et lesdits éléments, au moins un deuxième matériau, qui est conducteur (42, 44, 46) et susceptible de créer une réaction avec le premier matériau pour former un matériau conducteur à la surface du substrat, - traiter le substrat pour réaliser ladite réaction, - réaliser un retrait sélectif du deuxième matériau n'ayant pas réagi avec ledit premier matériau, pour laisser du deuxième matériau selon un motif qui correspond à au moins une partie de la connexion. Ce procédé permet d'obtenir notamment des connexions de niveau local sur le circuit intégré. L'invention concerne également un circuit intégré issu de ce procédé.

METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT FOR FAST ANALOG LINES USING SILICIDE LOCAL INTERCONNECT.

STRUCTURE AND METHOD OF FORMING BITLINE CONTACTS FOR A VERTICAL DRAM ARRAY USING A LINE BITLINE CONTACT MASK

자가-정렬된 콘택 및 방법

... 자가-정렬된 콘택들이 제공된다. 실 실시예에서, 자가-정렬된 콘택들은 게이트 전극 가까이로부터 제 1 유전체 물질을 부분적으로 제거하고, 게이트 전극 가까이로부터 제 2 유전체 물질을 완전히 제거함으로써 형성된다. 전도성 물질이 제거된 제 1 유전체 물질 및 제 2 유전체 물질의 영역에 증착되며, 전도성 물질 및 금속 게이트들이 스페이서 아래로 리세싱된다. 유전체 층은 리세싱된 전도성 물질 및 리세싱된 금속 게이트들 위에 증착되고, 자가-정렬된 콘택들은 유전체 층을 통해 형성된다.

SEMICONDUCTOR DEVICE AND ITS MANUFACTURE

A METHOD FOR SELECTIVELY FORMING A SELF ALIGNED LOCAL INTERCONNECT TO GATE

... 반도체 디바이스 제조 공정은 하드 마스크를 사용하여 반도체 기판에 트랜지스터 게이트(102)를 형성하는 것을 포함한다. 하드 마스크(112)는 게이트 위 하나 이상의 선택된 영역들에서 선택적으로 제거된다. 선택된 영역들에서 하드 마스크의 제거는 트랜지스터보다 실질적으로 위에 있는 적어도 하나의 절연층을 통해 상부 금속층에 게이트가 연결될 수 있게 한다. 전도성 물질이 적어도 하나의 절연층을 통해 하나 이상의 트렌치들에 증착된다. 전도성 물질은 선택된 영역들 중 적어도 하나에서 게이트에 로컬 배선을 형성한다.

Method for forming local interconnection line for use in semiconductor device

반도체 장치 및 그 제작 방법

... 본 발명은 트랜지스터를 구성하는 각 부재의 저항을 작게 하여 트랜지스터의 온 전류의 향상을 도모하고, 집적 회로의 고성능화를 도모하는 것을 과제의 하나로 한다. 단결정 반도체 기판 위에 절연층을 사이에 두고 형성되고, 소자 분리 절연층에 의하여 소자 분리된 n형 FET 및 p형 FET를 갖는 반도체 장치이고, FET 각각은, 반도체 재료를 포함하는 채널 형성 영역과, 채널 형성 영역에 접하여 반도체 자료를 포함하는 도전성 영역과, 도전성 영역에 접하는 금속 영역과, 채널 형성 영역에 접하는 게이트 절연층과, 게이트 절연층에 접하는 게이트 전극과, 금속 영역을 일부에 포함하는 소스 전극 또는 드레인 전극을 갖는다.

METHOD FOR MANUFACTURING CONTACT OF SEMICONDUCTOR DEVICE

PURPOSE: A method for manufacturing a contact of a semiconductor device is provided to manufacture easily a high-integrated semiconductor device by forming a fine contact hole. CONSTITUTION: A method for manufacturing a contact of a semiconductor device comprises the following steps. A first insulation layer(3) is formed on an upper portion of a predetermined substrate(1). A second and a third insulation layer(4,5) are formed on the first insulation layer. A first contact mask(6) is formed on a predetermined contact area of the third insulation layer. The third and the second insulation layers are etched by using the first contact mask and a second and a third insulation layer pattern are formed. The first contact mask is removed. A pad layer is formed on the whole surface of the structure. The pad layer with a projection portion is formed by performing an anisotropic etching for the pad layer. A fourth insulation layer(8) is formed on the whole surface of the structure. A second contact ...

METHOD FOR FABRICATING A CYLINDRIC CAPACITOR

PURPOSE: A cylindric capacitor fabricating method is provided to form a cylindric capacitor having a fine interval which is difficult to form by a photo lithography process. CONSTITUTION: A cylindric capacitor fabricating method comprises forming a conductive layer and an oxide preventing film sequentially over an entire surface of a semiconductor substrate. A photo resist film pattern is formed on the oxide preventing film. An oxide preventing film pattern is formed by etching the oxide preventing film and a part of the conductive layer. An oxide film is formed by oxidizing an exposed part of the conductive layer, and the oxide preventing film pattern is removed. A conductive layer exposed at both sides is etched, and a blanket etch process is performed so as to form a remaining oxide film(24a). A storage node pattern(15a) is formed by etching the exposed conductive layer using the remaining oxide film(24a) as a mask. COPYRIGHT 2000 KIPO ...

METHOD FOR THE PRODUCTION OF CONTACTS FOR INTEGRATED CIRCUITS AND SEMICONDUCTOR COMPONENT WITH SAID CONTACTS

LOCAL INTERCONNECT ETCH TECHNIQUE

임계치 이하 패턴 피쳐들을 달성하기 위한 컷 마스크 리소그래피와 종래의 리소그래피의 조합

... 반도체 칩 상에 피쳐들이 제작된다. 피쳐들은 칩을 생성하는데 이용되는 리소그래피의 임계치보다 더 작다. 방법은, 라인 팁-팁 공간 또는 라인 공간과 같은 미리결정된 거리만큼 분리될 (로컬 인터커넥트와 같은) 피쳐의 제 1 부분 및 피쳐의 제 2 부분을 패터닝하는 단계를 포함한다. 방법은 제 1 하위-부분(예를 들어, 콘택) 및 제 2 하위-부분을 형성하기 위해 컷 마스크로 제 1 부분을 패터닝하는 단계를 더 포함한다. 제 1 하위-부분의 치수는, 특정된 폭 해상도를 갖는 리소그래픽 프로세스의 라인 길이 해상도일 수 있는 제 2 미리결정된 거리의 치수 미만이다. 반도체 디바이스의 피쳐는 제 1 부분 및 제 1 부분의 리소그래픽 해상도 미만의 치수를 갖는 제 2 부분을 포함한다.

Semiconductor device and method of manufacturing the same

LDMOS TRANSISTOR

The LDMOS transistor (1) of the invention comprises a substrate (2), a gate electrode (10), a substrate contact region (11), a source region (3), a channel region (4) and a drain region (5), which drain region (5) comprises a drain contact region (6) and a drain extension region (7). The drain contact region (6) is electrically connected to a top metal layer (23), which extends over the drain extension region (7), with a distance (723) between the top metal layer (23) and the drain extension region (7) that is larger than 2μm. This way the area of the drain contact region (6) may be reduced and the RF power output efficiency of the LDMOS transistor (1) increased. In another embodiment the source region (3) is electrically connected to the substrate contact region (11) via a suicide layer (32) instead of a first metal layer (21), thereby reducing the capacitive coupling between the source region (3) and the drain region (5) and hence increasing the RF power output efficiency of the LDMOS ...

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

PURPOSE: A method for manufacturing a semiconductor device is provided to reduce time for forming a whole nitride layer which is a lower layer of a nitrogen-oxide dielectric layer, without decreasing the quality of the whole nitride layer. CONSTITUTION: A polycrystalline silicon layer(60) pattern for a storage electrode of a capacitor is formed on a silicon substrate. A native oxide layer on the polycrystalline silicon layer is nitridized at an arbitrary temperature by using a low pressure chemical vapor deposition(LPCVD) process. A nitride layer(71) is stacked on the nitridized native oxide layer on an in-situ state at the same temperature as the arbitrary temperature. An oxide layer is stacked on the nitride layer. A plate electrode pattern is formed on the oxide layer. COPYRIGHT 2001 KIPO ...

리세싱된 엣지들을 갖는 반도체 디바이스 및 그 제조방법

... 패키지 엣지를 따라 리세싱된 영역들을 활용하는 디바이스 및 제조 방법이 제공된다. 예를 들어, 집적형 팬 아웃 패키지에 있어서, 단품화 이후 유전체층들이 다이의 엣지들로부터 리세싱 백(recessed back)되도록, 유전체층들, 예컨대 재분배층들의 폴리머층들은 스크라이브 라인을 따라 제거된다. 모서리 영역들은 더욱 리세싱될 수 있다. 리세싱된 영역들은 삼각형, 둥근형, 또는 이와 다른 형상일 수 있다. 몇몇의 실시예들에서, 하나 이상의 모서리 영역들은 남아있는 모서리 영역들에 비해 더욱 리세싱될 수 있다. 재분배층들은 전측면 재분배층들과 후측면 재분배층들 중 하나 또는 이 둘 모두를 따라 리세싱될 수 있다.

반도체 장치 및 이의 제조 방법

... 굴곡진 바닥면을 갖는 소오스/드레인 컨택을 형성함으로써, 신뢰성 및 소자 성능을 개선할 수 있는 반도체 장치를 제공하는 것이다. 상기 반도체 장치는 서로 간에 이격되는 제1 활성 영역 및 제2 활성 영역, 상기 제1 활성 영역 및 상기 제2 활성 영역 상에, 상기 제1 활성 영역 및 상기 제2 활성 영역과 교차하는 게이트 전극, 상기 게이트 전극의 일측에 배치되고, 서로 간에 이격되는 제1 소오스/드레인 및 제2 소오스/드레인, 및 상기 제1 소오스/드레인 및 상기 제2 소오스/드레인 상에 각각 배치되는 제1 부분 및 제2 부분과, 상기 제1 부분과 상기 제2 부분을 서로 연결하는 연결 부분을 포함하는 컨택으로, 상기 제1 부분의 상면 및 상기 제2 부분의 상면은 상기 연결 부분의 상면과 동일 평면 상에 놓이고, 상기 제1 부분의 높이 및 상기 제2 부분의 높이는 상기 연결 부분의 높이와 다른 컨택을 포함한다.

METHODS FOR DEPOSITING ULTRA THIN LOW RESISTIVITY TUNGSTEN FILM FOR SMALL CRITICAL DIMENSION CONTACTS AND INTERCONNECTS

SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREOF

PURPOSE: A semiconductor device and its production method are provided to prevent the leakage current, and to have the excellent hold characteristic inside a memory circuit. CONSTITUTION: The production method of the semiconductor device has steps of: forming an opening in interlayer films(5, 11) by an anisotropic etching not by exposing the surface of a semiconductor substrate(1); forming a CVD film on the area containing the inner surface of the opening; exposing the surface of the semiconductor substrate by removing the CVD film in the bottom of the opening by an etching back and by removing the interlayer film under the opening; reclaiming the opening by a conductive material. COPYRIGHT 2000 KIPO ...

III-V 반도체 재료 층을 갖는 반도체 디바이스

... 종래의 디바이스에 비해 감소된 기생 콘택 저항을 갖는 트랜지스터 디바이스를 형성하는 기술이 개시된다. 일부 예시적 실시예에서, CMOS 디바이스의 MOS 트랜지스터의 콘택을 구현하는 기술을 사용할 수 있으며, 여기서 p-형 및 n-형 소스/드레인 영역들과 그들의 각 콘택 금속들 사이에 III-V 반도체 재료 중간층이 제공되어 콘택 저항을 현저히 감소시킨다. III-V 반도체 재료 중간층은 원하는 전도율을 제공하기 위해 작은 밴드 갭(예를 들어, 0.5 eV보다 낮은)을 가질 수 있고/있거나 도핑될 수 있다. 변형 및 비변형 채널 구조를 포함하는 다수의 트랜지스터 아키텍처(예를 들어, 평면형, 핀형 및 나노와이어 트랜지스터)에 대해 상기 기술을 사용할 수 있다.

METHOD FOR MONITORING SOURCE CONTACT OF FLASH MEMORY

PURPOSE: A method for monitoring source contact of flash memory is provided to improve the yield and the reliability of the flash memory by monitoring the contact condition of the source contact in the case that the flash memory is formed by the local interconnection method of a source line. CONSTITUTION: A plurality of word lines are connected to a common VG terminal(400), the first drain contact(27) is connected to a VD terminal(500), and the other drain contacts(27) are floated. The last common source contact(28) is connected to a VSS terminal(700), and the other common source contacts(28) are connected to a VS terminal(600). If the neighboring drain contacts(27) are separated, the drain contacts(27) are connected via a metal wire(300), so that current can be flowed from the VD terminal(500) to the VSS terminal(700). COPYRIGHT 2001 KIPO ...

METAL FILAMENT VIAS FOR INTERCONNECT STRUCTURE

MULTI FINGER TRANSISTOR HAVING A LOW GATE RESISTANCE AND A HIGH MAXIMUM OSCILLATION FREQUENCY

PURPOSE: A multi finger transistor is provided to have a low parasitic capacitance and a high cutoff frequency by forming a gate connecting unit between active regions. CONSTITUTION: Two active regions(420) are defined in a unit cell on a substrate(410). A multi finger gate(450) includes plural gate fingers(452) and a gate connecting unit(454). The gate fingers are formed in the active regions. The gate connecting unit connects the gate fingers to each other and is formed between the two active regions. Plural source regions(460) are formed at parts of the active regions adjacent to the gate fingers. Plural drain regions(470) are formed at parts of the active regions adjacent to the gate fingers. Each gate finger is formed to be extended in a first direction. The gate connecting unit is formed to be extended in a second direction perpendicular to the first direction. Each source/drain region is formed to be extended in the first direction and the second direction in turn. © KIPO 2008 ...

PROBE CARD

The present invention relates to a probe card. The probe card according to an embodiment of the present invention includes: a probe block including a plurality of probe pins in contact with a semiconductor element; a main printed circuit board which includes a through hole through which the probe block passes and is electrically connected to the probe block; an interposer disposed on the upper sides of the probe block and the main printed circuit board and electrically connecting the probe block and the main printed circuit board; and a base plate for fixing the probe block, the main printed circuit board, and the interposer. The interposer includes a film part and a circuit pattern part formed on one side of the film part. Accordingly, the present invention can provide the probe card applicable to the probe block with a fine pitch. COPYRIGHT KIPO 2017 ...

METHOD FOR MANUFACTURING A CAPACITOR OF A SEMICONDUCTOR DEVICE

PURPOSE: A method for manufacturing a capacitor of a semiconductor device is provided to reduce a leakage current of the capacitor and to increase electric permittivity, by using a carbon-free tantalum-based material as a dielectric layer. CONSTITUTION: A semiconductor substrate(11) having a lower structure for forming a capacitor of a semiconductor device is prepared. A charge storage electrode(13) is formed on the semiconductor substrate. A Ta2O5 dielectric layer(15) is formed on the entire structure by using a tantalum-based carbon-free material as a precursor. A plate electrode(16) is formed on the entire structure. COPYRIGHT 2001 KIPO ...

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

According to a technical concept of the present invention, a method for manufacturing a semiconductor device comprises the following steps of: preparing a substrate having a cell region and a peripheral region; forming a plurality of bit line structures which are separated from each other by first grooves arranged in a first direction in a cell region, extended in the first direction, and spaced apart from each other in a second direction orthogonal to the first direction, and forming a plurality of gate structures made of the same material as that of the bit line structures in the peripheral region; forming spacers on both sidewalls of the bit line structures and the gate structures; forming a sacrificial layer containing carbon which fills the first groove and covers upper surfaces of the gate structures; and polish-finishing upper surfaces of the bit line structures and the gate structures by chemically and mechanically polishing the sacrificial layer. COPYRIGHT KIPO 2016 ...

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

PURPOSE: A method for manufacturing a semiconductor device is provided to be capable of reducing the contact resistance of a storage node contact for connecting a source/drain and a lower electrode. CONSTITUTION: An interlayer dielectric(34) is formed on a semiconductor substrate(31) having a junction layer. A contact hole is formed to expose the junction layer(33) by selectively etching the interlayer dielectric. The first ohmic contact layer(38) is partially filled into the exposed junction layer in the contact hole, and a polysilicon plug(39) and the second ohmic contact layer(40) are sequentially filled into the contact hole, thereby forming a storage node contact. A capacitor including a lower electrode(42), a dielectric film(43) and an upper electrode(44), is then formed to connect the storage node contact. © KIPO 2003 ...

Semiconductor device and method of fabricating the same

Semiconductor product with interlocking metal-to-metal bonds and method for manufacturing thereof

Semiconductor devices, methods of manufacture thereof, and methods of singulating semiconductor devices

Copper interconnects having a titanium-platinum-titanium assembly between copper and compound semiconductor

Disclosed are devices and methods related to metallization of semiconductors. A metalized structure can include a first titanium (Ti) layer disposed over a compound semiconductor, a first barrier layer disposed over the first Ti layer, a second Ti layer disposed over the first barrier layer, and a copper (Cu) layer disposed over the second Ti layer. The second Ti layer can be configured to inhibit or reduce alloying of the Cu layer and the first barrier layer. The first Ti layer, the first barrier layer, and the second Ti layer can be configured to yield a barrier between the Cu layer and an ohmic metal layer formed on the compound semiconductor. The metalized structure can further include a third Ti layer disposed over the Cu layer and a second barrier layer disposed over the third Ti layer. The first and second barrier layers can include platinum (Pt) and/or palladium (Pd).

Layout designs with via routing structures

An approach for providing layout designs with via routing structures is disclosed. Embodiments include: providing a gate structure and a diffusion contact on a substrate; providing a gate contact on the gate structure; providing a metal routing structure that does not overlie a portion of the gate contact, the diffusion contact, or a combination thereof; and providing a via routing structure over the portion and under a part of the metal routing structure to couple the gate contact, the diffusion contact, or a combination thereof to the metal routing structure.

Semiconductor structure and manufacturing method thereof

A semiconductor structure includes a substrate, a gate structure disposed over the substrate, a dielectric material disposed over the substrate and the gate structure, a conductive structure extending within the dielectric material, and a void extending within the dielectric material and disposed over the gate structure.

Semiconductor devices and methods of fabricating the same

A method and structure for forming a via-first metal gate contact includes depositing a first dielectric layer over a substrate having a gate structure with a metal gate layer. An opening is formed within the first dielectric layer to expose a portion of the substrate, and a first metal layer is deposited within the opening. A second dielectric layer is deposited over the first dielectric layer and over the first metal layer. The first and second dielectric layers are etched to form a gate via opening. The gate via opening exposes the metal gate layer. A portion of the second dielectric layer is removed to form a contact opening that exposes the first metal layer. The gate via and contact openings merge to form a composite opening. A second metal layer is deposited within the composite opening, thus connecting the metal gate layer to the first metal layer.

Semiconductor device and method for manufacturing the same

An object is to reduce the resistance of each member included in a transistor, to improve ON current of the transistor, and to improve performance of an integrated circuit. A semiconductor device including an n-channel FET and a p-channel FET which are provided over a single crystal semiconductor substrate with an insulating layer interposed therebetween and are isolated by an element isolation insulating layer. In the semiconductor device, each FET includes a channel formation region including a semiconductor material, a conductive region which is in contact with the channel formation region and includes the semiconductor material, a metal region in contact with the conductive region, a gate insulating layer in contact with the channel formation region, a gate electrode in contact with the gate insulating layer, and a source or drain electrode partly including the metal region.

Method for fabricating an integrated semiconductor circuit

The invention relates to a method for fabricating an integrated semiconductor circuit, in which electric contacts (20) for first conductive structures (1) are fabricated in the memory region (I) and contact is made with the first conductive structures (1) without contact being made with second conductive structures (2) which are arranged to the sides of the first conductive structures (1) and laterally adjoin the first conductive structures (1) or are arranged too closely next to them for it to be possible for the second conductive structures to be lithographically masked selectively with respect to the first conductive structures. According to the invention, contact is made with the first conductive structures (1) as a result of a conductive layer (L), which is used in the logic region for example for the production of gate electrodes, being deposited in the memory region, at the height of the first conductive structures (1) which are above the second conductive structures (2), after a ...

Substrate processing method and device manufactured by using the same

Provided are a substrate processing method and a device manufactured by using the same, which may improve etch selectivity of an insulating layer deposited on a stepped structure. The substrate processing method includes: forming a first layer on a stepped structure having an upper surface, a lower surface, and a side surface connecting the upper surface and the lower surface; weakening at least a portion of the first layer; forming a second layer on the first layer; and performing an isotropic etching process on the first layer and the second layer.

Semiconductor device and method for fabricating the same

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a semiconductor substrate, a plurality of first set conductive elements separately positioned above the semiconductor substrate, a plurality of first set supporting pillars respectively correspondingly positioned between an adjacent pairs of the plurality of first set conductive elements, and a plurality of spaces respectively correspondingly positioned adjacent to the plurality of first set supporting pillars.

Semiconductor apparatus having stacked devices and method of manufacture thereof

Aspects of the disclosure provide a semiconductor apparatus including a plurality of structures. A first one of the structures comprises a first stack of transistors that includes a first transistor formed on a substrate and a second transistor stacked on the first transistor along a Z direction substantially perpendicular to a substrate plane of the semiconductor apparatus. The first one of the structures further includes local interconnect structures. The first transistor is sandwiched between two of the local interconnect structures. The first one of the structures further includes vertical conductive structures substantially parallel to the Z direction. The vertical conductive structures are configured to provide at least power supplies for the first one of the structures by electrically coupling with the local interconnect structures. A height of one of the vertical conductive structures along the Z direction is at least a height of the first one of the structures.

VIA RAIL SOLUTION FOR HIGH POWER ELECTROMIGRATION

Layout method and semiconductor structure

Method for manufacturing semiconductor device

Semiconductor device and method for fabricating the same

Scalable interconnect structures with selective via posts

A permanently-on transistor with buried contact

A permanently-ON MOS transistor comprises silicon source and drain regions of a first conductivity type in a silicon well region of a second conductivity type. A silicon contact region of the first conductivity types is buried in the well region, said contact region contacting said source region and said drain region. A first gate insulating layer is selectively placed over the silicon source and drain regions. A second gate insulating layer is selectively placed over the first gate insulating layer and over the silicon contact region. A polysilicon gate region is placed over the second gate insulating layer.

TRANSISTOR CONTACTS SELF-ALIGNED IN TWO DIMENSIONS

Semiconductor device with local interconnects

SEMICONDUCTOR APPARATUS AND MANUFACTURING METHOD OF THE SAME

A source/drain region (106) is formed at both sides of a gate electrode (103) on a semiconductor substrate (100). A shared contact has a lower level contact (113) that is connected to the source/drain region (106) and not connected to the gate electrode (103), and an upper level contact (118) connected to both the lower contact (113) and the gate electrode (103).

METHOD AND APPARATUS FOR A DIRECT BURIED STRAP FOR SAME LEVEL INTERCONNECTIONS FOR SEMICONDUCTOR DEVICES

A method and apparatus for forming a direct buried strap for a semiconductor device, in accordance with the present invention, includes forming a gate stack (106) on a semiconductor substrate (102), and forming a protective layer on sidewalls (108) of the gate stack. The protective layer extends horizontally (109) over a portion of the semiconductor substrate adjacent to the gate stack. A conductive layer (112) is formed over the protective layer and in contact with a gate conductor (107) of the gate stack and in contact with a diffusion region (104) formed in the semiconductor substrate adjacent to the gate conductor. A dielectric layer is formed over the conductive layer, and the dielectric layer is patterned to expose a portion of the conductive layer. The portion of the conductive layer which is exposed includes a portion of the conductive layer over the gate conductor and a portion of the substrate adjacent to the gate conductor. The exposed areas of the conductive layer are silicided ...

Metal semiconductor alloy structure for low contact resistance

Contact via holes are etched in a dielectric material layer overlying a semiconductor layer to expose the topmost surface of the semiconductor layer. The contact via holes are extended into the semiconductor material layer by continuing to etch the semiconductor layer so that a trench having semiconductor sidewalls is formed in the semiconductor material layer. A metal layer is deposited over the dielectric material layer and the sidewalls and bottom surface of the trench. Upon an anneal at an elevated temperature, a metal semiconductor alloy region is formed, which includes a top metal semiconductor alloy portion that includes a cavity therein and a bottom metal semiconductor alloy portion that underlies the cavity and including a horizontal portion. A metal contact via is formed within the cavity so that the top metal semiconductor alloy portion laterally surrounds a bottom portion of a bottom portion of the metal contact via.

Metal gate transistor, integrated circuits, systems, and fabrication methods thereof

A method of forming an integrated circuit structure includes providing a gate strip in an inter-layer dielectric (ILD) layer. The gate strip comprises a metal gate electrode over a high-k gate dielectric. An electrical transmission structure is formed over the gate strip and a conductive strip is formed over the electrical transmission structure. The conductive strip has a width greater than a width of the gate strip. A contact plug is formed above the conductive strip and surrounded by an additional ILD layer.

Self-Aligned Contacts for High k/Metal Gate Process Flow

A semiconductor structure is provided that includes a semiconductor substrate having a plurality of gate stacks located on a surface of the semiconductor substrate. Each gate stack includes, from bottom to top, a high k gate dielectric layer, a work function metal layer and a conductive metal. A spacer is located on sidewalls of each gate stack and a self-aligned dielectric liner is present on an upper surface of each spacer. A bottom surface of each self-aligned dielectric liner is present on an upper surface of a semiconductor metal alloy. A contact metal is located between neighboring gate stacks and is separated from each gate stack by the self-aligned dielectric liner. The structure also includes another contact metal having a portion that is located on and in direct contact with an upper surface of the contact metal and another portion that is located on and in direct contact with the conductive metal of one of the gate stacks. Methods of forming the semiconductor structure using a replacement gate and a non-replacement gate scheme are also disclosed.

FinFET STRUCTURE HAVING FULLY SILICIDED FIN

A semiconductor device which includes fins of a semiconductor material formed on a semiconductor substrate and then a gate electrode formed over and in contact with the fins. An insulator layer is deposited over the gate electrode and the fins. A trench opening is then etched in the insulator layer. The trench opening exposes the fins and extends between the fins. The fins are then silicided through the trench opening. Then, the trench opening is filled with a metal in contact with the silicided fins to form a local interconnect connecting the fins.

Semiconductor memory device, method of manufacturing the same and method of forming contact structure

When a first wiring and/or a second wiring is formed, a connection portion is formed in the first wiring and/or the second wiring which covers a part of a lower electrode layer outside the memory cell array. An etching suppressing portion is formed above the connection portion. A contact hole is formed in which a portion under the etching suppressing portion reaches up to a connection potion, and the other portion reaches up to the lower electrode layer by performing etching to a laminated body in a range including the etching suppressing portion. The laminated body includes the insulating layer, the first wiring, a memory cell layer, the second wiring, and the etching suppressing portion. The contact layer is formed by burying a conductive material in the contact hole.

Method of Forming Conductive Contacts on a Semiconductor Device with Embedded Memory and the Resulting Device

A method is disclosed that includes forming a conductive logic contact in a logic area of a semiconductor device, forming a bit line contact and a capacitor contact in a memory array of the semiconductor device, and performing at least one first common process to form a first metallization layer comprising a first conductive line in the logic area that is conductively coupled to the conductive logic contact and a bit line in the memory array that is conductively coupled to the bit line contact. The method further includes performing at least one second common process to form a second metallization layer comprising a first conductive structure conductively coupled to the first conductive line in the logic area and a second conductive structure in the memory array that that is conductively coupled to the capacitor contact.

Local interconnect having increased misalignment tolerance

A method is provided for forming an interconnect in a semiconductor memory device. The method includes forming a pair of source select transistors on a substrate. A source region is formed in the substrate between the pair of source select transistors. A first inter-layer dielectric is formed between the pair of source select transistors. A mask layer is deposited over the pair of source select transistors and the inter-layer dielectric, where the mask layer defines a local interconnect area between the pair of source select transistors having a width less than a distance between the pair of source select transistors. The semiconductor memory device is etched to remove a portion of the first inter-layer dielectric in the local interconnect area, thereby exposing the source region. A metal contact is formed in the local interconnect area.

Borderless Contacts in Semiconductor Devices

A method includes depositing a dummy fill material over exposed portions of a substrate and a gate stack disposed on the substrate, removing portions of the dummy fill material to expose portions of the substrate, forming a layer of spacer material over the exposed portions of the substrate, the dummy fill material and the gate stack, removing portions of the layer of spacer material to expose portions of the substrate and the dummy fill material, depositing a dielectric layer over the exposed portions of the spacer material, the substrate, and the gate stack, removing portions of the dielectric layer to expose portions of the spacer material, removing exposed portions of the spacer material to expose portions of the substrate and define at least one cavity in the dielectric layer, and depositing a conductive material in the at least one cavity.

Tungsten metallization: structure and fabrication of same

A local interconnect structure is provided in which a tungsten region, i.e., tungsten stud, that is formed within a middle-of-the-line (MOL) dielectric material is not damaged and/or contaminated during a multiple interconnect patterning process. This is achieved in the present disclosure by forming a self-aligned tungsten nitride passivation layer within a topmost surface and upper sidewalls portions of the tungsten region that extend above a MOL dielectric material which includes a first interconnect pattern formed therein. During the formation of the self-aligned tungsten nitride passivation layer, a nitrogen enriched dielectric surface also forms within exposed surface of the MOL dielectric material. A second interconnect pattern is then formed adjacent to, but not connect with, the first interconnect pattern. Because of the presence of the self-aligned tungsten nitride passivation layer on the tungsten region, no damaging and/or contamination of the tungsten region can occur.

Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device includes forming a first interconnection and a second interconnection above a semiconductor substrate, forming a first sidewall insulating film on a side wall of the first interconnection, and a second sidewall insulating film on a side wall of the second interconnection, forming a conductive film above the semiconductor substrate with the first interconnection, the first sidewall insulating film, the second interconnection and the second sidewall insulating film formed on, and selectively removing the conductive film above the first interconnection and the second interconnection to form in a region between the first interconnection and the second interconnection a third interconnection formed of the conductive film and spaced from the first interconnection and the second interconnection by the first sidewall insulating film and the second sidewall insulating film.

Method for improving the electromigration resistance in the copper interconnection process

The present invention belongs to the technical field of integrated semiconductor circuits, and relates to a method used in a process no greater than 32 nm to improve the electromigration resistance of Cu interconnects. Coating layers on Cu interconnects, such as CuSi 3 , CuGe, and CuSiN, can be prepared by autoregistration, and with the use of new impervious layer materials, the electromigration resistance of Cu interconnects can be largely improved and the high conductivity thereof can be kept, which provides an ideal solution for interconnection process for process nodes no greater than 32 nm.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

An upper surface of a plug (PL) is formed so as to be higher than an upper surface of an interlayer insulating film (PIL) by forming the interlayer insulating film (PIL) on a semiconductor substrate (S), completing a CMP method for forming the plug (PL) inside the interlayer insulating film (PIL), and then, making the upper surface of the interlayer insulating film (PIL) to recede. In this manner, reliability of connection between the plug (PL) and a wiring (W) in a vertical direction can be ensured. Also, the wiring (W) can be formed so as not to be embedded inside the interlayer insulating film (PIL), or a formed amount by the embedding can be reduced. 1. A method of manufacturing a semiconductor device comprising steps of:(a) forming a first interlayer insulating film on a semiconductor substrate;(b) forming a first contact hole in the first interlayer insulating film;(c) after the step of (b), forming a first conductive film on the semiconductor substrate so as to bury the first conductive film inside the first contact hole;(d) removing the first conductive film outside the first contact hole so as to form a first plug made of the first conductive film;(e) after the step of (d), making an upper surface of the first interlayer insulating film to recede so that an upper surface of the first interlayer insulating film is lower than an upper surface of the first plug;(f) after the step of (e), forming a second interlayer insulating film having a dielectric constant lower than a dielectric constant of silicon oxide on the semiconductor substrate;(g) forming a first wiring trench in the second interlayer insulating film so that a part of the first plug is exposed and so that a lower surface of the first wiring trench is lower than the upper surface of the first plug;(h) after the step of (g), forming a second conductive film on the semiconductor substrate so as to bury the second conductive film inside the first wiring trench; and(i) removing the second conductive ...

Semiconductor device and method of manufacturing the same

Characteristics of a semiconductor device are improved. A semiconductor device of the present invention includes: (a) a MISFET arranged in an active region formed of a semiconductor region surrounded by an element isolation region; and (b) an insulating layer arranged below the active region. Further, the semiconductor device includes: (c) a p-type semiconductor region arranged below the active region so as to interpose the insulating layer; and (d) an n-type semiconductor region whose conductivity type is opposite to the p-type, arranged below the p-type semiconductor region. And, the p-type semiconductor region includes a connection region extending from below the insulating layer, and the p-type semiconductor region and a gate electrode of the MISFET are connected to each other by a shared plug which is an integrally-formed conductive film extending from above the gate electrode to above the connection region.

Trench silicide and gate open with local interconnect with replacement gate process

A semiconductor device fabrication process includes forming insulating mandrels over replacement metal gates on a semiconductor substrate with first gates having sources and drains and at least one second gate being isolated from the first gates. Mandrel spacers are formed around each insulating mandrel. The mandrels and mandrel spacers include the first insulating material. A second insulating layer of the second insulating material is formed over the transistor. One or more first trenches are formed to the sources and drains of the first gates by removing the second insulating material between the insulating mandrels. A second trench is formed to the second gate by removing portions of the first and second insulating materials above the second gate. The first trenches and the second trench are filled with conductive material to form first contacts to the sources and drains of the first gates and a second contact to the second gate.

INTERCONNECTS FOR STACKED NON-VOLATILE MEMORY DEVICE AND METHOD

A method of forming a memory device includes providing a substrate having a surface region, defining a cell region and first and second peripheral regions, sequentially forming a first dielectric material, a first wiring structure for a first array of devices, and a second dielectric material over the surface region, forming an opening region in the first peripheral region, the opening region extending in a portion of at least the first and second dielectric materials to expose portions of the first wiring structure and the substrate, forming a second wiring material that is overlying the second dielectric material and fills the opening region to form a vertical interconnect structure in the first peripheral region, and forming a second wiring structure from the second wiring material for a second array of devices, the first and second wiring structures being separated from each other and electrically connected by the vertical interconnect structure. 1providing a substrate having a surface region;forming a first dielectric material overlying the surface region of the semiconductor substrate;defining a cell region, a first peripheral region, and a second peripheral region;forming a first crossbar array of memory cells in the cell region overlying the first dielectric material; the first crossbar array of memory cells comprises a first bottom wiring structure spatially extending in a first direction and including a portion extending into the first peripheral region, a first top wiring structure spatially extending in a second direction perpendicular to the first direction and a first switching region sandwiched in an intersection region between the first top wiring structure and the first bottom wiring structure, the first top wiring structure including a portion extending into the second peripheral region;forming a second dielectric material overlying the first crossbar array of memory cells;forming a via opening in a portion of the first periphery region, the via ...

Metal Structure for Memory Device

A semiconductor device is provided that includes a substrate, a static random access memory (SRAM) unit cell formed in the substrate, a first metal layer formed over the substrate, the first metal layer providing local interconnection to the SRAM unit cell, a second metal layer formed over the first metal layer, the second metal layer including: a bit line and a complementary bit line each having a first thickness and a Vcc line disposed between the bit line and the complementary bit line, and a third metal layer formed over the second metal layer, the third metal layer including a word line having a second thickness greater than the first thickness. 1. A method comprising:forming a memory unit cell in a substrate;forming a first metal layer over the substrate, the first metal layer providing local interconnection to the memory unit cell;forming a second metal layer over the first metal layer, the second metal layer including a first bit line and a second bit line each having a first thickness; andforming a third metal layer over the second metal layer, the third metal layer including a word line and a first Vss line, wherein the word line has a second thickness greater than the first thickness, wherein the Vss line continuously extends parallel to the word line from at least the first bit line to at least the second bit line.2. The method of claim 1 , wherein the second metal layer further includes a power supply line disposed between the first and second bit lines.3. The method of claim 1 , wherein a length ratio of the word line to the first bit line is greater than about 2.0 in the memory unit cell.4. The method of claim 1 , wherein the first bit line has a first resistance and the word line has a second resistance that is less than the first resistance.5. The method of claim 1 , further comprising forming a fourth metal layer over the third metal layer claim 1 , wherein the fourth metal layer includes a second Vss line electrically coupled to the first Vss line ...

PACKAGE SUBSTRATE AND METHOD OF FABRICATING THE SAME

Disclosed herein are a package substrate and a method of fabricating the same. The method of fabricating the package substrate includes preparing a base substrate, forming a metal material layer surrounding an entire surface of the base substrate, forming sacrificial patterns on partial regions of the base substrate on which the metal material layer is formed, forming pads contacting lateral surfaces of the sacrificial patterns, forming a gold plating layer on upper surfaces of the pads, and removing the sacrificial patterns and removing portions of the metal material layer to form a conductive layer that remains on partial regions so as to contact lower surfaces of the pads. 1. A method of fabricating a package substrate , comprising:preparing a base substrate;forming a metal material layer surrounding an entire surface of the base substrate;forming sacrificial patterns on partial regions of the base substrate on which the metal material layer is formed;forming pads contacting lateral surfaces of the sacrificial patterns;forming a gold plating layer on upper surfaces of the pads; andremoving the sacrificial patterns and removing portions of the metal material layer to form a conductive layer that remains on partial regions so as to contact lower surfaces of the pads.2. The method according to claim 1 , wherein the pads are each formed to have a smaller height than that of each of the sacrificial patterns.3. The method according to claim 1 , wherein the gold plating layer is formed to have a smaller height than that of each of the sacrificial patterns.4. The method according to claim 1 , further comprising forming an insulating layer on the base substrate claim 1 , except for the partial regions.5. A package substrate comprising:a base substrate;a conductive layer formed on partial regions of the base substrate;pads formed on the conductive layer; anda gold plating layer that is formed to contact upper surfaces of the pads.6. The package substrate according to claim ...

SELF-ALIGNED CONTACTS FOR HIGH k/METAL GATE PROCESS FLOW

A semiconductor structure is provided that includes a semiconductor substrate having a plurality of gate stacks located thereon. Each gate stack includes a high k gate dielectric layer, a work function metal layer and a conductive metal. A spacer is located on sidewalls of each gate stack and a self-aligned dielectric liner is present on an upper surface of each spacer. A bottom surface of each self-aligned dielectric liner is present on an upper surface of a semiconductor metal alloy. A contact metal is located between neighboring gate stacks and is separated from each gate stack by the self-aligned dielectric liner. The structure also includes another contact metal having a portion that is located on and in direct contact with an upper surface of the contact metal and another portion that is located on and in direct contact with the conductive metal of one of the gate stacks.

Integrated circuits including copper local interconnects and methods for the manufacture thereof

Embodiments of a method for manufacturing an integrated circuit are provided. In one embodiment, a partially-fabricated integrated circuit is produced including a semiconductor substrate having source/drain regions, and a plurality of transistors including a plurality of gate conductors formed over the semiconductor substrate and between the source/drain regions. Device-level contacts are formed in ohmic contact with the gate conductors and with the source/drain regions. The device-level contacts terminate at substantially the same level above the semiconductor substrate. Copper interconnect lines are then formed in a level above the device-level contacts and in ohmic contact therewith to locally interconnect the plurality of transistors.

Transistor with counter-electrode connection amalgamated with the source/drain contact

The field effect device includes an active area made from semi-conducting material and a gate electrode separated from the active area by a dielectric gate material. A counter-electrode is separated from the active area by a layer of electrically insulating material. Two source/drain contacts are arranged on the active area on each side of the gate electrode. One of the source/drain contacts is made from a single material, overspills from the active area and connects the active area with the counter-electrode. The counter-electrode contact is delineated by a closed peripheral insulating pattern.

Sram integrated circuits and methods for their fabrication

SRAM ICs and methods for their fabrication are provided. One method includes forming dummy gate electrodes overlying a semiconductor substrate and defining locations of gate electrodes for two cross coupled inverters and two pass gate transistors. A first insulating layer is deposited overlying the dummy gate electrodes and gaps between the dummy gate electrodes are filled with a second insulating layer. The second insulating layer is etched to form inter-gate openings exposing portions of the substrate. The first insulating layer is etched to reduce the thickness of selected locations thereof, and the dummy gate electrodes are removed. A gate electrode metal is deposited and planarized to form gate electrodes and local interconnections coupling the gate electrodes of one inverter to a node between the pull up and pull down transistors of the other inverter and to a source/drain of one of the pass gate transistors.

Methods of forming contacts for semiconductor devices using a local interconnect processing scheme

One method disclosed herein includes forming a plurality of source/drain contacts that are conductively coupled to a source/drain region of a plurality of transistor devices, wherein at least one of the source/drain contacts is a local interconnect structure that spans the isolation region and is conductively coupled to a first source/drain region in a first active region and to a second source/drain region in a second active region, and forming a patterned mask layer that covers the first and second active regions and exposes at least a portion of the local interconnect structure positioned above an isolation region that separates the first and second active regions. The method further includes performing an etching process through the patterned mask layer to remove a portion of the local interconnect structure, thereby defining a recess positioned above a remaining portion of the local interconnect structure, and forming an insulating material in the recess.

Semiconductor device and method of manufacturing thereof

A semiconductor device includes a substrate having a top surface. A semiconductor circuit defines a circuit area on the top surface of the substrate. An interconnect is spaced apart from the circuit area and extends from the top surface into the substrate. The interconnect includes a sidewall formed of an electrically insulating material. An opening is provided in the sidewall.

PACKAGING METHOD USING SOLDER COATING BALL AND PACKAGE MANUFACTURED THEREBY

Disclosed herein a packaging method including: (A) forming a plurality of pads and another circuit pattern on a substrate; (B) forming a second dry film pattern including opening exposing the pad; (C) mounting a solder coating ball in the opening of the second dry film pattern; (D) performing a reflow process on the solder coating ball in order to allow the solder coating ball to have a modified pattern; (E) delaminating the second dry film pattern; and (F) forming a solder pattern including the modified pattern of the solder coating ball in a solder to mount a chip on the substrate using the solder pattern. 1. A packaging method comprising:(A) forming a plurality of pads and another circuit pattern on a substrate;(B) forming a second dry film pattern including opening exposing the pad;(C) mounting a solder coating ball in the opening of the second dry film pattern;(D) performing a reflow process on the solder coating ball in order to allow the solder coating ball to have a modified pattern;(E) delaminating the second dry film pattern; and(F) forming a solder pattern including the modified pattern of the solder coating ball in a solder to mount a chip on the substrate using the solder pattern.2. The packaging method as set forth in claim 1 , wherein step (A) includes:(A-1) forming a first dry film pattern having openings corresponding to the pad and another circuit pattern;(A-2) filling the first dry film pattern with copper;(A-3) delaminating the first dry film pattern; and(A-4) forming a solder resist (SR) pattern enclosing a region of the pad and burying another circuit pattern.3. The packaging method as set forth in claim 2 , wherein step (A-2) is performed by any one of a chemical vapor deposition (CVD) method claim 2 , a physical vapor deposition (PVD) method claim 2 , a subtractive method claim 2 , an additive method using an electroless copper plating or electrolytic copper plating claim 2 , a semi-additive process (SAP) claim 2 , and a modified semi- ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

To prevent cracking in a passivation film by oxidation of an antireflection film, a semiconductor device includes a metal wiring layer for a pad, an insulating layer which is provided so as to cover the metal wiring layer and which includes an opening portion from which a part of a surface of the metal wiring layer is exposed. The metal wiring layer includes a first metal layer, and a second metal layer which is provided over the first metal layer except for the opening portion and which is thinner than the first metal layer. The metal wiring layer has a groove portion in a predetermined region except for the opening portion. The first metal layer protrudes, in an eaves shape, to the groove portion. The second metal layer on a side wall inside the groove portion is thinner than the second metal layer outside the groove portion. 1. A semiconductor device comprising:a metal wiring layer for a pad; andan insulating layer which is provided so as to cover the metal wiring layer and which includes an opening portion from which a part of a surface of the metal wiring layer is exposed, a first metal layer, and', 'a second metal layer which is provided over the first metal layer except for the opening portion, which is thinner than the first metal layer, and which has a reflectance lower than that of the first metal layer,, 'wherein the metal wiring layer includes'}the metal wiring layer includes a groove portion in a predetermined region except for the opening portion,the first metal layer protrudes, in an eaves shape, to the groove portion, andthe second metal layer on a side wall inside the groove portion is thinner than the second metal layer outside the groove portion.2. The semiconductor device according to claim 1 ,wherein a film thickness of the second metal layer is zero at at least a part of the side wall inside the groove portion.3. The semiconductor device according to claim 1 ,wherein the second metal layer includes titanium nitride, andthe first metal layer ...

Forming array contacts in semiconductor memories

Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts.

PIXEL CAPACITORS

A technique comprising: forming laterally-extending switching circuitry of a device for controlling an overlying laterally-extending array of pixel conductors of said device; forming an electrically conductive laterally-extending patterned screen over said switching circuitry via a first insulating region, said patterned screen defining holes for receiving conductive interlayer connects between said switching circuitry and said array of pixel conductors; and thereafter: forming a second insulating region over said patterned screen, forming said array of pixel conductors over said patterned screen via said second insulating region for capacitative coupling with said patterned screen, forming through holes through at least said first and second insulating regions at the locations of said holes defined in said patterned screen, and forming said interlayer connects in said through holes; and wherein said patterned screen is configured such that the area of overlap between the array of pixel conductors and underlying conductive elements is substantially constant within a range of lateral positions of the pixel conductors relative to the switching circuitry, which range is greater in a first direction than 40% of the pitch of the pixel conductors in said first direction. 1. A method , comprising: forming laterally-extending switching circuitry of a device for controlling an overlying laterally-extending array of pixel conductors of said device; forming an electrically conductive laterally-extending patterned screen over said switching circuitry via a first insulating region , said patterned screen defining holes for receiving conductive interlayer connects between said switching circuitry and said array of pixel conductors; and thereafter: forming a second insulating region over said patterned screen , forming said array of pixel conductors over said patterned screen via said second insulating region for capacitative coupling with said patterned screen , forming through ...

CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME

A package includes a semiconductor device including an active surface having a contact pad. A redistribution layer (RDL) structure includes a first post-passivation interconnection (PPI) line electrically connected to the contact pad and extending on the active surface of the semiconductor device. An under-bump metallurgy (UBM) layer is formed over and electrically connected to the first PPI line. A seal ring structure extends around the upper periphery of the semiconductor device. The seal ring structure includes a seal layer extending on the same level as at least one of the first PPI line and the UBM layer. 1. A package , comprising:a semiconductor device including an active surface having a contact pad;a redistribution layer (RDL) structure including a first post-passivation interconnection (PPI) line electrically connected to the contact pad and extending on the active surface of the semiconductor device;an under-bump metallurgy (UBM) layer over and electrically connected to the first PPI line; anda seal ring structure extending around and outside the upper periphery of the semiconductor device, the seal ring structure including a seal layer extending on the same level as at least one of the first PPI line and the UBM layer.2. The package of claim 1 , wherein the seal ring structure includes a top seal layer extending on the same level as and spaced apart from the UBM layer.3. The package of claim 2 , wherein the top seal layer and the UBM layer comprise the same material.4. The package of claim 2 , wherein the seal ring structure further includes a lower seal layer connected to the top seal layer claim 2 , and extended on the same level as the first PPI line.5. The package of claim 4 , wherein the lower seal layer and the first PPI line comprise the same material.6. The package of claim 4 , wherein the lower seal layer extends on the active surface of the semiconductor device.7. The package of claim 4 , whereinthe semiconductor device further includes a chip ...

Self-Aligned Source and Drain Contacts

Self-aligned semiconductor FET device source and drain contacts and techniques for formation thereof are provided. In one aspect, a semiconductor FET device includes: at least one gate disposed on a substrate; source and drains on opposite sides of the at least one gate; gate spacers offsetting the at least one gate from the source and drains; lower source and drain contacts disposed on the source and drains; upper source and drain contacts disposed on the lower source and drain contacts; and a silicide present between the lower source and drain contacts and the upper source and drain contacts. 1. A semiconductor field-effect transistor (FET) device , comprising:at least one gate disposed on a substrate;source and drains on opposite sides of the at least one gate;gate spacers offsetting the at least one gate from the source and drains;lower source and drain contacts disposed on the source and drains;upper source and drain contacts disposed on the lower source and drain contacts; anda silicide present between the lower source and drain contacts and the upper source and drain contacts, wherein the upper source and drain contacts overhang the silicide such that a top of the silicide directly contacts only a portion of a bottom-most surface of the upper source and drain contacts.2. The semiconductor FET device of claim 1 , wherein a top surface of the lower source and drain contacts is recessed a depth d below top surfaces of the gates and the gate spacers.3. The semiconductor FET device of claim 2 , wherein d is from about 5 nm to about 10 nm and ranges therebetween.4. The semiconductor FET device of claim 2 , wherein the silicide is present in a space between the gate spacers directly over the lower source and drain contacts.5. The semiconductor FET device of claim 2 , further comprising:a metal layer disposed on the lower source and drain contacts.6. The semiconductor FET device of claim 5 , wherein the metal layer comprises nickel (Ni) claim 5 , and wherein the ...

CHEMICAL SENSOR PACKAGE FOR HIGHLY PRESSURED ENVIRONMENT

A package for a chemical sensor including an encapsulation and a pressure balancing structure is disclosed. The encapsulation encapsulates a chemical sensor and has a hole for exposing a chemical sensitive part of the chemical sensor. The pressure balancing structure balances pressure applied to the chemical sensor at the chemical sensitive part. 1. A method for packaging a chemical sensor comprising:encapsulating a chemical sensor by a encapsulation;providing a hole for exposing a chemical sensitive part of the chemical sensor; andproviding a pressure balancing structure for balancing pressure applied to the chemical sensor at the chemical sensitive part.2. The method in accordance with claim 1 , wherein the pressure balancing structure is a pressure balancing hole for applying counter pressure to the chemical sensor at the opposite side of the chemical sensitive part claim 1 , the method further comprising providing Redistribution Layer (RDL) on the chemical sensor for moving a wiring outside of the encapsulation away from the opposite side of the chemical sensitive part.3. The method in accordance with claim 1 , wherein the pressure balancing structure is a pressure balancing supporting structure for applying counter pressure to the chemical sensor at the opposite side of the chemical sensitive part claim 1 , the method further comprising providing Redistribution Layer (RDL) on the chemical sensor for moving a wiring outside of the encapsulation away from the opposite side of the chemical sensitive part.4. The method in accordance with claim 1 , further comprising providing Through Mold Via (TMV) interconnection for connecting the chemical sensor to the wiring outside of the encapsulation.5. The method in accordance with claim 1 , wherein the package is fabricated through fan-out wafer level packaging (FO-WLP) processes.6. The method in accordance with claim 1 , further comprising coating the encapsulation by a hydrophobic conformal coating. This patent ...

TEST STRUCTURE MACRO FOR MONITORING DIMENSIONS OF DEEP TRENCH ISOLATION REGIONS AND LOCAL TRENCH ISOLATION REGIONS

Embodiments are directed to a method Embodiments are directed to a test structure of a fin-type field effect transistor (FinFET). The test structure includes a first conducting layer electrically coupled to a dummy gate of the FinFET, and a second conducting layer electrically coupled to a substrate of the FinFET. The test structure further includes a third conducting layer electrically coupled to the dummy gate of the FinFET, and a first region of the FinFET at least partially bound by the first conducting layer and the second conducting layer. The test structure further includes a second region of the FinFET at least partially bound by the second conducting layer and the third conducting layer, wherein the first region comprises a first dielectric having a first dimension, and wherein the second region comprises a second dielectric having a second dimension greater than the first dimension. 1. A test structure of a fin-type field effect transistor (FinFET) comprising:a first conducting layer electrically coupled to a dummy gate of the FinFET;a second conducting layer electrically coupled to a substrate of the FinFET;a third conducting layer electrically coupled to the dummy gate of the FinFET;a first region of the FinFET at least partially bound by the first conducting layer and the second conducting layer; anda second region of the FinFET at least partially bound by the second conducting layer and the third conducting layer;wherein the first region comprises a first dielectric having a first dimension; andwherein the second region comprises a second dielectric having a second dimension greater than the first dimension.2. The test structure of claim 1 , wherein the first conducting layer is electrically coupled to the dummy gate by a first local interconnect and a first via.3. The test structure of claim 2 , wherein the second conducting layer is electrically coupled to the substrate by a second local interconnect and a second via.4. The test structure of claim 3 ...

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME

A semiconductor structure and a method for forming the same are provided. The method includes forming a gate structure over a substrate and forming source and drain regions adjacent to the gate structure. The method also includes forming a first ILD layer surrounding the gate structure over the source and drain regions and forming a contact modulation structure over the gate structure. The method also includes etching the first ILD layer and the contact modulation structure to form a first contact trench over the source and drain regions and a second contact trench over the gate structure. The method further includes forming a first contact in the first contact trench and a second contact in the second contact trench. In addition, the first ILD layer has a first etching rate and the contact modulation structure has a second etching rate that is less than the first etching rate. 1. A method for forming a semiconductor structure , comprising:forming a gate structure over a substrate;forming source and drain regions adjacent to the gate structure in the substrate;forming a first inter-layer dielectric layer surrounding the gate structure over the source and drain regions over the substrate;forming a contact modulation structure over the gate structure;etching the first inter-layer dielectric layer to form a first contact trench over the source and drain regions and etching the contact modulation structure to form a second contact trench over the gate structure by performing a same etching process using a same etchant;forming a first contact in the first contact trench and a second contact in the second contact trench,wherein the first inter-layer dielectric layer has a first etching rate and the contact modulation structure has a second etching rate that is less than the first etching rate during the same etching process.2. The method for forming a semiconductor structure as claimed in claim 1 , wherein a ratio of the first etching rate to the second etching rate is in ...

AGGRESSIVE TIP-TO-TIP SCALING USING SUBTRACTIVE INTEGRATION

An interconnect structure including a semiconductor structure on a semiconductor substrate, the semiconductor structure having a gate structure, shallow trench isolation and a source and a drain; a trench adjacent to the gate structure; a metal line adjacent to the gate structure and filling the trench, the metal line contacts one of the source and the drain; a gap in the metal line so as to create segments of the metal line; and a dielectric material filling the gap such that ends of the metal line abut the dielectric material wherein the ends of the metal line have a flat surface. 1. An interconnect structure comprising:a semiconductor structure on a semiconductor substrate, the semiconductor structure having a gate structure, shallow trench isolation and a source and a drain;a trench adjacent to the gate structure;a metal line adjacent to the gate structure and filling the trench, the metal line contacts one of the source and the drain;a gap in the metal line so as to create segments of the metal line; anda dielectric material filling the gap such that ends of the metal line abut the dielectric material wherein the ends of the metal line have a flat surface.2. The interconnect structure of wherein the source and the drain are each a raised source and a raised drain.3. The interconnect structure of wherein the metal line directly contacts the one of the source and the drain.4. The interconnect structure of wherein the metal line is tungsten or cobalt.5. The interconnect structure of wherein the dielectric material filling the gap contacts the shallow trench isolation.6. The interconnect structure of wherein the dielectric material filling the gap directly contacts the shallow trench isolation.7. The interconnect structure of wherein the semiconductor structure is a planar structure.8. The interconnect structure of wherein the semiconductor structure is a FinFET structure.9. An interconnect structure comprising:a semiconductor structure on a semiconductor substrate ...

METHOD FOR CAPPING CU LAYER USING GRAPHENE IN SEMICONDUCTOR

An interconnect structure includes a substrate, a dielectric layer on the substrate, a metal interconnect layer in the dielectric layer and in contact with the substrate, the metal interconnect layer having an upper surface flush with an upper surface of the dielectric layer, and a graphene layer on the metal interconnect layer. The graphene layer insulates a metal from air and prevents the metal from being oxidized by oxygen in the air, thereby increasing the queue time for the CMP process and the device reliability. 1. A method of manufacturing an interconnect structure , the method comprising:providing a semiconductor structure comprising a substrate, a dielectric layer on the substrate, and a metal interconnect layer in the dielectric layer and in contact with the substrate; andforming a graphene layer on the metal interconnect layer.2. The method of claim 1 , wherein forming the graphene layer comprises forming an amorphous carbon layer on the dielectric layer claim 1 , the amorphous carbon layer being adjacent to the graphene layer.3. The method of claim 1 , wherein forming the graphene layer comprises introducing methane and a carrier gas into a reaction chamber to form a mixed gas claim 1 , the mixed gas having a volume ratio of methane in a range between 0.1% and 50% claim 1 , at a temperature in a range between 300° C. and 450° C. claim 1 , under a pressure in a range between 0.1 mTorr and 10 Torr claim 1 , and a radio frequency power in a range between 10 W and 1000 W.4. The method of claim 3 , wherein the carrier gas comprises nitrogen claim 3 , or hydrogen claim 3 , or nitrogen and hydrogen.5. The method of claim 1 , further comprising claim 1 , prior to forming the graphene layer: performing a hydrogen plasma cleaning process on an upper surface of the metal interconnect layer.6. The method of claim 5 , wherein performing the hydrogen plasma cleaning process comprises: introducing a hydrogen gas into a reaction chamber at a flow rate in a range between ...

METHOD OF MANUFACTURING INTERCONNECT LAYER AND SEMICONDUCTOR DEVICE WHICH INCLUDES INTERCONNECT LAYER

A semiconductor device includes an interconnect layer on an inter-layer dielectric (ILD) structure. The ILD structure includes: first contacts, extending through the ILD structure, electrically connected to corresponding first components located in a floor structure underlying the ILD structure; at least one second component located within the ILD structure and spaced from a surface of the ILD structure (in a direction perpendicular to a plane of the ILD structure) a distance which is less than a thickness of the ILD structure; and second contacts directly contacting corresponding first regions of the at least one second component. The interconnect layer includes: first metallization segments which directly contact corresponding ones of the first contacts; and second metallization segments located over a second region of the at least one second component, a width of the second metallization segments being less than a width of the first metallization segments. 1. A semiconductor device comprising: first contacts, extending through the ILD structure, electrically connected to corresponding first components of the semiconductor device, the first components being located in a floor structure underlying the ILD structure;', 'the at least one second component being located within the ILD structure and spaced from a surface of the ILD structure, in a direction perpendicular to a plane of the surface of the ILD structure, a distance which is less than a thickness of the ILD structure; and', 'at least one second component of the semiconductor device,'}, 'second contacts directly contacting corresponding first regions of the at least one second component; and, 'an inter-layer dielectric (ILD) structure including first metallization segments which directly contact corresponding ones of the first contacts; and', 'second metallization segments located over a second region of the at least one second component, a width of the second metallization segments being less than a width ...

SURFACE AREA AND SCHOTTKY BARRIER HEIGHT ENGINEERING FOR CONTACT TRENCH EPITAXY

Forming a contact is disclosed. A trench through an interlayer dielectric layer is opened down to a substrate. The interlayer dielectric layer is formed on the substrate such that the substrate is the bottom surface of the trench. A cleaning process of the trench is performed. The bottom surface of the trench is recessed. A trench contact epitaxial layer is formed in the trench. An oxide layer is formed on top of the trench contact epitaxial layer in the trench. A metal oxide layer is formed on top of the oxide layer in the trench. A metal contact is formed on top of the metal oxide layer, where the oxide layer and the metal oxide layer together form a dipole layer. 1. A method of forming a contact , the method comprising:opening a trench through an interlayer dielectric layer down to a substrate, wherein the interlayer dielectric layer is formed on the substrate such that the substrate is a bottom surface of the trench;performing a cleaning process of the trench;recessing the bottom surface of the trench, the recessing forms angled planes at a bottom of the trench through the bottom surface of the substrate;forming a trench contact epitaxial layer in the trench;forming an oxide layer on top of the trench contact epitaxial layer in the trench;forming a metal oxide layer on top of the oxide layer in the trench; andforming a metal contact on top of the metal oxide layer, wherein the oxide layer and the metal oxide layer together form a dipole layer.2. The method of claim 1 , wherein the cleaning process of the trench includes baking in hydrogen gas.3. The method of claim 2 , wherein the cleaning process of the trench further includes in-situ plasma cleaning of the trench.4. The method of claim 3 , wherein the in-situ plasma cleaning is with a compound of hydrogen and nitrogen claim 3 , a compound of nitrogen and fluorine claim 3 , or both the compound of hydrogen and nitrogen and the compound of nitrogen and fluorine.5. The method of claim 1 , wherein recessing the ...

SURFACE AREA AND SCHOTTKY BARRIER HEIGHT ENGINEERING FOR CONTACT TRENCH EPITAXY

Forming a contact is disclosed. A trench through an interlayer dielectric layer is opened down to a substrate. The interlayer dielectric layer is formed on the substrate such that the substrate is the bottom surface of the trench. A cleaning process of the trench is performed. The bottom surface of the trench is recessed. A trench contact epitaxial layer is formed in the trench. An oxide layer is formed on top of the trench contact epitaxial layer in the trench. A metal oxide layer is formed on top of the oxide layer in the trench. A metal contact is formed on top of the metal oxide layer, where the oxide layer and the metal oxide layer together form a dipole layer. 1. A contact for a semiconductor device , the semiconductor device comprising:a trench contact epitaxial layer formed in a trench;a dipole layer formed on top of the trench contact epitaxial layer; anda metal contact formed on top of the dipole layer.2. The semiconductor device of claim 1 , wherein the trench is formed through an interlayer dielectric layer.3. The semiconductor device of claim 2 , wherein the interlayer dielectric layer is on top of a substrate.4. The semiconductor device of claim 3 , wherein the trench contact epitaxial layer is partially formed in the substrate.5. The semiconductor device of claim 1 , wherein the dipole layer includes an oxide layer formed on top of the trench contact epitaxial layer in the trench and a metal oxide layer formed on top of the oxide layer in the trench.6. The semiconductor device of claim 1 , wherein a bottom surface of the trench has been recessed.7. The semiconductor device of claim 6 , wherein the bottom surface of the trench has been recessed along planes claim 6 , such that the planes are at angles defined by a bottom surface plane of the trench.8. The semiconductor device of claim 1 , wherein the dipole layer is configured to reduce contact resistance between the trench contact epitaxial layer and the metal contact as compared to having no dipole ...

SEMICONDUCTOR DEVICE INCLUDING WRAP AROUND CONTACT, AND METHOD OF FORMING THE SEMICONDUCTOR DEVICE

A method of forming a wrap around contact, includes forming a plurality of semiconductor layers on a plurality of fin structures, forming a sacrificial gate on the plurality of semiconductor layers, forming an epitaxial layer on the plurality of fin structures and on a sidewall of the plurality of semiconductor layers, forming a gate structure by replacing the sacrificial gate and the plurality of semiconductor layers with a metal layer, and forming a wrap around contact on the epitaxial layer. 1. A method of forming a wrap around contact , comprising:forming a plurality of semiconductor layers on a plurality of fin structures;forming a sacrificial gate on the plurality of semiconductor layers;forming an epitaxial layer on the plurality of fin structures and on a sidewall of the plurality of semiconductor layers;forming a gate structure by replacing the sacrificial gate and the plurality of semiconductor layers with a metal layer; andforming a wrap around contact on the epitaxial layer.2. The method of claim 1 , further comprising:forming a plurality of shallow trench isolation (STI) regions between the plurality of fin structures, the wrap around contact being formed on the STI regions.3. The method of claim 1 , wherein the forming of the gate structure comprises forming a plurality of gate structures.4. The method of claim 3 , wherein the gate structure comprises a spacer formed on a side of the metal layer claim 3 , and the forming of the wrap around contact comprises forming the wrap around contact on the spacer and on the epitaxial layer between the plurality of gate structures.5. The method of claim 1 , wherein the forming of the wrap around contact comprises:forming a conformal metal liner layer; andforming a barrier layer on the metal liner layer.6. The method of claim 5 , wherein the forming of the wrap around contact comprises:annealing the metal liner layer to form a metal silicide layer, the wrap around contact comprising the metal silicide layer and the ...

FinFET VARACTOR

A varactor transistor includes a semiconductor fin having a first conductivity type, a plurality of gate structures separated from each other and surrounding a portion of the semiconductor fin. The plurality of gates structures include a dummy gate structure on an edge of the semiconductor fin, and a first gate structure spaced apart from the dummy gate structure. The dummy gate structure and the gate structure each include a gate insulator layer on a surface portion of the semiconductor fin, a gate on the gate insulator layer, and a spacer on the gate. The varactor transistor also includes a raised source/drain region on the semiconductor fin and between the dummy gate structure and the first gate structure, the raised source/drain region and the gate of the dummy gate structure being electrically connected to a same potential. 1. A varactor transistor , comprising:a semiconductor fin having a first conductivity type;a plurality of gate structures separated from each other and surrounding a portion of the semiconductor fin, the plurality of gates structures comprising a dummy gate structure on an edge of the semiconductor fin, and a first gate structure spaced apart from the dummy gate structure, the dummy gate structure and the gate structure each comprising a gate insulator layer on a surface portion of the semiconductor fin, a gate on the gate insulator layer, and a spacer on the gate; anda raised source/drain region on the semiconductor fin and between the dummy gate structure and the first gate structure, the raised source/drain region and the gate of the dummy gate structure being electrically connected to a same potential.2. The varactor transistor of claim 1 , further comprising a substrate having a second conductivity type different from the first conductivity type claim 1 , the semiconductor fin on the substrate and a reverse pn junction formed between the semiconductor fin and the substrate.3. The varactor transistor of claim 1 , wherein the dummy gate ...

Low-k Dielectric and Processes for Forming Same

Embodiments described herein relate generally to methods for forming low-k dielectrics and the structures formed thereby. In some embodiments, a dielectric is formed over a semiconductor substrate. The dielectric has a k-value equal to or less than 3.9. Forming the dielectric includes using a plasma enhanced chemical vapor deposition (PECVD). The PECVD includes flowing a diethoxymethylsilane (mDEOS, C 5 H 14 O 2 Si) precursor gas, flowing an oxygen (O 2 ) precursor gas; and flowing a carrier gas. A ratio of a flow rate of the mDEOS precursor gas to a flow rate of the carrier gas is less than or equal to 0.2.

Device and Method for High Pressure Anneal

Embodiment methods for performing a high pressure anneal process during the formation of a semiconductor device, and embodiment devices therefor, are provided. The high pressure anneal process may be a dry high pressure anneal process in which a pressurized environment of the anneal includes one or more process gases. The high pressure anneal process may be a wet anneal process in which a pressurized environment of the anneal includes steam.

Epitaxial Layers in Source/Drain Contacts and Methods of Forming the Same

A method includes providing a p-type S/D epitaxial feature and an n-type source/drain (S/D) epitaxial feature, forming a semiconductor material layer over the n-type S/D epitaxial feature and the p-type S/D epitaxial feature, processing the semiconductor material layer with a germanium-containing gas, where the processing of the semiconductor material layer forms a germanium-containing layer over the semiconductor material layer, etching the germanium-containing layer, where the etching of the germanium-containing layer removes the germanium-containing layer formed over the n-type S/D epitaxial feature and the semiconductor material layer formed over the p-type S/D epitaxial feature, and forming a first S/D contact over the semiconductor material layer remaining over the n-type S/D epitaxial feature and a second S/D contact over the p-type S/D epitaxial feature. The semiconductor material layer may have a composition similar to that of the n-type S/D epitaxial feature.

Semiconductor Device Including a Conductive Feature Over an Active Region

A semiconductor device includes a substrate having an active region, a first gate structure over a top surface of the substrate, a second gate structure over the top surface of the substrate, a pair of first spacers on each sidewall of the first gate structure, a pair of second spacers on each sidewall of the second gate structure, an insulating layer over at least the first gate structure, a first conductive feature over the active region and a second conductive feature over the substrate. Further, the second gate structure is adjacent to the first gate structure and a top surface of the first conductive feature is coplanar with a top surface of the second conductive feature. 1. A method comprising:forming an active region in a substrate;forming a first gate structure and a second gate structure on the substrate, wherein the second gate structure is adjacent to the first gate structure;forming an insulating layer on the first gate structure and the second gate structure;forming a pair of first spacers on each sidewall of the first gate structure;forming a pair of second spacers on sidewalls of the second gate structure;forming a first conductive feature over the active region;etching a portion of the insulating layer over the first gate structure;etching a portion of the first gate structure; anddepositing a second conductive feature over at least the first gate structure, wherein a portion of a top surface of the second conductive feature is coplanar with a top surface of the insulating layer remaining over the second gate structure.2. The method of further comprising:forming a third conductive feature over the substrate, wherein a top surface of the first conductive feature is coplanar with a top surface of the third conductive feature.3. The method of further comprising:forming a fourth conductive feature, wherein the fourth conductive feature is over the first gate structure or the second gate structure.4. The method of claim 3 , wherein the second conductive ...

Partial Barrier Free Vias for Cobalt-Based Interconnects and Methods of Fabrication Thereof

Partial barrier-free vias and methods for forming such are disclosed herein. An exemplary interconnect structure of a multilayer interconnect feature includes a dielectric layer. A cobalt-comprising interconnect feature and a partial barrier-free via are disposed in the dielectric layer. The partial barrier-free via includes a first via plug portion disposed on and physically contacting the cobalt-comprising interconnect feature and the dielectric layer, a second via plug portion disposed over the first via plug portion, and a via barrier layer disposed between the second via plug portion and the first via plug portion. The via barrier layer is further disposed between the second via plug portion and the dielectric layer. The cobalt-comprising interconnect feature can be a device-level contact or a conductive line of the multilayer interconnect feature. The first via plug portion and the second via plug portion can include tungsten, cobalt, and/or ruthenium. 1. An interconnect structure comprising: a via barrier layer that physically contacts the dielectric layer; and', 'a via plug disposed between the via barrier layer and the first interconnect feature, such that the via plug physically contacts the first interconnect feature and the dielectric layer., 'a via disposed in a dielectric layer, wherein the via connects a first interconnect feature and a second interconnect feature, and further wherein the via includes2. The interconnect structure of claim 1 , wherein:the via plug is a first via plug portion; andthe via further includes a second via plug portion disposed over the via barrier layer, wherein the via barrier layer is disposed between the first via plug portion and the second via plug portion, and further wherein the via barrier layer is disposed between the dielectric layer and the second via plug portion.3. The interconnect structure of claim 2 , wherein a material of the first via plug portion is the same as a material of the second via plug portion.4. ...

Semiconductor device and semiconductor chip

Provided is a semiconductor device capable of improving relative accuracy of semiconductor elements and a yield of a semiconductor integrated circuit device. The semiconductor device includes a flat region formed on a surface of a semiconductor substrate, and having an outer peripheral shape formed by regional sides and regional chamfer portions; an outer peripheral region surrounding the flat region, and having a uniform height different from a height of the flat region; a plurality of semiconductor elements having similar shapes or the same shape, and formed on the flat region; and a wiring metal connecting the plurality of semiconductor elements via contact holes formed in a second insulating film on the semiconductor elements.

SEMICONDUCTOR DEVICE HAVING A LINER LAYER WITH A CONFIGURED PROFILE AND METHOD OF FABRICATING THEREOF

Devices and methods that include for configuring a profile of a liner layer before filling an opening disposed over a semiconductor substrate. The liner layer has a first thickness at the bottom of the opening and a second thickness a top of the opening, the second thickness being smaller that the first thickness. In an embodiment, the filled opening provides a contact structure. 1. A method comprising:forming an opening in a layer over a semiconductor substrate, wherein the opening has a sidewall and a bottom;performing a first deposition process to form a layer of material of a first composition on the sidewall and the bottom;forming a masking layer in the opening over the layer;etching a first portion of the layer while using the masking layer to protect a second portion of the layer;removing the masking layer to expose the second portion of the layer;performing a second deposition process to deposit material of the first composition over the second portion of the layer and on the sidewall of the opening; andafter performing the second deposition process, filling the opening with a conductive material.2. The method of claim 1 , wherein the first deposition process includes forming the layer of material of the first composition overlying a second composition claim 1 , the second composition different than the first composition.3. The method of claim 1 , wherein the first composition is TiN.4. The method of claim 1 , further comprising:after removing the masking layer and before performing the second deposition process, performing another etching to remove a region of the second portion of the layer disposed on the sidewall of the opening.5. The method of claim 4 , wherein the another etching does not remove the second portion of the layer from the bottom of the opening.6. The method of claim 4 , further comprising:performing a directional plasma treatment on the layer after the first deposition process.7. The method of claim 6 , wherein the directional plasma ...

Integrated circuit structure having gate contact and method of forming same

One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include: a gate stack having a gate conductor therein over a substrate, the gate stack being within a dielectric layer; a source/drain contact to a source/drain region over the substrate and adjacent to the gate stack within the dielectric layer; an upper conductor extending above, without contacting, the source/drain contact, wherein the upper conductor extends within the dielectric layer to contact the gate conductor within the gate stack.

Embedded Transistor

An embedded transistor for an electrical device, such as a DRAM memory cell, and a method of manufacture thereof is provided. A trench is formed in a substrate and a gate dielectric and a gate electrode formed in the trench of the substrate. Source/drain regions are formed in the substrate on opposing sides of the trench. In an embodiment, one of the source/drain regions is coupled to a storage node and the other source/drain region is coupled to a bit line. In this embodiment, the gate electrode may be coupled to a word line to form a DRAM memory cell. A dielectric growth modifier may be implanted into sidewalls of the trench in order to tune the thickness of the gate dielectric. 1. A semiconductor device comprising:a semiconductor substrate;a plurality of trenches formed within the semiconductor substrate, each one of the plurality of trenches having a first height;one or more dielectric materials filling a first one of the plurality of trenches;a gate dielectric lining a second one of the plurality of trenches, the gate dielectric having a first thickness that varies along a first sidewall of the second one of the plurality of trenches and has a second thickness that varies along a second sidewall of the second one of the plurality of trenches;a dielectric growth modifier located within the semiconductor substrate adjacent to the gate dielectric; anda gate electrode located within the second one of the plurality of trenches adjacent to the gate dielectric.2. The semiconductor device of claim 1 , wherein the first thickness at a top of the first one of the plurality of trenches is between about 30 Å and about 40 Å.3. The semiconductor device of claim 2 , wherein the first thickness at a bottom of the first one of the plurality of trenches is less than 20 Å.4. The semiconductor device of claim 3 , wherein the second thickness at the top of the first one of the plurality of trenches is between about 30 Å and about 40 Å.5. The semiconductor device of claim 4 , ...

Devices Having a Semiconductor Material That Is Semimetal in Bulk and Methods of Forming the Same

Devices, and methods of forming such devices, having a material that is semimetal when in bulk but is a semiconductor in the devices are described. An example structure includes a substrate, a first source/drain contact region, a channel structure, a gate dielectric, a gate electrode, and a second source/drain contact region. The substrate has an upper surface. The channel structure is connected to and over the first source/drain contact region, and the channel structure is over the upper surface of the substrate. The channel structure has a sidewall that extends above the first source/drain contact region. The channel structure comprises a bismuth-containing semiconductor material. The gate dielectric is along the sidewall of the channel structure. The gate electrode is along the gate dielectric. The second source/drain contact region is connected to and over the channel structure.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

According to one embodiment, a semiconductor device includes a plurality of wires arranged in parallel at a predetermined pitch, a plurality of first contacts that are each connected to an odd-numbered wire among the wires and are arranged in parallel in an orthogonal direction with respect to a wiring direction of the wires, and a plurality of second contacts that are each connected to an even-numbered wire among the wires and are arranged in parallel in an orthogonal direction with respect to the wiring direction of the wires in such a way as to be offset from the first contacts in the wiring direction of the wires, in which the first contacts are offset from the second contacts by a pitch of the wires in an orthogonal direction with respect to the wiring direction of the wires. 17-. (canceled)8. A manufacturing method of a semiconductor device comprising:forming core patterns, onto which a plurality of linear shaped first mask patterns, each of which is offset in a middle by a wiring pitch in an orthogonal direction with respect to a wiring direction, is transferred, on a processing target layer;forming first sidewall patterns on sidewalls of the core patterns;removing the core patterns while leaving the first sidewall patterns on the processing target layer;forming a second mask pattern that covers part of a space between the first sidewall patterns on the processing target layer; andforming first openings in the processing target layer by processing the processing target layer exposed from the first sidewall patterns and the second mask pattern.9. The manufacturing method of a semiconductor device according to claim 8 , wherein a width of the first mask patterns and an interval between the first mask patterns are twice the wiring pitch.10. The manufacturing method of a semiconductor device according to claim 8 , further comprising slimming the core patterns before forming the first sidewall patterns.11. The manufacturing method of a semiconductor device ...

STACK TYPE SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING AND TESTING THE SAME

There are proposed a stack type semiconductor device and a method of fabricating and testing the same. A stack type semiconductor device according to an embodiment of the present invention includes a plurality of contact pads externally exposed, a via array electrically connected to the contact pads, a semiconductor substrate configured to have vias, forming the via array, electrically conductive with each other or insulated from each other, and a bias pad configured to supply a bias to the semiconductor substrate, wherein the semiconductor substrate may be subject to back-grinding. 1. A method of fabricating each of dies of a stack type semiconductor device , the method comprising:forming a first type well having a first height on a lower side of a semiconductor substrate;forming one or more second type doping regions within the first type well at bottoms of regions where vias are expected to be formed;forming a first type doping region within the first type well at a bottom of a region where a bias contact is expected to be formed;forming the vias to be electrically connected to the second type doping regions, respectively;forming the bias contact to be electrically connected to the first type doping region;forming contact pads electrically connected the respective vias; andforming a bias pad electrically connected to the bias contact.2. The method according to claim 1 , further comprising performing a test by supplying a positive voltage or a negative voltage to the bias pad.3. The method according to claim 2 , further comprising performing back-grinding on the semiconductor substrate up to a position equal to or higher than the first height claim 2 , after performing the test.4. The method according to claim 1 , further comprising forming a wire layer configured to electrically couple the vias and the respective contact pads before forming the contact pads claim 1 , after forming the vias.5. The method according to claim 4 , further comprising performing a test ...

METHODS OF FABRICATING SEMICONDUCTOR DEVICES HAVING WRAPPING LAYER

A method of fabricating a semiconductor device includes providing a substrate having first areas and second areas, forming first metal wires on the first areas of the substrate, forming second metal wires on the second areas of the substrate, forming an interlayer insulation layer to cover the first and second metal wires, forming pad patterns on the first metal wires, forming a passivation layer to cover the pad patterns on the interlayer insulation layer, and forming a wrapping layer on the passivation layer. The wrapping layer includes first openings that are vertically aligned with the pad patterns, and second openings that are disposed on the second areas and that horizontally connect the first openings with each other. 1. A method of fabricating a semiconductor device , the method comprising:providing a substrate having first areas and second areas;forming first metal wires on the first areas of the substrate;forming second metal wires on the second areas of the substrate;forming an interlayer insulation layer to cover the first and second metal wires;forming pad patterns on the first metal wires;forming a passivation layer to cover the pad patterns on the interlayer insulation layer; andforming a wrapping layer on the passivation layer,wherein the wrapping layer includes:first openings that are vertically aligned with the pad patterns; andsecond openings that are disposed on the second areas and that horizontally connect the first openings with each other.2. The method as claimed in claim 1 , wherein the wrapping layer includes a photo-sensitive polyimide.3. The method as claimed in claim 1 , wherein the first openings are vertically aligned with portions of the pad patterns and the first metal wires.4. The method as claimed in claim 1 , wherein the second openings include two straight lines parallel to each other.5. The method as claimed in claim 1 , wherein side edges of the first openings and the second openings abutting on the wrapping layer are in a form ...

VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME

A vertical memory device includes first gate electrodes stacked on a cell region of a substrate and spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate, a channel extending through the first gate electrodes and extending in the vertical direction, a first contact plug structure contacting a corresponding one of the first gate electrodes, extending in the vertical direction, and including a first metal pattern, a first barrier pattern covering a lower surface and a sidewall of the first metal pattern and a first metal silicide pattern covering a lower surface and a sidewall of the first barrier pattern, and a second contact plug structure extending in the vertical direction on a peripheral circuit region of the substrate and including a second metal pattern and a second barrier pattern covering a lower surface and a sidewall of the second metal pattern. 1. A method of manufacturing a vertical memory device , the method comprising:forming a circuit pattern on a substrate;forming a first insulating interlayer to cover the circuit pattern;forming first gate electrodes spaced apart from each other on the first insulating interlayer in a vertical direction substantially perpendicular to an upper surface of the substrate, the first gate electrodes being covered by a second insulating interlayer and including a low electrical resistance metal and a metal nitride;forming first contact holes extending through the second insulating interlayer in the vertical direction to expose portions of the first gate electrodes, respectively;forming a polysilicon layer on the exposed portions of the first gate electrodes, sidewalls of the first contact holes, and the second insulating interlayer;forming a barrier layer on the polysilicon layer and the second insulating interlayer;transforming a portion of the barrier layer and the polysilicon layer into a metal silicide layer; andforming first metal patterns to fill ...

BACKSIDE CONTACT TO A FINAL SUBSTRATE

Device structures and fabrication methods for a backside contact to a final substrate. An electrically-conducting connection is formed that extends through a device layer of a silicon-on-insulator substrate and partially through a buried insulator layer of the silicon-on-insulator substrate. After the electrically-conducting connection is formed, a handle wafer of the silicon-on-insulator substrate is removed. After the handle wafer is removed, the buried insulator layer is partially removed to expose the electrically-conducting connection. After the buried insulator layer is partially removed, a final substrate is coupled to the buried insulator layer such that the electrically-conducting connection is coupled with the final substrate. 1. A method for fabricating a backside contact using a silicon-on-insulator substrate that includes a device layer , a buried insulator layer , and a handle wafer , the method comprising:forming an electrically-conducting connection in a trench that extends through the device layer and partially through the buried insulator layer;after the electrically-conducting connection is formed, removing the handle wafer;after the handle wafer is removed, partially removing the buried insulator layer to expose the electrically-conducting connection; andafter the buried insulator layer is partially removed, coupling a final substrate to the buried insulator layer such that the electrically-conducting connection contacts the final substrate,wherein the backside contact comprises the electrically-conducting connection.2. The method of wherein the buried insulator layer includes a first surface in direct contact with the device layer and a second surface in direct contact with the handle wafer claim 1 , and the trench has a bottom surface that terminates within the buried insulator layer between the first surface and the second surface when the electrically-conducting connection is formed.3. The method of wherein forming the electrically-conducting ...

Interconnect structures and fabrication method thereof

An interconnect structure is provided. The interconnect structure includes a substrate; and at least a first interconnect component having a first contact region and a second interconnect component having a second contact region. The interconnect structure also includes an interlayer dielectric layer formed on the semiconductor substrate at a same layer as the first interconnect component and the second interconnect component. Further, the interconnect structure includes an interconnect line layer electrically connecting the first contact region and the second contact region formed inside the interlayer dielectric layer.

AIR GAP BETWEEN TUNGSTEN METAL LINES FOR INTERCONNECTS WITH REDUCED RC DELAY

Systems and methods are directed to a semiconductor device, which includes an integrated circuit, wherein the integrated circuit includes at least a first layer comprising two or more Tungsten lines and at least one air gap between at least two Tungsten lines, the air gaps to reduce capacitance. An interposer is coupled to the integrated circuit, to reduce stress on the two or more Tungsten lines and the at least one air gap. A laminated package substrate may be attached to the interposer such that the interposer is configured to absorb mechanical stress induced by mismatch in coefficient of thermal expansion (CTE) between the laminated package substrate and the interposer and protect the air gap from the mechanical stress. 1. A semiconductor device comprising:an integrated circuit comprising a first layer comprising two or more Tungsten lines and at least one air gap between at least two Tungsten lines; andan interposer coupled to the integrated circuit, the interposer configured to reduce stress on the two or more Tungsten lines and the at least one air gap.2. The semiconductor device of claim 1 , wherein the Tungsten lines are formed from a Fluorine (F) free process.3. The semiconductor device of claim 1 , wherein the Tungsten lines are deposited by physical vapor deposition (PVD).4. The semiconductor device of claim 1 , further comprising a second layer comprising one or more Tungsten lines claim 1 , wherein the second layer is separated from the first layer by a cap layer claim 1 , and wherein the Tungsten lines of the first layer are connected to Tungsten lines of the second layer through vias.5. The semiconductor device of claim 1 , wherein the first layer further comprises an interlayer dielectric material.6. The semiconductor device of claim 1 , wherein the Tungsten lines are formed using dual damascene (DD) or etch claim 1 , followed by chemical mechanical polishing (CMP).7. The semiconductor device of claim 1 , wherein the air gap is of narrow width.8. ...

METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE

A method for fabricating semiconductor device includes the steps of: forming a dielectric layer on a substrate; forming a stop layer between the dielectric layer and the substrate, wherein the stop layer contacts the substrate directly and the dielectric layer covers the top surface of the stop layer; forming an opening in the dielectric layer, wherein the dielectric layer comprises a damaged layer adjacent to the opening; forming a dielectric protective layer in the opening; forming a metal layer in the opening; removing the damaged layer and the dielectric protective layer to form a void, wherein the void exposes a top surface of the substrate; and forming a cap layer on and covering the dielectric layer, the void, and the metal layer. 1. A method for fabricating semiconductor device , comprising:providing a substrate;forming a dielectric layer on the substrate;forming a stop layer between the dielectric layer and the substrate, wherein the stop layer contacts the substrate directly and the dielectric layer covers the top surface of the stop layer;forming an opening in the dielectric layer, wherein the dielectric layer comprises a damaged layer adjacent to the opening;forming a dielectric protective layer in the opening;forming a metal layer in the opening;removing the damaged layer and the dielectric protective layer to form a void, wherein the void exposes a top surface of the substrate and none of the damaged layer of the dielectric layer is remained between the dielectric layer and the void; andforming a cap layer on and covering the dielectric layer, the void, and the metal layer.2. The method of claim 1 , further comprising:forming the opening in the stop layer and the dielectric layer;forming the dielectric protective layer on the sidewalls of the dielectric layer and the stop layer; andforming the metal layer in the opening.3. The method of claim 2 , wherein the void comprisesa first bottom surface aligned to a top surface of the substrate; anda second ...

SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF

A method for fabricating a semiconductor device is provided. A substrate having a dummy gate thereon is prepared. A spacer is disposed on a sidewall of the dummy gate. A source/drain region is disposed adjacent to the dummy gate. A sacrificial layer is then formed on the source/drain region. A cap layer is then formed on the sacrificial layer. A top surface of the cap layer is coplanar with a top surface of the dummy gate. A replacement metal gate (RMG) process is performed to transform the dummy gate into a replacement metal gate. An opening is then formed in the cap layer to expose a top surface of the sacrificial layer. The sacrificial layer is removed through the opening, thereby forming a lower contact hole exposing a top surface of the source/drain region. A lower contact plug is then formed in the lower contact hole. 1: A method for fabricating a semiconductor device , comprising:providing a substrate having a dummy gate thereon, a spacer on a sidewall of the dummy gate, and a source/drain region adjacent to the dummy gate;forming a sacrificial layer on the source/drain region;forming a cap layer on the sacrificial layer, wherein a top surface of the cap layer is coplanar with a top surface of the dummy gate;performing a replacement metal gate (RMG) process to transform the dummy gate into a replacement metal gate;forming an opening in the cap layer to expose a top surface of the sacrificial layer;removing the sacrificial layer through the opening to thereby form a lower contact hole exposing a top surface of the source/drain region; andforming a lower contact plug in the lower contact hole.2: The method for fabricating a semiconductor device according to claim 1 , further comprising:depositing an inter-layer dielectric (ILD) layer on the replacement metal gate, the cap layer, and the lower contact plug; andforming an upper contact plug in the ILD layer, wherein the upper contact plug is electrically connected to the lower contact plug.3: The method for ...

INTEGRATED CIRCUIT STRUCTURE HAVING GATE CONTACT AND METHOD OF FORMING SAME

One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include: a gate stack having a gate conductor therein over a substrate, the gate stack being within a dielectric layer; a source/drain contact to a source/drain region over the substrate and adjacent to the gate stack within the dielectric layer; a conductor extending above, without contacting, the source/drain contact and extending within the dielectric layer to contact the gate conductor within the gate stack. 1. A method of forming an integrated circuit structure , the method comprising:lowering a height of a source/drain contact within a first dielectric layer to a height below a height of a gate conductor of a gate stack, the gate stack being adjacent to the gate conductor within the dielectric layer; andforming a conductor over and without contacting the source/drain contact, the conductor contacting the gate conductor.2. The method of claim 1 , wherein the lowering of the source/drain contact includes:recessing a portion of the source/drain contact within the first dielectric layer to create a first opening in the first dielectric layer over the recessed portion of the source/drain contact; andforming an insulator layer over the recessed portion of the source/drain contact within the first opening.3. The method of claim 2 , wherein forming the insulator layer includes forming a low-k dielectric layer over the recessed portion of the source/drain contact within the first opening.4. The method of claim 2 , wherein recessing the portion of the source/drain contact includes recessing the portion of the source/drain contact such that the portion of the source/drain contact remains within the first dielectric layer over a source/drain region.5. The method of claim 2 , wherein forming the conductor includes:after the forming of the insulating layer, forming a second dielectric layer over the first dielectric layer and the insulating layer;forming a second ...

INTERCONNECT STRUCTURE AND METHOD OF FABRICATING SAME

A structure comprises a passivation layer formed over a semiconductor substrate, a connection pad enclosed by the passivation layer, a redistribution layer formed over the passivation layer, wherein the redistribution layer is connected to the connection pad, a bump formed over the redistribution layer, wherein the bump is connected to the redistribution layer and a molding compound layer formed over the redistribution layer. The molding compound layer comprises a flat portion, wherein a bottom portion of the bump is embedded in the flat portion of the molding compound layer and a protruding portion, wherein a middle portion of the bump is surrounded by the protruding portion of the molding compound layer.

METHOD OF MANUFACTURING INTEGRATED CIRCUIT DEVICE

A method of manufacturing an integrated circuit device includes forming multilayered stack structures that extend parallel to and separated from one another on a substrate, followed by forming a buried conductive layer including a plurality of conductive line patterns that extend parallel to an extending direction of the multilayered stack structures and alternate with the multilayered stack structures; removing portions of the buried conductive layer to thereby separate the plurality of conductive line patterns of the buried conductive layer from one another as a plurality of contact plugs and, at the same time, form a plurality of insulating fence spaces that alternate with the plurality of contact plugs in the extending direction of the multilayered stack structures; and forming a plurality of insulating fences that fill the plurality of insulating fence spaces and include a plurality of insulating line patterns extending parallel to one another. 1. A method of manufacturing an integrated circuit device , the method comprising:forming a plurality of multilayered stack structures that extend parallel to and separated from one another on a substrate;forming a buried conductive layer including a plurality of conductive line patterns that extend parallel to an extending direction of the multilayered stack structures, each of the plurality of conductive line patterns being between each of the multilayered stack structures;removing portions of the buried conductive layer that correspond to a plurality of fence line areas which are spaced apart from one another and extend parallel to one another in a direction crossing the extending direction of the multilayered stack structures, to thereby separate the plurality of line patterns of the buried conductive layer from one another as a plurality of contact plugs and, at the same time, form a plurality of insulating fence spaces that alternate with the plurality of contact plugs in the extending direction of the multilayered ...

SELF-ALIGNED LOCAL INTERCONNECT TECHNOLOGY

A self-aligned interconnect structure includes a fin structure patterned in a substrate; an epitaxial contact disposed over the fin structure; a first metal gate and a second metal gate disposed over and substantially perpendicular to the epitaxial contact, the first metal gate and the second metal gate being substantially parallel to one another; and a metal contact on and in contact with the substrate in a region between the first and second metal gates. 1. A method for making a self-aligned interconnect structure , the method comprising:forming a first gate and a second gate over a source/drain contact, the first gate and the second gate comprising a replacement gate material;patterning an interconnect structure in an interconnect patterning stack between the first gate and the second gate such that the interconnect structure pattern laterally connects the first gate and the second gate; andfilling the interconnect patterning stack, the first gate, and the second gate with a gate metal to form an interconnect structure that laterally connects the first gate and the second gate and directly contacts the substrate.2. The method of claim 1 , wherein the first gate and the second gate each comprises amorphous silicon before patterning the contact.3. The method of claim 1 , wherein the first gate and the second gate each comprises polysilicon.4. The method of claim 1 , wherein an inter-layer dielectric layer (ILD) layer surrounds the source/drain contact.5. The method of claim 1 , wherein the source/drain contact is an epitaxial contact.6. The method of further comprising claim 1 , prior to patterning the interconnect structure claim 1 , performing an etching process to remove the replacement gate material and expose fins beneath the first gate and the second gate.7. The method of claim 6 , wherein the etching process is a directional etching process.8. The method of claim 7 , wherein the directional etching process is a reactive ion etching process.9. The method of ...

Integrated circuit device and method of manufacturing the same

An integrated circuit device may include a fin-type active region extending in a first direction on a substrate; an insulating separation structure extending in a second direction that intersects the first direction on the fin-type active region; a pair of split gate lines spaced apart from each other with the insulating separation structure therebetween and extending in the second direction to be aligned with the insulating separation structure; a pair of source/drain regions located on the fin-type active region and spaced apart from each other with the insulating separation structure therebetween; and a jumper contact located over the insulating separation structure and connected between the pair of source/drain regions.

MEMORY STRUCTURE AND MANUFACTURING METHOD THEREOF

A memory structure including a substrate, a memory cell structure, and a protective layer structure is provided. The memory cell structure is disposed on the substrate and has a first side and a second side opposite to each other. The protective layer structure covers the memory cell structure. The material of the protective layer structure is nitride. The protective layer structure is a continuous structure. The height of the protective layer structure adjacent to the second side of the memory cell structure is greater than the height of the protective layer structure adjacent to the first side of the memory cell structure. 1. A memory structure , comprising:a substrate;a memory cell structure disposed on the substrate and having a first side and a second side opposite to each other; anda protective layer structure covering the memory cell structure, whereina material of the protective layer structure is nitride,the protective layer structure is a continuous structure, anda height of the protective layer structure adjacent to the second side of the memory cell structure is greater than a height of the protective layer structure adjacent to the first side of the memory cell structure.2. The memory structure of claim 1 , wherein the memory cell structure comprises:a first dielectric layer disposed on the substrate;a charge storage structure disposed on the first dielectric layer;a second dielectric layer disposed on the charge storage structure; anda first conductive layer disposed on the second dielectric layer.3. The memory structure of claim 2 , wherein the memory cell structure further comprises:a metal silicide layer disposed on the first conductive layer;a first cap layer disposed on the first conductive layer; anda second cap layer disposed on the first cap layer.4. The memory structure of claim 1 , wherein the protective layer structure comprises a first spacer disposed on a sidewall of the first side of the memory cell structure and on a sidewall of the ...

SEMICONDUCTOR DEVICE WITH TRANSISTOR LOCAL INTERCONNECTS

A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate. The first transistor and a second transistor are formed on the semiconductor substrate. Each transistor comprises a source, a drain, and a gate. The gate of the first transistor extends longitudinally as part of a first linear strip and the gate of the second transistor extends longitudinally as part of the second linear strip parallel to and spaced apart from the first linear strip. A first CB layer forms a local interconnect layer electrically connected to the gate of the first transistor. A second CB layer forms a local interconnect layer electrically connected to the gate of the second transistor. A CA layer forms a local interconnect layer extending longitudinally between a first end and a second end of the CA layer. The CA layer is electrically connected to the first and second CB layers. The first CB layer is electrically connected adjacent the first end of the CA layer and the second layer is electrically connected adjacent the second end of the CA layer. The first CB layer, the second CB layer and the CA layer are disposed between a first metal layer and the semiconductor substrate. The first metal layer being disposed above each source, each drain, and each gate of the first and second transistors. The CA layer extends substantially parallel to the first and second linear strips and is substantially perpendicular to the first and second CB layers. At least one via selectively provides an electrical connection between the CA or CB layers and the at least one metal layer. 1. A semiconductor device comprising:a semiconductor substrate;a first transistor and a second transistor formed on the semiconductor substrate, wherein each transistor comprises a source, a drain, and a gate, wherein the gate of the first transistor extends longitudinally as part of a first linear strip and wherein the gate of the second transistor ...

REWIRING METHOD FOR SEMICONDUCTOR

A method for rewiring of semiconductor devices is provided, in which deviations of electrical connection terminals () on a carrier () are calculated and corrected by forming rewiring structures on the electrical connection terminals by mask-free photolithography. A wiring layer and/or solder balls () is/are then formed on the rewiring structures by processing the carrier () in a monolithic manner using mask-based photolithography. In this way, the combined use of mask-free photolithography and mask-based photolithography allows for higher efficiency and a shorter process cycle, compared to only using mask-free photolithography. 1. A method for rewiring of semiconductor devices , comprising the steps of:1) arranging a carrier for bearing a plurality of semiconductor devices, each of the semiconductor devices having a plurality of electrical connection terminals;2) measuring positions of the plurality of electrical connection terminals relative to the carrier, and obtaining deviations of the plurality of electrical connection terminals by comparing the measured positions with standard positions of the plurality of electrical connection terminals relative to the carrier;3) correcting the deviations by forming rewiring structures on the plurality of electrical connection terminals by performing a mask-free photolithography process based on the obtained deviations; and4) forming a wiring layer and/or solder balls on the rewiring structures by processing the carrier in a monolithic manner by performing a mask-based photolithography process.2. The method for rewiring of semiconductor devices of claim 1 , wherein step 3) comprises:depositing a first dielectric layer;coating a first photoresist layer on the first dielectric layer;forming a plurality of first-photoresist patterns in the first photoresist layer by performing the mask-free photolithography process based on the deviations obtained from step 2), wherein each of the plurality of first-photoresist patterns is ...

Method of Forming Contact Metal

A semiconductor device is disclosed. The device includes a source/drain feature formed over a substrate. A dielectric layer formed over the source/drain feature. A contact trench formed through the dielectric layer to expose the source/drain feature. A titanium nitride (TiN) layer deposited in the contact trench and a cobalt layer deposited over the TiN layer in the contact trench. 1. A device comprising:a source/drain feature disposed on a substrate;a silicide layer disposed on the source/drain feature;a dielectric layer disposed over the substrate;a titanium nitride (TiN) layer extending along a sidewall of the dielectric layer to a top surface of the silicide layer, wherein a comparison of a thickness of the TiN layer over the top surface of the silicide layer versus a thickness of the TiN layer along the sidewall of the dielectric layer is greater than 90%; anda conductive layer extending along the TiN layer.2. The device of claim 1 , further comprising a gate structure disposed on the substrate claim 1 , andwherein the TiN layer physically contacts the gate structure.3. The device of claim 2 , wherein the dielectric layer extends over a top surface of the gate structure.4. The device of claim 2 , wherein the gate structure includes a dielectric sidewall spacer claim 2 , andwherein the TiN layer physically contacts the dielectric sidewall spacer.5. The device of claim 1 , wherein the TiN layer has a u-shaped profile.6. The device of claim 1 , wherein the TiN layer includes a first sidewall portion and opposing second sidewall portion claim 1 , andwherein the conductive layer extends from the first sidewall portion to the second sidewall portion.7. The device of claim 1 , wherein the conductive layer has a first width adjacent the silicide layer and a second width disposed over the first width adjacent the silicide layer claim 1 , the second width different than the first width.8. A device comprising:a source/drain feature disposed on a substrate;a silicide layer ...

Interconnection Structure, Fabricating Method Thereof, and Semiconductor Device Using the Same

A semiconductor device includes a semiconductor substrate comprising a contact region, a silicide present on the contact region, a dielectric layer present on the semiconductor substrate, the dielectric layer comprising an opening to expose a portion of the contact region, a conductor present in the opening, a barrier layer present between the conductor and the dielectric layer, and a metal layer present between the barrier layer and the dielectric layer, wherein a Si concentration of the silicide is varied along a height of the silicide. 1. A device comprising:a multi-gate transistor, the multi-gate transistor including a source/drain region;a dielectric layer overlying the source/drain region;a filled contact opening extending through the dielectric layer, the filled contact opening defined by sidewalls of the dielectric layer;a metal liner extending along and contacting the sidewalls of the dielectric layer;a barrier layer extending along and contacting the metal liner, the metal liner being interjacent the barrier layer and the sidewalls of the dielectric layer;a silicide of the source/drain region and the metal liner at a bottom of the filled contact opening; anda conductor within the filled contact opening, the barrier layer extending between the conductor and the silicide.2. The device of claim 1 , wherein the multi-gate transistor is at least partially in a substrate claim 1 , and further comprising two p-well regions in the substrate and an n-well region in the substrate claim 1 , the n-well region being interjacent the two p-well regions.3. The device of claim 2 , wherein the multi-gate transistor is an n-type FinFET having a first fin extending from the n-well region.4. The device of claim 3 , further comprising:a p-type FinFET having a second fin extending from one of the two p-well regions and including a second source/drain region; anda continuous gate electrode extending over the first fin and the second fin.5. The device of wherein the source/drain ...

ROM Chip Manufacturing Structures

An integrated circuit (IC) chip embodiment includes first and second ROM cells arranged in a same row of a ROM array. The first and second ROM cells include first portions of first and second gate structures, respectively. The IC chip further includes a strap cell disposed between the first and second ROM cells. The strap cell includes second portions of the first and second gate structures. The first gate structure is physically separated from the second gate structure. 110.-. (canceled)11. An integrated circuit (IC) chip comprising: a plurality of physically separated gate structures, wherein lengths of the plurality of gate structures are substantially uniform; and', 'a plurality of first connection modules electrically connecting each of the plurality of physically separated gate structures to a common word line., 'a read-only-memory (ROM) array comprising a plurality of rows of ROM cells, wherein each of the plurality of rows of ROM cells comprises12. The IC chip of claim 11 , wherein the each of the plurality of physically separated gate structures span four claim 11 , eight claim 11 , sixteen claim 11 , thirty-two claim 11 , or sixty-four ROM cells.13. The IC chip of claim 11 , wherein the plurality of first connection modules are disposed over continuous areas the plurality of gate structures.14. The IC chip of claim 11 , wherein the plurality of first connection modules are disposed over separated areas of the plurality of gate structures.15. The IC chip of claim 11 , wherein the ROM array further comprises a plurality of isolation devices disposed between the plurality of rows claim 11 , and wherein gates of the plurality of isolation devices are electrically connected to ground potential.16. The IC chip of claim 15 , wherein the ROM array further comprises a second connection module electrically connecting the gates of the plurality of isolation devices to a common ground line.17. The IC chip of claim 15 , wherein gates of a first row of isolation devices ...

DUAL METAL NITRIDE LANDING PAD FOR MRAM DEVICES

A dual nitride landing pad for a high performance magnetoresistive random access memory (MRAM) device is formed on a recessed surface of the least one electrically conductive structure in a MRAM device area. The dual nitride landing pad includes a bottom metal nitride landing pad and a TaN-containing landing pad. 1. A method of forming a semiconductor structure , the method comprising:providing at least one electrically conductive structure embedded in a dielectric material layer and located in a MRAM device area, and at least one other electrically conductive structure embedded in the dielectric material layer and located in a non-MRAM device area;recessing the at least one electrically conductive structure in the MRAM device area,. wherein a block mask is formed over the non-MRAM device area prior to the recessing of the at least one electrically conductive structure in the MRAM device area;removing the block mask that is formed over the non-MRAM device area;forming, after the removing of the block mask, a dual nitride landing pad on a recessed surface of the least one electrically conductive structure in the MRAM device area, the dual nitride landing pad comprising a bottom metal nitride landing pad and a TaN-containing landing pad;forming a dielectric capping layer on the dielectric material layer, the dielectric capping layer having a topmost surface that is coplanar with a topmost surface of the TaN-containing landing pad;forming a magnetic tunnel junction (MTJ) structure on the TaN-containing landing pad;forming an interlayer dielectric (ILD) material layer laterally adjacent the MTJ structure and having a topmost surface that is coplanar with a topmost surface of the MTJ structure; andforming at least an electrically conductive metal or metal alloy layer on the MTJ structure and the ILD material layer.2. (canceled)3. The method of claim 1 , wherein the forming of the dual nitride landing pad comprises:forming, by a directional deposition process, a bottom ...

FORMATION OF WRAP-AROUND-CONTACT TO REDUCE CONTACT RESISTIVITY

A method of forming a source/drain contact is provided. The method includes forming a sacrificial layer on a source/drain, and depositing an oxidation layer on the sacrificial layer. The method further includes heat treating the oxidation layer and the sacrificial layer to form a modified sacrificial layer. The method further includes forming a protective liner on the modified sacrificial layer, and depositing an interlayer dielectric layer on the protective liner. The method further includes forming a trench in the interlayer dielectric layer that exposes a portion of the protective liner. 1. A method of forming a source/drain contact , comprising:forming a sacrificial layer on a source/drain;depositing an oxidation layer on the sacrificial layer;heat treating the oxidation layer and the sacrificial layer to form a modified sacrificial layer;forming a protective liner on the modified sacrificial layer;depositing an interlayer dielectric layer on the protective liner;forming a trench in the interlayer dielectric layer that exposes a portion of the protective liner;depositing a protective liner extension on the exposed sidewalls of the trench; andremoving the modified sacrificial layer to form a channel.2. (canceled)3. The method of claim 1 , further comprising forming a source/drain contact in the channel.4. The method of claim 3 , wherein the heat treatment is conducted at a temperature in a range of about 400° C. to about 700° C. in a 100% nitrogen (N) atmosphere.5. The method of claim 3 , wherein the modified sacrificial layer is silicon dioxide (SiO).6. The method of claim 3 , wherein the sacrificial layer is silicon-germanium (SiGe) claim 3 , and the oxidation layer is germanium dioxide (GeO).7. The method of claim 6 , wherein the source/drain is silicon germanium (SiGe) claim 6 , and the sacrificial layer is formed by epitaxial growth on the exposed surface of the source/drain.8. The method of claim 7 , wherein the source/drain has a germanium concentration in ...

VERTICAL ETCH HETEROLITHIC INTEGRATED CIRCUIT DEVICES

Vertical etch heterolithic integrated circuit devices are described. A method of manufacturing NIP diodes is described in one example. A P-type substrate is provided, and an intrinsic layer is formed on the P-type substrate. An oxide layer is formed on the intrinsic layer, and one or more openings are formed in the oxide layer. One or more N-type regions are implanted in the intrinsic layer through the openings in the oxide layer. The N-type regions form cathodes of the NIP diodes. A dielectric layer deposited over the oxide layer is selectively etched away with the oxide layer to expose certain ranges of the intrinsic layer to define a geometry of the NIP diodes. The intrinsic layer and the P-type substrate are vertically etched away within the ranges to expose sidewalls of the intrinsic layer and the P-type substrate. The P-type substrate forms the anodes of the NIP diodes. 1. A method of manufacturing a device , comprising:providing a P-type silicon substrate;forming an intrinsic layer on the P-type silicon substrate;growing an oxide layer on the intrinsic layer;forming at least one opening in the oxide layer;implanting an N-type region in the intrinsic layer through the at least one opening in the oxide layer;depositing a dielectric layer over the oxide layer and the N-type region;selectively etching the dielectric layer and the oxide layer away expose the intrinsic layer within at least one range to define a geometry of the device; andvertically etching the intrinsic layer and the P-type silicon substrate away within the at least one range to expose sidewalls of the intrinsic layer and the P-type silicon substrate.2. The method according to claim 1 , further comprising forming conductive regions on the sidewalls of the intrinsic layer and the P-type silicon substrate by diffusion of a P-type acceptor into the sidewalls.3. The method according to claim 1 , further comprising encapsulating the device in an insulative material.4. The method according to claim 3 , ...

METHOD OF FORMING A PATTERN IN A SEMICONDUCTOR DEVICE AND METHOD OF FORMING A GATE USING THE SAME

A method of forming a pattern in a semiconductor device is described. A substrate divided into cell and peripheral regions is provided, and an object layer is formed on a substrate. A buffer pattern is formed on the object layer in the cell region along a first direction. A spacer is formed along a sidewall of the buffer pattern in the cell region, and a hard mask layer remains on the object layer in the peripheral region. The buffer layer is removed, and the spacer is separated along a second direction different from the first direction, thereby forming a cell hard mask pattern. A peripheral hard mask pattern is formed in the peripheral region. A minute pattern is formed using the cell and peripheral hard mask patterns in the substrate. Therefore, a line width variation or an edge line roughness due to the photolithography process is minimized. 1. A method of manufacturing a semiconductor device , comprising:forming an object layer on a substrate;forming a first pattern on the object layer in a first region of the substrate, the first pattern having a plurality of spacers that are spaced apart from and parallel with each other;forming a second pattern on the object layer in a second region of the substrate; andpatterning the object layer on the substrate using the first and second patterns as a mask, respectively.2. The method of claim 1 , wherein the object layer includes a conductive layer claim 1 , so that first and second conductive patterns are formed on the substrate corresponding to the first and second patterns claim 1 , respectively.3. The method of claim 1 , wherein forming the first pattern includes:forming a buffer pattern on the object layer;forming the spacers on sidewalls of the buffer pattern; andremoving the buffer pattern from the object layer of the substrate, so that the spacers remain on the object layer and spaced apart from each other.4. The method of claim 3 , wherein forming the buffer pattern includes:forming a buffer layer on the object ...

INTERCONNECT STRUCTURE INCLUDING MIDDLE OF LINE (MOL) METAL LAYER LOCAL INTERCONNECT ON ETCH STOP LAYER

An interconnect structure includes an insulator stack on an upper surface of a semiconductor substrate. The insulator stack includes a first insulator layer having at least one semiconductor device embedded therein and an etch stop layer interposed between the first insulator layer and a second insulator layer. At least one electrically conductive local contact extends through each of the second insulator layer, etch stop layer and, first insulator layer to contact the at least one semiconductor device. The interconnect structure further includes at least one first layer contact element disposed on the etch stop layer and against the at least one conductive local contact. 1. An interconnect structure , comprising:an insulator stack on an upper surface of a semiconductor substrate, the insulator stack including a first insulator layer having at least one semiconductor device embedded therein and an etch stop layer interposed between the first insulator layer and a second insulator layer;at least one electrically conductive local contact extending through the second insulator layer, the etch stop layer and the first insulator layer to contact the at least one semiconductor device; andat least one first layer contact element on the etch stop layer and against the at least one conductive local contact.2. The interconnect structure of claim 1 , wherein the second insulator layer contains the first layer contact element and a portion of the at least one conductive local contact.3. The interconnect structure of claim 2 , wherein the at least one first layer contact element abuts a sidewall of the at least one conductive local contact.4. The interconnect structure of claim 3 , wherein an upper surface of the at least one first layer contact element is flush with an upper surface of the at least one conductive local contact.5. The interconnect structure of claim 4 , wherein the second insulator layer contains embedded therein the upper portion of the at least one conductive ...

Dipole-Based Contact Structure to Reduce Metal-Semiconductor Contact Resistance in MOSFETs

A transistor device includes a substrate; a source region and a drain region formed over the substrate; and a source/drain contact formed in contact with at least one of the source region and the drain region, the source/drain contact including a conductive metal and a bilayer disposed between the conductive metal and the at least one of the source and drain region, the bilayer including a metal oxide layer in contact with the conductive metal, and a silicon dioxide layer in contact with the at least one of the source and drain region.

Semiconductor device having structure for improving voltage drop and device including the same

A semiconductor device includes a semiconductor substrate and a plurality of metal layers above the semiconductor substrate. A first of the metal layers includes a plurality of first power rails which extend in a first direction and provide a first voltage, a plurality of second power rails which extend in the first direction and provide a second voltage, and a first conductor which is integral with one end of each of the first power rails and extends in a second direction. The first direction is perpendicular to the second direction. The first voltage is one of a ground voltage and a power source voltage and the second voltage is the other voltage.

Composite Hard Mask Etching Profile for Preventing Pattern Collapse in High-Aspect-Ratio Trenches

High-aspect ratio trenches in integrated circuits are fabricated of composite materials and with trench boundaries having pencil-like etching profiles. The fabrication methods reduce surface tension between trench boundaries and fluids applied during manufacture, thereby avoiding pattern bending, bowing, and collapse. The method, further, facilitates fill-in of trenches with suitable selected materials.

Spacers for Semiconductor Devices Including a Backside Power Rails

Semiconductor devices including air spacers formed in a backside interconnect structure and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure; and a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including a first dielectric layer on the backside of the first transistor structure; a first via extending through the first dielectric layer, the first via being electrically coupled to a first source/drain region of the first transistor structure; a first conductive line electrically coupled to the first via; and an air spacer adjacent the first conductive line, the first conductive line defining a first side boundary of the air spacer.

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, METHOD FOR PACKAGING SEMICONDUCTOR CHIP, METHOD FOR MANUFACTURING SHALLOW TRENCH ISOLATION (STI)

A method for manufacturing a semiconductor device includes forming a source region, a drain region, and a gate dielectric layer and a gate electrode covering a channel region between the source region and the drain region, forming an insulating layer over the source region, the drain region, and the gate electrode, forming first to third vias penetrating the insulating layer and exposing portions of the source region, the drain region, and the gate electrode, respectively, forming a source contact in the first via to electrically connect to the source region, forming a drain contact in the second via to electrically connect to the drain region, and forming a gate contact in the third via to electrically connect to the gate electrode. One or more of the first to third vias is formed by ion bombarding by a focused ion beam and followed by a thermal annealing process. 1. A method for manufacturing a semiconductor device , the method comprising:forming a source region, a drain region, and a gate dielectric layer and a gate electrode covering a channel region between the source region and the drain region;forming an insulating layer over the source region, the drain region, and the gate electrode; andforming first, second, and third vias penetrating the insulating layer and exposing portions of the source region, the drain region, and the gate electrode, respectively, ion bombarding the insulating layer using a focused ion beam at two or more connected sections at two or more different depths in the insulating layer, wherein at least a section of the two or more connected sections laterally extends further than other two or more connected sections, and', 'performing the thermal annealing after each ion bombarding of a section of the two or more connected sections to convert the section to a void, thereby the two or more connected sections are converted to two or more connected voids, wherein the ion bombarding comprises a first ion bombarding and a second ion bombarding, ...

SEMICONDUCTOR DEVICES

A semiconductor device includes circuit elements on a first substrate; gate electrodes on a second substrate and stacked to be apart from each other in a first direction; sacrificial insulating layers on a lower through-insulating layer penetrating the second substrate, stacked to be spaced apart from each other in the first direction, and having side surfaces opposing the gate electrodes; channel structures penetrating the gate electrodes, extending vertically on the second substrate, and including a channel layer; a first separation pattern penetrating the gate electrodes and including a first barrier pattern and a first pattern portion extending from the first barrier pattern in a second direction; and a second separation pattern penetrating the gate electrodes, disposed to be parallel to the first separation pattern, and extending in the second direction. Some of the side surfaces of the sacrificial insulating layers may overlap the first barrier pattern in a third direction. 1. A semiconductor device , comprising:a peripheral circuit region on a first substrate and including circuit elements; gate electrodes stacked to be spaced apart from each other in a first direction, perpendicular to an upper surface of the second substrate, on a first region of the second substrate and extending while having a staircase shape in a second direction, perpendicular to the first direction, on a second region of the second substrate, and', 'interlayer insulating layers stacked alternately with the gate electrodes;, 'a stack structure provided on a second substrate disposed on the peripheral circuit region and includinga channel structure penetrating through the stack structure, extending vertically on the second substrate, and including a channel layer;a separation structure penetrating through the stack structure and extending in a second direction, and including a first separation pattern and a pair of second separation patterns disposed to be parallel to the first ...

Device, a Method Used in Forming a Circuit Structure, a Method Used in Forming an Array of Elevationally-Extending Transistors and a Circuit Structure Adjacent Thereto

A device comprises an array of elevationally-extending transistors and a circuit structure adjacent and electrically coupled to the elevationally-extending transistors of the array. The circuit structure comprises a stair step structure comprising vertically-alternating tiers comprising conductive steps that are at least partially elevationally separated from one another by insulative material. Operative conductive vias individually extend elevationally through one of the conductive steps at least to a bottom of the vertically-alternating tiers and individually electrically couple to an electronic component below the vertically-alternating tiers. Dummy structures individually extend elevationally through one of the conductive steps at least to the bottom of the vertically-alternating tiers. Methods are also disclosed. 1. A device comprising:an array of elevationally-extending transistors; and a stair step structure comprising vertically-alternating tiers comprising conductive steps that are at least partially elevationally separated from one another by insulative material;', 'operative conductive vias individually extending elevationally through one of the conductive steps at least to a bottom of the vertically-alternating tiers and which individually electrically couple to an electronic component below the vertically-alternating tiers; and', 'dummy structures individually extending elevationally through one of the conductive steps at least to the bottom of the vertically-alternating tiers., 'a circuit structure adjacent and electrically coupled to the elevationally-extending transistors of the array, the circuit structure comprising2. The device of wherein the dummy structures are individually conductive top-to-bottom through the vertically-alternating tiers.3. The device of wherein the operative conductive vias and the dummy structures are individually of the same peripheral size and peripheral shape.4. The device of wherein the operative conductive vias and the ...

Gate capping structures in semiconductor devices

A semiconductor device and methods of fabricating the same are disclosed. The semiconductor device includes a substrate, a fin structure disposed on the substrate, a source/drain (S/D) region disposed on the fin structure, and a gate structure disposed on the fin structure adjacent to the S/D region. The gate structure includes a gate stack disposed on the fin structure and a gate capping structure disposed on the gate stack. The gate capping structure includes a conductive gate cap disposed on the gate stack and an insulating gate cap disposed on the conductive gate cap. The semiconductor device further includes a first contact structure disposed over the gate stack. A portion of the first contact structure is disposed within the gate capping structure and is separated from the gate stack by a portion of the conductive gate cap.

SEMICONDUCTOR DEVICE AND METHOD FOR MONOLITHICALLY INTEGRATED POWER DEVICE AND CONTROL LOGIC

A monolithic semiconductor device has a substrate with a power region and control region. The substrate can be a silicon-on-insulator substrate. An opening is formed in the power region and extends partially through the substrate. A semiconductor material is formed within the opening. A power semiconductor device, such as a vertical power transistor, is formed within the semiconductor material. A control logic circuit is formed in the control region. A first isolation trench is formed in the power region to isolate the power semiconductor device and control logic circuit. A second isolation trench is formed in the control region to isolate a first control logic circuit from a second control logic circuit. An interconnect structure is formed over the power region and control region to provide electrical interconnect between the control logic circuit and power semiconductor device. A termination trench is formed in the power region. 1. A method of making a monolithic semiconductor device , comprising:providing a substrate;forming an opening extending partially through the substrate;forming a semiconductor material within the opening;forming a power semiconductor device within the semiconductor material;forming a control logic circuit in a portion of the substrate outside the opening to control the power semiconductor device; andforming a first isolation trench in the semiconductor material to isolate the power semiconductor device and control logic circuit.2. The method of claim 1 , wherein the power semiconductor device includes a vertical power semiconductor device.3. The method of claim 1 , further including forming a second isolation trench in the portion of the substrate outside the opening to isolate a first control logic circuit from a second control logic circuit.4. The method of claim 1 , further including forming an interconnect structure over the power semiconductor device and control logic circuit.5. The method of claim 1 , wherein the substrate includes a ...

Fin field effect transistor

A substrate is patterned to form trenches and a semiconductor fin between the trenches. Insulators are formed in the trenches and a dielectric layer is formed to cover the semiconductor fin and the insulators. A dummy gate strip is formed on the dielectric layer. Spacers are formed on sidewalls of the dummy gate strip. The dummy gate strip and the dielectric layer underneath are removed until sidewalls of the spacers, a portion of the semiconductor fin and portions of the insulators are exposed. A second dielectric layer is selectively formed to cover the exposed portion of the semiconductor fin, wherein a thickness of the dielectric layer is smaller than a thickness of the second dielectric layer. A gate is formed between the spacers to cover the second dielectric layer, the sidewalls of the spacers and the exposed portions of the insulators.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

A semiconductor device has a plurality of first opening portions formed in an interlayer insulating film. The surface is covered with a metal film with a surface having concavities and convexities which scatter reflected light. Size of the first opening portion is of the same level as a contact hole of a component and cannot be recognized by an image recognition apparatus. The metal film can be recognized by the image recognition apparatus. By forming a TiN film serving as a reflection prevention film on an end of the metal film, portions that can easily scatter light and a portion that cannot easily reflect light are adjacent in an alignment marker. A passivation film is formed on the interlayer insulating film and the TiN film. Recessed portions disposed in the metal film are exposed to a second opening portion formed in the passivation film and the TiN film. 1. A semiconductor device in which an alignment marker is disposed on a semiconductor substrate , wherein the alignment marker includes:a wiring layer that is disposed on a surface of the semiconductor substrate;an interlayer insulating film that is disposed on the surface of the semiconductor substrate so as to cover the wiring layer;a plurality of first opening portions that are disposed in the interlayer insulating film to a depth which reaches the wiring layer;a first metal film for position detection that is disposed on a surface of the interlayer insulating film along an inner wall of the first opening portions so as to be brought into contact with the wiring layer, which has a shape in which concavities and convexities are continuously formed;a second metal film that is disposed on a surface of the first metal film such that recessed portions of the concavities and convexities of the first metal film are exposed, which is formed of a material which prevents reflection of incident light; anda passivation film that is disposed on the surfaces of the interlayer insulating film and the second metal film, ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device including a Fin FET device includes a fin structure protruding from a substrate layer and having a length extending in a first direction. A channel layer is formed on the fin structure. A gate stack including a gate electrode layer and a gate dielectric layer extending in a second direction perpendicular to the first direction is formed over the channel layer covering a portion of the length of the fin structure. The source and drain contacts are formed over trenches that extend into a portion of a height of the fin structure. 1. A method for manufacturing a semiconductor device , comprising:forming a spacer layer over a dummy gate, formed over a first portion of a fin structure, and a second portion of the fin structure;forming a dielectric layer over the spacer layer;removing the dielectric layer and the spacer layer formed over the dummy gate and the dummy gate to expose the first portion of the fin structure;forming a gate stack over the exposed first portion of the fin structure;forming trenches by removing the dielectric layer formed over a remaining portion of the spacer layer and a portion of a height of the fin structure underneath the dielectric layer; andforming source and drain contacts by filling the trenches with a metal.2. The method of claim 1 , further comprising forming the fin structure and the dummy gate prior to forming the spacer layer claim 1 , wherein forming the fin structure comprises forming a 2D channel comprising a 2D material over a fin that is formed on a substrate claim 1 , wherein the 2D material comprises a 2D semiconductor claim 1 , and wherein the 2D semiconductor comprises black phosphorous claim 1 , graphene claim 1 , or a transition metal dichalcogenide (TMD) including molybdenum disulfide (MoS).3. The method of claim 2 , wherein forming the 2D channel comprises a selective deposition using one of a chemical-vapor deposition (CVD) method or an atomic-layer deposition (ALD) method claim 2 , and wherein a ...

Disposable laser/flash anneal absorber for embedded neuromorphic memory device fabrication

A conformal disposable absorber is disclosed which is capable of providing efficient heat transfer to an embedded memory device during a localized absorber anneal, without adversary impacting the back-end-of-the-line (BEOL) structure. The disposable absorber is composed of an amorphous carbonitride material that can be designed to have a low reflection coefficient for laser/flash illumination, and a high extinction coefficient for efficient laser/flash illumination absorption. The disposable absorber is formed at a temperature of 400° C. or less.

INCREASED ISOLATION OF DIFFUSION BREAKS IN FINFET DEVICES USING AN ANGLED ETCH

Methods for forming semiconductor devices herein may include forming a trench in a substrate layer, wherein a hardmask is disposed atop the substrate layer, and implanting the trench at an angle relative to a top surface of the hardmask. The method may further include forming an oxide layer within the trench, wherein a thickness of the oxide layer along a bottom portion of the trench is greater than a thickness of the oxide layer along an upper portion of the trench. 1. A method of forming a semiconductor device , comprising:patterning a set of features atop a substrate; andforming a diffusion break trench in the substrate using angled ions impacting the substrate at a non-zero angle of inclination with respect to a perpendicular to a plane of the substrate, wherein the diffusion break trench has a first width at a bottom of the diffusion break trench and a second width at a top of the diffusion break trench, and wherein the first width is greater than the second width.2. The method of claim 1 , further comprising:forming an etch stop layer over the substrate;forming a dummy gate material over the etch stop layer;forming a hardmask layer over the dummy gate material;patterning the set of features atop the substrate to form a set of active gates and a dummy gate from the dummy gate material and the silicon nitride layer; andforming a gate spacer along the set of active gates and the dummy gate.3. The method of claim 2 , further comprising:forming a source/drain (S/D) epitaxial layer over the substrate;forming a silicon oxide layer over the S/D epitaxial layer; andpatterning an opening in a mask, the opening positioned over the dummy gate.4. The method of claim 2 , further comprising:opening the dummy gate by removing, from the dummy gate, the following: the etch stop layer, the dummy gate material, and the silicon nitride layer; andperforming the angled etch after the dummy gate is opened.5. The method of claim 2 , further comprising:forming a barrier layer within ...

Contact Conductive Feature Formation and Structure

Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back by a wet etching process. After etching back the portion of the barrier layer, an underlying dielectric welding layer is exposed. A conductive material is formed along the barrier layer.

Semiconductor device and manufacturing method

To provide a semiconductor device that has barrier metal and has a small variation in a threshold voltage. A semiconductor device is provided, including a semiconductor substrate, an interlayer dielectric film arranged on an upper surface of the semiconductor substrate, a titanium layer provided on the interlayer dielectric film, and a titanium nitride layer provided on the titanium layer, where the interlayer dielectric film is provided with an opening that exposes a part of the upper surface of the semiconductor substrate, the titanium layer and the titanium nitride layer are also provided within the opening, and the titanium layer arranged in contact with the semiconductor substrate and on a bottom portion of the opening is entirely titanium-silicided.

FORMATION METHOD OF SEMICONDUCTOR DEVICE STRUCTURE WITH METAL-SEMICONDUCTOR COMPOUND REGION

A method for forming a semiconductor device structure is provided. The method includes forming a fin structure over a semiconductor substrate and forming a gate stack over the fin structure. The method also includes forming an epitaxial structure over the fin structure, and the epitaxial structure is adjacent to the gate stack. The method further includes forming a dielectric layer over the epitaxial structure and forming an opening in the dielectric layer to expose the epitaxial structure. In addition, the method includes applying a metal-containing material on the epitaxial structure while the epitaxial structure is heated so that a portion of the epitaxial structure is transformed to form a metal-semiconductor compound region. 1. A method for forming a semiconductor device structure , comprising:forming a fin structure over a semiconductor substrate;forming a gate stack over the fin structure;forming an epitaxial structure over the fin structure, wherein the epitaxial structure is adjacent to the gate stack;forming a dielectric layer over the epitaxial structure;forming an opening in the dielectric layer to expose the epitaxial structure; andapplying a metal-containing material on the epitaxial structure while the epitaxial structure is heated so that a portion of the epitaxial structure is transformed to form a metal-semiconductor compound region.2. The method for forming a semiconductor device structure as claimed in claim 1 , wherein the metal-containing material is applied using a chemical vapor deposition process.3. The method for forming a semiconductor device structure as claimed in claim 1 , wherein the metal-containing material is applied using an atomic layer deposition process.4. The method for forming a semiconductor device structure as claimed in claim 1 , further comprising forming a modified region in the epitaxial structure before the metal-containing material is applied on the epitaxial structure claim 1 , wherein the modified region has lower ...

Semiconductor device with contact structures

A structure and a formation method of a semiconductor device are provided. The semiconductor device structure includes a first epitaxial structure and a second epitaxial structure over a semiconductor substrate. The semiconductor device structure also includes a first conductive via electrically connected to the first epitaxial structure through a conductive contact. The first conductive via is misaligned with the first epitaxial structure. The semiconductor device structure further includes a second conductive via electrically connected to the second epitaxial structure. The second conductive via is aligned with the second epitaxial structure.

3D VERTICAL FET WITH TOP AND BOTTOM GATE CONTACTS

A method for forming a semiconductor device includes flipping a vertical transistor including a bottom side having at least one connection to at least one bottom side metallization structure, and, after flipping the vertical transistor, forming at least one top side metallization structure having at least one connection to a top side of the vertical transistor. 1. A method for forming a semiconductor device , comprising:flipping a vertical transistor including a bottom side having at least one connection to at least one bottom side metallization structure; andafter flipping the vertical transistor, forming at least one top side metallization structure having at least one connection to a top side of the vertical transistor.2. The method as recited in claim 1 , further comprising removing a substrate prior to forming the at least one top side metallization structure.3. The method of claim 1 , further comprising forming a gate structure disposed about a channel region of the vertical transistor claim 1 , wherein the gate structure is contacted on the top side and the bottom side by gate contacts.4. The method as recited in claim 3 , further comprising forming gate contacts to the gate structure on the top side and the bottom side.5. The method of claim 4 , wherein the gate contacts are formed on opposite sides of a same gate structure on the top side and the bottom side.6. The method as recited in claim 1 , wherein the vertical transistor is contacted on the top side and the bottom side.7. The method as recited in claim 1 , wherein the top side includes front end of the line (FEOL) structures and the bottom side includes back end of the line (BEOL) structures.8. The method as recited in claim 1 , wherein the top side metallization structures have at least one connection to the vertical transistor on the top side.9. The method as recited in claim 1 , wherein the vertical transistor is a part of a logic device and the logic device connects to the bottom side and the top ...

Semiconductor product with interlocking metal-to-metal bonds and method for manufacturing thereof

A structure and method for performing metal-to-metal bonding in an electrical device. For example and without limitation, various aspects of this disclosure provide a structure and method that utilize an interlocking structure configured to enhance metal-to-metal bonding.

Semiconductor device and method of manufacturing the same

The semiconductor device includes: a first channel pattern including a first horizontal part, vertical parts extending from the first horizontal part, a connection part extending from the first horizontal part in a direction opposite to the vertical parts, and a second horizontal part extending from the connection part in a direction parallel to the first horizontal part; a first gate stack enclosing the vertical parts of the first channel pattern and disposed over the first horizontal part; a well structure disposed under the second horizontal part, and including a first conductivity type impurity; and a first well contact line directly contacting with the second horizontal part and the well structure to couple the second horizontal part of the first channel pattern with the well structure.

SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME

According to some embodiments, a semiconductor device may include gate structures on a substrate; first and second impurity regions formed in the substrate and at both sides of each of the gate structures; conductive line structures provided to cross the gate structures and connected to the first impurity regions; and contact plugs connected to the second impurity regions, respectively. For each of the conductive line structures, the semiconductor device may include a first air spacer provided on a sidewall of the conductive line structure; a first material spacer provided between the conductive line structure and the first air spacer; and an insulating pattern provided on the air spacer. The insulating pattern may include a first portion and a second portion, and the second portion may have a depth greater than that of the first portion and defines a top surface of the air spacer. 1. A semiconductor device , comprising:a gate structure on a substrate;first and second impurity regions formed in the substrate and at opposite sides of the gate structure, respectively;a conductive line structure provided to cross over the gate structure and connected to the first impurity region, the conductive line structure having a left sidewall and a right sidewall opposite to each other;a left spacer structure on the left sidewall of the conductive line structure;a right spacer structure on the right sidewall of the conductive line structure;a barrier layer conformally covering the conductive line structure, the left spacer structure, and the right spacer structure; andan insulating pattern penetrating a portion of the barrier layer and a portion of the conductive line structure to be in contact with the left spacer structure,wherein the left spacer structure includes:a first left material spacer contacting a lower portion of the left sidewall of the conductive line structure and exposing an upper portion of the left sidewall of the conductive line structure;a second left material ...

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING A STRUCTURE PATTERN HAVING A PLURALITY OF TRENCHES

A method of manufacturing a semiconductor device includes forming a base layer on a substrate. A structure layer is Conned on the base layer. The structure layer includes at least one material layer. A structure pattern is formed on the base layer. The structure pattern includes a first trench extending in a first direction and a second trench having a cross portion extending in a second direction that is perpendicular to the first direction. The second trench is connected to the first trench. The structure pattern further includes a base pattern having a recess portion recessed downward from a surface of the base layer at the cross portion of the second trench. 1. A semiconductor device , comprising:a base pattern on the substrate, the base pattern including a penetration portion for penetrating the base pattern; anda structure pattern on the base pattern, the structure pattern including a first trench extending in a first direction, and a second trench having a cross portion connected to the first trench and extending in a second direction that is perpendicular to the first direction;wherein the penetration portion corresponds the cross portion that crosses the first trench and the second trench, andwherein a width of the penetration portion is the same as a width of the first trench and a width of the second trench.2. The semiconductor device of claim 1 , wherein the width of the penetration portion is the same as the width of the first trench in the second direction.3. The semiconductor device of claim 1 , wherein the width of the penetration portion is the same as the width of the second trench in the first direction.4. The semiconductor device of claim 1 , further comprising a wiring layer buried in the penetration portion claim 1 , the first trench and second trench.5. The semiconductor device of claim 1 , wherein the second trench is connected to the first trench to form a T-shape claim 1 , and the cross portion of the second trench corresponds to a point ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

An upper surface of a plug (PL) is formed so as to be higher than an upper surface of an interlayer insulating film (PIL) by forming the interlayer insulating film (PIL) on a semiconductor substrate (S), completing a CMP method for forming the plug (PL) inside the interlayer insulating film (PIL), and then, making the upper surface of the interlayer insulating film (PIL) to recede. In this manner, reliability of connection between the plug (PL) and a wiring (W) in a vertical direction can be ensured. Also, the wiring (W) can be formed so as not to be embedded inside the interlayer insulating film (PIL), or a formed amount by the embedding can be reduced. 1. A semiconductor device comprising:a semiconductor substrate;a first insulating film formed over a main surface of the semiconductor substrate;a second insulating film formed over the first insulating film;a third insulating film formed over the second insulating film;a first conductor formed in the first insulating film and the second insulating film; anda second conductor formed in the second insulating film and the third insulating film,wherein an upper surface of the first conductor is formed higher than an upper surface of the first insulating film which is in contact with the second insulating film,wherein a lowermost lower surface of the second conductor is formed in the second insulating film, andwherein a dielectric constant of the third insulating film is lower than a dielectric constant of the first insulating film, andwherein the first insulating film is extended along a majority of a length of the first conductor in a direction from the semiconductor substrate to the second conductor.2. The semiconductor device according to claim 1 , further comprising:a wiring trench formed in the second insulating film and the third insulating film,wherein a lowermost lower surface of the wiring trench is formed in the second insulating film, andwherein an other lower surface of the wiring trench is formed on the ...

METHOD FOR FORMING A SEMICONDUCTOR DEVICE

A method for fabricating a semiconductor device is provided. The method includes forming a metal catalyst layer on an etching area of the semiconductor substrate; performing a wet etch process to the semiconductor substrate to etch the etching area of the semiconductor substrate under the metal catalyst layer, thereby forming a trench in the semiconductor substrate; and removing the metal catalyst layer from the semiconductor substrate after performing the wet etch process. 1. A method for fabricating a semiconductor device , comprising:forming a patterned mask layer on a semiconductor substrate, wherein the patterned mask layer exposes an etching area of the semiconductor substrate;depositing a metal catalyst material on the etching area and the patterned mask layer;removing the patterned mask layer and a portion of the metal catalyst material on the patterned mask layer to form a metal catalyst layer on the etching area of the semiconductor substrate;performing a wet etch process to the semiconductor substrate to etch the etching area of the semiconductor substrate under the metal catalyst layer, thereby forming a trench in the semiconductor substrate; andremoving the metal catalyst layer from the semiconductor substrate after performing the wet etch process.2. The method of claim 1 , further comprising:forming an isolation feature in the trench after removing the metal catalyst layer from the semiconductor substrate.3. The method of claim 2 , wherein forming the isolation feature in the trench comprises:overfilling the trench with a dielectric material; andplanarizing the dielectric material to remove a portion of the dielectric material outside the trench.45-. (canceled)6. The method of claim 1 , wherein performing the wet etch process comprises immersing the semiconductor substrate in an etching solution.7. The method of claim 1 , further comprising:forming an interconnect layer on a first side of the semiconductor substrate prior to depositing the metal ...

METHOD OF MANUFACTURING PHOTOMASK SET FOR FORMING PATTERNS

A method of manufacturing a photomask set includes: preparing a mask layout, the mask layout including a plurality of first layout patterns apart from one another in a first region, wherein distances between center points of three first layout patterns adjacent to one another from among the plurality of first layout patterns respectively have different values; grouping pairs of first layout patterns, in which a distance between two first layout patterns adjacent to each other does not have a smallest value, and splitting the mask layout pattern into at least two mask layouts; and forming a photomask set including at least two photomasks each including a mask pattern corresponding to the first layout pattern included in each of the mask layout patterns split into at least two mask layouts. 1. A method of manufacturing a photomask set , the method comprising:preparing a mask layout, the mask layout including a plurality of first layout patterns spaced apart from one another in a first region, and distances between center points of three first layout patterns adjacent to one another from among the plurality of first layout patterns respectively have different values;grouping pairs of first layout patterns of the plurality of first layout patterns, such that a distance between two first layout patterns adjacent to each other does not have a smallest value, and splitting the mask layout into at least two mask layout patterns; andforming a photomask set including at least two photomasks, each photomask including a mask pattern corresponding to the first layout pattern included in each of the at least two mask layout patterns.2. The method as claimed in claim 1 , wherein preparing the mask layout includes rendering a triangle connecting the center points of the three first layout patterns adjacent to one another from the plurality of first layout patterns to be a scalene triangle.3. The method as claimed in claim 2 , wherein preparing the mask layout further includes ...