Verfahren zum Bonden von Substraten mit Verteilen eines Verbindungsmaterials durch annähern der Substrate

Improved metal to metal bonding for stacked (3D) integrated circuits

Verfahren zum Bonden von Substraten

Die vorliegende Erfindung betrifft ein Verfahren zum Bonden eines ersten Substrats (1) mit einem zweiten Substrat (2) mittels einer zwischen den Substraten (1, 2) angeordneten Verbindungsschicht (7) aus einem Verbindungsmaterial (3, 5) mit folgenden Schritten: Aufbringen des Verbindungsmaterials (3, 5) auf das erste Substrat (1) und/oder das zweite Substrat (2) in flüssiger Form, Aufbringen des Verbindungsmaterials (3, 5) durch Schleuderbelackung oder Sprühbelackung gleichmäßig über eine Substratoberfläche (lo) des ersten unteren Substrats (1), Verteilen des Verbindungsmaterials (3, 5) zwischen den Substraten (1, 2) durch Annähern der Substrate (1, 2), wobei das Verteilen selbsttätig mittels der Kapillarkraft des flüssigen Verbindungsmaterials (3, 5) erfolgt, wobei eines der beiden Substrate (1, 2) nach einer Kontaktierung des mindestens einen Tropfens mit dem ersten unteren Substrat (1) freigelassen wird, und dadurch Ausbilden der Form der Verbindungsschicht (7) mit einer Dicke t, wobei ...

Method for permanent bonding of wafers

This invention relates to a method for bonding of a first solid substrate (1) to a second solid substrate (2) which contains a first material with the following steps, especially the following sequence: formation or application of a function layer (5) which contains a second material to the second solid substrate (2), making contact of the first solid substrate (1) with the second solid substrate (2) on the function layer (5), pressing together the solid substrates (1, 2) for forming a permanent bond between the first and second solid substrate (1, 2), at least partially reinforced by solid diffusion and/or phase transformation of the first material with the second material, an increase of volume on the function layer being caused.

IMPROVED METAL TO METAL BONDING FOR STACKED (3D) INTEGRATED CIRCUITS

The present invention provides a stabilized fine textured metal microstructure that constitutes a durable activated surface 310 usable for bonding a 3D stacked chip. A fine-grain layer that resists self anneal enables metal to metal bonding at moderate time and temperature and wider process flexibility.

Verfahren zum Bonden von Substraten

Die vorliegende Erfindung betrifft ein Verfahren zum Bonden eines ersten Substrats (1) mit einem zweiten Substrat (2) mittels einer zwischen den Substraten (1, 2) angeordneten Verbindungsschicht (7) aus einem Verbindungsmaterial (3, 5) mit folgenden Schritten: Aufbringen des Verbindungsmaterials (3, 5) auf das erste Substrat (1) und/oder das zweite Substrat (2) in flüssiger Form, Aufbringen des Verbindungsmaterials (3, 5) durch Schleuderbelackung oder Sprühbelackung gleichmäßig über eine Substratoberfläche (1o) des ersten unteren Substrats (1), Verteilen des Verbindungsmaterials (3, 5) zwischen den Substraten (1, 2) durch Annähern der Substrate (1, 2), wobei das Verteilen selbsttätig mittels der Kapillarkraft des flüssigen Verbindungsmaterials (3, 5) erfolgt, wobei eines der beiden Substrate (1, 2) nach einer Kontaktierung des mindestens einen Tropfens mit dem ersten unteren Substrat (1) freigelassen wird, und dadurch Ausbilden der Form der Verbindungsschicht (7) mit einer Dicke t, wobei ...

Chip package and method for forming the same

A chip package including a first substrate having an upper surface, a lower surface and a sidewall is provided. A sensing region or device region and a conducting pad are adjacent to the upper surface. A through-hole penetrates the first substrate. A redistribution layer extends from the lower surface into the through-hole and is electrically connected to the conducting pad. The redistribution layer further laterally extends from the lower surface to protrude from the sidewall. A method for forming the chip package is also provided.

Sheet-molded chip-scale package

Embodiments include but are not limited to apparatuses and systems including a microelectronic device including a die having a first surface and a second surface opposite the first surface, a conductive pillar formed on the first surface of the die, and an encapsulant material encasing the die, including covering the first surface, the second surface, and at least a portion of a side surface of the conductive pillar. Methods for making the same also are described.

Package structure

SOLDERING A CONDUCTOR TO AN ALUMINUM METALLIZATION

A method of making a semiconductor including soldering a conductor to an aluminum metallization is disclosed. In one example, the method includes substituting an aluminum oxide layer on the aluminum metallization by a substitute metal oxide layer or a substitute metal alloy oxide layer. Then, substitute metal oxides in the substitute metal oxide layer or the substitute metal alloy oxide layer are at least partly reduced. The conductor is soldered to the aluminum metallization using a solder material.

SEMICONDUCTOR DIE HAVING FINE PITCH ELECTRICAL INTERCONNECTS

Improved metal to metal bonding for stacked (3D) integrated circuits

Improved metal to metal bonding for stacked (3D) integrated circuits

The present invention provides a stabilized fine textured metal microstructure that constitutes a durable activated surface 310 usable for bonding a 3D stacked chip. A fine-grain layer that resists self anneal enables metal to metal bonding at moderate time and temperature and wider process flexibility.

SEMICONDUCTOR DIE HAVING FINE PITCH ELECTRICAL INTERCONNECTS

A die has interconnect pads on an interconnect side near an interconnect edge and has at least a portion of the interconnect side covered by a conformal dielectric coating, in which an interconnect trace over the dielectric coating forms a high interface angle with the surface of the dielectric coating. Because the traces have a high interface angle, a tendency for the interconnect materials to "bleed" laterally is mitigated and contact or overlap of adjacent traces is avoided. The interconnect trace includes a curable electrically conductive interconnect material; that is, it includes a material that can be applied in a flowable form, and thereafter cured or allowed to cure to form the conductive traces. Also, a method includes, prior to forming the traces, subjecting the surface of the conformal dielectric coating with a CF4 plasma treatment.

Method of forming a three-dimensional bonded semiconductor structure having nitridized oxide regions

A first semiconductor structure including a first bonding oxide layer having a first metallic bonding structure embedded therein and a second semiconductor structure including a second bonding oxide layer having a second metallic bonding structure embedded therein are provided. A nitride surface treatment process is performed to provide a nitrided surface layer to each structure. Each nitrided surface layer includes nitridized oxide regions located in an upper portion of the bonding oxide layer and nitridized metallic regions located in an upper portion of the metallic bonding structures. The nitrogen within the nitridized metallic regions is then removed to restore the upper portion of the metallic bonding structures to its original composition. Bonding is performed to form a dielectric bonding interface between the nitridized oxide regions present in the first and second structures, and a metallic bonding interface between the first and second metallic bonding structures.

ELECTRONIC APPARATUS AND METHOD FOR MANUFACTURING ELECTRONIC APPARATUS

An electronic apparatus includes: a first substrate; an electrode over the first substrate; a first conductor having a porous structure above the first substrate, the first conductor covering an upper surface and a side surface of the electrode; and an insulator above the first substrate, the insulator covering an upper surface and a side surface of the first conductor, wherein the insulator has an opening that exposes the first conductor.

Method for permanent connection of two metal surfaces

PACKAGE-ON-PACKAGE (POP) STRUCTURE AND METHOD

Metal to metal bonding for stacked (3D) integrated circuits

The present invention provides a stabilized fine textured metal microstructure that constitutes a durable activated surface usable for bonding a 3D stacked chip. A fine-grain layer that resists self anneal enables metal to metal bonding at moderate time and temperature and wider process flexibility.

METHOD FOR PERMANENT CONNECTION OF TWO METAL SURFACES

A process for the production of a permanent, electrically conductive connection between a first metal surface of a first substrate and a second metal surface of a second substrate, wherein a permanent, electrically conductive connection is produced, at least primarily, by substitution diffusion between metal ions and/or metal atoms of the two metal surfaces.

PACKAGE-ON-PACKAGE (POP) STRUCTURE AND METHOD

Chip package and method for forming the same

SEMICONDUCTOR DIE HAVING FINE PITCH ELECTRICAL INTERCONNECTS

A die has interconnect pads on an interconnect side near an interconnect edge and has at least a portion of the interconnect side covered by a conformal dielectric coating, in which an interconnect trace over the dielectric coating forms a high interface angle with the surface of the dielectric coating. Because the traces have a high interface angle, a tendency for the interconnect materials to "bleed" laterally is mitigated and contact or overlap of adjacent traces is avoided. The interconnect trace includes a curable electrically conductive interconnect material; that is, it includes a material that can be applied in a flowable form, and thereafter cured or allowed to cure to form the conductive traces. Also, a method includes, prior to forming the traces, subjecting the surface of the conformal dielectric coating with a CF4 plasma treatment.

Package on-package (PoP) structure including stud bulbs

Embodiments concern Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures. According to an embodiment, a structure includes a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs.

Chip package and method of manufacturing the same

SEMICONDUCTOR DIE HAVING FINE PITCH ELECTRICAL INTERCONNECTS

Method for permanent connection of two metal surfaces

The invention relates to a process for the production of a permanent, electrically conductive connection between a first metal surface of a first substrate and a second metal surface of a second substrate with the following method steps, in particular the course of the method: Conditioning of the first and second metal surfaces in such a way that in a connection of the metal surfaces, in particular in a time period of a few minutes after the conditioning, a permanent, electrically conductive connection-produced at least primarily by substitution diffusion between in particular similar, preferably identical, metal ions and/or metal atoms of the two metal surfaces-can be produced, Orientation and connection of the first and second metal surfaces, whereby during the conditioning, orientation and connection, a process temperature of at most 300 DEG C, in particular at most 260 DEG C, preferably 230 DEG C, even more preferably 200 DEG C, especially preferably at most 180 DEG C, and ideally at ...

METHOD FOR PERMANENT CONNECTION OF TWO METAL SURFACES

Package on-Package (PoP) structure including stud bulbs and method

Embodiments concern Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures. According to an embodiment, a structure includes a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs.

SOLDERING A CONDUCTOR TO AN ALUMINUM METALLIZATION

A method of making a semiconductor including soldering a conductor to an aluminum metallization is disclosed. In one example, the method includes substituting an aluminum oxide layer on the aluminum metallization by a substitute metal oxide layer or a substitute metal alloy oxide layer. Then, substitute metal oxides in the substitute metal oxide layer or the substitute metal alloy oxide layer are at least partly reduced. The conductor is soldered to the aluminum metallization using a solder material.

VERSTÄRKTER HALBLEITERCHIP UND DIESBEZÜGLICHE VERFAHREN

Implementierungen von Verfahren zum Bilden einer Vielzahl von verstärkten Chips können ein Bilden einer Vielzahl von Chips auf einem Substrat und ein Strukturieren eines Metallgatterrahmens zum Bilden einer Vielzahl von Metallplatten einschließen. Die Vielzahl von Metallplatten kann der Vielzahl von Chips entsprechen. Das Verfahren kann ein Koppeln des Metallgatterrahmens über die Vielzahl von Chips und ein Vereinzeln der Vielzahl von Chips einschließen. Jeder Chip der Vielzahl von Chips kann die entsprechende Metallplatte aus der Vielzahl von Metallplatten einschließen, die über die Vielzahl von Chips gekoppelt sind.

Verbessertes Metall-auf-Metall-Bonden für Stacked (3D) integrierte Schaltkreise

Die vorliegende Erfindung stellt eine stabilisierte fein texturierte Metallmikrostruktur bereit, die eine dauerfeste aktivierte Fläche 310 bildet, die zum Bonden eines 3D-Stacked Chips verwendbar ist. Eine feinkörnige Schicht, die der Selbstheilung widersteht, ermöglicht ein Bonden von Metall auf Metall in moderater Zeit und Temperatur und mit einer höheren Prozessflexibilität.

고체 상태 확산 또는 상 변환에 의해 연결 층에 의한 웨이퍼의 영구 접착을 위한 방법

... 본 발명은 제1 고체 기판(1)을 제1 물질을 포함하는 제2 고체 기판(2)에 접착하기 위한 방법이며, - 제2 물질을 포함하는 기능 층(5)을 제2 고체 기판(2)에 적용 또는 형성하고; - 상기 기능 층(5) 상의 제2 고체 기판(2)과 제1 고체 기판(1)을 접촉시키며; -고체 기판(1, 2)을 함께 프레스하여 제1 및 제2 고체 기판(1, 2) 사이의 영구 접착을 형성하도록 하는 순차적인 단계를 포함하고, 상기 영구 접착이 제1 물질과 제2 물질의 고체 확산 및/또는 상 변환에 의해 적어도 부분적으로 보강되고, 상기 기능 층 상의 볼륨 증가가 발생되도록 하는 방법에 대한 것이다.

LÖTEN EINES LEITERS AN EINE ALUMINIUMMETALLISIERUNG

Ein Verfahren zum Löten eines Leiters an eine Aluminiummetallisierung beinhaltet Substituieren einer Aluminiumoxidschicht auf der Aluminiummetallisierung durch eine Substitutmetalloxidschicht oder eine Substitutmetalllegierungsoxidschicht. Dann werden Substitutmetalloxide in der Substitutmetalloxidschicht oder der Substitutmetalllegierungsoxidschicht wenigstens teilweise reduziert. Der Leiter wird unter Verwendung eines Lotmaterials an die Aluminiummetallisierung gelötet.

기질들을 서로 모이게 하여 연결 재료를 분포시키는 동안 기질들을 결합시키기 위한 방법

... 본 발명은, 제1 기질(1) 및 제2 기질(2)사이에 배열되고 연결 재료(3,5)로 구성된 연결 층(7)에 의해 하기 단계들 특히 하기 시퀀스에 따라 상기 제1 기질(1)을 제2 기질(2)과 결합시키기 위한 방법에 관한 것이고, 상기 연결 재료(3,5)를 액체 형태로 상기 제1 기질(1) 및/또는 제2 기질(2)에 도포시키는 단계, 및 상기 제1 기질(1) 및 제2 기질(2)을 더욱 근접하게 이동시켜서 상기 제1 기질(1) 및 제2 기질(2)사이에 상기 연결 재료(3,5)를 분포시키고 그 결과 두께(t)를 가진 연결 층(7)의 형상을 형성시키는 단계를 포함한다.

METHOD FOR PERMANENTLY BONDING WAFERS BY A CONNECTING LAYER BY MEANS OF SOLID STATE DIFFUSION OR PHASE TRANSFORMATION

A method for bonding of a first solid substrate to a second solid substrate which contains a first material with the following steps, especially the following sequence: formation or application of a function layer which contains a second material to the second solid substrate, making contact of the first solid substrate with the second solid substrate on the function layer, pressing together the solid substrates for forming a permanent bond between the first and second solid substrate, at least partially reinforced by solid diffusion and/or phase transformation of the first material with the second material, an increase of volume on the function layer being caused.

Improved metal to metal bonding for stacked (3D) integrated circuits

The present invention provides a stabilized fine textured metal microstructure that constitutes a durable activated surface usable for bonding a 3D stacked chip. A fine-grain layer that resists self anneal enables metal to metal bonding at moderate time and temperature and wider process flexibility.

SEMICONDUCTOR DIE HAVING FINE PITCH ELECTRICAL INTERCONNECTS

A die has interconnect pads on an interconnect side near an interconnect edge and has at least a portion of the interconnect side covered by a conformal dielectric coating, in which an interconnect trace over the dielectric coating forms a high interface angle with the surface of the dielectric coating. Because the traces have a high interface angle, a tendency for the interconnect materials to "bleed" laterally is mitigated and contact or overlap of adjacent traces is avoided. The interconnect trace includes a curable electrically conductive interconnect material; that is, it includes a material that can be applied in a flowable form, and thereafter cured or allowed to cure to form the conductive traces. Also, a method includes, prior to forming the traces, subjecting the surface of the conformal dielectric coating with a CF4 plasma treatment.

Soldering a conductor to an aluminum metallization

A method of making a semiconductor including soldering a conductor to an aluminum metallization is disclosed. In one example, the method includes substituting an aluminum oxide layer on the aluminum metallization by a substitute metal oxide layer or a substitute metal alloy oxide layer. Then, substitute metal oxides in the substitute metal oxide layer or the substitute metal alloy oxide layer are at least partly reduced. The conductor is soldered to the aluminum metallization using a solder material.

Method for permanent connection of two metal surfaces

A process for the production of a permanent, electrically conductive connection between a first metal surface of a first substrate and a second metal surface of a second substrate, wherein a permanent, electrically conductive connection is produced, at least primarily, by substitution diffusion between metal ions and/or metal atoms of the two metal surfaces.

SHEET-MOLDED CHIP-SCALE PACKAGE

Embodiments include but are not limited to apparatuses and systems including a microelectronic device including a die having a first surface and a second surface opposite the first surface, a conductive pillar formed on the first surface of the die, and an encapsulant material encasing the die, including covering the first surface, the second surface, and at least a portion of a side surface of the conductive pillar. Methods for making the same also are described.

With accurate spacing of the electrical interconnection of a semiconductor die

METHOD FOR PERMANENTLY BONDING WAFERS BY A CONNECTING LAYER BY MEANS OF SOLID-STATE DIFFUSION OR PHASE TRANSFORMATION

Metal to metal bonding for stacked (3D) integrated circuits

The present invention provides a stabilized fine textured metal microstructure that constitutes a durable activated surface usable for bonding a 3D stacked chip. A fine-grain layer that resists self anneal enables metal to metal bonding at moderate time and temperature and wider process flexibility.

SOLDERING A CONDUCTOR TO AN ALUMINUM METALLIZATION

A method of making a semiconductor including soldering a conductor to an aluminum metallization is disclosed. In one example, the method includes substituting an aluminum oxide layer on the aluminum metallization by a substitute metal oxide layer or a substitute metal alloy oxide layer. Then, substitute metal oxides in the substitute metal oxide layer or the substitute metal alloy oxide layer are at least partly reduced. The conductor is soldered to the aluminum metallization using a solder material.

UNDER-BUMP METAL STRUCTURES FOR INTERCONNECTING SEMICONDUCTOR DIES OR PACKAGES AND ASSOCIATED SYSTEMS AND METHODS

The present technology is directed to manufacturing semiconductor dies with under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects or other types of interconnects. In one embodiment, a method for forming under-bump metal (UBM) structures on a semiconductor die comprises constructing a UBM pillar by plating a first material onto first areas of a seed structure and depositing a second material over the first material. The first material has first electrical potential and the second material has a second electrical potential greater than the first electrical potential. The method further comprises reducing the difference in the electrical potential between the first material and the second material, and then removing second areas of the seed structure between the UBM pillars thereby forming UBM structures on the semiconductor die.

Improved metal to metal bonding for stacked (3d) integrated circuits

UNDER-BUMP METAL STRUCTURES FOR INTERCONNECTING SEMICONDUCTOR DIES OR PACKAGES AND ASSOCIATED SYSTEMS AND METHODS

The present technology is directed to manufacturing semiconductor dies with under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects or other types of interconnects. In one embodiment, a method for forming under-bump metal (UBM) structures on a semiconductor die comprises constructing a UBM pillar by plating a first material onto first areas of a seed structure and depositing a second material over the first material. The first material has first electrical potential and the second material has a second electrical potential greater than the first electrical potential. The method further comprises reducing the difference in the electrical potential between the first material and the second material, and then removing second areas of the seed structure between the UBM pillars thereby forming UBM structures on the semiconductor die.

Methods for hybrid wafer bonding

Methods for hybrid wafer bonding. In an embodiment, a method is disclosed that includes forming a metal pad layer in a dielectric layer over at least two semiconductor substrates; performing chemical mechanical polishing on the semiconductor substrates to expose a surface of the metal pad layer and planarize the dielectric layer to form a bonding surface on each semiconductor substrate; performing an oxidation process on the at least two semiconductor substrates to oxidize the metal pad layer to form a metal oxide; performing an etch to remove the metal oxide, recessing the surface of the metal pad layer from the bonding surface of the dielectric layer of each of the at least two semiconductor substrates; physically contacting the bonding surfaces of the at least two semiconductor substrates; and performing a thermal anneal to form bonds between the metal pads of the semiconductor substrates. Additional methods are disclosed.

SELECTIVE SOLDER DEPOSITION BY SELF-ASSEMBLY OF NANO-SIZED SOLDER PARTICLES, AND METHODS OF ASSEMBLING SOLDERED PACKAGES

A nano-sized solder suspension flows by selective wetting onto a bond pad and away from a bond-pad resist area. A microelectronic package is also disclosed that uses the nano-sized solder suspension. A method of assembling a microelectronic package is also disclosed. A computing system is also disclosed that includes a bump that was reflowed from the nano-sized solder suspension.

Method for wafer-wafer bonding

A first semiconductor structure including a first bonding oxide layer having a first metallic bonding structure embedded therein and a second semiconductor structure including a second bonding oxide layer having a second metallic bonding structure embedded therein are provided. A nitride surface treatment process is performed to provide a nitrided surface layer to each structure. Each nitrided surface layer includes nitridized oxide regions located in an upper portion of the bonding oxide layer and nitridized metallic regions located in an upper portion of the metallic bonding structures. The nitrogen within the nitridized metallic regions is then removed to restore the upper portion of the metallic bonding structures to its original composition. Bonding is performed to form a dielectric bonding interface between the nitridized oxide regions present in the first and second structures, and a metallic bonding interface between the first and second metallic bonding structures.

METHOD FOR PERMANENTLY BONDING WAFERS BY A CONNECTING LAYER BY MEANS OF SOLID-STATE DIFFUSION OR PHASE TRANSFORMATION

The present invention relates to a method for bonding a first solid substrate (1) to a second solid substrate (2), which contains a first material, comprising the following steps, in particular with the following sequence: - forming or applying a functional layer (5) containing a second material onto the second solid substrate (2), - making contact between the first solid substrate (1) and the second solid substrate (2) at the functional layer (5), - pressing together the solid substrates (1, 2) to form a permanent bond between the first and the second solid substrates (1, 2), at least partly reinforced by solid-state diffusion and/or phase transformation of the first material with the second material, wherein an increase in volume is brought about at the functional layer (5). During bonding, the solubility limit of the first material for the second material is not exceeded, or is only slightly exceeded, such that precipitation of intermetallic phases is avoided to the greatest possible ...

Method for permanently bonding wafers by a connecting layer by means of solid-state diffusion or phase transformation

The present invention relates to a method for bonding a first solid substrate (1) to a second solid substrate (2), which contains a first material, comprising the following steps, in particular with the following sequence: - forming or applying a functional layer (5) containing a second material onto the second solid substrate (2), - making contact between the first solid substrate (1) and the second solid substrate (2) at the functional layer (5), - pressing together the solid substrates (1, 2) to form a permanent bond between the first and the second solid substrates (1, 2), at least partly reinforced by solid-state diffusion and/or phase transformation of the first material with the second material, wherein an increase in volume is brought about at the functional layer (5). During bonding, the solubility limit of the first material for the second material is not exceeded, or is only slightly exceeded, such that precipitation of intermetallic phases is avoided to the greatest possible ...

Electrostatic discharge protection apparatus and process

In a process, at least one circuit element is formed in a substrate. A conductive layer is formed over the substrate and in electrical contact with the at least one circuit element. Electrostatic charges are discharged from the substrate via the conductive layer.

Metal to metal bonding for stacked (3D) integrated circuits

The present invention provides a stabilized fine textured metal microstructure that constitutes a durable activated surface usable for bonding a 3D stacked chip. A fine-grain layer that resists self anneal enables metal to metal bonding at moderate time and temperature and wider process flexibility.

Löten eines Leiters an eine Aluminiumschicht

Eine Anordnung aus einem Leiter und einer Aluminiumschicht, die zusammengelötet sind, umfasst ein Substrat und die Aluminiumschicht, die über dem Substrat angeordnet ist. Das Aluminium bildet ein erstes Bondmaterial. Eine intermetallische Zusammensetzungsschicht ist über der Aluminiumschicht angeordnet. Eine Lotschicht ist über der intermetallischen Zusammensetzungsschicht angeordnet, wobei das Lot eine niedrigschmelzende Majoritätskomponente umfasst. Der Leiter ist über der Lotschicht angeordnet, wobei der Leiter eine Lötoberfläche aufweist, die ein zweites Bondmetall umfasst. Die intermetallische Zusammensetzung umfasst Aluminium und das zweite Bondmetall und ist überwiegend frei von der niedrigschmelzenden Majoritätskomponente.

Method for bonding substrates

This invention relates to a method for bonding a first substrate (1) with a second substrate (2) by means of a connecting layer (7) that is arranged between the substrates (1, 2) and that consists of a connecting material (3, 5) with the following steps, in particular with the following sequence: - Applying the connecting material (3, 5) to the first substrate (1) and/or the second substrate (2) in liquid form, and - Distributing the connecting material (3, 5) between the substrates (1, 2) by bringing the substrates (1, 2) closer and as a result forming the shape of the connecting layer (7) with a thickness t.

METHOD FOR PERMANENT CONNECTION OF TWO METAL SURFACES

Method for Permanent Connection of Two Metal Surfaces AbstractThe invention relates to a process for the production of a permanent, electrically conductive connection between a first metal surface of a first substrate and a second metal surface of a second substrate with the following method steps, in particular the course of the method:Conditioning of the first and second metal surfaces in such a way that in a connection of the metal surfaces, in particular in a time period of a fewminutes after the conditioning, a pennanent, electrically conductive connection - produced at least primarily by substitution diffusion between in particular similar, preferably identical, metal ions and/or metal atoms of the two metal surfaces can be produced,-Orientation and connection of the first and second metal surfaces, whereby during the conditioning, orientation and connection, a process temperature of at most 300°C, in particular at most 260°C, preferably 230°C, even more preferably 200°C, especially ...

REINFORCED SEMICONDUCTOR DIE AND RELATED METHODS

Implementations of methods of forming a plurality of reinforced die may include forming a plurality of die on a substrate and patterning a metal gang frame to form a plurality of metal plates. The plurality of metal plates may correspond to the plurality of die. The method may include coupling the metal gang frame over the plurality of die and singulating the plurality of die. Each die of the plurality of die may include the corresponding metal plate from the plurality of metal plates coupled over the plurality of die.

Electronic apparatus and method for manufacturing electronic apparatus

An electronic apparatus includes: a first substrate; an electrode over the first substrate; a first conductor having a porous structure above the first substrate, the first conductor covering an upper surface and a side surface of the electrode; and an insulator above the first substrate, the insulator covering an upper surface and a side surface of the first conductor, wherein the insulator has an opening that exposes the first conductor.

Package-On-Package (PoP) Structure Including Stud Bulbs

Embodiments concern Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures. According to an embodiment, a structure includes a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs.

METHOD FOR PERMANENT CONNECTION OF TWO METAL SURFACES

A process for the production of a permanent, electrically conductive connection between a first metal surface of a first substrate and a second metal surface of a second substrate, wherein a permanent, electrically conductive connection is produced, at least primarily, by substitution diffusion between metal ions and/or metal atoms of the two metal surfaces.

METHOD FOR BONDING SUBSTRATES

Method for permanent connection of two metal surfaces

The invention relates to a process for the production of a permanent, electrically conductive connection between a first metal surface of a first substrate and a second metal surface of a second substrate with the following method steps, in particular the course of the method: Conditioning of the first and second metal surfaces in such a way that in a connection of the metal surfaces, in particular in a time period of a few minutes after the conditioning, a permanent, electrically conductive connection produced at least primarily by substitution diffusion between in particular similar, preferably identical, metal ions and/or metal atoms of the two metal surfaces-can be produced, Orientation and connection of the first and second metal surfaces, whereby during the conditioning, orientation and connection, a process temperature of at most 300 DEG C, in particular at most 260 DEG C, preferably 230 DEG C, even more preferably 200 DEG C, especially preferably at most 180 DEG C, and ideally at ...

Package structure

Package-On-Package (PoP) structures and methods of forming PoP structures are disclosed. According to an embodiment, a structure comprises a first substrate, stud bulbs, a die, a second substrate, and electric connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs.

Metal to metal bonding for stacked (3D) integrated circuits

The present invention provides a stabilized fine textured metal microstructure that constitutes a durable activated surface usable for bonding a 3D stacked chip. A fine-grain layer that resists self anneal enables metal to metal bonding at moderate time and temperature and wider process flexibility.

Method for bonding substrates

A method for bonding a first substrate with a second substrate by means of a connecting layer that is arranged between the substrates and that is comprised of a connecting material with the following steps: applying the connecting material to the first substrate and/or the second substrate in liquid form, and distributing the connecting material between the substrates by bringing the substrates closer and as a result forming the shape of the connecting layer with a thickness t.

固相拡散または相変態を用いた接続層による恒久的なウエハ結合方法

METAL TO METAL BONDING FOR STACKED (3D) INTEGRATED CIRCUITS

The present invention provides a stabilized fine textured metal microstructure that constitutes a durable activated surface usable for bonding a 3D stacked chip. A fine-grain layer that resists self anneal enables metal to metal bonding at moderate time and temperature and wider process flexibility.

ELECTROSTATIC DISCHARGE PROTECTION APPARATUS AND PROCESS

In a process, at least one circuit element is formed in a substrate. A conductive layer is formed over the substrate and in electrical contact with the at least one circuit element. Electrostatic charges are discharged from the substrate via the conductive layer. 1. A method forming a semiconductor device , comprising:forming at least one circuit element in each die of a plurality of dies in a substrate, where an outer region of the substrate surrounds each die of the plurality of dies;forming a conductive layer over the substrate, wherein the conductive layer is over and vertically aligned with at least one die of the plurality of dies and over and vertically aligned with a portion of the outer region, the conductive layer in electrical contact with the at least one circuit element in the at least one die;discharging electrostatic charges from the substrate via the conductive layer, wherein the discharging includes directly contacting a grounded electrode to a top surface of the conductive layer; andafter the discharging electrostatic charges removing a portion of the conductive layer.2. The method of claim 1 , whereindischarging the electrostatic charges comprises causing the grounded electrode to temporarily contact the conductive layer over the outer region.3. The method of claim 2 , whereinthe outer region comprises at least one scribe line,said discharging the electrostatic charges comprises causing the grounded electrode to temporarily contact the conductive layer over the at least one scribe line.4. The method of claim 1 , wherein the plurality of dies includes at least one interposer.5. The method of claim 1 , further comprising:forming a conductive bump over the substrate prior to the discharging electrostatic charges.6. The method of claim 1 , wherein the conductive layer includes an under-bump metal (UBM) structure.7. The method of claim 1 , wherein the removing the portion of the conductive layer includes performing photolithographic masking and etching ...

ファインピッチ電気相互接続体を有する半導体ダイ

Method for bonding substrates

Method for bonding substrates while distributing a connecting material by bringing the substrate together

Method for permanent connection of two metal surfaces

The invention relates to a process for the production of a permanent, electrically conductive connection between a first metal surface of a first substrate and a second metal surface of a second substrate with the following method steps, in particular the course of the method: Conditioning of the first and second metal surfaces in such a way that in a connection of the metal surfaces, in particular in a time period of a few minutes after the conditioning, a permanent, electrically conductive connection-produced at least primarily by substitution diffusion between in particular similar, preferably identical, metal ions and/or metal atoms of the two metal surfaces-can be produced, Orientation and connection of the first and second metal surfaces, whereby during the conditioning, orientation and connection, a process temperature of at most 300 DEG C, in particular at most 260 DEG C, preferably 230 DEG C, even more preferably 200 DEG C, especially preferably at most 180 DEG C, and ideally at ...

Alleviation of the corrosion pitting of chip pads

Methods for processing a metal pad of a chip and chip structures including a chip with a metal pad. A surface modification agent is applied to the metal pad on the chip. The surface modification agent is effective to increase the hydrophobicity of the metal pad and may involve silylation.

Package-on-package (PoP) structure including stud bulbs and method

Embodiments concern Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures. According to an embodiment, a structure includes a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs.

Method for permanent connection of two metal surfaces

The invention relates to a process for the production of a permanent, electrically conductive connection between a first metal surface of a first substrate and a second metal surface of a second substrate with the following method steps, in particular the course of the method: Conditioning of the first and second metal surfaces in such a way that in a connection of the metal surfaces, in particular in a time period of a few minutes after the conditioning, a permanent, electrically conductive connection-produced at least primarily by substitution diffusion between in particular similar, preferably identical, metal ions and/or metal atoms of the two metal surfaces-can be produced, Orientation and connection of the first and second metal surfaces, whereby during the conditioning, orientation and connection, a process temperature of at most 300 DEG C, in particular at most 260 DEG C, preferably 230 DEG C, even more preferably 200 DEG C, especially preferably at most 180 DEG C, and ideally at ...

Package-On-Package (PoP) Structure Including Stud Bulbs and Method

Embodiments concern Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures. According to an embodiment, a structure includes a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs.

Package-on-package (PoP) structure including stud bulbs

Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures are provided. A structure may include a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs.

METHOD FOR PERMANENTLY BONDING WAFERS BY A CONNECTING LAYER BY MEANS OF SOLID-STATE DIFFUSION OR PHASE TRANSFORMATION

METHOD FOR PERMANENT CONNECTION OF TWO METAL SURFACES

Method for Permanent Connection of Two Metal Surfaces AbstractThe invention relates to a process for the production of a permanent, electrically conductive connection between a first metal surface of a first substrate and a second metal surface of a second substrate with the following method steps, in particular the course of the method:Conditioning of the first and second metal surfaces in such a way that in a connection of the metal surfaces, in particular in a time period of a fewminutes after the conditioning, a permanent, electrically conductive connection - produced at least primarily by substitution diffusion between in particular similar, preferably identical, metal ions and/or metal atoms of the two metal surfaces can be produced,Orientation and connection of the first and second metal surfaces, whereby during the conditioning, orientation and connection, a process temperature of at most 300°C, in particular at most 260°C, preferably 230°C, even more preferably 200°C, especially ...

ELECTROSTATIC DISCHARGE PROTECTION APPARATUS AND PROCESS

In a process, at least one circuit element is formed in a substrate. A conductive layer is formed over the substrate and in electrical contact with the at least one circuit element. Electrostatic charges are discharged from the substrate via the conductive layer.

METHOD FOR PERMANENT BONDING OF WAFERS

Method for Permanent Bonding of Wafers AbstractThis invention relates to a method for bonding of a first solid substrate (1) to a second solid substrate (2) which contains a first material with the following steps, especially the following sequence:-formation or application of a function layer (5) which contains a second material to the second solid substrate (2),- making contact of the first solid substrate (1) with the second solid substrate (2) on the function layer (5),- pressing together the solid substrates ( I. 2) for forming a permanent bond between the first and second solid substrate (1. 2), at least partially reinforced by solid diffusion andlor phase transformation of the first material with the second material, an increase of volume on the function layer being caused. Figure la ...

SOLDERING A CONDUCTOR TO AN ALUMINUM LAYER

An arrangement is disclosed. In one example, the arrangement of a conductor and an aluminum layer soldered together comprises a substrate and the aluminum layer disposed over the substrate. The aluminum forms a first bond metal. An intermetallic compound layer is disposed over the aluminum layer. A solder layer is disposed over the intermetallic compound layer, wherein the solder comprises a low melting majority component. The conductor is disposed over the solder layer, wherein the conductor has a soldering surface which comprises a second bond metal. The intermetallic compound comprises aluminum and the second bond metal and is predominantly free of the low melting majority component.

Methods for hybrid wafer bonding

Methods for hybrid wafer bonding are disclosed. In an embodiment, a method is disclosed that includes forming a metal pad layer in a dielectric layer over at least two semiconductor substrates; performing chemical mechanical polishing on the semiconductor substrates to expose a surface of the metal pad layer and planarize the dielectric layer to form a bonding surface on each semiconductor substrate; performing an oxidation process on the at least two semiconductor substrates to oxidize the metal pad layer to form a metal oxide; performing an etch to remove the metal oxide, recessing the surface of the metal pad layer from the bonding surface of the dielectric layer of each of the at least two semiconductor substrates; physically contacting the bonding surfaces of the at least two semiconductor substrates; and performing a thermal anneal to form bonds between the metal pads of the semiconductor substrates. Additional methods are disclosed.

METHOD FOR PERMANENT CONNECTION OF TWO METAL SURFACES

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Semiconductor die having fine pitch electrical interconnects

A die has interconnect pads on an interconnect side near an interconnect edge and has at least a portion of the interconnect side covered by a conformal dielectric coating, in which an interconnect trace over the dielectric coating forms a high interface angle with the surface of the dielectric coating. Because the traces have a high interface angle, a tendency for the interconnect materials to bleed laterally is mitigated and contact or overlap of adjacent traces is avoided. The interconnect trace includes a curable electrically conductive interconnect material; that is, it includes a material that can be applied in a flowable form, and thereafter cured or allowed to cure to form the conductive traces. Also, a method includes, prior to forming the traces, subjecting the surface of the conformal dielectric coating with a CF4 plasma treatment.

Method for permanent bonding of wafers

Method of assembling soldered packages utilizing selective solder deposition by self-assembly of nano-sized solder particles

A nano-sized solder suspension flows by selective wetting onto a bond pad and away from a bond-pad resist area. A microelectronic package is also disclosed that uses the nano-sized solder suspension. A method of assembling a microelectronic package is also disclosed. A computing system is also disclosed that includes a bump that was reflowed from the nano-sized solder suspension.

ALLEVIATION OF THE CORROSION PITTING OF CHIP PADS

Methods for processing a metal pad of a chip and chip structures including a chip with a metal pad. A surface modification agent is applied to the metal pad on the chip. The surface modification agent is effective to increase the hydrophobicity of the metal pad and may involve silylation.

Reinforced semiconductor die and related methods

Implementations of methods of forming a plurality of reinforced die may include forming a plurality of die on a substrate and patterning a metal gang frame to form a plurality of metal plates. The plurality of metal plates may correspond to the plurality of die. The method may include coupling the metal gang frame over the plurality of die and singulating the plurality of die. Each die of the plurality of die may include the corresponding metal plate from the plurality of metal plates coupled over the plurality of die.

Metal to metal bonding for stacked (3D) integrated circuits

The present invention provides a stabilized fine textured metal microstructure that constitutes a durable activated surface usable for bonding a 3D stacked chip. A fine-grain layer that resists self anneal enables metal to metal bonding at moderate time and temperature and wider process flexibility.

Chip package and method for forming the same

A chip package including a first substrate having an upper surface, a lower surface and a sidewall is provided. A sensing region or device region and a conducting pad are adjacent to the upper surface. A through-hole penetrates the first substrate. A redistribution layer extends from the lower surface into the through-hole and is electrically connected to the conducting pad, wherein the redistribution layer further laterally extends from the lower surface to penetrate from the sidewall. A method for forming the chip package is also provided.

Package-On-Package (PoP) Structure Including Stud Bulbs and Method

Embodiments concern Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures. According to an embodiment, a structure includes a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs.

Semiconductor die having fine pitch electrical interconnects

A die has interconnect pads on an interconnect side near an interconnect edge and has at least a portion of the interconnect side covered by a conformal dielectric coating, in which an interconnect trace over the dielectric coating forms a high interface angle with the surface of the dielectric coating. Because the traces have a high interface angle, a tendency for the interconnect materials to “bleed” laterally is mitigated and contact or overlap of adjacent traces is avoided. The interconnect trace includes a curable electrically conductive interconnect material; that is, it includes a material that can be applied in a flowable form, and thereafter cured or allowed to cure to form the conductive traces. Also, a method includes, prior to forming the traces, subjecting the surface of the conformal dielectric coating with a CF4 plasma treatment.

Under-bump metal structures for interconnecting semiconductor dies or packages and associated systems and methods

The present technology is directed to manufacturing semiconductor dies with under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects or other types of interconnects. In one embodiment, a method for forming under-bump metal (UBM) structures on a semiconductor die comprises constructing a UBM pillar by plating a first material onto first areas of a seed structure and depositing a second material over the first material. The first material has first electrical potential and the second material has a second electrical potential greater than the first electrical potential. The method further comprises reducing the difference in the electrical potential between the first material and the second material, and then removing second areas of the seed structure between the UBM pillars thereby forming UBM structures on the semiconductor die.

For mixing wafer bonding method

... 公开种用于混合晶圆接合的方法。在个实施例中，公开了种方法，包括：在至少两个半导体衬底之上的介电层中形成金属焊盘层；对半导体衬底执行化学机械抛光，以暴露金属焊盘层的表面，并且平坦化介电层，以在每个半导体衬底上形成接合表面；对至少两个半导体衬底执行氧化工艺，以氧化金属焊盘层，形成金属氧化物；执行蚀刻以去除金属氧化物，使金属焊盘层的表面从至少两个半导体衬底中的每个的介电层的接合表面凹陷；使至少两个半导体衬底的接合表面在物理上接触；以及执行热退火，以在半导体衬底的金属焊盘之间形成接合。公开了附加方法。 ...

Under-bump metal structures for interconnecting semiconductor dies or packages and associated systems and methods

The present technology is directed to manufacturing semiconductor dies with under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects or other types of interconnects. In one embodiment, a method for forming under-bump metal (UBM) structures on a semiconductor die comprises constructing a UBM pillar by plating a first material onto first areas of a seed structure and depositing a second material over the first material. The first material has first electrical potential and the second material has a second electrical potential greater than the first electrical potential. The method further comprises reducing the difference in the electrical potential between the first material and the second material, and then removing second areas of the seed structure between the UBM pillars thereby forming UBM structures on the semiconductor die.

Method for permanent connection of two metal surfaces

The invention relates to a process for the production of a permanent, electrically conductive connection between a first metal surface of a first substrate and a second metal surface of a second substrate with the following method steps, in particular the course of the method: Conditioning of the first and second metal surfaces in such a way that in a connection of the metal surfaces, in particular in a time period of a few minutes after the conditioning, a permanent, electrically conductive connection-produced at least primarily by substitution diffusion between in particular similar, preferably identical, metal ions and/or metal atoms of the two metal surfaces-can be produced, Orientation and connection of the first and second metal surfaces, whereby during the conditioning, orientation and connection, a process temperature of at most 300 DEG C, in particular at most 260 DEG C, preferably 230 DEG C, even more preferably 200 DEG C, especially preferably at most 180 DEG C, and ideally at ...

METHOD FOR PERMANENT CONNECTION OF TWO METAL SURFACES

Wiring board and method for manufacturing the same

A wiring board including a first insulation layer, a conductive pattern formed on the first insulation layer, a second insulation layer formed on the conductive pattern and the first insulation layer and having an opening portion exposing at least a portion of the conductive pattern, and a connection conductor formed in the opening portion of the second insulation layer such that the connection conductor is positioned on the portion of the conductive pattern. The connection conductor has a tip portion which protrudes from a surface of the second insulation layer and which has a tapered side surface tapering toward an end of the tip portion.

Semiconductor device and manufacturing method thereof

Semiconductor devices of embodiments include a plurality of solder bumps electrically connected on a plurality of electrode pads disposed on a semiconductor substrate in parallel at a pitch of 40 μm or less via under bump metals. The ratio of the diameter (the top diameter) of the portion of each solder bump most away from the semiconductor substrate and the diameter (the bottom diameter) of the bottom side of each solder bump is 1:1 to 1:4.

Conductive feature for semiconductor substrate and method of manufacture

A conductive feature on a semiconductor component is disclosed. A first passivation layer is formed over a substrate. A bond pad is formed over the first passivation layer. A second passivation layer overlies the first passivation layer and the bond pad. The second passivation layer has a first opening overlying the bond pad and a plurality of second openings exposing a top surface of the first passivation layer. A buffer layer overlies the second passivation layer and fills the plurality of second openings. The buffer layer has a third opening overlapping the first opening and together exposes a portion the bond pad. The combined first opening and third opening has sidewalls. An under bump metallurgy (UBM) layer overlies the sidewalls of the combined first opening and third opening, and contacts the exposed portion of the bond pad. A conductive feature overlies the UBM layer.

Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device including the following steps: forming an insulator layer over a first conductor over a semiconductor substrate; forming a barrier layer to coat the surface of the insulator layer; forming a second conductor over the barrier layer; melting the second conductor in an atmosphere containing either hydrogen or carboxylic acid in a condition that the surface of the insulator layer over the first conductor is coated with the barrier layer; and removing the barrier layer partially from the surface of the insulator layer with the second conductor as a mask.

Semiconductor device, semiconductor device unit, and semiconductor device production method

An example of a semiconductor device according to the present invention includes: a protective film ( 1 ) which has an opening to expose a part of the surface of an electrode pad ( 4 ) and covers the surface of the electrode pad ( 4 ) excluding the opening; and a bump ( 6 ) which is electrically connected with the electrode pad ( 4 ) through the opening of the protective film ( 1 ) and has a part exposed outside within the area of the electrode pad ( 4 ), wherein probe marks ( 7 ) are formed by a probe brought into contact with the electrode pad ( 4 ) for electrical characteristic inspection, and the probe marks ( 7 ) are positioned within a region where the protective film ( 1 ) is formed and are covered by the protective film ( 1 ).

Semiconductor laser mounting with intact diffusion barrier layer

A first contact surface of a semiconductor laser chip can be formed to a target surface roughness selected to have a maximum peak to valley height that is substantially smaller than a barrier layer thickness. A barrier layer that includes a non-metallic, electrically-conducting compound and that has the barrier layer thickness can be applied to the first contact surface, and the semiconductor laser chip can be soldered to a carrier mounting along the first contact surface using a solder composition by heating the soldering composition to less than a threshold temperature at which dissolution of the barrier layer into the soldering composition occurs. Related systems, methods, articles of manufacture, and the like are also described.

Semiconductor package, packaging substrate and fabrication method thereof

A packaging substrate and a semiconductor package using the packaging substrate are provided. The packaging substrate includes: a substrate body having a die attach area, a circuit layer formed around the die attach area and having a plurality of conductive traces each having a wire bonding pad, and a surface treatment layer formed on the wire bonding pads. Therein, only one of the conductive traces is connected to an electroplating line so as to prevent cross-talk that otherwise occurs between conductive traces due to too many electroplating lines in the prior art.

Semiconductor device having a through-substrate via

Semiconductor devices are described that include a via that extends only partially through the substrate. Through-substrate vias (TSV) furnish electrical interconnectivity to electronic components formed in the substrates. In implementations, the semiconductor devices are fabricated by first bonding a semiconductor wafer to a carrier wafer with an adhesive material. The semiconductor wafer includes an etch stop disposed within the wafer (e.g., between a first surface a second surface of the wafer). One or more vias are formed through the wafer. The vias extend from the second surface to the etch stop.

Mechanisms of forming connectors for package on package

The described embodiments of mechanisms of forming connectors for package on package enable smaller connectors with finer pitch, which allow smaller package size and additional connections. The conductive elements on one package are partially embedded in the molding compound of the package to bond with contacts or metal pads on another package. By embedding the conductive elements, the conductive elements may be made smaller and there are is gaps between the conductive elements and the molding compound. A pitch of the connectors can be determined by adding a space margin to a maximum width of the connectors. Various types of contacts on the other package can be bonded to the conductive elements.

Magnet Assisted Alignment Method for Wafer Bonding and Wafer Level Chip Scale Packaging

A high-precision alignment method with high throughput is proposed, which can be used for wafer-to-wafer, chip-to-wafer or chip-to-chip bonding. The scheme implements pairing patterned magnets predetermined designed and made using wafer level process on two components (wafer or chip). The magnetization in patterned magnet can be set at predetermined configuration before bonding starts. When, the two components are bought to close proximity after a coarse alignment, the magnetic force will bring the magnet pairs together and aligned the patterned magnet on one component with its mirrored or complimentary patterned magnets on the other component to minimize the overall the magnetic energy of the pairing magnet. A few patterned magnet structures and materials, with their unique merits are proposed as examples for magnet pair for the self-alignment purpose. This method enables solid contact at the bonding interface via patterned magnets under the magnetic force, which avoid the wafer drafting due to the formation of the liquid phases.

Semiconductor device fabrication method

A transistor formed on a semiconductor substrate is covered with a first insulating film, and first conductive vias which pierce the first insulating film and which reach the transistor and a second conductive via which pierces the first insulating film and which reaches an inside of the semiconductor substrate are formed. After the formation of the first conductive vias and the second conductive via, a second insulating film is formed over the first insulating film. Conducive portions connected to the first conductive vias leading to the transistor and a conductive portion connected to the second conductive via which reaches the inside of the semiconductor substrate are formed in the second insulating film. By doing so, a multilayer interconnection is formed.

Method to realize flux free indium bumping

A method to realize flux free indium bumping process includes several steps including substrate metallization, contact holes opening, underbump metallization (UBM) layer thickening, indium bump preparation and Ag layer coating. The method can be used in the occasion for some special application, e.g., the packaging of the photoelectric chip (with optical lens), MEMS and biological detection chip, where the usage of flux is prohibited.

Integrated wluf and sod process

This disclosure relates generally to a wafer having a plurality of semiconductor chips having a major surface, a metal contact positioned on one of the plurality of semiconductor chips and having a side surface and contact surface, the contact surface substantially parallel to the major surface, wherein the contact surface defines a thickness of the metal contact relative to the major surface, an underfill layer abutting the one of the plurality of semiconductor chips and the side surface of the metal contact, the underfill layer having a top surface substantially parallel to the major surface, wherein the top surface of the underfill layer defines a thickness of the underfill layer relative to the major surface, the thickness of the underfill layer being not greater than the thickness of the metal contact, and a solder bump formed in electrical contact with the contact surface of the metal contact.

Submicron connection layer and method for using the same to connect wafers

A submicron connection layer and a method for using the same to connect wafers is disclosed. The connection layer comprises a bottom metal layer formed on a connection surface of a wafer, an intermediary diffusion-buffer metal layer formed on the bottom metal layer, and a top metal layer formed on the intermediary diffusion-buffer metal layer. The melting point of the intermediary diffusion-buffer metal layer is higher than the melting points of the top and bottom metal layers. The top and bottom metal layers may form a eutectic phase. During bonding wafers, two top metal layers are joined in a liquid state; next the intermediary diffusion-buffer metal layers are distributed uniformly in the molten top metal layers; then the top and bottom metal layers diffuse to each other to form a low-resistivity eutectic intermetallic compound until the top metal layers are completely exhausted by the bottom metal layers.

Power MOSFET Having Selectively Silvered Pads for Clip and Bond Wire Attach

A packaged power field effect transistor device includes a power field effect transistor die, a DBA substrate, a clip, a wire bond, leads, and an amount of plastic encapsulant. The top of the DBA has a plurality of metal plate islands. A sintered silver feature is disposed on one of the islands. A silvered backside of the die is directly bonded to the sintered silver structure of the DBA. The upper surface of the die includes a first aluminum pad (a source pad) and a second aluminum pad (a gate pad). A sintered silver structure is disposed on the first aluminum pad, but there is no sintered silver structure disposed on the second aluminum pad. A high current clip is attached via soft solder to the sintered silver structure on the first aluminum pad (the source pad). A bond wire is ultrasonically welded to the second aluminum pad (gate pad).

TWO-SIDED-ACCESS EXTENDED WAFER-LEVEL BALL GRID ARRAY (eWLB) PACKAGE, ASSEMBLY AND METHOD

A two-sided-access (TSA) eWLB is provided that makes it possible to easily access electrical contact pads disposed on both the front and rear faces of the die(s) of the eWLB package. When fabricating the IC die wafer, metal stamps are formed in the IC die wafer in contact with the rear faces of the IC dies. When the IC dies are subsequently reconstituted in an artificial wafer, portions of the metal stamps are exposed through the mold of the artificial wafer. When the artificial wafer is sawed to singulate the TSA eWLB packages and the packages are mounted on PCBs, any electrical contact pad that is disposed on the rear face of the IC die can be accessed via the respective metal stamp of the IC die.

ITERATIVE FORMATION OF DAMASCENE INTERCONNECTS

Disclosed herein are interconnects and methods of fabricating a plurality of interconnects. The method includes depositing a conformal layer of a plating base in each of a plurality of vias, and depositing a photoresist on two portions of a surface of the plating base outside and above the plurality of vias. The method also includes depositing a plating metal over the plating base in each of the plurality of vias, the depositing resulting in each of the plurality of vias being completely filled or incompletely filled, performing a chemical mechanical planarization (CMP), and performing metrology to determine if any of the plurality of vias is incompletely filled following the depositing the plating metal. A second iteration of the depositing the plating metal over the plating base is performed in each of the plurality of vias based on determining that at least one of the plurality of vias is incompletely filled. 1. A method of fabricating a plurality of interconnects , the method comprising:depositing a conformal layer of a plating base in each of a plurality of vias;depositing a photoresist on two portions of a surface of the plating base outside and above the plurality of vias;depositing a plating metal over the plating base in each of the plurality of vias, wherein the depositing the plating metal results in each of the plurality of vias being completely filled or incompletely filled with the plating metal;performing a chemical mechanical planarization (CMP);performing metrology to determine if any of the plurality of vias is incompletely filled following the depositing the plating metal; andperforming a second iteration of the depositing the plating metal over the plating base in each of the plurality of vias based on determining that at least one of the plurality of vias is incompletely filled.2. The method according to claim 1 , further comprising forming a plurality of intermediate structures corresponding to the plurality of interconnects by etching a ...

PROCESS FLOW FOR FABRICATION OF CAP METAL OVER TOP METAL WITH SINTER BEFORE PROTECTIVE DIELECTRIC ETCH

A method of forming a semiconductor device for improving an electrical connection. The semiconductor device includes a top metal layer. A protective dielectric layer is formed over the top metal layer. A sintering operation is performed while the top metal layer is covered by the protective dielectric layer. After the sintering operation, the protective dielectric layer is patterned to expose areas on the top metal layer for bond pads of the semiconductor device. A bond pad cap is formed on the top metal layer where exposed by the protective dielectric layer. 1. A method of forming a semiconductor device , comprising:providing a device substrate containing the semiconductor device, the device substrate including a semiconductor material;forming an active component extending into the semiconductor material;forming an interconnect region on the semiconductor material; andforming a top metal layer in the interconnect region;forming a protective dielectric layer on the top metal layer, the protective dielectric layer being at least 1 micron thick;heating the semiconductor device in a sintering operation while the protective dielectric layer covers the top metal layer;after the sintering operation, removing the protective dielectric layer from a bond pad opening in the protective dielectric layer to expose a portion of the top metal layer; andforming a bond pad cap on the top metal layer in the bond pad opening.2. The method of claim 1 , wherein the sintering operation has a sinter thermal profile sufficient to passivate the active component.3. The method of claim 2 , wherein the sinter thermal profile includes heating the semiconductor device to a sinter temperature for a sinter time claim 2 , wherein a product of the sinter time claim 2 , in minutes claim 2 , and an Arrhenius factor of the sinter temperature is greater than 0.0027 minutes claim 2 , the Arrhenius factor of the sinter temperature being determined by the expression:{'br': None, 'i': E', 'k', '+T, 'sub': A ...

Molded Semiconductor Package

A molded semiconductor package includes a mold compound having opposing first and second main surfaces and an edge extending between the first and second main surfaces. A semiconductor die is embedded in the mold compound. A plurality of metal pads embedded in the mold compound are electrically connected to the semiconductor die. The metal pads have a bottom face which is uncovered by the mold compound at the second main surface of the mold compound. The metal pads disposed around a periphery of the molded package have a side face which is uncovered by the mold compound at the edge of the mold compound. The faces of the metal pads uncovered by the mold compound are plated. The side face of each metal pad disposed around the periphery of the molded package is recessed inward from the edge of the mold compound. A corresponding manufacturing method is also described.

BOND PADS FOR LOW TEMPERATURE HYBRID BONDING

Various chip stacks and methods and structures of interconnecting the same are disclosed. In one aspect, an apparatus is provided that includes a first semiconductor chip that has a first glass layer and plural first groups of plural conductor pads in the first glass layer. Each of the plural first groups of conductor pads is configured to bumplessly connect to a corresponding second group of plural conductor pads of a second semiconductor chip to make up a first interconnect of a plurality interconnects that connect the first semiconductor chip to the second semiconductor chip. The first glass layer is configured to bond to a second glass layer of the second semiconductor chip. 1. An apparatus , comprising:a first semiconductor chip having a first glass layer and plural first groups of plural conductor pads in the first glass layer, each of the plural first groups of conductor pads including a main conductor pad and one or more dummy pads adjacent the main conductor pad and being configured to bumplessly connect to a corresponding second group of plural conductor pads of a second semiconductor chip to make up a first interconnect of a plurality of interconnects that connect the first semiconductor chip to the second semiconductor chip; andthe first glass layer being configured to bond to a second glass layer of the second semiconductor chip.2. The apparatus of claim 1 , wherein each of the first groups comprises a main conductor pad and plural dummy pads circumferentially arranged around the main conductor pad.3. The apparatus of claim 1 , comprising the second semiconductor chip mounted on the first semiconductor chip and electrically connected thereto by the plurality of interconnects.4. An apparatus claim 1 , comprising:a first semiconductor chip having a first glass layer and plural first conductor pads in the first glass layer, each of the plural first conductor pads including a base layer and a bonding layer on the base layer, the base layer having a greater ...

METHOD TO IMPROVE CMP SCRATCH RESISTANCE FOR NON PLANAR SURFACES

An electronic device is formed by providing a substrate having a recess at a top surface. A layer of an organic protective material is formed over the substrate, with the organic protective material extending into the recess. A polishing process is performed on the layer of protective material. The polishing process may remove a portion of an underlying metal layer over the top surface while protecting the underlying metal layer within the recess. 1. A method of forming an electronic device , comprising:providing a substrate having a recess in a top surface of the substrate;forming a layer of an organic protective material over the substrate, the layer of organic protective material extending into the recess and covering the top surface;performing a polishing process on the layer of protective material.2. The method of claim 1 , wherein the layer of protective material comprises photoresist.3. The method of claim 1 , wherein the layer of protective material comprises a resin.4. The method of claim 1 , wherein the layer of protective material comprises polymer.5. The method of claim 1 , wherein the layer of protective material comprises a material mixed with a solvent.6. The method of claim 5 , wherein the layer of protective material is treated to remove solvent.7. The method of claim 1 , wherein forming a layer of an organic protective material includes spin-coating the organic protective material onto the top surface.8. The method of claim 1 , wherein the top surface of the substrate comprises a dielectric material.9. The method of claim 1 , wherein the polishing processes comprises chemical-mechanical polishing.10. The method of claim 1 , wherein a metal layer is located over the substrate surface and within the recess prior to forming a layer of an organic protective material over the substrate claim 1 , and the polishing process removes the metal layer from over the top surface and leaves a remaining portion of the metal layer within the recess.11. The method ...

LEAD-FREE SOLDER JOINING OF ELECTRONIC STRUCTURES

A method and structure for joining a semiconductor device and a laminate substrate or two laminate substrates where the joint is formed with lead free solders and lead free compositions. The various lead free solders and lead free compositions are chosen so that there is a sufficient difference in liquidus temperatures such that some components may be joined to, or removed from, the laminate substrate without disturbing other components on the laminate substrate. 1. A method of joining a semiconductor structure comprising:forming a first low melting temperature lead free solder having a liquidus temperature less than 230° C. on a first substrate;placing a lead free ball comprising copper and tin having a liquidus temperature greater than 250° C. on the first low melting temperature lead free solder;reflowing the first low melting temperature lead free solder at a temperature lower than the liquidus temperature of the lead free ball;annealing at a temperature of 140 to 165° C. to convert the first low melting temperature lead free solder into a higher melting temperature lead free solder having a liquidus temperature of 240 to 250° C.;placing a second low melting temperature lead free solder having a liquidus temperature of 220° C. or less on a second substrate;placing the lead free ball in direct contact with the second low melting temperature lead free solder; andheating at 240 to 260° C. the semiconductor structure to cause the second low melting temperature lead free solder to reflow and join with the lead free ball.2. The method of wherein the first low melting temperature lead free solder and the second low melting temperature lead free solder each comprise an alloy of tin claim 1 , silver and copper.3. The method of wherein the lead free ball has a liquidus temperature of 250-280 C.4. The method of wherein the lead free ball is an alloy comprising tin/silver/nickel/copper/gold having the composition claim 1 , in weight percent claim 1 , of 0.01 to 6% copper ...

SUPERCONDUCTING BUMP BONDS

A device includes a first chip having a first circuit element, a first interconnect pad in electrical contact with the first circuit element, and a barrier layer on the first interconnect pad, a superconducting bump bond on the barrier layer, and a second chip joined to the first chip by the superconducting bump bond, the second chip having a first quantum circuit element, in which the superconducting bump bond provides an electrical connection between the first circuit element and the first quantum circuit element. 18.-. (canceled)9. A method comprising:providing a first chip comprising a first circuit element;forming a first aluminum interconnect pad on a first surface of the first chip so that the first aluminum interconnect pad is electrically connected to the first circuit element;forming a first titanium nitride barrier layer on the first aluminum interconnect pad;providing a second chip comprising a second circuit element;forming an indium bump bond; andjoining the first chip to the second chip with the indium bump bond so that the first circuit element is electrically connected to the second circuit element.10. (canceled)11. The method of claim 9 , further comprising removing a native oxide from the first aluminum interconnect pad prior to forming the first titanium nitride barrier layer.12. The method of claim 11 , wherein removing the native oxide comprises ion milling a surface of the first aluminum interconnect pad.13. The method of claim 9 , wherein forming the first titanium nitride barrier comprises reactive sputtering titanium nitride on the first aluminum interconnect pad.14. The method of claim 9 , further comprising ion milling a surface of the first titanium nitride barrier layer prior to joining the first chip to the second chip.15. The method of claim 9 , further comprising exposing a surface of the indium bump bond to a Hplasma.16. The method of claim 9 , further comprising:forming a second aluminum interconnect pad on a first surface of the ...

SUPERCONDUCTING BUMP BONDS

A device includes a first chip having a first circuit element, a first interconnect pad in electrical contact with the first circuit element, and a barrier layer on the first interconnect pad, a superconducting bump bond on the barrier layer, and a second chip joined to the first chip by the superconducting bump bond, the second chip having a first quantum circuit element, in which the superconducting bump bond provides an electrical connection between the first circuit element and the first quantum circuit element. 1. A device comprising:a first chip comprising a first circuit element, a first interconnect pad in electrical contact with the first circuit element, and a barrier layer on the first interconnect pad, wherein the barrier layer is titanium nitride;a superconducting bump bond on the barrier layer; anda second chip joined to the first chip by the superconducting bump bond, the second chip comprising a first quantum circuit element, wherein the superconducting bump bond provides an electrical connection between the first circuit element and the first quantum circuit element.2. The device of claim 1 , wherein the first interconnect pad is aluminum.3. The device of claim 1 , wherein the superconducting bump bond is indium.4. The device of claim 1 , wherein the first circuit element comprises a rapid single flux quantum (RSFQ) device.5. The device of claim 1 , wherein the first circuit element comprises a second quantum circuit element.6. The device of claim 1 , wherein at least one of the first chip and the second chip comprises a silicon substrate.7. The device of claim 1 , wherein at least one of the first chip and the second chip comprises a sapphire substrate.8. The device of claim 1 , wherein a first surface of the first chip is spaced apart from and faces a first surface of the second chip to form a gap. This application claims priority to and is a divisional of U.S. patent application Ser. No. 16/062,064, filed on Jun. 13, 2018, which claims priority ...

SEMICONDUCTOR DEVICE PROCESSING METHOD FOR MATERIAL REMOVAL

A method of removing at least a portion of a layer of material from over a semiconductor substrate that can include dispensing an etching solution over the semiconductor substrate to form a pool of etching solution on the layer of material, wherein a footprint of the pool of etching solution is less than a footprint of the semiconductor substrate. The pool of etching solution and the semiconductor substrate can be moved with respect to each other. A pool boundary of the pool of etching solution can be defined on the semiconductor substrate with at least one air-knife such that the pool of etching solution etches the layer of material over the semiconductor substrate within the footprint of the pool of etching solution. The etching solution and at least a portion of the layer of material etched by the etching solution can be removed with the at least one air-knife. 1. A method of removing material from a semiconductor device , comprising:providing a semiconductor substrate comprising a length L, a first surface, and a second surface opposite the first surface;forming a layer of material over the first surface of the semiconductor substrate;providing a conveyor;providing a first air-knife disposed over the conveyor;providing a second air-knife disposed over the conveyor and offset from the first air-knife by a distance D that is less than the length L of the semiconductor substrate;placing the semiconductor substrate on the conveyor with the layer of material oriented facing away from the conveyor, the semiconductor substrate being placed on the conveyor before the first air-knife and before the second air-knife;advancing the semiconductor substrate along the conveyor and under the first air-knife so that a portion of the semiconductor substrate is disposed between the first air-knife and the second air-knife;forming a pool of etching solution by dispensing an etching solution onto the layer of material over the portion of the semiconductor substrate disposed between ...

CHIP PACKAGE AND METHOD OF FORMING A CHIP PACKAGE WITH A METAL CONTACT STRUCTURE AND PROTECTIVE LAYER, AND METHOD OF FORMING AN ELECTRICAL CONTACT

In various embodiments, a chip package is provided. The chip package may include a chip, a metal contact structure including a non-noble metal and electrically contacting the chip, a packaging material, and a protective layer including or essentially consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material, wherein the protective layer may include a noble metal, wherein the portion of the protective layer may include a plurality of regions free from the noble metal, and wherein the regions free from the noble metal may provide an interface between the packaging material and the non-noble metal of the metal contact structure. 1. A method of forming an electrical contact , comprising:arranging an intermediate layer on the metal surface;arranging a metal contact structure over or on a metal surface; andplating a metal layer on the metal surface and on the metal contact structure, thereby fixing the metal contact structure to the metal surface and forming an electrical contact between the metal contact structure and the metal surface or strengthening or thickening an existing electrical contact between the metal contact structure and the metal surface.2. The method of claim 1 , further comprising:before plating the metal layer on the metal surface and on the metal contact structure, treating the metal surface and the metal contact structure by a process involving wet chemistry, dry chemistry, and/or a plasma in order to prepare a surface of the metal surface and of the metal contact structure for the plating.3. The method of claim 1 , wherein the metal contact structure claim 1 , the metal surface and/or a metallization material comprises or consists of copper.4. The method of claim 1 , wherein the metal contact structure may contain or consist of the same metal as the metal surface.5. The method of claim 3 , wherein the metallization comprises a galvanic deposit or an electroless deposit.6. The method of ...

Method for processing an electronic component and an electronic component

According to various embodiments an electronic component includes: at least one electrically conductive contact region; a contact pad including a self-segregating composition disposed over the at least one electrically conductive contact region; a segregation suppression structure disposed between the contact pad and the at least one electrically conductive contact region, wherein the segregation suppression structure includes more nucleation inducing topography features than the at least one electrically conductive contact region for perturbing a chemical segregation of the self-segregating composition by crystallographic interfaces of the contact pad defined by the nucleation inducing topography features.

SEMICONDUCTOR STRUCTURES AND METHODS OF MANUFACTURE

Wire-bonded semiconductor structures using organic insulating material and methods of manufacture are disclosed. The method includes forming a metal wiring layer in an organic insulator layer. The method further includes forming a protective layer over the organic insulator layer. The method further includes forming a via in the organic insulator layer over the metal wiring layer. The method further includes depositing a metal layer in the via and on the protective layer. The method further includes patterning the metal layer with an etch chemistry that is damaging to the organic insulator layer. 1. A method , comprising:forming an organic insulator layer on an underlying substrate, using a spin on technique;forming a wiring layer in a patterned section of the organic insulator layer using an electroplating process;forming a protective layer over the organic insulator layer;forming a via in the organic insulator layer using an etching chemistry that minimizes damage to the organic insulator layer, the via being in alignment with the wiring layer;depositing an Al layer in the via and on the protective layer;patterning the Al layer with a chlorine etch chemistry to form at least a bond structure;forming an insulating layer over the bond structure; andforming a via structure to the patterned metal layer.2. The method of claim 1 , further comprising forming a layer over the wiring layer claim 1 , and under the organic insulator layer claim 1 , wherein:the Al layer is formed by a blanket deposition process; andthe forming of the via exposes the wiring layer.3. The method of claim 1 , wherein the organic insulator layer is one of polyimide claim 1 , BCB (Benzocyclobutene) and PBO (polybenzoxazole).4. The method of claim 1 , further comprising removing exposed portions of the protective layer using a fluorine based etching process that minimizes damage to the organic insulator layer claim 1 , after the patterning.5. The method of claim 4 , wherein the protective layer is a ...

Passivation scheme for pad openings and trenches

An integrated circuit (IC) comprising an enhanced passivation scheme for pad openings and trenches is provided. In some embodiments, an interlayer dielectric (ILD) layer covers a substrate and at least partially defines a trench. The trench extends through the ILD layer from a top of the ILD layer to the substrate. A conductive pad overlies the ILD layer. A first passivation layer overlies the ILD layer and the conductive pad, and further defines a pad opening overlying the conductive pad. A second passivation layer overlies the ILD layer, the conductive pad, and the first passivation layer, and further lines sidewalls of the first passivation layer in the pad opening and sidewalls of the ILD layer in the trench. Further, the second passivation layer has a low permeability for moisture or vapor relative to the ILD layer.

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

A method for manufacturing semiconductor devices is provided. In the method, a conductive pad and a metal protrusion pattern are formed in a metallization layer. A passivation layer is conformally deposited over the metallization, and a protection layer is conformity deposited over the passivation layer. Further, a post-passivation interconnect structure (PPI) is conformally formed on the protection layer, and the PPI structure includes a landing pad region, a protrusion pattern over at least a portion of the landing pad region and a connection line electrically connected to the conductive pad. A solder bump is then placed on the landing pad region in contact with the protrusion pattern of PPI structure. A semiconductor device with bum stop structure is also provided. 1. A method for manufacturing semiconductor devices , the method comprising:forming a conductive pad and a metal protrusion pattern in a metallization layer;conformally depositing a passivation layer over the metallization layer;forming a first opening in the passivation layer to expose the conductive pad;conformally depositing a protection layer over the passivation layer;forming a second opening to expose the conductive pad through the first opening;conformally forming a post-passivation interconnect (PPI) structure on the protection layer, the PPI structure having a landing pad region, a protrusion pattern over at least a portion of the landing pad region and a connection line electrically connected to the conductive pad; andplacing a solder bump on the landing pad region in contact with the protrusion pattern of PPI structure.2. The method of claim 1 , wherein the protrusion pattern of PPI structure is a rectangular stud in or across the landing pad region and adjacent to the connection line.3. The method of claim 1 , wherein the PPI structure is redistribution lines (RDLs) claim 1 , power lines claim 1 , or passive components.4. The method of claim 1 , wherein conformally depositing the protection ...

Semiconductor Chip and Method for Forming a Chip Pad

A semiconductor chip with different chip pads and a method for forming a semiconductor chip with different chip pads are disclosed. In some embodiments, the method comprises depositing a barrier layer over a chip front side, depositing a copper layer after depositing the barrier layer, and removing a part of the copper layer located outside a first chip pad region, wherein a remaining portion of the copper layer within the first chip pad region forms a surface layer of the chip pad. The method further comprises removing a part of the barrier layer located outside the first chip pad region.

Semiconductor devices and processing methods

Various embodiments provide a semiconductor device, including a final metal layer having a top side and at least one sidewall; and a passivation layer disposed over at least part of at least one of the top side and the at least one sidewall of the final metal layer; wherein the passivation layer has a substantially uniform thickness.

Strong, heat stable junction

Provided among other things is an electrical device comprising: a first component that is a semiconductor or an electrical conductor; a second component that is an electrical conductor; and a strong, heat stable junction there between including an intermetallic bond formed of: substantially (a) indium (In), tin (Sn) or a mixture thereof, and (b) substantially nickel (Ni). The junction can have an electrical contact resistance that is small compared to the resistance of the electrical device.

Segmented Bond Pads and Methods of Fabrication Thereof

In accordance with an embodiment of the present invention, a semiconductor device includes a first bond pad disposed at a first side of a substrate. The first bond pad includes a first plurality of pad segments. At least one pad segment of the first plurality of pad segments is electrically isolated from the remaining pad segments of the first plurality of pad segments. 1. A semiconductor device comprising:a first bond pad disposed at a first side of a substrate, the first bond pad comprising a first plurality of pad segments, wherein at least one pad segment of the first plurality of pad segments is electrically isolated from the remaining pad segments of the first plurality of pad segments.2. The device of claim 1 , further comprising a second bond pad spaced from the first bond pad disposed at the first side claim 1 , the second bond pad comprising a second plurality of pad segments claim 1 , wherein at least one pad segment of the second plurality of pad segments is electrically isolated from the remaining pad segments of the second plurality of pad segments.3. The device of claim 2 , wherein the first bond pad is coupled to a source node of a transistor claim 2 , and wherein the second bond pad is coupled to a gate node of the transistor.4. The device of claim 2 , wherein the first bond pad is coupled to a drain node of a transistor claim 2 , and wherein the second bond pad is coupled to a gate node of the transistor.5. The device of claim 1 , wherein each of the first plurality of pad segments is separated from an adjacent pad segment of the first plurality of pad segments by a plurality of openings.6. The device of claim 5 , wherein the plurality of openings comprise a dielectric material.7. The device of claim 1 , wherein the semiconductor device comprises a discrete semiconductor device.8. The device of claim 1 , wherein the semiconductor device comprises an integrated circuit.9. The device of claim 1 , wherein the first bond pad is a solder pad.10. A ...

Battery protection package and process of making the same

The present invention discloses small-size battery protection packages and provides a process of fabricating small-size battery protection packages. A battery protection package includes a first common-drain metal oxide semiconductor field effect transistor (MOSFET), a second common-drain MOSFET, a power control integrated circuit (IC), a plurality of solder balls, a plurality of conductive bumps, and a packaging layer. The power control IC is vertically stacked on top of the first and second common-drain MOSFETs. At least a majority portion of the power control IC and at least majority portions of the plurality of solder balls are embedded into the packaging layer. The process of fabricating battery protection packages includes steps of fabricating power control ICs; fabricating common-drain MOSFET wafer; integrating the power control ICs with the common-drain MOSFET wafer and connecting pinouts; forming a packaging layer; applying grinding processes; forming a metal layer; and singulating battery protection packages.

Packaging Devices and Methods of Manufacture Thereof

Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer disposed over the substrate and a first portion of the contact pad, a second portion of the contact pad being exposed. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to the second portion of the contact pad. A PPI pad is disposed over the passivation layer and is coupled to the PPI line. An insulating material is disposed over the PPI line, the PPI pad being exposed. The insulating material is spaced apart from an edge portion of the PPI pad by a predetermined distance. 1. A method of forming a packaging device , the method comprising:forming a contact pad over a substrate;forming a passivation layer over the substrate and a first portion of the contact pad yet leaving a second portion of the contact pad exposed;forming a post passivation interconnect (PPI) line and a PPI pad over the passivation layer, the PPI line being coupled to the second portion of the contact pad, the PPI pad being coupled to the PPI line;depositing a first insulating material over the PPI line, the PPI pad, and the passivation layer; andpatterning the first insulating material to expose the PPI pad, wherein after the patterning, the first insulating material has a first sidewall spaced apart from a second sidewall of the PPI pad by a predetermined distance, the first sidewall of the first insulating material extending below a top surface of the PPI pad.2. The method of further comprising:forming a conductive material on the PPI pad.3. The method of further comprising:depositing a second insulating material over the first insulating material and surrounding at least a lower portion of the conductive material, the second insulating material being interposed between the first sidewall of the first insulating material and the second sidewall ...

Semiconductor device and a method for manufacturing a semiconductor device

According to various embodiments, a semiconductor device may include: at least one first contact pad on a front side of the semiconductor device; at least one second contact pad on the front side of the semiconductor device; a layer stack disposed at least partially over the at least one first contact pad, wherein the at least one second contact pad is at least partially free of the layer stack; wherein the layer stack includes at least an adhesion layer and a metallization layer; and wherein the metallization layer includes a metal alloy and wherein the adhesion layer is disposed between the metallization layer and the at least one first contact pad for adhering the metal alloy of the metallization layer to the at least one first contact pad.

Molded Semiconductor Package Having an Optical Inspection Feature

A molded semiconductor package includes a mold compound having opposing first and second main surfaces and an edge extending between the first and second main surfaces. A semiconductor die is embedded in the mold compound. A plurality of metal pads embedded in the mold compound are electrically connected to the semiconductor die. The metal pads have a bottom face which is uncovered by the mold compound at the second main surface of the mold compound. The metal pads disposed around a periphery of the molded package have a side face which is uncovered by the mold compound at the edge of the mold compound. The faces of the metal pads uncovered by the mold compound are plated. The side face of each metal pad disposed around the periphery of the molded package is recessed inward from the edge of the mold compound. A corresponding manufacturing method is also described. 1. A molded semiconductor package , comprising:a mold compound having a first main surface, a second main surface opposite the main surface, and an edge extending between the first and the second main surfaces;a semiconductor die embedded in the mold compound; anda plurality of metal pads embedded in the mold compound and electrically connected to the semiconductor die,wherein the metal pads have a bottom face which is uncovered by the mold compound at the second main surface of the mold compound,wherein the metal pads disposed around a periphery of the molded package have a side face which is uncovered by the mold compound at the edge of the mold compound,wherein the faces of the metal pads uncovered by the mold compound are plated,wherein the side face of each metal pad disposed around the periphery of the molded package is recessed inward from the edge of the mold compound.2. The molded semiconductor package of claim 1 , wherein the faces of the metal pads uncovered by the mold compound are plated with a layer of nickel-phosphorus or nickel-boron alloy and a layer of gold.3. The molded semiconductor ...

Ag UNDERLAYER- ATTACHED METALLIC MEMBER, Ag UNDERLAYER- ATTACHED INSULATING CIRCUIT SUBSTRATE,SEMICONDUCTOR DEVICE, HEAT SINK- ATTACHED INSULATING CIRCUIT SUBSTRATE, AND METHOD FOR MANUFACTURING Ag UNDERLAYER-ATTACHED METALLIC MEMBER

An Ag underlayer-attached metallic member includes a metallic member joined with a body to be joined and an Ag underlayer formed on a joining surface of the metallic member with the body to be joined, the Ag underlayer includes a glass layer formed on a metallic member side and an Ag layer laminated on the glass layer, and an area proportion of voids in an Ag layer surface of the Ag underlayer is 25% or less.

Bonding structure including metal nano particles and bonding method using metal nano particles

A bonding structure including metal nano particles includes a first member having a metal surface on at least one side, a second member having a metal surface on at least one side, the second member being disposed such that the metal surface of the second member faces the metal surface of the first member, and a bonding material bonding the first member and the second member by sinter-bonding the metal nano particles. At least one of the metal surfaces of the first member and the second member is formed to be a rough surface having a surface roughness within the range from 0.5 μm to 2.0 μm.

CHIP PACKAGE AND FABRICATION METHOD THEREOF

A fabrication method of a chip package includes the following steps. A wafer structure having a wafer and a protection layer is provided. The first opening of the wafer is aligned with and communicated with the second opening of the protection layer. A first insulating layer having a first thickness is formed on a conductive pad exposed from the second opening, and a second insulating layer having a second thickness is formed on a first sidewall of the protection layer surrounding the second opening and a second sidewall of the wafer surrounding the first opening. The first and second insulating layers are etched, such that the first insulating layer is completely removed, and the second thickness of the second insulating layer is reduced. 1. A fabrication method of a chip package comprising:(a) providing a wafer structure that has a wafer and a protection layer, wherein a first opening of the wafer is aligned with and communicated with a second opening of the protection layer;(b) forming a first insulating layer that has a first thickness on a conductive pad exposed through the second opening, and forming a second insulating layer that has a second thickness on a first sidewall of the protection layer surrounding the second opening and a second sidewall of the wafer surrounding the first opening; and(c) etching the first and second insulating layers to completely remove the first insulating layer and reduce the second thickness of the second insulating layer.2. The fabrication method of the chip package of claim 1 , wherein step (c) comprises:laterally etching the second insulating layer on the first sidewall, such that the second insulating layer on the first sidewall has an oblique surface.3. The fabrication method of the chip package of claim 2 , wherein an acute angle is included between the oblique surface of the second insulating layer and the conductive pad.4. The fabrication method of the chip package of claim 2 , wherein step (b) performs a chemical vapor ...

SEMICONDUCTOR PACKAGE HAVING A SUBSTRATE STRUCTURE WITH SELECTIVE SURFACE FINISHES

The present disclosure relates to a semiconductor package having a substrate structure with selective surface finishes, and a process for making the same. The disclosed semiconductor package includes a substrate body, a first metal structure having a first finish area and a second finish area, a second metal structure having a third finish area, a surface finish, and a tuning wire. The first metal structure and the second metal structure are formed over the substrate body. The surface finish is provided over the first finish area of the first metal structure and at least a portion of the third finish area of the second metal structure. The surface finish is not provided over the second finish area of the first metal structure. The tuning wire is coupled between the first finish area and at least one portion of the third finish area. 1. An apparatus comprising:a substrate body having a top surface;a first finished metal structure comprising a first metal structure that is formed over the top surface of the substrate body and has a first finish area and a second finish area, wherein the first finish area is finished with a first surface finish and the second finish area is not finished with the first surface finish;a second finished metal structure comprising a second metal structure that is formed over the top surface of the substrate body and has a third finish area, wherein at least one portion of the third finish area is finished with the first surface finish; anda tuning wire coupled between the first finish area and the at least one portion of the third finish area.2. The apparatus of wherein the first surface finish is electroless nickel electroless palladium immersion gold (ENEPIG).3. The apparatus of wherein the first surface finish comprises:a first layer formed of gold with a thickness between 0.06 μm and 0.14 μm;a second layer formed of palladium with a thickness between 0.08 μm and 0.16 μm; anda third layer formed of nickel with a thickness between 0.3 μm ...

SUBSTRATE STRUCTURE WITH SELECTIVE SURFACE FINISHES FOR FLIP CHIP ASSEMBLY

The present disclosure relates to a substrate structure with selective surface finishes used in flip chip assembly, and a process for making the same. The disclosed substrate structure includes a substrate body, a metal structure with a first finish area and a second finish area, a first surface finish, and a second surface finish. The metal structure is formed on a top surface of the substrate body, the first surface finish is formed over the first finish area of the metal structure, and the second surface finish is formed over the second finish area of the metal structure. The first surface finish is different from the second surface finish. 1. An apparatus comprising:a substrate body;a first metal structure formed on a top surface of the substrate body and having a first finish area and a second finish area;a first surface finish provided over the first finish area; anda second surface finish that is different from the first surface finish and provided over the second finish area.2. The apparatus of wherein the first surface finish is electroless nickel electroless palladium immersion gold (ENEPIG).3. The apparatus of wherein the first surface finish comprises:a first layer formed of gold with a thickness between 0.06 μm and 0.14 μm;a second layer formed of palladium with a thickness between 0.08 μm and 0.16 μm; anda third layer formed of nickel with a thickness between 0.3 μm and 0.5 μm, wherein the third layer is over the first finish area, the second layer is over the third layer, and the first layer is over the second layer.4. The apparatus of wherein the first surface finish is bussless NiAu or electroless palladium immersion gold (EPIG).5. The apparatus of wherein the second surface finish is an organic surface protectorant (OSP).6. The apparatus of wherein a thickness of the second surface finish is between 0.2 μm and 0.4 μm.7. The apparatus of wherein the first surface finish comprises gold and the second surface finish does not comprise gold.8. The ...

SEMICONDUCTOR DEVICE

A semiconductor device includes a semiconductor substrate and a metal film formed on the semiconductor substrate. The metal film includes a Ni base and a material having condensation energy higher than that of Ni. In a method of manufacturing a semiconductor device, a semiconductor substrate and a target, which is formed by melting P in Ni, are prepared, and sputtering is performed with the target while a portion of the semiconductor substrate where the metal film is to be formed is heated to a temperature of from 280° C. inclusive to 870° C. inclusive. 1. A semiconductor device comprising:a semiconductor substrate; anda metal film formed on the semiconductor substrate, whereinthe metal film includes a Ni base and a material having condensation energy higher than that of Ni.2. The semiconductor device according to claim 1 , whereinthe material having condensation energy higher than that of Ni is any of Sc, Ti, V, Cr, Fe, Co, Zr, Nb, Mo, Hf, Ta, W, B, and P.3. The semiconductor device according to claim 1 , wherein{'sub': x', 'y, 'the material having condensation energy higher than that of Ni is a stoichiometric material represented by NiP, where each of x and y is an integer.'}4. The semiconductor device according to claim 1 , wherein{'sub': '3', 'the material having condensation energy higher than that of Ni is a NiP particle.'}5. The semiconductor device according to claim 4 , wherein{'sub': '3', 'the NiP particle is uniformly distributed in the Ni base.'}6. The semiconductor device according to claim 1 , further comprising:another metal film made of Al or Cu and located between the semiconductor substrate and the metal film, the other metal film being in contact with the metal film.7. The semiconductor device according to claim 1 , further comprising:another metal film made of Ti and located between the semiconductor substrate and the metal film, the other metal film being in contact with the metal film.8. The semiconductor device according to claim 1 , further ...

FABRICATION METHOD OF PACKAGING SUBSTRATE

A packaging substrate and a semiconductor package using the packaging substrate are provided. The packaging substrate includes: a substrate body having a die attach area, a circuit layer formed around the die attach area and having a plurality of conductive traces each having a wire bonding pad, and a surface treatment layer formed on the wire bonding pads. Therein, only one of the conductive traces is connected to an electroplating line so as to prevent cross-talk that otherwise occurs between conductive traces due to too many electroplating lines in the prior art. 114-. (canceled)15. A fabrication method of a packaging substrate , comprising the steps of:providing a substrate body having a die attach area and a circuit layer formed around the die attach area, wherein the circuit layer has a plurality of conductive traces each having a first end positioned adjacent to the die attach area and an apposing second end positioned away from the die attach area, each of the first ends has a wire bonding pad, the second end of at least one of the conductive traces at at least one side of the die attach area is connected to an electroplating line, and the electroplating lines and the wire bonding pads at the same side of the die attach area are different in number;forming a conductive layer at an edge of the die attach area between the die attach area and the circuit layer, and electrically connecting the conductive layer to the conductive traces;performing an electroplating process through the conductive layer and the electroplating line so as to form a surface treatment layer on the wire bonding pads; andremoving the conductive layer.16. The package of claim 15 , wherein each of the wire bonding pads is connected to an extending line so as to be connected to the conductive layer.17. The method of claim 15 , wherein the conductive layer is removed by laser claim 15 , a chemical solution or a scraper.18. The method of claim 15 , further comprising forming an adhesive layer ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A flip-chip mounting technique with high reliability is provided in flip-chip mounting using a Cu pillar. In a semiconductor device to be coupled to a mounting board via a Cu pillar, the Cu pillar is caused to have a laminated structure including a pillar layer, a barrier layer, and a bump in this order from below, and the bump is formed to be smaller than the barrier layer. 1. A manufacturing method of a semiconductor device , comprising the steps of:(a) applying a resist film over a terminal pad formed over a main surface of a semiconductor substrate;(b) forming an opening in the resist film for exposing the terminal pad in the bottom thereof;(c) forming a Cu film, an Ni film, and an SnAg film in the opening in this order from below;(d) removing the resist film; and(e) etching an outer peripheries of the SnAg film.2. The manufacturing method of a semiconductor device according to claim 1 ,wherein, in the step (e), the etching is performed by using dilute hydrofluoric acid.3. The manufacturing method of a semiconductor device according to claim 1 ,wherein, in the step (b), the forming the opening is performed by using photolithography.4. The manufacturing method of a semiconductor device according to claim 1 ,wherein, in the step (c), the Cu film, the Ni film, and the SnAg film are formed by electrolytic plating.5. The manufacturing method of a semiconductor device according to claim 1 ,wherein, in the step (d), the resist film is removed by ashing.6. The manufacturing method of a semiconductor device according to claim 1 ,wherein, in the step (e), the outer peripheries of the SnAg film is wet etched.7. A manufacturing method of a semiconductor device claim 1 , comprising the steps of:(a) applying a first resist film over a terminal pad formed over a main surface of a semiconductor substrate;(b) forming a first opening in the first resist film for exposing the terminal pad in the bottom thereof;(c) forming a Cu film and an Ni film in this order from below;(d) ...

Package-On-Package (PoP) Structure Including Stud Bulbs

Embodiments concern Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures. According to an embodiment, a structure includes a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs. 1. A device comprising:a first pad on a first surface of a first substrate;a second pad on a second surface of a second substrate;a metallic element interposed between the first pad and the second pad, the metallic element electrically coupled to the first pad, the metallic element comprising a base portion and an elongated portion extending from the base portion toward the second pad;a solder connector in contact with the elongated portion and electrically coupled to the second pad; andan inter-metallic compound (IMC) between the elongated portion and the solder connector.2. The device of claim 1 , further comprising a protection layer extending over the base portion and the elongated portion.3. The device of claim 1 , further comprising a die attached to the first substrate adjacent the metallic element.4. The device of claim 3 , wherein a height of the metallic element from the first substrate is greater than a height of the die from the first substrate.5. The device of claim 1 , wherein the metallic element comprises a copper wire.6. The device of claim 1 , wherein the base portion and the elongated portion comprises a single continuous element.7. A device comprising:a first substrate having a first pad;a second substrate having a second pad;a first connector interposed between the first pad and the second pad, the first connector having a first wide portion and a second elongated portion, the first wide portion being ...

A-staged Thermoplastic-Polyimide (TPI) Adhesive Compound Containing Flat Inorganic Particle Fillers and Method of Use

A compound and method of use thereof consisting of an A-staged thermoplastic-polyimide (TPI) adhesive, a viscous uncured liquid of polyamic-acid polymer (PAA), the TPI precursor, synthesized and dissolved in a polar aprotic organic solvent, and including, as appropriate, combinations of flat particulate inorganic ceramic and/or metallic electrically insulating, and/or electrically conducting, and/or thermally conducting fillers for interface-bonding to create a robust joint between surfaces with conventional lamination processes that utilize relatively moderate temperatures and applied pressures, such particles resulting in the reduction of the occurrence and size of gas voids within the adhesive bondline. 1. The process of reducing the occurrence and size of gas voids in a bondline formed by the thermoplastic polyimide adhesive interface bonding of two surfaces , said process comprising in combination: 1. a quantity of polar aprotic organic solvent;', '2. a quantity of TPI precursor polyamic-acid polymer (PAA) synthesized and dissolved in said solvent wherein said polyamic-acid polymer comprises a mixture of diamine and dianhydride monomers, said monomers selected, in combination, to result in a thermoplastic polyimide having the characteristic of being insoluble in an organic solvent in the fully imidized, fully cured state, and', '3. a quantity of flat particulate filler; said filler comprising an inorganic material having a particle size of between 0.1 and 2.0 um in thickness, and 1.0 and 20.0 um in width and wherein the width of said particles is greater than the thickness;, 'A. providing an adhesive solution consisting of an A-staged uncured thermoplastic-polyimide (TPI) solution, said thermoplastic polyimide having the characteristic of being insoluble in an organic solvent in the fully imidized, fully cured state, in the form of a viscous liquid solution containing in combinationB. applying said uncured solution to at least one of said surfaces;C. applying ...

Method of fabricating a semiconductor device

A semiconductor device and a semiconductor package, the device including a first buffer dielectric layer on a first dielectric layer; a second dielectric layer and a second buffer dielectric layer sequentially disposed on the first buffer dielectric layer, the second buffer dielectric layer being in contact with the first buffer dielectric layer; and a pad interconnection structure that penetrates the first buffer dielectric layer and the second buffer dielectric layer, wherein the pad interconnection structure includes copper and tin.

INTEGRATED CIRCUIT INCLUDING WIRE STRUCTURE AND RELATED METHOD

An integrated circuit (IC), design structure, and a method of making the same. In one embodiment, the IC includes: a substrate; a dielectric layer disposed on the substrate; a set of wire components disposed on the dielectric layer, the set of wire components including a first wire component disposed proximate a second wire component; a bond pad disposed on the first wire component, the bond pad including an exposed portion; a passivation layer disposed on the dielectric layer about a portion of the bond pad and the set of wire components, the passivation layer defining a wire structure via connected to the second wire component; and a wire structure disposed on the passivation layer proximate the bond pad and connected to the second wire component through the wire structure via. 1. A method , comprising:forming a dielectric layer on a substrate;forming a metal layer on the dielectric layer;forming a set of wire components from the metal layer, the set of wire components including a first wire component proximate a second wire component;depositing a bond pad on the first wire component;forming a passivation layer on the dielectric layer and about portions of the set of wire components, the passivation layer including a wire component via connected to the second wire component; andforming a wire structure above the second wire component and physically isolated from the bond pad.2. The method of claim 1 , wherein the forming the wire structure includes patterned plating of copper on at least one of the dielectric layer and the set of wire components.3. The method of claim 1 , further comprising forming a diffusion barrier on at least one of the set of wire components following the forming of the passivation layer.4. The method of claim 3 , wherein the diffusion barrier is self-aligning.5. The method of claim 1 , further comprising:depositing a pattern resist on the bond pad following the depositing of the bond pad, the pattern resist configured to prevent formation of ...

Hybrid Bonding Systems and Methods for Semiconductor Wafers

Hybrid bonding systems and methods for semiconductor wafers are disclosed. In one embodiment, a hybrid bonding system for semiconductor wafers includes a chamber and a plurality of sub-chambers disposed within the chamber. A robotics handler is disposed within the chamber that is adapted to move a plurality of semiconductor wafers within the chamber between the plurality of sub-chambers. The plurality of sub-chambers includes a first sub-chamber adapted to remove a protection layer from the plurality of semiconductor wafers, and a second sub-chamber adapted to activate top surfaces of the plurality of semiconductor wafers prior to hybrid bonding the plurality of semiconductor wafers together. The plurality of sub-chambers also includes a third sub-chamber adapted to align the plurality of semiconductor wafers and hybrid bond the plurality of semiconductor wafers together. 1. A method comprising:depositing a first protection layer on a first bonding surface of a first semiconductor wafer;removing the first protection layer from the first bonding surface of the first semiconductor wafer to expose the first bonding surface of the first semiconductor wafer;applying a plasma process to the first bonding surface of the first semiconductor wafer;performing a cleaning process on the first bonding surface of the first semiconductor wafer;coupling the first semiconductor wafer to a second semiconductor wafer; andannealing the first semiconductor wafer and the second semiconductor wafer to bond the first bonding surface of the first semiconductor wafer to a second bonding surface of the second semiconductor wafer, wherein bonding the first bonding surface of the first semiconductor wafer to the second bonding surface of the second semiconductor wafer comprises:forming a first bond between a first insulating layer of the first bonding surface and a second insulating layer of the second bonding surface; andforming a second bond between a first conductive pad of the first bonding ...

Semiconductor package with air gap

The present application provides a semiconductor package with air gaps for reducing capacitive coupling between conductive features and a method for manufacturing the semiconductor package. The semiconductor package includes a first semiconductor structure and a second semiconductor structure bonded with the first semiconductor structure. The first semiconductor structure has a first bonding surface. The second semiconductor structure has a second bonding surface partially in contact with the first bonding surface. A portion of the first bonding surface is separated from a portion of the second bonding surface, a space between the portions of the first and second bonding surfaces is sealed and forms an air gap in the semiconductor package.

SEMICONDUCTOR DEVICE

A semiconductor device includes a substrate, a dielectric layer, a plurality of dielectric patterns and a conductive pad. The substrate includes a first surface and a second surface opposite to the first surface. The dielectric layer is disposed at the first surface of the substrate, and the substrate is disposed between the dielectric layer and the second surface of the substrate. The dielectric patterns are disposed on the dielectric layer and between the first surface and the second surface of the substrate. The conductive pad is inserted between the plurality of dielectric patterns and extended into the dielectric layer. 1. A semiconductor device , comprising:a substrate comprising a first surface and a second surface opposite to the first surface;a dielectric layer at the first surface of the substrate, the substrate being disposed between the dielectric layer and the second surface of the substrate;{'b': ['116', '132', '110', '110', '110'], 'i': ['a', 'b'], '#text': 'a plurality of dielectric patterns () on the dielectric layer () and between the first surface () and the second surface () of the substrate (); and'}{'b': ['152', '116', '132'], '#text': 'a conductive pad (), inserted between the plurality of dielectric patterns () and extended into the dielectric layer ().'}2. The semiconductor device of claim 1 , wherein an interface between the dielectric layer and the plurality of dielectric patterns is substantially coplanar with the first surface of the substrate.3. The semiconductor device of claim 1 , wherein the plurality of dielectric patterns are separated from the substrate by a lateral distance.4. The semiconductor device of claim 1 , wherein the substrate comprises a first portion and a second portion separated from each other claim 1 , and the plurality of dielectric patterns are disposed between the first portion and the second portion.5. The semiconductor device of further comprising a dummy pattern between the plurality of dielectric patterns ...

MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICES

A manufacturing method for semiconductor devices includes the steps of forming an Ni/Au film that includes an Ni film and an Au film formed over the Ni film over a wiring that is coupled to each of a plurality of electrode pads formed over a principal surface of a semiconductor wafer and arranges each of the electrode pads at a different position, grinding a back surface of the semiconductor wafer, performing reduction treatment on a surface of the Ni/Au film, and forming a solder bump over the Ni/Au film. In the reduction treatment, respective processes of flux application, reflow soldering and cleaning are performed and the solder bump is bonded to the Ni/Au film after the reduction treatment has been completed. Thereby, bonding reliability in flip chip bonding of a semiconductor device is improved. 1. A manufacturing method for semiconductor devices , comprising the steps of:(a) forming an Ni/Au film that includes an Ni film and an Au film formed over the Ni film over a wiring that is coupled to each of a plurality of electrode pads formed over a principal surface of a semiconductor wafer and arranges each of the electrode pads at a different position;(b) after the step (a), performing reduction treatment on a surface of the Ni/Au film; and(c) after the step (b), forming a solder bump over the Ni/Au film.2. The manufacturing method for semiconductor devices according to claim 1 ,wherein the reduction treatment includes the steps of,(b1) applying a flux constituent material,(b2) after the step (b1), performing reflow soldering, and(b3) after the step (b2), performing cleaning.3. The manufacturing method for semiconductor devices according to claim 2 ,wherein as the flux constituent material, a material that is the same as that of a flux material that is applied to the Au film after the reduction treatment has been performed and before the solder bump is formed.4. The manufacturing method for semiconductor devices according to claim 2 ,wherein before the solder ...

PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

A package structure includes a substrate, a patterned solder resist layer, a plurality of solders, a chip and a polymer gel. The substrate includes a plurality of solder pads. The patterned solder resist layer is disposed on the substrate and includes a plurality of stepped openings. The stepped openings expose the solder pads respectively. The solders are disposed on the solder pads and located in the stepped openings respectively. The chip is disposed on the substrate and includes an active surface and a plurality of bond pads. The bond pads are disposed on the active surface and connected to the solder pads by the solders. The polymer gel fills between a top surface of the patterned solder resist layer and the active surface. The polymer gel at least surrounds a disposing region of the solders and fills between two adjacent solders. 1. A manufacturing method of a package structure , comprising:providing a substrate, wherein the substrate comprises a plurality of solder pads;forming a patterned solder resist layer on the substrate, wherein the patterned solder resist layer comprises a plurality of stepped openings exposing the solder pads respectively;disposing a polymer gel on a top surface of the patterned solder resist layer, wherein the polymer gel at least surrounds a disposing region of the solder pads and disposed between adjacent two of the solder pads;disposing a plurality of solders on the solder pads respectively, wherein the solders are located in the stepped openings respectively;disposing a chip on the substrate, wherein the chip comprises an active surface and a plurality of bond pads located on the active surface and the bond pads are connected to the solder pads through the solders; andperforming a reflow process on the solders, such that the polymer gel is filled between a top surface of the patterned solder resist layer and the active surface.2. The manufacturing method of a package structure as claimed in claim 1 , wherein the step of forming ...

METHOD OF FORMING A SOLDER BUMP STRUCTURE

A solder bump structure includes a pillar formed on an electrode pad. The pillar has a concave curve-shaped surface and a geometry defined at least in part by dimensions including a first height greater than a first width. The solder bump structure further includes solder formed on the concave curve-shaped surface of the pillar. The solder has a convex top surface and having dimensions including a second height greater than a second width due to the geometry of the pillar. 1. A solder bump structure comprising:a pillar formed on an electrode pad, the pillar having a concave curve-shaped surface and a geometry defined at least in part by dimensions including a first height greater than a first width; andsolder formed on the concave curve-shaped surface of the pillar, the solder having a convex top surface and having dimensions including a second height greater than a second width due to the geometry of the pillar.2. The solder bump structure according to claim 1 , wherein the solder is in contact with an entirety of the curve-shaped surface of the pillar.3. The solder bump structure according to claim 1 , wherein the pillar includes at least one material selected from the group consisting of: copper claim 1 , nickel claim 1 , silver and gold.4. The solder bump structure according to claim 1 , wherein a thickness of a central portion of the pillar is in a range of ⅕ to ⅔ of a length from a surface of the electrode pad to the convex top surface of the solder.5. The solder bump structure according to claim 4 , wherein the electrode pad includes aluminum.6. The solder bump structure according to claim 1 , wherein a thickness of a central portion of the pillar is in a range of 1 to 50 micrometers.7. The solder bump structure according to claim 1 , wherein the solder has a non-spherical shape.8. A solder bump structure comprising:a resist layer including an opening;a pillar formed on an electrode pad and in the opening of the resist layer, the pillar having a concave curve ...

Semiconductor device

A semiconductor device suitable for preventing malfunction is provided. The semiconductor device includes a semiconductor chip 1 , a first electrode pad 21 laminated on the semiconductor chip 1 , an intermediate layer 4 having a rectangular shape defined by first edges 49 a and second edges, and a plurality of bumps 5 arranged to sandwich the intermediate layer 4 by cooperating with the semiconductor chip 1 . The first edges 49 a extend in the direction x, whereas the second edges extend in the direction y. The plurality of bumps 5 include a first bump 51 electrically connected to the first electrode pad 21 and a second bump 52 electrically connected to the first electrode pad 21 . The first bump 51 is arranged at one end in the direction x and one end in the direction y.

SEMICONDUCTOR PACKAGING AND MANUFACTURING METHOD THEREOF

The present disclosure provides a semiconductor package, which includes a substrate, a passivation layer, a post-passivation interconnect (PPI) having a top surface; and a conductive structure. The top surface of the PPI includes a first region receiving the conductive structure, and a second region surrounding the first region. The second region includes metal derivative transformed from materials made of the first region. The present disclosure provide a method of manufacturing a semiconductor package, including forming a first flux layer covering a portion of a top surface of a PPI; transforming a portion of the top surface of the PPI uncovered by the first flux layer into a metal derivative layer; removing the first flux layer; forming a second flux layer on the first region of the PPI; dropping a solder ball on the flux layer; and forming electrical connection between the solder ball and the PPI. 1. A method of manufacturing a semiconductor package , comprising:patterning a metal derivative in a second region of a post-passivation interconnect (PPI);forming a flux layer in a first region of the PPI, wherein the first region is surrounded by the second region;dropping a solder ball on the flux layer; andforming electrical connection between the solder ball and the PPI.2. The method of manufacturing a semiconductor package in claim 1 , wherein the to patterning the metal derivative in the second region of the PPI further comprising forming a mask layer over the PPI.3. The method of manufacturing a semiconductor package in claim 2 , wherein the forming the mask layer over the PPI comprises forming a mask layer on the PPI.4. The method of manufacturing a semiconductor package in claim 2 , wherein the forming the mask layer over the PPI comprises positioning a first stencil plate over the PPI.5. The method of manufacturing a semiconductor package in claim 1 , wherein the patterning the metal derivative in the second region of the PPI comprises an oxygen plasma ...

TEXTURED BOND PADS

In some examples, a package comprises a semiconductor die and a bond pad formed upon the semiconductor die. The bond pad has a protrusion on a top surface of the bond pad. The package also comprises a metal contact and a bond wire coupled to the protrusion and to the metal contact. 1. A package , comprising:a semiconductor die;a bond pad formed upon the semiconductor die, the bond pad having a protrusion on a top surface of the bond pad;a metal contact; anda bond wire coupled to the protrusion and to the metal contact.2. The package of claim 1 , wherein the protrusion comprises a rectangular prism.3. The package of claim 1 , wherein the bond pad has multiple protrusions on the top surface of the bond pad.4. The package of claim 3 , wherein a first protrusion of the multiple protrusions is positioned on top of a second protrusion of the multiple protrusions.5. The package of claim 1 , wherein the protrusion comprises a triangular prism.6. The package of claim 1 , wherein the protrusion is spherical.7. The package of claim 1 , wherein the protrusion has a thickness of between 0.01 microns and 0.1 microns claim 1 , inclusive.8. The package of claim 1 , wherein the protrusion occupies less than 50% of the top surface.9. The package of claim 1 , wherein the bond pad comprises:a first metal layer;a second metal layer on the first metal layer; anda third metal layer on the second metal layer, the third metal layer having the top surface having the protrusion;10. The package of claim 9 , wherein the first metal layer comprises copper claim 9 , the second metal layer comprises nickel claim 9 , and the third metal layer comprises palladium.11. The package of claim 1 , wherein the protrusion is part of a textured surface on the top surface.12. The package of claim 11 , wherein the bond pad comprises multiple metal layers.13. The package of claim 12 , wherein the multiple metal layers include a copper layer claim 12 , a palladium layer claim 12 , and a nickel layer positioned ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device is provided and includes first and second semiconductor chips bonded together. The first chip includes a first substrate, a first insulating layer disposed on the first substrate and having a top surface, a first metal pad embedded in the first insulating layer and having a top surface substantially planar with the top surface of the first insulating layer, and a first barrier disposed between the first insulating layer and the first metal pad. The second chip includes a second substrate, a second insulating layer, a second metal pad, and a second barrier with a similar configuration to the first chip. The top surfaces of the first and second insulating layers are bonded to provide a bonding interface, the first and second metal pads are connected, and a portion of the first insulating layer is in contact with a side region of the first metal pad. 1. A semiconductor device comprising:a first semiconductor chip; anda second semiconductor chip disposed on the first semiconductor chip, a first substrate;', 'a first insulating layer disposed on the first substrate and having a top surface;', 'a first metal pad embedded in the first insulating layer and having a top surface substantially planar with the top surface of the first insulating layer; and', 'a first barrier disposed between the first insulating layer and the first metal pad,, 'wherein the first semiconductor chip includes a second substrate;', 'a second insulating layer disposed below the second substrate and having a top surface;', 'a second metal pad embedded in the second insulating layer and having a top surface substantially planar with the top surface of the second insulating layer; and', 'a second barrier disposed between the second insulating layer and the second metal pad, and, 'wherein the second semiconductor chip includeswherein the top surfaces of the first insulating layer and the second insulating layer are bonded to provide a bonding interface,the first metal pad and the ...

BONDING PAD STRUCTURE, SEMICONDUCTOR STRUCTURE, SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR PREPARING SAME

A bonding pad structure includes a bonding pad layer, and an expansion stagnating block that is at least wrapped by the bonding pad layer partially. The expansion stagnating block is subjected to high-temperature tempering treatment. A semiconductor structure, a semiconductor package structure and a method for preparing the same are also provided. 1. A bonding pad structure , comprising a bonding pad layer , and an expansion stagnating block that is at least wrapped by the bonding pad layer partially , the expansion stagnating block being subjected to A high-temperature tempering treatment.2. The bonding pad structure of claim 1 , wherein an isolation layer is arranged between the bonding pad layer and the expansion stagnating block.3. The bonding pad structure of claim 1 , wherein the bonding pad layer comprises a bonding pad top layer and a bonding pad bottom layer that are arranged in a stacked manner claim 1 , the bonding pad top layer is arranged on a side of a bonding pad close to a bonding surface claim 1 , the bonding pad bottom layer and the bonding pad top layer are integrated as a whole claim 1 , and projection of the bonding pad bottom layer on the bonding surface is positioned in projection of the bonding pad top layer on the bonding surface.4. The bonding pad structure of claim 3 , wherein an area of an end of the bonding pad layer close to the bonding surface is greater than an area of an end of the bonding pad layer far away from the bonding surface.5. The bonding pad structure of claim 1 , wherein the bonding pad layer is a metal block.6. A semiconductor package structure comprising a semiconductor substrate provided with the bonding pad structure of .7. The semiconductor package structure of claim 6 , wherein the semiconductor substrate comprises a substrate layer far away from a bonding surface claim 6 , and a dielectric layer and a dielectric surface layer that are arranged on the substrate layer sequentially claim 6 , the bonding pad structure ...

Semiconductor device with slanted conductive layers and method for fabricating the same

The present application discloses a semiconductor device with slanted conductive layers and a method for fabricating the semiconductor device with the slanted conductive layers. The semiconductor device includes a substrate, a first insulating layer positioned above the substrate, first slanted conductive layers positioned in the first insulating layer, and a top conductive layer positioned covering the first slanted conductive layers.

Conductive Pad Structure for Hybrid Bonding and Methods of Forming Same

A representative device includes a patterned opening through a layer at a surface of a device die. A liner is disposed on sidewalls of the opening and the device die is patterned to extend the opening further into the device die. After patterning, the liner is removed. A conductive pad is formed in the device die by filling the opening with a conductive material. 1. A device comprising:a first substrate;a first redistribution structure over the first substrate;a first dielectric layer over the first redistribution structure; and a first portion extending through the first dielectric layer, the first portion having a first width; and', 'a second portion extending through the first redistribution structure, the second portion having a second width, the second width being different from the first width., 'a first conductive pad extending through the first dielectric layer and the first redistribution structure, a bottommost surface of the first conductive pad being below a bottommost surface of the first redistribution structure, wherein the first conductive pad comprises2. The device of claim 1 , wherein the second width is less than the first width.3. The device of claim 1 , further comprising:a second substrate;a second redistribution structure interposed between the second substrate and the first dielectric layer;a second dielectric layer interposed between the second redistribution structure and the first dielectric layer, the second dielectric layer being in physical contact with first dielectric layer; anda second conductive pad extending through the second dielectric layer and the second redistribution structure, the second conductive pad being in physical contact with the first conductive pad.4. The device of claim 3 , wherein a topmost surface of the second conductive pad is above a topmost surface of the second redistribution structure.5. The device of claim 3 , wherein the second conductive pad comprises:a third portion extending through the second ...

Package with ubm and methods of forming

Package structures and methods of forming package structures are discussed. A package structure, in accordance with some embodiments, includes an integrated circuit die, an encapsulant at least laterally encapsulating the integrated circuit die, a redistribution structure on the integrated circuit die and the encapsulant, a connector support metallization coupled to the redistribution structure, a dummy pattern, a second dielectric layer, and an external connector on the connector support metallization. The redistribution structure comprises a first dielectric layer having a first surface disposed distally from the encapsulant and the integrated circuit die. The dummy pattern is on the first surface of the first dielectric layer and around the connector support metallization. The second dielectric layer is on the first surface of the first dielectric layer and on at least a portion of the dummy pattern. The second dielectric layer does not contact the connector support metallization.

Metal Routing Architecture for Integrated Circuits

A device includes a substrate, a metal pad over the substrate, and a metal trace electrically disconnected from the metal pad. The metal pad and the metal trace are level with each other. A passivation layer includes a portion overlapping an edge portion of the metal pad. A metal pillar is overlying the metal pad, and is electrically connected to the metal pad. The metal trace has a portion overlapped by the metal pillar.

MASKLESS SELECTIVE RETENTION OF A CAP UPON A CONDUCTOR FROM A NONCONDUCTIVE CAPPING LAYER

A semiconductor structure includes an electrically conductive structure formed upon an uppermost organic layer of a semiconductor substrate. A capping layer is formed upon the uppermost organic layer covering the electrically conductive structure. A maskless selective removal lasering technique ejects portions of the capping layer while retaining the portion of the capping layer covering the electrically conductive structure. Portions of the capping layer are ejected from the uppermost organic layer by a shockwave as a result of the laser beam vaporizing the uppermost organic layer of the semiconductor substrate. Portions of the capping layer contacting the electrically conductive structure are retained by the conductive structure dissipating heat from the laser that would otherwise vaporize the uppermost organic layer of the semiconductor substrate. 1. A method to form a cap upon a semiconductor chip to package interconnect contact structure comprising:forming a contact structure upon an uppermost organic layer of a semiconductor substrate;forming a capping layer upon the uppermost organic layer covering the contact structure, and;directing a laser beam to eject portions of the capping layer from the uppermost organic layer and form a cap by retaining the capping layer covering the electrically conductive structure.2. The method of claim 1 , wherein portions of the capping layer are ejected from the uppermost organic layer by a shockwave as a result of the laser beam vaporizing the uppermost organic layer of the semiconductor substrate.3. The method of claim 1 , wherein the capping layer is formed from silicon nitride.4. The method of claim 1 , wherein the capping layer covering the contact structure is retained by the contact structure dissipating heat from the laser that would otherwise vaporize the uppermost organic layer of the semiconductor substrate.5. The method of claim 1 , further comprising:removing particulate of the ejected portions of the capping layer ...

METHOD OF MANUFACTURING WAFER LEVEL LOW MELTING TEMPERATURE INTERCONNECTIONS

A method of manufacturing a wafer assembly includes forming an array of planar wafer level metal posts extending from a surface of a substrate of a first wafer. After forming the array of posts, an oxide layer is applied over the surface of the first wafer and around the array of posts, the oxide layer being applied at a temperature of below 150 degrees Celsius. 1. A method of manufacturing an array of planar wafer level metal posts comprising:plating an array of posts within a photoresist (PR) pattern mold on a substrate of a first wafer;stripping the PR pattern mold from the substrate and array of posts;applying an oxide layer, at a temperature of below 150 degrees Celsius, over a surface of the first wafer and around the array of posts extending from the surface; andapplying chemical-mechanical polishing (CMP) to planarize the oxide layer and the array of posts.2. The method of further comprising claim 1 , after the step of stripping the pattern mold claim 1 , applying a PR layer around each of the posts.3. The method of further comprising claim 2 , after the step of applying a PR layer claim 2 , etching a metal seed layer on the substrate to singulate the array of posts.4. The method of further comprising claim 3 , after the step of etching a metal seed layer claim 3 , stripping the PR layer.5. The method of further comprising claim 2 , after the step of applying CMP claim 2 , protecting exposed surfaces of the array of posts with a second PR layer.6. The method of further comprising claim 5 , after the step of protecting exposed surfaces of the array of posts claim 5 , cleaning a surface of the oxide layer.7. The method of wherein claim 6 , in the step of cleaning a surface of the oxide layer claim 6 , the surface is cleaned by applying HCl.8. The method of wherein claim 1 , in the step of applying an oxide layer claim 1 , the oxide layer is applied at a temperature of between 127 degrees Celsius and 147 degrees Celsius.9. The method of wherein claim 1 , in the ...

FABRICATION OF SOLDER BALLS WITH INJECTION MOLDED SOLDER

Wafers include a contact pad on a surface of a bulk redistribution layer. A final redistribution layer is formed on the surface and in contact with the contact pad. Solder is formed on the contact pad. The solder includes a pedestal portion formed to a same height as the final redistribution layer and a ball portion above the pedestal portion. 1. A wafer , comprising:a contact pad on a surface of a bulk redistribution layer;a final redistribution layer formed on the surface and in contact with the contact pad; andsolder formed on the contact pad, comprising a pedestal portion formed to a same height as the final redistribution layer and a ball portion above the pedestal portion.2. The wafer of claim 1 , wherein the final redistribution layer is formed from a material selected from the group consisting of a photosensitive phenolic resin and a polymide material.3. The wafer of claim 1 , wherein the wafer comprises a plurality of contact pads on the surface and solder formed on respective contact pads.4. The wafer of claim 1 , wherein the final redistribution layer comprises a hole formed directly over the contact pads.5. The wafer of claim 1 , wherein a top surface of the final redistribution layer has a height that is lower than a height of a top of the solder.6. The wafer of claim 1 , wherein a top surface of the final redistribution layer has a height that is greater than a height of a top surface of the contact pad.7. The wafer of claim 1 , wherein the bulk redistribution layers is formed from one or more of the materials selected from the group consisting of a polymide material claim 1 , a polybenzoxazole material claim 1 , and a benocyclobutane material.8. The wafer of claim 1 , wherein the solder has a composition of about 0.5% copper claim 1 , about 96.5% tin claim 1 , and about 3% silver.9. The wafer of claim 1 , wherein the solder has a diameter of about 90 μm.10. The wafer of claim 1 , wherein the ball portion of the solder extends laterally above the final ...

Stacked Semiconductor Structure and Method

A device comprises a first chip comprising a first connection pad embedded in a first dielectric layer and a first bonding pad embedded in the first dielectric layer, wherein the first bonding pad comprises a first portion and a second portion, the second portion being in contact with the first connection pad and a second chip comprising a second bonding pad embedded in a second dielectric layer of the second chip, wherein the first chip and the second chip are face-to-face bonded together through the first bonding pad the second bonding pad. 1. A device comprising: a first connection pad embedded in a first dielectric layer;', 'a first connector embedded in the first dielectric layer, the first connector directly contacting the first connection pad; and', 'a first bonding pad embedded in the first dielectric layer, the first connector being interposed between first bonding pad and the first connection pad; and, 'a first chip comprising a semiconductor substrate', 'an interconnect structure interposed between the semiconductor substrate and the first chip;', 'an external connection pad directly on the interconnect structure, the interconnect structure being interposed between the external connection pad and the first chip;', 'a second dielectric layer interposed between the interconnect structure the first chip, the second dielectric layer being directly bonded to the first dielectric layer; and', 'a second bonding pad embedded in the second dielectric layer of the second chip, wherein the first chip and the second chip are face-to-face bonded together through the first bonding pad the second bonding pad., 'a second chip bonded to the first chip, the second chip comprising2. The device of claim 1 , wherein a width of the first connector is less than a width of the first bonding pad and a width of the first connection pad.3. The device of claim 2 , wherein a width of the first bonding pad is less than a width of the second bonding pad.4. The device of claim 1 , ...

Flat metal features for microelectronics applications

Advanced flat metals for microelectronics are provided. While conventional processes create large damascene features that have a dishing defect that causes failure in bonded devices, example systems and methods described herein create large damascene features that are planar. In an implementation, an annealing process creates large grains or large metallic crystals of copper in large damascene cavities, while a thinner layer of copper over the field of a substrate anneals into smaller grains of copper. The large grains of copper in the damascene cavities resist dishing defects during chemical-mechanical planarization (CMP), resulting in very flat damascene features. In an implementation, layers of resist and layers of a second coating material may be applied in various ways to resist dishing during chemical-mechanical planarization (CMP), resulting in very flat damascene features.

Chip package, method of forming a chip package and method of forming an electrical contact

In various embodiments, a method of forming an electrical contact is provided. The method may include depositing, by atomic layer deposition, a passivation layer over at least a region of a metal surface, wherein the passivation layer may include aluminum oxide, and electrically contacting the region of the metal surface with a metal contact structure, wherein the metal contact structure may include copper.

MASKLESS SELECTIVE RETENTION OF A CAP UPON A CONDUCTOR FROM A NONCONDUCTIVE CAPPING LAYER

A semiconductor structure includes an electrically conductive structure formed upon an uppermost organic layer of a semiconductor substrate. A capping layer is formed upon the uppermost organic layer covering the electrically conductive structure. A maskless selective removal lasering technique ejects portions of the capping layer while retaining the portion of the capping layer covering the electrically conductive structure. Portions of the capping layer are ejected from the uppermost organic layer by a shockwave as a result of the laser beam vaporizing the uppermost organic layer of the semiconductor substrate. Portions of the capping layer contacting the electrically conductive structure are retained by the conductive structure dissipating heat from the laser that would otherwise vaporize the uppermost organic layer of the semiconductor substrate. 1. A semiconductor structure comprising:a substrate comprising an uppermost organic layer;a plurality of conductive structures upon the uppermost organic layer; anda cap covering each of the plurality of conductive structures,wherein the uppermost organic layer top surface comprises a laser stich mark crevasse between the plurality of conductive structures.2. The semiconductor structure of wherein the laser stich mark crevasse is a resultant of the laser beam vaporizing the uppermost organic layer to selectively eject portions of a capping layer upon the uppermost organic layer to form the cap covering each of the plurality of conductive structures.3. The semiconductor structure of claim 1 , wherein residual capping layer material is comprised within the stich mark crevasse.4. The semiconductor structure of claim 2 , wherein portions of the capping layer are ejected from the uppermost organic layer by a shockwave.519. The semiconductor structure of claim claim 2 , wherein the conductive structures dissipates heat from the laser that would otherwise vaporize the capping layer upon the conductive structures.6. The ...

Method for producing structure, and structure

This method for producing a structure wherein base materials are bonded by atomic diffusion comprises: a step for applying a liquid resin on the base material; a step for smoothing the surface of the liquid resin by surface tension; a step for forming a resin layer by curing; a step for forming a metal thin film on the resin layer; a step for forming a metal thin film on the base material; and a step for bringing the metal thin film of the base material and the metal thin film of the base material into close contact with each other, thereby bonding the metal thin film of the resin layer and the metal thin film of the base material with each other by atomic diffusion

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

A semiconductor device of an embodiment includes: a semiconductor substrate; a first insulating layer provided on or above the semiconductor substrate; an aluminum layer provided on the first insulating layer; a second insulating layer provided on the first insulating layer, the second insulating layer covering a first region of a surface of the aluminum layer; and an aluminum oxide film provided on a second region other than the first region of the surface of the aluminum layer, the aluminum oxide film including α-alumina as a main component, and a film thickness of the aluminum oxide film being equal to or larger than 0.5 nm and equal to or smaller than 3 nm. 1. A semiconductor device comprising:a semiconductor substrate;a first insulating layer provided on or above the semiconductor substrate;an aluminum layer provided on the first insulating layer;a second insulating layer provided on the first insulating layer, the second insulating layer covering a first region of a surface of the aluminum layer; andan aluminum oxide film provided on a second region other than the first region of the surface of the aluminum layer, the aluminum oxide film including α-alumina as a main component, and a film thickness of the aluminum oxide film being equal to or larger than 0.5 nm and equal to or smaller than 3 nm.2. The semiconductor device according to claim 1 , wherein the aluminum layer includes at least one of silicon and copper.3. The semiconductor device according to claim 1 , further comprising a polyimide layer provided on the second insulating layer.4. The semiconductor device according to claim 1 , further comprising a bonding wire provided on the second region.5. The semiconductor device according to claim 4 , wherein the aluminum oxide film exists in a part between the bonding wire and the aluminum layer.6. A method of manufacturing a semiconductor device claim 4 , comprising:forming a first insulating layer on or above a semiconductor substrate;forming an aluminum ...

WAFER-LEVEL PACKAGE INCLUDING UNDER BUMP METAL LAYER

A semiconductor package includes a semiconductor chip comprising a first surface and a second surface, a redistribution layer on the first surface of the semiconductor chip, an under bump metal (UBM) layer on the redistribution layer, and a solder bump on the UBM layer, and the solder bump covers both outer side surfaces of the UBM layer. 1. A wafer-level semiconductor package comprising:a semiconductor chip including a first surface and a second surface, and including a connection pad on the first surface;a first passivation layer covering the first surface of the semiconductor chip, the first passivation layer including a first trench exposing the connection pad;a redistribution layer in the first trench and on the first passivation layer;a second passivation layer on the redistribution layer, and the second passivation layer includes a second trench exposing the redistribution layer;a UBM layer in the second trench and on the second passivation and in contact with the redistribution layer, and the thickness of the UBM layer is approximately 25 to 35 μm; anda solder bump on the UBM layer and covering an outer surface of the UBM layer, and a thickness of the solder bump is approximately 210 to 220 μm.2. The wafer-level semiconductor package of claim 1 , wherein the solder bump includes Au.3. The wafer-level semiconductor package of claim 1 , wherein the solder bump further comprises a contact surface in contact with the second passivation layer.4. The wafer-level semiconductor package of claim 1 , wherein an width of a portion of the solder bump covering the outer surface of the UBM layer gradually increases from the second passivation layer to the bottom surface of the UBM layer.5. The wafer-level semiconductor package of claim 1 , wherein the UBM layer comprises a first UBM layer in contact with the redistribution layer and a second UBM layer disposed on the first UBM layer.6. The wafer-level semiconductor package of claim 1 , wherein the wafer-level ...

DRIVING SUBSTRATE AND MANUFACTURING METHOD THEREOF, AND MICRO LED BONDING METHOD

The present disclosure provides a driving substrate and a manufacturing method thereof, and a micro LED bonding method. The driving substrate includes: a base substrate; a driving function layer provided on the base substrate, and including a plurality of driving thin film transistors and a plurality of common electrode lines; a pad layer including a plurality of pads provided on a side of the driving function layer away from the base substrate, each pad including a pad body and a microstructure of hard conductive material provided on a side of the pad body away from the base substrate; and a plurality of buffer structures provided on the side of the driving function layer away from the base substrate, each buffer structure surrounding a portion of a corresponding microstructure close to the base substrate, and a height of the buffer structure being lower than a height of the microstructure. 1. A driving substrate , comprising:a base substrate;a driving function layer provided on the base substrate, the driving function layer comprising a plurality of driving thin film transistors and a plurality of common electrode lines;a pad layer comprising a plurality of pads provided on a side of the driving function layer away from the base substrate, each pad comprising a pad body and a microstructure of hard conductive material provided on a side of the pad body away from the base substrate; anda plurality of buffer structures provided on the side of the driving function layer away from the base substrate, each buffer structure surrounding a portion of a corresponding microstructure close to the base substrate, and a height of the buffer structure being lower than a height of the microstructure.2. The driving substrate according to claim 1 , wherein each driving thin film transistor in the driving function layer comprises a gate claim 1 , a first electrode and a second electrode claim 1 , the pad layer comprises a plurality of first pads and a plurality of second pads claim ...

Edge Cut Debond Using a Temporary Filler Material With No Adhesive Properties and Edge Cut Debond Using an Engineered Carrier to Enable Topography

A semiconductor device assembly that includes a first side of a semiconductor device supported on a substrate to permit the processing of a second side of the semiconductor device. A filler material deposited on the semiconductor device supports the semiconductor device on the substrate. The filler material does not adhere to the semiconductor device or the substrate. Alternatively, the filler material may be deposited on the substrate. Instead of a filler material, the substrate may include a topography configured to support the semiconductor device. Adhesive applied between an outer edge of the first side of the semiconductor and the substrate bonds the outer edge of the semiconductor device to the substrate to form a semiconductor device assembly. A second side of the semiconductor device may then be processed and the outer edge of the semiconductor device may be cut off to release the semiconductor device from the assembly.

SEMICONDUCTOR STRUCTURE WITH CONDUCTIVE STRUCTURE

A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a conductive pad formed over a substrate, and a conductive structure formed over the conductive pad. The conductive structure has a curved top surface. The semiconductor device structure also includes a protection layer between the conductive pad and the conductive structure. A lowest point of the curved top surface of the conductive structure is higher than a topmost surface of the protection layer. 1. A semiconductor device structure , comprising:a conductive pad formed over a substrate;a conductive structure formed over the conductive pad, wherein the conductive structure has a curved top surface; anda protection layer between the conductive pad and the conductive structure, wherein a lowest point of the curved top surface of the conductive structure is higher than a topmost surface of the protection layer.2. The semiconductor device structure as claimed in claim 1 , further comprising:a seed layer formed on the conductive structure, wherein the seed layer is in direct contact with the conductive structure and has a curved bottom surface.3. The semiconductor device structure as claimed in claim 2 , wherein the seed layer and the conductive structure are made of different materials claim 2 , and an interface between the seed layer and the conductive structure is curved.4. The semiconductor device structure as claimed in claim 2 , wherein the seed layer has a middle portion and an edge portion claim 2 , the middle portion has a curved top surface claim 2 , and the edge portion has a planar top surface claim 2 , and the curved top surface is lower than the middle top surface.5. The semiconductor device structure as claimed in claim 2 , further comprising:a post-passivation interconnect (PPI) structure formed over the seed layer, wherein the PPI structure has a curved bottom surface.6. The semiconductor device structure as claimed in claim 1 , ...

Quad flat no lead package and production method thereof

The present invention discloses a quad flat no lead package and a production method thereof. The quad flat no lead package comprises a lead frame carrier consisting of a carrier pit and three circles of leads arranged around the carrier pit, wherein the three circles of leads respectively consist of a plurality of leads that are disconnected mutually; an IC chip is adhered in the carrier pit; and an inner lead chemical nickel and porpezite plated layer is plated on all the leads; the inner lead chemical nickel and porpezite plated layer is arranged in the same direction as the IC chip; the IC chip is connected with the inner lead chemical nickel and porpezite plated layer through a bonding wire; and the IC chip, the ends of all the leads plated with the inner lead chemical plating nickel and palladium metal layers and the bonding wire are all packaged in a plastic package. The quad flat no lead package is manufactured through the following steps of: thinning and scribing a wafer; manufacturing a lead frame; loading the chip; performing pressure welding and plastic packaging; performing post-curing; printing; electroplating; separating the leads; separating a product; and testing/braiding. According to the package, the problems of few leads, long welding wire, high welding cost and limited frequency application during single-face packaging of the existing normal quad flat no lead package are solved.

Substrate attachment for attaching a substrate thereto

A method for bonding a first substrate with a second substrate, characterized in that the first substrate and/or the second substrate is/are thinned before the bonding.

Battery protection package and process of making the same

The present invention discloses small-size battery protection packages and provides a process of fabricating small-size battery protection packages. A battery protection package includes a first common-drain metal oxide semiconductor field effect transistor (MOSFET), a second common-drain MOSFET, a power control integrated circuit (IC), a plurality of solder balls, a plurality of conductive bumps, and a packaging layer. The power control IC is vertically stacked on top of the first and second common-drain MOSFETs. At least a majority portion of the power control IC and at least majority portions of the plurality of solder balls are embedded into the packaging layer. The process of fabricating battery protection packages includes steps of fabricating power control ICs; fabricating common-drain MOSFET wafer; integrating the power control ICs with the common-drain MOSFET wafer and connecting pinouts; forming a packaging layer; applying grinding processes; forming a metal layer; and singulating battery protection packages.

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME

A semiconductor structure is provided. A first semiconductor device includes a first conductive layer formed over a first substrate; a first etching stop layer formed over the first conductive layer, and the first etching stop layer is in direct contact with the first conductive layer. A first bonding layer is formed over the first etching stop layer, and a first bonding via is formed through the first bonding layer and the first etching stop layer. The semiconductor structure includes a second semiconductor device. The second semiconductor device includes a second bonding layer formed over the second etching stop layer and a second bonding via formed through the second bonding layer and a second etching stop layer. A bonding structure between the first substrate and the second substrate, and the bonding structure includes the first bonding via bonded to the second bonding via. 1. A semiconductor structure , comprising: a first conductive layer formed over a first substrate;', 'a first etching stop layer formed over the first conductive layer, wherein the first etching stop layer is in direct contact with the first conductive layer;', 'a first bonding layer formed over the first etching stop layer;', 'a first bonding via formed through the first bonding layer and the first etching stop layer, wherein the first bonding via is electrically connected to the first conductive layer;, 'a first semiconductor device, wherein the first semiconductor device comprises a second conductive layer formed over a second substrate;', 'a second etching stop layer formed over the second conductive layer, wherein the second etching stop layer is in direct contact with the second conductive layer;', 'a second bonding layer formed over the second etching stop layer;', 'a second bonding via formed through the second bonding layer and the second etching stop layer, wherein the second bonding via is electrically connected to the second conductive layer; and, 'a second semiconductor device, ...

SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME

A method for fabricating a semiconductor structure is provided. The method includes: providing a semiconductor chip comprising an active surface; forming a conductive bump over the active surface of the semiconductor chip; and coupling the conductive bump to a substrate. The conductive bump includes a plurality of bump segments including a first group of bump segments and a second group of bump segments. Each bump segment has a same segment thickness in a direction orthogonal to the active surface of the semiconductor chip, and each bump segment has a volume defined by a multiplication of the same segment thickness with an average cross-sectional area of the bump segment in a plane parallel to the active surface of the semiconductor chip. A ratio of a total volume of the first group of bump segments to a total volume of the second group of bump segments is between 0.03 and 0.8. 1. A method for fabricating a semiconductor structure comprising:providing a semiconductor chip comprising an active surface;forming a conductive bump over the active surface of the semiconductor chip; andcoupling the conductive bump to a substrate,wherein the conductive bump comprises:a plurality of bump segments comprising a first group of bump segments and a second group of bump segments, wherein each bump segment has a same segment thickness in a direction orthogonal to the active surface of the semiconductor chip, and each bump segment has a volume defined by a multiplication of the same segment thickness with an average cross-sectional area of the bump segment in a plane parallel to the active surface of the semiconductor chip;wherein a ratio of a total volume of the first group of bump segments to a total volume of the second group of bump segments is between 0.03 and 0.8.2. The method of claim 1 , wherein each bump segment comprises a shape of a pillar or a frustum.3. The method of claim 1 , wherein forming the conductive bump over the semiconductor chip comprises forming different ...

Silver-to-silver bonded ic package having two ceramic substrates exposed on the outside of the package

A packaged power device involves no soft solder and no wire bonds. The direct-bonded metal layers of two direct metal bonded ceramic substrate assemblies, such as Direct Bonded Aluminum (DBA) substrates, are provided with sintered silver pads. Silver nanoparticle paste is applied to pads on the frontside of a die and the paste is sintered to form silver pads. Silver formed by an evaporative process covers the backside of the die. The die is pressed between the two DBAs such that direct silver-to-silver bonds are formed between sintered silver pads on the frontside of the die and corresponding sintered silver pads of one of the DBAs, and such that a direct silver-to-silver bond is formed between the backside silver of the die and a sintered silver pad of the other DBA. After leadforming, leadtrimming and encapsulation, the finished device has exposed ceramic of both DBAs on outside package surfaces.

Ir assisted fan-out wafer level packaging using silicon handler

A support structure for use in fan-out wafer level packaging is provided that includes, a silicon handler wafer having a first surface and a second surface opposite the first surface, a release layer is located above the first surface of the silicon handler wafer, and a layer selected from the group consisting of an adhesive layer and a redistribution layer is located on a surface of the release layer. After building-up a fan-out wafer level package on the support structure, infrared radiation is employed to remove (via laser ablation) the release layer, and thus remove the silicon handler wafer from the fan-out wafer level package.

Semiconductor device and semiconductor package including the same

A semiconductor device and a semiconductor package, the device including a first buffer dielectric layer on a first dielectric layer; a second dielectric layer and a second buffer dielectric layer sequentially disposed on the first buffer dielectric layer, the second buffer dielectric layer being in contact with the first buffer dielectric layer; and a pad interconnection structure that penetrates the first buffer dielectric layer and the second buffer dielectric layer, wherein the pad interconnection structure includes copper and tin.

Package With UBM and Methods of Forming

Package structures and methods of forming package structures are discussed. A package structure, in accordance with some embodiments, includes an integrated circuit die, an encapsulant at least laterally encapsulating the integrated circuit die, a redistribution structure on the integrated circuit die and the encapsulant, a connector support metallization coupled to the redistribution structure, a dummy pattern, a second dielectric layer, and an external connector on the connector support metallization. The redistribution structure comprises a first dielectric layer having a first surface disposed distally from the encapsulant and the integrated circuit die. The dummy pattern is on the first surface of the first dielectric layer and around the connector support metallization. The second dielectric layer is on the first surface of the first dielectric layer and on at least a portion of the dummy pattern. The second dielectric layer does not contact the connector support metallization. 1. A method comprising:encapsulating an integrated circuit die with an encapsulant;forming a redistribution structure on the integrated circuit die and the encapsulant, the redistribution structure comprising a first dielectric layer having a first surface distal from the integrated circuit die and the encapsulant;forming an under ball metallization (UBM) and a dummy pattern on the redistribution structure, the dummy pattern surrounding the UBM on the first surface of the first dielectric layer, the dummy pattern being electrically isolated; andforming a second dielectric layer on the first surface of the first dielectric layer and at least a portion of the dummy pattern, wherein after the forming the second dielectric layer, the second dielectric layer is physically spaced apart from the UBM, wherein the second dielectric layer covers an exterior portion of the dummy pattern laterally distal from the UBM and exposes an interior portion of the dummy pattern proximate the UBM.2. The ...

BUMP BONDED CRYOGENIC CHIP CARRIER

A technique relates to a device. First thin films are characterized by having a first opposing surface and a first connection surface in which the first connection surface is in physical contact with a first superconducting region. Second thin films are characterized by having a second opposing surface and a second connection surface in which the first and second opposing surfaces are opposite one another. The second connection surface is in physical contact with a second superconducting region. A solder material electrically connects the first and second opposing surfaces, and the solder material is characterized by maintaining a low ohmic electrical contact between the first and second opposing surfaces at temperatures below 100 degrees Kelvin. The first and second superconducting regions are formed of materials that have a melting point of at least 700 degrees Celsius. 1. A device comprising:a first plurality of thin films, the first plurality of thin films characterized by having a first opposing surface and a first connection surface, wherein the first connection surface is in physical contact with a first superconducting region;a second plurality of thin films, the second plurality of thin films characterized by having a second opposing surface and a second connection surface, the first and second opposing surfaces being opposite one another, wherein the second connection surface is in physical contact with a second superconducting region; anda solder material electrically connecting the first and second opposing surfaces, the solder material characterized by maintaining a low ohmic electrical contact between the first and second opposing surfaces at temperatures below 100 degrees Kelvin, wherein the first and second superconducting regions are comprised of materials that have a melting point of at least 700 degrees Celsius.2. The device of claim 1 , wherein the first and second plurality of thin films are electrically conductive.3. The device of claim 1 , ...

BOND PAD STRUCTURE FOR LOW TEMPERATURE FLIP CHIP BONDING

Methods for preparing 3D integrated semiconductor devices and the resulting devices are disclosed. Embodiments include forming a first and a second bond pad on a first and a second semiconductor device, respectively, the first and the second bond pads each having plural metal segments, the metal segments of the first bond pad having a configuration different from a configuration of the metal segments of the second bond pad or having the same configuration as a configuration of the metal segments of the second bond pad but rotated with respect to the second bond pad; and bonding the first and second semiconductor devices together through the first and second bond pads. 1. A method comprising:forming a first and a second bond pad on a first and a second semiconductor device, respectively, the first and the second bond pads each having plural metal segments, the metal segments of the first bond pad having a configuration different from a configuration of the metal segments of the second bond pad or having the same configuration as a configuration of the metal segments of the second bond pad but rotated with respect to the second bond pad; andbonding the first and second semiconductor devices together through the first and second bond pads.2. The method according to claim 1 , comprising forming a larger first bond pad on the first semiconductor device than the second bond pad on the second semiconductor device.3. The method according to claim 1 , comprising patterning the first and second bond pads on the first and second semiconductor devices claim 1 , respectively claim 1 , by a copper damascene process.4. The method according to claim 1 , further comprising surrounding the first and second bond pads on the first and second semiconductor devices claim 1 , respectively claim 1 , by a dielectric layer; andbonding the first and second semiconductor devices together through the dielectric layers in a chemical or plasma activated fusion bonding process.5. The method ...

Semiconductor Device and Method for Manufacturing Semiconductor Device

This invention provides a semiconductor device with improved reliability. A semiconductor chip (semiconductor device) includes a plurality of electrode pads arranged in a plurality of lines extending along a side (chip side) of a perimeter of the semiconductor chip in plan view. Among the electrode pads, the areas of respective electrode pads arranged in a first line along the chip side are smaller than the areas of respective electrode pads arranged in a line located further than the first line from the chip side. 1. A semiconductor device comprising:a semiconductor substrate having an element formation surface;a first insulating film that has a first surface facing the semiconductor substrate, a second surface opposite to the first surface, and a plurality of openings passing therethrough from one of the first surface and the second surface to the other in the thickness direction, and is formed so as to cover the element formation surface of the semiconductor substrate; anda plurality of electrode pads that are formed between the first insulating film and the semiconductor substrate, and are exposed from the first insulating film at positions overlapping the openings in the first insulating film, a plurality of the first-line electrode pads formed in a first line along a first chip side of a perimeter of the second surface in plan view;', 'a plurality of second-line electrode pads formed in a second line along the first chip side, the second line located further than the first line from the first chip side in plan view; and', 'a plurality of third-line electrode pads formed in a third line along the first chip side, the third line located further than the second line from the first chip side in plan view, and, 'wherein, the electrode pads includewherein, the areas of the respective first-line electrode pads are smaller than the areas of the respective second-line electrode pads and the respective third-line electrode pads.2. The semiconductor device according to ...

Conductive Line System and Process

A system and method for providing a conductive line is provided. In an embodiment the conductive line is formed by forming two passivation layers, wherein each passivation layer is independently patterned. Once formed, a seed layer is deposited into the two passivation layers, and a conductive material is deposited to fill and overfill the patterns within the two passivation layers. A planarization process such as a chemical mechanical polish may then be utilized in order to remove excess conductive material and form the conductive lines within the two passivation layers. 1. A method of manufacturing a semiconductor device , the method comprising:applying a positive tone photosensitive material over a negative tone photosensitive material over a substrate;forming a first conductive material to extend through the positive tone photosensitive material and the negative tone photosensitive material to make electrical connection with a contact pad; andforming a second conductive material to extend through the positive tone photosensitive material, wherein after the forming the second conductive material a first surface of the second conductive material faces a second surface of the negative tone photosensitive material, the second surface of the negative tone photosensitive material facing away from the substrate.8. A method of manufacturing a semiconductor device , the method comprising:coating a dielectric layer with a negative tone photosensitive material, the dielectric layer exposing a first portion of a first contact pad;patterning and developing the negative tone photosensitive material;coating the negative tone photosensitive material with a positive tone photosensitive material;patterning and developing the positive tone photosensitive material to expose a first portion of the negative tone photosensitive material and also to expose the first portion of the first contact pad, wherein the first portion of the negative tone photosensitive material is separated ...

Semiconductor device with contact pad and method of making

A semiconductor structure includes a conductive structure over a first passivation layer; and a second passivation layer over the conductive structure and the first passivation layer. The second passivation layer has a first oxide film extending along a top surface of the first passivation layer, sidewalls and a top surface of the conductive structure, wherein a top surface of the first oxide film is planar. The second passivation layer further includes a second oxide film over a top surface of the first oxide film and a top surface of the conductive structure, wherein a top surface of the second oxide film is planar. The second passivation layer further includes a third oxide film extending along a top surface of the second oxide film, the sidewalls and the top surface of the conductive structure, wherein a top surface of the third oxide film is curved.

Method for fabricating an electronic device

The method for fabricating a device includes the following successive steps: providing a first substrate made from silicon of (100), (110) or (111) orientation, from a material of III-IV type or from a material of II-VI type, provided with at least one salient metal pad, and providing a second substrate; fixing the first substrate with the second substrate, the at least one metal pad forming a blocking means preventing movement beyond a threshold position; and performing an anneal of the metal pad so as to melt the metal pad and eliminate the blocking means.

ELECTRONIC DEVICE HAVING COATED CONTACT PADS

A system and method for bonding an electrically conductive mechanical interconnector (e.g., a bonding wire, solder, etc.) to an electrical contact (e.g., contact pad, termination on a printed circuit board (PCB), etc.) made from an electrically conductive metal (e.g., aluminum) on an electronic device (e.g., integrated circuit (IC), die, wafer, PCB, etc.) is provided. The electrical contact is chemically coated with a metal (e.g., cobalt) that provides a protective barrier between the mechanical interconnector and the electrical contact. The protective barrier provides a diffusion barrier to inhibit galvanic corrosion (i.e. ion diffusion) between the mechanical interconnector and the electrical contact. 1. A method , comprising:providing an array of electrical devices, each of the electrical devices having an aluminum pad;immersing the array of electrical devices into a cobalt ion solution to chemically displace an aluminum oxide layer from each aluminum pad, wherein the aluminum oxide layer is oxidized to form an aluminum ion and free electrons, wherein the cobalt ion liquid solution combines with the free electrons to form a cobalt metal, and wherein a layer of the cobalt metal is deposited on each aluminum pad in place of the aluminum oxide layer; andbonding an electrically conductive mechanical interconnector to the layer of cobalt metal.2. The method of claim 1 , wherein bonding the electrically conductive mechanical interconnector includes bonding a copper bonding wire to the layer of cobalt metal.3. The method of claim 1 , wherein bonding the electrically conductive mechanical interconnector includes disposing a solder ball comprised at least one of copper claim 1 , tin claim 1 , and silver on the layer of cobalt metal.4. The method of claim 1 , wherein prior to immersing the electrical device into the cobalt ion solution claim 1 , the method comprising mixing cobalt citrate claim 1 , polyethylenimine claim 1 , and aluminum fluoride to form the cobalt ion ...

METHODS AND APPARATUS FOR PROCESSING A SUBSTRATE

Methods and apparatus for processing a substrate are provided herein. For example, a method for processing a substrate can includes selectively etching from a substrate disposed in the PVD chamber an exposed first layer of material, covering an underlying second layer of material, and adjacent to an exposed third layer of material, using both process gas ions and metal ions formed from a target of the PVD chamber, in an amount sufficient to expose the second layer of material while simultaneously depositing a layer of metal onto the third layer of material; and subsequently depositing metal from the target onto the second layer of material. 1. A method for processing a substrate in a physical vapor deposition (PVD) chamber , comprising:selectively etching from a substrate disposed in the PVD chamber an exposed first layer of material, covering an underlying second layer of material, and adjacent to an exposed third layer of material, using both process gas ions and metal ions formed from a target of the PVD chamber, in an amount sufficient to expose the second layer of material while simultaneously depositing a layer of metal onto the third layer of material; andsubsequently depositing metal from the target onto the second layer of material.2. The method of claim 1 , wherein subsequently depositing metal from the target onto the second layer of material comprises depositing metal from the target onto the layer of material deposited on the third layer of material.3. The method of claim 1 , wherein selectively etching the first layer of material comprises using both a DC power source and an RF power source.4. The method of claim 1 , wherein depositing metal comprises using only a DC power source.5. The method of claim 1 , wherein the first layer of material is a layer of metal oxide claim 1 , the second layer of material is a metal claim 1 , and the third layer of material is a layer of polymer.6. The method of claim 5 , wherein the layer of metal oxide is aluminum ...

CHIP PACKAGING METHOD AND CHIP PACKAGING STRUCTURE

Provided are a chip packaging method and a chip packaging structure. A passivation layer is provided on a pad of a wafer, a first metal bonding layer is then formed on the passivation layer, a second metal bonding layer is formed on a substrate, the substrate and the wafer are bonded and packaged together through bonding of the first metal bonding layer and the second metal bonding layer, a first shielding layer is provided on the substrate, and the first shielding layer is connected to the second metal bonding layer; and after the wafer and the substrate are bonded, semi-cutting is performed on the wafer until the first metal bonding layer is exposed, and a second shielding layer is then formed, and the second shielding layer is electrically connected to the first metal bonding layer, such that an electromagnetic shielding structure jointly composed of the first shielding layer, the second metal bonding layer, the second shielding layer and the first metal bonding layer is obtained. The shielding structure is thus approximately closed, thereby improving the electromagnetic shielding effect. 1. A method for packaging a chip , comprising:providing a wafer, wherein the wafer comprises a first surface and a second surface that are opposite to each other, at least two functional circuit regions and a plurality of bonding pads are formed on the first surface, and the plurality of bonding pads are located around each of the at least two functional circuit regions;forming a passivation layer on each of the plurality of bonding pads, wherein the passivation layer comprises a center region and a peripheral region surrounding the center region;forming a first metal bonding layer on the passivation layer, wherein the first metal bonding layer covers the peripheral region of the passivation layer;providing a substrate, wherein the substrate comprises a third surface and a fourth surface that are opposite to each other, a second metal bonding layer and a first shielding layer ...

SEMICONDUCTOR DEVICE

A semiconductor device includes: a semiconductor substrate having a first main surface; an aluminum electrode having a first surface facing the first main surface and a second surface opposite to the first surface, the aluminum electrode being disposed on the semiconductor substrate; a passivation film that covers a peripheral edge of the second surface and that is provided with an opening from which a portion of the second surface is exposed; a copper film disposed on the second surface exposed from the opening so as to be separated from the passivation film; and a metal film disposed on the second surface exposed from between the passivation film and the copper film. The metal film is constituted of at least one selected from a group consisting of a nickel film, a tantalum film, a tantalum nitride film, a tungsten film, a titanium film, and a titanium nitride film. 1. A semiconductor device comprising:a semiconductor substrate having a first main surface;an aluminum electrode having a first surface facing the first main surface and a second surface opposite to the first surface, the aluminum electrode being disposed on the semiconductor substrate;a passivation film that covers a peripheral edge of the second surface and that is provided with an opening from which a portion of the second surface is exposed;a copper film disposed on the second surface exposed from the opening so as to be separated from the passivation film; anda metal film disposed on the second surface exposed from between the passivation film and the copper film, whereinthe metal film is constituted of at least one selected from a group consisting of a nickel film, a tantalum film, a tantalum nitride film, a tungsten film, a titanium film, and a titanium nitride film.2. The semiconductor device according to claim 1 , wherein the passivation film is a polyimide film.3. The semiconductor device according to claim 1 , wherein the metal film is an electroless nickel plating film.4. The semiconductor ...

MASKLESS SELECTIVE RETENTION OF A CAP UPON A CONDUCTOR FROM A NONCONDUCTIVE CAPPING LAYER

A semiconductor structure includes an electrically conductive structure formed upon an uppermost organic layer of a semiconductor substrate. A capping layer is formed upon the uppermost organic layer covering the electrically conductive structure. A maskless selective removal lasering technique ejects portions of the capping layer while retaining the portion of the capping layer covering the electrically conductive structure. Portions of the capping layer are ejected from the uppermost organic layer by a shockwave as a result of the laser beam vaporizing the uppermost organic layer of the semiconductor substrate. Portions of the capping layer contacting the electrically conductive structure are retained by the conductive structure dissipating heat from the laser that would otherwise vaporize the uppermost organic layer of the semiconductor substrate. 1. A semiconductor device fabrication method comprising:forming a electrically conductive structure upon an uppermost organic layer of a semiconductor substrate;forming a capping layer upon the uppermost organic layer covering the electrically conductive structure, and;directing a laser beam to eject portions of the capping layer from the uppermost organic layer and form a cap by retaining the capping layer covering the electrically conductive structure.2. The semiconductor device fabrication method of claim 1 , wherein portions of the capping layer are ejected from the uppermost organic layer by a shockwave as a result of the laser beam vaporizing the uppermost organic layer of the semiconductor substrate.3. The semiconductor device fabrication method of claim 2 , wherein the capping layer is formed from silicon nitride.4. The semiconductor device fabrication method of claim 2 , wherein the capping layer covering the electrically conductive structure is retained by the electrically conductive structure dissipating heat from the laser that would otherwise vaporize the uppermost organic layer of the semiconductor ...

METHOD FOR BONDING SUBSTRATES

A method for bonding a first substrate with a second substrate by means of a connecting layer that is arranged between the substrates and that is comprised of a connecting material with the following steps: applying the connecting material to the first substrate and/or the second substrate in liquid form, and distributing the connecting material between the substrates by bringing the substrates closer and as a result forming the shape of the connecting layer with a thickness t. 16-. (canceled)7. A method for bonding a first lower substrate with a second upper substrate by means of a connecting layer that is arranged between the first lower substrate and the second upper substrate , the connecting layer including a connecting material , wherein the method comprises:applying at least one droplet of the connecting material to the second upper substrate in a liquid form; anddistributing the connecting material between the first lower substrate and the second upper substrate by bringing the substrates closer to each other, wherein the distributing takes place automatically by capillary action of the liquid connecting material,wherein one of the substrates is released after contacting the at least one droplet with the first lower substrate, thereby forming the shape of the connecting layer with a thickness t, andwherein the connecting material is applied in an amount that is free of surplus.8. The method according to claim 7 , wherein the connecting material is applied in an amount that is free of excess and that is preset by the thickness t of the connecting layer and a diameter of at least one of the substrates.9. The method according to claim 7 , wherein the connecting material is applied to the first lower substrate and the second upper substrate.10. The method according to claim 9 , wherein the connecting material is applied to areas of the substrates that correspond to each another.11. The method according to claim 7 , wherein the distributing of the connecting ...