Leistungshalbleiterchip und Verfahren zur Herstellung eines Leistungshalbleiterchips und Leistungshalbleitereinrichtung

Leistungshalbleiterchip mit einem Halbleiterbauelementkörper (2) und mit einer auf dem Halbleiterbauelementkörper (2) angeordneten mehrschichtigen Metallisierung (10), die eine über dem Halbleiterbauelementkörper (2) angeordnete Nickelschicht (6) aufweist, wobei die Metallisierung (10) eine auf dem Halbleiterbauelementkörper (2) angeordnete, Aluminium aufweisende erste Metallschicht (3) aufweist, wobei die Nickelschicht (6) über der ersten Metallschicht (3) angeordnet ist, wobei die Metallisierung (10) eine zweite Metallschicht (4), die als Chromschicht ausgebildet ist und eine auf der zweiten Metallschicht (4) angeordnete Zwischenschicht (13), die aus Nickel besteht und eine auf der Zwischenschicht (13) angeordnete dritte Metallschicht (5), die als Silberschicht ausgebildet ist, aufweist, wobei die zweite Metallschicht (4) auf der ersten Metallschicht (3) angeordnet ist, wobei die Nickelschicht (6) auf der dritten Metallschicht (5) angeordnet ist, wobei die Nickelschicht (6) eine Dicke ...

Method and structures for testing a semiconductor wafer prior to performing a flip chip bumping process

HIGHLY RELIABLE ONES NOT CONDUCTIVE ADHESIVES FOR SOLDERING LOTS FLIP CHIP BONDINGS AND FLIP CHIPBONDVERFAHREN THEREBY

Semiconductor device and a method of manufacturing the semiconductor device

A semiconductor device having redistribution interconnects in the WPP technology and improved reliability, wherein the redistribution interconnects have first patterns and second patterns which are electrically separated from each other within the plane of the semiconductor substrate, the first patterns electrically coupled to the multi-layer interconnects and the floating second patterns are coexistent within the plane of the semiconductor substrate, and the occupation ratio of the total of the first patterns and the second patterns within the plane of the semiconductor substrate, that is, the occupation ratio of the redistribution interconnects is 35 to 60%.

PROCESS OF WELDING OF TWO ELEMENTS BETWEEN THEM BY MEANS OF A MATERIAL OF BRAZING

Power electronic component with cooling surfaces includes dual cooling panels forming sandwich to enclose semiconductor element

Ce composant (28) comprend une semelle (2) destinée à reposer sur un premier élément de refroidissement (30), au moins une première structure composite (4) de transfert thermique et d'isolation électrique, et au moins un premier circuit semi-conducteur de puissance (10) comportant des plots (12) métalliques de connexion. Les plots de connexion sont assujettis, par leur face opposée à ladite première structure (4), à un réseau plan (18A) d'éléments conducteurs isolés entre eux, qui appartient à un ensemble de liaison rapporté (22), apte à entrer en contact, par sa face opposée audit réseau plan, avec un deuxième élément de refroidissement (32). Ce composant peut être refroidi à la fois depuis sa face supérieure et sa face inférieure.

Semiconductor product with interlocking metal-to-metal bonds and method for manufacturing thereof

Solder bump/under bump metallurgy structure for high temperature applications

Solder bump structures, which comprise a solder bump on a UBM structure, are provided for operation at temperatures of 250 DEG C and above. According to a first embodiment, the UBM structure comprises layers of Ni-P, Pd-P, and gold, wherein the Ni-P and Pd-P layers act as barrier and/or solderable/bondable layers. The gold layer acts as a protective layer. According to second embodiment, the UBM structure comprises layers of Ni-P and gold, wherein the Ni-P layer acts as a diffusion barrier as well as a solderable/bondable layer, and the gold acts as a protective layer. According to a third embodiment, the UBM structure comprises: (i) a thin layer of metal, such as titanium or aluminum or Ti/W alloy; (ii) a metal, such as NiV, W, Ti, Pt, TiW alloy or Ti/W/N alloy; and (iii) a metal alloy such as Pd-P, Ni-P, NiV, or TiW, followed by a layer of gold. Alternatively, a gold, silver, or palladium bump may be used instead of a solder bump in the UBM structure.

Method and structures for testing a semiconductor wafer prior to performing a flip chip bumping process

An interface assembly (20) and method for testing a semiconductor wafer prior to performing a flip chip bumping process are provided. The interface assembly includes a flip chip bonding pad (24) having a region (28) for performing the bumping process. A test pad (22) is integrally constructed with the bonding pad and includes a probe region (26) for performing wafer-level testing prior to performing the bumping process. The integral construction of the bonding and testing pads avoids, for example, an introduction of propagation delays to test signals passing therethrough, thereby improving the accuracy and reliability of wafer test results.

Method for making a direct chip attach device and structure

A method for forming a direct chip attach device (1) includes attaching an electronic chip (3) to a lead frame structure (2), which includes a flag (18). Next, conductive studs (22) are attached to bond pads (13) on electronic chip (3) and flag (18) to form a sub-assembly (24). Sub-assembly (24) is then placed in a molding apparatus (27, 47), which includes a first plate (29, 49) and second plate (31, 51). Second plate (31, 51) includes a cavity (32, 52) for receiving electronic chip (3) and flag (18), and pins (36, 56). During a molding step, pins (36, 56) contact conductive studs (22) to prevent encapsulating material (4) from covering studs (22). This forms openings (6) to receive solder balls (9) during a subsequent processing step.

Light-emitting device, light-emitting element and method of manufacturing same

STABLE GOLD BUMP SOLDER CONNECTIONS

A metallic interconnect structure (200) for connecting a gold bump (205) and a copper pad (212), as used for example in semiconductor flip-chip assembly. A first region (207) of binary AuSn2 intermetallic is adjacent to the gold bump. A region (208) of binary AuSn4 intermetallic is adjacent to the first AuSn2 region. Then, a region (209) of binary gold-tin solid solution is adjacent to the AuSn4 region, and a second region (210) of binary AuSn2 intermetallic is adjacent to the solid solution region. The second AuSn2 region is adjacent to a nickel layer (213) (preferred thickness about 0.08 μm), which covers the copper pad. The nickel layer insures that the gold/tin intermetallic s and solutions remain substantially free of copper and thus avoid ternary compounds, providing stabilized gold bump/solder connections.

Method of making a semiconductor chip assemby with a metal containment wall and a solder terminal

A method of making a semiconductor chip assembly includes providing a metal base, a routing line, a metal containment wall and a solder layer in which the metal containment wall includes a cavity and the solder terminal contacts the metal containment wall in the cavity, mechanically attaching a semiconductor chip to the routing line, forming a connection joint that electrically connects the routing line and the pad, etching the metal base to reduce contact area between the metal base and the routing line and between the metal base and the metal containment wall, and providing a solder terminal that includes the solder layer.

Multi-component integrated circuit contacts

An integrated circuit connection is describe that includes a first, securing member and a second, connection member. The first member, in an embodiment, is a spike that has a portion of its body fixed in a layer of an integrated circuit structure and extends outwardly from the integrated circuit structure. The second material is adapted to form a mechanical connection to a further electrical device. The second material (e.g., solder), is held by the first member to the integrated circuit structure. The first member increases the strength of the connection and assists in controlling the collapse of second member to form the mechanical connection to another circuit. The connection is formed by coating the integrated circuit structure with a patterned resist and etching the layer beneath the resist. A first member material (e.g.,metal) is deposited. The resist is removed. The collapsible material is fixed to the first member.

Semiconductor device and manufacturing method thereof

A semiconductor device and manufacturing method thereof improving moisture resistance of a FeRAM. After a probe test using a pad, a metal film is formed to cover the pad in an opening of a protective film and a region from the pad to an opening outer periphery of the protective film. On the metal film, a metal bump is formed. The metal film is formed to have a two-layer structure of the first and second metal films. Materials of the lower and upper layers are selected mainly in consideration of adhesion to the protective film and adhesion to the metal bump, respectively. Film formation conditions thereof are set to provide metal films with a desired quality and thickness. Thus, penetration of moisture from the pad or the periphery into a ferroelectric capacitor can be prevented and therefore, occurrence of potential inversion abnormalities due to penetrated moisture can be effectively suppressed.

Autoclave capable chip-scale package

A power semiconductor package that includes a power semiconductor device having a threshold voltage that does not vary when subjected to an autoclave test.

Semiconductor device having wire studs as vertical interconnect in FO-WLP

A semiconductor device has a substrate and semiconductor die disposed over a first surface of the substrate. A wire stud is attached to the first surface of the substrate. The wire stud includes a base portion and stem portion. A bonding pad is formed over a second surface of the substrate. An encapsulant is deposited over the substrate, semiconductor die, and wire stud. A portion of the encapsulant is removed by LDA to expose the wire stud. A portion of the encapsulant is removed by LDA to expose the substrate. An interconnect structure is formed over the encapsulant and electrically connected to the wire stud and semiconductor die. A bump is formed over the interconnect structure. A semiconductor package is disposed over the encapsulant and electrically connected to the substrate. A discrete semiconductor device is disposed over the encapsulant and electrically connected to the substrate.

Semiconductor device assemblies including intermetallic compound interconnect structures

A method of forming a semiconductor device assembly comprises forming on a first substrate, at least one bond pad comprising a first nickel material over the first substrate, a first copper material on the first nickel material, and a solder-wetting material on the first copper material. On a second substrate is formed at least one conductive pillar comprising a second nickel material, a second copper material directly contacting the second nickel material, and a solder material directly contacting the second copper material. The solder-wetting material is contacted with the solder material. The first copper material, the solder-wetting material, the second copper material, and the solder material are converted into a substantially homogeneous intermetallic compound interconnect structure. Additional methods, semiconductor device assemblies, and interconnect structures are also described.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

Object is to prevent a coupling failure between a rewiring and a coupling member for coupling to outside. A passivation film and a first polyimide film are formed so as to cover a wiring layer. A first opening portion is formed in the first polyimide film. A rewiring is formed on the first polyimide film so as to be coupled to the wiring layer via the first opening portion. A second polyimide film that covers the rewiring and has a second opening portion communicated with the rewiring is formed. A palladium film is formed as a barrier film by sputtering on a portion of the surface of the rewiring at which the second opening portion exists. A solder ball is coupled to the palladium film.

Semiconductor Device and Method of Forming Shielding Layer Over Semiconductor Die Mounted to TSV Interposer

A semiconductor device has a plurality of conductive vias formed partially through a substrate. A conductive layer is formed over the substrate and electrically connected to the conductive vias. A semiconductor die is mounted over the substrate. An encapsulant is deposited over the semiconductor die and substrate. A trench is formed through the encapsulant around the semiconductor die. A shielding layer is formed over the encapsulant. The trench is formed partially through the substrate and the shielding layer is formed in the trench partially through the substrate. An insulating layer can be formed in the trench prior to forming the shielding layer. A portion of the substrate is removed to expose the conductive vias. An interconnect structure is formed over the substrate opposite the semiconductor die. The interconnect structure is electrically connected to the conductive vias. The shielding layer is electrically connected to the interconnect structure.

RADIATION DETECTOR UBM ELECTRODE STRUCTURE BODY, RADIATION DETECTOR, AND METHOD OF MANUFACTURING SAME

The present invention provides a radiation detector UBM electrode structure body and a radiation detector which suppress the degradation of metal electrode layers at the time of formation of UBM layers and achieve sufficient electric characteristics, and a method of manufacturing the same. A radiation detector UBM electrode structure body according to the present invention includes a substrate made of CdTe or CdZnTe, comprising a Pt or Au electrode layer formed on the substrate by electroless plating, an Ni layer formed on the Pt or Au electrode layer by sputtering, and an Au layer formed on the Ni layer by sputtering.

Semiconductor device and method comprising redistribution layers

A method of making a semiconductor package can include forming a plurality of redistribution layer (RDL) traces disposed over active surfaces of a plurality of semiconductor die and electrically connected to contact pads on the plurality of semiconductor die. The method can include disposing an encapsulant material over the active surfaces, contacting at least four side surfaces of each of the plurality of semiconductor die, and disposed over the plurality of RDL traces. The method can also include forming a via through the encapsulant material to expose at least one of the plurality of RDL traces, forming an electrical interconnect disposed within the via and coupled to the at least one RDL trace, and singulating the plurality of semiconductor packages through the encapsulant material to leave an offset of 30-140 μm of the encapsulant material disposed around a periphery of each of the plurality of semiconductor die.

Method of manufacturing semiconductor device and semiconductor device

Object is to prevent a coupling failure between a rewiring and a coupling member for coupling to outside. A passivation film and a first polyimide film are formed so as to cover a wiring layer. A first opening portion is formed in the first polyimide film. A rewiring is formed on the first polyimide film so as to be coupled to the wiring layer via the first opening portion. A second polyimide film that covers the rewiring and has a second opening portion communicated with the rewiring is formed. A palladium film is formed as a barrier film by sputtering on a portion of the surface of the rewiring at which the second opening portion exists. A solder ball is coupled to the palladium film.

SEMICONDUCTOR PACKAGE

A semiconductor package includes a first semiconductor chip having a first chip substrate, the first chip substrate having a first upper surface and a first lower surface opposite to each other, a first through-silicon via (TSV), a lower connection pad and a first lower passivation layer on the first lower surface of the first chip substrate, the first lower passivation layer exposing a portion of the lower connection pad, an upper connection pad and a first upper passivation layer on the first upper surface of the first chip substrate, the first upper passivation layer including a first upper inorganic material layer, and a second semiconductor chip connected to the first semiconductor chip, the second semiconductor chip including a second TSV, wherein the first lower passivation layer has a stacked structure of a first lower inorganic material layer and a lower organic material layer.

Semiconductor device and manufacturing method thereof

SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To provide a semiconductor device which is equipped with a capacitance element in the same semiconductor device to make the overall device compact, the capacitance element having larger electrostatic capacity than conventionally. SOLUTION: A semiconductor integrated circuit 1 and a pad electrode 4 are formed on the top surface of a semiconductor substrate 2. A second insulating film 10 is formed on a flank and a reverse surface of the semiconductor substrate 2, and a capacity electrode 9, which is in contact with the reverse surface of the semiconductor substrate 2, is formed between the reverse surface of the semiconductor substrate 2 and the second insulating film 10. The second insulating film 10 is covered with a wiring layer 11 electrically connected to the pad electrode 4, and the wiring layer 11 and capacity electrode 9 overlap each other, via the second insulating film 10 interposed. Accordingly, a capacitor 16 is formed of the capacity electrode 9, the second ...

ГИБКО ОБОРАЧИВАЕМЫЙ КРИСТАЛЛ ИНТЕГРАЛЬНОЙ СХЕМЫ

Kontakt-Struktur für ein Halbleiter-Bauelement sowie Verfahren zur Herstellung desselben

Ein Halbleiter-Bauelement (1) umfasst ein Substrat (2) mit einer ersten Seite (3) und einer zweiten Seite (4) und einer auf mindestens einer Seite (3, 4) des Substrats (2) angeordneten mehrschichtigen Kontakt-Struktur (9), wobei die Kontakt-Struktur (9) eine Sperr-Schicht (6) zur Verhinderung der Diffusion von Ionen von der dem Substrat (2) gegenüberliegenden Seite der Sperr-Schicht (6) in das Substrat (2) aufweist.

Semiconductor component e.g. transistor, has electroplating area extending from circuit contact port on lateral surfaces, and insulation layer arranged between area and body comprising opening for connection of port with area

The component has a semiconductor body with two main surfaces and lateral surfaces connecting the main surfaces. A coupling area adjacent to one of the main surfaces comprises a circuit contact port (104a). An electroplating area extends from the port on the lateral surfaces. An insulation layer (110) arranged between the area and the body comprises an opening for connection of the port with the area. An independent claim is also included for a method of producing a semiconductor component.

IMPROVEMENTS REGARDING INTEGRATED CIRCUITS

Semiconductor apparatus, method for manufacturing the same and electric device

ELECTRONIC DEVICE PACKAGE AND ELECTRONIC EQUIPMENT

UNDER BUMP METALLIZATION FOR ON-DIE CAPACITOR

THERMAL MECHANICAL FLIP CHIP DIE BONDING

A thermal mechanical process for bonding a flip chip die to a substrate. The flip chip die includes a plurality of copper pillar bumps, each copper pillar bump of the plurality of copper pillar bumps having a copper portion attached to the die and a bonding cap attached to the copper portion. The process includes positioning the die on the substrate such that the bonding cap of each copper pillar bump of the plurality of copper pillar bumps contacts a corresponding respective one of a plurality of bonding pads on the substrate, and thermosonically bonding the die to the substrate.

Semiconductor chip assembly with metal containment wall and solder terminal

A semiconductor chip assembly includes a semiconductor chip that includes a conductive pad, a conductive trace that includes a routing line, a metal containment wall and a solder terminal, and a connection joint that electrically connects the routing line and the pad. The metal containment wall includes a cavity, and the solder terminal contacts the metal containment wall in the cavity and is spaced from the routing line.

Structure and method for power field effect transistor

A packaged semiconductor device has a metal plate (1200) with sawed sides (1200c), a flat first surface (1200a) and a parallel second surface (1200b); the plate is separated into a first section (1201) and a second section (1202) spaced apart by a gap (1230). The plate has on the second surface (1200b) at least one insular mesa (1205) of the same metal in each section, the mesas raised from the second plate surface. The device further has an insulating member (1231), which adheres to the first plate surface, bridges the gap, and thus couples the first and second sections together. The device further has a vertical stack (1270) of two power FET chips (1210) and (1220), each having a pair of terminals on the first chip surface (1211 and 1212; 1221 and 1222 respectively) and a single terminal on the second chip surface. The single terminals of chip (1210) and chip (1220) are attached to each other to form the common terminal (1240). The terminal pair (1221) and (1222) is conductively attached ...

Method of forming an integrated crackstop

A method including forming a first dielectric layer above a conductive pad and above a metallic structure, the conductive pad and the metallic structure are each located within an interconnect level above a substrate, forming a first opening and a second opening in the first dielectric layer, the first opening is aligned with and exposes the conductive pad and the second opening is aligned with and exposes the metallic structure, and forming a metallic liner on the conductive pad, on the metallic structure, and above the first dielectric layer. The method may further include forming a second dielectric layer above the metallic liner, and forming a third dielectric layer above the second dielectric layer, the third dielectric layer is thicker than either the first dielectric layer or the second dielectric layer.

SEMICONDUCTOR DEVICE

A semiconductor device where an outside connection terminal of a semiconductor element and an electrode of a wiring board are connected to each other via a conductive adhesive, the conductive adhesive includes a first conductive adhesive; and a second conductive adhesive covering the first conductive adhesive; wherein the first conductive adhesive contains a conductive filler including silver (Ag); and the second conductive adhesive contains a conductive filler including a metal selected from a group consisting of tin (Sn), zinc (Zn), cobalt (Co), iron (Fe), palladium (Pd), and platinum (Pt).

Mounting spring elements on semiconductor devices, and wafer-level testing methodology

Resilient contact structures are mounted directly to bond pads on semiconductor dies, prior to the dies being singulated (separated) from a semiconductor wafer. This enables the semiconductor dies to be exercised (e.g., tested and/or burned-in) by connecting to the semiconductor dies with a circuit board or the like having a plurality of terminals disposed on a surface thereof. Subsequently, the semiconductor dies may be singulated from the semiconductor wafer, whereupon the same resilient contact structures can be used to effect interconnections between the semiconductor dies and other electronic components (such as wiring substrates, semiconductor packages, etc.). Using the all-metallic composite interconnection elements of the present invention as the resilient contact structures, burn-in can be performed at temperatures of at least 150° C., and can be completed in less than 60 minutes.

ENHANCED RELIABILITY FOR SEMICONDUCTOR DEVICES USING DIELECTRIC ENCASEMENT

A method and device for enhanced reliability for semiconductor devices using dielectric encasement is disclosed. The method and device are directed to improving the reliability of the solder joint that connects the integrated circuit (IC) chip to the substrate. The method comprises applying a layer of a photoimageable permanent dielectric material to a top surface of the semiconductor device, and patterning the layer of the photoimageable permanent dielectric material to have an opening over each feature. The method further comprises dispensing or stencil printing fluxing material into the permanent dielectric material openings, and applying solder, which contains no flux, to a top surface of the fluxing material. In one or more embodiments, the method further comprises heating the semiconductor device to a reflow temperature appropriate for the reflow of the solder, thereby causing the solder to conform to sidewalls of the permanent dielectric material openings to form a protective seal ...

Adhesive for semiconductor, fluxing agent, manufacturing method for semiconductor device, and semiconductor device

An adhesive for a semiconductor, comprising an epoxy resin, a curing agent, and a compound having a group represented by the following formula (1): wherein R1represents an electron-donating group.

PROTECTIVE BARRIER LAYER FOR SEMICONDUCTOR DEVICE ELECTRODES

SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD

PROBLEM TO BE SOLVED: To provide a semiconductor device wherein a semiconductor element is flip-chip mounted on a wiring board by joining electrodes of the wiring board and external connection terminals of the semiconductor element using a conductive adhesive containing silver (Ag) having excellent electric conductivity and the ion migration of the silver (Ag) can be prevented, and also to provide its manufacturing method. SOLUTION: In the semiconductor device wherein the external connection terminals 13 of the semiconductor element 12 and the electrodes 14 of the wiring board 11 are joined via the conductive adhesive 20, the conductive adhesive 20 contains a first conductive adhesive 20-1 and a second conductive adhesive 20-2 covering the first conductive adhesive 20-1. The first conductive adhesive 20-1 contains a conductive filler containing silver (Ag), while the second conductive adhesive 20-2 contains a conductive filler containing a metal selected among a group of tin (Sn), zinc ...

ГИБКО ОБОРАЧИВАЕМЫЙ КРИСТАЛЛ ИНТЕГРАЛЬНОЙ СХЕМЫ

Использование: для создания интегральной схемы. Сущность изобретения заключается в том, что устройство на основе гибко оборачиваемого кристалла интегральной схемы содержит подложку и гибкий кристалл интегральной схемы, соединенный с подложкой по существу в вертикальной ориентации относительно поверхности подложки. Технический результат: обеспечение возможности улучшенного теплоотведения и сохранения компактности. 4 н. и 21 з.п. ф-лы, 8 ил.

Halbleitermodule und Verfahren zu deren Bildung

Gemäß einer Ausführungsform der vorliegenden Erfindung umfasst ein Halbleitermodul ein erstes Halbleitergehäuse, das einen ersten Halbleiterchip (50) aufweist, der in einem ersten Einkapselungsmittel (80) angeordnet ist. Eine Öffnung (100) ist im ersten Einkapselungsmittel (80) angeordnet. Ein zweites Halbleitergehäuse (150), das einen zweiten Halbleiterchip umfasst, ist in einem zweiten Einkapselungsmittel (180) angeordnet. Das zweite Halbleitergehäuse (150) ist wenigstens teilweise innerhalb der Öffnung (100) im ersten Einkapselungsmittel (80) angeordnet.

Halbleiterbauelement mit einem Verspannungspuffermaterial, das über einem Metallisierungssystem mit kleinem ε gebildet ist

Halbleiterbauelement (200) mit: einem über einem Substrat gebildeten Metallisierungssystem, das mehrere Metallisierungsschichten aufweist, wovon zumindest einige ein dielektrisches Material mit kleinem aufweisen; einer Verspannungspufferschicht (260), die über einer letzten Metallisierungsschicht (140) des Metallisierungssystems (120) gebildet ist, wobei die Verspannungspufferschicht (260) kupferenthaltende Puffergebiete (265) aufweist, die mit kupferenthaltenden Kontaktanschlussflächen (242) in Verbindung stehen, die in der letzten Metallisierungsschicht (140) des Metallisierungssystems (120) vorgesehen und voneinander durch Isoliergräben (266) getrennt sind; bleifreien Kontaktelementen (210), die auf Teilen der kupferenthaltenden Puffergebiete (265) ausgebildet sind; und einem Gehäusesubstrat, das mit dem Metallisierungssystem (120) über die bleifreien Kontaktelemente (210) verbunden ist; und wobei die Verspannungspufferschicht (260) ferner ein dielektrisches Abstandshaltermaterial, das ...

Method and structure for testing a semiconductor wafer prior to performing a flip chip bumping process

An interface assembly 20 and method for testing a semiconductor wafer prior to performing a flip chip bumping process are provided. The interface assembly includes a flip chip bonding pad 24 having a region 28 for performing the bumping process. A test pad 22 is integrally constructed with the bonding pad and includes a probe region 26 for performing wafer-level testing prior to performing the bumping process. The integral construction of the bonding and testing pads avoids, for example, an introduction of propagation delays to test signals passing therethrough, thereby improving the accuracy and reliability of wafer test results. The interface assembly may be used with metal redistribution layers (fig 5: 52, 54) for connecting the metal bonding pad to metal runners, interconnect lines or other pads.

PROCEDURE FOR the VERSCHWEIßEN OF TWO PARTS WITH THE HELP OF a SOLDERING MATERIAL

Semiconductor device and semiconductor packaging structure provided with the same

Buffer layer(s) on stacked structure having via

Semiconductor device and its making method

Enhanced reliability for semiconductor devices using dielectric encasement

A method and device for enhanced reliability for semiconductor devices using dielectric encasement is disclosed. The method and device are directed to improving the reliability of the solder joint that connects the integrated circuit (IC) chip to the substrate. The method comprises applying a layer of a photoimageable permanent dielectric material to a top surface of the semiconductor device, and patterning the layer of the photoimageable permanent dielectric material to have an opening over each feature. The method further comprises dispensing or stencil printing fluxing material into the permanent dielectric material openings, and applying solder, which contains no flux, to a top surface of the fluxing material. In one or more embodiments, the method further comprises heating the semiconductor device to a reflow temperature appropriate for the reflow of the solder, thereby causing the solder to conform to sidewalls of the permanent dielectric material openings to form a protective seal ...

THERMAL MECHANICAL FLIP CHIP DIE BONDING

... 기판에 플립 칩 다이를 본딩하는 열 기계 방법이 제공된다. 플립 칩 다이는 다이에 부착된 구리 부분과 구리 부분에 부착된 본딩 캡을 각기 갖는 복수의 구리 기둥 범프를 포함한다. 상기 방법은 복수의 구리 기둥 범프 각각의 본딩 캡이 기판상의 복수의 본딩 패드 중 대응하는 본딩 패드에 접촉하도록 기판상에 다이를 위치 결정하는 스텝 및 기판에 다이를 서모소닉 본딩하는 스텝을 포함한다.

SENSOR AND METHOD OF PRODUCING THE SAME

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

Solder pillar bumping and a method of making the same

Solderable top metal for SiC device

A silicon carbide device includes at least one power electrode on a surface thereof, a solderable contract formed on the power electrode, and at least one passivation layer that surrounds the solderable contact but is spaced from the solderable contract, thereby forming a gap.

Direct chip attach structure and method

ELECTRONIC STRUCTURE AND STACKED STRUCTURE

SEMICONDUCTOR DEVICE AND METHOD OF FORMING BOND-ON-LEAD INTERCONNECTION FOR MOUNTING SEMICONDUCTOR DIE IN FO-WLCSP

Abstract SEMICONDUCTOR DEVICE AND METHOD OF FORMING BOND-ON-LEAD INTERCONNECTION FOR MOUNTING SEMICONDUCTOR DIE IN FO-WLCSPA semiconductor die has a conductive layer including a plurality of trace lines formed over a carrier. The conductive layer Includes a plurality of contact pads electrically continuous with the trace lines. A semiconductor die has a plurality of contact pads and bumps formed over the contact pads. A plurality of conductive pillars can be formed over the contact pads of the semiconductor die. The bumps are formed over theconductive pillars. The semiconductor die is mounted to the conductive layer with the bumps directly bonded to an end portion of the trace lines to provide a fine pitch Interconnect. An encapsulant is deposited over the semiconductor die and conductive layer. The conductive layer contains wettable material to reduce die shifting during encapsulation. The carrier is removed. An Interconnect structure is formed over the encapsulant and semiconductor die ...

Substrate for element bonding and manufacturing method thereof

The object of the present invention is to provide a substrate for element bonding, capable of bonding element(s) at high strength, which is used for soldering at low temperature a soft solder metal of low melting point, such as a Au-Sn based solder having Au content 10 weight %, to the Au electrode formed on the substrate of aluminum nitride and the like. The substrate for element bonding is characterized by laminating (i) a layer consisting of an element of platinum group, (ii) a layer consisting of at least an element of transition metals selected from the group of Ti, V, Cr and Co, (iii) a barrier metal layer consisting of at least a metal selected from the group of Ag, Cu and Ni, and (iv) a solder layer consisting of a solder containing Sn or In as main ingredient, in sequence, onto the Au electrode layer formed on the surface of a substrate.

Chip having metal pillar structure

The present invention relates to a chip having metal pillar structure. The chip includes a chip body, at least one chip pad, a first passivation layer, an under ball metal layer and at least one metal pillar structure. The chip body has an active surface. The chip pad is disposed on the active surface. The first passivation layer is disposed on the active surface, and has at least one first opening so as to expose part of the chip pad. The under ball metal layer is disposed on the chip pad. The metal pillar structure is disposed on the under ball metal layer, and includes a metal pillar and a solder. The metal pillar is disposed on the under ball metal layer. The solder is disposed on the metal pillar, and the diameter of the solder is smaller than or equals to that of the metal pillar. Therefore, when the pitch between two metal pillar structures of the chip is fine pitch, the problem of solder bridge can be avoided, so that the yield rate is raised.

Conductive bump and electroless Pt plating bath

The present invention provides a bump that can prevent diffusion of a metal used as a base conductive layer of the bump into a surface of an Au layer or an Ag layer. A conductive bump of the present invention is s conductive bump formed on a substrate. The conductive bump comprises, at least in order from the substrate: a base conductive layer; a Pd layer; a Pt layer; and an Au layer or an Ag layer having directly contact with the Pd layer, wherein a diameter of the conductive bump is 20 [mu]m or less.

Method of manufacturing electronic device

A method of manufacturing an electronic device. As non-limiting examples, various aspects of this disclosure provide an electronic device having a top side pin array, for example which may be utilized for three-dimensional stacking, and a method for manufacturing such an electronic device.

METHOD OF FORMING SOLDER BUMP AND METHOD OF MOUNTING SEMICONDUCTOR DEVICE

A method of forming solder bumps that realizes high-density mounting; and a highly reliable method of mounting semiconductor devices. Flat board (10,30) furnished at its surface with multiple protruding parts (12) or concave parts (32) is provided. The flat board is disposed opposite to electronic component (14,34), and resin composition (18,19) containing solder powder (22,23) is fed in an interstice between the flat board and the electronic component. The resin composition is heated so that the solder powder contained in the resin composition is melted. The molten solder powder undergoes self-assembly on terminal parts (16,36) to thereby attain growth up to the surface of the flat board. Thus, on the terminal parts, there are formed solder bumps (24,38). The solder bumps are cooled and solidified, and thereafter the flat board is removed. In this manner, there are formed solder bumps (24,38) having recessed parts (24a) corresponding to the protruding parts (12) or having protrudent parts ...

SOLDERABLE TOP METAL FOR SIC DEVICE

A silicon carbide device includes at least one power electrode on a surface thereof, a solderable contact formed on the power electrode, and at least one passivation layer that surrounds the solderable contact but is spaced from the solderable contact, thereby forming a gap.

ADHESIVE FOR SEMICONDUCTOR, FLUXING AGENT, MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE

Provided is an adhesive for a semiconductor that contains an epoxy resin, a curing agent, and a compound having the group represented by formula (1). [In the formula, R1 indicates an electron-donating group.] ...

Process of making pad structure for solder ball limiting metallurgy having reduced edge stress

A two-step masking process is disclosed for forming a ball limiting metallurgy (BLM) pad structure for a solder joint interconnection used between a support substrate and a semiconductor chip. A solder non-wettable layer and a solder wettable layer are deposited on the surface of a support substrate or semiconductor chip which are to be connected. A phased transition layer is deposited between the wettable and non-wettable layers. A thin photo-resist mask defines an area of the solder wettable and phased layers which are etched to form a raised, wettable frustum cone portion. A second mask is deposited on the surface of the support substrate or semiconductor chip, and has an opening concentrically positioned about the frustum cone. Solder is deposited in the opening and covers the frustum cone and the area about its periphery. When solidified, the solder, acting as a mask, is used to sub-etch the underlying solder non-wettable layer thereby defining the BLM pad. When reflowed, the solder ...

Method of forming bump pad structure having buffer pattern

The method includes forming an upper layer on a lower layer, forming a metal interconnection in the upper layer, forming a passivation layer exposing a center part of the metal interconnection on the upper layer, forming a buffer pattern exposing the center part of the metal interconnection, and selectively and asymmetrically covering a peripheral region of the metal interconnect and a part of the passivation layer, forming a wrapping pattern covering the buffer pattern and exposing the center part of the metal interconnection on the passivation layer, and forming a pad pattern on the center part of the metal interconnection.

Adhesive for connection of circuit member and semiconductor device using the same

An adhesive for connecting circuit members, which is interposed between a semiconductor chip having protruding connecting terminals and a board having wiring patterns formed thereon for electrically connecting the connecting terminals and the wiring patterns facing each other and bonding the semiconductor chip and the board by applying pressure/heat, containing a resin composition containing a thermoplastic resin, a crosslinkable resin and a hardening agent for forming a crosslink structure of the crosslinkable resin; and composite oxide particles dispersed in the resin composition.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

A metal layer is formed on an upper surface of a resin layer provided to cover a plurality of semiconductor chips at a side on which an internal connecting terminal is disposed and the internal connecting terminal, and the metal layer is pressed to cause the metal layer in a corresponding portion to a wiring pattern to come in contact with the internal connecting terminal, and to then bond the metal layer in a portion provided in contact with the internal connecting terminal to the internal connecting terminal in a portion provided in contact with the metal layer.

Thermal mechanical flip chip die bonding

A thermal mechanical process for bonding a flip chip die to a substrate. The flip chip die includes a plurality of copper pillar bumps, each copper pillar bump of the plurality of copper pillar bumps having a copper portion attached to the die and a bonding cap attached to the copper portion. The process includes positioning the die on the substrate such that the bonding cap of each copper pillar bump of the plurality of copper pillar bumps contacts a corresponding respective one of a plurality of bonding pads on the substrate, and thermosonically bonding the die to the substrate.

METHOD OF USING A SACRIFICIAL CONDUCTIVE STACK TO PREVENT CORROSION

A method of fabricating an integrated circuit (IC) chip is disclosed. The method starts with opening a window on a first surface of the IC chip through a passivation overcoat to expose the copper metallization layer. The window has sidewalls and a bottom that is adjacent the copper metallization layer. The method continues with depositing a barrier conductive stack on the passivation overcoat and exposed portions of the copper metallization layer, then depositing a sacrificial conductive stack on the barrier conductive stack. The sacrificial conductive stack has a thickness between 50 Å and 500 Å. The first surface of the semiconductor chip is polished to remove the sacrificial conductive stack and the barrier conductive stack from the surface of the passivation overcoat.

Photoelectric conversion element having a semiconductor and semiconductor device using the same

A semiconductor device, particularly, a photoelectric conversion element having a semiconductor layer is demonstrated. The photoelectric conversion element of the present invention comprises, over a substrate, a photoelectric conversion layer and first and second electrodes which are electrically connected to the photoelectric conversion layer. The photoelectric conversion element further comprises a wiring board over which a third and fourth electrodes are provided. The characteristic point of the present invention is that a bonding layer, which readily forms an alloy with a conductive material, is formed over the first and second electrodes. This bonding layer improves the bonding strength between the first and third electrodes and the second and fourth electrode, which contributes to the prevention of the connection defect between the substrate and the wiring board and consequentially to high reliability of the photoelectric conversion element.

Semiconductor Device with an Improved Solder Joint

A semiconductor device with an improved solder joint system is described. The solder system includes two copper contact pads connected by a body of solder and the solder is an alloy including tin, silver, and at least one metal from the transition groups IIIA, IVA, VA, VIA, VIIA, and VIIIA of the Periodic Table of the Elements. The solder joint system also includes, between the pads and the solder, layers of intermetallic compounds, which include grains of copper and tin compounds and copper, silver, and tin compounds. The compounds contain the transition metals. The inclusion of the transition metals in the compound grains reduce the compound grains size and prevent grain size increases after the solder joint undergoes repeated solid/liquid/solid cycles.

Semiconductor Device and Method of Forming Conductive THV and RDL on Opposite Sides of Semiconductor Die for RDL-to-RDL Bonding

A semiconductor device has a plurality of semiconductor die mounted to a carrier. An encapsulant is deposited over the carrier around a peripheral region of the semiconductor die. A plurality of vias is formed through the encapsulant. A first conductive layer is conformally applied over a sidewall of the vias to form conductive vias. A second conductive layer is formed over a first surface of the semiconductor die between the conductive vias and contact pads of the semiconductor die. The first and second conductive layers can be formed during the same manufacturing process. A third conductive layer is formed over a second surface of the semiconductor die opposite the first surface of the semiconductor die. The third conductive layer is electrically connected to the conductive vias. A plurality of semiconductor die is stacked and electrically connected through the conductive vias and second and third conductive layers.

Semiconductor device and manufacturing method thereof

A semiconductor device includes a substrate and a bump. The substrate includes a first surface and a second surface. A notch is at the second surface and at a sidewall of the substrate. A depth of the notch is smaller than about half the thickness of the substrate. The bump is disposed on the first surface of the substrate.

Lötmetallisierungsstapel und Verfahren zum Bilden desselben

Ein Halbleiterbauelement umfasst eine Kontaktmetallschicht, die über einer Halbleiteroberfläche eines Substrats angeordnet ist, eine über der Kontaktmetallschicht angeordnete Diffusionssperrschicht, eine über der Diffusionssperrschicht angeordnete, inerte Schicht und eine über der inerten Schicht angeordnete Lötschicht.

Elektronikbaugruppe und Verfahren zur Herstellung einer Elektronikbaugruppe

Es werden ein Verfahren zur Herstellung einer Elektronikbaugruppe und eine entsprechend hergestellte Elektronikbaugruppe angegeben. Dabei werden in einem Halbleitersubstrat (10, 10') CMOS-Strukturen (20, 20') zur Bildung eines Schaltkreises ausgebildet, und nach der Ausbildung der CMOS-Strukturen (20, 20') wird zumindest ein elektrischer Leiter (30, 30') in einem Niedertemperaturprozess, insbesondere bei einer Temperatur kleiner 450 DEG C, derart in eine Öffnung des Halbleitersubstrats (10, 10') eingebracht, dass der elektrische Leiter (30, 30') zwischen einer ersten Seite (S1) und einer zweiten, der ersten Seite (S1) gegenüberliegenden Seite (S2) des Halbleitersubstrats (10, 10') zur Verbindung des Schaltkreises ausgebildet wird. Die Elektronikbaugruppe erlaubt eine enge Anordnung von Elektronik und Detektoren (80, 80') und eignet sich insbesondere für ein medizintechnisches Gerät.

Connection method and connection structure of pad electrodes, and inspecting methods for connection state therefor

Semiconductor device and manufacturing method thereof

METHOD FOR MANUFACTURING AND TESTING AN INTEGRATED ELECTRONIC CIRCUIT

SEMICONDUCTOR DEVICE HAS STUDS OF CONNECTION PROVIDED With INSERTS

Dispositif semi-conducteur comprenant un circuit intégré et des plots de connexion électrique extérieure, dans lequel les plots (3) présentent des évidements (E) au moins partiellement remplis par une matière différente de celle les constituant, de façon à former des inserts (I).

SOLDERABLE TOP METAL FOR SIC DEVICE

FLIP CHIP INTERCONNECTION WITH DOUBLE POST

A packaged microelectronic assembly includes a microelectronic element (104) having a front surface (122) and a plurality of first solid metal posts (110) extending away from the front surface (122). Each of the first posts (110) has a width in a direction of the front surface (122) and a height extending from the front surface (122), wherein the height (H2) is at least half of the width (Wl). There is also a substrate (102) having a top surface (101) and a plurality of second solid metal posts (108) extending from the top surface (102) and joined to the first solid metal posts (110).

SUBSTRATE FOR DEVICE BONDING AND METHOD FOR MANUFACTURING SAME

Disclosed is a substrate for device bonding which enables to bond a device with high bonding strength to an Au electrode which is formed on the substrate composed of an aluminum nitride or the like by soldering at a low temperature using a soft solder metal having a low melting point such as an Au-Sn solder with an Au content of 10 weight%. The substrate for device bonding is characterized in that (i) a layer composed of a platinum group element, (ii) a layer composed of at least one transition metal element selected from the group consisting of Ti, V, Cr and Co, (iii) a barrier metal layer composed of at least one metal selected from the group consisting of Ag, Cu and Ni, and (iv) a solder layer composed of a solder mainly containing Sn or In are sequentially formed in this order on an Au electrode layer which is formed over the surface of the substrate for device bonding.

Ball limiting metalization process for interconnection

A two-step masking process is disclosed for forming a ball limiting metallurgy (BLM) pad structure for a solder joint interconnection used between a support substrate and a semiconductor chip. A solder non-wettable layer and a solder wettable layer are deposited on the surface of a support substrate or semiconductor chip which are to be connected. A phased transition layer is deposited between the wettable and non-wettable layers. A thin photo-resist mask defines an area of the solder wettable and phased layers which are etched to form a raised, wettable frustum cone portion. A second mask is deposited on the surface of the support substrate or semiconductor chip, and has an opening concentrically positioned about the frustum cone. Solder is deposited in the opening and covers the frustum cone and the area about its periphery. When solidified, the solder, acting as a mask, is used to sub-etch the underlying solder non-wettable layer thereby defining the BLM pad. When reflowed, the solder ...

Packaging conductive structure for a semiconductor substrate having a metallic layer

A packaging conductive structure for a semiconductor substrate and a method for forming the structure are provided. The dielectric layer of the packaging conductive structure partially overlays the metallic layer of the semiconductor substrate and has a receiving space. The lifting layer and conductive layer are formed in the receiving space, wherein the conductive layer extends for connection to a bump. The lifting layer is partially connected to the dielectric layer. As a result, the conductive layer can be stably deposited on the edge of the dielectric layer for enhancing the reliability of the packaging conductive structure.

Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask

A semiconductor device has a semiconductor die with an die bump pad and substrate with a trace line and integrated bump pad. Conductive bump material is deposited on the substrate bump pad or die bump pad. The semiconductor die over the substrate so that the bump material is disposed between the die bump pad and substrate bump pad. The bump material is reflowed without a solder mask around the die bump pad or substrate bump pad to form an interconnect. The bump material is self-confined within a footprint of the die bump pad or substrate bump pad. The bump material can be immersed in a flux solution prior to reflow to increase wettability. Alternatively, the interconnect includes a non-fusible base and fusible cap. The volume of bump material is selected so that a surface tension maintains self-confinement of the bump material within the bump pads during reflow.

PB-FREE SOLDER BUMPS WITH IMPROVED MECHANICAL PROPERTIES

A method of forming a semiconductor device is disclosed. A semiconductor substrate is provided that has a first contact and an undoped electroplated lead-free solder bump (610) formed thereon. A device package substrate is provided that has a second contact and a doped lead-free solder layer (510) on the second contact that includes a dopant. The dopant reduces a solidification undercooling temperature of the undoped lead-free solder bump when the dopant is incorporated into the lead-free solder bump. The undoped electroplated lead-free solder bump and the doped lead-free solder layer are melted thereby incorporating the dopant into the undoped lead-free solder to form a doped solder bump (140). The solder bump provides an electrical connection between the first contact and the second contact.

Semiconductor device having flange structure

A semiconductor device may include a semiconductor element. A layer of material may be provided on the semiconductor element which may have an opening through which a bond pad may be exposed. At least one flange structure may be provided on the first bond pad, the at least one flange structure made of at least two metal layers with different etch rates.

Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask

A semiconductor device has a semiconductor die with a die bump pad and substrate with a trace line and integrated bump pad. Conductive bump material is deposited on the substrate bump pad or die bump pad. The semiconductor die is mounted over the substrate so that the bump material is disposed between the die bump pad and substrate bump pad. The bump material is reflowed without a solder mask around the die bump pad or substrate bump pad to form an interconnect. The bump material is self-confined within a footprint of the die bump pad or substrate bump pad. The bump material can be immersed in a flux solution prior to reflow to increase wettability. Alternatively, the interconnect includes a non-fusible base and fusible cap. The volume of bump material is selected so that a surface tension maintains self-confinement of the bump material within the bump pads during reflow.

Verfahren zum Verschweißen von zwei Teilen mit Hilfe eines Lötmaterials

Semiconductor device

As a discrete semiconductor chip, there has been known one that enables flip-chip mounting by providing first and second electrodes in a current path above a first surface of a semiconductor substrate. However, there is a problem that a horizontal current flow in the substrate increases resistance components. A first electrode and a second electrode, which are connected to an element region, are provided above a first surface. Moreover, a thick metal layer having corrosion resistance and oxidation resistance and also having a low resistance is provided above a second surface. Thus, resistancecomponents of a current flowing in a horizontal direction of a substrate are reduced. Moreover, by appropriately selecting a thickness of the thick metal layer, a resistance value of a device can be reduced while suppressing a cost increase. Furthermore, by adopting Au as the thick metal layer, defects such as discoloration of the thick metal layer with time can be prevented.

TEST AND MANUFACTORING PROCESS Of a JUST ELECTRONIC CIRCUIT

INTEGRATED CIRCUIT HAVING BOND PAD WITH IMPROVED THERMAL AND MECHANICAL PROPERTIES

CIRCUIT CONNECTING MATERIAL, CONNECTION STRUCTURE AND METHOD FOR PRODUCING THE SAME

Microelectronic packages with dual or multiple-etched flip-chip connectors

A packaged microelectronic element includes a microelectronic element having a front surface and a plurality of first solid metal posts extending away from the front surface. A substrate has a major surface and a plurality of conductive elements exposed at the major surface and joined to the first solid metal posts. In particular examples, the conductive elements can be bond pads or can be second posts having top surfaces and edge surfaces extending at substantial angles away therefrom. Each first solid metal post includes a base region adjacent the microelectronic element and a tip region remote from the microelectronic element, the base region and tip region having respective concave circumferential surfaces. Each first solid metal post has a horizontal dimension which is a first function of vertical location in the base region and which is a second function of vertical location in the tip region.

Semiconductor device

There is provided a semiconductor device with which stress can be prevented from locally concentrating on an external connecting terminal on a post and thus damages of the external connecting terminal can be prevented. The semiconductor device includes a semiconductor chip, a sealing resin layer stacked on a surface of the semiconductor chip, and the post which penetrates the sealing resin layer in a stacking direction of the semiconductor chip and the sealing resin layer, protrudes from the sealing resin layer, and has a periphery of the protruding portion opposedly in contact with a surface of the sealing resin layer in the stacking direction.

Semiconductor device having pad structure with stress buffer layer

A semiconductor device has a pad structure with a ring-shaped stress buffer layer between a metal pad and an under-bump metallization (UBM) layer. The stress buffer layer is formed of a dielectric layer with a dielectric constant less than 3.5, a polymer layer, or an aluminum layer. The stress buffer layer is a circular ring, a square ring, an octagonal ring, or any other geometric ring.

Bond pad for wafer and package for cmos imager

An electronic packaging having at least one bond pad positioned on a chip for effectuating through-wafer connections to an integrated circuit. The electronic package is equipped with an edge seal between the bond pad region and an active circuit region, and includes a crack stop, which is adapted to protect the arrangement from the entry of deleterious moisture and combination into the active regions of the chip containing the bond pads.

Conductive feature for semiconductor substrate and method of manufacture

A conductive feature on a semiconductor component is disclosed. A first passivation layer is formed over a substrate. A bond pad is formed over the first passivation layer. A second passivation layer overlies the first passivation layer and the bond pad. The second passivation layer has a first opening overlying the bond pad and a plurality of second openings exposing a top surface of the first passivation layer. A buffer layer overlies the second passivation layer and fills the plurality of second openings. The buffer layer has a third opening overlapping the first opening and together exposes a portion the bond pad. The combined first opening and third opening has sidewalls. An under bump metallurgy (UBM) layer overlies the sidewalls of the combined first opening and third opening, and contacts the exposed portion of the bond pad. A conductive feature overlies the UBM layer.

Method of manufacturing semiconductor device including plural semiconductor chips stacked together

Such a method is disclosed that includes preparing first and second semiconductor chips, the first semiconductor chip including a first electrode formed on one surface thereof and a second electrode formed on the other surface thereof so as to overlap the first electrode as viewed from a stacking direction, and the second semiconductor chip including a third electrode formed on one surface thereof and a fourth electrode formed on the other surface thereof so as not to overlap the third electrode as viewed from the stacking direction, and stacking the first and second semiconductor chips in the stacking direction so that the second electrode is connected to the third electrode by using a bonding tool including a concave at a position corresponding to the fourth electrode.

Semiconductor Device and Method of Forming a Wafer Level Package Structure Using Conductive Via and Exposed Bump

A semiconductor device has a carrier. A semiconductor wafer including a semiconductor die is mounted to the carrier with an active surface of the semiconductor die facing away from the carrier. A plurality of bumps is formed over the active surface of the semiconductor die. An opening is formed in a periphery of the semiconductor die. An encapsulant is deposited over the carrier and semiconductor die, in the opening, and around the plurality of bumps such that an exposed portion of the plurality of bumps is devoid of encapsulant. A conductive via is formed through the encapsulant, within the opening, and extends to the carrier. A conductive layer is formed over the encapsulant and electrically connects to the conductive via and the exposed portion of the plurality of bumps. The carrier is removed to expose an end of the conductive via.

Semiconductor apparatus, method for manufacturing the same and electric device

A semiconductor apparatus includes: a semiconductor device including a first electrode; a substrate including a second electrode and a recess; and a heat-dissipating adhesive material to set the semiconductor device in the recess so as to arrange the first electrode close to the second electrode, wherein the first electrode is coupled to the second electrode and the heat-dissipating adhesive material covers a bottom surface and at least part of a side surface of the semiconductor device.

Semiconductor Device and Method of Forming Stacked Vias Within Interconnect Structure for FO-WLCSP

A semiconductor device has a semiconductor die mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A first insulating layer is formed over the encapsulant and semiconductor die. First vias are formed through the first insulating layer to expose contact pads of the semiconductor die. A first conductive layer is formed over the first insulating layer and into the first vias to electrically connect to the contact pads of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. Second vias are formed through the second insulating layer by laser direct ablation and aligned or offset with the first vias to expose the first conductive layer. A second conductive layer is formed over the second insulating layer and into the second vias. Conductive vias can be formed through the encapsulant.

Post-passivation interconnect structure and method of forming the same

A semiconductor device includes a conductive layer formed on the surface of a post-passivation interconnect (PPI) structure by an immersion tin process. A polymer layer is formed on the conductive layer and patterned with an opening to expose a portion of the conductive layer. A solder bump is then formed in the opening of the polymer layer to electrically connect to the PPI structure.

Semiconductor Device and Method of Forming RDL Under Bump for Electrical Connection to Enclosed Bump

A semiconductor device has a semiconductor wafer with a plurality of semiconductor die. A first conductive layer is formed over a surface of the wafer. A first insulating layer is formed over the surface of the wafer and first conductive layer. A second conductive layer has first and second segments formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and second conductive layer. A UBM layer is formed over the second insulating layer and the first segment of the second conductive layer. A first bump is formed over the UBM layer. The first bump is electrically connected to the second segment and electrically isolated from the first segment of the second conductive layer. A second bump is formed over the surface of the wafer and electrically connected to the first segment of the second conductive layer.

Wafer Level Semiconductor Package

There are disclosed herein various implementations of improved wafer level semiconductor packages. One exemplary implementation comprises forming a post-fabrication redistribution layer (post-Fab RDL) between first and second dielectric layers affixed over a surface of a wafer, and forming a window for receiving an electrical contact body in the second dielectric layer, the window exposing the post-Fab RDL. At least one of the first and second dielectric layers is a pre-formed dielectric layer, which may be affixed over the surface of the wafer using a lamination process. In one implementation, the window is formed using a direct laser ablation process.

Semiconductor device and method for production of semiconductor device

A semiconductor device with a connection pad in a substrate, the connection pad having an exposed surface made of a metallic material that diffuses less readily into a dielectric layer than does a metal of a wiring layer connected thereto.

Semiconductor device and method for manufacturing the same

The present invention relates to a semiconductor device and a method for making the same. The semiconductor device includes a substrate, a first redistribution layer and a conductive via. The substrate has a substrate body and a pad. The pad and the first redistribution layer are disposed adjacent to the first surface of the substrate body, and electrically connected to each other. The interconnection metal is disposed in a through hole of the substrate body, and contacts the first redistribution layer. Whereby, the pad can be electrically connected to the second surface of the substrate body through the first redistribution layer and the conductive via.

Contact Test Structure and Method

A system and method for testing electrical connections is provided. In an embodiment one or more floating pads may be manufactured in electrical connection with an underbump metallization structure. A test may then be performed to measure the electrical characteristics of the underbump metallization structure through the floating pad in order to test for defects. Alternatively, a conductive connection may be formed on the underbump metallization and the test may be performed on the conductive connection and the underbump metallization together.

Method of manufacturing a semiconductor integrated circuit device

The TSV technology has been popular as one of stacking technologies of a plurality of semiconductor chips. It has however been revealed by the present inventors that when TSV is formed using a so-called first via process, via middle process, front-via via last process, or the like, there is a possibility of defects such as gate breakdown occurring due to electrostatic breakdown in the subsequent process. In order to overcome the above problem, the present invention provides a method of manufacturing a semiconductor integrated circuit device, in which a through via electrode is formed by forming a hole in a semiconductor substrate, forming an insulating member in the hole, and burying a conductive member in the resulting hole while covering a portion of the hole except for the bottom portion with the insulating member.

Cleaning Methods and Compositions

Methods and chemical solvents used for cleaning residues on metal contacts during a semiconductor device packaging process are disclosed. A chemical solvent for cleaning a residue formed on a metal contact may comprise a reactive inorganic component and a reactive organic component. The method may comprise spraying a semiconductor device with a chemical solvent at a first pressure, and spraying the semiconductor device with the chemical solvent at a second pressure less than the first pressure.

Semiconductor integrated circuit device

In semiconductor integrated circuit devices for vehicle use, an aluminum pad on a semiconductor chip and an external device are coupled to each other by wire bonding using a gold wire for the convenience of mounting. Such a semiconductor integrated circuit device, however, causes a connection failure due to the interaction between aluminum and gold in use for a long time at a relatively high temperature (about 150 degrees C.). A semiconductor integrated circuit device can include a semiconductor chip as a part of the device, an electrolytic gold plated surface film (gold-based metal plated film) provided over an aluminum-based bonding pad on a semiconductor chip via a barrier metal film, and a gold bonding wire (gold-based bonding wire) for interconnection between the plated surface film and an external lead provided over a wiring board (wiring substrate).

Discrete semiconductor device package and manufacturing method

Disclosed is a discrete semiconductor device package ( 100 ) comprising a semiconductor die ( 110 ) having a first surface and a second surface opposite said first surface carrying a contact ( 112 ); a conductive body ( 120 ) on said contact; an encapsulation material ( 130 ) laterally encapsulating said conductive body; and a capping member ( 140, 610 ) such as a solder cap, a further semiconductor die or a combination thereof in conductive contact with the solder portion, said solder cap extending over the encapsulation material. A further solder cap ( 150 ) may be provided over the first surface. A method of manufacturing such a discrete semiconductor device package is also disclosed.

Semiconductor chip with expansive underbump metallization structures

Methods and apparatus to protect fragile dielectric layers in a semiconductor chip are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first polymer layer over a conductor pad of a semiconductor chip where the conductor pad has a first lateral dimension. An underbump metallization structure is formed on the first polymer layer and in ohmic contact with the conductor pad. The underbump metallization structure has a second lateral dimension greater than the first lateral dimension. A second polymer layer is formed on the first polymer layer with a first opening exposing at least a portion of the underbump metallization structure.

Methods and Apparatus of Packaging Semiconductor Devices

Methods and apparatuses for wafer level packaging (WLP) semiconductor devices are disclosed. A redistribution layer (RDL) is formed on a first passivation layer in contact with a conductive pad over a surface of a die. The RDL layer is on top of a first region of the first passivation layer. A second passivation layer is formed on the RDL layer with an opening to expose the RDL layer, and over the first passivation layer. An under bump metallization (UBM) layer is formed over the second passivation layer in contact with the exposed RDL layer. A second region of the first passivation layer disjoint from the first region is determined by projecting an outer periphery of a solder ball or other connector onto the surface.

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

In a method of manufacturing a semiconductor device, a semiconductor chip has first and second pads, a passivation film formed such that respective parts of the first and second pads are exposed, a first surface-metal-layer provided on the part of the first pad and a part of the passivation film, and a second surface-metal-layer provided on the part of the second pad and another part of the passivation film. Respective wires are electrically connected to the first and second surface-metal-layers. The semiconductor chip and the respective wires are then sealed with a resin. 1. A method of manufacturing a semiconductor device , comprising: a main surface on which a first pad and a second pad arranged next to the first pad are provided,', 'a passivation film formed on the main surface of the semiconductor chip such that a first part of the first pad and a second part of the second pad are exposed from the passivation film,', 'a first surface-metal layer provided over the first part of the first pad and a first part of the passivation film, and', 'a second surface-metal layer provided over the second part of the second pad and a second part of the passivation film,, '(a) providing a semiconductor chip havingwherein, in plan view, a width of the first surface-metal layer is less than a width of the first pad,wherein, in plan view, a width of the second surface-metal layer is less than a width of the second pad,wherein the width of each of the first surface-metal layer, the second surface-metal layer, the first pad and the second pad is a respective dimension along the main surface of the semiconductor chip and, in plan view, in a direction along which the first pad and the second pad are arranged,wherein the passivation film has a third part located between the first pad and the second pad in cross-section view, andwherein, in cross-section view, a surface of the third part is located closer to the main surface of the semiconductor chip than a surface of the first part ...

Methods and Apparatus of Packaging Semiconductor Devices

Methods and apparatuses for wafer level packaging (WLP) semiconductor devices are disclosed. A redistribution layer (RDL) is formed on a first passivation layer in contact with a conductive pad over a surface of a die. The RDL layer is on top of a first region of the first passivation layer. A second passivation layer is formed on the RDL layer with an opening to expose the RDL layer, and over the first passivation layer. An under bump metallization (UBM) layer is formed over the second passivation layer in contact with the exposed RDL layer. A second region of the first passivation layer disjoint from the first region is determined by projecting an outer periphery of a solder ball or other connector onto the surface. 1. A semiconductor device comprising:a contact pad over a substrate;a redistribution layer in electrical connection with the contact pad;a passivation layer over the redistribution layer;an underbump metallization extending through the passivation layer to be in physical contact with a surface of the redistribution layer facing away from the substrate; anda solder ball in physical contact with the underbump metallization, wherein the solder ball is laterally separated from the redistribution layer in a direction parallel with a major surface of the substrate.2. The semiconductor device of claim 1 , wherein the underbump metallization comprises a reflowable material along a top surface of the underbump metallization.3. The semiconductor device of claim 1 , wherein the underbump metallization extends through the passivation layer at two or more locations.4. The semiconductor device of claim 1 , wherein the redistribution layer comprises a plurality of sub-layers.5. The semiconductor device of claim 1 , wherein the underbump metallization comprises a plurality of sub-layers.6. The semiconductor device of claim 1 , wherein the underbump metallization comprises a plurality of connection branches.7. The semiconductor device of claim 1 , wherein a sidewall of ...

Repackaged integrated circuit assembly method

A method is provided. The method includes one or more of extracting a die from an original packaged integrated circuit, modifying the extracted die, reconditioning the modified extracted die, placing the reconditioned die into a cavity of a hermetic package base, bonding a plurality of bond wires between reconditioned die pads of the reconditioned die to leads of the hermetic package base or downbonds to create an assembled hermetic package base, and sealing a hermetic package lid to the assembled hermetic package base to create a new packaged integrated circuit. Modifying the extracted die includes removing the one or more ball bonds on the one or more die pads. Reconditioning the modified extracted die includes adding a sequence of metallic layers to bare die pads of the modified extracted die. The extracted die is a fully functional semiconductor die with one or more ball bonds on one or more die pads of the extracted die. 1. A method , comprising:extracting a die from an original packaged integrated circuit, wherein the extracted die is a fully functional semiconductor die with one or more ball bonds on one or more die pads of the extracted die;modifying the extracted die, comprising removing the one or more ball bonds on the one or more die pads; 'adding a sequence of metallic layers to bare die pads of the modified extracted die;', 'reconditioning the modified extracted die, comprisingplacing the reconditioned die into a cavity of a hermetic package base;bonding a plurality of bond wires between reconditioned die pads of the reconditioned die to leads of the hermetic package base or downbonds to create an assembled hermetic package base; andsealing a hermetic package lid to the assembled hermetic package base to create a new packaged integrated circuit.2. The method as recited in claim 1 , wherein bare die pads of the modified extracted die comprises all metallic and chemical residue claim 1 , all ball bonds claim 1 , and all bond wires removed from all die ...

Semiconductor Device and Method of Forming Build-Up Interconnect Structures Over a Temporary Substrate

A semiconductor device has a first build-up interconnect structure formed over a substrate. The first build-up interconnect structure includes an insulating layer and conductive layer formed over the insulating layer. A vertical interconnect structure and semiconductor die are disposed over the first build-up interconnect structure. The semiconductor die, first build-up interconnect structure, and substrate are disposed over a carrier. An encapsulant is deposited over the semiconductor die, first build-up interconnect structure, and substrate. A second build-up interconnect structure is formed over the encapsulant. The second build-up interconnect structure electrically connects to the first build-up interconnect structure through the vertical interconnect structure. The substrate provides structural support and prevents warpage during formation of the first and second build-up interconnect structures. The substrate is removed after forming the second build-up interconnect structure. A portion of the insulating layer is removed exposing the conductive layer for electrical interconnect with subsequently stacked semiconductor devices. 1. A method of making a semiconductor device , comprising:providing a substrate;forming a first interconnect structure over the substrate;disposing a first semiconductor die over the first interconnect structure;disposing the substrate over a carrier with the first semiconductor die oriented away from the carrier;depositing an encapsulant over the carrier, substrate, and first semiconductor die;forming a second interconnect structure over the encapsulant and semiconductor die; andremoving the substrate to expose the first interconnect structure after forming the second interconnect structure.2. The method of claim 1 , further including forming a conductive column over the first interconnect structure.3. The method of claim 2 , wherein the conductive column extends from the first interconnect structure to the second interconnect structure ...

Forming Metal Bonds with Recesses

A method includes forming a first device die, which includes depositing a first dielectric layer, and forming a first metal pad in the first dielectric layer. The first metal pad includes a recess. The method further includes forming a second device die including a second dielectric layer and a second metal pad in the second dielectric layer. The first device die is bonded to the second device die, with the first dielectric layer being bonded to the second dielectric layer, and the first metal pad being bonded to the second metal pad. 1. A device comprising: a first dielectric layer; and', a diffusion barrier contacting the first dielectric layer; and', 'a metallic material between opposite portions of the diffusion barrier, wherein in a cross-sectional view of the first metal pad, an edge portion of the metallic material is recessed from a top edge of a nearest portion of the diffusion barrier to form an air gap; and, 'a first metal pad comprising], 'a first device die comprising a second dielectric layer bonded to the first dielectric layer; and', 'a second metal pad bonded to the first metal pad through metal-to-metal direct bonding., 'a second device die comprising2. The device of claim 1 , wherein the air gap further extends into the second metal pad.3. The device of claim 1 , wherein the air gap is formed between a sidewall of the diffusion barrier claim 1 , a surface of the metallic material claim 1 , and a surface of the second metal pad.4. The device of claim 1 , wherein the air gap is formed between a sidewall of the diffusion barrier claim 1 , a surface of the metallic material claim 1 , and a surface of the second dielectric layer.5. The device of claim 1 , wherein a surface of the metallic material in the first metal pad and facing the air gap is rounded.6. The device of claim 1 , wherein a surface of the second metal pad facing the air gap is rounded.7. The device of claim 1 , wherein the first device die further comprises a third metal pad comprising ...

Power semiconductor device and method for manufacturing power semiconductor device

This power semiconductor device is provided with: a substrate; and a semiconductor element which is bonded onto the substrate using a sinterable metal bonding material. The semiconductor element comprises: a base; a first conductive layer that is provided on a first surface of the base, said first surface being on the substrate side; and a second conductive layer that is provided on a second surface of the base, said second surface being on the reverse side of the first surface. The thickness of the first conductive layer is from 0.5 times to 2.0 times (inclusive) the thickness of the second conductive layer.

Semiconductor Device with Shielding Structure for Cross-Talk Reduction

A method includes embedding a die in a molding material; forming a first dielectric layer over the molding material and the die; forming a conductive line over an upper surface of the first dielectric layer facing away from the die; and forming a second dielectric layer over the first dielectric layer and the conductive line. The method further includes forming a first trench opening extending through the first dielectric layer or the second dielectric layer, where a longitudinal axis of the first trench is parallel with a longitudinal axis of the conductive line, and where no electrically conductive feature is exposed at a bottom of the first trench opening; and filling the first trench opening with an electrically conductive material to form a first ground trench.

SEMICONDUCTOR DEVICES HAVING METAL BUMPS WITH FLANGE

A semiconductor device having a terminal site () including a flat pad () of a first metal covered by a layer () of dielectric material, the layer over the pad parallel to the pad and having a window of a first diameter () exposing the surface of the underlying pad. The terminal site further has a patch-shaped film () of a second metal covering the surface of the exposed first metal and the surface of an annulus of the dielectric layer framing the window, the film patch having a second diameter () greater than the first diameter; and a bump () of a third metal adhering to the film, the bump having a third diameter () smaller than the second diameter, whereby the film protrudes like a flange from the bump. 18-. (canceled)9. A method for fabricating a semiconductor chip comprising:providing a semiconductor wafer having a plurality of devices, each device having a plurality of terminal sites;forming a bond pad over each of the plurality of terminal sites, the bond pad being flat and made of a first metal adhering to semiconductor wafer;depositing a layer of dielectric material across the semiconductor wafer covering the bond pads of all terminal sites;patterning the layer of dielectric material over each bond pad to open a window of a first diameter to each bond pad, the window exposing the surface of the underlying bond pad; sputtering a metallic seed layer of a refractory metal over the semiconductor wafer;', 'subsequently patterning the metallic seed layer to form patches of the refractory metal over the window and the surface of the bond pad at each terminal site, the patches having a second diameter greater than the first diameter; and', 'using the patches as a seed material, plating to form the flange on the bond pad at each terminal site, the flange being a film of a second metal adhering to the first metal as well as to the layer of dielectric material; and, 'forming a flange for bumps on each bond pad; comprisingforming a bump of a third metal on each flange, ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

An improvement is achieved in the reliability of a semiconductor device. Over a semiconductor substrate, an interlayer insulating film is formed and, over the interlayer insulating film, a pad is formed. Over the interlayer insulating film, an insulating film is formed so as to cover the pad. In the insulating film, an opening is formed to expose a part of the pad. The pad is a pad to which a copper wire is to be electrically coupled and which includes an Al-containing conductive film containing aluminum as a main component. Over the Al-containing conductive film in a region overlapping the opening in plan view, a laminated film including a barrier conductor film, and a metal film over the barrier conductor film is formed. The metal film is in an uppermost layer. The barrier conductor film is a single-layer film or a laminated film including one or more layers of films selected from the group consisting of a Ti film, a TiN film, a Ta film, a TaN film, a W film, a WN film, a TiW film, and a TaW film. The metal film is made of one or more metals selected from the group consisting of Pd, Au, Ru, Rh, Pt, and Ir. 1. A semiconductor device , comprising:a semiconductor substrate;a first insulating film formed over the semiconductor substrate;a pad formed over the first insulating film;a second insulating film formed over the first insulating film so as to cover the pad; andan opening formed in the second insulating film to expose a part of the pad,wherein the pad is a pad to which a copper wire is to be electrically coupled and which includes an Al-containing conductive film containing aluminum as a main component,wherein, over the Al-containing conductive film in a region overlapping the opening in plan view, a first laminated film including a first conductor film, and a second conductor film over the first conductor film is formed,wherein the second conductor film is in an uppermost layer of the first laminated film,wherein the first conductor film is a single-layer film ...

PRE-PLATED SUBSTRATE FOR DIE ATTACHMENT

A method for attaching a semiconductor die to a substrate includes providing a substrate that includes an attachment layer at a surface of the substrate. The attachment layer is covered by a protective flash plating layer. The protective flash plating layer has a reflow temperature less than or equal to a reflow temperature of the attachment layer. The method further includes preheating the substrate to a temperature greater than or equal to a reflow temperature of the attachment layer, attaching a semiconductor die to the attachment layer, and cooling the substrate and semiconductor die. 19-. (canceled)10. A method of preparing a substrate for attachment to a semiconductor die , the method comprising:providing a substrate;selectively forming an attachment layer on a surface of the substrate at one or more die attachment locations, the attachment layer having a reflow temperature; andcovering the attachment layer with a protective flash plating layer, the protective flash plating layer having a reflow temperature that is less than or equal to the reflow temperature of the attachment layer.11. The method of claim 10 , wherein the formation of the attachment layer includes selectively plating one or more attachment stacks to the surface of the substrate at the one or more die attachment locations.12. The method of claim 10 , wherein the formation of the attachment layer includes selectively stamping one or more attachment preforms onto the surface of the substrate at the one or more die attachment locations.13. The method of claim 10 , wherein the formation of the attachment layer includes spot welding one or more attachment preforms at diagonal corners of each of the one or more die attachment locations.14. The method of claim 10 , wherein the formation of the attachment layer includes hot rolling one or more attachment preforms onto the surface of the substrate at the one or more die attachment locations.15. The method of claim 10 , wherein the protective flash ...

Package assembly

In some embodiments, the present disclosure relates to a package assembly having a bump on a first substrate. A molding compound is on the first substrate and contacts sidewalls of the bump. A no-flow underfill layer is on a conductive region of a second substrate. The no-flow underfill layer and the conductive region contact the bump. A mask layer is arranged on the second substrate and laterally surrounds the no-flow underfill layer. The no-flow underfill layer contacts the substrate between the conductive region and the mask layer.

Interconnect structures for assembly of semiconductor structures including superconducting integrated circuits

A multi-layer semiconductor structure includes a first semiconductor structure and a second semiconductor structure, with at least one of the first and second semiconductor structures provided as a superconducting semiconductor structure. The multi-layer semiconductor structure also includes one or more interconnect structures. Each of the interconnect structures is disposed between the first and second semiconductor structures and coupled to respective ones of interconnect pads provided on the first and second semiconductor structures. Additionally, each of the interconnect structures includes a plurality of interconnect sections. At least one of the interconnect sections includes at least one superconducting and/or a partially superconducting material.

Interconnect structures with intermetallic palladium joints and associated systems and methods

Interconnect structures with intermetallic palladium joints are disclosed herein. In one embodiment, a method of forming an interconnect structure includes depositing a first conductive material comprising nickel on a first conductive surface of a first die, and depositing a second conductive material comprising nickel on a second conductive surface of a second die spaced apart from the first surface. The method further includes depositing a third conductive material on the second conductive material, and thermally compressing tin/solder between the first and third conductive materials to form an intermetallic palladium joint that extends between the first conductive material and the second conductive material such that one end of the intermetallic palladium joint is bonded directly to the first conductive material and an opposite end of the intermetallic palladium joint is bonded directly to the second conductive material.

CHIP PARTS AND METHOD FOR MANUFACTURING THE SAME, CIRCUIT ASSEMBLY HAVING THE CHIP PARTS AND ELECTRONIC DEVICE

A chip part according to the present invention includes a substrate having a penetrating hole, a pair of electrodes formed on a front surface of the substrate and including one electrode overlapping the penetrating hole in a plan view and another electrode facing the one electrode, and an element formed on the front surface side of the substrate and electrically connected to the pair of electrodes. 1. A bidirectional Zener diode chip , comprising:a semiconductor substrate of a first conductivity type;an insulating film which covers a front surface of the semiconductor substrate;a first diffusion region of a second conductivity type formed in the semiconductor substrate and exposed at the front surface of the semiconductor substrate;a second diffusion region of the second conductivity type formed in the semiconductor substrate across an interval from the first diffusion region and exposed at the front surface of the semiconductor substrate;contact holes in the insulating film for selectively exposing the first diffusion region and the second diffusion region through the insulating film;a first electrode formed on the front surface of the semiconductor substrate and connected to the first diffusion region; anda second electrode formed on the front surface of the semiconductor substrate and connected to the second diffusion region,wherein the first electrode includes a plurality of first extraction electrodes which are defined to cover the first diffusion region,wherein the second electrode includes a plurality of second extraction electrodes which are defined to cover the second diffusion region along the second extraction electrodes extending parallel to the first extraction electrodes in a lengthwise direction as viewed from a plan view,wherein the plurality of first extraction electrodes and the plurality of second extraction electrodes are defined in a comb-toothed shape engaging with each other,wherein a shape of the contact holes is an elongated shape in the ...

DUAL BOND PAD STRUCTURE FOR PHOTONICS

A dual bond pad structure for a wafer with laser die attachment and methods of manufacture are disclosed. The method includes forming a bonding layer on a surface of a substrate. The method further includes forming solder bumps on the bonding layer. The method further includes patterning the bonding layer to form bonding pads some of which comprise the solder bumps thereon. The method further includes attaching a laser diode to selected bonding pads using solder connections formed on the laser diode. The method further includes attaching an interposer substrate to the solder bumps formed on the bonding pads. 1. A method , comprising:forming a masking layer over a bonding layer;patterning the bonding layer to form bonding pads;attaching a laser diode to selected bonding pads using solder connections formed on the laser diode such that the laser diode is unobstructed by solder bumps and the selected bonding pads; andattaching an interposer substrate to the solder bumps which are on the bonding pads such that the interposer substrate is spaced away and disconnected from the laser diode.2. The method of claim 1 , wherein the masking layer is formed over portions of the bonding layer which are to be attached to the laser diode.3. The method of claim 1 , wherein the solder bumps are formed through a resist pattern claim 1 , after the forming of the masking layer over the bonding layer.4. The method of claim 1 , further comprising forming the solder bumps on the bonding layer.5. The method of claim 4 , wherein the patterning of the bonding layer is performed after the forming of the solder bumps such that the solder bumps and the masking layer protect underlying portions of the bonding layer during an etching process.6. The method of claim 5 , further comprising removing the masking layer and attaching the solder connections formed on the laser diode directly to the bonding pads which are formed underneath the masking layer prior to removal.7. The method of claim 6 , ...

CONDUCTIVE CONNECTIONS, STRUCTURES WITH SUCH CONNECTIONS, AND METHODS OF MANUFACTURE

A solder connection may be surrounded by a solder locking layer () and may be recessed in a hole () in that layer. The recess may be obtained by evaporating a vaporizable portion () of the solder connection. Other features are also provided. 1. A manufacturing method comprising: one or more first components each of which comprises solder and a material sublimatable or vaporizable when the solder is melted; and', 'a first layer comprising a top surface and one or more holes in the top surface, each hole containing at least a segment of a corresponding first component;, 'obtaining a first structure comprisingheating each first component to sublimate or vaporize at least part of each sublimatable or vaporizable material and provide an electrically conductive connection at a location of each first component;wherein in the heating operation at least part of each first component recedes down from the top surface to provide or increase a recess in each hole at the top surface.2. The method of wherein each hole is a through-hole.3. The method of wherein each hole's sidewall is a dielectric sidewall.4. The method of wherein the first layer is dielectric.5. The method of wherein the first layer is formed by molding.6. The method of further comprising:obtaining a second structure with one or more protruding conductive posts; andinserting each conductive post into a corresponding recess provided or increased in the heating operation, and forming a solder bond in each recess between the corresponding conductive post and the corresponding electrically conductive connection.7. The method of wherein before the heating operation claim 1 , at least a segment of each first component either:comprises of a solder core coated with the sublimatable or vaporizable material; orconsists of the sublimatable or vaporizable material.8. The method of wherein in obtaining the first structure claim 7 , the one or more first components are formed before the first layer.9. The method of wherein in ...

Method for processing an electronic component and an electronic component

According to various embodiments an electronic component includes: at least one electrically conductive contact region; a contact pad including a self-segregating composition disposed over the at least one electrically conductive contact region; a segregation suppression structure disposed between the contact pad and the at least one electrically conductive contact region, wherein the segregation suppression structure includes more nucleation inducing topography features than the at least one electrically conductive contact region for perturbing a chemical segregation of the self-segregating composition by crystallographic interfaces of the contact pad defined by the nucleation inducing topography features.

SURFACE FINISHES FOR INTERCONNECTION PADS IN MICROELECTRONIC STRUCTURES

A surface finish may be formed in a microelectronic structure, wherein the surface finish may include a multilayer interlayer structure. Thus, needed characteristics, such as compliance and electro-migration resistance, of the interlayer structure may be satisfied by different material layers, rather attempting to achieve these characteristics with a single layer. In one embodiment, the multilayer interlayer structure may comprises a two-layer structure, wherein a first layer is formed proximate a solder interconnect and comprises a material which forms a ductile joint with the solder interconnect, and a second layer comprising a material having strong electro-migration resistance formed between the first layer and an interconnection pad. In a further embodiment, third layer may be formed adjacent the interconnection pad comprising a material which forms a ductile joint with the interconnection pad. 125.-. (canceled)26. A microelectronic structure , comprising:an interconnection pad;a surface finish on the interconnection pad, wherein the surface finish comprises a multilayer interlayer structure including at least one ductile layer and at least one electro-migration resistant layer; anda solder interconnect on the surface finish.27. The microelectronic structure of claim 26 , wherein the at least one ductile layer comprises a nickel material having phosphorus content of between about 2% and 10% by weight.28. The microelectronic structure of claim 26 , wherein the at least one electro-migration resistant layer comprises a nickel material having phosphorus content of between about 11% and 20% by weight.29. The microelectronic structure of claim 26 , wherein the at least one electro-migration resistant layer comprises a high atomic weight metal.30. The microelectronic structure of claim 29 , wherein the high atomic weight metal is selected from the group consisting of nickel claim 29 , cobalt claim 29 , and iron.31. The microelectronic structure of claim 26 , wherein ...

PACKAGE WITH METAL-INSULATOR-METAL CAPACITOR AND METHOD OF MANUFACTURING THE SAME

A package includes a chip formed in a first area of the package and a molding compound formed in a second area of the package adjacent to the first area. A first polymer layer is formed on the chip and the molding compound, a second polymer layer is formed on the first polymer layer, and a plurality of interconnect structures is formed between the first polymer layer and the second polymer layer. A metal-insulator-metal (MIM) capacitor is formed on the second polymer layer and electrically coupled to at least one of the plurality of interconnect structures. A metal bump is formed over and electrically coupled to at least one of the plurality of interconnect structures. 1. A package comprising:a chip and a molding compound adjacent to each other;a first polymer layer and a second polymer layer that are stacked on the chip and the molding compound, wherein the second polymer layer overlies the first polymer layer;a first interconnect structure between the first and second polymer layers;a capacitor on the second polymer layer and protruding through the second polymer layer to the first interconnect structure, wherein the capacitor comprises a lower electrode, a dielectric layer overlying the lower electrode, and an upper electrode overlying the dielectric layer;a barrier layer overlying and independent of the upper electrode, wherein the barrier layer is conductive;a metal layer overlying the barrier layer, wherein the capacitor, the barrier layer, and the metal layer collectively define a first common sidewall and collectively define a second common sidewall on an opposite side of the capacitor as the first common sidewall;an isolation coating covering the first and second polymer layers and the metal layer, wherein the isolation coating directly contacts a top surface of the metal layer continuously from the first common sidewall to the second common sidewall; anda conductive bump in an opening defined by the isolation coating and level with the capacitor.2. The ...

Semiconductor product with interlocking metal-to-metal bonds and method for manufacturing thereof

A structure and method for performing metal-to-metal bonding in an electrical device. For example and without limitation, various aspects of this disclosure provide a structure and method that utilize an interlocking structure configured to enhance metal-to-metal bonding.

CONDUCTIVE BUMP AND ELECTROLESS Pt PLATING BATH

The present invention provides a bump that can prevent diffusion of a metal used as a base conductive layer of the bump into a surface of an Au layer or an Ag layer. A conductive bump of the present invention is a conductive bump formed on a substrate. The conductive bump comprises, at least in order from the substrate: a base conductive layer; a Pd layer; a Pt layer; and an Au layer or an Ag layer having directly contact with the Pd layer, wherein a diameter of the conductive bump is 20 μm or less.

Semiconductor Chip and Method for Forming a Chip Pad

A semiconductor chip with different chip pads and a method for forming a semiconductor chip with different chip pads are disclosed. In some embodiments, the method comprises depositing a barrier layer over a chip front side, depositing a copper layer after depositing the barrier layer, and removing a part of the copper layer located outside a first chip pad region, wherein a remaining portion of the copper layer within the first chip pad region forms a surface layer of the chip pad. The method further comprises removing a part of the barrier layer located outside the first chip pad region.

Integrated Circuit Packages and Methods for Forming the Same

A method includes forming an electrical connector over a substrate of a wafer, and molding a polymer layer, with at least a portion of the electrical connector molded in the polymer layer. A first sawing step is performed to form a trench in the polymer layer. After the first sawing step, a second sawing step is performed to saw the wafer into a plurality of dies. 1. A chip comprising:a substrate;a metal pad over the substrate;a passivation layer having a portion over the metal pad;a polymer layer over the passivation layer, wherein the polymer layer extends to an edge of the chip, and a first edge of the polymer layer forms a part of the edge of the chip;an electrical connector; and a first horizontal surface substantially perpendicular to the edge of the chip; and', 'a slant sidewall surface, wherein the first horizontal surface is connected to a first end of the slant sidewall surface, and the slant sidewall surface is neither perpendicular to nor parallel to the edge of the chip., 'a molding compound encircling a portion of the electrical connector, wherein a lower portion of the electrical connector is in the molding compound, and wherein the molding compound comprises a surface comprising2. The chip of further comprising a second horizontal surface substantially perpendicular to the edge of the chip claim 1 , wherein the second horizontal surface is connected to a second end of the slant sidewall surface claim 1 , and the first horizontal surface claim 1 , the slant sidewall surface claim 1 , and the second horizontal surface form a step.3. The chip of claim 1 , wherein the first horizontal surface extends to the electrical connector.4. The chip of further comprising:a plurality of dielectric layers underlying the metal pad; anda seal ring proximal edges of the chip, wherein the seal ring extends into the plurality of dielectric layers.5. The chip of claim 4 , wherein the molding compound comprises:first portions on opposite sides of electrical connector, ...

SEMICONDUCTOR DEVICES, SEMICONDUCTOR PACKAGES, AND METHODS OF MANUFACTURING THE SEMICONDUCTOR DEVICES

A semiconductor device includes a conductive component on a substrate, a passivation layer on the substrate and including an opening that exposes at least a portion of the conductive component, and a pad structure in the opening and located on the passivation layer, the pad structure being electrically connected to the conductive component. The pad structure includes a lower conductive layer conformally extending on an inner sidewall of the opening, the lower conductive layer including a conductive barrier layer, a first seed layer, an etch stop layer, and a second seed layer that are sequentially stacked, a first pad layer on the lower conductive layer and at least partially filling the opening, and a second pad layer on the first pad layer and being in contact with a peripheral portion of the lower conductive layer located on the top surface of the passivation layer. 1. A semiconductor device comprising:a conductive component on a substrate;a passivation layer on the substrate and including an opening therein, wherein the opening exposes at least a portion of the conductive component; and a lower conductive layer conformally extending on an inner sidewall of the opening and on a top surface of the passivation layer around the opening, the lower conductive layer including a conductive barrier layer, a first seed layer, an etch stop layer, and a second seed layer that are sequentially stacked,', 'a first pad layer on the lower conductive layer, the first pad layer at least partially filling the opening, and', 'a second pad layer on the first pad layer, the second pad layer laterally extending beyond the first pad layer to contact a peripheral portion of the lower conductive layer located on the top surface of the passivation layer., 'a pad structure on the passivation layer and in the opening, the pad structure electrically connected to the conductive component, the pad structure comprising2. The semiconductor device of claim 1 , wherein the second pad layer is ...

Al bond pad clean method

Embodiments of the present disclosure provide a method for controlling moisture from substrate being processed. Particularly, embodiments of the present disclosure provide methods for removing moisture from polymer materials adjacent bond pad areas. One embodiment of the present includes providing a moisture sensitive precursor and forming a compound from a reaction between the moisture to be controlled and the moisture sensitive precursor.

HYBRID BONDING WITH THROUGH SUBSTRATE VIA (TSV)

A semiconductor device structure is provided. The semiconductor device structure includes a first polymer layer formed between a first substrate and a second substrate, and a first conductive layer formed over the first polymer. The semiconductor device includes a first through substrate via (TSV) formed over the first conductive layer, and the conductive layer is in direct contact with the first TSV and the first polymer. 1. A semiconductor device structure , comprising:a first polymer layer formed between a first substrate and a second substrate;a first conductive layer formed over the first polymer; anda first through substrate via (TSV) formed over the first conductive layer, wherein the conductive layer is in direct contact with the first TSV and the first polymer.2. The semiconductor device structure as claimed in claim 1 , further comprising:an interconnect structure formed over the first substrate, wherein the interconnect structure is in direct contact with the first TSV.3. The semiconductor device structure as claimed in claim 1 , further comprising:a first transistor formed in the first substrate; anda first contact plug formed below the first transistor, wherein a bottom surface of the first contact plug is level with a bottom surface of the first TSV.4. The semiconductor device structure as claimed in claim 3 , wherein a sidewall of the first contact plug is aligned with a sidewall of the first conductive layer.5. The semiconductor device structure as claimed in claim 1 , further comprising:a second TSV formed in the second substrate, wherein a first width of the first TSV is smaller than a second width of the second TSV.6. The semiconductor device structure as claimed in claim 5 , further comprising:a second polymer layer formed between the first substrate and the second substrate; anda second conductive layer formed below the second polymer layer, wherein the second conductive layer is in direct contact with the second polymer layer and the second TSV ...

PAD STRUCTURE FOR FRONT SIDE ILLUMINATED IMAGE SENSOR

The present disclosure relates to an integrated circuit. The integrated circuit includes a plurality of interconnects within a dielectric structure over a substrate. A passivation structure is arranged over the dielectric structure. The passivation structure has sidewalls connected to one or more upper surfaces of the passivation structure. A bond pad is arranged directly between the sidewalls of the passivation structure. An upper passivation layer is disposed over the passivation structure and the bond pad. The upper passivation layer extends from over an upper surface of the bond pad to within a recess in the upper surface of the bond pad. 1. An integrated circuit , comprising:a plurality of interconnects within a dielectric structure over a substrate;a passivation structure arranged over the dielectric structure and having sidewalls connected to one or more upper surfaces of the passivation structure;a bond pad arranged directly between the sidewalls of the passivation structure; andan upper passivation layer disposed over the passivation structure and the bond pad, wherein the upper passivation layer extends from over an upper surface of the bond pad to within a recess in the upper surface of the bond pad.2. The integrated circuit of claim 1 ,wherein the upper passivation layer comprises both a first sidewall and a second sidewall laterally between the bond pad and the passivation structure; andwherein the first sidewall and the second sidewall of the upper passivation layer face one another and are separated from one another by a non-zero distance.3. The integrated circuit of claim 1 , wherein the upper passivation layer has surfaces defining a ‘U’ shaped segment between an outermost sidewall of the bond pad and one of the sidewalls of the passivation structure.4. The integrated circuit of claim 1 , wherein the passivation structure comprises a first material and a second material over the first material claim 1 , the upper passivation layer having a sidewall ...

Semiconductor device and a method for manufacturing a semiconductor device

According to various embodiments, a semiconductor device may include: at least one first contact pad on a front side of the semiconductor device; at least one second contact pad on the front side of the semiconductor device; a layer stack disposed at least partially over the at least one first contact pad, wherein the at least one second contact pad is at least partially free of the layer stack; wherein the layer stack includes at least an adhesion layer and a metallization layer; and wherein the metallization layer includes a metal alloy and wherein the adhesion layer is disposed between the metallization layer and the at least one first contact pad for adhering the metal alloy of the metallization layer to the at least one first contact pad.

Semiconductor structure and manufacturing method thereof

A semiconductor structure includes a substrate; a first dielectric layer disposed over the substrate; a conductive member surrounded by the first dielectric layer; a second dielectric layer disposed over the substrate, the first dielectric layer and the conductive member; a capacitor disposed over the conductive member and the second dielectric layer; a third dielectric layer disposed over the second dielectric layer and the capacitor; a conductive via disposed over and contacted with the conductive member, and extended through the second dielectric layer, the capacitor and the third dielectric layer; a conductive pad disposed over and contacted with the conductive via; a fourth dielectric layer disposed over the third dielectric layer and surrounding the conductive pad; and a conductive bump disposed over and electrically connected to the conductive pad, wherein the third dielectric layer includes an oxide layer and a nitride layer.

Bonding structure including metal nano particles and bonding method using metal nano particles

A bonding structure including metal nano particles includes a first member having a metal surface on at least one side, a second member having a metal surface on at least one side, the second member being disposed such that the metal surface of the second member faces the metal surface of the first member, and a bonding material bonding the first member and the second member by sinter-bonding the metal nano particles. At least one of the metal surfaces of the first member and the second member is formed to be a rough surface having a surface roughness within the range from 0.5 μm to 2.0 μm.

SUBSTRATE STRUCTURE WITH SELECTIVE SURFACE FINISHES FOR FLIP CHIP ASSEMBLY

The present disclosure relates to a substrate structure with selective surface finishes used in flip chip assembly, and a process for making the same. The disclosed substrate structure includes a substrate body, a metal structure with a first finish area and a second finish area, a first surface finish, and a second surface finish. The metal structure is formed on a top surface of the substrate body, the first surface finish is formed over the first finish area of the metal structure, and the second surface finish is formed over the second finish area of the metal structure. The first surface finish is different from the second surface finish. 1. An apparatus comprising:a substrate body;a first metal structure formed on a top surface of the substrate body and having a first finish area and a second finish area;a first surface finish provided over the first finish area; anda second surface finish that is different from the first surface finish and provided over the second finish area.2. The apparatus of wherein the first surface finish is electroless nickel electroless palladium immersion gold (ENEPIG).3. The apparatus of wherein the first surface finish comprises:a first layer formed of gold with a thickness between 0.06 μm and 0.14 μm;a second layer formed of palladium with a thickness between 0.08 μm and 0.16 μm; anda third layer formed of nickel with a thickness between 0.3 μm and 0.5 μm, wherein the third layer is over the first finish area, the second layer is over the third layer, and the first layer is over the second layer.4. The apparatus of wherein the first surface finish is bussless NiAu or electroless palladium immersion gold (EPIG).5. The apparatus of wherein the second surface finish is an organic surface protectorant (OSP).6. The apparatus of wherein a thickness of the second surface finish is between 0.2 μm and 0.4 μm.7. The apparatus of wherein the first surface finish comprises gold and the second surface finish does not comprise gold.8. The ...

Method of manufacturing semiconductor device

To provide a semiconductor device capable of having improved adhesion between a plating film and a wiring layer. A method of manufacturing the semiconductor device includes a step of forming a wiring layer having a surface covered with an oxide film, a step of removing a portion of the oxide film by dry etching to form, in the oxide film, a first opening f exposing a portion of the wiring layer, a step of forming a passivation film covering the wiring layer, is provided with a second opening communicated with the first opening, and is made of an insulating resin material, and a step of growing a plating film on the wiring layer exposed from the first and second openings.

Semiconductor chip and method of processing a semiconductor chip

Various embodiments provide a semiconductor chip, wherein the semiconductor chip comprises a first contact area and a second contact area both formed at a frontside of the semiconductor chip; a passivation layer arranged at the frontside between the first contact area and the second contact area; and a contact stack formed over the frontside of the semiconductor chip and comprising a plurality of layers, wherein at least one layer of the plurality of layers is removed from the passivation layer and boundary regions of the contact areas being adjacent to the passivation layer and wherein at least one another layer of the plurality of different layer is present in the boundary region of the contact areas adjoining the passivation layer. 1. A semiconductor chip comprising:a contact area formed at a frontside of the semiconductor chip, wherein a passivation layer is arranged at the frontside adjoining the contact area in a boundary region of the contact area;a multilayer metallization stack comprising an adhesion promoter layer, a contact layer and a planar protection layer, wherein the contact layer is arranged between the adhesion promoter layer and the protection layer,wherein only the adhesion promoter layer of the multilayer metallization stack is formed above at least portions of the contact area, the boundary region and portions of the passivation layer and the contact layer and the planar protection layer are formed only above portions of the contact area.2. The semiconductor chip according to claim 1 , wherein the multilayer metallization stack extends over at least portions of the contact area while at the boundary region only the adhesion promoter layer remains claim 1 , so that sidewalls of the contact layer and the planar protection layer are exposed to the boundary region and the adhesion layer extends laterally over the contact area and the passivation layer claim 1 , wherein the passivation layer is partially free of the adhesion layer.3. The ...

Integrated Circuit Structure Having Dies with Connectors of Different Sizes

An embodiment is a structure comprising a substrate, a first die, and a second die. The substrate has a first surface. The first die is attached to the first surface of the substrate by first electrical connectors. The second die is attached to the first surface of the substrate by second electrical connectors. A size of one of the second electrical connectors is smaller than a size of one of the first electrical connectors. 1. A structure comprising:an interposer;a first die on a first surface of the interposer, the first die being electrically and mechanically coupled to the interposer by first connectors, the first connectors having a first diameter and having a first pitch between adjacent ones of the first connectors; and a first under bump metal (UBM) structure on a lower side of the second die facing the interposer;', 'a first metal pillar electrically and mechanically coupled to the first UBM structure;', 'a second UBM structure on the first surface of the interposer;', 'a second metal pillar electrically and mechanically coupled to the second UBM structure; and', 'a solder material between and electrically coupling the first metal pillar and the second metal pillar, wherein sidewalls of the first metal pillar are free of the solder material., 'a second die on the first surface of the interposer, the second die being electrically and mechanically coupled to the interposer by second connectors, the second connectors having a second diameter and having a second pitch between adjacent ones of the second connectors, the first diameter being greater than the second diameter, and the first pitch being greater than the second pitch, wherein each of the second connectors comprises2. The structure of claim 1 , wherein the solder material extends along sidewalls of the second metal pillar toward the first surface of the interposer.3. The structure of claim 2 , wherein sidewalls of the second UBM structure are covered by the solder material.4. The structure of claim 1 ...

Buffer layer(s) on a stacked structure having a via

A structure includes first and second substrates, first and second stress buffer layers, and a post-passivation interconnect (PPI) structure. The first and second substrates include first and second semiconductor substrates and first and second interconnect structures on the first and second semiconductor substrates, respectively. The second interconnect structure is on a first side of the second semiconductor substrate. The first substrate is bonded to the second substrate at a bonding interface. A via extends at least through the second semiconductor substrate into the second interconnect structure. The first stress buffer layer is on a second side of the second semiconductor substrate opposite from the first side of the second semiconductor substrate. The PPI structure is on the first stress buffer layer and is electrically coupled to the via. The second stress buffer layer is on the PPI structure and the first stress buffer layer.

COMPOSITE BOND STRUCTURE IN STACKED SEMICONDUCTOR STRUCTURE

A semiconductor device includes a substrate, a dielectric structure, a top metal layer and a bonding structure. The dielectric structure is disposed on the substrate. The top metal layer is disposed in the dielectric structure. The bonding structure is disposed on the dielectric structure and the top metal layer. The bonding structure includes a silicon oxide layer, a silicon oxy-nitride layer, a conductive bonding layer and a barrier layer. The silicon oxide layer is disposed on the dielectric structure. The silicon oxy-nitride layer covers the silicon oxide layer. The conductive bonding layer is disposed in the silicon oxide layer and the silicon oxy-nitride layer. The barrier layer covers a sidewall and a bottom of the conductive bonding layer. 1. A semiconductor device , comprising:a substrate;a dielectric structure disposed on the substrate;a top metal layer disposed in the dielectric structure; anda bonding structure disposed on the dielectric structure and the top metal layer, and the bonding structure comprising:a silicon oxide layer disposed on the dielectric structure;a silicon oxy-nitride layer covering the silicon oxide layer and physically contacting the silicon oxide layer;a conductive bonding layer disposed in the silicon oxide layer and the silicon oxy-nitride layer; anda barrier layer covering a sidewall and a bottom of the conductive bonding layer.2. The semiconductor device of claim 1 , wherein a top surface of the conductive bonding layer is at a first elevation claim 1 , a top surface of the silicon oxy-nitride layer is at a second elevation claim 1 , and a result of the first elevation minus the second elevation ranges from substantially −50 angstroms to substantially 100 angstroms.3. The semiconductor device of claim 1 , wherein a top surface of the conductive bonding layer is at a first elevation claim 1 , a top surface of the silicon oxy-nitride layer is at a second elevation claim 1 , and a result of the first elevation minus the second ...

Remapped Packaged Extracted Die

A remapped extracted die is provided. The remapped extracted die includes an extracted die removed from a previous integrated circuit package. The extracted die includes a plurality of original bond pads having locations that do not correspond to desired pin assignments of a new package base and an interposer, bonded to the extracted die. The interposer includes first bond pads configured to receive new bond wires from the plurality of original bond pads, and second bond pads corresponding to desired pin assignments of the new package base, each individually electrically coupled to one of the first bond pads and configured to receive new bond wires from package leads or downbonds of the new package base. 1. A remapped extracted die , comprising:an extracted die removed from a previous integrated circuit package, the extracted die comprising a plurality of original bond pads having locations that do not correspond to desired pin assignments of a new package base; and first bond pads configured to receive new bond wires from the plurality of original bond pads; and', 'second bond pads corresponding to desired pin assignments of the new package base, each individually electrically coupled to one of the first bond pads and configured to receive new bond wires from package leads or downbonds of the new package base., 'an interposer, bonded to the extracted die, comprising2. The remapped extracted die of claim 1 , wherein locations that do not correspond to desired pin assignments of a new package base comprises bond pad locations for new bond wires that cross other new bond wires if the extracted die is bonded to the new package base without the interposer.3. The remapped extracted die of claim 1 , wherein a pinout of the previous integrated circuit package is different than a pinout of the new package base.4. A packaged integrated circuit claim 1 , comprising:an extracted die removed from a previous packaged integrated circuit;a new package base, comprising package ...

Semiconductor device

An inventive semiconductor device includes: a semiconductor chip including an integrated circuit; a plurality of electrode pads provided on the semiconductor chip and connected to the integrated circuit; a rewiring to which the electrode pads are electrically connected together, the rewiring being exposed on an outermost surface of the semiconductor chip and having an exposed surface area greater than the total area of the electrode pads; and a resin package which seals the semiconductor chip.

Semiconductor device with pads of enhanced moisture blocking ability

A semiconductor device is provided having a pad with an improved moisture blocking ability. The semiconductor device has: a circuit portion including a plurality of semiconductor elements formed on a semiconductor substrate; lamination of insulator covering the circuit portion, including a passivation film as an uppermost layer having openings; ferro-electric capacitors formed in the lamination of insulator; wiring structure formed in the lamination of insulator and connected to the semiconductor elements and the ferro-electric capacitors; pad electrodes connected to the wiring structure, formed in the lamination of insulator and exposed in the openings of the passivation film; a conductive pad protection film, including a Pd film, covering each pad electrode via the opening of the passivation film, and extending on the passivation film; and stud bump or bonding wire connected to the pad electrode via the conductive pad protection film.

Method of fabricating a semiconductor device

A semiconductor device and a semiconductor package, the device including a first buffer dielectric layer on a first dielectric layer; a second dielectric layer and a second buffer dielectric layer sequentially disposed on the first buffer dielectric layer, the second buffer dielectric layer being in contact with the first buffer dielectric layer; and a pad interconnection structure that penetrates the first buffer dielectric layer and the second buffer dielectric layer, wherein the pad interconnection structure includes copper and tin.

Solder Metallization Stack and Methods of Formation Thereof

A semiconductor device includes a contact metal layer disposed over a semiconductor surface of a substrate, a diffusion barrier layer disposed over the contact metal layer, an inert layer disposed over the diffusion barrier layer, and a solder layer disposed over inert layer. 1. A semiconductor device comprising:a contact metal layer disposed over a semiconductor surface of a substrate;a diffusion barrier layer disposed over the contact metal layer;an inert layer disposed over the diffusion barrier layer; anda solder layer disposed over inert layer.2. The semiconductor device of claim 1 , wherein the diffusion barrier layer comprises titanium or chromium claim 1 , wherein the inert layer comprises tungsten claim 1 , titanium nitride claim 1 , tantalum claim 1 , tantalum nitride claim 1 , and chromium claim 1 , and wherein the solder layer comprises tin and silver.3. The semiconductor device of claim 1 , wherein the diffusion barrier layer comprises titanium or chromium claim 1 , wherein the inert layer comprises a tungsten titanium alloy claim 1 , and wherein the solder layer comprises tin and silver.4. The semiconductor device of claim 1 , further comprising:an intermetallic layer disposed between the inert layer and the solder layer.5. The semiconductor device of claim 4 , wherein the intermetallic layer comprises a copper tin intermetallic.6. The semiconductor device of claim 5 , further comprising a tin vanadium layer disposed in the intermetallic layer.7. A semiconductor device comprising:a contact metal layer disposed over a semiconductor surface of a substrate;a diffusion barrier layer disposed over the contact metal layer;an inert layer disposed over the diffusion barrier layer;a solder active layer over the inert layer; anda capping layer over the solder active layer.8. The semiconductor device of claim 7 , wherein the contact metal layer comprises an aluminum layer claim 7 , wherein the diffusion barrier layer comprises a titanium or chromium layer claim 7 ...

Electronic device package and fabrication method thereof

An electronic device package and fabrication method thereof is provided. First, a semiconductor substrate is provided and the upper surface of it is etched to from recesses. A first isolation layer is formed on the upper surface and the sidewalls of the recesses. A conductive part is formed to fulfill the recesses and a conductive pad is formed on the first isolation layer to connect the conductive part. An electronic device is combined with the semiconductor substrate on the supper surface, wherein the electronic device has a connecting pad electrically connected to the conductive pad. The semiconductor substrate is thinned form its lower surface to expose the conductive part. A second isolation layer is formed below the lower surface and has an opening to expose the conductive part. A redistribution metal line is formed below the second isolation layer and in the opening to electrically connect to the conductive part.

SEMICONDUCTOR PACKAGE

A semiconductor package includes; a redistribution substrate including a redistribution pattern, a semiconductor chip mounted on a top surface of the redistribution substrate, and a connection terminal between the semiconductor chip and the redistribution substrate. The redistribution substrate further includes; a pad structure including a pad interconnection and a pad via, disposed between the redistribution pattern and the connection terminal, wherein the pad structure is electrically connected to the redistribution pattern and a top surface of the pad structure contacts the connection terminal, a shaped insulating pattern disposed on a top surface of the redistribution pattern, and a pad seed pattern disposed on the redistribution pattern and covering the shaped insulating pattern. 1. A semiconductor package comprising:a redistribution substrate including a redistribution pattern;a semiconductor chip mounted on a top surface of the redistribution substrate; anda connection terminal between the semiconductor chip and the redistribution substrate,{'claim-text': ['a pad structure including a pad interconnection and a pad via, disposed between the redistribution pattern and the connection terminal, wherein the pad structure is electrically connected to the redistribution pattern and a top surface of the pad structure contacts the connection terminal;', 'a shaped insulating pattern disposed on a top surface of the redistribution pattern; and', 'a pad seed pattern disposed on the redistribution pattern and covering the shaped insulating pattern.'], '#text': 'wherein the redistribution substrate further includes:'}2. The semiconductor package of claim 1 , wherein the pad structure comprises:a first metal pattern and a second metal pattern sequentially stacked on the pad interconnection, wherein the connection terminal contacts a top surface of the second metal pattern.3. The semiconductor package of claim 1 , wherein the redistribution substrate further includes an ...

Polymer Layers Embedded with Metal Pads for Heat Dissipation

An integrated circuit structure includes a metal pad, a passivation layer including a portion over the metal pad, a first polymer layer over the passivation layer, and a first Post-Passivation Interconnect (PPI) extending into to the first polymer layer. The first PPI is electrically connected to the metal pad. A dummy metal pad is located in the first polymer layer. A second polymer layer is overlying the first polymer layer, the dummy metal pad, and the first PPI. An Under-Bump-Metallurgy (UBM) extends into the second polymer layer to electrically couple to the dummy metal pad. 1. An integrated circuit structure comprising:a metal pad;a passivation layer comprising a portion over the metal pad;a first polymer layer comprising a portion over the passivation layer;a dummy metal pad in the first polymer layer, wherein the dummy metal pad is electrically floating;a second polymer layer over the first polymer layer and the dummy metal pad; anda first Under-Bump-Metallurgy (UBM) extending into the second polymer layer to electrically couple to the dummy metal pad.2. The integrated circuit structure of claim 1 , wherein a top surface and a bottom surface of the dummy metal pad are coplanar with a top surface and a bottom surface claim 1 , respectively claim 1 , of the first polymer layer.3. The integrated circuit structure of further comprising:a package component comprising a surface metallic feature; anda solder region bonding the surface metallic feature in the package component to the first UBM, wherein the dummy metal pad, the solder region, and the surface metallic feature in combination are electrically floating.4. The integrated circuit structure of further comprising:a third polymer layer between the first polymer layer and the second polymer layer; anda Post-Passivation Interconnect (PPI) extending into to the third polymer layer, wherein the PPI electrically couples the dummy metal pad to the first UBM.5. The integrated circuit structure of further comprising: ...

STACK STRUCTURES IN ELECTRONIC DEVICES

Structures, methods and devices are disclosed, related to improved stack structures in electronic devices. In some embodiments, a stack structure includes a pad implemented on a substrate, the pad including a polymer layer having a side that forms an interface with another layer of the pad, the pad further including an upper metal layer over the interface, the upper metal layer having an upper surface. In some embodiments, the stack structure also includes a passivation layer implemented over the upper metal layer, the passivation layer including a pattern configured to provide a compressive force on the upper metal layer to thereby reduce the likelihood of delamination at the interface, the pattern defining a plurality of openings to expose the upper surface of the upper metal layer. 1. A stack structure comprising:a pad implemented on a substrate, the pad including a polymer layer having a side that forms an interface with another layer of the pad, the pad further including an upper metal layer over the interface, the upper metal layer having an upper surface; anda passivation layer implemented over the upper metal layer, the passivation layer including a pattern configured to provide a compressive force on the upper metal layer to thereby reduce the likelihood of delamination at the interface, the pattern defining a plurality of openings to expose the upper surface of the upper metal layer.2. The stack structure of further comprising a metal structure implemented over the pad such that the metal structure is connected to the exposed upper surface of the upper metal layer through the plurality of openings of the passivation layer.3. The stack structure of wherein the other layer is a metal layer such that the interface is between the polymer layer and the metal layer.4. The stack structure of wherein the metal layer is below the upper metal layer.5. The stack structure of wherein the upper metal layer is the metal layer forming the interface with the polymer layer ...

Semiconductor chip, display panel, and electronic device

A semiconductor chip, a display device or an electronic device includes a substrate, one or more conductive pads disposed on the substrate, and one or more bumps electrically connected to the one or more conductive pads, in which the one or more bumps includes a metal core, a polymer layer disposed over a surface of the metal core, and a conductive coating layer disposed over a surface of the polymer layer and electrically connected to the one or more conductive pads.

SEMICONDUCTOR COPPER METALLIZATION STRUCTURE AND RELATED METHODS

Implementations of semiconductor packages may include: a silicon die including a pad, the pad including aluminum and copper; a passivation layer over at least a portion of the silicon die and a layer of one of a polyimide (PI) a polybenzoxazole (PBO), or a polymer resin coupled to the passivation layer. The package may include a first copper layer coupled over the pad, the first copper layer being about 1 microns to about 20 microns thick; a second copper layer coupled over the first copper layer, the second copper layer may be about 5 microns to about 40 microns thick; where a width of the first copper layer above the pad may be wider than a width of the second copper layer above the pad. The first and second copper layers may be configured to bond with a heavy copper wire or solder with a copper clip. 1. A semiconductor package comprising:a silicon die comprising a pad, the pad comprising one of aluminum copper (AlCu); aluminum copper silicon (AlCuSi); aluminum copper tungsten (AlCuW); aluminum silicon (AlSi); and any combination thereof;a passivation layer over at least a portion of the silicon die;a layer of one of a polyimide (PI), a polybenzoxazole (PBO), a polymer resin, and any combination thereof coupled to the passivation layer;a first copper layer coupled directly over and to the pad and at least a portion of the layer of one of a polyimide (PI), a polybenzoxazole (PBO), a polymer resin, and any combination thereof, the first copper layer being 1 microns to 20 microns thick; anda second copper layer coupled over the first copper layer, the second copper layer being 5 microns to 40 microns thick;wherein a width of the first copper layer above the pad is wider than a width of the second copper layer above the pad; andwherein the first and second copper layers are configured to one of bond with a heavy copper wire and solder with a copper clip.2. A semiconductor package of claim 1 , wherein the heavy copper wire is more than 5 mil in diameter.3. The ...

Design Scheme for Connector Site Spacing and Resulting Structures

A system and method for preventing cracks in a passivation layer is provided. In an embodiment a contact pad has a first diameter and an opening through the passivation layer has a second diameter, wherein the first diameter is greater than the second diameter by a first distance of about 10 μm. In another embodiment, an underbump metallization is formed through the opening, and the underbump metallization has a third diameter that is greater than the first diameter by a second distance of about 5 μm. In yet another embodiment, a sum of the first distance and the second distance is greater than about 15 μm. In another embodiment the underbump metallization has a first dimension that is less than a dimension of the contact pad and a second dimension that is greater than a dimension of the contact pad. 1. A device comprising:a first contact pad on a first substrate, the first contact pad having a first line of symmetry and a second line of symmetry, the first line of symmetry being perpendicular to the second line of symmetry, the first contact pad having a first width along the first line of symmetry, the first contact pad having a second width along the second line of symmetry;a first underbump metallization on the first contact pad; anda first conductive bump on the first underbump metallization, the first conductive bump, having a third line of symmetry and a fourth line of symmetry, the third line of symmetry being perpendicular to the fourth line of symmetry, the first conductive bump having a third width along the third line of symmetry, the first conductive bump having a fourth width along the fourth line of symmetry, the third width being greater than the first width, the fourth width being less than the second width.2. The device of claim 1 , wherein the first width is equal to the second width.3. The device of claim 1 , wherein the first width is different from the second width.4. The device of further comprising:a second contact pad on the first substrate; ...

Semiconductor device

A semiconductor device suitable for preventing malfunction is provided. The semiconductor device includes a semiconductor chip 1 , a first electrode pad 21 laminated on the semiconductor chip 1 , an intermediate layer 4 having a rectangular shape defined by first edges 49 a and second edges, and a plurality of bumps 5 arranged to sandwich the intermediate layer 4 by cooperating with the semiconductor chip 1 . The first edges 49 a extend in the direction x, whereas the second edges extend in the direction y. The plurality of bumps 5 include a first bump 51 electrically connected to the first electrode pad 21 and a second bump 52 electrically connected to the first electrode pad 21 . The first bump 51 is arranged at one end in the direction x and one end in the direction y.

Organic Light Emitting Display Device

Disclosed is an organic light emitting display device that may include first and second pads on a pad area of a substrate, wherein the first pad includes a first bonding region and a first link region, and the second pad includes a second bonding region, a contact region, and a second link region. A first bonding electrode in the first bonding region is electrically connected to one or more signal lines in the active area of the device through contact holes in the first bonding region. A second bonding electrode is electrically connected to one or more signal lines of the device through contact holes in the contact region. The contact region is closer to the active area than the first bonding region. 1. A display device comprising:a substrate with an active area and a pad area;a first signal line and a second signal line in the active area; and a link region electrically connected to the first signal line; and', 'a first bonding region having a first bonding electrode for bonding to an external circuit, the first bonding region including one or more first contact holes through which the first bonding electrode is electrically connected to the link region; and, 'a first pad in the pad area and connected to the first signal line, wherein the first pad comprises a second bonding region having a second bonding electrode for bonding to the external circuit; and', 'a contact region electrically connected with the second bonding region, the contact region having one or more second contact holes through which the second bonding electrode is electrically connected to the second signal line, the contact region being closer to the active area than the first bonding region., 'a second pad in the pad area and connected to the second signal line, wherein the second pad comprises2. The display device of claim 1 , wherein a width of the first bonding region of the first pad is greater than a width of the contact region of the second pad.3. The display device of claim 1 , wherein a ...

Semiconductor Device and Method of Self-Confinement of Conductive Bump Material During Reflow Without Solder Mask

A semiconductor device has a semiconductor die with a die bump pad and substrate with a trace line and integrated bump pad. Conductive bump material is deposited on the substrate bump pad or die bump pad. The semiconductor die is mounted over the substrate so that the bump material is disposed between the die bump pad and substrate bump pad. The bump material is reflowed without a solder mask around the die bump pad or substrate bump pad to form an interconnect. The bump material is self-confined within a footprint of the die bump pad or substrate bump pad. The bump material can be immersed in a flux solution prior to reflow to increase wettability. Alternatively, the interconnect includes a non-fusible base and fusible cap. The volume of bump material is selected so that a surface tension maintains self-confinement of the bump material within the bump pads during reflow.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

To enhance reliability of a test by suppressing defective bonding of a solder in the test of a semiconductor device, a method of manufacturing the semiconductor device includes: preparing a semiconductor wafer that includes a first pad electrode provided with a first cap film and a second pad electrode provided with a second cap film. Further, a polyimide layer that includes a first opening on the first pad electrode and a second opening on the second pad electrode is formed, and then, a rearrangement wiring that is connected to the second pad electrode via the second opening is formed. Next, an opening is formed in the polyimide layer such that an organic reaction layer remains on each of the first pad electrode and a bump land of the rearrangement wiring, then heat processing is performed on the semiconductor wafer, and then, a bump is formed on the rearrangement wiring. 1(a) preparing a semiconductor substrate that includes a first pad electrode and a second pad electrode, the first pad electrode being formed at an uppermost layer of a plurality of wiring layers and having a first metal film formed on a surface of the first pad electrode, and the second pad electrode being electrically connected to the first pad electrode, being formed at the uppermost layer of the plurality of wiring layers and having a second metal film formed on a surface of the second pad electrode;(b) foaming a first insulating film having a first opening, for exposing the first metal film in the first pad electrode, and a second opening for exposing the second metal film in the second pad electrode;(c) forming a mask layer on the first insulating film for covering the first opening and exposing the second opening;(d) forming a wiring which is electrically connected to the second pad electrode via the second opening;(e) forming a second insulating film on the first pad electrode and on the wiring;(f) forming a third opening in the second insulating film above the first pad electrode and ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A method of manufacturing a semiconductor device includes providing a semiconductor substrate, forming, over a main surface the semiconductor substrate, a first insulating film, forming, over the first insulating film, an Al-containing conductive film containing aluminum as a main component, patterning the Al-containing conductive film to form a pad, forming, over the first insulating film, a second insulating film to cover the pad therewith, forming an opening in the second insulating film, and electrically coupling a copper wire to the pad exposed from the opening. 1. A method of manufacturing a semiconductor device , the method comprising:(a) providing a semiconductor substrate;(b) forming, over a main surface the semiconductor substrate, a first insulating film;(c) forming, over the first insulating film, an Al-containing conductive film containing aluminum as a main component;(d) patterning the Al-containing conductive film to form a pad;(e) forming, over the first insulating film, a second insulating film to cover the pad therewith;(f) forming an opening in the second insulating film;(g) electrically coupling a copper wire to the pad exposed from the opening;(h) after the (c) and before the (g), forming a first conductor film over the Al-containing conductive film; and(i) after the (h) and before the (g), forming a second conductor film over the first conductor film,wherein the first conductor film includes a single-layer film or a laminated film including one or more layers of films selected from a group consisting of a titanium film, a titanium nitride film, a tantalum film, a tantalum nitride film, a tungsten film, a tungsten nitride film, a titanium-tungsten film, and a tantalum-tungsten film,wherein the second conductor film comprises one or more metals selected from a group consisting of palladium, gold, ruthenium, rhodium, platinum, and iridium, andwherein, in the (g), the copper wire is bonded to the second conductor film.2. The method of manufacturing ...

SEMICONDUCTOR DEVICE STRUCTURE AND MANUFACTURING METHOD

A semiconductor device structure and a manufacturing method are provided. The semiconductor device structure includes a semiconductor substrate and a dielectric layer over the semiconductor substrate. The semiconductor device structure also includes a conductive trace over the dielectric layer. The semiconductor device structure further includes a conductive feature over the conductive trace, and a width of the conductive feature is substantially equal to or larger than a maximum width of the conductive trace. In addition, the semiconductor device structure includes a conductive bump over the conductive feature. 1. A structure , comprising:a substrate;a conductive trace disposed over the substrate, the conductive trace including a first segment and a second segment that each extend in a first direction, wherein the first segment and the second segment have substantially equal dimensions measured in a second direction;a conductive layer disposed over the first segment, but not over the second segment, of the conductive trace, wherein a dimension of the conductive layer measured in the second direction is greater than the dimension of the first segment of the conductive trace; anda conductive bump disposed over the conductive layer.2. The structure of claim 1 , wherein the conductive bump is in direct contact with the conductive layer.3. The structure of claim 2 , wherein the conductive bump is separated from a sidewall of the conductive trace by the conductive layer.4. The structure of claim 1 , wherein the conductive bump and the conductive layer have similar top view profiles.5. The structure of claim 4 , wherein the conductive bump and the conductive layer each have rounded top view profiles.6. The structure of claim 1 , wherein the conductive trace is free of having a passivation layer formed thereon.7. The structure of claim 1 , wherein an entirety of the conductive trace has a uniform dimension measured in the second direction.8. The structure of claim 1 , ...

Method and apparatus for manufacturing a semiconductor device including a plurality of semiconductor chips connected with bumps

A method for manufacturing a semiconductor device including a plurality of semiconductor chips includes steps of placing, on a first semiconductor chip, a second semiconductor chip, such that a plurality of bumps is located between the first semiconductor chip and the second semiconductor chip, determining a distance between the first semiconductor chip and the second semiconductor chip, and determining whether or not the distance is within a predetermined range and stopping placement of additional chips if the distance is determined to be outside the predetermined range.

Metal Routing Architecture for Integrated Circuits

A device includes a substrate, a metal pad over the substrate, and a metal trace electrically disconnected from the metal pad. The metal pad and the metal trace are level with each other. A passivation layer includes a portion overlapping an edge portion of the metal pad. A metal pillar is overlying the metal pad, and is electrically connected to the metal pad. The metal trace has a portion overlapped by the metal pillar.

METALLIC RIBBON FOR POWER MODULE PACKAGING

A metallic ribbon for power module packaging is described. The metallic ribbon has a rectangular, oval or oblong cross section. The composition of the metallic ribbon is silver-palladium alloy containing 0.2 to 6 wt % Pd. The metallic ribbon has a thickness of 10 μm to 500 μm. The width of the metallic ribbon is 2 to 100 times its thickness. The metallic ribbon includes a plurality of grains. The average grain size of the grains observed in the transverse cross section is 2 μm to 10 μm. The metallic ribbon has a plurality of twin grains observed in the transverse cross section, and the number of twin grains observed in the transverse cross section accounts for at least 5% of the total number of grains observed in the transverse cross section. 1. A metallic ribbon for power module packaging , wherein:the metallic ribbon has a rectangular, oval or oblong cross section;a composition of the metallic ribbon is a silver-palladium alloy comprising 0.2 to 6 wt % palladium;the metallic ribbon has a thickness of 10 μm to 500 μm;a width of the metallic ribbon is 2 to 100 times the thickness;the metallic ribbon comprises a plurality of grains, an average grain size of grains observed in a transverse cross section of the metallic ribbon is 2 μm to 10 μm; andthe metallic ribbon has a plurality of twin grains observed in the transverse cross section of the metallic ribbon, and a number of the twin grains observed in the transverse cross section accounts for at least 5% of a total number of the grains observed in the transverse cross section.2. The metallic ribbon for power module packaging of claim 1 , wherein a hardness of the metallic ribbon is 40 Hv to 70 Hv.3. The metallic ribbon for power module packaging of claim 1 , wherein the width of the metallic ribbon is not greater than 5 mm.4. The metallic ribbon for power module packaging of claim 1 , wherein a surface of the metallic ribbon is covered by one or more metal layers claim 1 , wherein a composition of the one or more ...

INTERCONNECTION STRUCTURE OF A SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE INCLUDING THE INTERCONNECTION STRUCTURE

An interconnection structure of a semiconductor chip may include an interconnection via, a lower pad, a conductive bump, and an upper pad. The interconnection via may be arranged in the semiconductor chip. The lower pad may be arranged on a lower end of the interconnection via exposed through a lower surface of the semiconductor chip. The conductive bump may be arranged on the lower pad. The upper pad may be arranged on an upper end of the interconnection via exposed through an upper surface of the semiconductor chip. The upper pad may have a width wider than a width of the interconnection via and narrower than a width of the lower pad. Thus, an electrical short between the conductive bumps may not be generated in the interconnection structure having a thin thickness. 1. An interconnection structure of a semiconductor chip , the interconnection structure comprising:an interconnection via arranged in the semiconductor chip;a lower pad arranged on a lower end of the interconnection via exposed through a lower surface of the semiconductor chip;a conductive bump arranged on the lower pad; andan upper pad including a body pad arranged on an upper end of the interconnection via exposed through an upper surface of the semiconductor chip, and an interconnection pad arranged on an upper surface of the body pad,wherein the body pad has a width substantially the same as a width of the lower pad, and the interconnection pad has a width wider than a width of the interconnection via and narrower than the width of the lower pad.2. The interconnection structure of claim 1 , wherein the interconnection pad is positioned on a central portion of the upper surface of the body pad.3. The interconnection structure of claim 1 , wherein the interconnection pad is arranged on an upper surface and a side surface of the body pad.4. The interconnection structure of claim 1 , wherein the width of the lower pad is about 15 μm to about 20 μm claim 1 , the width of the interconnection via is about ...

SEMICONDUCTOR PACKAGE

A semiconductor package includes a semiconductor substrate and an electrode pad formed on the semiconductor substrate. The electrode pad includes a central portion and a peripheral portion, and a first pattern is located on the peripheral portion. A passivation layer is formed on the semiconductor substrate and the electrode pad. The passivation layer has an opening exposing the central portion of the electrode pad and a second pattern located on the first pattern. A seed layer is formed on the electrode pad and the passivation layer. The seed layer has a third pattern formed on the second pattern. A bump is formed on the seed layer and electrically connected to the electrode pad. An undercut is formed around the third pattern located under an edge of a lower portion of the bump. 1. A semiconductor package comprising:a semiconductor substrate;an electrode pad on the semiconductor substrate and including a central portion and a peripheral portion, wherein a first pattern is located on the peripheral portion;a passivation layer on the semiconductor substrate and the electrode pad, the passivation layer having an opening exposing the central portion of the electrode pad and a second pattern located on the first pattern;a seed layer on the electrode pad and the passivation layer and having a third pattern on the second pattern; anda bump on the seed layer and electrically connected to the electrode pad,wherein an undercut is formed in the third pattern located under an edge of a lower portion of the bump.2. The semiconductor package of claim 1 , wherein the bump comprises a pillar layer being in contact with the seed layer and a solder layer on the pillar layer.3. The semiconductor package of claim 2 , wherein a top surface of the pillar layer is a flat surface claim 2 , anda bottom surface of the pillar layer is a curved surface corresponding to the third pattern.4. The semiconductor package of claim 2 , wherein a distance from a center of the pillar layer to a side ...

Semiconductor Device and Method of Forming Patterned Repassivation Openings Between RDL and UBM to Reduce Adverse Effects of Electro-Migration

A semiconductor device has a semiconductor wafer with a first conductive layer formed over a surface of the semiconductor wafer. A first insulating layer is formed over the surface of the semiconductor wafer and first conductive layer. A second conductive layer is formed over the first insulating layer and first conductive layer. A second insulating layer is formed over the first insulating layer and second conductive layer. A plurality of openings is formed in the second insulating layer in a bump formation area of the semiconductor wafer to expose the second conductive layer and reduce adverse effects of electro-migration. The openings are separated by portions of the second insulating layer. A UBM layer is formed over the openings in the second insulating layer in the bump formation area electrically connected to the second conductive layer. A bump is formed over the UBM layer.

Semiconductor Device Having Through Silicon Vias and Manufacturing Method Thereof

In the semiconductor device, a semiconductor substrate has first and second surfaces. A circuitry layer is formed over the first surface and a first insulating layer is further formed over the circuitry layer. A second insulating layer including a first insulating element is formed over the second surface. A third insulating layer including a second insulating element different from the first insulating element of the second insulating layer is formed over the second surface with an intervention of the second insulating layer therebetween. A penetration electrode penetrates through the semiconductor substrate, the circuitry layer, the first insulating layer, the second insulating layer and the third insulating layer. 1. A method of forming a semiconductor device , comprising:providing a semiconductor substrate having a plurality of transistors on a first surface thereof;forming a first interlayer dielectric film on the first surface;forming a multi-level wiring structure on the first interlayer dielectric film;thinning the semiconductor substrate from a surface opposite to the first surface to form a second surface of the semiconductor substrate;forming a first back insulating layer on the second surface of the semiconductor substrate;forming a second back insulating layer in direct contact with the first back insulating layer, the second back insulating layer having a back surface away from first back insulating layer, wherein the second back insulating layer includes an insulating material different from the first back insulating layer;forming an opening on the second back insulating layer, sequentially etching the first back insulating layer and the semiconductor substrate through the opening to form a substrate through hole, wherein the substrate through hole at least reaches the first interlayer dielectric film;forming a through silicon via within the substrate through hole, wherein the through silicon via extends from the first surface of the semiconductor ...

WAFER-LEVEL PACKAGE INCLUDING UNDER BUMP METAL LAYER

A semiconductor package includes a semiconductor chip comprising a first surface and a second surface, a redistribution layer on the first surface of the semiconductor chip, an under bump metal (UBM) layer on the redistribution layer, and a solder bump on the UBM layer, and the solder bump covers both outer side surfaces of the UBM layer. 1. A wafer-level semiconductor package comprising:a semiconductor chip including a first surface and a second surface, and including a connection pad on the first surface;a first passivation layer covering the first surface of the semiconductor chip, the first passivation layer including a first trench exposing the connection pad;a redistribution layer in the first trench and on the first passivation layer;a second passivation layer on the redistribution layer, and the second passivation layer includes a second trench exposing the redistribution layer;a UBM layer in the second trench and on the second passivation and in contact with the redistribution layer, and the thickness of the UBM layer is approximately 25 to 35 μm; anda solder bump on the UBM layer and covering an outer surface of the UBM layer, and a thickness of the solder bump is approximately 210 to 220 μm.2. The wafer-level semiconductor package of claim 1 , wherein the solder bump includes Au.3. The wafer-level semiconductor package of claim 1 , wherein the solder bump further comprises a contact surface in contact with the second passivation layer.4. The wafer-level semiconductor package of claim 1 , wherein an width of a portion of the solder bump covering the outer surface of the UBM layer gradually increases from the second passivation layer to the bottom surface of the UBM layer.5. The wafer-level semiconductor package of claim 1 , wherein the UBM layer comprises a first UBM layer in contact with the redistribution layer and a second UBM layer disposed on the first UBM layer.6. The wafer-level semiconductor package of claim 1 , wherein the wafer-level ...

FILM-TYPE SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

A film-type semiconductor package includes a metal lead portion arranged on a film substrate, a semiconductor chip including a pad, and a bump connecting the metal lead portion to the pad of the semiconductor chip. The bump includes a metal pillar arranged on the pad and including a first metal and a soldering portion arranged on an entire surface of the metal pillar, bonded to the metal lead portion, and including the first metal and a second metal that is different from the first metal. 1. A film-type semiconductor package comprising:a metal lead portion on a film substrate;a semiconductor chip including a pad; and a metal pillar on the pad and including a first metal; and', 'a soldering portion on an entire surface of the metal pillar, bonded to the metal lead portion, and including the first metal and a second metal that is different from the first metal;, 'a bump connecting the metal lead portion to the pad of the semiconductor chip, the bump including,'}wherein the metal lead portion comprises a metal lead and a lead protective layer protecting a surface of the metal lead;the metal lead includes a copper layer, andthe lead protective layer includes a tin layer.23-. (canceled)4. The film-type semiconductor package of claim 1 , wherein the metal pillar comprises a gold layer or a copper layer.5. The film-type semiconductor package of claim 1 , wherein the soldering portion comprises a gold-tin eutectic alloy layer.6. The film-type semiconductor package of claim 5 , wherein a content of tin atoms in the gold-tin eutectic alloy layer is equal to or greater than about 25% and equal to or less than about 45%.7. The film-type semiconductor package of claim 1 , wherein the soldering portion surrounds a bottom and opposite side surfaces of the metal lead portion.8. The film-type semiconductor package of claim 1 , wherein the diffusion preventing layer includes a third metal that is different from the first metal and the second metal.9. The film-type semiconductor ...

SEMICONDUCTOR DEVICE

A semiconductor device includes an insulating layer, a barrier electrode layer formed on the insulating layer, a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer, and an outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer. 1. A semiconductor comprising:an insulating layer;a barrier electrode layer formed on the insulating layer;a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer; andan outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer.2. The semiconductor device according to claim 1 , wherein the outer-surface insulating film is in contact with the principal surface of the barrier electrode layer at a position with an interval from a peripheral edge of the barrier electrode layer toward an inward side of the barrier electrode layer.3. The semiconductor device according to claim 1 , wherein the Cu electrode layer includes a first surface and a second surface that is positioned on a side opposite to the first surface and that is connected to the barrier electrode layer claim 1 , anda peripheral edge of the second surface of the Cu electrode layer is formed at a position with an interval from the peripheral edge of the barrier electrode layer toward the inward side of the barrier electrode layer.4. The semiconductor device according to claim 1 , wherein the Cu electrode layer includes a first surface and a second surface that is positioned on a side opposite to the first surface and that is connected to the barrier electrode layer claim 1 , andthe second surface of the Cu electrode layer is formed narrower than ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Properties of a semiconductor device are improved. A semiconductor device is configured so as to have a protective film provided over an interconnection and having an opening, and a plating film provided in the opening. A slit is provided in a side face of the opening, and the plating film is also disposed in the slit. Thus, the slit is provided in the side face of the opening, and the plating film is also grown in the slit. This results in a long penetration path of a plating solution during subsequent formation of the plating film. Hence, a corroded portion is less likely to be formed in the interconnection (pad region). Even if the corroded portion is formed, a portion of the slit is corroded prior to the interconnection (pad region) at a sacrifice, making it possible to suppress expansion of the corroded portion into the interconnection (pad region). 1. A semiconductor device , comprising:a first insulating film provided above a semiconductor substrate;a first interconnection provided over the first insulating film;a second insulating film provided over the first interconnection and having a first opening;a plating film provided in the first opening; anda slit provided in a side face of the first opening,wherein a bottom of the first opening is a pad region being part of the first interconnection, andwherein the plating film is also provided in the slit.2. The semiconductor device according to claim 1 ,wherein the first interconnection contains aluminum (Al), andwherein the plating film contains a metal selected from nickel (Ni), gold (Au), and palladium (Pd).3. The semiconductor device according to claim 2 ,wherein the first interconnection contains aluminum (Al), andwherein the plating film includes a first plating film containing nickel (Ni), and a second plating film provided on the first plating film and containing gold (Au).4. The semiconductor device according to claim 3 , further comprising a third plating film containing palladium (Pd) between the first ...

Method of fabricating wafer-level chip package

A method of fabricating a wafer-level chip package is provided. First, a wafer with two adjacent chips is provided, the wafer having an upper surface and a lower surface, and one side of each chip includes a conducting pad on the lower surface. A recess and an isolation layer extend from the upper surface to the lower surface, which the recess exposes the conducting pad. A part of the isolation layer is disposed in the recess with an opening to expose the conducting pad. A conductive layer is formed on the isolation layer and the conductive pad, and a photo-resist layer is spray coated on the conductive layer. The photo-resist layer is exposed and developed to expose the conductive layer, and the conductive layer is etched to form a redistribution layer. After stripping the photo-resist layer, a solder layer is formed on the isolation layer and the redistribution layer.

Integrated Circuit Packages and Methods for Forming the Same

A method includes forming an electrical connector over a substrate of a wafer, and molding a polymer layer, with at least a portion of the electrical connector molded in the polymer layer. A first sawing step is performed to form a trench in the polymer layer. After the first sawing step, a second sawing step is performed to saw the wafer into a plurality of dies. 1. A method comprising:forming a solder region on a wafer, wherein the wafer comprises a plurality of chips, with the solder region being in a first chip of the plurality of chips;forming a dielectric layer to embed a portion of the solder region in the dielectric layer, wherein the dielectric layer comprises a first portion and a second portion;thinning the first portion of the dielectric layer without thinning the second portion of the dielectric layer; andsawing the wafer to separate the plurality of chips from each other, wherein the sawing comprises using a feature underlying the thinned first portion of the dielectric layer for alignment.2. The method of claim 1 , wherein the thinning results in a trench to be formed in the dielectric layer claim 1 , wherein the trench extends into the first chip.3. The method of claim 2 , wherein the trench further extends into a scribe line claim 2 , with the scribe line separating the first chip and a second chip from each other.4. The method of claim 1 , wherein after the thinning claim 1 , a remaining portion of the first portion of the dielectric layer is left claim 1 , and has a thickness allowing the feature directly underlying the remaining portion to be visible through the remaining portion.5. The method of claim 1 , wherein before the thinning claim 1 , the first portion of the dielectric layer is thick enough to prevent the feature from being visible through the first portion of the dielectric layer.6. The method of claim 1 , wherein the dielectric layer comprises a molding compound.7. The method of claim 1 , wherein the thinning is performed using a ...

Semiconductor device and semiconductor package including the same

A semiconductor device and a semiconductor package, the device including a first buffer dielectric layer on a first dielectric layer; a second dielectric layer and a second buffer dielectric layer sequentially disposed on the first buffer dielectric layer, the second buffer dielectric layer being in contact with the first buffer dielectric layer; and a pad interconnection structure that penetrates the first buffer dielectric layer and the second buffer dielectric layer, wherein the pad interconnection structure includes copper and tin.

Semiconductor Device

Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion () formed on the upper surface of a semiconductor substrate (), a passivation layer () so formed on the upper surface of the semiconductor substrate () as to overlap a part of the electrode pad portion () and having a first opening portion () where the upper surface of the electrode pad portion () is exposed, a barrier metal layer () formed on the electrode pad portion (), and a solder bump () formed on the barrier metal layer (). The barrier metal layer () is formed such that an outer peripheral end () lies within the first opening portion () of the passivation layer () when viewed in plan. 110.-. (canceled)11. A semiconductor device comprising: an electrode pad portion on a face of a substrate;', 'a first protection layer including a first opening through which a top face of the electrode pad portion is exposed, the first protection layer disposed on the face of the substrate and overlapping part of the electrode pad portion;', 'a barrier metal layer on the electrode pad portion;', 'a second protection layer covering a region on the first protection layer and a region on the electrode par portion; and', 'a plurality of bump electrodes on the barrier metal layer;, 'a semiconductor chip includinga circuit board on which the semiconductor chip is mounted, the circuit board having, formed on a first face thereof facing the semiconductor chip, a connection pad portion connected to the bump electrodes;a plurality of electrode terminals formed on a second face of the circuit board facing away from the semiconductor chip, the electrode terminals being electrically connected to the connection pad portion; anda resin member filling a gap between the semiconductor chip and the circuit board,wherein the barrier metal layer has a circumferential end part thereof formed inward of the first opening in the first protection layer as seen in a plan ...

BUMP BONDED CRYOGENIC CHIP CARRIER

A technique relates to a device. First thin films are characterized by having a first opposing surface and a first connection surface in which the first connection surface is in physical contact with a first superconducting region. Second thin films are characterized by having a second opposing surface and a second connection surface in which the first and second opposing surfaces are opposite one another. The second connection surface is in physical contact with a second superconducting region. A solder material electrically connects the first and second opposing surfaces, and the solder material is characterized by maintaining a low ohmic electrical contact between the first and second opposing surfaces at temperatures below 100 degrees Kelvin. The first and second superconducting regions are formed of materials that have a melting point of at least 700 degrees Celsius. 1. A device comprising:a first plurality of thin films, the first plurality of thin films characterized by having a first opposing surface and a first connection surface, wherein the first connection surface is in physical contact with a first superconducting region;a second plurality of thin films, the second plurality of thin films characterized by having a second opposing surface and a second connection surface, the first and second opposing surfaces being opposite one another, wherein the second connection surface is in physical contact with a second superconducting region; anda solder material electrically connecting the first and second opposing surfaces, the solder material characterized by maintaining a low ohmic electrical contact between the first and second opposing surfaces at temperatures below 100 degrees Kelvin, wherein the first and second superconducting regions are comprised of materials that have a melting point of at least 700 degrees Celsius.2. The device of claim 1 , wherein the first and second plurality of thin films are electrically conductive.3. The device of claim 1 , ...

Manufacturing method of wafer level chip scale package structure

A manufacturing method of wafer level chip scale package structure is provided. Firstly, a wafer including a plurality of semiconductor devices is provided. An active surface of one of the semiconductor devices has an active an active region and an outer region. A first electrode and a second electrode are arranged on the active region, and the outer region has a cutting portion and a channel portion. Next, a patterned protecting layer having a plurality of openings is formed on the active surface to respectively expose the first and second electrodes and channel portion. Subsequently, a wafer back thinning process is performed and then a back electrode layer is deposited. Subsequently, the channel portion is etched to form a trench exposing the back electrode layer, and a conductive structure connected to the back electrode layer is formed through the trench. Thereafter, the wafer is cut along the cutting portion.

Semiconductor structure

The invention provides a semiconductor structure. The semiconductor structure includes a substrate. A first passivation layer is disposed on the substrate. A conductive pad is disposed on the first passivation layer. A second passivation layer is disposed on the first passivation layer. A passive device is disposed on the conductive pad, passing through the second passivation layer. An organic solderability preservative film covers the passive device.

FULLY MOLDED MINIATURIZED SEMICONDUCTOR MODULE

A semiconductor module can comprise a fully molded base portion comprising a planar surface that further comprises a semiconductor die comprising contact pads, conductive pillars coupled to the contact pads and extending to the planar surface, and an encapsulant material disposed over the active surface, four side surfaces, and around the conductive pillars, wherein ends of the conductive pillars are exposed from the encapsulant material at the planar surface of the fully molded base portion. A build-up interconnect structure comprising a routing layer can be disposed over the fully molded base portion. A photo-imageable solder mask material can be disposed over the routing layer and comprise openings to form surface mount device (SMD) land pads electrically coupled to the semiconductor die and the conductive pillars. A SMD component can be electrically coupled to the SMD land pads with surface mount technology (SMT). 1. A semiconductor module , comprising: a semiconductor die comprising contact pads,', 'conductive pillars coupled to the contact pads and extending to the planar surface, and', 'an encapsulant material disposed over the active surface, four side surfaces, and around the conductive pillars, wherein ends of the conductive pillars are exposed from the encapsulant material at the planar surface of the fully molded base portion;, 'a fully molded base portion comprising a planar surface that further comprisesa build-up interconnect structure comprising a routing layer disposed over the fully molded base portion;a photo-imageable solder mask material disposed over the routing layer and comprising openings to form surface mount device (SMD) land pads electrically coupled to the semiconductor die and the conductive pillars; anda SMD component electrically coupled to the SMD land pads with surface mount technology (SMT).2. The semiconductor module of claim 1 , wherein the photo-imageable solder mask comprises at least one of epoxy solder resist claim 1 , ...

CHIP PARTS AND METHOD FOR MANUFACTURING THE SAME, CIRCUIT ASSEMBLY HAVING THE CHIP PARTS AND ELECTRONIC DEVICE

A chip part according to the present invention includes a substrate having a penetrating hole, a pair of electrodes formed on a front surface of the substrate and including one electrode overlapping the penetrating hole in a plan view and another electrode facing the one electrode, and an element formed on the front surface side of the substrate and electrically connected to the pair of electrodes. 1. A bidirectional Zener diode chip , comprising:a semiconductor substrate of a first conductivity type;a first diffusion region of a second conductivity type formed on the semiconductor substrate and exposed at a front surface of the semiconductor substrate;a second diffusion region of the second conductivity type formed on the semiconductor substrate across an interval from the first diffusion region and exposed at the front surface of the semiconductor substrate;a first electrode formed on the front surface of the semiconductor substrate and connected to the first diffusion region; anda second electrode formed on the front surface of the semiconductor substrate and connected to the second diffusion region, wherein,{'sup': '2', 'in a plan view of the semiconductor substrate from a normal direction, respective areas of the first diffusion region and the second diffusion region are not more than 2500 μmrespectively.'}2. The bidirectional Zener diode chip according to claim 1 , wherein the respective areas of the first diffusion region and the second diffusion region are not more than 2000 μmrespectively and the respective peripheral lengths of the first diffusion region and the second diffusion region are not less than 470 μm respectively.3. The bidirectional Zener diode chip according to claim 1 , wherein the ESD resistance is not less than 12 kV.4. The bidirectional Zener diode chip according to claim 1 , wherein the first diffusion region and the second diffusion region have mutually equal areas.5. The bidirectional Zener diode chip according to claim 1 , wherein the ...

SEMICONDUCTOR COPPER METALLIZATION STRUCTURE AND RELATED METHODS

Implementations of semiconductor packages may include: a silicon die including a pad, the pad including aluminum and copper; a passivation layer over at least a portion of the silicon die and a layer of one of a polyimide (PI) a polybenzoxazole (PBO), or a polymer resin coupled to the passivation layer. The package may include a first copper layer coupled over the pad, the first copper layer being about 1 microns to about 20 microns thick; a second copper layer coupled over the first copper layer, the second copper layer may be about 5 microns to about 40 microns thick; where a width of the first copper layer above the pad may be wider than a width of the second copper layer above the pad. The first and second copper layers may be configured to bond with a heavy copper wire or solder with a copper clip. 1. A semiconductor package comprising:a die comprising a pad on a first side of the die, the pad comprising one of aluminum and copper (AlCu); aluminum, copper and silicon (AlCuSi); aluminum, copper, and tungsten (AlCuW); aluminum silicon (AlSi); or any combination thereof;a first copper layer coupled directly over and to the pad;a second copper layer coupled over the first copper layer; anda metal layer comprised on a second side of the die opposite the first side of the die, wherein an implanted doped layer is formed in the second side of the die.2. A semiconductor package of claim 1 , wherein a width of the first copper layer above the pad is wider than a width of the second copper layer above the pad.3. The semiconductor package of claim 1 , further comprising a metal coating forming one of a metal cap on a top of the second copper layer or a full metal coverage of the first and the second copper layers claim 1 , the metal coating applied through one of electroless plating or electrolytic plating.4. The semiconductor package of claim 3 , wherein the metal coating comprises one of nickel and gold (Ni/Au); nickel claim 3 , palladium claim 3 , and gold (Ni/Pd/Au); ...

Interconnect Crack Arrestor Structure and Methods

A system and method for preventing cracks is provided. An embodiment comprises placing crack stoppers into a connection between a semiconductor die and a substrate. The crack stoppers may be in the shape of hollow or solid cylinders and may be placed so as to prevent any cracks from propagating through the crack stoppers. 1. A semiconductor device comprising:a conductive region on a first semiconductor substrate; anda first crack stopper on the conductive region, the first crack stopper comprising a wire that is wire bonded to the conductive region on the first semiconductor substrate.2. The semiconductor device of claim 1 , wherein the first crack stopper further comprises a plurality of wires that are wire bonded to the conductive region on the first semiconductor substrate.3. The semiconductor device of claim 2 , wherein the plurality of wires have a first height of less than 200 μm.4. The semiconductor device of claim 1 , wherein the wire comprises a cylindrical shape.5. The semiconductor device of claim 1 , wherein the conductive region is an underbump metallization.6. A semiconductor device comprising:metallization layers over a substrate;a contact pad electrically connected to the metallization layers;an underbump metallization in physical contact with the contact pad;a first crack stopper wire bonded to the underbump metallization; andsolder encapsulating the first crack stopper wire.7. The semiconductor device of claim 6 , further comprising a protective layer located between the first crack stopper wire and the solder.8. The semiconductor device of claim 7 , wherein the protective layer comprises palladium.9. The semiconductor device of claim 6 , wherein the first crack stopper wire comprises gold.10. The semiconductor device of claim 6 , wherein the first crack stopper wire has a length of between about 100 μm and about 300 μm.11. The semiconductor device of claim 10 , wherein the first crack stopper wire has a length of about 200 μm.12. The semiconductor ...

SEMICONDUCTOR DEVICE

A semiconductor device of the present disclosure includes: a semiconductor substrate having a first main surface; a first aluminum electrode having a first surface facing the first main surface and a second surface opposite to the first surface, the first aluminum electrode being disposed on the semiconductor substrate; a passivation film that covers a peripheral edge of the second surface and that is provided with an opening from which a portion of the second surface is exposed; and a copper film. The second surface exposed from the opening is provided with a recess that is depressed toward the first surface. The copper film is disposed in the recess. 1. A semiconductor device comprising:a semiconductor substrate having a first main surface;a first aluminum electrode having a first surface facing the first main surface and a second surface opposite to the first surface, the first aluminum electrode being disposed on the semiconductor substrate;a passivation film that covers a peripheral edge of the second surface and that is provided with an opening from which a portion of the second surface is exposed; anda copper film, whereinthe second surface exposed from the opening is provided with a recess that is depressed toward the first surface, andthe copper film is disposed in the recess.2. The semiconductor device according to claim 1 , wherein the passivation film is a polyimide film.3. The semiconductor device according to claim 1 , wherein the semiconductor substrate is a silicon carbide semiconductor substrate.4. The semiconductor device according to claim 1 , further comprising:a second aluminum electrode disposed on the semiconductor substrate;a plurality of first bonding wires connected to the copper film; anda second bonding wire connected to the second aluminum electrode, whereineach of the first bonding wires is composed of copper or a copper alloy, andthe second bonding wire is composed of aluminum or an aluminum alloy.5. The semiconductor device according ...

PAD STRUCTURE FOR FRONT SIDE ILLUMINATED IMAGE SENSOR

The present disclosure relates to an integrated circuit having a bond pad with a relatively flat surface topography that mitigates damage to underlying layers. In some embodiments, the integrated circuit has a plurality of metal interconnect layers within a dielectric structure over a substrate. A passivation structure is arranged over the dielectric structure. The passivation structure has a recess with sidewalls connecting a horizontal surface of the passivation structure to an upper surface of the passivation structure. A bond pad is arranged within the recess and has a lower surface overlying the horizontal surface. One or more protrusions extend outward from the lower surface through openings in the passivation structure to contact one of the metal interconnect layers. Arranging the bond pad within the recess and over the passivation structure mitigates stress to underlying layers during bonding without negatively impacting an efficiency of an image sensing element within the substrate. 1. An integrated circuit , comprising:a plurality of metal interconnect layers arranged within a dielectric structure over a semiconductor substrate;a passivation structure arranged over the dielectric structure and having a recess within an upper surface of the passivation structure, wherein the recess comprises sidewalls connecting a horizontal surface of the passivation structure to the upper surface; anda bond pad arranged within the recess and having a lower surface that overlies the horizontal surface, wherein the bond pad comprises one or more protrusions extending outward from the lower surface of the bond pad through openings in the passivation structure to contact one of the plurality of metal interconnect layers.2. The integrated circuit of claim 1 , further comprising:a second recess arranged within a top surface of the dielectric structure and having sidewalls contacting a horizontal surface of the dielectric structure to the top surface, wherein the passivation ...

SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF

Present disclosure provides a semiconductor structure, including a substrate, a pad on the substrate, a conductive layer electrically coupled to the pad at one end, a metal bump including a top surface and a sidewall, a solder bump on the top surface of the metal bump, a dielectric layer surrounding the sidewall of the metal bump and having a top surface, and the top surface of the metal bump entirely protruding the top surface of the dielectric layer, and a polymer layer on the top surface of the dielectric layer, the polymer layer being spaced from both the sidewall of the metal bump and a nearest outer edge of the solder bump with a gap. A method for fabricating a semiconductor device is also provided. 1. A semiconductor device , comprising:a substrate;a pad on the substrate;a conductive layer electrically coupled to the pad at one end;a metal bump including a top surface and a sidewall;a solder bump on the top surface of the metal bump;a dielectric layer surrounding the sidewall of the metal bump and having a top surface, and the top surface of the metal bump entirely protruding the top surface of the dielectric layer; anda polymer layer on the top surface of the dielectric layer, the polymer layer being spaced from both the sidewall of the metal bump and a nearest outer edge of the solder bump with a gap.2. The semiconductor device of claim 1 , wherein the sidewall of the metal bump is tapered.3. The semiconductor device of claim 1 , wherein a coefficient of thermal expansion (CTE) of the polymer layer is greater than a CTE of the dielectric layer.4. The semiconductor device of claim 1 , wherein the gap is in a range of from about 31 μm to about 95 μm.5. The semiconductor device of claim 1 , wherein the metal bump comprises a bottom surface contacting with the conductive layer.6. The semiconductor device of claim 1 , wherein the metal bump comprises a thickness between about 8 μm and about 12 μm.7. The semiconductor device of claim 1 , wherein the top surface ...