Halbleitervorrichtung aus einer galliumnitridartigen III-V-Halbleiterverbindung und Verfahren zu ihrer Herstellung

Laminatpackung von Chip auf Träger und in Kavität

Eine Packung (100), umfassend einen Chipträger (102), hergestellt aus einem ersten Material, einen Körper (104), hergestellt aus einem zweiten Material, das sich vom ersten Material unterscheidet, und angeordnet auf dem Chipträger (102) zum Bilden einer Kavität (106), einen Halbleiterchip (108), mindestens teilweise in der Kavität (106) angeordnet, und ein Laminat (110), einkapselnd mindestens eines von mindestens einem Teil des Chipträgers (102), mindestens einem Teils des Körpers (104) und mindestens einem Teil des Halbleiterchips (108).

HALBLEITERANORDNUNG MIT EINER DICHTSTRUKTUR

Es wird eine Halbleiteranordnung offenbart. Die Halbleiteranordnung enthält einen Halbleiterkörper mit einer ersten Oberfläche, einem inneren Gebiet und einem Randgebiet, wobei das Randgebiet das innere Gebiet umgibt, eine Befestigungsschicht, die in einer ersten Richtung von der ersten Oberfläche des Halbleiterkörpers beabstandet ist, eine Zwischenschicht, die zwischen der ersten Oberfläche des Halbleiterkörpers und der Befestigungsschicht angeordnet ist, und zumindest eine Dichtstruktur ersten Typs. Die Dichtstruktur enthält eine erste Barriere, eine zweite Barriere und eine dritte Barriere. Die erste Barriere ist in der Zwischenschicht angeordnet und in der ersten Richtung von der Befestigungsschicht beabstandet. Die zweite Barriere ist in der Zwischenschicht angeordnet, ist in der ersten Richtung von der ersten Oberfläche beabstandet, und ist in einer zweiten Richtung von der ersten Barriere beabstandet. Die dritte Barriere erstreckt sich in der zweiten Richtung von der ersten Barriere ...

A METHOD OF JOINING TWO ELECTRONIC COMPONENTS, FLIP-BY ANNEALING THE UV, OBTAINED ASSEMBLY

A METHOD OF JOINING TWO ELECTRONIC COMPONENTS, FLIP UV BY ANNEALING, RESULTING ASSEMBLY

L'invention concerne un procédé d'assemblage de type Flip-Chip, entre un premier (1) et un deuxième (2) composants comportant chacun des plots de connexion (11, 21) sur une de leurs faces, dites faces d'assemblage, selon lequel on reporte les composants l'un sur l'autre par leurs faces d'assemblage de sorte à réaliser des interconnexions électriques entre les plots du premier et ceux du deuxième composant. Selon l'invention, on réalise une transformation de l'oxyde de cuivre en cuivre par recuit UV, très localement dans l'espacement entre composants au moins autour des zones au droit des plots de connexion. Le procédé selon l'invention peut être utilisé pour n'importe quel composant transparent aux UV, y compris pour des substrats en matière plastique tels que des substrats en PEN ou en PET.

THREE-DIMENSIONAL CHIP STACK AND METHOD OF FORMING THE SAME

DIRECTLY SAWING WAFERS COVERED WITH LIQUID MOLDING COMPOUND

Semiconductor product with interlocking metal-to-metal bonds and method for manufacturing thereof

Semiconductor device and process for manufacturing the same

A semiconductor device has a pad structure with a ring-shaped stress buffer layer between a metal pad and an under-bump metallization (UBM) layer. The stress buffer layer is formed of a dielectric layer with a dielectric constant less than 3.5, a polymer layer, or an aluminum layer. The stress buffer layer is a circular ring, a square ring, an octagonal ring, or any other geometric ring.

Semiconductor devices having metal bumps with flange

A semiconductor device having a terminal site (100) including a flat pad (110) of a first metal covered by a layer (130) of dielectric material, the layer over the pad parallel to the pad and having a window of a first diameter (132) exposing the surface of the underlying pad. The terminal site further has a patch-shaped film (140) of a second metal covering the surface of the exposed first metal and the surface of an annulus of the dielectric layer framing the window, the film patch having a second diameter (141) greater than the first diameter; and a bump (150) of a third metal adhering to the film, the bump having a third diameter (151) smaller than the second diameter, whereby the film protrudes like a flange from the bump.

Interconnect structures for preventing solder bridging, and associated systems and methods

Semiconductor dies having interconnect structures formed thereon, and associated systems and methods, are disclosed herein. In one embodiment, an interconnect structure includes a conductive material electrically coupled to an electrically conductive contact of a semiconductor die. The conductive material includes a first portion vertically aligned with the conductive contact, and a second portion that extends laterally away from the conductive contact. A solder material is disposed on the second portion of the interconnect structure such that the solder material is at least partially laterally offset from the conductive contact of the semiconductor die. In some embodiments, an interconnect structure can further include a containment layer that prevents wicking or other undesirable movement of the solder material during a reflow process.

USING AN INTERCONNECT BUMP TO TRAVERSE THROUGH A PASSIVATION LAYER OF A SEMICONDUCTOR DIE

A semiconductor die, which includes a first semiconductor device, a first passivation layer, and a first interconnect bump, is disclosed. The first passivation layer is over the first semiconductor device, which includes a first group of device fingers. The first interconnect bump is thermally and electrically connected to each of the first group of device fingers. Additionally, the first interconnect bump protrudes through a first opening in the first passivation layer.

Interconnect structure and method of fabricating same

An interconnect structure and a method of fabrication of the same are introduced. In an embodiment, a post passivation interconnect (PPI) structure is formed over a passivation layer of a substrate. A bump is formed over the PPI structure. A molding layer is formed over the PPI structure. A film is applied over the molding layer and the bump using a roller. The film is removed from over the molding layer and the bump, and the remaining material of the film on the molding layer forms the protective layer. A plasma cleaning is preformed to remove the remaining material of the film on the bump.

Semiconductor package and fabrication method thereof

A semiconductor package is provided, which includes: a first semiconductor device having a first top surface and a first bottom surface opposite to the first top surface; a plurality of conductive balls formed on the first top surface of the first semiconductor device; a second semiconductor device having a second top surface and a second bottom surface opposite to the second top surface; and a plurality of conductive posts formed on the second bottom surface of the second semiconductor device and correspondingly bonded to the conductive balls for electrically connecting the first semiconductor device and the second semiconductor device, wherein the conductive posts have a height less than 300 um. Therefore, the present invention can easily control the height of the semiconductor package and is applicable to semiconductor packages having fine-pitch conductive balls.

Chip structure having bonding wire

A chip structure includes a chip, a first metal layer, a second metal layer and a bonding wire. The first metal layer is disposed on the chip, and a material of the first metal layer includes nickel or nickel alloy. The second metal layer is disposed on the first metal layer, and a material of the second metal layer includes copper, copper alloy, aluminum, aluminum alloy, palladium or palladium alloy. The bonding wire is connected to the second metal layer, and a material of the bonding wire includes copper or copper alloy.

Directly Sawing Wafers Covered with Liquid Molding Compound

A method includes forming a passivation layer over a metal pad, wherein the metal pad is further overlying a semiconductor substrate of a wafer. A Post-Passivation Interconnect (PPI) is formed to electrically couple to the metal pad, wherein a portion of the PPI is overlying the passivation layer. A metal bump is formed over and electrically coupled to the PPI. The method further includes applying a molding compound over the metal bump and the PPI, applying a release film over the molding compound, pressing the release film against the molding compound, and curing the molding compound when the release film is pressed against the molding compound. The release film is then removed from the molding compound. The wafer is sawed into dies using a blade, with the blade cutting through the molding compound.

DISPLAY BACKPLANE AND MANUFACTURING METHOD THEREOF AND DISPLAY DEVICE

A display backplane is provided, including a base, wherein pixel circuits, bonding electrodes, and bonding connection wires are on the base; the bonding electrodes are coupled to the bonding connection wires in a one-to-one correspondence; the bonding electrodes and the bonding connection wires are on two opposite surfaces of the base; the pixel circuits and the bonding connection wires are on a same side of the base; one end of each bonding connection wire is coupled to the bonding electrode through the first via in the base; the other end of each of at least some bonding connection wires is coupled to the pixel circuit; and an orthographic projection of at least one of the bonding electrodes and the bonding connection wires on the base is not coincident with an orthographic projection of the pixel circuit on the base.

SEMICONDUCTOR PACKAGE

A semiconductor package includes a first structure having a first insulating layer and a first bonding pad penetrating the first insulating layer, and a second structure on the first structure and having a second insulating layer bonded to the first insulating layer, a bonding pad structure penetrating the second insulating layer and bonded to the first bonding pad, and a test pad structure penetrating the second insulating layer and including a test pad in an opening penetrating the second insulating layer and having a protrusion with a flat surface, and a bonding layer filling the opening and covering the test pad and the flat surface, the protrusion of the test pad extending from a surface in contact with the bonding layer, and the flat surface of the protrusion being within the opening and spaced apart from an interface between the bonding layer and the first insulating layer.

Durchkontaktierungssubstrat und ein Verfahren zur Herstellung eines Durchkontaktierungssubstrats

Ein Blindloch ist auf einem Substrat von einer ersten Seite des Substrats aus in Richtung einer zweiten Seite des Substrats gebildet. Ein Leiter ist in das Blindloch eingefüllt. Das Substrat wird von der gegenüberliegenden Seite aus abgetragen, um den Leiter, der in das Blindloch eingefüllt ist, freizulegen.

Halbleitervorrichtung aus einer galliumnitridartigen III-V-Halbleiterverbindung und Verfahren zu ihrer Herstellung

Semiconductor device

Integrated circuit element and packaging component

The invention provides an integrated circuit element and a packaging component. The integrated circuit element comprises a semiconductor substrate, a conductive column which is disposed on the semiconductor substrate and has a side wall surface and an upper surface, a boss lower metal layer which is disposed between the semiconductor substrate and the conductive column and has a surface area which is adjacently connected to the side wall surface of the conductive column and extends from the side wall surface, and a protection structure which is disposed on the side wall surface of a copper column and on the surface area of the boss lower metal layer. The protection structure is made of metal materials and the conductive column is composed by copper layers. The side wall protection structure covers at least a part of the side wall surface of the boss structure, and the protection structures disposed on the copper column side wall and on the surface area of the boss lower metal layer are ...

AN INTEGRATED CIRCUIT HAVING A HEAT SINK

A ROUTING LAYER FOR MITIGATING STRESS IN A SEMICONDUCTOR DIE

Thin 3D die with electromagnetic radiation blocking encapsulation

After forming a first electromagnetic radiation blocking layer over a front side of a device wafer, the device wafer is bonded to a handle substrate from the front side. A semiconductor substrate in the device wafer is thinned from its backside. Trenches are formed extending through the device wafer and the first electromagnetic radiation blocking layer such that the device wafer is singulated into semiconductor dies. A second electromagnetic radiation blocking layer portion is formed on a backside surface of and sidewalls surfaces of each of the semiconductor dies such that each of the semiconductor dies are fully encapsulated by the first and second electromagnetic radiation blocking layer portions.

MPS-C2 semiconductor device having shorter supporting posts

Disclosed is a MPS-C2 (Metal Post Soldering Chip Connection) semiconductor device having shorter supporting posts. Bonding pads are reentrant from a wafer-level packaging (WLP) layer formed on the active surface. A patterned UBM metal layer includes a plurality of UBM pads disposed on the bonding pads and at least a UBM island disposed on the WLP layer. The island area of the UBM island on the WLP layer is at least four times larger than the unit area of the UBM pads. A plurality of I/O pillars are one-to-one disposed on the UBM pads by plating and a plurality of supporting pillars are many-to-one disposed on the UBM island by one plating process. The unit footprint of the supporting pillars on the UBM island is smaller than the unit footprint of the I/O pillars on the UBM pads so as to compensate the height difference between the top jointing surfaces of the supporting pillars and the I/O pillars.

SEMICONDUCTOR ELEMENT AND METHOD FOR IDENTIFYING SEMICONDUCTOR ELEMENT

A semiconductor element encompasses a first external electrode on an upper surface side of a semiconductor chip, a second external electrode, spaced apart from the first external electrode, provided in parallel with the first external electrode; and a protective film covering the first and second external electrodes, having first and second windows to expose portions of upper surfaces of the first and second external electrodes, respectively. Planar patterns of the first and second windows are in two-fold rotational symmetry with respect to a center point of an area including the first and second external electrodes and to be asymmetric with respect to a center line between the first and second external electrodes. 1. A semiconductor element comprising:a first external electrode provided on an upper surface side of a semiconductor chip;a second external electrode, spaced apart from the first external electrode, provided in parallel with the first external electrode; anda protective film covering the first and second external electrodes, having first and second windows to expose portions of upper surfaces of the first and second external electrodes, respectively, whereinplanar patterns of the first and second windows are in two-fold rotational symmetry with respect to a center point of an area including the first and second external electrodes and to be asymmetric with respect to a center line between the first and second external electrodes.2. The semiconductor element of claim 1 , wherein the first and second windows have rectangular shapes claim 1 , respectively claim 1 , and positions of sides of the first and second windows are different in the longer side direction of the first and second windows.3. The semiconductor element of claim 1 , wherein a concave portion directed inward is provided at a corner portion of each planar pattern of the first and second windows.4. The semiconductor element of claim 1 , further comprising:a semiconductor substrate which ...

Method of manufacturing semiconductor packaging

The present disclosure is related to a method of providing a die structure for semiconductor packaging. The method includes providing a substrate with a bonding pad; forming a patterned mask layer on the substrate; forming an opening on the mask layer; depositing a conductive layer in the opening; forming a cap layer on the conductive layer, and removing the mask layer. The cap layer forming step allows the contacting area between the cap layer and the conductive layer to be substantially equal to the top surface area of the conductive layer by reflowing solder material prior to the removal of the mask layer.

Semiconductor chip and method of processing a semiconductor chip

Various embodiments provide a semiconductor chip, wherein the semiconductor chip comprises a first contact area and a second contact area both formed at a frontside of the semiconductor chip; a passivation layer arranged at the frontside between the first contact area and the second contact area; and a contact stack formed over the frontside of the semiconductor chip and comprising a plurality of layers, wherein at least one layer of the plurality of layers is removed from the passivation layer and boundary regions of the contact areas being adjacent to the passivation layer and wherein at least one another layer of the plurality of different layer is present in the boundary region of the contact areas adjoining the passivation layer. 1. A semiconductor chip comprising:a contact area formed at a frontside of the semiconductor chip, wherein a passivation layer is arranged at the frontside adjoining the contact area in a boundary region of the contact area;a multilayer metallization stack comprising an adhesion promoter layer, a contact layer and a planar protection layer, wherein the contact layer is arranged between the adhesion promoter layer and the protection layer,wherein only the adhesion promoter layer of the multilayer metallization stack is formed above at least portions of the contact area, the boundary region and portions of the passivation layer and the contact layer and the planar protection layer are formed only above portions of the contact area.2. The semiconductor chip according to claim 1 , wherein the multilayer metallization stack extends over at least portions of the contact area while at the boundary region only the adhesion promoter layer remains claim 1 , so that sidewalls of the contact layer and the planar protection layer are exposed to the boundary region and the adhesion layer extends laterally over the contact area and the passivation layer claim 1 , wherein the passivation layer is partially free of the adhesion layer.3. The ...

Bump-on-Trace Structures with High Assembly Yield

A package includes first package component, which further includes a first metal trace at a surface of the first package component, with the first metal trace having a trace width measured in a direction perpendicular to a lengthwise direction of the first metal trace. The first package component further includes a second metal trace at the surface of the first package component. The first metal trace and the second metal trace are parallel to each other. A second package component is overlying the first package component, wherein the second package component includes a metal bump. A solder region bonds the metal bump to the first metal trace, wherein the solder region contacts a top surface and sidewalls of the first portion of the first metal trace. A ratio of a volume of the solder region to the trace width is between about 1,100 μm2 and about 1,300 μm2.

Conductive external connector structure and method of forming

External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure.

3DIC Package and Method Forming the Same

A method includes bonding a first device die to a second device die through face-to-face bonding, wherein the second device die is in a device wafer, forming a gap-filling region to encircle the first device die, performing a backside-grinding process on the device wafer to reveal a through-via in the second device die, and forming a redistribution structure on the backside of the device wafer. The redistribution structure is electrically connected to the first device die through the through-via in the second device die. A supporting substrate is bonded to the first device die.

SURFACE-MOUNTED CHIP

Halbleitermodule und Verfahren zu deren Bildung

Gemäß einer Ausführungsform der vorliegenden Erfindung umfasst ein Halbleitermodul ein erstes Halbleitergehäuse, das einen ersten Halbleiterchip (50) aufweist, der in einem ersten Einkapselungsmittel (80) angeordnet ist. Eine Öffnung (100) ist im ersten Einkapselungsmittel (80) angeordnet. Ein zweites Halbleitergehäuse (150), das einen zweiten Halbleiterchip umfasst, ist in einem zweiten Einkapselungsmittel (180) angeordnet. Das zweite Halbleitergehäuse (150) ist wenigstens teilweise innerhalb der Öffnung (100) im ersten Einkapselungsmittel (80) angeordnet.

Device for allowing electrical interconnection of superconducting materials between cold detection circuit and read-out circuit of bolometer, has stack including layers made of conducting materials and formed perpendicularly with trajectory

Ce dispositif comprend un premier circuit électronique (1) connecté à un second circuit électronique (2) à l'aide d'au moins une interconnexion électrique (8) définissant un trajet des électrons entre lesdits circuits. La ou chaque interconnexion électrique (8) comporte au moins un empilement formant miroir à phonons, ledit empilement comprenant au moins deux couches (3, 4) de matériaux conducteurs différents, chaque empilement étant réalisé perpendiculairement audit trajet d'électrons, et au moins l'une des couches de chaque empilement étant constituée d'un matériau supraconducteur.

반도체 장치, 반도체 패키지 및 반도체 패키지의 제조 방법

... 반도체 장치가 개시된다. 반도체 장치는, 기판 상에 형성된 도전 성분(conductive component); 상기 기판 상에 형성되며 개구부를 구비하는 패시베이션층으로서, 상기 개구부가 상기 도전 성분의 적어도 일부분을 노출하는, 상기 패시베이션층; 및 상기 패시베이션층 상에서 상기 개구부를 채우며, 상기 도전 성분과 전기적으로 연결되는 패드 구조물을 포함한다. 상기 패드 구조물은 상기 개구부의 내벽 상에 및 상기 개구부 주위의 상기 패시베이션층 상면 상에 콘포말하게 형성되며, 순서대로 적층된 도전 배리어층, 제1 시드층, 식각 정지층 및 제2 시드층을 포함하는 하부 도전층, 상기 하부 도전층 상에 형성되며, 상기 개구부를 적어도 부분적으로 채우는 제1 패드층, 및 상기 제1 패드층 상에 형성되며, 상기 패시베이션층의 상기 상면 상에 배치되는 상기 하부 도전층의 외주 부분과 접촉하는 제2 패드층을 포함한다.

Integrated circuit devices and packaging assembly

A sidewall protection structure is provided for covering at least a portion of a sidewall surface of a bump structure, in which a protection structure on the sidewall of a Cu pillar and a surface region of an under-bump-metallurgy (UBM) layer is formed of at least one non-metal material layers, for example a dielectric material layer, a polymer material layer, or combonations thereof.

Chip package and method for forming the same

A chip package including a substrate is provided. A sensing region or device region of the substrate is electrically connected to a conducting pad. A first insulating layer is disposed on the substrate. A redistribution layer is disposed on the first insulating layer. A first portion and a second portion of the redistribution layer are electrically connected to the conducting pad. A second insulating layer conformally extends on the first insulating layer, and covers side surfaces of the first portion and the second portion. A protection layer is disposed on the second insulating layer. A portion of the second insulating layer is located between the protection layer and the first insulating layer. A method of forming the chip package is also provided.

SEMICONDUCTOR DEVICE

A semiconductor chip includes a substrate, an electrode pad formed on the substrate, an insulating layer covering the substrate and the electrode pad, and having an opening exposing a portion of a surface of the electrode pad, a first conductive layer formed on the exposed portion of the surface of the electrode pad and extending to a surface of the insulating layer, and a second conductive layer formed on the first conductive layer, covering the first conductive layer in a plan view, and having an outer edge portion which is located further out than an outer edge of the first conductive layer in a plan view. The outer edge portion of the second conductive layer has at least one curved portion. At least one portion of the curved portion is located between the outer edge of the first conductive layer and an outer edge of the second conductive layer in a plan view.

ELECTRONIC COMPONENT MOUNTING STRUCTURE

An electronic component mounting structure includes: an electronic component including a plurality of bump electrodes that includes a base resin provided on an active face of the electronic component and a plurality of conductive films that cover a part of a surface of the base resin, expose an area excluding the part of the surface, and are electrically coupled to a plurality of electrode terminals provided on the active face; and a substrate including a plurality of terminals. In the structure, the electronic component is mounted on the substrate, and the base resin includes: a first opening surrounding the plurality of the electrode terminals; a connection portion in which a part of one ends of the plurality of the conductive films that are drawn out on the surface of the base resin is disposed, the other ends of the conductive films being coupled to the electrode terminals; and a bonding portion that is bonded to the substrate, and is formed in an area excluding the first opening and ...

Routing layer for mitigating stress in a semiconductor die

A routing layer for a semiconductor die is disclosed. The routing layer includes traces interconnecting integrated circuit bond-pads to UBMs. The routing layer is formed on a layer of dielectric material. The routing layer includes conductive traces arranged underneath the UBMs as to absorb stress from solder bumps attached to the UMBs. Traces beneath the UBMs protect parts of the underlying dielectric material proximate the solder bumps, from the stress.

Method for Producing a Connection Between Component Parts, and Component Made of Component Parts

A method for producing a connection between component parts and a component made of component parts are disclosed. In an embodiment, a includes providing a first component part having a first exposed insulation layer and a second component part having a second exposed insulation layer, wherein each of the insulation layers has at least one opening, joining together the first and second component parts such that the opening of the first insulation layer and the opening of the second insulation layer overlap in top view, wherein an Au layer and a Sn layer are arranged one above the other in at least one of the openings and melting the Au layer and the Sn layer to form an AuSn alloy, wherein the AuSn alloy forms a through-via after cooling electrically conductively connecting the first component part to the second component part.

Gallium nitride-based III-V group compound semiconductor

A gallium nitride-based III-V Group compound semi-conductor device has a gallium nitride-based III-V Group compound semiconductor layer provided over a substrate, and an ohmic electrode provided in contact with the semiconductor layer. The ohmic electrode is formed of a metallic material, and has been annealed.

Method for manufacturing a semiconductor device having multiple heat sinks

A method for manufacturing a semiconductor device is provided, the method including: mounting a first element on a wiring substrate, placing a first heat sink on the first element with a metal material interposed between the first heat sink and the first element, attaching the first heat sink to the first element via the metal material by heating and melting the metal material, and mounting a second element on the wiring substrate after the steps of attaching the first heat sink to the first element.

Semiconductor device and method of manufacture

A semiconductor device structure and method of manufacturing a semiconductor device. The semiconductor device may comprise a semiconductor die having a top major surface that has one or more electrical contacts formed thereon, an opposing bottom major surface, and side surfaces; a molding material encapsulating the top major surface, the bottom major surface and the side surfaces of the semiconductor die, wherein the molding material defines a package body that has a top surface and a side surface; wherein the plurality of electrical contacts are exposed on the top surface of the package body and a metal layer is arranged over and electrically connected to the electrical contacts and wherein the metal layer extends to and at least partially covers a side surface of the package body.

DISPLAY DEVICE, METHOD OF MANUFACTURING THE SAME, AND TILED DISPLAY DEVICE HAVING THE SAME

A display device comprises a substrate comprising a first contact hole, a barrier insulating layer disposed on the substrate and comprising a second contact hole, a fan-out line disposed in a first metal layer on the barrier insulating layer and comprising a pad part inserted into the second contact hole, a display layer disposed on the fan-out line, and a flexible film disposed below the substrate and having a lead electrode which is inserted into the first contact hole and bonded to the pad part. The pad part comprises a first base, a first protrusion integral with the first base and protruding from the first base, and a second protrusion protruding from the first protrusion.

Semiconductor Device Having Through Silicon Vias and Manufacturing Method Thereof

In the semiconductor device, a semiconductor substrate has first and second surfaces. A circuitry layer is formed over the first surface and a first insulating layer is further formed over the circuitry layer. A second insulating layer including a first insulating element is formed over the second surface. A third insulating layer including a second insulating element different from the first insulating element of the second insulating layer is formed over the second surface with an intervention of the second insulating layer therebetween. A penetration electrode penetrates through the semiconductor substrate, the circuitry layer, the first insulating layer, the second insulating layer and the third insulating layer. 1. A method of forming a semiconductor device , comprising:providing a semiconductor substrate having a plurality of transistors on a first surface thereof;forming a first interlayer dielectric film on the first surface;forming a multi-level wiring structure on the first interlayer dielectric film;thinning the semiconductor substrate from a surface opposite to the first surface to form a second surface of the semiconductor substrate;forming a first back insulating layer on the second surface of the semiconductor substrate;forming a second back insulating layer in direct contact with the first back insulating layer, the second back insulating layer having a back surface away from first back insulating layer, wherein the second back insulating layer includes an insulating material different from the first back insulating layer;forming an opening on the second back insulating layer, sequentially etching the first back insulating layer and the semiconductor substrate through the opening to form a substrate through hole, wherein the substrate through hole at least reaches the first interlayer dielectric film;forming a through silicon via within the substrate through hole, wherein the through silicon via extends from the first surface of the semiconductor ...

INTEGRATED CIRCUIT COMPRISING A HEAT SINK

Ce circuit intégré comporte un dissipateur (60) de chaleur dépourvu de composants électroniques et interposé entre une face arrière (36) d'une puce électronique basse (24) et une face extérieure supérieure (56) d'un boîtier, ce dissipateur comportant une face avant (62) disposée sur la face arrière de la puce électronique basse et une face arrière (64), cette face arrière étant comprise entre un premier et un second plans parallèles au plan d'un substrat (10), le premier et le second plans étant situés, respectivement, à 0,15*H en-dessous et à 0,15*H au-dessus d'une face arrière (32) d'une puce électronique haute (22, 26), où H est la hauteur de la face arrière (32) de la puce électronique haute par rapport à une face intérieure (20) du substrat. La conductivité thermique à 25 °C du dissipateur est au moins deux fois supérieure à la conductivité thermique d'une couche épaisse du boîtier.

SURFACE-MOUNT CHIP

L'invention concerne une puce à montage en surface réalisée dans et sur un substrat de silicium ayant une face avant et un flanc, la puce comprenant : au moins une métallisation destinée à être brasée à un dispositif extérieur, cette métallisation comprenant une première portion (30a) recouvrant au moins une partie de la face avant du substrat, et une deuxième portion (30b) recouvrant au moins une partie du flanc du substrat ; et une région en silicium poreux (20), incluse dans le substrat, séparant la deuxième portion (30b) de la métallisation du reste du substrat.

Methods for etching copper during the fabrication of integrated circuits

Methods for etching copper in the fabrication of integrated circuits are disclosed. In one exemplary embodiment, a method for fabricating an integrated circuit includes providing an integrated circuit structure including a copper bump structure and a copper seed layer underlying and adjacent to the copper bump structure and etching the seed layer selective to the copper bump structure using a wet etching chemistry consisting of H3PO4 in a volume percentage of about 0.07 to about 0.36, H2O2 in a volume percentage of about 0.1 to about 0.7, and a remainder of H2O, and optionally NH4OH.

SEMICONDUCTOR DEVICE

This semiconductor device has a laminated chip resulting from joining a first semiconductor chip (100) and a second semiconductor chip (200). On the primary surface of the first semiconductor chip are formed a first electrode pad (110) and a first bump (120) formed on the first electrode pad. On the primary surface of the second semiconductor chip (200) is formed a second bump (220) for joining to the first bump. The first electrode pad (110) has an aperture such that the central portion has a stepped shape. The first bump (120) has a concavity of which the central portion is depressed formed in a manner so as to straddle the stepped shape of the aperture and peripheral section of the first electrode pad (110).

Bonded system with coated copper conductor

A semiconductor component includes a semiconductor die and a copper-containing electrical conductor. The semiconductor die has a semiconductor device region, an aluminum-containing metal layer on the semiconductor device region, and at least one additional metal layer on the aluminum-containing metal layer which is harder than the aluminum-containing metal layer. The copper-containing electrical conductor is bonded to the at least one additional metal layer of the semiconductor die via an electrically conductive coating of the copper-containing electrical conductor which is softer than the copper of the copper-containing electrical conductor.

FRONT-TO-BACK BONDING WITH THROUGH-SUBSTRATE VIA (TSV)

Methods for forming a semiconductor device structure are provided. The method includes providing a first semiconductor wafer and a second semiconductor wafer. A first transistor is formed in a front-side of the first semiconductor wafer, and no devices are formed in the second semiconductor wafer. The method further includes bonding the front-side of the first semiconductor wafer to a backside of the second semiconductor wafer and thinning a front-side of the second semiconductor wafer. After thinning the second semiconductor wafer, a second transistor is formed in the front-side of the second semiconductor wafer. At least one first through substrate via (TSV) is formed in the second semiconductor wafer, and the first TSV directly contacts a conductive feature of the first semiconductor wafer.

Semiconductor Device Assembly Including a Chip Carrier, Semiconductor Wafer and Method of Manufacturing a Semiconductor Device

A semiconductor device includes a chip carrier and a semiconductor die with a semiconductor portion and a conductive structure. A soldered layer mechanically and electrically connects the chip carrier and the conductive structure at a soldering side of the semiconductor die. At the soldering side an outermost surface portion along an edge of the semiconductor die has a greater distance to the chip carrier than a central surface portion. The conductive structure covers the central surface portion and at least a section of an intermediate surface portion tilted to the central surface portion. Solder material is effectively prevented from coating such semiconductor surfaces that are prone to damages and solder-induced contamination is significantly reduced.

Semiconductor package

A semiconductor package includes a substrate, through-electrodes penetrating the substrate, first bumps spaced apart from each other in a first direction parallel to a top surface of the substrate and electrically connected to the through-electrodes, respectively, and at least one second bump disposed between the first bumps and electrically insulated from the through-electrodes. The first bumps and the at least one second bump constitute one row in the first direction. A level of a bottom surface of the at least one second bump from the top surface of the substrate is a substantially same as levels of bottom surfaces of the first bumps from the top surface of the substrate.

Manufacturing method of ultra-thin semiconductor device package assembly

A manufacturing method of ultra-thin semiconductor device package structure is provided. Firstly, a wafer including a plurality of semiconductor devices is provided, and one of the semiconductor devices has an active surface having an active region and an outer region and a back surface. A first electrode and a second electrode are arranged in the active region, and the outer region has a cutting portion and a channel portion. Subsequently, a trench is formed in the channel portion, and filled with a conductive structure. The wafer is fixed on a supporting board, and then a thinning process and a deposition process of a back electrode layer are performed on the back surface in sequence. Thereafter, the supporting board is removed and a plurality of contacting pads is formed. A cutting process is performed along the cutting portion.

Semiconductor device

The semiconductor device includes a semiconductor chip 1, a first electrode pad 21 laminated on the semiconductor chip 1, an intermediate layer 4 having a rectangular shape defined by first edges 49a and second edges, and a plurality of bumps 5 arranged to sandwich the intermediate layer 4 by cooperating with the semiconductor chip 1. The first edges 49a extend in the direction x, whereas the second edges extend in the direction y. The plurality of bumps 5 include a first bump 51 electrically connected to the first electrode pad 21 and a second bump 52 electrically connected to the first electrode pad 21. The first bump 51 is arranged at one end in the direction x and one end in the direction y.

Routing layer for mitigating stress in a semiconductor die

A routing layer for a semiconductor die is disclosed. The routing layer includes traces interconnecting integrated circuit bond-pads to UBMs. The routing layer is formed on a layer of dielectric material. The routing layer includes conductive traces arranged underneath the UBMs as to absorb stress from solder bumps attached to the UMBs. Traces beneath the UBMs protect parts of the underlying dielectric material proximate the solder bumps, from the stress.

Semiconductor device for use in flip-chip bonding, which reduces lateral displacement

A semiconductor device includes multilayer chips in which a first semiconductor chip and a second semiconductor chip are bonded together. A first electrode pad is formed on a principal surface of the first semiconductor chip, and a first bump is formed on the first electrode pad. A second bump is formed on the principal surface of the second semiconductor chip such that the second bump is bonded to the first bump. The first electrode pad has an opening, and the opening and an entire peripheral portion of the opening form a stepped shape form a stepped shape. The first bump has a recessed shape that is recessed at a center thereof and covers the stepped shape.

Package with solder regions aligned to recesses

A method includes forming a passivation layer over a portion of a metal pad, forming a polymer layer over the passivation layer, and exposing the polymer layer using a photolithography mask. The photolithography mask has an opaque portion, a transparent portion, and a partial transparent portion. The exposed polymer layer is developed to form an opening, wherein the metal pad is exposed through the opening. A Post-Passivation Interconnect (PPI) is formed over the polymer layer, wherein the PPI includes a portion extending into the opening to connect to the metal pad.

Semiconductor device

A semiconductor device has a semiconductor element provided with a functional surface on which a functional circuit is formed and with a back surface facing in the opposite direction to the functional surface, while also having a lead supporting the semiconductor element and electrically connected to the semiconductor element, and a resin package covering at least a portion of the semiconductor element and the lead. The semiconductor element has a functional surface side electrode formed on the functional surface and equipped with a functional surface side raised part that projects in the direction in which the functional surface faces. The functional surface side raised part of the functional surface side electrode is joined to the lead by solid state bonding.

ELECTRONIC APPARATUS AND METHOD FOR MANUFACTURING ELECTRONIC APPARATUS

An electronic apparatus includes: a first substrate; an electrode over the first substrate; a first conductor having a porous structure above the first substrate, the first conductor covering an upper surface and a side surface of the electrode; and an insulator above the first substrate, the insulator covering an upper surface and a side surface of the first conductor, wherein the insulator has an opening that exposes the first conductor.

SEMICONDUCTOR PACKAGE

A semiconductor package is provided. The semiconductor package includes: a first stack including a first semiconductor substrate; a through via that penetrates the first semiconductor substrate in a first direction; a second stack that includes a second face facing a first face of the first stack, on the first stack; a first pad that is in contact with the through via, on the first face of the first stack; a second pad including a concave inner side face that defines an insertion recess, the second pad located on the second face of the second stack; and a bump that connects the first pad and the second pad, wherein the bump includes a first upper bump on the first pad, and a first lower bump between the first upper bump and the first pad.

Halbleiterchip und Verfahren zum Bilden einer Chip-Anschlussfläche

Es werden ein Halbleiterchip mit unterschiedlichen Chip-Anschlussflächen und ein Verfahren zum Bilden eines Halbleiterchips mit unterschiedlichen Chip-Anschlussflächen offenbart. Bei einigen Ausführungsbeispielen umfasst das Verfahren das Abscheiden einer Barriereschicht über einer Chipvorderseite, das Abscheiden einer Kupferschicht nach dem Abscheiden der Barriereschicht und das Entfernen eines Teils der Kupferschicht, der sich außerhalb einer ersten Chip-Anschlussflächenregion befindet, wobei ein verbleibender Abschnitt der Kupferschicht innerhalb der ersten Chip-Anschlussflächenregion eine Oberflächenschicht der Chip-Anschlussfläche bildet. Das Verfahren umfasst ferner das Entfernen eines Teils der Barriereschicht, der sich außerhalb der ersten Chip-Anschlussflächenregion befindet.

A routing layer for mitigating stress in a semiconductor die

A routing layer for a semiconductor die is disclosed. The routing layer includes traces interconnecting integrated circuit bond-pads to UBMs. The routing layer is formed on a layer of dielectric material. The routing layer includes conductive traces arranged underneath the UBMs as to absorb stress from solder bumps attached to the UMBs. Traces beneath the UBMs protect parts of the underlying dielectric material proximate the solder bumps, from the stress.

Integrated circuit package and method for forming the same

The invention relates to an integrated circuit package and a method for forming the same. The method includes forming an electrical connector over a substrate of a wafer, and molding a polymer layer, with at least a portion of the electrical connector molded in the polymer layer. A first sawing step is performed to form a trench in the polymer layer. After the first sawing step, a second sawing step is performed to saw the wafer into a plurality of dies.

보울 형상 솔더 구조물

... 대체로 기판에 관한 장치가 개시된다. 이러한 장치에서, 제1 금속 층이 기판 상에 있다. 제1 금속 층은 개구를 갖는다. 제1 금속 층의 개구는 저부 및 저부로부터 연장된 하나 이상의 측부들을 갖는다. 제2 금속 층이 제1 금속 층 상에 있다. 제1 금속 층 및 제2 금속 층은 보울 형상 구조물을 제공한다. 보울 형상 구조물의 내부 표면은 제1 금속 층의 개구 및 그 상부의 제2 금속 층에 대응하여 한정된다. 보울 형상 구조물의 개구는 리플로우 공정 동안에 접합 재료를 수용하도록 그리고 그를 적어도 부분적으로 보유하도록 구성된다.

Semiconductor device package and device for semiconductor packaging

Semiconductor device and method for forming a semiconductor device

Chip package and manufacturing method thereof

Bond Pad Having Ruthenium Covering Passivation Sidewall

A method of forming bond pads includes providing a substrate including an integrated circuit (IC) device formed thereon having an oxidizable uppermost metal interconnect layer which provides a plurality of bond pads that are coupled to circuit nodes on the IC device. The plurality of bond pads include a metal bond pad area. At least one passivation layer provides a trench including dielectric sidewalls above the metal bond pad area. A ruthenium (Ru) layer is deposited directly on the dielectric sidewalls and directly on the metal bond pad area, which removes the need for a barrier layer lining the dielectric sidewalls of the trench. The Ru layer is patterned to provide a bond pad surface for the plurality of bond pads.

Pad structure for front side illuminated image sensor

The present disclosure relates to an integrated circuit having a bond pad with a relatively flat surface topography that mitigates damage to underlying layers. In some embodiments, the integrated circuit has a plurality of metal interconnect layers within a dielectric structure over a substrate. A passivation structure is arranged over the dielectric structure. The passivation structure has a recess with sidewalls connecting a horizontal surface of the passivation structure to an upper surface of the passivation structure. A bond pad is arranged within the recess and has a lower surface overlying the horizontal surface. One or more protrusions extend outward from the lower surface through openings in the passivation structure to contact one of the metal interconnect layers. Arranging the bond pad within the recess and over the passivation structure mitigates stress to underlying layers during bonding without negatively impacting an efficiency of an image sensing element within the substrate ...

POWER MOSFET

A power MOSFET includes a substrate, a dielectric layer, solder balls, first and second patterned-metal layers. The substrate includes an active surface, a back surface, a source region and a gate region on the active surface, and a drain region on the back surface. The first patterned-metal layer disposed on the active surface includes a source electrode, a gate electrode, a drain electrode and a connecting trace. The source and gate electrodes electrically connect the source and gate regions. The connecting trace located at an edge of the substrate electrically connects the drain electrode. The dielectric layer disposed on the active surface exposes the first patterned-metal layer. The second patterned-metal layer includes UBM layers covering the source, gate and drain electrodes and a connecting metal layer covering the connecting trace and extending to the edge to electrically connect the drain region. The solder balls are disposed on the UBM layers.

LOW TEMPERATURE BONDED STRUCTURES

Devices and techniques including process steps make use of recesses in conductive interconnect structures to form reliable low temperature metallic bonds. A fill layer is deposited into the recesses prior to bonding. First conductive interconnect structures are bonded at ambient temperatures to second metallic interconnect structures using direct bonding techniques, with the fill layers in the recesses in one or both of the first and second interconnect structures.

Semiconductor device and method of manufacturing the same

A semiconductor device in which reliability of a bonding pad to which a conductive wire is bonded is achieved. A bonding pad having an OPM structure is formed of an Al—Cu alloy film having a Cu concentration of 2 wt % or more. By increasing the Cu concentration, the Al—Cu alloy film forming the bonding pad is hardened. Therefore, the bonding pad is difficult to be deformed by impact in bonding of a Cu wire, and deformation of an OPM film as following the deformation of the bonding pad can be reduced. In this manner, concentration of a stress on the OPM film caused by the impact from the Cu wire can be reduced, and therefore, the breakage of the OPM film can be prevented.

Semiconductor device

A semiconductor device of the present disclosure includes: a semiconductor substrate having a first main surface; a first aluminum electrode having a first surface facing the first main surface and a second surface opposite to the first surface, the first aluminum electrode being disposed on the semiconductor substrate; a passivation film that covers a peripheral edge of the second surface and that is provided with an opening from which a portion of the second surface is exposed; and a copper film. The second surface exposed from the opening is provided with a recess that is depressed toward the first surface. The copper film is disposed in the recess.

Halbleiterelement und Verfahren zu dessen Herstellung

Bei einem Halbleiterelement (1) gemäß der vorliegenden Erfindung werden eine stromlose Nickel-Phosphor-Abscheidungsschicht (4) und eine stromlose Gold-Abscheidungsschicht (5) sowohl auf einer Vorderseiten-Elektrode (3a) als auch auf einer Rückseiten-Elektrode (3b) eines Vorder-Rückseiten-Leitungstyp-Substrats (2) ausgebildet. Die Vorderseiten-Elektrode (3a) und die Rückseiten-Elektrode (3b) werden aus Aluminium oder einer Aluminiumlegierung gebildet. Das Verhältnis der Dicke der auf der Vorderseiten-Elektrode (3a) ausgebildeten stromlosen Nickel-Phosphor-Abscheidungsschicht (4) zu der Dicke der auf der Rückseiten-Elektrode (3b) ausgebildeten stromlosen Nickel-Phosphor-Abscheidungsschicht (4) liegt in einem Bereich zwischen 1,0 und 3,5. Mit dem Halbleiterelement (1) der vorliegenden Erfindung kann das Auftreten von Fehlstellen in Lötstellen während der Anbringung mit einem Lötverfahren verhindert werden.

氮化镓系Ⅲ-Ⅴ族化合物半导体器件

... 一种氮化镓系III-V族化合物半导体器件，其特征在于包括：具有第一和第二主表面的衬底；形成在所述衬底的第一主表面上、包括n型氮化镓系III-V族化合物半导体层和p型氮化镓系III-V族化合物半导体层的半导体叠层结构；在除去设置在所述n型半导体层上的p型层后露出的n型层上形成的第一电极；以及形成在所述p型半导体层上的第二电极；其中，所述第二电极具有从由铬、镍、金、钛、铂构成的一组中选出的至少二种材料的金属材料。 ...

SURFACE-MOUNT CHIP

드라이버 IC용 금속 범프 구조체 및 그의 제조 방법

... 본 발명에 따른 드라이버 IC용 금속 범프 구조체는, 금속 패드 상에 설치되어 금속 패드 상의 리세스를 한정하는 패시베이션층, 리세스 내에, 그리고 금속 패드 및 패시베이션층 상에 설치되는 접착층, 리세스 내에 설치되어 접착층을 완전히 커버하는 금속 범프, 및 금속 범프 상에 설치되고 금속 범프가 주위 분위기에 노출되지 않도록 금속 범프를 완전히 커버하는 캡핑층을 포함한다.

ETCHING SOLUTION CONSISTING OF NITRIC ACID, HYDROCHLORIC ACID, ORGANIC ACID AND WATER FOR ETCHING A METAL LAYER, AN ETCHING METHOD USING THE SAME, AND A METHOD OF FABRICATING A SEMICONDUCTOR PRODUCT USING THE SAME

PURPOSE: An etching solution for etching a metal layer, an etching method using the same, and a method of fabricating a semiconductor product using the same are provided to enhance an etching speed of the metal layer having Au without increasing contents of nitric acid and hydrochloric acid. CONSTITUTION: A metal etching solution includes nitric acid, hydrochloric acid, organic acid and water, in which an amount of the organic acid is less than an amount of the nitric acid. A content of the nitric acid is about 20 to 40 wt%, a content of the hydrochloric acid is about 3 to 18 wt%, and a content of the organic acid is about 0.1 to 3 wt%. The organic acid is at least one selected from ascorbic acid or fatty acid. The fatty acid is at least one selected from oxalic acid, citric acid, acetylsalicylic acid, acetic acid, propionic acid, butyric acid, glycolic acid, formic acid, lactic acid, malic acid, succinic acid, or tartaric acid. © KIPO 2008 ...

Semiconductor device

A semiconductor device includes a bump structure formed on a post-passivation interconnect (PPI) line and surrounded by a protection structure. The protection structure includes a polymer layer and at least one dielectric layer. The dielectric layer may be formed on the top surface of the polymer layer, underlying the polymer layer, inserted between the bump structure and the polymer layer, inserted between the PPI line and the polymer layer, covering the exterior sidewalls of the polymer layer, or combination thereof.

Conductive structure for a semiconductor integrated circuit

SEMICONDUCTOR DEVICE

A semiconductor device provided with a pad having improved moisture resistance. The semiconductor device is provided with a circuit section including a plurality of semiconductor elements formed on a semiconductor substrate; an insulating stacked layer which covers the circuit section, is formed on the semiconductor substrate and includes a passivation film as a topmost layer with an opening; a ferroelectric capacitor formed in the insulating stacked layer; a wiring structure which is formed in the insulating stacked layer and connected with the semiconductor element and the ferroelectric capacitor; a pad electrode structure which is connected with the wiring structure, formed in the insulating stacked layer and exposed from the opening on the passivation film; a conductive pad protection film which includes a Pd film, covers the pad electrode structure through the opening on the passivation film, and extends on the passivation film; and a stud bump or a bonding wire which is connected ...

Polymer layers embedded with metal pads for heat dissipation

An integrated circuit structure includes a metal pad, a passivation layer including a portion over the metal pad, a first polymer layer over the passivation layer, and a first Post-Passivation Interconnect (PPI) extending into to the first polymer layer. The first PPI is electrically connected to the metal pad. A dummy metal pad is located in the first polymer layer. A second polymer layer is overlying the first polymer layer, the dummy metal pad, and the first PPI. An Under-Bump-Metallurgy (UBM) extends into the second polymer layer to electrically couple to the dummy metal pad.

Interconnect structure and method of fabricating same

An interconnect structure and a method of fabrication of the same are introduced. In an embodiment, a post passivation interconnect (PPI) structure is formed over a passivation layer of a substrate. A bump is formed over the PPI structure. A molding layer is formed over the PPI structure. A film is applied over the molding layer and the bump using a roller. The film is removed from over the molding layer and the bump, and the remaining material of the film on the molding layer forms the protective layer. A plasma cleaning is preformed to remove the remaining material of the film on the bump.

SEMICONDUCTOR DEVICE PACKAGE AND A METHOD OF MANUFACTURING THE SAME

A semiconductor package includes: (1) a substrate; (2) a first isolation layer disposed on the substrate, the first isolation layer including an opening; (3) a pad disposed on the substrate and exposed from the opening; (4) an interconnection layer disposed on the pad; and (5) a conductive post including a bottom surface, the bottom surface having a first part disposed on the interconnection layer and a plurality of second parts disposed on the first isolation layer.

Semiconductor device with pads of enhanced moisture blocking ability

A semiconductor device is provided having a pad with an improved moisture blocking ability. The semiconductor device has: a circuit portion including a plurality of semiconductor elements formed on a semiconductor substrate; lamination of insulator covering the circuit portion, including a passivation film as an uppermost layer having openings; ferro-electric capacitors formed in the lamination of insulator; wiring structure formed in the lamination of insulator and connected to the semiconductor elements and the ferro-electric capacitors; pad electrodes connected to the wiring structure, formed in the lamination of insulator and exposed in the openings of the passivation film; a conductive pad protection film, including a Pd film, covering each pad electrode via the opening of the passivation film, and extending on the passivation film; and stud bump or bonding wire connected to the pad electrode via the conductive pad protection film.

Semiconductor Devices, Methods of Manufacture Thereof, and Packaged Semiconductor Devices

Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a plurality of contact pads over a substrate, and forming an insulating material over the plurality of contact pads and the substrate. The insulating material is patterned to form an opening over each of the plurality of contact pads, and the plurality of contact pads is cleaned. The method includes forming an under-ball metallization (UBM) structure over the plurality of contact pads and portions of the insulating material. Cleaning the plurality of contact pads recesses a top surface of each of the plurality of contact pads.

Semiconductor product with interlocking metal-to-metal bonds and method for manufacturing thereof

A structure and method for performing metal-to-metal bonding in an electrical device. For example and without limitation, various aspects of this disclosure provide a structure and method that utilize an interlocking structure configured to enhance metal-to-metal bonding.

Acoustic wave resonator and method for manufacturing the same

An acoustic wave resonator includes: a substrate; a resonating portion formed on a first surface of the substrate; a metal pad connected to the resonating portion through a via hole formed in the substrate; and a protective layer disposed on a second surface of the substrate and including a plurality of layers, wherein the plurality of layers includes an internal protective layer directly in contact with the second surface of the substrate and formed of an insulating material including an adhesion that is stronger than an adhesion of other layers, among the plurality of layers.

CHIPGEHÄUSE UND VERFAHREN ZUR HERSTELLUNG EINES CHIPGEHÄUSES

Es wird ein Verfahren zur Herstellung eines Chipgehäuses bereitgestellt, wobei das Verfahren folgende Schritte aufweist: Bilden (210) einer Schichtanordnung über einem Träger, Anordnen (220) eines Chips, einschließlich einer oder mehrerer Kontaktstellen, über der Schichtanordnung, wobei der Chip zumindest einen Teil der Schichtanordnung bedeckt, und selektives Entfernen (230) eines oder mehrerer Abschnitte der Schichtanordnung und Verwenden des Chips als Maske, so dass zumindest ein Teil der Schichtanordnung, der vom Chip nicht bedeckt ist, nicht entfernt wird.

Verfahren zur Herstellung einer Verbindung zwischen Bauteilen und Bauelement aus Bauteilen

Es wird ein Verfahren zur Herstellung einer elektrischen Verbindung zwischen einem ersten Bauteil (1) und einem zweiten Bauteil (2) angegeben, bei dem das erste Bauteil mit einer ersten freiliegenden Isolationsschicht (II) und das zweite Bauteil mit einer zweiten freiliegenden Isolationsschicht (21) bereitgestellt werden, wobei die Isolationsschichten jeweils zumindest eine Öffnung (1IC, 2IC) aufweisen. Die Bauteile werden derart zusammengeführt, dass sich die Öffnung (1IC) der ersten Isolationsschicht und die Öffnung (2IC) der zweiten Isolationsschicht in Draufsicht überlappen, wobei in mindestens einer der Öffnungen (1IC, 2IC) eine Au-Schicht (S1, S2) und eine Sn-Schicht (S1, S2) übereinander angeordnet sind. Die Au-Schicht und die Sn-Schicht werden zur Bildung einer AuSn-Legierung aufgeschmolzen, wobei die AuSn-Legierung nach einer Abkühlung eine Durchkontaktierung (12) bildet, welche das erste Bauteil mit dem zweiten Bauteil elektrisch leitend verbindet. Des Weiteren wird ein Bauelement ...

Processing of Thick Metal Pads

TECHNIQUE FOR EFFICIENTLY PATTERNING AN UNDERBUMP METALLIZATION LAYER USING A DRY ETCH PROCESS

By patterning an underbump metallization layer stack (105) on the basis of a dry etch process (111), significant advantages may be achieved compared to conventional techniques involving a highly complex wet chemical etch process. In particular embodiments, a titanium tungsten layer or any other appropriate last layer (105B) of an underbump metallization layer stack (105) may be etched on the basis of a plasma etch process (107) using a fluorine-based chemistry and oxygen as a physical component. Moreover, appropriate cleaning processes (110, 113) may be performed for removing particles (109) and residues (112) prior to and after the plasma-based patterning process (107). © KIPO & WIPO 2008 ...

Manufacturing method of wafer level chip scale package structure

A manufacturing method of wafer level chip scale package structure is provided. The manufacturing method includes the following steps. Firstly, a wafer including a plurality of semiconductor devices is provided, and one of the semiconductor devices has an active surface having an active region and an outer region and a back surface. A first electrode and a second electrode are arranged in the active region, and the outer region has a cutting portion and a passing portion. Next, a patterned protecting layer having a plurality of openings is formed on the active surface and only respectively exposing the first and second electrodes and passing portion. Subsequently, a thinning process and a process for deposition of a back electrode layer are performed on the back surface in sequence. Subsequently, a selective etching process is performed to form a groove at the passing portion which exposes the back electrode layer, and a conductive structure connected to the back electrode layer is formed ...

METHOD AND STRUCTURE FOR TOP METAL FORMATION OF LIQUID CRYSTAL ON SILICON DEVICES

The present invention provides an LCOS device having improved bonding pad features. The device has a substrate, a transistor layer overlying the substrate and an interlayer dielectric layer overlying the transistor layer. A first conductive layer is overlying the interlayer dielectric layer and a second interlayer dielectric layer is overlying the first conductive layer. An enlarged opening for a bonding pad structure is in a first portion of the second interlayer dielectric layer. A barrier metal layer is formed within the enlarged opening to form a liner that covers exposed regions of the enlarged opening. A metal material is overlying the liner to fill the enlarged opening. A thickness of an aluminum material is overlying the metal material. The device has a bonding pad structure formed from a first portion of the thickness of the aluminum material and is coupled to the metal material in the enlarged opening.

Semiconductor device having pad structure with stress buffer layer

A semiconductor device has a pad structure with a ring-shaped stress buffer layer between a metal pad and an under-bump metallization (UBM) layer. The stress buffer layer is formed of a dielectric layer with a dielectric constant less than 3.5, a polymer layer, or an aluminum layer. The stress buffer layer is a circular ring, a square ring, an octagonal ring, or any other geometric ring.

Method of manufacturing semiconductor device including plural semiconductor chips stacked together

Such a method is disclosed that includes preparing first and second semiconductor chips, the first semiconductor chip including a first electrode formed on one surface thereof and a second electrode formed on the other surface thereof so as to overlap the first electrode as viewed from a stacking direction, and the second semiconductor chip including a third electrode formed on one surface thereof and a fourth electrode formed on the other surface thereof so as not to overlap the third electrode as viewed from the stacking direction, and stacking the first and second semiconductor chips in the stacking direction so that the second electrode is connected to the third electrode by using a bonding tool including a concave at a position corresponding to the fourth electrode.

Discrete semiconductor device package and manufacturing method

Disclosed is a discrete semiconductor device package ( 100 ) comprising a semiconductor die ( 110 ) having a first surface and a second surface opposite said first surface carrying a contact ( 112 ); a conductive body ( 120 ) on said contact; an encapsulation material ( 130 ) laterally encapsulating said conductive body; and a capping member ( 140, 610 ) such as a solder cap, a further semiconductor die or a combination thereof in conductive contact with the solder portion, said solder cap extending over the encapsulation material. A further solder cap ( 150 ) may be provided over the first surface. A method of manufacturing such a discrete semiconductor device package is also disclosed.

Forming Metal Bonds with Recesses

A method includes forming a first device die, which includes depositing a first dielectric layer, and forming a first metal pad in the first dielectric layer. The first metal pad includes a recess. The method further includes forming a second device die including a second dielectric layer and a second metal pad in the second dielectric layer. The first device die is bonded to the second device die, with the first dielectric layer being bonded to the second dielectric layer, and the first metal pad being bonded to the second metal pad. 1. A device comprising: a first dielectric layer; and', a diffusion barrier contacting the first dielectric layer; and', 'a metallic material between opposite portions of the diffusion barrier, wherein in a cross-sectional view of the first metal pad, an edge portion of the metallic material is recessed from a top edge of a nearest portion of the diffusion barrier to form an air gap; and, 'a first metal pad comprising], 'a first device die comprising a second dielectric layer bonded to the first dielectric layer; and', 'a second metal pad bonded to the first metal pad through metal-to-metal direct bonding., 'a second device die comprising2. The device of claim 1 , wherein the air gap further extends into the second metal pad.3. The device of claim 1 , wherein the air gap is formed between a sidewall of the diffusion barrier claim 1 , a surface of the metallic material claim 1 , and a surface of the second metal pad.4. The device of claim 1 , wherein the air gap is formed between a sidewall of the diffusion barrier claim 1 , a surface of the metallic material claim 1 , and a surface of the second dielectric layer.5. The device of claim 1 , wherein a surface of the metallic material in the first metal pad and facing the air gap is rounded.6. The device of claim 1 , wherein a surface of the second metal pad facing the air gap is rounded.7. The device of claim 1 , wherein the first device die further comprises a third metal pad comprising ...

SEMICONDUCTOR DEVICES HAVING METAL BUMPS WITH FLANGE

A semiconductor device having a terminal site () including a flat pad () of a first metal covered by a layer () of dielectric material, the layer over the pad parallel to the pad and having a window of a first diameter () exposing the surface of the underlying pad. The terminal site further has a patch-shaped film () of a second metal covering the surface of the exposed first metal and the surface of an annulus of the dielectric layer framing the window, the film patch having a second diameter () greater than the first diameter; and a bump () of a third metal adhering to the film, the bump having a third diameter () smaller than the second diameter, whereby the film protrudes like a flange from the bump. 18-. (canceled)9. A method for fabricating a semiconductor chip comprising:providing a semiconductor wafer having a plurality of devices, each device having a plurality of terminal sites;forming a bond pad over each of the plurality of terminal sites, the bond pad being flat and made of a first metal adhering to semiconductor wafer;depositing a layer of dielectric material across the semiconductor wafer covering the bond pads of all terminal sites;patterning the layer of dielectric material over each bond pad to open a window of a first diameter to each bond pad, the window exposing the surface of the underlying bond pad; sputtering a metallic seed layer of a refractory metal over the semiconductor wafer;', 'subsequently patterning the metallic seed layer to form patches of the refractory metal over the window and the surface of the bond pad at each terminal site, the patches having a second diameter greater than the first diameter; and', 'using the patches as a seed material, plating to form the flange on the bond pad at each terminal site, the flange being a film of a second metal adhering to the first metal as well as to the layer of dielectric material; and, 'forming a flange for bumps on each bond pad; comprisingforming a bump of a third metal on each flange, ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

An improvement is achieved in the reliability of a semiconductor device. Over a semiconductor substrate, an interlayer insulating film is formed and, over the interlayer insulating film, a pad is formed. Over the interlayer insulating film, an insulating film is formed so as to cover the pad. In the insulating film, an opening is formed to expose a part of the pad. The pad is a pad to which a copper wire is to be electrically coupled and which includes an Al-containing conductive film containing aluminum as a main component. Over the Al-containing conductive film in a region overlapping the opening in plan view, a laminated film including a barrier conductor film, and a metal film over the barrier conductor film is formed. The metal film is in an uppermost layer. The barrier conductor film is a single-layer film or a laminated film including one or more layers of films selected from the group consisting of a Ti film, a TiN film, a Ta film, a TaN film, a W film, a WN film, a TiW film, and a TaW film. The metal film is made of one or more metals selected from the group consisting of Pd, Au, Ru, Rh, Pt, and Ir. 1. A semiconductor device , comprising:a semiconductor substrate;a first insulating film formed over the semiconductor substrate;a pad formed over the first insulating film;a second insulating film formed over the first insulating film so as to cover the pad; andan opening formed in the second insulating film to expose a part of the pad,wherein the pad is a pad to which a copper wire is to be electrically coupled and which includes an Al-containing conductive film containing aluminum as a main component,wherein, over the Al-containing conductive film in a region overlapping the opening in plan view, a first laminated film including a first conductor film, and a second conductor film over the first conductor film is formed,wherein the second conductor film is in an uppermost layer of the first laminated film,wherein the first conductor film is a single-layer film ...

PRE-PLATED SUBSTRATE FOR DIE ATTACHMENT

A method for attaching a semiconductor die to a substrate includes providing a substrate that includes an attachment layer at a surface of the substrate. The attachment layer is covered by a protective flash plating layer. The protective flash plating layer has a reflow temperature less than or equal to a reflow temperature of the attachment layer. The method further includes preheating the substrate to a temperature greater than or equal to a reflow temperature of the attachment layer, attaching a semiconductor die to the attachment layer, and cooling the substrate and semiconductor die. 19-. (canceled)10. A method of preparing a substrate for attachment to a semiconductor die , the method comprising:providing a substrate;selectively forming an attachment layer on a surface of the substrate at one or more die attachment locations, the attachment layer having a reflow temperature; andcovering the attachment layer with a protective flash plating layer, the protective flash plating layer having a reflow temperature that is less than or equal to the reflow temperature of the attachment layer.11. The method of claim 10 , wherein the formation of the attachment layer includes selectively plating one or more attachment stacks to the surface of the substrate at the one or more die attachment locations.12. The method of claim 10 , wherein the formation of the attachment layer includes selectively stamping one or more attachment preforms onto the surface of the substrate at the one or more die attachment locations.13. The method of claim 10 , wherein the formation of the attachment layer includes spot welding one or more attachment preforms at diagonal corners of each of the one or more die attachment locations.14. The method of claim 10 , wherein the formation of the attachment layer includes hot rolling one or more attachment preforms onto the surface of the substrate at the one or more die attachment locations.15. The method of claim 10 , wherein the protective flash ...

Package assembly

In some embodiments, the present disclosure relates to a package assembly having a bump on a first substrate. A molding compound is on the first substrate and contacts sidewalls of the bump. A no-flow underfill layer is on a conductive region of a second substrate. The no-flow underfill layer and the conductive region contact the bump. A mask layer is arranged on the second substrate and laterally surrounds the no-flow underfill layer. The no-flow underfill layer contacts the substrate between the conductive region and the mask layer.

Interconnect structures with intermetallic palladium joints and associated systems and methods

Interconnect structures with intermetallic palladium joints are disclosed herein. In one embodiment, a method of forming an interconnect structure includes depositing a first conductive material comprising nickel on a first conductive surface of a first die, and depositing a second conductive material comprising nickel on a second conductive surface of a second die spaced apart from the first surface. The method further includes depositing a third conductive material on the second conductive material, and thermally compressing tin/solder between the first and third conductive materials to form an intermetallic palladium joint that extends between the first conductive material and the second conductive material such that one end of the intermetallic palladium joint is bonded directly to the first conductive material and an opposite end of the intermetallic palladium joint is bonded directly to the second conductive material.

CHIP PARTS AND METHOD FOR MANUFACTURING THE SAME, CIRCUIT ASSEMBLY HAVING THE CHIP PARTS AND ELECTRONIC DEVICE

A chip part according to the present invention includes a substrate having a penetrating hole, a pair of electrodes formed on a front surface of the substrate and including one electrode overlapping the penetrating hole in a plan view and another electrode facing the one electrode, and an element formed on the front surface side of the substrate and electrically connected to the pair of electrodes. 1. A bidirectional Zener diode chip , comprising:a semiconductor substrate of a first conductivity type;an insulating film which covers a front surface of the semiconductor substrate;a first diffusion region of a second conductivity type formed in the semiconductor substrate and exposed at the front surface of the semiconductor substrate;a second diffusion region of the second conductivity type formed in the semiconductor substrate across an interval from the first diffusion region and exposed at the front surface of the semiconductor substrate;contact holes in the insulating film for selectively exposing the first diffusion region and the second diffusion region through the insulating film;a first electrode formed on the front surface of the semiconductor substrate and connected to the first diffusion region; anda second electrode formed on the front surface of the semiconductor substrate and connected to the second diffusion region,wherein the first electrode includes a plurality of first extraction electrodes which are defined to cover the first diffusion region,wherein the second electrode includes a plurality of second extraction electrodes which are defined to cover the second diffusion region along the second extraction electrodes extending parallel to the first extraction electrodes in a lengthwise direction as viewed from a plan view,wherein the plurality of first extraction electrodes and the plurality of second extraction electrodes are defined in a comb-toothed shape engaging with each other,wherein a shape of the contact holes is an elongated shape in the ...

DUAL BOND PAD STRUCTURE FOR PHOTONICS

A dual bond pad structure for a wafer with laser die attachment and methods of manufacture are disclosed. The method includes forming a bonding layer on a surface of a substrate. The method further includes forming solder bumps on the bonding layer. The method further includes patterning the bonding layer to form bonding pads some of which comprise the solder bumps thereon. The method further includes attaching a laser diode to selected bonding pads using solder connections formed on the laser diode. The method further includes attaching an interposer substrate to the solder bumps formed on the bonding pads. 1. A method , comprising:forming a masking layer over a bonding layer;patterning the bonding layer to form bonding pads;attaching a laser diode to selected bonding pads using solder connections formed on the laser diode such that the laser diode is unobstructed by solder bumps and the selected bonding pads; andattaching an interposer substrate to the solder bumps which are on the bonding pads such that the interposer substrate is spaced away and disconnected from the laser diode.2. The method of claim 1 , wherein the masking layer is formed over portions of the bonding layer which are to be attached to the laser diode.3. The method of claim 1 , wherein the solder bumps are formed through a resist pattern claim 1 , after the forming of the masking layer over the bonding layer.4. The method of claim 1 , further comprising forming the solder bumps on the bonding layer.5. The method of claim 4 , wherein the patterning of the bonding layer is performed after the forming of the solder bumps such that the solder bumps and the masking layer protect underlying portions of the bonding layer during an etching process.6. The method of claim 5 , further comprising removing the masking layer and attaching the solder connections formed on the laser diode directly to the bonding pads which are formed underneath the masking layer prior to removal.7. The method of claim 6 , ...

CONDUCTIVE CONNECTIONS, STRUCTURES WITH SUCH CONNECTIONS, AND METHODS OF MANUFACTURE

A solder connection may be surrounded by a solder locking layer () and may be recessed in a hole () in that layer. The recess may be obtained by evaporating a vaporizable portion () of the solder connection. Other features are also provided. 1. A manufacturing method comprising: one or more first components each of which comprises solder and a material sublimatable or vaporizable when the solder is melted; and', 'a first layer comprising a top surface and one or more holes in the top surface, each hole containing at least a segment of a corresponding first component;, 'obtaining a first structure comprisingheating each first component to sublimate or vaporize at least part of each sublimatable or vaporizable material and provide an electrically conductive connection at a location of each first component;wherein in the heating operation at least part of each first component recedes down from the top surface to provide or increase a recess in each hole at the top surface.2. The method of wherein each hole is a through-hole.3. The method of wherein each hole's sidewall is a dielectric sidewall.4. The method of wherein the first layer is dielectric.5. The method of wherein the first layer is formed by molding.6. The method of further comprising:obtaining a second structure with one or more protruding conductive posts; andinserting each conductive post into a corresponding recess provided or increased in the heating operation, and forming a solder bond in each recess between the corresponding conductive post and the corresponding electrically conductive connection.7. The method of wherein before the heating operation claim 1 , at least a segment of each first component either:comprises of a solder core coated with the sublimatable or vaporizable material; orconsists of the sublimatable or vaporizable material.8. The method of wherein in obtaining the first structure claim 7 , the one or more first components are formed before the first layer.9. The method of wherein in ...

Method for processing an electronic component and an electronic component

According to various embodiments an electronic component includes: at least one electrically conductive contact region; a contact pad including a self-segregating composition disposed over the at least one electrically conductive contact region; a segregation suppression structure disposed between the contact pad and the at least one electrically conductive contact region, wherein the segregation suppression structure includes more nucleation inducing topography features than the at least one electrically conductive contact region for perturbing a chemical segregation of the self-segregating composition by crystallographic interfaces of the contact pad defined by the nucleation inducing topography features.

Semiconductor product with interlocking metal-to-metal bonds and method for manufacturing thereof

A structure and method for performing metal-to-metal bonding in an electrical device. For example and without limitation, various aspects of this disclosure provide a structure and method that utilize an interlocking structure configured to enhance metal-to-metal bonding.

Semiconductor Chip and Method for Forming a Chip Pad

A semiconductor chip with different chip pads and a method for forming a semiconductor chip with different chip pads are disclosed. In some embodiments, the method comprises depositing a barrier layer over a chip front side, depositing a copper layer after depositing the barrier layer, and removing a part of the copper layer located outside a first chip pad region, wherein a remaining portion of the copper layer within the first chip pad region forms a surface layer of the chip pad. The method further comprises removing a part of the barrier layer located outside the first chip pad region.

Integrated Circuit Packages and Methods for Forming the Same

A method includes forming an electrical connector over a substrate of a wafer, and molding a polymer layer, with at least a portion of the electrical connector molded in the polymer layer. A first sawing step is performed to form a trench in the polymer layer. After the first sawing step, a second sawing step is performed to saw the wafer into a plurality of dies. 1. A chip comprising:a substrate;a metal pad over the substrate;a passivation layer having a portion over the metal pad;a polymer layer over the passivation layer, wherein the polymer layer extends to an edge of the chip, and a first edge of the polymer layer forms a part of the edge of the chip;an electrical connector; and a first horizontal surface substantially perpendicular to the edge of the chip; and', 'a slant sidewall surface, wherein the first horizontal surface is connected to a first end of the slant sidewall surface, and the slant sidewall surface is neither perpendicular to nor parallel to the edge of the chip., 'a molding compound encircling a portion of the electrical connector, wherein a lower portion of the electrical connector is in the molding compound, and wherein the molding compound comprises a surface comprising2. The chip of further comprising a second horizontal surface substantially perpendicular to the edge of the chip claim 1 , wherein the second horizontal surface is connected to a second end of the slant sidewall surface claim 1 , and the first horizontal surface claim 1 , the slant sidewall surface claim 1 , and the second horizontal surface form a step.3. The chip of claim 1 , wherein the first horizontal surface extends to the electrical connector.4. The chip of further comprising:a plurality of dielectric layers underlying the metal pad; anda seal ring proximal edges of the chip, wherein the seal ring extends into the plurality of dielectric layers.5. The chip of claim 4 , wherein the molding compound comprises:first portions on opposite sides of electrical connector, ...

SEMICONDUCTOR DEVICES, SEMICONDUCTOR PACKAGES, AND METHODS OF MANUFACTURING THE SEMICONDUCTOR DEVICES

A semiconductor device includes a conductive component on a substrate, a passivation layer on the substrate and including an opening that exposes at least a portion of the conductive component, and a pad structure in the opening and located on the passivation layer, the pad structure being electrically connected to the conductive component. The pad structure includes a lower conductive layer conformally extending on an inner sidewall of the opening, the lower conductive layer including a conductive barrier layer, a first seed layer, an etch stop layer, and a second seed layer that are sequentially stacked, a first pad layer on the lower conductive layer and at least partially filling the opening, and a second pad layer on the first pad layer and being in contact with a peripheral portion of the lower conductive layer located on the top surface of the passivation layer. 1. A semiconductor device comprising:a conductive component on a substrate;a passivation layer on the substrate and including an opening therein, wherein the opening exposes at least a portion of the conductive component; and a lower conductive layer conformally extending on an inner sidewall of the opening and on a top surface of the passivation layer around the opening, the lower conductive layer including a conductive barrier layer, a first seed layer, an etch stop layer, and a second seed layer that are sequentially stacked,', 'a first pad layer on the lower conductive layer, the first pad layer at least partially filling the opening, and', 'a second pad layer on the first pad layer, the second pad layer laterally extending beyond the first pad layer to contact a peripheral portion of the lower conductive layer located on the top surface of the passivation layer., 'a pad structure on the passivation layer and in the opening, the pad structure electrically connected to the conductive component, the pad structure comprising2. The semiconductor device of claim 1 , wherein the second pad layer is ...

HYBRID BONDING WITH THROUGH SUBSTRATE VIA (TSV)

A semiconductor device structure is provided. The semiconductor device structure includes a first polymer layer formed between a first substrate and a second substrate, and a first conductive layer formed over the first polymer. The semiconductor device includes a first through substrate via (TSV) formed over the first conductive layer, and the conductive layer is in direct contact with the first TSV and the first polymer. 1. A semiconductor device structure , comprising:a first polymer layer formed between a first substrate and a second substrate;a first conductive layer formed over the first polymer; anda first through substrate via (TSV) formed over the first conductive layer, wherein the conductive layer is in direct contact with the first TSV and the first polymer.2. The semiconductor device structure as claimed in claim 1 , further comprising:an interconnect structure formed over the first substrate, wherein the interconnect structure is in direct contact with the first TSV.3. The semiconductor device structure as claimed in claim 1 , further comprising:a first transistor formed in the first substrate; anda first contact plug formed below the first transistor, wherein a bottom surface of the first contact plug is level with a bottom surface of the first TSV.4. The semiconductor device structure as claimed in claim 3 , wherein a sidewall of the first contact plug is aligned with a sidewall of the first conductive layer.5. The semiconductor device structure as claimed in claim 1 , further comprising:a second TSV formed in the second substrate, wherein a first width of the first TSV is smaller than a second width of the second TSV.6. The semiconductor device structure as claimed in claim 5 , further comprising:a second polymer layer formed between the first substrate and the second substrate; anda second conductive layer formed below the second polymer layer, wherein the second conductive layer is in direct contact with the second polymer layer and the second TSV ...

PAD STRUCTURE FOR FRONT SIDE ILLUMINATED IMAGE SENSOR

The present disclosure relates to an integrated circuit. The integrated circuit includes a plurality of interconnects within a dielectric structure over a substrate. A passivation structure is arranged over the dielectric structure. The passivation structure has sidewalls connected to one or more upper surfaces of the passivation structure. A bond pad is arranged directly between the sidewalls of the passivation structure. An upper passivation layer is disposed over the passivation structure and the bond pad. The upper passivation layer extends from over an upper surface of the bond pad to within a recess in the upper surface of the bond pad. 1. An integrated circuit , comprising:a plurality of interconnects within a dielectric structure over a substrate;a passivation structure arranged over the dielectric structure and having sidewalls connected to one or more upper surfaces of the passivation structure;a bond pad arranged directly between the sidewalls of the passivation structure; andan upper passivation layer disposed over the passivation structure and the bond pad, wherein the upper passivation layer extends from over an upper surface of the bond pad to within a recess in the upper surface of the bond pad.2. The integrated circuit of claim 1 ,wherein the upper passivation layer comprises both a first sidewall and a second sidewall laterally between the bond pad and the passivation structure; andwherein the first sidewall and the second sidewall of the upper passivation layer face one another and are separated from one another by a non-zero distance.3. The integrated circuit of claim 1 , wherein the upper passivation layer has surfaces defining a ‘U’ shaped segment between an outermost sidewall of the bond pad and one of the sidewalls of the passivation structure.4. The integrated circuit of claim 1 , wherein the passivation structure comprises a first material and a second material over the first material claim 1 , the upper passivation layer having a sidewall ...

Semiconductor structure and manufacturing method thereof

A semiconductor structure includes a substrate; a first dielectric layer disposed over the substrate; a conductive member surrounded by the first dielectric layer; a second dielectric layer disposed over the substrate, the first dielectric layer and the conductive member; a capacitor disposed over the conductive member and the second dielectric layer; a third dielectric layer disposed over the second dielectric layer and the capacitor; a conductive via disposed over and contacted with the conductive member, and extended through the second dielectric layer, the capacitor and the third dielectric layer; a conductive pad disposed over and contacted with the conductive via; a fourth dielectric layer disposed over the third dielectric layer and surrounding the conductive pad; and a conductive bump disposed over and electrically connected to the conductive pad, wherein the third dielectric layer includes an oxide layer and a nitride layer.

SUBSTRATE STRUCTURE WITH SELECTIVE SURFACE FINISHES FOR FLIP CHIP ASSEMBLY

The present disclosure relates to a substrate structure with selective surface finishes used in flip chip assembly, and a process for making the same. The disclosed substrate structure includes a substrate body, a metal structure with a first finish area and a second finish area, a first surface finish, and a second surface finish. The metal structure is formed on a top surface of the substrate body, the first surface finish is formed over the first finish area of the metal structure, and the second surface finish is formed over the second finish area of the metal structure. The first surface finish is different from the second surface finish. 1. An apparatus comprising:a substrate body;a first metal structure formed on a top surface of the substrate body and having a first finish area and a second finish area;a first surface finish provided over the first finish area; anda second surface finish that is different from the first surface finish and provided over the second finish area.2. The apparatus of wherein the first surface finish is electroless nickel electroless palladium immersion gold (ENEPIG).3. The apparatus of wherein the first surface finish comprises:a first layer formed of gold with a thickness between 0.06 μm and 0.14 μm;a second layer formed of palladium with a thickness between 0.08 μm and 0.16 μm; anda third layer formed of nickel with a thickness between 0.3 μm and 0.5 μm, wherein the third layer is over the first finish area, the second layer is over the third layer, and the first layer is over the second layer.4. The apparatus of wherein the first surface finish is bussless NiAu or electroless palladium immersion gold (EPIG).5. The apparatus of wherein the second surface finish is an organic surface protectorant (OSP).6. The apparatus of wherein a thickness of the second surface finish is between 0.2 μm and 0.4 μm.7. The apparatus of wherein the first surface finish comprises gold and the second surface finish does not comprise gold.8. The ...

Method of manufacturing semiconductor device

To provide a semiconductor device capable of having improved adhesion between a plating film and a wiring layer. A method of manufacturing the semiconductor device includes a step of forming a wiring layer having a surface covered with an oxide film, a step of removing a portion of the oxide film by dry etching to form, in the oxide film, a first opening f exposing a portion of the wiring layer, a step of forming a passivation film covering the wiring layer, is provided with a second opening communicated with the first opening, and is made of an insulating resin material, and a step of growing a plating film on the wiring layer exposed from the first and second openings.

Integrated Circuit Structure Having Dies with Connectors of Different Sizes

An embodiment is a structure comprising a substrate, a first die, and a second die. The substrate has a first surface. The first die is attached to the first surface of the substrate by first electrical connectors. The second die is attached to the first surface of the substrate by second electrical connectors. A size of one of the second electrical connectors is smaller than a size of one of the first electrical connectors. 1. A structure comprising:an interposer;a first die on a first surface of the interposer, the first die being electrically and mechanically coupled to the interposer by first connectors, the first connectors having a first diameter and having a first pitch between adjacent ones of the first connectors; and a first under bump metal (UBM) structure on a lower side of the second die facing the interposer;', 'a first metal pillar electrically and mechanically coupled to the first UBM structure;', 'a second UBM structure on the first surface of the interposer;', 'a second metal pillar electrically and mechanically coupled to the second UBM structure; and', 'a solder material between and electrically coupling the first metal pillar and the second metal pillar, wherein sidewalls of the first metal pillar are free of the solder material., 'a second die on the first surface of the interposer, the second die being electrically and mechanically coupled to the interposer by second connectors, the second connectors having a second diameter and having a second pitch between adjacent ones of the second connectors, the first diameter being greater than the second diameter, and the first pitch being greater than the second pitch, wherein each of the second connectors comprises2. The structure of claim 1 , wherein the solder material extends along sidewalls of the second metal pillar toward the first surface of the interposer.3. The structure of claim 2 , wherein sidewalls of the second UBM structure are covered by the solder material.4. The structure of claim 1 ...

Semiconductor device with pads of enhanced moisture blocking ability

A semiconductor device is provided having a pad with an improved moisture blocking ability. The semiconductor device has: a circuit portion including a plurality of semiconductor elements formed on a semiconductor substrate; lamination of insulator covering the circuit portion, including a passivation film as an uppermost layer having openings; ferro-electric capacitors formed in the lamination of insulator; wiring structure formed in the lamination of insulator and connected to the semiconductor elements and the ferro-electric capacitors; pad electrodes connected to the wiring structure, formed in the lamination of insulator and exposed in the openings of the passivation film; a conductive pad protection film, including a Pd film, covering each pad electrode via the opening of the passivation film, and extending on the passivation film; and stud bump or bonding wire connected to the pad electrode via the conductive pad protection film.

SEMICONDUCTOR PACKAGE

A semiconductor package includes; a redistribution substrate including a redistribution pattern, a semiconductor chip mounted on a top surface of the redistribution substrate, and a connection terminal between the semiconductor chip and the redistribution substrate. The redistribution substrate further includes; a pad structure including a pad interconnection and a pad via, disposed between the redistribution pattern and the connection terminal, wherein the pad structure is electrically connected to the redistribution pattern and a top surface of the pad structure contacts the connection terminal, a shaped insulating pattern disposed on a top surface of the redistribution pattern, and a pad seed pattern disposed on the redistribution pattern and covering the shaped insulating pattern. 1. A semiconductor package comprising:a redistribution substrate including a redistribution pattern;a semiconductor chip mounted on a top surface of the redistribution substrate; anda connection terminal between the semiconductor chip and the redistribution substrate,{'claim-text': ['a pad structure including a pad interconnection and a pad via, disposed between the redistribution pattern and the connection terminal, wherein the pad structure is electrically connected to the redistribution pattern and a top surface of the pad structure contacts the connection terminal;', 'a shaped insulating pattern disposed on a top surface of the redistribution pattern; and', 'a pad seed pattern disposed on the redistribution pattern and covering the shaped insulating pattern.'], '#text': 'wherein the redistribution substrate further includes:'}2. The semiconductor package of claim 1 , wherein the pad structure comprises:a first metal pattern and a second metal pattern sequentially stacked on the pad interconnection, wherein the connection terminal contacts a top surface of the second metal pattern.3. The semiconductor package of claim 1 , wherein the redistribution substrate further includes an ...

Polymer Layers Embedded with Metal Pads for Heat Dissipation

An integrated circuit structure includes a metal pad, a passivation layer including a portion over the metal pad, a first polymer layer over the passivation layer, and a first Post-Passivation Interconnect (PPI) extending into to the first polymer layer. The first PPI is electrically connected to the metal pad. A dummy metal pad is located in the first polymer layer. A second polymer layer is overlying the first polymer layer, the dummy metal pad, and the first PPI. An Under-Bump-Metallurgy (UBM) extends into the second polymer layer to electrically couple to the dummy metal pad. 1. An integrated circuit structure comprising:a metal pad;a passivation layer comprising a portion over the metal pad;a first polymer layer comprising a portion over the passivation layer;a dummy metal pad in the first polymer layer, wherein the dummy metal pad is electrically floating;a second polymer layer over the first polymer layer and the dummy metal pad; anda first Under-Bump-Metallurgy (UBM) extending into the second polymer layer to electrically couple to the dummy metal pad.2. The integrated circuit structure of claim 1 , wherein a top surface and a bottom surface of the dummy metal pad are coplanar with a top surface and a bottom surface claim 1 , respectively claim 1 , of the first polymer layer.3. The integrated circuit structure of further comprising:a package component comprising a surface metallic feature; anda solder region bonding the surface metallic feature in the package component to the first UBM, wherein the dummy metal pad, the solder region, and the surface metallic feature in combination are electrically floating.4. The integrated circuit structure of further comprising:a third polymer layer between the first polymer layer and the second polymer layer; anda Post-Passivation Interconnect (PPI) extending into to the third polymer layer, wherein the PPI electrically couples the dummy metal pad to the first UBM.5. The integrated circuit structure of further comprising: ...

SEMICONDUCTOR COPPER METALLIZATION STRUCTURE AND RELATED METHODS

Implementations of semiconductor packages may include: a silicon die including a pad, the pad including aluminum and copper; a passivation layer over at least a portion of the silicon die and a layer of one of a polyimide (PI) a polybenzoxazole (PBO), or a polymer resin coupled to the passivation layer. The package may include a first copper layer coupled over the pad, the first copper layer being about 1 microns to about 20 microns thick; a second copper layer coupled over the first copper layer, the second copper layer may be about 5 microns to about 40 microns thick; where a width of the first copper layer above the pad may be wider than a width of the second copper layer above the pad. The first and second copper layers may be configured to bond with a heavy copper wire or solder with a copper clip. 1. A semiconductor package comprising:a silicon die comprising a pad, the pad comprising one of aluminum copper (AlCu); aluminum copper silicon (AlCuSi); aluminum copper tungsten (AlCuW); aluminum silicon (AlSi); and any combination thereof;a passivation layer over at least a portion of the silicon die;a layer of one of a polyimide (PI), a polybenzoxazole (PBO), a polymer resin, and any combination thereof coupled to the passivation layer;a first copper layer coupled directly over and to the pad and at least a portion of the layer of one of a polyimide (PI), a polybenzoxazole (PBO), a polymer resin, and any combination thereof, the first copper layer being 1 microns to 20 microns thick; anda second copper layer coupled over the first copper layer, the second copper layer being 5 microns to 40 microns thick;wherein a width of the first copper layer above the pad is wider than a width of the second copper layer above the pad; andwherein the first and second copper layers are configured to one of bond with a heavy copper wire and solder with a copper clip.2. A semiconductor package of claim 1 , wherein the heavy copper wire is more than 5 mil in diameter.3. The ...

Semiconductor device

A semiconductor device suitable for preventing malfunction is provided. The semiconductor device includes a semiconductor chip 1 , a first electrode pad 21 laminated on the semiconductor chip 1 , an intermediate layer 4 having a rectangular shape defined by first edges 49 a and second edges, and a plurality of bumps 5 arranged to sandwich the intermediate layer 4 by cooperating with the semiconductor chip 1 . The first edges 49 a extend in the direction x, whereas the second edges extend in the direction y. The plurality of bumps 5 include a first bump 51 electrically connected to the first electrode pad 21 and a second bump 52 electrically connected to the first electrode pad 21 . The first bump 51 is arranged at one end in the direction x and one end in the direction y.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A method of manufacturing a semiconductor device includes providing a semiconductor substrate, forming, over a main surface the semiconductor substrate, a first insulating film, forming, over the first insulating film, an Al-containing conductive film containing aluminum as a main component, patterning the Al-containing conductive film to form a pad, forming, over the first insulating film, a second insulating film to cover the pad therewith, forming an opening in the second insulating film, and electrically coupling a copper wire to the pad exposed from the opening. 1. A method of manufacturing a semiconductor device , the method comprising:(a) providing a semiconductor substrate;(b) forming, over a main surface the semiconductor substrate, a first insulating film;(c) forming, over the first insulating film, an Al-containing conductive film containing aluminum as a main component;(d) patterning the Al-containing conductive film to form a pad;(e) forming, over the first insulating film, a second insulating film to cover the pad therewith;(f) forming an opening in the second insulating film;(g) electrically coupling a copper wire to the pad exposed from the opening;(h) after the (c) and before the (g), forming a first conductor film over the Al-containing conductive film; and(i) after the (h) and before the (g), forming a second conductor film over the first conductor film,wherein the first conductor film includes a single-layer film or a laminated film including one or more layers of films selected from a group consisting of a titanium film, a titanium nitride film, a tantalum film, a tantalum nitride film, a tungsten film, a tungsten nitride film, a titanium-tungsten film, and a tantalum-tungsten film,wherein the second conductor film comprises one or more metals selected from a group consisting of palladium, gold, ruthenium, rhodium, platinum, and iridium, andwherein, in the (g), the copper wire is bonded to the second conductor film.2. The method of manufacturing ...

Metal Routing Architecture for Integrated Circuits

A device includes a substrate, a metal pad over the substrate, and a metal trace electrically disconnected from the metal pad. The metal pad and the metal trace are level with each other. A passivation layer includes a portion overlapping an edge portion of the metal pad. A metal pillar is overlying the metal pad, and is electrically connected to the metal pad. The metal trace has a portion overlapped by the metal pillar.

METALLIC RIBBON FOR POWER MODULE PACKAGING

A metallic ribbon for power module packaging is described. The metallic ribbon has a rectangular, oval or oblong cross section. The composition of the metallic ribbon is silver-palladium alloy containing 0.2 to 6 wt % Pd. The metallic ribbon has a thickness of 10 μm to 500 μm. The width of the metallic ribbon is 2 to 100 times its thickness. The metallic ribbon includes a plurality of grains. The average grain size of the grains observed in the transverse cross section is 2 μm to 10 μm. The metallic ribbon has a plurality of twin grains observed in the transverse cross section, and the number of twin grains observed in the transverse cross section accounts for at least 5% of the total number of grains observed in the transverse cross section. 1. A metallic ribbon for power module packaging , wherein:the metallic ribbon has a rectangular, oval or oblong cross section;a composition of the metallic ribbon is a silver-palladium alloy comprising 0.2 to 6 wt % palladium;the metallic ribbon has a thickness of 10 μm to 500 μm;a width of the metallic ribbon is 2 to 100 times the thickness;the metallic ribbon comprises a plurality of grains, an average grain size of grains observed in a transverse cross section of the metallic ribbon is 2 μm to 10 μm; andthe metallic ribbon has a plurality of twin grains observed in the transverse cross section of the metallic ribbon, and a number of the twin grains observed in the transverse cross section accounts for at least 5% of a total number of the grains observed in the transverse cross section.2. The metallic ribbon for power module packaging of claim 1 , wherein a hardness of the metallic ribbon is 40 Hv to 70 Hv.3. The metallic ribbon for power module packaging of claim 1 , wherein the width of the metallic ribbon is not greater than 5 mm.4. The metallic ribbon for power module packaging of claim 1 , wherein a surface of the metallic ribbon is covered by one or more metal layers claim 1 , wherein a composition of the one or more ...

INTERCONNECTION STRUCTURE OF A SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE INCLUDING THE INTERCONNECTION STRUCTURE

An interconnection structure of a semiconductor chip may include an interconnection via, a lower pad, a conductive bump, and an upper pad. The interconnection via may be arranged in the semiconductor chip. The lower pad may be arranged on a lower end of the interconnection via exposed through a lower surface of the semiconductor chip. The conductive bump may be arranged on the lower pad. The upper pad may be arranged on an upper end of the interconnection via exposed through an upper surface of the semiconductor chip. The upper pad may have a width wider than a width of the interconnection via and narrower than a width of the lower pad. Thus, an electrical short between the conductive bumps may not be generated in the interconnection structure having a thin thickness. 1. An interconnection structure of a semiconductor chip , the interconnection structure comprising:an interconnection via arranged in the semiconductor chip;a lower pad arranged on a lower end of the interconnection via exposed through a lower surface of the semiconductor chip;a conductive bump arranged on the lower pad; andan upper pad including a body pad arranged on an upper end of the interconnection via exposed through an upper surface of the semiconductor chip, and an interconnection pad arranged on an upper surface of the body pad,wherein the body pad has a width substantially the same as a width of the lower pad, and the interconnection pad has a width wider than a width of the interconnection via and narrower than the width of the lower pad.2. The interconnection structure of claim 1 , wherein the interconnection pad is positioned on a central portion of the upper surface of the body pad.3. The interconnection structure of claim 1 , wherein the interconnection pad is arranged on an upper surface and a side surface of the body pad.4. The interconnection structure of claim 1 , wherein the width of the lower pad is about 15 μm to about 20 μm claim 1 , the width of the interconnection via is about ...

SEMICONDUCTOR PACKAGE

A semiconductor package includes a semiconductor substrate and an electrode pad formed on the semiconductor substrate. The electrode pad includes a central portion and a peripheral portion, and a first pattern is located on the peripheral portion. A passivation layer is formed on the semiconductor substrate and the electrode pad. The passivation layer has an opening exposing the central portion of the electrode pad and a second pattern located on the first pattern. A seed layer is formed on the electrode pad and the passivation layer. The seed layer has a third pattern formed on the second pattern. A bump is formed on the seed layer and electrically connected to the electrode pad. An undercut is formed around the third pattern located under an edge of a lower portion of the bump. 1. A semiconductor package comprising:a semiconductor substrate;an electrode pad on the semiconductor substrate and including a central portion and a peripheral portion, wherein a first pattern is located on the peripheral portion;a passivation layer on the semiconductor substrate and the electrode pad, the passivation layer having an opening exposing the central portion of the electrode pad and a second pattern located on the first pattern;a seed layer on the electrode pad and the passivation layer and having a third pattern on the second pattern; anda bump on the seed layer and electrically connected to the electrode pad,wherein an undercut is formed in the third pattern located under an edge of a lower portion of the bump.2. The semiconductor package of claim 1 , wherein the bump comprises a pillar layer being in contact with the seed layer and a solder layer on the pillar layer.3. The semiconductor package of claim 2 , wherein a top surface of the pillar layer is a flat surface claim 2 , anda bottom surface of the pillar layer is a curved surface corresponding to the third pattern.4. The semiconductor package of claim 2 , wherein a distance from a center of the pillar layer to a side ...

WAFER-LEVEL PACKAGE INCLUDING UNDER BUMP METAL LAYER

A semiconductor package includes a semiconductor chip comprising a first surface and a second surface, a redistribution layer on the first surface of the semiconductor chip, an under bump metal (UBM) layer on the redistribution layer, and a solder bump on the UBM layer, and the solder bump covers both outer side surfaces of the UBM layer. 1. A wafer-level semiconductor package comprising:a semiconductor chip including a first surface and a second surface, and including a connection pad on the first surface;a first passivation layer covering the first surface of the semiconductor chip, the first passivation layer including a first trench exposing the connection pad;a redistribution layer in the first trench and on the first passivation layer;a second passivation layer on the redistribution layer, and the second passivation layer includes a second trench exposing the redistribution layer;a UBM layer in the second trench and on the second passivation and in contact with the redistribution layer, and the thickness of the UBM layer is approximately 25 to 35 μm; anda solder bump on the UBM layer and covering an outer surface of the UBM layer, and a thickness of the solder bump is approximately 210 to 220 μm.2. The wafer-level semiconductor package of claim 1 , wherein the solder bump includes Au.3. The wafer-level semiconductor package of claim 1 , wherein the solder bump further comprises a contact surface in contact with the second passivation layer.4. The wafer-level semiconductor package of claim 1 , wherein an width of a portion of the solder bump covering the outer surface of the UBM layer gradually increases from the second passivation layer to the bottom surface of the UBM layer.5. The wafer-level semiconductor package of claim 1 , wherein the UBM layer comprises a first UBM layer in contact with the redistribution layer and a second UBM layer disposed on the first UBM layer.6. The wafer-level semiconductor package of claim 1 , wherein the wafer-level ...

SEMICONDUCTOR DEVICE

A semiconductor device includes an insulating layer, a barrier electrode layer formed on the insulating layer, a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer, and an outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer. 1. A semiconductor comprising:an insulating layer;a barrier electrode layer formed on the insulating layer;a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer; andan outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer.2. The semiconductor device according to claim 1 , wherein the outer-surface insulating film is in contact with the principal surface of the barrier electrode layer at a position with an interval from a peripheral edge of the barrier electrode layer toward an inward side of the barrier electrode layer.3. The semiconductor device according to claim 1 , wherein the Cu electrode layer includes a first surface and a second surface that is positioned on a side opposite to the first surface and that is connected to the barrier electrode layer claim 1 , anda peripheral edge of the second surface of the Cu electrode layer is formed at a position with an interval from the peripheral edge of the barrier electrode layer toward the inward side of the barrier electrode layer.4. The semiconductor device according to claim 1 , wherein the Cu electrode layer includes a first surface and a second surface that is positioned on a side opposite to the first surface and that is connected to the barrier electrode layer claim 1 , andthe second surface of the Cu electrode layer is formed narrower than ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Properties of a semiconductor device are improved. A semiconductor device is configured so as to have a protective film provided over an interconnection and having an opening, and a plating film provided in the opening. A slit is provided in a side face of the opening, and the plating film is also disposed in the slit. Thus, the slit is provided in the side face of the opening, and the plating film is also grown in the slit. This results in a long penetration path of a plating solution during subsequent formation of the plating film. Hence, a corroded portion is less likely to be formed in the interconnection (pad region). Even if the corroded portion is formed, a portion of the slit is corroded prior to the interconnection (pad region) at a sacrifice, making it possible to suppress expansion of the corroded portion into the interconnection (pad region). 1. A semiconductor device , comprising:a first insulating film provided above a semiconductor substrate;a first interconnection provided over the first insulating film;a second insulating film provided over the first interconnection and having a first opening;a plating film provided in the first opening; anda slit provided in a side face of the first opening,wherein a bottom of the first opening is a pad region being part of the first interconnection, andwherein the plating film is also provided in the slit.2. The semiconductor device according to claim 1 ,wherein the first interconnection contains aluminum (Al), andwherein the plating film contains a metal selected from nickel (Ni), gold (Au), and palladium (Pd).3. The semiconductor device according to claim 2 ,wherein the first interconnection contains aluminum (Al), andwherein the plating film includes a first plating film containing nickel (Ni), and a second plating film provided on the first plating film and containing gold (Au).4. The semiconductor device according to claim 3 , further comprising a third plating film containing palladium (Pd) between the first ...

Integrated Circuit Packages and Methods for Forming the Same

A method includes forming an electrical connector over a substrate of a wafer, and molding a polymer layer, with at least a portion of the electrical connector molded in the polymer layer. A first sawing step is performed to form a trench in the polymer layer. After the first sawing step, a second sawing step is performed to saw the wafer into a plurality of dies. 1. A method comprising:forming a solder region on a wafer, wherein the wafer comprises a plurality of chips, with the solder region being in a first chip of the plurality of chips;forming a dielectric layer to embed a portion of the solder region in the dielectric layer, wherein the dielectric layer comprises a first portion and a second portion;thinning the first portion of the dielectric layer without thinning the second portion of the dielectric layer; andsawing the wafer to separate the plurality of chips from each other, wherein the sawing comprises using a feature underlying the thinned first portion of the dielectric layer for alignment.2. The method of claim 1 , wherein the thinning results in a trench to be formed in the dielectric layer claim 1 , wherein the trench extends into the first chip.3. The method of claim 2 , wherein the trench further extends into a scribe line claim 2 , with the scribe line separating the first chip and a second chip from each other.4. The method of claim 1 , wherein after the thinning claim 1 , a remaining portion of the first portion of the dielectric layer is left claim 1 , and has a thickness allowing the feature directly underlying the remaining portion to be visible through the remaining portion.5. The method of claim 1 , wherein before the thinning claim 1 , the first portion of the dielectric layer is thick enough to prevent the feature from being visible through the first portion of the dielectric layer.6. The method of claim 1 , wherein the dielectric layer comprises a molding compound.7. The method of claim 1 , wherein the thinning is performed using a ...

Manufacturing method of wafer level chip scale package structure

A manufacturing method of wafer level chip scale package structure is provided. Firstly, a wafer including a plurality of semiconductor devices is provided. An active surface of one of the semiconductor devices has an active an active region and an outer region. A first electrode and a second electrode are arranged on the active region, and the outer region has a cutting portion and a channel portion. Next, a patterned protecting layer having a plurality of openings is formed on the active surface to respectively expose the first and second electrodes and channel portion. Subsequently, a wafer back thinning process is performed and then a back electrode layer is deposited. Subsequently, the channel portion is etched to form a trench exposing the back electrode layer, and a conductive structure connected to the back electrode layer is formed through the trench. Thereafter, the wafer is cut along the cutting portion.

Semiconductor structure

The invention provides a semiconductor structure. The semiconductor structure includes a substrate. A first passivation layer is disposed on the substrate. A conductive pad is disposed on the first passivation layer. A second passivation layer is disposed on the first passivation layer. A passive device is disposed on the conductive pad, passing through the second passivation layer. An organic solderability preservative film covers the passive device.

CHIP PARTS AND METHOD FOR MANUFACTURING THE SAME, CIRCUIT ASSEMBLY HAVING THE CHIP PARTS AND ELECTRONIC DEVICE

A chip part according to the present invention includes a substrate having a penetrating hole, a pair of electrodes formed on a front surface of the substrate and including one electrode overlapping the penetrating hole in a plan view and another electrode facing the one electrode, and an element formed on the front surface side of the substrate and electrically connected to the pair of electrodes. 1. A bidirectional Zener diode chip , comprising:a semiconductor substrate of a first conductivity type;a first diffusion region of a second conductivity type formed on the semiconductor substrate and exposed at a front surface of the semiconductor substrate;a second diffusion region of the second conductivity type formed on the semiconductor substrate across an interval from the first diffusion region and exposed at the front surface of the semiconductor substrate;a first electrode formed on the front surface of the semiconductor substrate and connected to the first diffusion region; anda second electrode formed on the front surface of the semiconductor substrate and connected to the second diffusion region, wherein,{'sup': '2', 'in a plan view of the semiconductor substrate from a normal direction, respective areas of the first diffusion region and the second diffusion region are not more than 2500 μmrespectively.'}2. The bidirectional Zener diode chip according to claim 1 , wherein the respective areas of the first diffusion region and the second diffusion region are not more than 2000 μmrespectively and the respective peripheral lengths of the first diffusion region and the second diffusion region are not less than 470 μm respectively.3. The bidirectional Zener diode chip according to claim 1 , wherein the ESD resistance is not less than 12 kV.4. The bidirectional Zener diode chip according to claim 1 , wherein the first diffusion region and the second diffusion region have mutually equal areas.5. The bidirectional Zener diode chip according to claim 1 , wherein the ...

SEMICONDUCTOR COPPER METALLIZATION STRUCTURE AND RELATED METHODS

Implementations of semiconductor packages may include: a silicon die including a pad, the pad including aluminum and copper; a passivation layer over at least a portion of the silicon die and a layer of one of a polyimide (PI) a polybenzoxazole (PBO), or a polymer resin coupled to the passivation layer. The package may include a first copper layer coupled over the pad, the first copper layer being about 1 microns to about 20 microns thick; a second copper layer coupled over the first copper layer, the second copper layer may be about 5 microns to about 40 microns thick; where a width of the first copper layer above the pad may be wider than a width of the second copper layer above the pad. The first and second copper layers may be configured to bond with a heavy copper wire or solder with a copper clip. 1. A semiconductor package comprising:a die comprising a pad on a first side of the die, the pad comprising one of aluminum and copper (AlCu); aluminum, copper and silicon (AlCuSi); aluminum, copper, and tungsten (AlCuW); aluminum silicon (AlSi); or any combination thereof;a first copper layer coupled directly over and to the pad;a second copper layer coupled over the first copper layer; anda metal layer comprised on a second side of the die opposite the first side of the die, wherein an implanted doped layer is formed in the second side of the die.2. A semiconductor package of claim 1 , wherein a width of the first copper layer above the pad is wider than a width of the second copper layer above the pad.3. The semiconductor package of claim 1 , further comprising a metal coating forming one of a metal cap on a top of the second copper layer or a full metal coverage of the first and the second copper layers claim 1 , the metal coating applied through one of electroless plating or electrolytic plating.4. The semiconductor package of claim 3 , wherein the metal coating comprises one of nickel and gold (Ni/Au); nickel claim 3 , palladium claim 3 , and gold (Ni/Pd/Au); ...

SEMICONDUCTOR DEVICE

A semiconductor device of the present disclosure includes: a semiconductor substrate having a first main surface; a first aluminum electrode having a first surface facing the first main surface and a second surface opposite to the first surface, the first aluminum electrode being disposed on the semiconductor substrate; a passivation film that covers a peripheral edge of the second surface and that is provided with an opening from which a portion of the second surface is exposed; and a copper film. The second surface exposed from the opening is provided with a recess that is depressed toward the first surface. The copper film is disposed in the recess. 1. A semiconductor device comprising:a semiconductor substrate having a first main surface;a first aluminum electrode having a first surface facing the first main surface and a second surface opposite to the first surface, the first aluminum electrode being disposed on the semiconductor substrate;a passivation film that covers a peripheral edge of the second surface and that is provided with an opening from which a portion of the second surface is exposed; anda copper film, whereinthe second surface exposed from the opening is provided with a recess that is depressed toward the first surface, andthe copper film is disposed in the recess.2. The semiconductor device according to claim 1 , wherein the passivation film is a polyimide film.3. The semiconductor device according to claim 1 , wherein the semiconductor substrate is a silicon carbide semiconductor substrate.4. The semiconductor device according to claim 1 , further comprising:a second aluminum electrode disposed on the semiconductor substrate;a plurality of first bonding wires connected to the copper film; anda second bonding wire connected to the second aluminum electrode, whereineach of the first bonding wires is composed of copper or a copper alloy, andthe second bonding wire is composed of aluminum or an aluminum alloy.5. The semiconductor device according ...

PAD STRUCTURE FOR FRONT SIDE ILLUMINATED IMAGE SENSOR

The present disclosure relates to an integrated circuit having a bond pad with a relatively flat surface topography that mitigates damage to underlying layers. In some embodiments, the integrated circuit has a plurality of metal interconnect layers within a dielectric structure over a substrate. A passivation structure is arranged over the dielectric structure. The passivation structure has a recess with sidewalls connecting a horizontal surface of the passivation structure to an upper surface of the passivation structure. A bond pad is arranged within the recess and has a lower surface overlying the horizontal surface. One or more protrusions extend outward from the lower surface through openings in the passivation structure to contact one of the metal interconnect layers. Arranging the bond pad within the recess and over the passivation structure mitigates stress to underlying layers during bonding without negatively impacting an efficiency of an image sensing element within the substrate. 1. An integrated circuit , comprising:a plurality of metal interconnect layers arranged within a dielectric structure over a semiconductor substrate;a passivation structure arranged over the dielectric structure and having a recess within an upper surface of the passivation structure, wherein the recess comprises sidewalls connecting a horizontal surface of the passivation structure to the upper surface; anda bond pad arranged within the recess and having a lower surface that overlies the horizontal surface, wherein the bond pad comprises one or more protrusions extending outward from the lower surface of the bond pad through openings in the passivation structure to contact one of the plurality of metal interconnect layers.2. The integrated circuit of claim 1 , further comprising:a second recess arranged within a top surface of the dielectric structure and having sidewalls contacting a horizontal surface of the dielectric structure to the top surface, wherein the passivation ...

DUAL BOND PAD STRUCTURE FOR PHOTONICS

A dual bond pad structure for a wafer with laser die attachment and methods of manufacture are disclosed. The method includes forming a bonding layer on a surface of a substrate. The method further includes forming solder bumps on the bonding layer. The method further includes patterning the bonding layer to form bonding pads some of which comprise the solder bumps thereon. The method further includes attaching a laser diode to selected bonding pads using solder connections formed on the laser diode. The method further includes attaching an interposer substrate to the solder bumps formed on the bonding pads. 1. A method , comprising:forming a bonding layer on a surface of a substrate;forming solder bumps on the bonding layer;forming a masking layer over the bonding layer;patterning the bonding layer to form bonding pads some of which comprise the solder bumps thereon;attaching a laser diode to selected bonding pads using solder connections formed on the laser diode; andattaching an interposer substrate to the solder bumps formed on the bonding pads.2. The method of claim 1 , wherein the masking layer is formed over portions of the bonding layer which are to be attached to the laser diode.3. The method of claim 1 , wherein the solder bumps are formed through a resist pattern claim 1 , after the forming of the masking layer over the bonding layer.4. The method of claim 1 , wherein the patterning of the bonding layer is performed after the forming of the solder bumps claim 1 , such that the solder bumps and the masking layer protect underlying portions of the bonding layer during an etching process.5. The method of claim 1 , further comprising removing the masking layer and attaching the solder connections formed on the laser diode directly to the bonding pads which are formed underneath the masking layer prior to removal.6. The method of claim 1 , wherein the interposer substrate is attached to the solder bumps through a reflow process.7. The method of claim 1 , ...

Conductive External Connector Structure and Method of Forming

External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure. 1. A method of manufacturing a semiconductor device , the method comprising:immersing a conductive contact into a first plating solution, the first plating solution having a positive first level of agitation;immersing the conductive contact into a second plating solution different from the first plating solution, the second plating solution having a second level of agitation; andimmersing the conductive contact into a third plating solution different from the second plating solution, the third plating solution having a third level of agitation greater than either the first level of agitation or the second level of agitation.2. The method of claim 1 , wherein the first plating solution plates copper onto the conductive contact.3. The method of claim 2 , wherein the second plating solution plates a barrier layer onto the copper.4. The method of claim 3 , wherein the third plating solution plates solder onto the barrier layer.5. The method of claim 1 , wherein the first level of agitation comprises a first positive level of reciprocation of a first paddle and the third level of agitation comprises a second positive level of reciprocation of the first paddle.6. The method of claim 1 , wherein the first level of agitation is ...

Ball Amount Process in the Manufacturing of Integrated Circuit

An integrated circuit structure includes a semiconductor substrate, a metal pad over the semiconductor substrate, a passivation layer including a portion over the metal pad, a polymer layer over the passivation layer, and a Post-Passivation Interconnect (PPI) over the polymer layer. The PPI is electrically connected to the metal pad. The PPI includes a PPI line have a first width, and a PPI pad having a second width greater than the first width. The PPI pad is connected to the PPI line. The PPI pad includes an inner portion having a first thickness, and an edge portion having a second thickness smaller than the first thickness.

Semiconductor element and production method thereof

In a semiconductor element of the present invention, an electroless nickel-phosphorus plating layer and an electroless gold plating layer are formed on both a front-side electrode and a back-side electrode of a front-back conduction-type substrate. The front-side electrode and the back-side electrode are formed of aluminum or an aluminum alloy. The proportion of the thickness of the electroless nickel-phosphorus plating layer formed on the front-side electrode with respect to the thickness of the electroless nickel-phosphorus plating layer formed on the back-side electrode is in a range of 1.0 to 3.5. The semiconductor element of the present invention allows the occurrence of voids inside solder during mounting by soldering to be prevented.

FRONT-TO-BACK BONDING WITH THROUGH-SUBSTRATE VIA (TSV)

Methods for forming a semiconductor device structure are provided. The method includes bonding a first wafer and a second wafer, and a first transistor is formed in a front-side of the first semiconductor wafer. The method further includes thinning a front-side of the second wafer and forming a second transistor in the front-side of the second wafer. 1. A method for forming a semiconductor device structure , comprising:bonding a first wafer and a second wafer, wherein a first transistor is formed in a front-side of the first wafer;thinning a front-side of the second wafer; andforming a second transistor in the front-side of the second wafer.2. The method as claimed in claim 1 , further comprising:forming at least one first TSV in the second wafer, wherein the first TSV directly contacts a conductive feature of the first wafer; andforming at least one second TSV in the first wafer and the second wafer to directly contact a redistribution (RDL) structure formed over a backside of the first wafer.3. The method as claimed in claim 2 , further comprising:thinning a backside of the first wafer to expose the second TSV.4. The method as claimed in claim 2 , wherein the second TSV has a second height greater than a first height of the first TSV.5. The method as claimed in claim 2 , further comprising:forming a contact plug over the first transistor, wherein a top surface of the contact plug is level with a top surface of the first TSV.6. The method as claimed in claim 1 , further comprising:forming an interconnect structure over the front-side of the second wafer, wherein the interconnect structure is electrically connected to the conductive feature of the first wafer.7. The method as claimed in claim 1 , wherein the step of bonding the first wafer and the second wafer is performed by using a first bonding layer and a second bonding layer claim 1 , and the first bonding layer and the second bonding layer made of silicon oxide claim 1 , silicon oxynitride or silane oxide.8. ...

Forming Metal Bonds with Recesses

A method includes forming a first device die, which includes depositing a first dielectric layer, and forming a first metal pad in the first dielectric layer. The first metal pad includes a recess. The method further includes forming a second device die including a second dielectric layer and a second metal pad in the second dielectric layer. The first device die is bonded to the second device die, with the first dielectric layer being bonded to the second dielectric layer, and the first metal pad being bonded to the second metal pad. 1. A method comprising: depositing a first dielectric layer; and', 'forming a first metal pad in the first dielectric layer, wherein the first metal pad comprises a first recess adjacent to an edge portion of the first metal pad;, 'forming a first device die comprising a second dielectric layer; and', 'a second metal pad in the second dielectric layer; and, 'forming a second device die comprisingbonding the first device die to the second device die, wherein the first dielectric layer is bonded to the second dielectric layer, and the first metal pad is bonded to the second metal pad.2. The method of claim 1 , wherein the first metal pad comprises:a diffusion barrier; anda copper-containing material between opposite portions of the diffusion barrier, wherein an edge portion of the copper-containing material is recessed lower than a top edge of the diffusion barrier to form the first recess.3. The method of claim 1 , wherein the bonding comprises:performing a pre-anneal; andperforming an anneal, wherein during the anneal, the first recess is reduced.4. The method of claim 1 , wherein the forming the first metal pad comprises performing a planarization claim 1 , wherein the first recess is generated by the planarization.5. The method of claim 4 , wherein the planarization comprises a Chemical Mechanical Polish (CMP) performed using a slurry having a pH value lower than about 4.0.6. The method of claim 4 , wherein the planarization ...

Semiconductor device

A semiconductor substrate ( 1 ) has a front surface and a back surface that are opposite each other. A first metal layer ( 2 ) is formed on the front surface of the semiconductor substrate ( 1 ). A second metal layer ( 3 ) for soldering is formed on the first metal layer ( 2 ). A third metal layer ( 5 ) is formed on the back surface of the semiconductor substrate ( 1 ). A fourth metal layer ( 6 ) for soldering is formed on the third metal layer ( 5 ). The second metal layer ( 3 ) has a larger thickness than that of the fourth metal layer ( 6 ). The first, third, and fourth metal layers ( 2, 5, 6 ) are not divided in a pattern. The second metal layer ( 3 ) is divided in a pattern and has a plurality of metal layers electrically connected to each other via the first metal layer ( 2 ).

SEMICONDUCTOR PACKAGE

A semiconductor package includes a substrate, through-electrodes penetrating the substrate, first bumps spaced apart from each other in a first direction parallel to a top surface of the substrate and electrically connected to the through-electrodes, respectively, and at least one second bump disposed between the first bumps and electrically insulated from the through-electrodes. The first bumps and the at least one second bump constitute one row in the first direction. A level of a bottom surface of the at least one second bump from the top surface of the substrate is a substantially same as levels of bottom surfaces of the first bumps from the top surface of the substrate. 120-. (canceled)21. A semiconductor package , comprising:a substrate;through-electrodes penetrating the substrate;first bumps spaced apart from each other in a first direction parallel to a top surface of the substrate, the first bumps being electrically connected to the through-electrodes, respectively;at least one second bump disposed between the first bumps, the at least one second bump being electrically insulated from the through-electrodes; andan underfill covering the substrate, the first bumps, and the at least one second bump,wherein the first bumps and the at least one second bump constitute one row in the first direction, andwherein at least one second bump is disposed at a higher level from the substrate than the first bumps.22. The semiconductor package as claimed in claim 21 , further comprising:an insulating pattern disposed between the substrate and the at least one second bump.23. The semiconductor package as claimed in claim 22 , wherein the insulating pattern has through-holes overlapping top surfaces of the through-electrodes claim 22 , respectively claim 22 , andwherein the first bumps are provided in the through-holes so as to be electrically connected to the through-electrodes, respectively.24. The semiconductor package as claimed in claim 21 , further comprising:a pad ...

CHIP STRUCTURE HAVING BONDING WIRE

A chip structure includes a chip, a first metal layer, a second metal layer and a bonding wire. The first metal layer is disposed on the chip, and a material of the first metal layer includes nickel or nickel alloy. The second metal layer is disposed on the first metal layer, and a material of the second metal layer includes copper, copper alloy, aluminum, aluminum alloy, palladium or palladium alloy. The bonding wire is connected to the second metal layer, and a material of the bonding wire includes copper or copper alloy. 1. A chip structure , comprising:a chip;a first metal layer, disposed on the chip, a material of the first metal layer comprising nickel or nickel alloy;a second metal layer, disposed on the first metal layer, a material of the second metal layer comprising copper or copper alloy; anda wedge bonding wire, wedge bonded to the second metal layer, a material of the wedge bonding wire comprising copper or copper alloy.2. The chip structure as recited in claim 1 , wherein a wire diameter of the wedge bonding wire is greater than 102 μm.3. (canceled)4. The chip structure as recited in claim 1 , further comprises a bonding pad disposed between the chip and the first metal layer claim 1 , and a material of the bonding pad comprises aluminum claim 1 , aluminum alloy claim 1 , copper or copper alloy.5. The chip structure as recited in claim 1 , wherein the chip is a power semiconductor.6. A chip structure claim 1 , comprising:a chip;a first metal layer, disposed on the chip, a material of the first metal layer comprising nickel or nickel alloy;a second metal layer, disposed on the first metal layer, a material of the second metal layer comprising aluminum or aluminum alloy; anda wedge bonding wire, wedge bonded to the second metal layer, a material of the wedge bonding wire comprising copper or copper alloy.7. The chip structure as recited in claim 6 , wherein a wire diameter of the wedge bonding wire is greater than 102 μm.8. (canceled)9. The chip ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE

A method of manufacturing a semiconductor device includes forming a barrier metal film on a surface of at least one of a first electrode of a wiring board and a second electrode of a semiconductor element, providing a connection terminal between the first and second electrodes, the connection terminal being made of solder containing tin, bismuth and zinc, and bonding the connection terminal to the barrier metal film by heating the connection terminal and maintaining the temperature of the connection terminal at a constant temperature not lower than a melting point of the solder for a certain period of time. 1. A semiconductor device comprising:a wiring board including a first electrode;a semiconductor element including a second electrode;a barrier metal film provided on a surface of any one of the first electrode and the second electrode; anda connection terminal provided between the first and second electrodes, bonded to the barrier metal film, and made of solder containing tin, bismuth and zinc, whereinan alloy layer made of a material of the barrier metal film and the zinc is formed between the barrier metal film and the connection terminal.2. The semiconductor device according to claim 1 , wherein the barrier metal film is a metal layer containing a nickel film.3. The semiconductor device according to claim 2 , wherein the metal layer is a laminated film obtained by laminating the nickel film and a gold film in this order.4. The semiconductor device according to claim 1 , wherein major components of the solder are the tin and the bismuth.5. The semiconductor device according to claim 1 , wherein the concentration of the zinc in the solder is not less than 0.1 wt % and not more than 1 wt %. This application is a divisional of application Ser. No. 14/063,866, filed Oct. 25, 2013, which is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2013-013433, filed on Jan. 28, 2013, the entire contents of which are incorporated ...

Stacked device and method of manufacturing the same

A stacked device encompasses a lower chip including a plurality of wiring lands and a plurality of wall-block patterns, each of the wall-block patterns is allocated at a position except locations where the wiring lands are disposed, each of the wall-block patterns has a inclined plane, a height of each of the wall-block patterns measured from a reference plane of the array of the wiring lands is higher than the wiring lands, and an upper chip including a plurality of wiring bumps assigned correspondingly to the positions of the wiring lands, respectively, and a plurality of cone bumps assigned correspondingly to the positions of the wall-block patterns, respectively.

Ball Amount Process in the Manufacturing of Integrated Circuit

An integrated circuit structure includes a semiconductor substrate, a metal pad over the semiconductor substrate, a passivation layer including a portion over the metal pad, a polymer layer over the passivation layer, and a Post-Passivation Interconnect (PPI) over the polymer layer. The PPI is electrically connected to the metal pad. The PPI includes a PPI line have a first width, and a PPI pad having a second width greater than the first width. The PPI pad is connected to the PPI line. The PPI pad includes an inner portion having a first thickness, and an edge portion having a second thickness smaller than the first thickness.

SEMICONDUCTOR COPPER METALLIZATION STRUCTURE AND RELATED METHODS

Implementations of semiconductor packages may include: a silicon die including a pad, the pad including aluminum and copper; a passivation layer over at least a portion of the silicon die and a layer of one of a polyimide (PI) a polybenzoxazole (PBO), or a polymer resin coupled to the passivation layer. The package may include a first copper layer coupled over the pad, the first copper layer being about 1 microns to about 20 microns thick; a second copper layer coupled over the first copper layer, the second copper layer may be about 5 microns to about 40 microns thick; where a width of the first copper layer above the pad may be wider than a width of the second copper layer above the pad. The first and second copper layers may be configured to bond with a heavy copper wire or solder with a copper clip. 1. A method for making a semiconductor package , the method comprising:providing a die comprising a pad on a first side of the die, the pad comprising one of aluminum and copper (AlCu); aluminum, copper and silicon (AlCuSi); aluminum, copper, and tungsten (AlCuW); aluminum silicon (AlSi); and any combination thereof;applying a passivation layer over at least a portion of the first side of the die;applying and patterning one of a polyimide (PI) layer and a polybenzoxazole layer (PBO) over the passivation layer;applying a seed layer to the pad;patterning a first photoresist layer over the seed layer;electroplating a first copper layer directly over and to the seed layer, the first copper layer having a thickness of between 1 microns and 20 microns;patterning a second photoresist layer over the first copper layer;electroplating a second copper layer over the first copper layer, the second copper layer having a thickness of between 5 microns and 40 microns;removing the first photoresist layer;removing the second photoresist layer;stripping the seed layer;wherein a width of the first copper layer is wider that a width of the second copper layer; andwherein the second ...

Conductive External Connector Structure and Method of Forming

External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure.

SEMICONDUCTOR PACKAGE

A semiconductor package includes a substrate, through-electrodes penetrating the substrate, first bumps spaced apart from each other in a first direction parallel to a top surface of the substrate and electrically connected to the through-electrodes, respectively, and at least one second bump disposed between the first bumps and electrically insulated from the through-electrodes. The first bumps and the at least one second bump constitute one row in the first direction. A level of a bottom surface of the at least one second bump from the top surface of the substrate is a substantially same as levels of bottom surfaces of the first bumps from the top surface of the substrate. 120.-. (canceled)21. A semiconductor package comprising:a substrate;a first chip on the substrate, the first chip has first through-electrodes penetrating the first chip;a second chip on the first chip;bumps between the first chip and the second chip; andan underfill filling a space between the first chip and the second chip, first bumps spaced apart from each other in a first direction parallel to a top surface of the first chip, the first bumps being electrically connected to the through-electrodes, respectively, and', 'at least one second bump between the first bumps, the at least one second bump being electrically insulated from the through-electrodes,, 'wherein the bumps includewherein the first bumps and the at least one second bump constitute one row in the first direction,wherein a level of a bottom surface of the at least one second bump from the top surface of the substrate is a substantially same level as levels of bottom surfaces of the first bumps from the top surface of the substrate, andwherein the underfill covers a space between the first bumps and covers a space between the first bumps and the at least one second bump.22. The semiconductor package as claimed in claim 21 , wherein:the first bumps have a first thickness in a second direction perpendicular to the top surface of ...

WAFER-LEVEL PACKAGE INCLUDING UNDER BUMP METAL LAYER

A semiconductor package includes a semiconductor chip comprising a first surface and a second surface, a redistribution layer on the first surface of the semiconductor chip, an under bump metal (UBM) layer on the redistribution layer, and a solder bump on the UBM layer, and the solder bump covers both outer side surfaces of the UBM layer. 1. A wafer-level semiconductor package comprising:a semiconductor chip comprising a first surface and a second surface;a redistribution layer on the first surface of the semiconductor chip;an under bump metal (UBM) layer on the redistribution layer; anda solder bump on the UBM layer,wherein the solder bump covers both outer side surfaces of the UBM layer.2. The wafer-level semiconductor package of claim 1 , wherein a thickness of the UBM layer is in a range of 10% to 50% of a thickness of the solder bump.3. The wafer-level semiconductor package of claim 1 , further comprising:a first passivation layer on the first surface of the semiconductor chip; anda second passivation layer on the first passivation layer and covering at least a portion of the UBM layer,wherein the solder bump further comprises a contact surface in contact with a bottom surface of the second passivation layer.4. The wafer-level semiconductor package of claim 1 , wherein both of the outer side surfaces of the UBM layer are each inclined toward an inside of the solder bump.5. The wafer-level semiconductor package of claim 1 , wherein at least one of the outer side surfaces of the UBM layer comprises a curved side surface.6. The wafer-level semiconductor package of claim 1 , further comprising a mold layer that covers a sidewall of and exposes the first surface of the semiconductor chip.7. The wafer-level semiconductor package of claim 6 , wherein the mold layer has a thickness greater than a thickness of the semiconductor chip.8. The wafer-level semiconductor package of claim 6 , wherein the redistribution layer extends on the first surface and a bottom surface of ...

SEMICONDUCTOR DEVICE

A semiconductor chip includes a substrate, an electrode pad formed on the substrate, an insulating layer covering the substrate and the electrode pad, and having an opening exposing a portion of a surface of the electrode pad, a first conductive layer formed on the exposed portion of the surface of the electrode pad and extending to a surface of the insulating layer, and a second conductive layer formed on the first conductive layer, covering the first conductive layer in a plan view, and having an outer edge portion which is located further out than an outer edge of the first conductive layer in a plan view. The outer edge portion of the second conductive layer has at least one curved portion. At least one portion of the curved portion is located between the outer edge of the first conductive layer and an outer edge of the second conductive layer in a plan view. 1. A semiconductor chip , comprising:a substrate;an electrode pad formed on the substrate;an insulating layer covering the substrate and the electrode pad, and having an opening exposing a portion of a surface of the electrode pad therethrough;a first conductive layer formed on the exposed portion of the surface of the electrode pad and extending to a surface of the insulating layer; anda second conductive layer formed on the first conductive layer, covering the first conductive layer in a plan view, and having an outer edge portion which is located further out than an outer edge of the first conductive layer in a plan view,wherein the outer edge portion of the second conductive layer has at least one curved portion, andat least one portion of the curved portion is located between the outer edge of the first conductive layer and an outer edge of the second conductive layer in a plan view.2. The semiconductor chip according to claim 1 , further comprising a bump electrode formed on the second conductive layer and covering the curved portion.3. The semiconductor chip according to claim 2 , wherein at least ...

Semiconductor structure with ubm layer and method of fabricating the same

A semiconductor structure with an under bump metallization (UBM) layer is provided. The semiconductor structure at least includes a substrate, a metal pad disposed on the substrate, an insulating layer covering the substrate and an edge of the metal pad, wherein at least one recess is disposed within the insulating layer and a first UBM layer contacts the metal pad. The recess is adjacent to the metal pad and the recess is in the shape of a ring. The first UBM layer contacts part of the recess.

Semiconductor Arrangement with a Sealing Structure

A semiconductor arrangement includes a semiconductor body with a first surface, an inner region and an edge region, the edge region surrounding the inner region, an attachment layer spaced apart from the first surface of the semiconductor body in a first direction, an intermediate layer arranged between the first surface of the semiconductor body and the attachment layer, and at least one first type sealing structure. The sealing structure includes a first barrier, a second barrier, and a third barrier. The first barrier is arranged in the intermediate layer and spaced apart from the attachment layer in the first direction. The second barrier is arranged in the intermediate layer, is spaced apart from the first surface in the first direction, and is spaced apart from the first barrier in a second direction. The third barrier extends from the first barrier to the second barrier in the second direction. 1. A semiconductor arrangement , comprising:a semiconductor body with a first surface, an inner region and an edge region, the edge region surrounding the inner region;an attachment layer spaced apart from the first surface of the semiconductor body in a first direction;an intermediate layer arranged between the first surface of the semiconductor body and the attachment layer; and a first barrier arranged in the intermediate layer and spaced apart from the attachment layer in the first direction;', 'a second barrier arranged in the intermediate layer, the second barrier adjoining the attachment layer, being spaced apart from the first surface in the first direction and being spaced apart from the first barrier in a second direction; and', 'a third barrier extending from the first barrier to the second barrier in the second direction., 'at least one first type sealing structure, comprising2. The semiconductor arrangement of claim 1 , further comprising a fourth barrier arranged in a trench extending from the first surface into the semiconductor body claim 1 , wherein ...

Semiconductor devices including thick pad

A semiconductor device may include a semiconductor chip in an encapsulant. A first insulation layer may be disposed on the encapsulant and the semiconductor chip. A horizontal wiring and a primary pad may be disposed on the first insulation layer. A secondary pad may be disposed on the primary pad. A second insulation layer covering the horizontal wiring may be disposed on the first insulation layer. A solder ball may be disposed on the primary pad and the secondary pad. The primary pad may have substantially the same thickness as a thickness of the horizontal wiring.

Semiconductor product with interlocking metal-to-metal bonds and method for manufacturing thereof

A structure and method for performing metal-to-metal bonding in an electrical device. For example and without limitation, various aspects of this disclosure provide a structure and method that utilize an interlocking structure configured to enhance metal-to-metal bonding.

Semiconductor Chip and Method for Forming a Chip Pad

A semiconductor chip with different chip pads and a method for forming a semiconductor chip with different chip pads are disclosed. In some embodiments, a semiconductor chip includes a chip front side, a first chip pad located on the chip front side, a second chip pad located on the chip front side and an electrically insulating material located between the first chip pad and the second chip pad, wherein the first chip pad includes a surface layer predominantly comprising copper and the second chip pad includes a surface layer predominantly comprising aluminum. 1. A semiconductor chip comprising:a chip front side;a first chip pad located on the chip front side;a second chip pad located on the chip front side; andan electrically insulating material located between the first chip pad and the second chip pad,wherein the first chip pad comprises a surface layer predominantly comprising copper and the second chip pad comprises a surface layer predominantly comprising aluminum.2. The semiconductor chip of claim 1 , wherein the first chip pad further comprises a titanium tungsten barrier layer under the surface layer of the first chip pad.3. The semiconductor chip of claim 2 , wherein the titanium tungsten barrier layer has a tungsten content ranging from 60% to 90%.4. The semiconductor chip of claim 2 , wherein the titanium tungsten barrier layer has a tungsten content ranging from 70% to 85%.5. The semiconductor chip of claim 2 , wherein the titanium tungsten barrier layer has a composition of Ti0.2W0.8.6. The semiconductor chip of claim 1 , wherein the surface layer of the second chip pad consists essentially of aluminum.7. The semiconductor chip of claim 1 , wherein the surface layer of the first chip pad consists essentially of copper.8. The semiconductor chip of claim 1 , further comprising a soldering material in contact with the surface layer of the first chip pad.9. The semiconductor chip of claim 8 , further comprising a bond wire joined to the surface layer of ...

Integrated Circuit Structure Having Dies with Connectors

An embodiment is an integrated circuit structure including a first die having a bump structure, and a second die having a pad structure. The first die is attached to the second die by bonding the bump structure and the pad structure. The bump structure includes a metal pillar, a metal cap layer on the metal pillar, a metal insertion layer on the metal cap layer, and a solder layer on the metal insertion layer. The pad structure includes at least one of a nickel (Ni) layer, a palladium (Pd) layer or a gold (Au) layer.

Semiconductor module

A semiconductor module includes a first semiconductor chip including a first signal line and a first ground, a mounting board or a second semiconductor chip including a second signal line and a second ground, a signal line coupling bump that couples the first signal line and the second signal line with each other, a first ground coupling bump that couples the first ground and the second ground with each other, a signal line side insulating film including a capacitance that causes a series resonance with an inductance by the signal line coupling bump at a target frequency and a ground side insulating film including a capacitance that causes a series resonance with an inductance by the first ground coupling bump at a target frequency.

SEMICONDUCTOR DEVICE

A semiconductor device includes an insulating layer, a barrier electrode layer formed on the insulating layer, a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer, and an outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer. 1. A semiconductor device comprising:an insulating layer;a barrier electrode layer formed over a part of a region of a surface of the insulating layer;a bonding pad formed on a principal surface of the barrier electrode layer,wherein the bonding pad has three layers which include a Cu electrode layer that includes a metal composed mainly of copper, a nickel layer, and a surface metal layer, those layers are formed from bottom to top; andwherein a surface of the surface metal layer is fully exposed from the insulating layer for connecting a bonding wire on the surface, a thickness of the surface metal layer is thinner than a thickness of the nickel layer, and a thickness of the nickel layer is thinner than a thickness of the Cu electrode layer.2. The semiconductor device according to claim 1 , wherein a width of the surface metal layer is wider than a width of the Cu electrode layer in a sectional view.3. The semiconductor device according to claim 1 , wherein a curved portion is formed around a bottom of the Cu electrode layer to make an upper portion of the Cu electrode layer wider.4. The semiconductor device according to claim 3 , wherein an insulating material is intruding to the curved portion so that part of the Cu electrode layer is on the insulating material.5. The semiconductor device according to claim 1 , wherein a thickness of the insulating layer is thicker than a thickness of the barrier electrode layer.6. The semiconductor device according to claim 1 , wherein the Cu electrode layer and the insulating ...

INTERCONNECT STRUCTURES FOR PREVENTING SOLDER BRIDGING, AND ASSOCIATED SYSTEMS AND METHODS

Semiconductor dies having interconnect structures formed thereon, and associated systems and methods, are disclosed herein. In one embodiment, an interconnect structure includes a conductive material electrically coupled to an electrically conductive contact of a semiconductor die. The conductive material includes a first portion vertically aligned with the conductive contact, and a second portion that extends laterally away from the conductive contact. A solder material is disposed on the second portion of the interconnect structure such that the solder material is at least partially laterally offset from the conductive contact of the semiconductor die. In some embodiments, an interconnect structure can further include a containment layer that prevents wicking or other undesirable movement of the solder material during a reflow process. 1. A semiconductor die , comprising:a substrate having a center portion and an outer edge portion;an insulating material over a surface of the substrate;an electrically conductive contact at the surface of the substrate;an interconnect structure electrically coupled to the conductive contact, wherein the interconnect structure includes a top surface having a first portion and a second portion, wherein the first portion is vertically aligned with the conductive contact, and wherein the second portion extends (a) laterally away from the first portion in a direction away from the center portion and toward the outer edge portion of the substrate and (b) over at least a portion of the insulating material; anda solder material disposed at least partially on the second portion of the top surface.2. The semiconductor die of wherein the conductive contact is exposed at an opening in the insulating material.3. The semiconductor die of claim 1 , further comprising a containment layer over substantially all of the first portion of the top surface of the interconnect structure.4. The semiconductor die of wherein the containment layer is ...

SEMICONDUCTOR PACKAGE HAVING A METAL BARRIER

A semiconductor device having a barrier metal layer positioned over a metallization layer, and an under bump metallurgy layer over the barrier metal layer, and a solder bump over the under bump metallurgy layer. 120-. (canceled)21. A semiconductor device comprising:a metallization layer electrically connected to an integrated circuit;a passivation layer adjacent to the metallization layer;a barrier layer, composed of nickel, electrically connected to the metallization layer and contacting the passivation layer;a polyimide layer in contact with the passivation layer and in contact with portions of the barrier layer;a metal structure electrically connected to the barrier layer, the metal structure in contact with the polyimide layer; andsolder in contact with the metal structure.22. The semiconductor device of claim 21 , wherein an edge of the metal structure and an edge of the barrier layer align with each other in a cross-sectional view of the semiconductor device.23. The semiconductor device of claim 21 , further comprising:a first adhesion layer between portions of the metallization layer and the barrier layer; anda second adhesion layer between portions of the barrier layer and the metal structure.24. The semiconductor device of claim 23 , wherein an edge of the first adhesion layer and an edge of the second adhesion layer align with each other in a cross-sectional view of the semiconductor device.25. The semiconductor device of claim 23 , wherein the second adhesion layer contacts portions of the polyimide layer.26. The semiconductor device of claim 23 , wherein each of the first adhesion layer and the second adhesion layer is selected from a group consisting of TiW/Au claim 23 , TiW/Ni/Au claim 23 , TiW/Pd/Au claim 23 , and TiW/Cu/Ni/Au.27. The semiconductor device of claim 21 , wherein the metal structure is composed of a metal selected from a group consisting of copper and nickel.28. An integrated circuit package comprising:a metallization layer electrically ...

Package with Solder Regions Aligned to Recesses

A method includes forming a passivation layer over a portion of a metal pad, forming a polymer layer over the passivation layer, and exposing the polymer layer using a photolithography mask. The photolithography mask has an opaque portion, a transparent portion, and a partial transparent portion. The exposed polymer layer is developed to form an opening, wherein the metal pad is exposed through the opening. A Post-Passivation Interconnect (PPI) is formed over the polymer layer, wherein the PPI includes a portion extending into the opening to connect to the metal pad. 1. An integrated circuit structure comprising:a substrate;a dielectric layer over the substrate, wherein the dielectric layer comprises a top surface; a first portion over and contacting the top surface of the dielectric layer; and', 'a plurality of second portions extending from the top surface of the dielectric layer into the dielectric layer; and, 'a conductive pad comprisinga solder region overlying and contacting the conductive pad.2. The integrated circuit structure of claim 1 , wherein the first portion of the conductive pad encircles the second portions of the conductive pad.3. The integrated circuit structure of claim 1 , wherein the solder region overlaps the first portion and the plurality of second portions of the conductive pad.4. The integrated circuit structure of claim 1 , wherein the second portions of the conductive pad have substantially planar bottom surfaces and slanted sidewalls.5. The integrated circuit structure of claim 1 , wherein the solder region further overlaps a portion of the dielectric layer claim 1 , and the portion of the dielectric layer is between two of the plurality of second portions of the conductive pad.6. The integrated circuit structure of claim 1 , wherein the plurality of second portions of the conductive pad extend to an intermediate level of the dielectric layer claim 1 , with the intermediate level being between the top surface and a bottom surface of the ...

Semiconductor device having a bump structure and method for manufacturing the same

A method for manufacturing a semiconductor device includes an extra etching process. A bump or a UBM layer is etched additionally in the extra etching process after forming the semiconductor device such that the semiconductor device can conform to the standard of performance and appearance.

PACKAGED SEMICONDUCTOR DEVICE WITH ELECTROPLATED PILLARS

In a described example, a device includes an overcoat layer covering an interconnect; an opening in the overcoat layer exposing a portion of a surface of the interconnect; a stud on the exposed portion of the surface of the interconnect in the opening; a surface of the stud approximately coplanar with a surface of the overcoat layer; and a conductive pillar covering the stud and covering a portion of the overcoat layer surrounding the stud, the conductive pillar having a planar and un-dished surface facing away from the stud and the overcoat layer. 1. A device , comprising:an overcoat layer covering an interconnect;an opening in the overcoat layer exposing a portion of a surface of the interconnect;a stud on the exposed portion of the surface of the interconnect in the opening;a surface of the stud approximately coplanar with a surface of the overcoat layer; anda conductive pillar covering the stud and covering a portion of the overcoat layer surrounding the stud, the conductive pillar having a planar and un-dished surface facing away from the stud and the overcoat layer.2. The device of claim 1 , wherein the device is a semiconductor device.3. The device of claim 1 , wherein the device is a circuit board.4. The device of claim 1 , wherein the interconnect is one selected from a group consisting essentially of: aluminum claim 1 , tungsten claim 1 , titanium/tungsten claim 1 , copper and alloys thereof.5. The device of claim 1 , wherein the conductive pillar comprises copper.6. The device of claim 5 , wherein the conductive pillar comprises electroplated copper.7. The device of claim 1 , wherein the conductive pillar comprises an electroplated material that is one selected from a group consisting essentially of: silver claim 1 , gold claim 1 , nickel claim 1 , palladium claim 1 , and copper.8. The device of claim 1 , wherein the stud comprises copper.9. The device of claim 8 , wherein the stud comprises electroplated copper.10. The device of claim 8 , wherein the ...

Interconnect Structures and Methods of Forming Same

Embodiments of the present disclosure include interconnect structures and methods of forming interconnect structures. An embodiment is an interconnect structure including a post-passivation interconnect (PPI) over a first substrate and a conductive connector on the PPI. The interconnect structure further includes a molding compound on a top surface of the PPI and surrounding a portion of the conductive connector, a top surface of the molding compound adjoining the conductive connector at an angle from about 10 degrees to about 60 degrees relative to a plane parallel with a major surface of the first substrate, the conductive connector having a first width at the adjoining top surface of the molding compound, and a second substrate over the conductive connector, the second substrate being mounted to the conductive connector. 1. A method comprising:forming a contact pad on a top surface of a first substrate;depositing a first passivation layer on the top surface of the first substrate, the first passivation layer contacting a first portion of a top surface of the contact pad;depositing a second passivation layer on the first passivation layer, the second passivation layer contacting a second portion of the top surface of the contact pad;forming a post-passivation interconnect (PPI) extending along a top surface of the second passivation layer and extending through the second passivation layer to contact the top surface of the contact pad;forming a connector on the top surface of the PPI;forming a molding compound on the top surface of the PPI and around the connector, a topmost surface of the molding compound being below an upper portion of the connector;after the forming the molding compound, shaping the molding compound such that the molding compound covers a middle portion of the connector, the upper portion of the connector extending above the molding compound; andbonding a bond pad of a second substrate to the connector, the bond pad having a second width, the ...

Semiconductor device and method of fabricating the same

A semiconductor device includes a semiconductor substrate, a conductive pad disposed on the semiconductor substrate, and a pillar pattern disposed on the conductive pad. The semiconductor device further includes a solder seed pattern disposed on the pillar pattern, and a solder portion disposed on the pillar pattern and the solder seed pattern. A first width of the solder seed pattern is less than a second width of a top surface of the pillar pattern.

Chip parts and method for manufacturing the same, circuit assembly having the chip parts and electronic device

A chip part according to the present invention includes a substrate having a penetrating hole, a pair of electrodes formed on a front surface of the substrate and including one electrode overlapping the penetrating hole in a plan view and another electrode facing the one electrode, and an element formed on the front surface side of the substrate and electrically connected to the pair of electrodes.

SEMICONDUCTOR PACKAGE WITH RIGID UNDER BUMP METALLURGY (UBM) STACK

The invention provides a semiconductor package. The semiconductor package includes a semiconductor die and a conductive pillar bump structure and a conductive plug. The semiconductor die has a die pad thereon. The conductive pillar bump structure is positioned overlying the die pad. The conductive pillar bump structure includes an under bump metallurgy (UBM) stack having a first diameter and a conductive plug on the UBM stack. The conductive plug has a second diameter that is different than the first diameter. 1. A semiconductor package , comprising:a semiconductor die having a die pad thereon; and an under bump metallurgy (UBM) stack having a first diameter; and', 'a conductive plug on the UBM stack,', 'wherein the conductive plug has a second diameter that is different than the first diameter., 'a conductive pillar bump structure overlying the die pad, wherein the conductive pillar bump structure comprises2. The semiconductor package as claimed in claim 1 , wherein the first diameter and the second diameter are along a direction that is substantially parallel to a front-side surface of the semiconductor die.3. The semiconductor package as claimed in claim 1 , wherein the first diameter is greater than the second diameter.4. The semiconductor package as claimed in claim 1 , wherein an overlapping area between the conductive plug and a top surface of the UBM stack is less than an area of the top surface of the UBM stack.5. The semiconductor package as claimed in claim 1 , wherein the conductive plug is overlying a portion of the top surface of the UBM stack.6. The semiconductor package as claimed in claim 1 , wherein an interface between the conductive plug and the UBM stack is a planar surface.7. The semiconductor package as claimed in claim 1 , wherein the UBM stack comprises:a first metal layer in contact with the die pad of the semiconductor die; anda second metal pad overlying the first metal layer and in contact with the conductive plug.8. The semiconductor ...

RELIABLE PASSIVATION FOR INTEGRATED CIRCUITS

Device and method for forming a device are presented. A substrate having circuit component and a back-end-of-line (BEOL) dielectric layer with interconnects is provided. A pad dielectric layer is formed over the BEOL dielectric layer. The pad dielectric layer includes a pad via opening which exposes a surface of one of the interconnects in the BEOL dielectric layer. A pad interconnect is formed on the pad dielectric layer and the pad interconnect is coupled to one of the interconnect in the BEOL dielectric by a pad via contact in the pad via opening. The pad interconnect comprises a pad interconnect pattern which is devoid of 90° angles and any angled structures contained in the pad interconnect pattern less than 90°. A passivation layer is formed on the substrate. The passivation layer lines the pad interconnect and covers an exposed surface of the pad dielectric layer. 1. A method of forming a device comprising:providing a substrate prepared with circuit component and a back-end-of-line (BEOL) dielectric layer with interconnects;forming a pad dielectric layer over the BEOL dielectric layer, wherein the pad dielectric layer includes a pad via opening which exposes a surface of one of the interconnects in the BEOL dielectric layer;depositing a pad conductive layer on a surface of the substrate, wherein the pad conductive layer fills the pad via opening and covers the pad dielectric layer;patterning the pad conductive layer, wherein patterning forms a pad interconnect having a pad interconnect pattern which is devoid of 90° angles and any angled structure contained in the pad interconnect pattern less than 90°;forming a passivation layer on the substrate surface, the passivation layer lines the pad interconnect and covers a surface of the pad dielectric layer exposed by patterning the pad conductive layer to form the pad interconnect, wherein the interconnect pattern which is devoid of 90° angles increases the integrity of the passivation layer.2. The method of ...

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

A semiconductor structure includes a substrate; a conductive pad disposed over the substrate; a passivation disposed over the substrate and covering a portion of the conductive pad; a bump pad disposed over the conductive pad and the passivation; a conductive bump including a conductive pillar disposed over the bump pad and a soldering member disposed over the conductive pillar; and a dielectric member disposed over the passivation and surrounding the conductive pillar. 1. A semiconductor structure , comprising:a substrate;a conductive pad disposed over the substrate;a passivation disposed over the substrate and covering a portion of the conductive pad;a bump pad disposed over the conductive pad and the passivation;a conductive bump including a conductive pillar disposed over the bump pad and a soldering member disposed over the conductive pillar; anda dielectric member disposed over the passivation and surrounding the conductive pillar.2. The semiconductor structure of claim 1 , wherein the soldering member is exposed from the dielectric member.3. The semiconductor structure of claim 1 , wherein the dielectric member is in contact with the bump pad and the conductive pillar.4. The semiconductor structure of claim 1 , wherein a first interface is disposed between the dielectric member and the passivation.5. The semiconductor structure of claim 4 , wherein material of the dielectric member is different from material of the passivation.6. The semiconductor structure of claim 1 , wherein a second interface between the soldering member and the conductive pillar is substantially coplanar with an exposed surface of the dielectric member.7. The semiconductor structure of claim 6 , wherein a third interface between the conductive pillar and the dielectric member is substantially orthogonal to the second interface between the soldering member and the conductive pillar.8. The semiconductor structure of claim 1 , wherein the conductive pillar is enclosed by the bump pad claim ...

INTERCONNECT STRUCTURES WITH INTERMETALLIC PALLADIUM JOINTS AND ASSOCIATED SYSTEMS AND METHODS

Interconnect structures with intermetallic palladium joints are disclosed herein. In one embodiment, an interconnect structure includes a first conductive element, a second conductive element, and an intermetallic palladium joint. The intermetallic palladium joint includes an intermetallic crystallite spanning between the first and second conductive elements. The intermetallic crystallite includes a first end portion and a second end portion. The first end portion directly contacts the first conductive element. The second end portion directly contacts the second conductive element. 1. An interconnect structure , comprising:a first conductive element;a second conductive element; andan intermetallic palladium joint comprising an intermetallic crystallite spanning between the first and second conductive elements, the intermetallic crystallite comprising a first end portion and a second end portion, the first end portion directly contacting the first conductive element, the second end portion directly contacting the second conductive element.2. The interconnect structure of wherein the intermetallic palladium joint has a thickness between the first and second conductive elements.3. The interconnect structure of wherein the thickness of the intermetallic palladium joint is in a range between about 5 μm to 10 μm.4. The interconnect structure of claim 1 , further comprising a first barrier material on the first conductive element claim 1 , wherein the first barrier material bonds the first end portion to the first conductive element.5. The interconnect structure of claim 4 , further comprising a second barrier material on the second conductive element claim 4 , wherein the second barrier material bonds the second end portion to the second conductive element.6. The interconnect structure of wherein the first barrier material comprises nickel.7. The interconnect structure of wherein the second barrier material comprises nickel.8. The interconnect structure of wherein the ...

SEMICONDUCTOR DEVICE

A semiconductor device includes an insulating layer, a barrier electrode layer formed on the insulating layer, a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer, and an outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer. 1. A semiconductor device comprising:an insulating layer;a TiN layer formed over a part of a region of a surface of the insulating layer;a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the TiN layer; anda nickel layer formed on the Cu electrode layer,wherein a width of the nickel layer is wider than a width of the Cu electrode layer in a sectional view.2. The semiconductor device according to claim 1 , wherein a surface metal layer is formed on the nickel layer.3. The semiconductor device according to claim 2 , wherein a thickness of the surface metal layer is thinner than a thickness of the nickel layer.4. The semiconductor device according to claim 3 , wherein a width of the surface metal layer is wider than a width of the Cu electrode layer in a sectional view.5. The semiconductor device according to claim 4 , wherein a curved portion is formed around a bottom of the Cu electrode layer to make an upper portion of the Cu electrode layer wider.6. The semiconductor device according to claim 5 , wherein an insulating material is intruding to the curved portion so that part of the Cu electrode layer is on the insulating material.7. The semiconductor device according to claim 6 , wherein a thickness of the insulating layer is thicker than a thickness of the TiN layer.8. The semiconductor device according to claim 7 , wherein the Cu electrode layer and the insulating layer are connected by the TiN layer disposed between the Cu electrode layer and the ...

Interconnect Structures and Methods of Forming Same

Embodiments of the present disclosure include interconnect structures and methods of forming interconnect structures. An embodiment is an interconnect structure including a post-passivation interconnect (PPI) over a first substrate and a conductive connector on the PPI. The interconnect structure further includes a molding compound on a top surface of the PPI and surrounding a portion of the conductive connector, a top surface of the molding compound adjoining the conductive connector at an angle from about 10 degrees to about 60 degrees relative to a plane parallel with a major surface of the first substrate, the conductive connector having a first width at the adjoining top surface of the molding compound, and a second substrate over the conductive connector, the second substrate being mounted to the conductive connector. 18.-. (canceled)9. An interconnect structure comprising:a contact pad on a surface of a first substrate;a post-passivation interconnect (PPI) contacting a surface of the contact pad;a first passivation layer on a surface of the PPI;a connector on the surface of the PPI, the first passivation layer directly adjoining a lower portion of the connector;a molding compound disposed on a surface of the first passivation layer, the molding compound covering a middle portion of the connector and exposing another portion of the connector; anda bond pad on a surface of a second substrate, the bond pad being bonded to the connector.10. The interconnect structure of further comprising:a second passivation layer on the contact pad and the surface of the first substrate; anda third passivation layer on the second passivation layer and the contact pad, the PPI extending through the second passivation layer and the third passivation layer, the first passivation layer being disposed on the third passivation layer.11. The interconnect structure of claim 10 , wherein the molding compound has a concave top surface adjoining the connector claim 10 , the connector ...

Semiconductor device and method of manufacturing the same

A semiconductor device in which reliability of a bonding pad to which a conductive wire is bonded is achieved. A bonding pad having an OPM structure is formed of an Al—Cu alloy film having a Cu concentration of 2 wt % or more. By increasing the Cu concentration, the Al—Cu alloy film forming the bonding pad is hardened. Therefore, the bonding pad is difficult to be deformed by impact in bonding of a Cu wire, and deformation of an OPM film as following the deformation of the bonding pad can be reduced. In this manner, concentration of a stress on the OPM film caused by the impact from the Cu wire can be reduced, and therefore, the breakage of the OPM film can be prevented.

Semiconductor device and method of manufacturing the same

It is possible to prevent deterioration of a redistribution layer due to exposure of the redistribution layer from an upper insulating film and the resultant reaction with moisture, ions, or the like. As means thereof, in a semiconductor device having a plurality of wiring layers formed in an element formation region and having a redistribution layer connected with a pad electrode which is an uppermost wiring layer, a dummy pattern is arranged in a region closer to a scribe region than the redistribution layer.

Semiconductor device

A semiconductor device suitable for preventing malfunction is provided. The semiconductor device includes a semiconductor chip 1, a first electrode pad 21 laminated on the semiconductor chip 1, an intermediate layer 4 having a rectangular shape defined by first edges 49 a and second edges, and a plurality of bumps 5 arranged to sandwich the intermediate layer 4 by cooperating with the semiconductor chip 1. The first edges 49 a extend in the direction x, whereas the second edges extend in the direction y. The plurality of bumps 5 include a first bump 51 electrically connected to the first electrode pad 21 and a second bump 52 electrically connected to the first electrode pad 21. The first bump 51 is arranged at one end in the direction x and one end in the direction y.

SEMICONDUCTOR DEVICES, SEMICONDUCTOR PACKAGES, AND METHODS OF MANUFACTURING THE SEMICONDUCTOR DEVICES

A semiconductor device includes a conductive component on a substrate, a passivation layer on the substrate and including an opening that exposes at least a portion of the conductive component, and a pad structure in the opening and located on the passivation layer, the pad structure being electrically connected to the conductive component. The pad structure includes a lower conductive layer conformally extending on an inner sidewall of the opening, the lower conductive layer including a conductive barrier layer, a first seed layer, an etch stop layer, and a second seed layer that are sequentially stacked, a first pad layer on the lower conductive layer and at least partially filling the opening, and a second pad layer on the first pad layer and being in contact with a peripheral portion of the lower conductive layer located on the top surface of the passivation layer. 1. A semiconductor device comprising:a conductive component on a substrate;a passivation layer on the substrate and including an opening therein, wherein the opening exposes at least a portion of the conductive component;a lower conductive layer on an inner wall of the opening and electrically connected to the conductive component, the lower conductive layer including a conductive barrier layer, a first seed layer, an etch stop layer, and a second seed layer that are sequentially stacked; anda pad layer on the lower conductive layer, the pad layer filling the opening,wherein the first seed layer and the conductive barrier layer extend onto a top surface of the passivation layer around the opening, andwherein an undercut region is formed at a portion of the conductive barrier layer under a peripheral portion of the first seed layer.2. The semiconductor device of claim 1 , wherein the lower conductive layer includes a first portion disposed on the inner wall of opening and a second portion disposed on the top surface of the passivation layer claim 1 ,the first portion of the lower conductive layer has a ...

Dummy Flip Chip Bumps for Reducing Stress

A device includes a metal pad over a substrate. A passivation layer includes a portion over the metal pad. A post-passivation interconnect (PPI) is electrically coupled to the metal pad, wherein the PPI comprises a portion over the metal pad and the passivation layer. A polymer layer is over the PPI. A dummy bump is over the polymer layer, wherein the dummy bump is electrically insulated from conductive features underlying the polymer layer. 1. A method comprising: bonding a first solder region to be between and joining to both of an electrical connector of the device die and a metal trace of the package component, wherein the first solder region contacts a bottom surface and sidewalls of the metal trace, and the metal trace is in a surface dielectric layer of the package component; and', 'contacting a second solder region to a bottom surface of the surface dielectric layer or a bond pad of the package component, wherein the bond pad is in the surface dielectric layer, and wherein the second solder region is joined to a dummy bump of the device die., 'bonding a package component to a device die, wherein the bonding comprises2. The method of further comprising forming the device die comprising:forming an additional dielectric layer; andforming the dummy bump over the additional dielectric layer, with an entirety of a bottom surface of the dummy bump contacting a top surface of the additional dielectric layer.3. The method of claim 2 , wherein the dummy bump is electrically disconnected from all conductive components that are lower than the top surface of the additional dielectric layer.4. The method of claim 1 , wherein after the bonding claim 1 , the dummy bump is electrically floating.5. The method of claim 1 , wherein the first solder region extends into an opening in the surface dielectric layer of the package component.6. The method of further comprising claim 5 , after the package component is bonded to the device die claim 5 , dispensing an underfill between ...

Integrated Circuit Structure and Method for Reducing Polymer Layer Delamination

An embodiment integrated circuit structure includes a substrate, a metal pad over the substrate, a post-passivation interconnect (PPI) structure over the substrate and electronically connected to the metal pad, a first polymer layer over the PPI structure, an under bump metallurgy (UBM) extending into an opening in the first polymer layer and electronically connected to the PPI structure, and a barrier layer on a top surface of the first polymer layer adjacent to the UBM. 1. A semiconductor device comprising:a substrate comprising a metal pad;a first polymer layer over the substrate;a post-passivation interconnect (PPI) pad extending through the first polymer layer, wherein the PPI pad is electrically connected to the metal pad, wherein the first polymer layer contacts sidewalls of the PPI pad from a bottom surface of the PPI pad to a top surface of the PPI pad, and wherein a top surface of the PPI pad is level with a top surface of the first polymer layer;a second polymer layer over the first polymer layer and the PPI pad;a PPI structure over the first polymer layer and the PPI pad, wherein the PPI structure is electrically connected to the metal pad, wherein the PPI structure extends through the second polymer layer, and wherein the PPI structure extends along a top surface of the second polymer layer;a third polymer layer over the PPI structure;an under bump metallurgy (UBM) extending at least partially through the third polymer layer, wherein the UBM is electrically connected to and in physical contact with the PPI structure; anda barrier layer over the third polymer layer, the barrier layer comprising a greater hydrogen concentration than the third polymer layer, wherein a top surface of the barrier layer is level with a top surface of the third polymer layer, the top surface of the third polymer layer being in contact with the UBM, wherein a sidewall of the third polymer layer is in contact with a sidewall of the barrier layer, the sidewall of the third ...

WAFER-LEVEL PACKAGE INCLUDING UNDER BUMP METAL LAYER

A semiconductor package includes a semiconductor chip comprising a first surface and a second surface, a redistribution layer on the first surface of the semiconductor chip, an under bump metal (UBM) layer on the redistribution layer, and a solder bump on the UBM layer, and the solder bump covers both outer side surfaces of the UBM layer. 1. A method of manufacturing a wafer-level semiconductor package , the method comprising:forming a redistribution layer and a passivation layer on the semiconductor chip;forming an under bump metal (UBM) on the redistribution layer;forming a preliminary solder layer covering the UBM surface; anddropping a solder ball on the preliminary solder layer,wherein at least one of the UBM and the preliminary solder layer is formed through an electroless plating method, andwherein the thickness of the preliminary solder layer is approximately 1-50 μm.2. The method of claim 1 , wherein the preliminary solder layer is a tin-silver (Sn—Ag) based metal layer.3. The method of claim 1 , wherein the preliminary solder layer is a solder paste containing solder powder and flux.4. The method of claim 1 , wherein claim 1 , before forming the redistribution layer and the passivation layer claim 1 , further comprising forming a mold layer partially covering the semiconductor chip.5. The method of claim 4 , wherein the forming the redistribution layer and the passivation layer comprising:forming a first passivation layer on the semiconductor chip and the mold layer;forming a first trench exposing a connection pad of the semiconductor chip in the first passivation layer;forming the redistribution layer in the first trench in contact with the connection pad; andforming a second passivation layer on the redistribution layer.6. The method of claim 5 , wherein the forming the UBM comprising:forming a mask pattern having an open area on the second passivation layer;etching the second passivation layer through the open region to form a second trench;removing the ...

Package with Solder Regions Aligned to Recesses

A method includes forming a passivation layer over a portion of a metal pad, forming a polymer layer over the passivation layer, and exposing the polymer layer using a photolithography mask. The photolithography mask has an opaque portion, a transparent portion, and a partial transparent portion. The exposed polymer layer is developed to form an opening, wherein the metal pad is exposed through the opening. A Post-Passivation Interconnect (PPI) is formed over the polymer layer, wherein the PPI includes a portion extending into the opening to connect to the metal pad.

Semiconductor Device Having Through Silicon Vias and Manufacturing Method Thereof

In the semiconductor device, a semiconductor substrate has first and second surfaces. A circuitry layer is formed over the first surface and a first insulating layer is further formed over the circuitry layer. A second insulating layer including a first insulating element is formed over the second surface. A third insulating layer including a second insulating element different from the first insulating element of the second insulating layer is formed over the second surface with an intervention of the second insulating layer therebetween. A penetration electrode penetrates through the semiconductor substrate, the circuitry layer, the first insulating layer, the second insulating layer and the third insulating layer. 1. A method of forming a semiconductor device , comprising:providing a semiconductor substrate having a plurality of transistors on a first surface thereof;forming a first interlayer dielectric film on the first surface;forming a multi-level wiring structure on the first interlayer dielectric film;thinning the semiconductor substrate from a surface opposite to the first surface to form a second surface of the semiconductor substrate;forming a first back insulating layer on the second surface of the semiconductor substrate;forming a second back insulating layer in direct contact with the first back insulating layer, the second back insulating layer having a back surface away from first back insulating layer, wherein the second back insulating layer includes an insulating material different from the first back insulating layer;forming an opening on the second back insulating layer, sequentially etching the first back insulating layer and the semiconductor substrate through the opening to form a substrate through hole, wherein the substrate through hole at least reaches the first interlayer dielectric film;forming a through silicon via within the substrate through hole, wherein the through silicon via extends from the first surface of the semiconductor ...

PRE-PLATED SUBSTRATE FOR DIE ATTACHMENT

A method for attaching a semiconductor die to a substrate includes providing a substrate that includes an attachment layer at a surface of the substrate. The attachment layer is covered by a protective flash plating layer. The protective flash plating layer has a reflow temperature less than or equal to a reflow temperature of the attachment layer. The method further includes preheating the substrate to a temperature greater than or equal to a reflow temperature of the attachment layer, attaching a semiconductor die to the attachment layer, and cooling the substrate and semiconductor die. 1. A method for attaching a semiconductor die to a substrate , the method comprising:providing a substrate, the substrate including an attachment layer at a surface of the substrate, the attachment layer directly overlaid by a protective flash plating layer to cover the attachment layer, the protective flash plating layer having a reflow temperature less than or equal to a reflow temperature of the attachment layer;preheating the substrate to a temperature greater than or equal to a reflow temperature of the attachment layer, wherein the protective flash plating layer melts during the preheating to permit access to the attachment layer;attaching a semiconductor die to the attachment layer while the flash plating layer is melted; andcooling the substrate and semiconductor die.2. The method of claim 1 , wherein the protective flash plating layer is made from gold.3. The method of claim 2 , wherein the protective flash plating layer has a thickness in a region above a surface of the attachment layer of about 10 micro-inches or less.4. The method of claim 1 , wherein the attachment layer is made from a combination of gold and tin.5. The method of claim 1 , wherein the substrate is preheated to a temperature of about 310° C.6. The method of claim 1 , wherein the semiconductor die is formed of gallium nitride.7. The method of claim 1 , wherein the substrate is gold plated.8. The method ...

Semiconductor device

There is a need to improve reliability of the semiconductor device. A semiconductor device includes a printed circuit board and a semiconductor chip mounted over the printed circuit board. The semiconductor chip includes a pad, an insulation film including an opening to expose part of the pad, and a pillar electrode formed over the pad exposed from the opening. The printed circuit board includes a terminal and a resist layer including an opening to expose part of the terminal. The pillar electrode of the semiconductor chip and the terminal of the printed circuit board are coupled via a solder layer. Thickness h 1 of the pillar electrode is measured from the upper surface of the insulation film. Thickness h 2 of the solder layer is measured from the upper surface of the resist layer. Thickness h 1 is greater than or equal to a half of thickness h 2 and is smaller than or equal to thickness h 2 .

Semiconductor device and method for manufacturing the same

A pad is formed on an interlayer insulating film, art insulating film is formed on the interlayer insulating film to cover the pad, and an opening portion exposing a part of the pad is formed in the insulating film. A metal film electrically connected to the pad is formed on the pad exposed from the opening portion and on the insulating film. The metal film integrally includes a first portion on the pad exposed from the opening portion and a second portion on the insulating film. An upper surface of the metal film has a wire bonding region for bonding a wire to the metal film and a probe contact region for bringing the probe into contact with the metal film, the wire bonding region is located on the first portion of the metal film, and the probe contact region is located on the second portion of the metal film.

METHOD FOR PROCESSING AN ELECTRONIC COMPONENT AND AN ELECTRONIC COMPONENT

According to various embodiments, a method for processing an electronic component including at least one electrically conductive contact region may include: forming a contact pad including a self-segregating composition over the at least one electrically conductive contact region to electrically contact the electronic component; forming a segregation suppression structure between the contact pad and the electronic component, wherein the segregation suppression structure includes more nucleation inducing topography features than the at least one electrically conductive contact region for perturbing a chemical segregation of the self-segregating composition by crystallographic interfaces of the contact pad defined by the nucleation inducing topography features. 1. A method for processing an electronic component comprising at least one electrically conductive contact region , the method comprising:forming a contact pad comprising a self-segregating composition over the at least one electrically conductive contact region to electrically contact the electronic component;forming a segregation suppression structure between the contact pad and the electronic component, wherein the segregation suppression structure comprises more nucleation inducing topography features than the at least one electrically conductive contact region for perturbing a chemical segregation of the self-segregating composition by crystallographic interfaces of the contact pad defined by the nucleation inducing topography features.2. The method of claim 1 ,wherein each nucleation inducing topography feature of the segregation suppression structure is configured to induce crystallite nucleation thereon such that a crystallographic interface is formed between adjacent nucleation inducing topography features of the segregation suppression structure.3. The method of claim 1 ,wherein at least one nucleation inducing topography feature of the segregation suppression structure is disposed between two ...

Dummy Flip Chip Bumps for Reducing Stress

A device includes a metal pad over a substrate. A passivation layer includes a portion over the metal pad. A post-passivation interconnect (PPI) is electrically coupled to the metal pad, wherein the PPI comprises a portion over the metal pad and the passivation layer. A polymer layer is over the PPI. A dummy bump is over the polymer layer, wherein the dummy bump is electrically insulated from conductive features underlying the polymer layer. 1. A device comprising:a substrate;a metal pad over the substrate;a passivation layer comprising a portion over the metal pad;a post-passivation interconnect (PPI) electrically coupling to the metal pad, wherein the PPI comprises a portion over the metal pad and the passivation layer;a polymer layer over the PPI; a first portion extending into the polymer layer to electrically couple to the metal pad; and', 'a second portion having a bottom surface contacting a top surface of the polymer layer; and, 'a non-solder electrical connector comprisinga dummy bump having a bottom surface contacting the top surface of the polymer layer.2. The device of claim 1 , wherein the dummy bump comprises:a non-solder bump and a solder cap over the non-solder bump.3. The device of further comprising a device over the non-solder electrical connector and the dummy bump claim 1 , wherein the device comprises a dielectric layer claim 1 , and a bottom surface of the dielectric layer in the device is in contact with a top surface of the dummy bump.4. The device of claim 3 , wherein the dummy bump comprises a solder region claim 3 , and the bottom surface of the dielectric layer is in contact with the top surface of the dummy bump.5. The device of claim 4 , wherein the dummy bump further comprises a non-solder portion underlying the solder region.6. The device of claim 1 , wherein the polymer layer is a polyimide layer claim 1 , and wherein the dummy bump comprises a copper-containing material.7. The device of claim 1 , wherein the dummy bump is ...