Semiconductor package and method of manufacturing thereof

SEMICONDUCTOR DEVICE WITH A SOLDER BUMP AND METHODS FOR MANUFACTURING THE SEMICONDUCTOR DEVICE AND A WIRING SUBSTRATE

PURPOSE: A semiconductor device and methods for manufacturing the same and a wiring substrate are provided to precisely form a solder layer on a desirable area of a wiring pad by forming the solder layer using a patterned photoresist layer. CONSTITUTION: An electrode pad(9) is formed on a semiconductor substrate(5). A passivation film(6) covers the semiconductor substrate and the periphery of the electrode pad. A contact layer(7) and a seed metal layer(8) are formed on the electrode pad in order. A barrier metal layer(2) and a solder layer(3) are formed on the seed metal layer in order. A stopper film(4) is formed on the upper part of the barrier metal layer. COPYRIGHT KIPO 2013 ...

Semiconductor device, method of manufacturing the same, and method of manufacturing wiring board

Pillar structure and manufacturing method thereof

BUMP STRESS MITIGATION LAYER FOR INTEGRATED CIRCUITS

An apparatus comprises a semiconductor substrate having a device layer, a plurality of metallization layers, a passivation layer, and a metal bump formed on the passivation layer that is electrically coupled to at least one of the metallization layers. The apparatus further includes a solder limiting layer formed on the passivation layer that masks an outer edge of the top surface of the metal bump, thereby making the outer edge of the top surface non-wettable to a solder material.

PRECISION ELECTROPLATED SOLDER BUMPS AND METHOD FOR MANUFACTURING THEREOF

A solder bump structure and a method for fabrication of a solder bump, comprising applying preferably an insulating film, followed by applying a multilayer underbump metallization, a layer of a photoresist, and a thin layer of titanium on a substrate containing, preferably, III-V semiconductor circuits.

Semiconductor devices having metal bumps with flange

A semiconductor device having a terminal site (100) including a flat pad (110) of a first metal covered by a layer (130) of dielectric material, the layer over the pad parallel to the pad and having a window of a first diameter (132) exposing the surface of the underlying pad. The terminal site further has a patch-shaped film (140) of a second metal covering the surface of the exposed first metal and the surface of an annulus of the dielectric layer framing the window, the film patch having a second diameter (141) greater than the first diameter; and a bump (150) of a third metal adhering to the film, the bump having a third diameter (151) smaller than the second diameter, whereby the film protrudes like a flange from the bump.

Interconnect structures for preventing solder bridging, and associated systems and methods

Semiconductor dies having interconnect structures formed thereon, and associated systems and methods, are disclosed herein. In one embodiment, an interconnect structure includes a conductive material electrically coupled to an electrically conductive contact of a semiconductor die. The conductive material includes a first portion vertically aligned with the conductive contact, and a second portion that extends laterally away from the conductive contact. A solder material is disposed on the second portion of the interconnect structure such that the solder material is at least partially laterally offset from the conductive contact of the semiconductor die. In some embodiments, an interconnect structure can further include a containment layer that prevents wicking or other undesirable movement of the solder material during a reflow process.

TERMINAL PAD STRUCTURES AND METHODS OF FABRICATING SAME

Terminal pads and methods of fabricating terminal pads. The methods including forming a conductive diffusion barrier under a conductive pad in or overlapped by a passivation layer comprised of multiple dielectric layers including diffusion barrier layers. The methods including forming the terminal pads subtractively or by a damascene process.

Low fabrication cost, fine pitch and high reliability solder bump

A barrier layer is deposited over a layer of passivation including in an opening to a contact pad created in the layer of passivation. A column of three layers of metal is formed overlying the barrier layer and aligned with the contact pad and having a diameter that is about equal to the surface of the contact pad. The three metal layers of the column comprise, in succession when proceeding from the layer that is in contact with the barrier layer, a layer of pillar metal, a layer of under bump metal and a layer of solder metal. The layer of pillar metal is reduced in diameter, the barrier layer is selectively removed from the surface of the layer of passivation after which reflowing of the solder metal completes the solder bump of the invention.

Method for manufacturing precision electroplated solder bumps

A method for fabrication of a solder bump, comprising applying preferably an insulating film, followed by applying a multilayer underbump metallization, a layer of a photoresist, and a thin layer of titanium on a substrate containing, preferably, III-V semiconductor circuits. The multilayer UBM pad, preferably comprising a 0.02 to 0.05 micrometer thick layer of titanium, a 0.5 to 1.0 micrometer thick layer of nickel and a 0.1 to 0.2 thick layer of gold. The protective film with the thickness of preferably 0.5 to 40 micrometer comprises a photoresist. After the solder has been electroplated, the protective film is removed, preferably by dry etching or with a solvent. The titanium film serves a dual function of being a membrane for electroplating of the solder and of being a non-wettable dam for wetting back of the plated solder. The titanium film with the thickness of 200 to 1,000 Angstroms is preferably deposited by evaporation. After the solder has been electroplated, much of the titanium ...

Metallic strain-absorbing layer for improved fatigue resistance of solder-attached devices

An integrated circuit chip 501 has a plurality of contact pads (FIG. 5 B) to be connected by reflow attachment 510 to outside parts. The chip comprises a deposited layer 505 of nickel/titanium alloy on each of the pads; the alloy has a composition and crystalline structure operable in reversible phase transitions under thermomechanical stress, whereby mechanical strain is absorbed by the alloy layer. Preferably, the alloy has between 55.0 and 56.0 weight % nickel, between 44.0 and 45.0 weight % titanium, and a thickness in the range from 0.3 to 6.0 mum, recrystallized after deposition in a temperature range from 450 to 600° C. for a time period between 4 and 6 min. A layer 506 of solderable metal is on the alloy, operable as diffusion barrier after reflow attachment.

Wire and solder bond forming methods

Methods of forming wire and solder bond structures are disclosed. In one embodiment, a method includes providing a structure including a wire bond metal region for the wire bond and a solder bond metal region for the solder bond; forming a protective layer over the wire bond metal region only; forming a silicon nitride layer over a silicon oxide layer over the wire bond metal region and the solder bond metal region; forming the solder bond to the solder bond metal region while maintaining the wire bond metal region covered; exposing the wire bond metal region including removing the protective layer; and forming the wire bond to the wire bond metal region. Wire bond and solder bond structures can be made accessible on a single multi-part wafer (MPW) wafer or on a single chip, if necessary.

Autoclave capable chip-scale package

A power semiconductor package that includes a power semiconductor device having a threshold voltage that does not vary when subjected to an autoclave test.

Fabrication method of semiconductor structure

The present invention provides a semiconductor structure and a method of fabricating the same. The method includes: providing a chip having conductive pads, forming a metal layer on the conductive pads, forming a passivation layer on a portion of the metal layer, and forming conductive pillars on the metal layer. Since the metal layer is protected by the passivation layer, the undercut problem is solved, the supporting strength of the conductive pillars is increased, and the product reliability is improved.

SEMICONDUCTOR PACKAGE

A semiconductor package includes a first semiconductor chip having a first chip substrate, the first chip substrate having a first upper surface and a first lower surface opposite to each other, a first through-silicon via (TSV), a lower connection pad and a first lower passivation layer on the first lower surface of the first chip substrate, the first lower passivation layer exposing a portion of the lower connection pad, an upper connection pad and a first upper passivation layer on the first upper surface of the first chip substrate, the first upper passivation layer including a first upper inorganic material layer, and a second semiconductor chip connected to the first semiconductor chip, the second semiconductor chip including a second TSV, wherein the first lower passivation layer has a stacked structure of a first lower inorganic material layer and a lower organic material layer.

Wafer-level moat structures

Handling thin wafer during chip manufacture

Integrated circuit element and packaging component

The invention provides an integrated circuit element and a packaging component. The integrated circuit element comprises a semiconductor substrate, a conductive column which is disposed on the semiconductor substrate and has a side wall surface and an upper surface, a boss lower metal layer which is disposed between the semiconductor substrate and the conductive column and has a surface area which is adjacently connected to the side wall surface of the conductive column and extends from the side wall surface, and a protection structure which is disposed on the side wall surface of a copper column and on the surface area of the boss lower metal layer. The protection structure is made of metal materials and the conductive column is composed by copper layers. The side wall protection structure covers at least a part of the side wall surface of the boss structure, and the protection structures disposed on the copper column side wall and on the surface area of the boss lower metal layer are ...

Tri-dimensional integrated circuit structure

Manufactoring process of bumps for chips

Un procédé de fabrication d'une bosse (7) en métal pour puce comprend les étapes consistant à: former une couche de métal d'arrêt (5) sur un substrat sur lequel est formée une pastille; former une couche de photorésist (6) sur la couche de métal d'arrêt (5) et ouvrir une zone de la pastille; former une bosse (7) pour puce par électrodéposition sur la zone ouverte; sélectivement éliminer la couche de photorésist (6) en utilisant la bosse (7) en tant que masque; attaquer une zone prédéterminée de la couche de métal d'arrêt (5) en utilisant comme masque la couche de photorésist restante (10); et former une bosse (7) pour puce sur la pastille en éliminant la couche de photorésist restante (10).

HYBRIDIZATION TO-FACE TWO MICROELECTRONIC COMPONENTS USING ANNEAL UV

Ce procédé de fabrication d'un dispositif microélectronique comportant un premier composant (12) hybridé à un second composant (14) au moyen d'interconnexions électriques, consiste : ▪ à réaliser des premier et second composants (12, 14), le second composant (14) étant transparent à un rayonnement ultraviolet au moins au droit d'emplacements prévus pour les interconnexions ; ▪ à former des éléments d'interconnexion (22) comprenant de l'oxyde de cuivre sur le second composant (14) aux emplacements prévus pour les interconnexions; ▪ à reporter les premier et second composants (12, 14) l'un sur l'autre ; et ▪ à appliquer un rayonnement ultraviolet au travers le second composant (14) sur les éléments comprenant de l'oxyde de cuivre de manière à mettre en œuvre un recuit ultraviolet transformant l'oxyde de cuivre en cuivre.

METAL WIRING STRUCTURES FOR UNIFORM CURRENT DENSITY IN C4 BALLS

반도체 장치 및 이의 제조 방법

... 본 발명은 반도체 장치 및 이의 제조 방법을 제공한다. 이 반도체 장치에서는, 재배선 패턴들 사이에 유기 절연 패턴이 개재된다. 상기 재배선 패턴이 열에 의해 팽창될 경우 발생되는 물리적 스트레스를 상기 유기 절연 패턴이 흡수할 수 있다. 이로써 유연성을 증대시킬 수 있다. 재배선 패턴들 사이에 유기절연 패턴이 개재되므로, 재배선 패턴들 사이에 반도체 패턴이 개재되는 경우에 비해, 절연성을 증대시킬 수 있다. 또한 재배선 패턴과 유기 절연 패턴 사이 그리고 반도체 기판과 유기 절연 패턴 사이에 시드막 패턴이 개재되므로, 재배선 패턴의 접착력이 향상되어 박리 문제를 개선할 수 있다. 또한 재배선 패턴을 구성하는 금속이 유기 절연 패턴으로 확산되는 것을 시드막 패턴이 방지할 수 있다. 이로써, 신뢰성이 향상된 반도체 장치를 구현할 수 있다.

ON-CHIP CAPACITORS AND METHODS OF ASSEMBLING SAME

A ROUTING LAYER FOR MITIGATING STRESS IN A SEMICONDUCTOR DIE

METHOD FOR FORMING SOLDER BUMP AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

PURPOSE: To provide a method for forming solder bumps suitable for an IC chip inexpensively, and a method for manufacturing a semiconductor device. CONSTITUTION: An opening 6 is made in an inexpensive photoresist 5 having low heat resistance formed on a wafer 1, and only a solder paste 9 filling that opening 6 is heated locally with laser light 16 to form a solder bump 10. According to the method, solder bumps 10 of a specified quantity can be formed with no variation in the openings 6 made with a high accuracy and a method for forming solder bumps at a low cost through use of an inexpensive photoresist can be provided. © KIPO & JPO 2002 ...

UNDER BUMP METALLIZATION FOR ON-DIE CAPACITOR

BUMP WITH MULTIPLE VIAS FOR SEMICONDUCTOR PACKAGE TO INCREASE SURFACE AREA OF WIRING, FABRICATING METHOD THEREOF, AND SEMICONDUCTOR PACKAGE USING THE SAME

PURPOSE: A bump with multiple vias for a semiconductor package, a fabricating method thereof, and a semiconductor package using the same are provided to increase a surface area of a wiring by forming a polymer layer having the multiple vias on an electrode pad. CONSTITUTION: An electrode pad(115) is formed on a semiconductor chip(110), and a polymer layer(130) having plural vias(135) is formed on the electrode pad. An under bump metal layer(170) having plural vias is formed on the polymer layer. A metal bump(180) is bonded on the under bump metal layer. The electrode pad is redistributed from a first region to a second region. A stress relaxation layer(160) is formed on the polymer layer having the vias. The under bump metal layer includes at least one of an adhesion layer, a diffusion-barrier layer, and a wetting layer. © KIPO 2007 ...

Semiconductor structure and manufacturing method thereof

A semiconductor structure includes a substrate, a conductive interconnection exposed from the substrate, a passivation covering the substrate and a portion of the conductive interconnection, an under bump metallurgy (UBM) pad disposed over the passivation and contacted with an exposed portion of the conductive interconnection, and a conductor disposed over the UBM pad, wherein the conductor includes a top surface, a first sloped outer surface extended from the top surface and including a first gradient, and a second sloped outer surface extended from an end of the first sloped outer surface to the UBM pad and including a second gradient substantially smaller than the first gradient.

Semiconductor packaging and manufacturing method thereof

The present disclosure provides a semiconductor package, which includes a substrate, a passivation layer, a post-passivation interconnect (PPI) having a top surface; and a conductive structure. The top surface of the PPI includes a first region receiving the conductive structure, and a second region surrounding the first region. The second region includes metal derivative transformed from materials made of the first region. The present disclosure provide a method of manufacturing a semiconductor package, including forming a first flux layer covering a portion of a top surface of a PPI; transforming a portion of the top surface of the PPI uncovered by the first flux layer into a metal derivative layer; removing the first flux layer; forming a second flux layer on the first region of the PPI; dropping a solder ball on the flux layer; and forming electrical connection between the solder ball and the PPI.

Extended under-bump metal layer for blocking alpha particles in a semiconductor device

An integrated circuit (IC) has an under-bump metal (UBM) pad disposed between a solder bump and a semiconductor portion of the IC. The UBM pad has a contact perimeter formed with the solder bump. The UBM pad extends beyond the contact perimeter a sufficient distance to block alpha particles emitted from the surface of the solder bump from causing an upset event in the semiconductor portion.

Semiconductor structure and method of manufacturing thereof

High q factor integrated circuit inductor

PRECISION ELECTROPLATED SOLDER BUMPS AND METHOD FOR MANUFACTURING THEREOF

A solder bump structure and a method for fabrication of a solder bump, comprising applying preferably an insulating film, followed by applying a multilayer underbump metallization, a layer of a photoresist, and a thin layer of titanium or chrome, or Ti-Ni-Ti, Ti-Ni-Cr, Ti-Pt-Ti, or Ti-Ni-SiOX deposited over or under said underbump metallization, on a substrate containing, preferably, III-V semiconductor circuits and removing said thin layer in a region spaced from said underbump metallization.

SEMICONDUCTOR DEVICE HAVING A BUMP ELECTRODE AND METHOD FOR ITS MANUFACTURE

Various semiconductor die conductor structures and methods of fabricating the same are provided. In one aspect, a method of manufacturing is provided that includes forming a conductor structure (230) on a conductor pad (200) of a semiconductor die (170). The conductor layer has a surface. A polymeric layer (240) is formed on the surface of the conductor layer while a portion of the surface is left exposed. A solder.structure (280) is formed on the exposed portion of the surface and a portion of the polymeric layer.

Radiate under-bump metallization structure for semiconductor devices

An under-bump metallization (UBM) structure for a semiconductor device is provided. The UBM structure has a center portion and extensions extending out from the center portion. The extensions may have any suitable shape, including a quadrangle, a triangle, a circle, a fan, a fan with extensions, or a modified quadrangle having a curved surface. Adjacent UBM structures may have the respective extensions aligned or rotated relative to each other. Flux may be applied to a portion of the extensions to allow an overlying conductive bump to adhere to a part of the extensions.

Solder bumps in flip-chip technologies

A solder bump structure and method for forming the same. The structure includes (a) a dielectric layer including a dielectric layer top surface (b) an electrically conducting bond pad on and in direct physical contact with the dielectric layer top surface; (c) a patterned support/interface layer on the dielectric layer top surface and thicker than the electrically conducting bond pad in the reference direction, wherein the patterned support/interface layer comprises a hole and a trench, wherein the hole is directly above the electrically conducting bond pad, and wherein the trench is not filled by any electrically conducting material; and (d) an electrically conducting solder bump filling the hole and electrically coupled to the electrically conducting bond pad.

Electronic component, semiconductor device employing same, and method for manufacturing electronic component

Herein disclosed an electronic component having a passivation layer in which an opening that exposes a part of a pad electrode is formed, an underlying metal layer formed on the pad electrode and the passivation layer, and a barrier metal layer formed on the underlying metal layer for an external connection electrode, the electronic component including a recess or/and a projection configured to be provided under the barrier metal layer outside or/and inside the opening, the underlying metal layer being formed on the recess or/and the projection and having a surface shape that follows the recess or/and the projection.

Bond pad scheme for Cu process

A novel method of forming a bond pad of a semiconductor device and a novel bond pad structure. Two passivation layers are used to form bond pads of a semiconductor device. A portion of the second passivation layer resides between adjacent bond pads, preventing shorting of the bond pads during subsequent wire bonding processes or flip-chip packaging processes.

Connecting device for connecting a semiconductor chip to a conductor

A connecting device, and corresponding method, for connecting a semiconductor chip/chip and a conductor, the connecting device including: a pad formed on the chip; a passivation layer formed around the pad thereby defining an aperture in the passivation layer; a pad-to-bump connecting layer at least in the aperture; and a bump, formed on the pad-to-bump connecting layer, not extending laterally outside of the aperture. The passivation layer is also formed on an edge area of the pad so as to define shoulder portions between which the aperture is located. The pad-to-bump connecting layer includes: a first base layer formed in the aperture and also on the shoulder portions of the passivation layer so that the first base layer extends laterally outside the aperture; and a second base layer formed at least in the aperture. The cross-sectional area of the bump is less than the cross-sectional area of the aperture.

SEMICONDUCTOR DEVICE MANUFACTURING METHOD

A method of manufacturing a semiconductor device includes a first process in which a first wiring 3 is provided on a first surface 2a of a semiconductor substrate 2; a second process in which a light transmitting substrate 5 is attached to the first surface 2a; a third process in which the semiconductor substrate 2 is thinned so that the thickness of the semiconductor substrate 2 is smaller than the thickness of the light transmitting substrate 5; a fourth process in which a through hole 7 is formed in the semiconductor substrate 2; a fifth process in which a dip coating method is performed using a first resin material and thus a resin insulating layer 10 is provided; a sixth process in which a contact hole 16 is formed in the resin insulating layer 10; and a seventh process in which a second wiring 8 is provided on a surface 10b of the resin insulating layer 10, and the first wiring 3 and the second wiring 8 are electrically connected via a contact hole 16.

ENHANCED RELIABILITY FOR SEMICONDUCTOR DEVICES USING DIELECTRIC ENCASEMENT

A method and device for enhanced reliability for semiconductor devices using dielectric encasement is disclosed. The method and device are directed to improving the reliability of the solder joint that connects the integrated circuit (IC) chip to the substrate. The method comprises applying a layer of a photoimageable permanent dielectric material to a top surface of the semiconductor device, and patterning the layer of the photoimageable permanent dielectric material to have an opening over each feature. The method further comprises dispensing or stencil printing fluxing material into the permanent dielectric material openings, and applying solder, which contains no flux, to a top surface of the fluxing material. In one or more embodiments, the method further comprises heating the semiconductor device to a reflow temperature appropriate for the reflow of the solder, thereby causing the solder to conform to sidewalls of the permanent dielectric material openings to form a protective seal ...

Semiconductor device with fuse to be blown with energy beam and method of manufacturing the semiconductor device

A semiconductor device has a fuse to be blown with an energy beam. The semiconductor device has copper wiring levels formed on a semiconductor substrate on which semiconductor elements are formed, an uppermost wiring level formed on said copper wiring levels and including a refractory metal film connected to a top one of the copper wiring levels, the fuse formed from a part of the uppermost wiring level, and a surface protective film formed on the uppermost wiring level.

UBM etching methods for eliminating undercut

A method includes forming an under-bump metallurgy (UBM) layer overlying a substrate, and forming a mask overlying the UBM layer. The mask covers a first portion of the UBM layer, and a second portion of the UBM layer is exposed through an opening in the mask. A metal bump is formed in the opening and on the second portion of the UBM layer. The mask is then removed. A laser removal is performed to remove a part of the first portion of the UBM layer and to form an UBM.

Stress Reduction in Chip Packaging by Using a Low-Temperature Chip-Package Connection Regime

A semiconductor chip and a package substrate may be directly connected on the basis of form closure by providing appropriately shaped complementary contact structures in the semiconductor chip and the package substrate. Consequently, solder material may no longer be required and thus any elevated temperatures during the assembly process may be avoided, which may conventionally result in significant stress forces, thereby creating damage, in particular in very complex metallization systems.

НИТРИДНЫЙ ПОЛУПРОВОДНИКОВЫЙ СВЕТОИЗЛУЧАЮЩИЙ ЭЛЕМЕНТ И СПОСОБ ЕГО ИЗГОТОВЛЕНИЯ

Способ изготовления нитридного полупроводникового светоизлучающего элемента с перевернутым кристаллом, включающего в себя структуру нитридного полупроводникового светоизлучающего элемента, имеющего слой нитридного полупроводника n-типа и слой нитридного полупроводника р-типа, которые нанесены на подложку, а также участок соединения электрода n-стороны с нитридным полупроводниковым слоем n-типа и участок соединения электрода р-стороны с нитридным полупроводниковым слоем р-типа с одной и той же плоской стороны подложки, электрод n-стороны, соединенный с участком соединения электрода n-стороны и электрод р-стороны, соединенный с участком соединения электрода р-стороны; и металлические столбиковые выводы, сформированные на электроде n-стороны и электроде р-стороны, включающий последовательно выполняемые операции: этап формирования защитного слоя, этап формирования первой структуры резиста, этап вытравливания защитного слоя, этап формирования первого металлического слоя, этап формирования второй ...

HALBLEITERANORDNUNG VON METALLHOECKER-TYP UND VERFAHREN ZU DEREN HERSTELLUNG.

Halbleiterbauelement mit einem Verspannungspuffermaterial, das über einem Metallisierungssystem mit kleinem ε gebildet ist

Halbleiterbauelement (200) mit: einem über einem Substrat gebildeten Metallisierungssystem, das mehrere Metallisierungsschichten aufweist, wovon zumindest einige ein dielektrisches Material mit kleinem aufweisen; einer Verspannungspufferschicht (260), die über einer letzten Metallisierungsschicht (140) des Metallisierungssystems (120) gebildet ist, wobei die Verspannungspufferschicht (260) kupferenthaltende Puffergebiete (265) aufweist, die mit kupferenthaltenden Kontaktanschlussflächen (242) in Verbindung stehen, die in der letzten Metallisierungsschicht (140) des Metallisierungssystems (120) vorgesehen und voneinander durch Isoliergräben (266) getrennt sind; bleifreien Kontaktelementen (210), die auf Teilen der kupferenthaltenden Puffergebiete (265) ausgebildet sind; und einem Gehäusesubstrat, das mit dem Metallisierungssystem (120) über die bleifreien Kontaktelemente (210) verbunden ist; und wobei die Verspannungspufferschicht (260) ferner ein dielektrisches Abstandshaltermaterial, das ...

Method of applying a bump to a substrate

DRAHTUND SOLDER JOINT MANUFACTURING PROCESS

ROBUST INTERCONNECT STRUCTURE

A structure comprising a layer of copper (1), a barrier layer (10), a layer of AlCu (9), and a pad-limiting layer (7), wherein the layer of AlCu and barrier layer are interposed between the layer of copper and pad-limiting layer.

Method and structure for reduction of soft error rates in integrated circuits

A structure and a method for reduction of soft error rates in integrated circuits. The structure including: a semiconductor substrate; and a stack of one or more wiring levels stacked from a lowermost wiring level to an uppermost wiring level, the lowermost wiring level nearer the semiconductor substrate than the uppermost wiring level; and an alpha particle blocking layer on a top surface of the uppermost wiring level of the one or more wiring levels, the blocking layer comprising metal wires and a dielectric material, the blocking layer having a combination of a thickness of the blocking layer and a volume percent of metal wires in the blocking layer sufficient to stop a predetermined percentage of alpha particles of a selected energy or less striking the blocking layer from penetrating into the stack of one or more wiring levels or the substrate.

Method for forming inductor and semiconductor structure

Enhanced reliability for semiconductor devices using dielectric encasement

A method and device for enhanced reliability for semiconductor devices using dielectric encasement is disclosed. The method and device are directed to improving the reliability of the solder joint that connects the integrated circuit (IC) chip to the substrate. The method comprises applying a layer of a photoimageable permanent dielectric material to a top surface of the semiconductor device, and patterning the layer of the photoimageable permanent dielectric material to have an opening over each feature. The method further comprises dispensing or stencil printing fluxing material into the permanent dielectric material openings, and applying solder, which contains no flux, to a top surface of the fluxing material. In one or more embodiments, the method further comprises heating the semiconductor device to a reflow temperature appropriate for the reflow of the solder, thereby causing the solder to conform to sidewalls of the permanent dielectric material openings to form a protective seal ...

Method for assembling integrated circuit with another integrated circuit to form three-dimensional integrated structure, involves realizing electrically conducting pillar crossing from integrated circuit front face and leading to metal line

Structure intégrée tridimensionnelle et procédé d'assemblage de circuits intégrés correspondant, ladite structure comprenant un assemblage d'un premier circuit intégré (CI1) et d'un deuxième circuit intégré (CI2), dans lequel la face arrière (BF1) du premier circuit intégré est collée directement à la face avant (FF2) du deuxième circuit intégré et comprenant au moins un pilier électriquement conducteur (PC) traversant le premier circuit intégré depuis le voisinage de la face avant du premier circuit intégré et débouchant sur une ligne métallique (LM2) du deuxième circuit intégré.

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

A semiconductor structure includes a substrate, a conductive interconnection part exposed from the substrate, a passivation part covering the substrate and a portion of the conductive interconnection part, an under bump metallurgy (UBM) pad disposed on the upper side of the passivation part and touching an exposed portion of the conductive interconnection part, and a conductor disposed on the upper side of the UBM pad. The conductor includes a top surface, a first sloped outer surface extended from the top surface and including a first gradient, and a second sloped outer surface extended from an end of the first sloped outer surface to the UBM pad and including a second gradient substantially smaller than the first gradient. COPYRIGHT KIPO 2016 (AA) W_conductor (BB) W_lower end (CC) W_upper end (DD) W_protrusion (EE) H_protrusion (FF) H_conductor ...

ROBUST INTERCONNECT STRUCTURE

BUMP STRESS MITIGATION LAYER FOR INTEGRATED CIRCUITS

Routing under bond pad for the replacement of an interconnect layer

전자 장치

... 전자 장치를 제공한다. 이 장치는 기판의 제1 면 상에 형성되며 서로 이격된 도전성의 제1 및 제2 배선들을 포함한다. 상기 제1 및 제2 배선들을 갖는 기판을 덮으며, 상기 제1 배선의 소정 영역을 노출시키는 개구부를 갖는 제1 절연성 물질막이 제공된다. 상기 제1 개구부를 채우며 상기 제1 개구부 보다 큰 폭을 갖는 도전성의 제1 패드가 제공된다. 상기 제1 및 제2 배선들은 제1 물질로 이루어지고, 상기 제1 패드는 상기 제1 물질 보다 낮은 밀도를 갖는 제2 물질로 이루어진다.

Integrated circuit devices and packaging assembly

A sidewall protection structure is provided for covering at least a portion of a sidewall surface of a bump structure, in which a protection structure on the sidewall of a Cu pillar and a surface region of an under-bump-metallurgy (UBM) layer is formed of at least one non-metal material layers, for example a dielectric material layer, a polymer material layer, or combonations thereof.

Semiconductor device and method of forming interconnect structure over seed layer on contact pad of semiconductor die without undercutting seed layer beneath interconnect structure

A semiconductor device has a semiconductor die with a first conductive layer formed over the die. A first insulating layer is formed over the die with a first opening in the first insulating layer disposed over the first conductive layer. A second conductive layer is formed over the first insulating layer and into the first opening over the first conductive layer. An interconnect structure is constructed by forming a second insulating layer over the first insulating layer with a second opening having a width less than the first opening and depositing a conductive material into the second opening. The interconnect structure can be a conductive pillar or conductive pad. The interconnect structure has a width less than a width of the first opening. The second conductive layer over the first insulating layer outside the first opening is removed while leaving the second conductive layer under the interconnect structure.

Method of manufacturing electronic device

A method of manufacturing an electronic device. As non-limiting examples, various aspects of this disclosure provide an electronic device having a top side pin array, for example which may be utilized for three-dimensional stacking, and a method for manufacturing such an electronic device.

Semiconductor device and method for manufacturing same

The objects of the present invention is to improve the impact resistance of the semiconductor device against the impact from the top surface direction, to improve the corrosion resistance of the surface of the top layer interconnect, to inhibit the crack occurred in the upper layer of the interconnect layer when the surface of the electrode pad is poked with the probe during the non-defective/defective screening, and to prevent the corrosion of the interconnect layer when the surface of electrode pad is poked with the probe during the non-defective/defective screening. A Ti film 116, a TiN film 115 and a pad metal film 117 are formed in this sequence on the upper surface of a Cu interconnect 112. The thermal annealing process is conducted within an inert gas atmosphere to form a Ti—Cu layer 113, and thereafter a polyimide film 118 is formed, and then a cover through hole is provided thereon to expose the surface of the pad metal film 117, and finally a solder ball 120 is joined thereto.

Low fabrication cost, fine pitch and high reliability solder bump

A barrier layer is deposited over a layer of passivation including in an opening to a contact pad created in the layer of passivation. A column of three layers of metal is formed overlying the barrier layer and aligned with the contact pad and having a diameter that is about equal to the surface of the contact pad. The three metal layers of the column comprise, in succession when proceeding from the layer that is in contact with the barrier layer, a layer of pillar metal, a layer of under bump metal and a layer of solder metal. The layer of pillar metal is reduced in diameter, the barrier layer is selectively removed from the surface of the layer of passivation after which reflowing of the solder metal completes the solder bump of the invention.

Semiconductor device and method for manufacturing the same, semiconductor wafer and semiconductor device manufactured thereby

A semiconductor device including a base semiconductor substrate having an edge area which surrounds an element forming area, a buried oxide film provided over the base semiconductor substrate in the element forming area, and an element forming semiconductor substrate provided over the buried oxide film.

FORMING ROBUST SOLDER INTERCONNECT STRUCTURES BY REDUCING EFFECTS OF SEED LAYER UNDERETCHING

A method for forming an interconnect structure for a semiconductor device includes defining a via in a passivation layer so as expose a top metal layer in the semiconductor device. A seed layer is formed over the passivation layer, sidewalls of the via, and the top metal layer. A barrier layer is formed over an exposed portion of the seed layer, the exposed portion defined by a first patterned opening of a first diameter, and a solder material is formed over the barrier layer using a second patterned opening of a second diameter. The second patterned opening is configured such that the second diameter is larger than the first diameter.

Etchant and method for manufacturing semiconductor device using same

Disclosed are an etchant which is used for redistribution of a semiconductor substrate having an electrode and which is capable of selectively etching copper without etching nickel; and a method for manufacturing a semiconductor device using the same. Specifically disclosed are an etchant which is used for redistribution of a semiconductor substrate and which contains hydrogen peroxide and citric acid and has a content of hydrogen peroxide of from 0.75 to 12% by mass and a content of citric acid of from 1 to 20% by mass, with a molar ratio of hydrogen peroxide and citric acid being in the range of from 0.3 to 5; an etchant for selective etching of copper which is used for redistribution of a semiconductor substrate and which contains hydrogen peroxide and malic acid and has a content of hydrogen peroxide of from 0.75 to 12% by mass and a content of malic acid of from 1.5 to 25% by mass, with a molar ratio of hydrogen peroxide and malic acid being in the range of from 0.2 to 6; and a method ...

Metal contact for chip packaging structure

A chip packaging structure and packaging method. The packaging structure comprises: a semiconductor substrate; a metal pad provided inside the semiconductor substrate; an insulating layer provided on the semiconductor substrate, the insulating layer having an opening for exposing the metal pad; a sub-ball metal electrode provided on the metal pad; a solder ball provided on the surface of the sub-ball metal electrode, the solder ball having a first apron structure and the first apron structure covering partial metal pad on the periphery of the bottom of the under-ball metal electrode. The chip packaging structure of the present invention enhances the adhesion between the solder ball and the metal pad, and improves the reliability in chip packaging.

METHOD OF USING A SACRIFICIAL CONDUCTIVE STACK TO PREVENT CORROSION

A method of fabricating an integrated circuit (IC) chip is disclosed. The method starts with opening a window on a first surface of the IC chip through a passivation overcoat to expose the copper metallization layer. The window has sidewalls and a bottom that is adjacent the copper metallization layer. The method continues with depositing a barrier conductive stack on the passivation overcoat and exposed portions of the copper metallization layer, then depositing a sacrificial conductive stack on the barrier conductive stack. The sacrificial conductive stack has a thickness between 50 Å and 500 Å. The first surface of the semiconductor chip is polished to remove the sacrificial conductive stack and the barrier conductive stack from the surface of the passivation overcoat. 1. A method of fabricating an integrated circuit (IC) chip , the method comprising:etching an opening through a passivation overcoat to a copper metallization layer;depositing a barrier conductive stack on the passivation overcoat and in the opening on the copper metallization layer;depositing a sacrificial conductive stack on the barrier conductive stack; andpolishing to remove the sacrificial conductive stack and the barrier conductive stack from over the passivation overcoat.2. The method of claim 1 , wherein the barrier conductive stack comprises a first layer of tantalum nitride.3. The method of claim 2 , wherein the barrier conductive stack further comprises a layer of nickel.4. The method of claim 3 , wherein the barrier conductive stack further comprises a second layer of tantalum nitride.5. The method of claim 2 , wherein the barrier conductive stack further comprises a layer of tungsten.6. The method of claim 1 , wherein the sacrificial conductive stack comprises any of palladium claim 1 , platinum claim 1 , gold claim 1 , ruthenium or any combination thereof.7. The method of claim 1 , further comprising performing an etching process to remove the sacrificial conductive stack from at ...

Bonding pad structure

Bonding pad structure is provided. The bonding pad structure comprises a semiconductor substrate having a top metal layer thereon, a first passivation layer formed on the semiconductor substrate and the top metal layer, and a bonding pad formed on the first passivation layer and connected to the top metal layer. The bonding pad structure further comprises a second passivation layer formed on the bonding pad and the first passivation layer and a solder bump or bond wire formed on the bonding pad and an upper surface of the second passivation layer, wherein at least one of the first passivation layer and the second passivation layer comprises a photosensitive polymer material.

ALTERNATING CURRENT LIGHT EMITTING DIODE FLIP-CHIP

An alternating current light emitting diode flip chip is provided. The flip chip includes an alternating current light emitting diode chip having a first bond pad and a second bond pad formed thereon. A first solder ball is disposed on the first bond pad and a second solder ball is disposed on the second bond pad. A flip-chip bonding process is performed to bond a carrier substrate with the first solder ball and the second solder ball.

Routing layer for mitigating stress in a semiconductor die

A routing layer for a semiconductor die is disclosed. The routing layer includes traces interconnecting integrated circuit bond-pads to UBMs. The routing layer is formed on a layer of dielectric material. The routing layer includes conductive traces arranged underneath the UBMs as to absorb stress from solder bumps attached to the UMBs. Traces beneath the UBMs protect parts of the underlying dielectric material proximate the solder bumps, from the stress.

Pillar on pad interconnect structures, semiconductor dice and die assemblies including such interconnect structures, and related methods

Methods of fabricating interconnect structures for semiconductor dice comprise forming conductive elements in contact with bond pads on an active surface over a full pillar diameter of the conductive elements, followed by application of a photodefinable material comprising a photoresist to the active surface and over the conductive elements. The polyimide material is selectively exposed and developed to remove photodefinable material covering at least tops of the conductive elements. Semiconductor dice and semiconductor die assemblies are also disclosed.

FABRICATION METHOD OF SEMICONDUCTOR STRUCTURE

The present invention provides a semiconductor structure and a method of fabricating the same. The method includes: providing a chip having conductive pads, forming a metal layer on the conductive pads, forming a passivation layer on a portion of the metal layer, and forming conductive pillars on the metal layer. Since the metal layer is protected by the passivation layer, the undercut problem is solved, the supporting strength of the conductive pillars is increased, and the product reliability is improved.

Semiconductor device and method of manufacturing the same

Disclosed herein is a device that includes a first terminal operatively supplied with a pulse signal, a second terminal, a set of third terminals operatively supplied with identification information, a storage unit configured to store the identification information in response to the pulse signal, and a control unit configured to electrically disconnect the first terminal from the second terminal until the storage unit stores the identification information and electrically connect the first terminal to the second terminal after the storage unit has stored the identification information. This device may be used as each of semiconductor chips that are stacked with each other.

Connector structure and method of forming same

Connector structures and methods of forming the same are provided. A method includes forming a first patterned passivation layer on a workpiece, the first patterned passivation layer having a first opening exposing a conductive feature of the workpiece. A seed layer is formed over the first patterned passivation layer and in the first opening. A patterned mask layer is formed over the seed layer, the patterned mask layer having a second opening exposing the seed layer, the second opening overlapping with the first opening. A connector is formed in the second opening. The patterned mask layer is partially removed, an unremoved portion of the patterned mask layer remaining in the first opening. The seed layer is patterned using the unremoved portion of the patterned mask layer as a mask.

Halbleitervorrichtungen mit Metallisierungen aus porösem Kupfer und zugehörige Herstellungsverfahren

Eine Halbleitervorrichtung umfasst: einen Halbleiterchip; ein elektrisches Anschlusselement zum elektrischen Verbinden der Halbleitervorrichtung mit einem Träger; und eine an das elektrische Anschlusselement angrenzende Metallisierung, wobei die Metallisierung poröses nanokristallines Kupfer enthält.

Halbleiterbauelement mit einem Aufbau für reduzierte Verspannung von Metallsäulen

In einem Metallisierungssystem eines modernen Halbleiterbauelements werden Metallsäulen so vorgesehen, dass diese eine höhere Effizienz der Verteilung einer mechanischen Verspannung besitzen, die auf diese ausgeübt wird. Dies kann erreicht werden, indem der Oberflächenbereich der letzten Passivierungsschicht, der in engem mechanischen Kontakt mit der Metallsäule ist, deutlich vergrößert wird.

Zwischenverbindungsstruktur in einer Waferebenenpackung und Herstellungsverfahren

Zwischenverbindungsstruktur in einer Waferebenenpackung mit - einer elastischen Zwischenverbindung, die einen Metallverbindungskontaktfleck (130) beinhaltet, der sich teilweise über einem in einer hohlraumbildenden Schicht (110) vorgesehenen Hohlraum (120) erstreckt und nur in einem randseitigen Bereich auf der dielektrischen Schicht aufliegt, dadurch gekennzeichnet, dass - sich wenigstens ein Teil des Hohlraums (120) lateral über den Metallverbindungskontaktfleck (130) hinaus erstreckt.

DURABLE CONNECTING STRUCTURE

Semiconductor device and making method

Method for forming a bump for chips.

기판 상에 솔더 성막 및 비용융 범프 구조들을 형성하는 방법

... 기판 상에 금속 또는 금속 합금 층을 형성하는 방법이 개시되며, 그 방법은 i) 적어도 하나의 콘택트 영역 상부의 영구 수지 층 및 상기 영구 수지 층 상부의 임시 수지 층을 포함하는 기판을 제공하는 단계,ii) 상기 적어도 하나의 콘택트 영역을 포함하는 전체 기판 영역을 상기 기판 표면 상에 전도성 층을 제공하는데 적합한 용액과 접촉시키는 단계, iii) 상기 전도성 층 상에 금속 또는 금속 합금 층을 전기도금하는 단계를 포함한다.

SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF

PURPOSE: To provide a semiconductor device and a manufacturing method thereof by which peeling of a electrode pad and a barrier film can be prevented, the yield can be improved and the connection reliability between the semiconductor device and a wiring board can be improved even if stress distortion occurs due to a difference in thermal expansion coefficients between the semiconductor device and the wiring board when the semiconductor device and the wiring board are connected by solder balls formed on the surface of the semiconductor device. CONSTITUTION: This semiconductor device is provided with a barrier film 18 and an electrode pad 19 containing Cu which are formed on a semiconductor substrate 11 and a solder ball 24 containing Sn which is formed on the electrode pad 19. An electrode of a wiring board and the electrode pad 19 on the semiconductor substrate 11 corresponding to this electrode are connected via the solder ball 24. This semiconductor device is provided with a sidewall ...

범프들을 포함한 패키징 소자 및 제조 방법

... 범프들을 포함한 패키징 소자 및 제조 방법을 제시한다. 패키징 소자 제조 방법은, 제1 및 제2접속 패드들을 포함한 패키징 베이스 상에 상기 패키징 베이스를 덮는 유전층을 형성하고, 하부층을 형성한다. 유전층에 중첩되는 복수의 더미 범프들들을 형성하고, 더미 범프들 사이를 메우는 차폐 패턴을 형성한다. 하부층의 차폐 패턴에 의해 차폐되지 않고 드러난 일부 부분들을 제거하여, 복수의 더미 범프들이 배치된 하부층 패턴을 형성한다.

Conductive pillar structure

The invention relates to a bump structure of a semiconductor device. An exemplary structure for a semiconductor device comprises a substrate; a contact pad over the substrate; a passivation layer extending over the substrate having an opening over the contact pad; and a conductive pillar over the opening of the passivation layer, wherein the conductive pillar comprises an upper portion substantially perpendicular to a surface of the substrate and a lower portion having tapered sidewalls.

METHOD AND STRUCTURE FOR REDUCTION OF SOFT ERROR RATES IN INTEGRATED CIRCUITS

A structure and a method for reduction of soft error rates in integrated circuits. The structure including: a semiconductor substrate; and a stack of one or more wiring levels stacked from a lowermost wiring level to an uppermost wiring level, the lowermost wiring level nearer the semiconductor substrate than the uppermost wiring level; and an alpha particle blocking layer on a top surface of the uppermost wiring level of the one or more wiring levels, the blocking layer comprising metal wires and a dielectric material, the blocking layer having a combination of a thickness of the blocking layer and a volume percent of metal wires in the blocking layer sufficient to stop a predetermined percentage of alpha particles of a selected energy or less striking the blocking layer from penetrating into the stack of one or more wiring levels or the substrate.

Semiconductor device packages and methods of manufacturing the same

A semiconductor device package includes a connection structure having a first portion and a second portion extending from the first portion, the second portion having a width less than the first portion; and a dielectric layer surrounding the connection structure, wherein the dielectric layer and the second portion of the connection structure defines a space.

Chip scale package using large ductile solder balls

A chip scale package design for a flip chip integrated circuit includes a redistribution metal layer upon the upper surface of a semiconductor wafer for simultaneously forming solder bump pads as well as the metal redistribution traces that electrically couple such solder bump pads with the conductive bond pads of the underlying integrated circuit. A patterned passivation layer is applied over the redistribution metal layer. Relatively large, ductile solder balls are placed on the solder bump pads for mounting the chip scale package to a circuit board or other substrate without the need for an underfill material. The back side of the semiconductor wafer can be protected by a coating for mechanical strength during handling. A method of forming such a chip scale package at the wafer processing level is also disclosed.

Semiconductor device and method of forming bump structure with insulating buffer layer to reduce stress on semiconductor wafer

A semiconductor wafer has a plurality of semiconductor die with contact pads for electrical interconnect. An insulating layer is formed over the semiconductor wafer. A bump structure is formed over the contact pads. The bump structure has a buffer layer formed over the insulating layer and contact pad. A portion of the buffer layer is removed to expose the contact pad and an outer portion of the insulating layer. A UBM layer is formed over the buffer layer and contact pad. The UBM layer follows a contour of the buffer layer and contact pad. A ring-shaped conductive pillar is formed over the UBM layer using a patterned photoresist layer filled with electrically conductive material. A conductive barrier layer is formed over the ring-shaped conductive pillar. A bump is formed over the conductive barrier layer. The buffer layer reduces thermal and mechanical stress on the bump and contact pad.

Routing layer for mitigating stress in a semiconductor die

A routing layer for a semiconductor die is disclosed. The routing layer includes traces interconnecting integrated circuit bond-pads to UBMs. The routing layer is formed on a layer of dielectric material. The routing layer includes conductive traces arranged underneath the UBMs as to absorb stress from solder bumps attached to the UMBs. Traces beneath the UBMs protect parts of the underlying dielectric material proximate the solder bumps, from the stress.

MANUFACTURING METHOD OF SEMICONDUCTOR PACKAGE

The present disclosure provides a semiconductor package, which includes a substrate, a passivation layer, a post-passivation interconnect (PPI) having a top surface; and a conductive structure. The top surface of the PPI includes a first region receiving the conductive structure, and a second region surrounding the first region. The second region includes metal derivative transformed from materials made of the first region. The present disclosure provide a method of manufacturing a semiconductor package, including forming a first flux layer covering a portion of a top surface of a PPI; transforming a portion of the top surface of the PPI uncovered by the first flux layer into a metal derivative layer; removing the first flux layer; forming a second flux layer on the first region of the PPI; dropping a solder ball on the flux layer; and forming electrical connection between the solder ball and the PPI. 1. A method of manufacturing a semiconductor package , comprising:patterning a first region and a second region on a post-passivation interconnect (PPI), the second region being an oxide or a nitride derivative of the first region; andannealing the first region and the second region on the PPI with a first temperature heat treatment;wherein the first region is surrounded by the second region.2. The method of manufacturing a semiconductor package in claim 1 , wherein the patterning the first region and the second region on the PPI further comprises forming a mask layer over the PPI.3. The method of manufacturing a semiconductor package in claim 2 , wherein the forming the mask layer over the PPI comprises forming a mask layer in contact with the PPI.4. The method of manufacturing a semiconductor package in claim 2 , wherein the forming the mask layer over the PPI comprises positioning a first stencil plate over the PPI.5. The method of manufacturing a semiconductor package in claim 4 , further comprising forming a flux layer in the first region of the PPI by positioning ...

Package with solder regions aligned to recesses

A method includes forming a passivation layer over a portion of a metal pad, forming a polymer layer over the passivation layer, and exposing the polymer layer using a photolithography mask. The photolithography mask has an opaque portion, a transparent portion, and a partial transparent portion. The exposed polymer layer is developed to form an opening, wherein the metal pad is exposed through the opening. A Post-Passivation Interconnect (PPI) is formed over the polymer layer, wherein the PPI includes a portion extending into the opening to connect to the metal pad.

Method for manufacturing a semiconductor device having a refractory metal containing film

A semiconductor device and a method for manufacturing the same of the present invention in which the semiconductor device is provided with a fuse structure or an electrode pad structure, suppress the copper blowing-out from a copper containing metal film. The semiconductor device comprises a silicon substrate, SiO 2 film provided on the silicon substrate, copper films embedded in the SiO 2 film, TiN films covering an upper face of a boundary region between an upper face of copper films and the copper films, and the SiO 2 film, and SiON films covering an upper face of the TiN films.

Semiconductor Device and Method of Making a Semiconductor Device

A semiconductor device and a method of manufacturing a semiconductor device are disclosed. An embodiment comprises forming a bump on a die, the bump having a solder top, melting the solder top by pressing the solder top directly on a contact pad of a support substrate, and forming a contact between the die and the support substrate.

Method to form solder deposits and non-melting bump structures on substrates

Described is a method of forming a metal or metal alloy layer onto a substrate comprising the following steps i) provide a substrate including a permanent resin layer on top of at least one contact area and a temporary resin layer on top of the permanent resin layer, ii) contact the entire substrate area including the at least one contact area with a solution suitable to provide a conductive layer on the substrate surface and i) electroplate a metal or metal alloy layer onto the conductive layer.

Semiconductor chips including passivation layer trench structure

An integrated circuit including an active region a passive region and a cut line in the passive region includes a passivation layer that includes an outer nitride layer over an oxide layer. The integrated circuit also includes a crack stop below the passivation layer and in the passive region, and a solder ball in the active region. The passivation layer has a trench formed therein in a location that is further from the active region than the crack stop and closer to the active region than the cut line, the trench passing completely through the outer nitride layer and a least a portion of the way through the oxide layer.

Semiconductor chip with expansive underbump metallization structures

Methods and apparatus to protect fragile dielectric layers in a semiconductor chip are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first polymer layer over a conductor pad of a semiconductor chip where the conductor pad has a first lateral dimension. An underbump metallization structure is formed on the first polymer layer and in ohmic contact with the conductor pad. The underbump metallization structure has a second lateral dimension greater than the first lateral dimension. A second polymer layer is formed on the first polymer layer with a first opening exposing at least a portion of the underbump metallization structure.

Integrated wluf and sod process

This disclosure relates generally to a wafer having a plurality of semiconductor chips having a major surface, a metal contact positioned on one of the plurality of semiconductor chips and having a side surface and contact surface, the contact surface substantially parallel to the major surface, wherein the contact surface defines a thickness of the metal contact relative to the major surface, an underfill layer abutting the one of the plurality of semiconductor chips and the side surface of the metal contact, the underfill layer having a top surface substantially parallel to the major surface, wherein the top surface of the underfill layer defines a thickness of the underfill layer relative to the major surface, the thickness of the underfill layer being not greater than the thickness of the metal contact, and a solder bump formed in electrical contact with the contact surface of the metal contact.

METHOD FOR FORMING CONDUCTIVE LAYER, AND CONDUCTIVE STRUCTURE AND FORMING METHOD THEREFOR

A method for forming the conductive layer includes: providing a first conductive film and a solution with a conductive material; coating a surface of the first conductive film with the solution, before performing the coating, a temperature of the first conductive film being lower than an evaporation temperature or a sublimation temperature of the solution; and in a process step of performing the coating or after performing the coating, heating the first conductive film, such that the temperature of the first conductive film is higher than or equal to the evaporation temperature or the sublimation temperature of the solution, and forming a second conductive film covering the surface of the first conductive film, wherein the second conductive film including the conductive material. 1. A method for forming a conductive layer , comprising:providing a first conductive film and a solution with a conductive material;coating a surface of the first conductive film with the solution, and prior to said coating, a temperature of the first conductive film being lower than an evaporation temperature or a sublimation temperature of the solution; andin a process step of performing the coating or after performing the coating, heating the first conductive film, such that the temperature of the first conductive film is higher than or equal to the evaporation temperature or the sublimation temperature of the solution, and forming a second conductive film covering the surface of the first conductive film, the second conductive film comprising the conductive material.2. The method for forming a conductive layer of claim 1 , wherein the first conductive film has a damaged surface; the damaged surface is coated with the solution; and after said coating claim 1 , the second conductive film covering the damaged surface is formed.3. The method for forming a conductive layer of claim 1 , wherein in a process step of heating the first conductive film claim 1 , the temperature of the first ...

BUMP STRUCTURES FOR INTERCONNECTING FOCAL PLANE ARRAYS

A method of forming bump structures for interconnecting components includes dry etching a layer of insulating material to create a pattern for bump structures. A seed layer is deposited on the insulating material over the pattern. The seed layer is patterned with a photo resist material. The method also includes forming bump structures over the seed layer and the photo resist material with a plating material to form bump structures in the pattern, wherein the bump structures are isolated from one another. 1. A system comprising:a layer of insulating material with holes therein;a seed layer seated within the holes, wherein the seed layer is recessed below a top surface of the insulating material that is opposite a bottom surface of the holes; anda respective bump structure seated in the seed layer of each hole.2. The system as recited in claim 1 , wherein the bump structures are on one of a photodiode array (PDA) or a read-out integrated circuit (ROIC) claim 1 , and wherein the PDA and ROIC are joined together by the bump structures.3. The system as recited in claim 2 , wherein the PDA and ROIC define a plurality of pixels claim 2 , wherein the plurality of pixels have a pitch size claim 2 , wherein the pitch size is less than 10 μm.4. The system as recited in claim 1 , wherein the bump structures each have a diameter less than 5 um.5. The system as recited in claim 1 , wherein the bump structures each have a height to diameter ratio of greater than 1:1.6. The system as recited in claim 1 , wherein a portion of the bump structures extend from the seed layer proud of the top surface of the insulating material.7. The system as recited in claim 1 , further comprising a dielectric layer on the top surface of the insulating material claim 1 , wherein the seed layer is recessed below the insulating material to provide a gap between the bump structures and the insulating material claim 1 , wherein the gap between the bump structures and the insulating material is also ...

METHOD FOR FORMING BUMP STRUCTURE

Methods for forming semiconductor structures are provided. The method for forming a semiconductor structure includes forming a metal pad over a first substrate and forming a resist layer having an opening over the metal layer. The method for forming a semiconductor structure further includes forming a conductive pillar and a solder layer over the conductive pillar in the opening of the resist layer and removing the resist layer. The method for forming a semiconductor structure further includes removing a portion of the conductive pillar so that the conductive pillar has an angled sidewall. 1. A method for forming a semiconductor structure , comprising:forming a metal pad over a first substrate;forming a resist layer having an opening over the metal layer;forming a conductive pillar and a solder layer over the conductive pillar in the opening of the resist layer;removing the resist layer; andremoving a portion of the conductive pillar so that the conductive pillar has an angled sidewall.2. The method for forming a semiconductor structure as claimed in claim 1 , wherein the angled sidewall includes a first sidewall at a top portion of the conductive pillar and a second sidewall at a bottom portion of the conductive pillar claim 1 , and the first sidewall is in a first direction and the second sidewall is in a second direction different from the first direction.3. The method for forming a semiconductor structure as claimed in claim 2 , further comprising:reflowing the solder layer after the removing the portion of the conductive pillar to form the angled sidewall.4. The method for forming a semiconductor structure as claimed in claim 3 , wherein an inter-metal compound is formed partially covering the first sidewall of the top portion of the conductive pillar after reflowing the solder layer.5. The method for forming a semiconductor structure as claimed in claim 1 , further comprising:forming a seed layer over the metal pad before the conductive pillar is formed, ...

SEMICONDUCTOR DEVICE WITH TRENCH-LIKE FEED-THROUGHS

A semiconductor device (e.g., a flip chip) includes a substrate layer that is separated from a drain contact by an intervening layer. Trench-like feed-through elements that pass through the intervening layer are used to electrically connect the drain contact and the substrate layer when the device is operated. 1. A semiconductor device comprising:an electrically conductive substrate layer;a layer of drain metal, wherein said substrate layer is separated from said drain metal by an intervening layer;a plurality of gate trenches in a gate region under a layer of source metal and that extend into but not completely through said intervening layer, said gate trenches comprising a first gate trench and a second gate trench, each of said gate trenches filled with a first filler material;a plurality of source contact trenches in a source region under said layer of source metal and that that extend into but not completely through said intervening layer, each of said source contact trenches filled with a second filler material, said source contact trenches comprising a first source contact trench and a second source contact trench, wherein said first source contact trench is between said first gate trench and said second gate trench, and wherein said second gate trench is between said first source contact trench and said second source contact trench; anda plurality of feed-through trenches under said layer of drain metal and that extend completely through said intervening layer to said substrate layer, each of said feed-through trenches filled with said second filler material and coupled to said drain metal, wherein said plurality of feed-through trenches are arrayed in only a portion of a drain region of said device under said drain metal, wherein said plurality of feed-through trenches are not included outside said portion and wherein said feed-through trenches within said portion are concentrated toward said source region.2. The semiconductor device of wherein said first ...

Copper Post Structure for Wafer Level Chip Scale Package

In a method for forming a packaging structure, a metal pad is formed on a semiconductor substrate, and a first polymer insulating layer is formed over the semiconductor substrate. An opening passing through the first polymer insulating layer is formed to expose a portion of the metal pad. A copper-containing material is deposited in the opening and over the first polymer insulating layer, thereby forming a copper-containing layer having a first thickness and a first width over the first polymer insulating layer. A conductive bump having a second width is formed over the copper-containing layer, in which the second width is smaller than the first width. An exposed portion of the copper-containing layer is etched using the conductive bump as a mask until the exposed portion is reduced to a second thickness, thereby forming a monolithic copper-containing structure. 1. A device , comprising:a semiconductor substrate;a metal pad on the semiconductor substrate;a first polymer insulating layer overlying the semiconductor substrate and covering a portion of the metal pad;a monolithic copper-containing structure over the metal pad and the first polymer insulating layer, and electrically connected to the metal pad, the monolithic copper-containing structure comprising:a via portion contacting the metal pad embedded in the first polymer insulating layer;a bottom portion having a first thickness and a first width, wherein the bottom portion comprises a post-passivation interconnect (PPI) line; anda top portion adjoining the bottom portion and having a second thickness and a second width, the monolithic copper-containing structure having an undercut structure between the top portion and the bottom portion, wherein the second thickness is greater than the first thickness, and the first width is greater than the second width; anda conductive bump over the top portion of the monolithic copper-containing structure.2. The device of claim 1 , wherein the PPI line is a redistribution ...

Semiconductor Devices and Methods of Forming Thereof

In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes forming a contact layer over a first major surface of a substrate. The substrate includes device regions separated by kerf regions. The contact layer is disposed in the kerf region and the device regions. A structured solder layer is formed over the device regions. The contact layer is exposed at the kerf region after forming the structured solder layer. The contact layer and the substrate in the kerf regions are diced.

Integrated circuit chip and display device including the same

An exemplary embodiment provides a driving circuit chip including: a substrate; a terminal electrode disposed on the substrate; and an electrode pad disposed on the terminal electrode, wherein the electrode pad includes: a bump structure protruded from the substrate to include a short side and a long side; and a bump electrode disposed on the bump structure and connected with the terminal electrode around a short edge portion of the bump structure, wherein the bump electrode is disposed to not cover at least a part of a long edge portion of the bump structure.

METHOD FOR FORMING BUMP STRUCTURE

Methods for forming semiconductor structures are provided. The method for forming a semiconductor structure includes forming a metal pad over a first substrate and forming a polymer layer over the metal pad. The method for forming a semiconductor structure further includes forming a seed layer over the metal pad and extending over the polymer layer and forming a conductive pillar over the seed layer. The method for forming a semiconductor structure further includes wet etching the seed layer using an etchant comprising H2O2. In addition, the step of wet etching the seed layer is configured to form an extending portion having a slope sidewall. 1. A method for forming a semiconductor structure , comprising:forming a metal pad over a first substrate;forming a polymer layer over the metal pad;forming a seed layer over the metal pad and extending over the polymer layer;forming a conductive pillar over the seed layer; and{'sub': 2', '2, 'wet etching the seed layer using an etchant comprising HO, wherein the step of wet etching the seed layer is configured to form an extending portion having a slope sidewall.'}2. The method for forming a semiconductor structure as claimed in claim 1 , wherein the slope sidewall extends from a bottommost of a sidewall of the conductive pillar to a top surface of the polymer layer.3. The method for forming a semiconductor structure as claimed in claim 2 , wherein an inclination of the slope sidewall of the extending portion of the seed layer is different from an inclination of the sidewall of the conductive pillar.4. The method for forming a semiconductor structure as claimed in claim 3 , wherein an angle between the slope sidewall and a bottom surface of the seed layer is in a range from about 20° to about 80°.5. The method for forming a semiconductor structure as claimed in claim 1 , wherein the conductive pillar is directly formed on the seed layer.6. The method for forming a semiconductor structure as claimed in claim 1 , further ...

SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME

The present disclosure provides a semiconductor package, including a substrate, an active region in the substrate, an interconnecting layer over the active region, a conductive pad over the interconnecting layer, surrounded by a dielectric layer. At least two discrete regions of the conductive pad are free from coverage of the dielectric layer. A method of manufacturing the semiconductor package is also disclosed. 1. A semiconductor package , comprising:a substrate;an active region in the substrate;an interconnecting layer over the active region;a conductive pad over the interconnecting layer, surrounded by a dielectric layer, wherein at least two discrete regions of the conductive pad are free from coverage of the dielectric layer: anda conductive bump over the conductive pad and the dielectric layer, the conductive bump comprises at least two protrusions separated by the dielectric layer.2. The semiconductor package of claim 1 , wherein the dielectric layer comprises:a passivation layer having a portion at a same level with the conductive pad; anda polymer layer stacking over the passivation layer.3. The semiconductor package of claim 1 , wherein the conductive bump being in contact with the conductive pad at the at least two discrete regions.4. The semiconductor package of claim 1 , further comprising:an under bump metallurgy (UBM) layer over the conductive pad and the dielectric layer, the UBM layer being in contact with the conductive pad at the at least two discrete regions, wherein the protrusions of the conductive bump are in contact with the UBM layer over the at least two discrete regions of the conductive pad.5. The semiconductor package of claim 1 , wherein the at least two discrete regions comprise different sizes from a top view perspective.6. The semiconductor package of claim 3 , further comprising:a solder bump at an opposite end of the conductive bump contacting the conductive pad; anda package substrate connected to the solder bump.7. The ...

Semiconductor structure and method of manufacturing thereof

A semiconductor structure and a method of manufacturing thereof are provided. The semiconductor includes a semiconductor integrated circuit device and a redistribution layer structure. The semiconductor integrated circuit device has a top surface and an electrode on the top surface. The redistribution layer structure is formed on the top surface. The redistribution layer structure includes an oxide layer, a nitride layer, a dielectric layer, a groove and a through via. The oxide layer and the nitride layer are formed on the top surface. The dielectric layer is formed on the nitride layer. The groove is formed at a topside of the dielectric layer and overlaps the electrode. The through via is formed at a bottom of the groove and extends within the electrode through the dielectric layer, the nitride layer and the oxide layer. The through via and the groove are filled with a conductive material.

INTEGRATED CIRCUIT COMPONENT AND PACKAGE STRUCTURE HAVING THE SAME

An integrated circuit component includes a semiconductor substrate, conductive pads, a passivation layer and conductive vias. The semiconductor substrate has an active surface. The conductive pads are located on the active surface of the semiconductor substrate and electrically connected to the semiconductor substrate, and the conductive pads each have a contact region and a testing region, where in each of the conductive pads, an edge of the contact region is in contact with an edge of the testing region. The passivation layer is located on the semiconductor substrate, where the conductive pads are located between the semiconductor substrate and the passivation layer, and the testing regions and the contact regions of the conductive pads are exposed by the passivation layer. The conductive vias are respectively located on the contact regions of the conductive pads. 1. An integrated circuit component , comprising:a semiconductor substrate having an active surface;conductive pads, located on the active surface of the semiconductor substrate, electrically connected to the semiconductor substrate, and each having a contact region and a testing region, wherein in each of the conductive pads, an edge of the contact region is in contact with an edge of the testing region;a passivation layer, located on the semiconductor substrate, wherein the conductive pads are located between the semiconductor substrate and the passivation layer, and the testing regions and the contact regions of the conductive pads are exposed by the passivation layer; andconductive vias, respectively located on the contact regions of the conductive pads.2. The integrated circuit component of claim 1 , further comprising:a post-passivation layer, located on the semiconductor substrate, wherein the testing regions of the conductive pads exposed by the passivation layer are covered by the post-passivation layer, and the contact regions of the conductive pads exposed by the passivation layer are exposed ...

Semiconductor device with pads of enhanced moisture blocking ability

A semiconductor device is provided having a pad with an improved moisture blocking ability. The semiconductor device has: a circuit portion including a plurality of semiconductor elements formed on a semiconductor substrate; lamination of insulator covering the circuit portion, including a passivation film as an uppermost layer having openings; ferro-electric capacitors formed in the lamination of insulator; wiring structure formed in the lamination of insulator and connected to the semiconductor elements and the ferro-electric capacitors; pad electrodes connected to the wiring structure, formed in the lamination of insulator and exposed in the openings of the passivation film; a conductive pad protection film, including a Pd film, covering each pad electrode via the opening of the passivation film, and extending on the passivation film; and stud bump or bonding wire connected to the pad electrode via the conductive pad protection film.

SEMICONDUCTOR PACKAGE

The present disclosure provides a semiconductor package including a semiconductor chip and a package substrate. The semiconductor chip includes a substrate, a plurality of conductive pads in the substrate, and a plurality of conductive bumps. Each of the conductive bumps is over corresponding conductive pad. At least one of the conductive bumps proximity to an edge of the semiconductor chip is in contact with at least two discrete regions of the corresponding conductive pad. The package substrate has a concave surface facing the semiconductor chip and joining the semiconductor chip through the plurality of conductive bumps. 1. A semiconductor package , comprising: a substrate;', 'a plurality of conductive pads in the substrate; and', 'a plurality of conductive bumps, each over corresponding conductive pad, at least one of the conductive bumps proximity to an edge of the semiconductor chip being in contact with at least two discrete regions of the corresponding conductive pad; and, 'a semiconductor chip, comprisinga package substrate having a concave surface facing the semiconductor chip and joining the semiconductor chip through the plurality of conductive bumps.2. The semiconductor package of claim 1 , wherein one of the at least two discrete regions closer to a center of the semiconductor chip is larger than another one of the at least two discrete regions closer to the edge of the semiconductor chip.3. The semiconductor package of claim 1 , wherein the conductive pads having at least two discrete regions are ellipses from top view perspective.4. The semiconductor package of claim 3 , wherein the two discrete regions are on a major axis of each of the conductive pads from top view perspective.5. The semiconductor package of claim 1 , further comprising:an active region in the substrate; andan interconnecting layer over the active region and in contact with a bottom of each of the conductive pads.6. The semiconductor package of claim 5 , further comprising a ...

Polymer Layers Embedded with Metal Pads for Heat Dissipation

An integrated circuit structure includes a metal pad, a passivation layer including a portion over the metal pad, a first polymer layer over the passivation layer, and a first Post-Passivation Interconnect (PPI) extending into to the first polymer layer. The first PPI is electrically connected to the metal pad. A dummy metal pad is located in the first polymer layer. A second polymer layer is overlying the first polymer layer, the dummy metal pad, and the first PPI. An Under-Bump-Metallurgy (UBM) extends into the second polymer layer to electrically couple to the dummy metal pad. 1. An integrated circuit structure comprising:a metal pad;a passivation layer comprising a portion over the metal pad;a first polymer layer comprising a portion over the passivation layer;a dummy metal pad in the first polymer layer, wherein the dummy metal pad is electrically floating;a second polymer layer over the first polymer layer and the dummy metal pad; anda first Under-Bump-Metallurgy (UBM) extending into the second polymer layer to electrically couple to the dummy metal pad.2. The integrated circuit structure of claim 1 , wherein a top surface and a bottom surface of the dummy metal pad are coplanar with a top surface and a bottom surface claim 1 , respectively claim 1 , of the first polymer layer.3. The integrated circuit structure of further comprising:a package component comprising a surface metallic feature; anda solder region bonding the surface metallic feature in the package component to the first UBM, wherein the dummy metal pad, the solder region, and the surface metallic feature in combination are electrically floating.4. The integrated circuit structure of further comprising:a third polymer layer between the first polymer layer and the second polymer layer; anda Post-Passivation Interconnect (PPI) extending into to the third polymer layer, wherein the PPI electrically couples the dummy metal pad to the first UBM.5. The integrated circuit structure of further comprising: ...

Semiconductor chip, display panel, and electronic device

A semiconductor chip, a display device or an electronic device includes a substrate, one or more conductive pads disposed on the substrate, and one or more bumps electrically connected to the one or more conductive pads, in which the one or more bumps includes a metal core, a polymer layer disposed over a surface of the metal core, and a conductive coating layer disposed over a surface of the polymer layer and electrically connected to the one or more conductive pads.

SEMICONDUCTOR PACKAGING AND MANUFACTURING METHOD THEREOF

The present disclosure provides a semiconductor package, which includes a substrate, a passivation layer, a post-passivation interconnect (PPI) having a top surface; and a conductive structure. The top surface of the PPI includes a first region receiving the conductive structure, and a second region surrounding the first region. The second region includes metal derivative transformed from materials made of the first region. The present disclosure provide a method of manufacturing a semiconductor package, including forming a first flux layer covering a portion of a top surface of a PPI; transforming a portion of the top surface of the PPI uncovered by the first flux layer into a metal derivative layer; removing the first flux layer; forming a second flux layer on the first region of the PPI; dropping a solder ball on the flux layer; and forming electrical connection between the solder ball and the PPI. 1. A method of manufacturing a semiconductor package , comprising:patterning a metal derivative in a second region of a post-passivation interconnect (PPI);forming a flux layer in a first region of the PPI, wherein the first region is surrounded by the second region;dropping a solder ball on the flux layer; andforming electrical connection between the solder ball and the PPI.2. The method of manufacturing a semiconductor package in claim 1 , wherein the to patterning the metal derivative in the second region of the PPI further comprising forming a mask layer over the PPI.3. The method of manufacturing a semiconductor package in claim 2 , wherein the forming the mask layer over the PPI comprises forming a mask layer on the PPI.4. The method of manufacturing a semiconductor package in claim 2 , wherein the forming the mask layer over the PPI comprises positioning a first stencil plate over the PPI.5. The method of manufacturing a semiconductor package in claim 1 , wherein the patterning the metal derivative in the second region of the PPI comprises an oxygen plasma ...

SEMICONDUCTOR DEVICE STRUCTURE AND MANUFACTURING METHOD

A semiconductor device structure and a manufacturing method are provided. The semiconductor device structure includes a semiconductor substrate and a dielectric layer over the semiconductor substrate. The semiconductor device structure also includes a conductive trace over the dielectric layer. The semiconductor device structure further includes a conductive feature over the conductive trace, and a width of the conductive feature is substantially equal to or larger than a maximum width of the conductive trace. In addition, the semiconductor device structure includes a conductive bump over the conductive feature. 1. A structure , comprising:a substrate;a conductive trace disposed over the substrate, the conductive trace including a first segment and a second segment that each extend in a first direction, wherein the first segment and the second segment have substantially equal dimensions measured in a second direction;a conductive layer disposed over the first segment, but not over the second segment, of the conductive trace, wherein a dimension of the conductive layer measured in the second direction is greater than the dimension of the first segment of the conductive trace; anda conductive bump disposed over the conductive layer.2. The structure of claim 1 , wherein the conductive bump is in direct contact with the conductive layer.3. The structure of claim 2 , wherein the conductive bump is separated from a sidewall of the conductive trace by the conductive layer.4. The structure of claim 1 , wherein the conductive bump and the conductive layer have similar top view profiles.5. The structure of claim 4 , wherein the conductive bump and the conductive layer each have rounded top view profiles.6. The structure of claim 1 , wherein the conductive trace is free of having a passivation layer formed thereon.7. The structure of claim 1 , wherein an entirety of the conductive trace has a uniform dimension measured in the second direction.8. The structure of claim 1 , ...

Three-dimensional memory device having bonding structures connected to bit lines and methods of making the same

Three-dimensional memory devices in the form of a memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack, in which each of the memory stack structures includes a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. Bit lines are electrically connected to an end portion of a respective one of the vertical semiconductor channels. Bump connection via structures contact a top surface of a respective one of the bit lines, in which each of the bump connection via structures has a greater lateral dimension along a lengthwise direction of the bit lines than along a widthwise direction of the bit lines. Metallic bump structures of another semiconductor die contact respective ones of the bump connection via structures to make respective electrical connections between the two dies.

SEMICONDUCTOR DEVICE PACKAGES AND METHODS OF MANUFACTURING THE SAME

A semiconductor device package includes a connection structure having a first portion and a second portion extending from the first portion, the second portion having a width less than the first portion; and a dielectric layer surrounding the connection structure, wherein the dielectric layer and the second portion of the connection structure defines a space. 1. A semiconductor device package , comprising:a connection structure having a first portion and a second portion extending from the first portion, the second portion having a width less than the first portion; anda dielectric layer surrounding the connection structure,wherein the dielectric layer and the second portion of the connection structure defines a space, the second portion comprises a third interconnection layer and a fourth interconnection layer, the third interconnection layer is formed on the fourth interconnection layer, and at least one portion of a lateral surface of the third interconnection layer is exposed to the space.2. The semiconductor device package of claim 1 , wherein the first portion of the connection structure comprises a first interconnection layer claim 1 , and wherein the first interconnection layer has a cup structure.3. The semiconductor device package of claim 1 , wherein the first portion of the connection structure comprises a first interconnection layer claim 1 , and wherein the first interconnection layer has a U shape or a U shape-like structure.4. The semiconductor device package of or claim 1 , wherein the first portion of the connection structure comprises a second interconnection layer surrounding the first interconnection layer.5. The semiconductor device package of claim 3 , wherein a first part of the first portion of the connection structure is covered by the dielectric layer and a second part of the first portion of the connection structure is exposed by the dielectric layer.6. The semiconductor device package of claim 5 , wherein the second part of the first ...

Package with ubm and methods of forming

Package structures and methods of forming package structures are discussed. A package structure, in accordance with some embodiments, includes an integrated circuit die, an encapsulant at least laterally encapsulating the integrated circuit die, a redistribution structure on the integrated circuit die and the encapsulant, a connector support metallization coupled to the redistribution structure, a dummy pattern, a second dielectric layer, and an external connector on the connector support metallization. The redistribution structure comprises a first dielectric layer having a first surface disposed distally from the encapsulant and the integrated circuit die. The dummy pattern is on the first surface of the first dielectric layer and around the connector support metallization. The second dielectric layer is on the first surface of the first dielectric layer and on at least a portion of the dummy pattern. The second dielectric layer does not contact the connector support metallization.

DRIVING SUBSTRATE AND MANUFACTURING METHOD THEREOF, AND MICRO LED BONDING METHOD

The present disclosure provides a driving substrate and a manufacturing method thereof, and a micro LED bonding method. The driving substrate includes: a base substrate; a driving function layer provided on the base substrate, and including a plurality of driving thin film transistors and a plurality of common electrode lines; a pad layer including a plurality of pads provided on a side of the driving function layer away from the base substrate, each pad including a pad body and a microstructure of hard conductive material provided on a side of the pad body away from the base substrate; and a plurality of buffer structures provided on the side of the driving function layer away from the base substrate, each buffer structure surrounding a portion of a corresponding microstructure close to the base substrate, and a height of the buffer structure being lower than a height of the microstructure. 1. A driving substrate , comprising:a base substrate;a driving function layer provided on the base substrate, the driving function layer comprising a plurality of driving thin film transistors and a plurality of common electrode lines;a pad layer comprising a plurality of pads provided on a side of the driving function layer away from the base substrate, each pad comprising a pad body and a microstructure of hard conductive material provided on a side of the pad body away from the base substrate; anda plurality of buffer structures provided on the side of the driving function layer away from the base substrate, each buffer structure surrounding a portion of a corresponding microstructure close to the base substrate, and a height of the buffer structure being lower than a height of the microstructure.2. The driving substrate according to claim 1 , wherein each driving thin film transistor in the driving function layer comprises a gate claim 1 , a first electrode and a second electrode claim 1 , the pad layer comprises a plurality of first pads and a plurality of second pads claim ...

LATERALLY EXTENDED CONDUCTIVE BUMP BUFFER

A semiconductor device includes: a conductive structure, a conductive bump extending into the conductive structure and contacting the conductive structure along a first surface, the conductive bump configured to interface with an external semiconductor device at a second surface opposite the first surface, the conductive bump being wider along the first surface than the second surface. 1. A semiconductor device , comprising:a conductive structure,a conductive bump extending into the conductive structure and contacting the conductive structure with a buffer material along a first surface, the conductive bump with a head material configured to interface with an external semiconductor device at a second surface opposite the first surface, the conductive bump being wider along the first surface with the buffer material contacting and laterally surrounded by the conductive structure than along the second surface with the head material.2. The semiconductor device of claim 1 , wherein the conductive bump extends into the conductive structure along an isotropic recess that extends into the conductive structure.3. The semiconductor device of claim 2 , wherein the conductive bump is formed in an anisotropic recess formed using anisotropic etching.4. The semiconductor device of claim 1 , wherein the conductive bump comprises nickel at the first surface and gold at the second surface.5. The semiconductor device of claim 4 , wherein the conductive structure comprises copper.6. The semiconductor device of claim 1 , wherein the conductive bump comprises sidewalls that are nonlinear.7. The semiconductor device of claim 1 , wherein the conductive bump comprises sidewalls that include a corner.8. A semiconductor device claim 1 , comprising:a horizontal conductive structure;a layer overlaying the horizontal conductive structure; and a head material, and', 'a buffer material adjoining the head material, the buffer material extending into and laterally surrounded by the horizontal ...

Chip structure, packaging structure and manufacturing method for chip structure

The present disclosure provides a chip structure, a packaging structure and a manufacturing method for the chip structure. The chip structure includes at least one chip body, each of which includes at least one radio frequency front-end device; the chip structure further includes a redistribution layer stacked on the chip body and at least one pin on the redistribution layer; each radio frequency front-end device corresponds to one pin, which is electrically connected to the radio frequency front-end device through an electrical connector extending through the redistribution layer; an extending direction of the radio frequency front-end device is consistent with an extending direction of the pin corresponding to the radio frequency front-end device; a surface of the pin distal to the redistribution layer is a first plane. In the present disclosure, with the first plane, the chip may be directly and electrically connected to a flexible circuit board.

Semiconductor device and manufacturing method thereof

A method of manufacturing a semiconductor structure includes receiving a substrate including a die pad disposed thereon; disposing a passivation over the substrate and around the die pad; disposing a polymer over the passivation; forming a post passivation interconnect (PPI) including an elongated portion and a via portion contacting with the die pad; depositing a metallic paste on the elongated portion of the PPI by a stencil; disposing a conductive bump over the metallic paste; and disposing a molding over the PPI and around the metallic paste and the conductive bump.

ELECTRONIC APPARATUS

An electronic apparatus includes first and second packages. The first package includes a first semiconductor chip between opposing first and second surfaces of the first package, a plurality of terminals on the first semiconductor chip facing a first direction that is perpendicular to the first and second surface, the terminals including first input/output terminals and a second input/output terminal, and a plurality of bumps that are electrically connected to the plurality of first input/output terminals at positions that are directly below the first semiconductor chip in the first direction. The second package includes a second semiconductor chip provided on the second surface of the first package, a wire that electrically connects the second semiconductor chip to a conductor that is electrically connected to the second input/output terminal, and coating resin that covers the second surface of the first package, the second semiconductor chip and the wire. 1. An electronic apparatus comprising:a first package including a first surface that faces a first direction, a second surface that is opposite to the first surface, a first semiconductor chip that is provided between the first surface and the second surface, a plurality of first terminals provided on the first semiconductor chip and facing the first direction, a second terminal that is provided on the first semiconductor chip and faces the first direction, a power supply terminal, a first interlayer connection conductor that is spaced from the first semiconductor chip in a second direction intersecting the first direction, a first connection conductor that connects the second terminal and the first interlayer connection conductor to each other, a second connection conductor at least a part of which is provided on the second surface and that is connected to the first interlayer connection conductor, a plurality of first bumps that are electrically connected to the plurality of first terminals and protrude from ...

INTERCONNECT STRUCTURES FOR FINE PITCH ASSEMBLY OF SEMICONDUCTOR STRUCTURES

A semiconductor structure includes a substrate having first and second opposing surfaces and a plurality of electrical connections extending between the first and second surfaces. The semiconductor structure also includes one or more interconnect pads having first and second opposing surfaces and one or more sides. The first surface of each one of the interconnect pads is disposed over or beneath select portions of at least the second surface of the substrate and is electrically coupled to select ones of the plurality of electrical connections. The semiconductor structure additionally includes an isolating layer having first and second opposing surfaces and openings formed in select portions of the isolating layer extending between the second surface of the isolating layer and the second surfaces of the interconnect pads. A corresponding method for fabricating a semiconductor structure is also provided. 1. A method for fabricating a semiconductor structure , comprising:providing a substrate having first and second opposing surfaces and a plurality of electrical connections extending between the first and second surfaces;providing one or more interconnect pads having first and second opposing surfaces and one or more sides, wherein the first surface of each one of the interconnect pads is disposed over or beneath select portions of at least the second surface of the substrate and is electrically coupled to select ones of the plurality of electrical connections;applying an isolating layer having first and second opposing surfaces, wherein the first surface of the isolating layer is disposed over the second surface of the substrate and the second surfaces and one or more sides of the interconnect pads;forming openings having a predetermined shape in select portions of the isolating layer extending between the second surface of the isolating layer and the first surface of the isolating layer;providing one or more pad interconnects having a pad portion and an ...

Pre-conductive array disposed on target circuit substrate and conductive structure array thereof

A pre-conductive array disposed on a target circuit substrate comprises a plurality of conductive electrode groups disposed on the target circuit substrate, and at least a conductive particle dispose on each of conductive electrodes of a part or all of the conductive electrode groups. The at least a conductive particle and the corresponding conductive electrode form a pre-conductive structure, and the pre-conductive structures form the pre-conductive array.

Wafer Level Chip Scale Package Device with One or More Pre-solder Layers and Manufacturing Method Thereof

The present invention discloses a method for manufacturing a wafer level chip scale package device with one or more pre-solder layers, and a wafer level chip scale package device made thereby. The device includes: a chip including at least one bonding pad; a UBM layer disposed on the bonding pad; at least one pre-solder layer disposed on the UBM layer; and a bump melted and combined with the pre-solder layer. The device may include two pre-solder layers. 113.-. (canceled)14. A method for manufacturing a wafer level chip scale package device , comprising:providing a chip having at least one bonding pad;forming a UBM layer on the bonding pad;forming a pre-solder layer on the UBM layer; andmelting and combining a bump and the pre-solder layer, whereby the pre-solder layer is melted and combined together with the bump to form one ball as an I/O contact.15. The method for manufacturing a wafer level chip scale package device of claim 14 , further comprising: forming a high melting point pre-solder layer between the UBM layer and the pre-solder layer claim 14 , wherein the melting point of the high melting point pre-solder layer is higher than the melting point of the pre-solder layer.16. The method for manufacturing a wafer level chip scale package device of claim 14 , further comprising:forming a barrier layer on the bonding pad; andforming a seed layer between the barrier layer and the UBM layer.17. The method for manufacturing a wafer level chip scale package device of claim 14 , wherein the bump is a solder ball.18. The method for manufacturing a wafer level chip scale package device of claim 17 , wherein the material of the pre-solder layer includes one selected from the group consisting of tin claim 17 , an alloy of tin and lead claim 17 , an alloy of tin and zinc claim 17 , an alloy of tin and copper claim 17 , and an alloy of tin claim 17 , silver and copper.19. The method for manufacturing a wafer level chip scale package device of claim 17 , wherein the ...

Package With UBM and Methods of Forming

Package structures and methods of forming package structures are discussed. A package structure, in accordance with some embodiments, includes an integrated circuit die, an encapsulant at least laterally encapsulating the integrated circuit die, a redistribution structure on the integrated circuit die and the encapsulant, a connector support metallization coupled to the redistribution structure, a dummy pattern, a second dielectric layer, and an external connector on the connector support metallization. The redistribution structure comprises a first dielectric layer having a first surface disposed distally from the encapsulant and the integrated circuit die. The dummy pattern is on the first surface of the first dielectric layer and around the connector support metallization. The second dielectric layer is on the first surface of the first dielectric layer and on at least a portion of the dummy pattern. The second dielectric layer does not contact the connector support metallization. 1. A method comprising:encapsulating an integrated circuit die with an encapsulant;forming a redistribution structure on the integrated circuit die and the encapsulant, the redistribution structure comprising a first dielectric layer having a first surface distal from the integrated circuit die and the encapsulant;forming an under ball metallization (UBM) and a dummy pattern on the redistribution structure, the dummy pattern surrounding the UBM on the first surface of the first dielectric layer, the dummy pattern being electrically isolated; andforming a second dielectric layer on the first surface of the first dielectric layer and at least a portion of the dummy pattern, wherein after the forming the second dielectric layer, the second dielectric layer is physically spaced apart from the UBM, wherein the second dielectric layer covers an exterior portion of the dummy pattern laterally distal from the UBM and exposes an interior portion of the dummy pattern proximate the UBM.2. The ...

MULTILAYERS OF NICKEL ALLOYS AS DIFFUSION BARRIER LAYERS

A structure for a semiconductor device includes a copper (Cu) layer and a first nickel (Ni) alloy layer with a Ni grain size a. The structure also includes a second Ni alloy layer with a Ni grain size a, wherein ax.4. The method of claim 1 , wherein the copper layer is over a pad of the die.5. The method of claim 1 , wherein the first nickel alloy layer and the second nickel alloy layer include one of NiCe claim 1 , NiMoW claim 1 , and NiWCe.6. A method of forming an integrated circuit package claim 1 , the method ...

Circuit device, oscillator, electronic apparatus, and moving object

A circuit device includes a first pad and a second pad that are disposed in a first pad disposition region along a first side; a third pad and a fourth pad that are disposed in a second pad disposition region along a second side which faces the first side; and a first to fourth electrostatic protection circuits that are disposed in a circuit disposition region between the first pad disposition region and the second pad disposition region and are connected to the first to fourth pads.

PILLAR STRUCTURE AND MANUFACTURING METHOD THEREOF

A pillar structure is disposed on a substrate. The pillar structure includes a pad, a metal wire bump, a metal wire, and a metal plating layer. The pad is disposed on the substrate. The metal wire bump is disposed on the pad. The metal wire is connected to the metal wire bump. The metal wire extends in a first extension direction, the substrate extends in a second extension direction, and the first extension direction is perpendicular to the second extension direction. The metal plating layer covers the pad and completely encapsulates the metal wire bump and the metal wire. 1. A pillar structure disposed on a substrate and comprising:a pad disposed on the substrate;a metal wire bump disposed on the pad;a metal wire connected to the metal wire bump, the metal wire and the metal wire bump being integrally formed, wherein the metal wire extends in a first extension direction with the same diameter, the substrate extends in a second extension direction, and the first extension direction is perpendicular to the second extension direction, wherein a diameter of the metal wire is less than a width of the metal wire bump; anda metal plating layer covering the pad and completely encapsulating the metal wire bump and the metal wire.2. The pillar structure as recited in claim 1 , wherein an orthogonal projection of the metal wire bump on the substrate and an orthogonal projection of the pad on the substrate are completely overlapped claim 1 , and an area of the orthogonal projection of the metal wire bump on the substrate is smaller than an area of the orthogonal projection of the pad on the substrate.3. The pillar structure as recited in claim 1 , wherein a length of the metal wire is ⅘ a length of the metal plating layer.4. The pillar structure as recited in claim 1 , wherein a diameter of the metal wire is within a range from 15 micrometers to 200 micrometers.5. The pillar structure as recited in claim 1 , wherein he metal plating layer covers an upper surface of the pad ...

Multilayers of nickel alloys as diffusion barrier layers

A structure for a semiconductor device includes a copper (Cu) layer and a first nickel (Ni) alloy layer with a Ni grain size a 1 . The structure also includes a second Ni alloy layer with a Ni grain size a 2 , wherein a 1 <a 2 . The first Ni alloy layer is between the Cu layer and the second Ni alloy layer. The structure further includes a tin (Sn) layer. The second Ni alloy layer is between the first Ni alloy layer and the Sn layer.

BACKPLANE STRUCTURE AND PROCESS FOR MICRODRIVER AND MICRO LED

Micro LED and microdriver chip integration schemes are described. In an embodiment a microdriver chip includes a plurality of trenches formed in a bottom surface of the microdriver chip, with each trench surrounding a conductive stud extending below a bottom surface of the microdriver chip body. Integration schemes are additionally described for providing electrical connection to conductive terminal contacts and micro LEDs bonded to a display substrate and adjacent to a microdriver chip. 1. A chip comprising:a device layer;a passivation layer below the device layer, the passivation layer including a bottom surface;a plurality of trenches in the passivation layer;a plurality of conductive studs within the plurality of trenches;wherein each conductive stud is surrounded by sidewalls of a corresponding trench such that a reservoir is formed between the conductive stud and the sidewalls of the corresponding trench; andeach conductive stud includes a bottom surface that is below the bottom surface of the passivation layer.2. The chip of claim 1 , further comprising an array of landing pads claim 1 , and each stud extends from a landing pad.3. The chip of claim 2 , further comprising a barrier layer formed on the bottom surface of the passivation layer and on the sidewalls of the plurality of trenches.4. The chip of claim 3 , wherein the barrier layer is formed on the plurality of landing pads.5. The chip of claim 4 , wherein the barrier layer is thinner than the passivation layer.6. A display comprising:a display substrate including an array of contact pads;an array of LEDs bonded to the display substrate;an array of chips bonded to the display substrate;wherein each chip is electrically connected to one or more LEDs to drive the one or more LEDs; a passivation layer including a plurality of trenches;', 'a plurality of conductive studs within the plurality of trenches and extended below a bottom surface of the passivation layer;', 'wherein each conductive stud is bonded ...

Method for bonding semiconductor components

A method of bonding semiconductor components is described. In one aspect a first component, for example a semiconductor die, is bonded to a second component, for example a semiconductor wafer or another die, by direct metal-metal bonds between metal bumps on one component and corresponding bumps or contact pads on the other component. In addition, a number of solder bumps are provided on one of the components, and corresponding contact areas on the other component, and fast solidified solder connections are established between the solder bumps and the corresponding contact areas, without realizing the metal-metal bonds. The latter metal-metal bonds are established in a heating step performed after the soldering step. This enables a fast bonding process applied to multiple dies bonded on different areas of the wafer and/or stacked one on top of the other, followed by a single heating step for realizing metal-metal bonds between the respective dies and the wafer or between multiple stacked dies. The method allows to improve the throughput of the bonding process, as the heating step takes place only once for a plurality of dies and/or wafers.

Semiconductor Device Structure and Manufacturing Method

A semiconductor device structure and a manufacturing method are provided. The semiconductor device structure includes a semiconductor substrate and a dielectric layer over the semiconductor substrate. The semiconductor device structure also includes a conductive trace over the dielectric layer. The semiconductor device structure further includes a conductive feature over the conductive trace, and a width of the conductive feature is substantially equal to or larger than a maximum width of the conductive trace. In addition, the semiconductor device structure includes a conductive bump over the conductive feature. 1. A structure , comprising:a first substrate;a dielectric layer disposed over the first substrate;a first conductive trace disposed over the dielectric layer;an under-bump metallization (UBM) element disposed over the first conductive trace; anda conductive bump disposed over the UBM element.2. The structure of claim 1 , further comprising a conductive line embedded in the dielectric layer claim 1 , wherein the first conductive trace is electrically coupled to the conductive line.3. The structure of claim 1 , wherein a sidewall of the first conductive trace is aligned with a sidewall of the UBM element.4. The structure of claim 1 , wherein a width of the first conductive trace is substantially equal to a width of the UBM element.5. The structure of claim 1 , wherein the conductive bump is disposed on a sidewall of the UBM element but not on a sidewall of the first conductive trace.6. The structure of claim 1 , wherein a portion of the UBM element is disposed on a sidewall of the first conductive trace.7. The structure of claim 1 , further comprising:a second substrate; anda second conductive trace disposed over the second substrate;wherein the second conductive trace is bonded to the conductive bump.8. The structure of claim 7 , further comprising: a protection material that surrounds the first conductive trace claim 7 , the UBM element claim 7 , the ...

SEMICONDUCTOR DEVICE ASSEMBLY WITH DIE SUPPORT STRUCTURES

A semiconductor device assembly is provided. The assembly includes a first semiconductor die and a second semiconductor die disposed over the first semiconductor die. The assembly further includes a plurality of die support structures between the first and second semiconductor dies and a plurality of interconnects between the first and second semiconductor dies. Each of the plurality of die support structures includes a stand-off pillar and a stand-off pad having a first bond material with a first solder joint thickness between them. Each of the plurality of interconnects includes a conductive pillar and a conductive pad having a second bond material with a second solder joint thickness between them. The first solder joint thickness is less than the second solder joint thickness. 1. A semiconductor package comprising a plurality of dies arranged in a stack ,wherein adjacent ones of the plurality of dies are separated by a plurality of interconnects and a plurality of die support structures,wherein each of the plurality of die support structures includes a stand-off pillar and a stand-off pad with a first distance between the stand-off pillar and the stand-off pad,wherein each of the plurality of interconnects includes a conductive pillar, a conductive pad, and a bond material with a solder joint thickness between the conductive pillar and the conductive pad, andwherein the first distance is less than the solder joint thickness.2. The semiconductor package of claim 1 , wherein the plurality of die support structures includes die support structures disposed about a periphery of the semiconductor package.3. The semiconductor package of claim 1 , wherein the plurality of die support structures includes die support structures disposed in a medial region of the semiconductor device assembly.4. The semiconductor package of claim 1 , wherein the plurality of dies includes more than two dies.5. The semiconductor package of claim 1 , wherein the plurality of dies includes at ...

Semiconductor Packages and Methods of Forming Same

In an embodiment, a package includes a first package structure including a first die having a first active side and a first back-side, the first active side including a first bond pad and a first insulating layer a second die bonded to the first die, the second die having a second active side and a second back-side, the second active side including a second bond pad and a second insulating layer, the second active side of the second die facing the first active side of the first die, the second insulating layer being bonded to the first insulating layer through dielectric-to-dielectric bonds, and a conductive bonding material bonded to the first bond pad and the second bond pad, the conductive bonding material having a reflow temperature lower than reflow temperatures of the first and second bond pads. 1. A package comprising: a first die having a first active side and a first back-side, the first active side comprising a first bond pad and a first insulating layer;', 'a second die bonded to the first die, the second die having a second active side and a second back-side, the second active side comprising a second bond pad and a second insulating layer, the second active side of the second die facing the first active side of the first die, the second insulating layer spaced apart from the first insulating layer;', 'a conductive bonding material bonded to the first bond pad and the second bond pad, the conductive bonding material having a reflow temperature lower than reflow temperatures of the first bond pad and the second bond pad;', 'a sealing layer on the first active side of the first die and on a sidewall of the second die, the sealing layer sealing a gap between the first insulating layer and the second insulating layer; and', 'a first encapsulant on the sealing layer., 'a first package structure comprising2. The package of claim 1 , wherein the first bond pad is recessed into the first insulating layer.3. The package of claim 1 , wherein the first active side ...

System and Method for an Improved Fine Pitch Joint

Presented herein are an interconnect and method for forming the same, the method comprising forming an interconnect on a mounting surface of a mounting pad disposed on a first surface of a first substrate, the interconnect comprising a conductive material, optionally solder or metal, the interconnect avoiding the sides of the mounting pad. A molding compound is applied to the first surface of the first substrate and molded around the interconnect to covering at least a lower portion of the interconnect and a second substrate may be mounted on the interconnect. The interconnect may comprise an interconnect material disposed between a first and second substrate and a molding compound disposed on a surface of the first substrate, and exposing a portion of the interconnect. A sidewall of the interconnect material contacts the mounting pad at an angle less than about 30 degrees from a plane perpendicular to the first substrate.

Semiconductor structure and method of manufacturing the same

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes: a semiconductor chip; a substrate facing an active surface of the semiconductor chip; and a conductive bump extending from the active surface of the semiconductor chip toward the substrate, wherein the conductive bump comprises: a plurality of bump segments comprising a first group of bump segments and a second group of bump segments, wherein each bump segment comprises the same segment height in a direction orthogonal to the active surface of the semiconductor chip, and each bump segment comprises a volume defined by the multiplication of the segment height with the average cross-sectional area of the bump segment; wherein the ratio of the total volume of the first group of bump segments to the total volume of the second group of bump segments is between about 0.03 and about 0.8.

MICRO-CONNECTION STRUCTURE AND MANUFACTURING METHOD THEREOF

A micro-connection structure is provided. The micro-connection structure includes an under bump metallurgy (UBM) pad, a bump and an insulating ring. The UBM pad is electrically connected to at least one metallic contact of a substrate. The bump is disposed on the UBM pad and electrically connected with the UBM pad. The insulating ring surrounds the bump and the UBM pad. The bump is separate from the insulating ring with a distance and the bump is isolated by a gap between the insulating ring and the bump. 1. A micro-connection structure , comprising:an under bump metallurgy (UBM) pad, electrically connected to at least one metallic contact of a substrate;a bump, disposed on the UBM pad and electrically connected with the UBM pad;an insulating ring surrounding the bump and the UBM pad; anda barrier layer, disposed on and covering the insulating ring,wherein the bump is separate and isolated from the barrier layer and the insulating ring by an open trench between the barrier layer on a sidewall of the insulating ring and the bump.2. The structure of claim 1 , wherein the barrier layer is in contact with the UBM pad without being in contact with the bump.3. (Withdrawn and currently amended) The structure of claim 1 , wherein the UBM pad is located directly on the barrier layer and the barrier layer is not in contact with the bump located on the UBM pad.4. The structure of claim 3 , wherein the barrier layer comprises a tantalum layer conformally covering the insulating ring and an aluminum layer located on the tantalum layer.5. The structure of claim 1 , further comprising a metallic pad disposed directly under the UBM pad and sandwiched between the UBM pad and the at least one metallic contact claim 1 , wherein the UBM pad is electrically connected to the at least one metallic contact through the metallic pad.6. The structure of claim 5 , wherein the UBM pad includes a sidewall portion surrounding the bump and covering a sidewall of the bump claim 5 , and a height of ...

SEMICONDUCTOR DEVICE

A semiconductor device includes a substrate, a contact pad arranged in the substrate, a bump arranged on the contact pad to be electrically connected with the contact pad, an insulating film arranged on the substrate to surround a side surface of the bump and to expose at least a portion of the contact pad to the bump, and a photosensitive film which is formed on the insulating film and comprises a polyimide, wherein the photosensitive film comprises a first region surrounding the side surface of the bump and having a first thickness measured in a vertical direction, and a second region arranged on the first region and having a second thickness thickermeasured in the vertical direction, wherein the second region is spaced apart from the bump in a horizontal direction, and wherein the second thickness is greater than a thickness two times thicker than a difference value between the second thickness and the first thickness. 1. A semiconductor device , comprising:a substrate;a contact pad arranged in the substrate;a bump arranged on the contact pad to be electrically connected with the contact pad;an insulating film arranged on the substrate to surround a side surface of the bump and to expose at least a portion of the contact pad to the bump; anda photosensitive film which is formed on the insulating film and comprises a polyimide, wherein the photosensitive film comprises a first region surrounding the side surface of the bump and having a first thickness measured in a vertical direction, and a second region arranged on the first region and having a second thickness thicker measured in the vertical direction,wherein the second region is spaced apart from the bump in a horizontal direction, andwherein the second thickness is greater than a thickness two times thicker than a difference value between the second thickness and the first thickness.2. The semiconductor device of claim 1 , wherein the first region of the photosensitive film comprises a first opening to allow ...

Semiconductor device and display device having the same

A semiconductor device includes: a semiconductor chip including a substrate having a first surface and a second surface, which are opposite to each other; a through hole penetrating the substrate; a first conductive pad on the first surface of the substrate; a first bump formed over and electrically connected to the first conductive pad; a second conductive pad on the second surface of the substrate; a second bump formed over and electrically connected to the second conductive pad; and a connection electrode buried in the through hole, the connection electrode electrically connecting the first bump and the second bump.

Copper pillar bump having annular protrusion

A copper pillar bump for an electrode pad of a semiconductor chip includes a first copper layer, a first metal layer formed directly on the first copper layer, a second copper layer formed directly on the first metal layer, and a second metal layer formed directly on the second copper layer, wherein the first metal layer and the second metal layer are made of a metal having a different etching rate than copper, wherein an outer perimeter ring of the first metal layer protrudes beyond a lateral surface of the first copper layer, and wherein an outer perimeter ring of the second metal layer protrudes beyond a lateral surface of the second copper layer.

Element chip manufacturing method

Provided is a method of manufacturing a semiconductor chip, the method comprising: preparing a plurality of semiconductor chips, each of which has a surface to which a BG tape is stuck, and a rear surface to which a DAF is stuck, and which are held spaced from each other by the BG tape and the DAF, exposing the DAF between semiconductor chips that are adjacent to each other when viewed from the surface side, by stripping the BG tape from the surface of each of the plurality of semiconductor chips, etching the DAF that is exposed between the semiconductor chips that are adjacent to each other, by irradiating the plurality of semiconductor chips held on the DAF, with plasma.

Semiconductor device and method of manufacturing the same

A semiconductor device includes a substrate, an electrical conductor and a passivation layer. The substrate includes a first surface. The electric conductor is over the first surface of the substrate. The passivation layer is over the first surface of the substrate. The passivation layer includes a first part and a second part. In some embodiments, the first part is in contact with an edge of the electrical conductor, the second part is connected to the first part and apart from the edge of the electrical conductor, and the first part of the passivation layer has curved surface.

SEMICONDUCTOR CHIP WITH REDUCED PITCH CONDUCTIVE PILLARS

Various semiconductor chips and packages are disclosed. In one aspect, an apparatus is provided that includes a semiconductor chip that has a side, and plural conductive pillars on the side. Each of the conductive pillars includes a pillar portion that has an exposed shoulder facing away from the semiconductor chip. The shoulder provides a wetting surface to attract melted solder. The pillar portion has a first lateral dimension at the shoulder. A solder cap is positioned on the pillar portion. The solder cap has a second lateral dimension smaller than the first lateral dimension. 1. An apparatus , comprising: a semiconductor chip having a side; plural conductive pillars on the side , each of the conductive pillars including a pillar portion having an exposed shoulder facing away from the semiconductor chip , the shoulder providing a wetting surface to attract melted solder , the pillar portion having a first lateral dimension at the shoulder; and a solder cap positioned on the pillar portion , the solder cap having a second lateral dimension smaller than the first lateral dimension.2. The apparatus of claim 1 , wherein the pillar portion includes a pillar base portion and a pillar barrier layer positioned on the pillar base portion claim 1 , the solder cap being positioned on the pillar barrier layer.3. The apparatus of claim 2 , comprising an underbump metallization (UBM) seed layer positioned beneath the pillar base portion.4. The apparatus of claim 2 , wherein the pillar base portion has the exposed shoulder.5. The apparatus of claim 1 , wherein the pillar portion comprises a pillar base portion and pillar pedestal portion projecting away from the pillar base portion claim 1 , the pillar base portion having the exposed shoulder.6. The apparatus of claim 5 , wherein the pillar portion and the pillar pedestal comprise the same material.7. The apparatus of claim 1 , comprising a circuit board claim 1 , the semiconductor being mounted on the circuit board.8. An ...

Semiconductor device

A semiconductor device is provided and includes a first pad and a second pad, a first conductive connector and a second conductive connector, a first conductive structure and a second conductive structure. The first conductive connector and the second conductive connector are disposed over the first pad and the second pad. The first conductive structure is electrically connected to the first pad and the first conductive connector, and includes a first portion, a second portion and a connecting portion connecting the first and second portions. The first portion and the second portion are not overlapped in a vertical direction, and the first portion, the connecting portion and the second portion are integrally formed. The second conductive structure is electrically connected to the second pad and the second conductive connector, wherein a portion of the second conductive structure is overlapped with the first conductive structure therebeneath in the vertical direction.

SELF-ALIGNED UNDER BUMP METAL

An integrated circuit including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, with a solder ball formed on the self-aligned under bump metal pad. Processes of forming integrated circuits including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, by a process of forming one or more metal layers on the interconnect level and the dielectric layer, selectively removing the metal from over the dielectric layer, and subsequently forming a solder ball on the self-aligned under bump metal pad. Some examples include additional metal layers formed after the selective removal process, and may include an additional selective removal process on the additional metal layers. 1. An integrated circuit , comprising:an interconnect level in an interconnect region, the interconnect level including a connection pad;a dielectric layer over the interconnect level, such that the dielectric layer overlaps a periphery of the connection pad but not a center portion of the connection pad, and such that a connection opening sidewall is formed at an edge of the dielectric layer over the connection pad;an under bump metal pad on the center portion of the connection pad, such that the under bump metal pad contacts the connection opening sidewall, and such that the under bump metal pad does not extend over any portion of the dielectric layer; anda solder ball on the under bump metal pad, wherein the under bump metal pad includes:at least one of a metal adhesion sub-layer and a metal blocking sub-layer that is continuous along the connection opening sidewall, and is less than one-half as thick as the dielectric layer; anda solder connection sub-layer, wherein the solder connection sub-layer is at least one-half as thick as the dielectric layer.2. The integrated circuit of claim 1 , wherein the at least one of the metal adhesion sub-layer and the ...

FLIP CHIP PACKAGE STRUCTURE AND FABRICATION PROCESS THEREOF

Disclosed herein are various chip packaging structures and methods of fabrication. In one embodiment, a flip chip package structure can include: (i) a pad on a chip; (ii) an isolation layer on the chip and the pad, where the isolation layer includes a through hole that exposes a portion of an upper surface of the pad; (iii) a metal layer on the pad, where the metal layer fully covers the exposed upper surface portion of the pad; and (iv) a bump on the metal layer, where side edges of the bump do not make contact with the isolation layer. 1. (canceled)2. (canceled)3. (canceled)4. (canceled)5. (canceled)6. (canceled)7. (canceled)8. A method of fabricating a flip chip package structure , the method comprising:a) forming a pad on a die;b) depositing an isolation layer on said die and said pad;c) forming a through hole in said isolation layer to selectively expose a portion of said pad;d) depositing a metal layer on said pad to fully cover said exposed portion of said pad; ande) forming a bump on said metal layer, wherein said bump is separated from said isolation layer by gaps.9. The method of claim 8 , wherein said isolation layer comprises a passivation layer.10. The method of claim 8 , wherein said metal layer comprises a first type metal layer for protecting said pad from corrosion.11. The method of claim 8 , wherein said depositing said metal layer comprises:a) sputtering a titanium metal layer on said exposed portion of said pad; andb) sputtering a copper metal layer on said titanium metal layer.12. The method of claim 10 , wherein said first type metal layer comprises a tungsten metal layer.13. The method of claim 8 , wherein said depositing said metal layer comprises:a) sputtering a titanium metal layer on said exposed portion of said pad;b) sputtering a tungsten metal layer on said titanium metal layer; andc) sputtering a copper metal layer on said tungsten metal layer.14. The method of claim 8 , wherein said bump comprises at least one of: tin claim 8 , copper ...

INTEGRATED CIRCUIT COMPONENT AND PACKAGE STRUCTURE HAVING THE SAME

An integrated circuit component includes a semiconductor substrate, conductive pads, a passivation layer and conductive vias. The semiconductor substrate has an active surface. The conductive pads are located on the active surface of the semiconductor substrate and electrically connected to the semiconductor substrate, and the conductive pads each have a contact region and a testing region, where in each of the conductive pads, an edge of the contact region is in contact with an edge of the testing region. The passivation layer is located on the semiconductor substrate, where the conductive pads are located between the semiconductor substrate and the passivation layer, and the testing regions and the contact regions of the conductive pads are exposed by the passivation layer. The conductive vias are respectively located on the contact regions of the conductive pads. 1. A method of manufacturing an integrated circuit component , comprising: providing the semiconductor substrate; and', 'forming the conductive pads on the semiconductor substrate, the conductive pads being electrically connected to the semiconductor substrate and each having a testing region and a contact region comprising a core contact region and a buffer contact region, wherein along one direction, the conductive pads each have a maximum length less than a sum of a maximum length of the testing region and a maximum length of the buffer contact region;, 'providing a wafer comprising a semiconductor substrate and conductive pads on the semiconductor substrate, wherein providing the wafer comprisesforming conductive vias respectively on the contact regions of the conductive pads; anddicing the wafer to form the integrated circuit component.2. The method of claim 1 , prior to forming the conductive vias respectively on the contact regions claim 1 , further comprising:forming a passivation layer over the wafer on the semiconductor substrate to partially cover the conductive pads.3. The method of claim 2 , ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE

A semiconductor device includes a semiconductor substrate, a conductor provided on a main surface of the semiconductor substrate, an insulating layer disposed to cover a surface of the conductor and having a recess from a surface thereof towards the conductor, the recess having an opening provided at a bottom portion of the recess and exposing a portion of the conductor, and an external connection terminal connected to the portion of the conductor exposed from the opening. In a plan view of the semiconductor device, the external connection terminal covers the entire opening, and the entire external connection terminal is within the recess. 1. A semiconductor device , comprising:a semiconductor substrate;a conductor provided on a main surface of the semiconductor substrate;an insulating layer disposed to cover a surface of the conductor and having a recess from a surface thereof towards the conductor, the recess having an opening provided at a bottom portion of the recess and exposing a portion of the conductor; andan external connection terminal connected to the portion of the conductor exposed from the opening, whereinin a plan view of the semiconductor device, the external connection terminal covers the entire opening, and the entire external connection terminal is within the recess.2. The semiconductor device according to claim 1 , wherein the recces has a side face in an area other than the opening claim 1 , the sidewall having a curved inclined surface or a stepwise surface.3. The semiconductor device according to claim 1 , wherein the insulating layer includes a first insulating film and a second insulating film.4. The semiconductor device according to claim 3 , whereinthe first insulating film is disposed to cover the surface of the conductor and has as the opening a first opening that exposes the portion of the conductor, andthe second insulating film is disposed on the first insulating film and has a second opening that exposes a portion of the first ...

DIE ATTACH SURFACE COPPER LAYER WITH PROTECTIVE LAYER FOR MICROELECTRONIC DEVICES

A microelectronic device is formed by thinning a substrate of the microelectronic device from a die attach surface of the substrate, and forming a copper-containing layer on the die attach surface of the substrate. A protective metal layer is formed on the copper-containing layer. Subsequently, the copper-containing layer is attached to a package member having a package die mount area. The protective metal layer may optionally be removed prior to attaching the copper-containing layer to the package member. Alternatively, the protective metal layer may be left on the copper-containing layer when the copper-containing layer is attached to the package member. A structure formed by the method is also disclosed. 1. A microelectronic device , comprising:a substrate having a component surface and a die attach surface located opposite from the component surface;components located proximate to the component surface;a copper-containing layer on the die attach surface, the copper-containing layer being recessed from a lateral perimeter of the die attach surface in its entirety from a bottom view of the microelectronics device; anda die attach material on the copper-containing layer, wherein the copper-containing layer is attached to a package member by the die attach material.2. The microelectronic device of claim 1 , wherein the copper-containing layer is 5 microns to 10 microns thick.3. The microelectronic device of claim 1 , further comprising an intermediate layer between the copper-containing layer and the die attach surface.4. The microelectronic device of claim 3 , wherein the intermediate layer includes titanium.5. The microelectronic device of claim 1 , further comprising a protective metal layer between the copper-containing layer and the die attach material claim 1 , the protective metal layer including at least one metal selected from the group consisting of tin claim 1 , silver claim 1 , and nickel.6. The microelectronic device of claim 1 , wherein the die attach ...

Semiconductor Device and Method of Self-Confinement of Conductive Bump Material During Reflow Without Solder Mask

A semiconductor device has a semiconductor die with a die bump pad. A substrate has a conductive trace with an interconnect site. A conductive bump material is deposited on the interconnect site or die bump pad. The semiconductor die is mounted over the substrate so that the bump material is disposed between the die bump pad and interconnect site. The bump material is reflowed without a solder mask around the die bump pad or interconnect site to form an interconnect structure between the die and substrate. The bump material is self-confined within the die bump pad or interconnect site. The volume of bump material is selected so that a surface tension maintains self-confinement of the bump material substantially within a footprint of the die bump pad and interconnect site. The interconnect structure can have a fusible portion and non-fusible portion. An encapsulant is deposited between the die and substrate.

INTERCONNECT STRUCTURES FOR PREVENTING SOLDER BRIDGING, AND ASSOCIATED SYSTEMS AND METHODS

Semiconductor dies having interconnect structures formed thereon, and associated systems and methods, are disclosed herein. In one embodiment, an interconnect structure includes a conductive material electrically coupled to an electrically conductive contact of a semiconductor die. The conductive material includes a first portion vertically aligned with the conductive contact, and a second portion that extends laterally away from the conductive contact. A solder material is disposed on the second portion of the interconnect structure such that the solder material is at least partially laterally offset from the conductive contact of the semiconductor die. In some embodiments, an interconnect structure can further include a containment layer that prevents wicking or other undesirable movement of the solder material during a reflow process. 1. A method comprising:forming an interconnect structure on a semiconductor die by plating a conductive material onto a surface of the semiconductor die and at least partially over a conductive contact of the semiconductor die so that the interconnect structure is electrically coupled to the conductive contact;forming a containment layer on at least a first portion of a top surface of the interconnect structure; anddisposing a solder material on a second portion of the top surface of the interconnect structure, wherein the second portion of the top surface of the interconnect structure is at least partially laterally offset from the conductive contact of the semiconductor die, and wherein the containment layer is configured to inhibit wicking of the solder material from the second portion to the first portion of the top surface of the interconnect structure.2. The method of wherein forming the interconnect structure includes—plating a first conductive material onto the conductive contact and an insulating material at the surface of the semiconductor die; andplating a second conductive material onto the first conductive material.3. ...

Electronic device and semiconductor device

An electronic device includes a first wiring substrate and a semiconductor device mounted on the first wiring substrate. A plurality of first semiconductor chips and a second semiconductor chip which controls each of the plurality of first semiconductor chips are mounted side by side on a second wiring substrate of the semiconductor device. Further, the plurality of first semiconductor chips are mounted between a first substrate side of the wiring substrate and an extension line of a first chip side of the second semiconductor chip. Furthermore, the first wiring substrate includes a first power line which supplies a first power potential to each of the plurality of first semiconductor chips and a second power line which supplies a second power potential to the second semiconductor chip and has a width larger than that of the first power line. Also, the second power line intersects the first substrate side of the second wiring substrate and extends from a side of the first substrate side of the second wiring substrate toward the second semiconductor chip when seen in a plan view.

ADVANCED NODE COST REDUCTION BY ESD INTERPOSER

An apparatus including an electrostatic discharge circuit including a first circuit portion coupled beneath a die contact pad of an integrated circuit die and a second circuit portion in an interposer separate from the integrated circuit die, the interposer including a first contact point coupled to the contact pad of the integrated circuit die and a second contact point operable for connection to an external source. A method including forming an integrated circuit die including a first electrostatic discharge structure beneath a contact pad of the die; and coupling the die to an interposer including an interposer contact and a second electrostatic discharge structure, wherein a signal at the contact pad of the die is operable to be routed through the interposer. 1. An apparatus comprising:an electrostatic discharge circuit comprising a first circuit portion coupled beneath a die contact pad of an integrated circuit die and a second circuit portion in an interposer separate from the integrated circuit die, the interposer comprising a first contact point coupled to the contact pad of the integrated circuit die and a second contact point operable for connection to an external source.2. The apparatus of claim 1 , wherein the first circuit portion comprises an ESD robustness that is different than an ESD protection robustness of the second circuit portion.3. The apparatus of claim 2 , wherein the first circuit portion comprises a smaller maximum discharge current than a maximum discharge current of the second circuit portion and a trigger voltage of the second circuit portion is less than a trigger voltage of the first circuit portion.4. The apparatus of claim 1 , wherein the interposer comprises an interposer contact pad operable to connect an assembly of the die and the interposer to a substrate and the second circuit portion is coupled to the interposer contact pad and the die contact pad.5. The apparatus of claim 4 , wherein the first circuit portion and the second ...

Flip-Chip Hybridisation Of Two Microelectronic Components Using A UV Anneal

A method of manufacturing a microelectronic device including a first component hybridized with a second component via electric interconnects, involves the steps of: (i) forming the first and second components, the second component being transparent to ultraviolet radiation at least in line with locations provided for the interconnects; (ii) forming interconnection elements including copper oxide on the second component at the locations provided for the interconnects; (iii) placing the first and second components on each other; and (iv) applying the ultraviolet radiation through the second component on the elements including copper oxide to implement an ultraviolet anneal converting copper oxide into copper.

INTERCONNECT STRUCTURES FOR PREVENTING SOLDER BRIDGING, AND ASSOCIATED SYSTEMS AND METHODS

Semiconductor dies having interconnect structures formed thereon, and associated systems and methods, are disclosed herein. In one embodiment, an interconnect structure includes a conductive material electrically coupled to an electrically conductive contact of a semiconductor die. The conductive material includes a first portion vertically aligned with the conductive contact, and a second portion that extends laterally away from the conductive contact. A solder material is disposed on the second portion of the interconnect structure such that the solder material is at least partially laterally offset from the conductive contact of the semiconductor die. In some embodiments, an interconnect structure can further include a containment layer that prevents wicking or other undesirable movement of the solder material during a reflow process. 1. A semiconductor die , comprising:a substrate having a center portion and an outer edge portion;an insulating material over a surface of the substrate;an electrically conductive contact at the surface of the substrate;an interconnect structure electrically coupled to the conductive contact, wherein the interconnect structure includes a top surface having a first portion and a second portion, wherein the first portion is vertically aligned with the conductive contact, and wherein the second portion extends (a) laterally away from the first portion in a direction away from the center portion and toward the outer edge portion of the substrate and (b) over at least a portion of the insulating material; anda solder material disposed at least partially on the second portion of the top surface.2. The semiconductor die of wherein the conductive contact is exposed at an opening in the insulating material.3. The semiconductor die of claim 1 , further comprising a containment layer over substantially all of the first portion of the top surface of the interconnect structure.4. The semiconductor die of wherein the containment layer is ...

SEMICONDUCTOR PACKAGE

A semiconductor package includes a first semiconductor chip having a first chip substrate, the first chip substrate having a first upper surface and a first lower surface opposite to each other, a first through-silicon via (TSV), a lower connection pad and a first lower passivation layer on the first lower surface of the first chip substrate, the first lower passivation layer exposing a portion of the lower connection pad, an upper connection pad and a first upper passivation layer on the first upper surface of the first chip substrate, the first upper passivation layer including a first upper inorganic material layer, and a second semiconductor chip connected to the first semiconductor chip, the second semiconductor chip including a second TSV, wherein the first lower passivation layer has a stacked structure of a first lower inorganic material layer and a lower organic material layer. 1. A semiconductor package , comprising: a first chip substrate, the first chip substrate having a first upper surface and a first lower surface opposite to each other,', 'a first through-silicon via (TSV),', 'a lower connection pad and a first lower passivation layer on the first lower surface of the first chip substrate, the first lower passivation layer exposing a portion of the lower connection pad,', 'an upper connection pad and a first upper passivation layer on the first upper surface of the first chip substrate, the first upper passivation layer including a first upper inorganic material layer; and, 'a first semiconductor chip includinga second semiconductor chip connected to the first semiconductor chip, the second semiconductor chip including a second TSV,wherein the first lower passivation layer has a stacked structure of a first lower inorganic material layer and a lower organic material layer.2. The semiconductor package as claimed in claim 1 , wherein the first lower inorganic material layer is on the first lower surface of the first chip substrate claim 1 , and the ...

Manufacturing method for semiconductor device

Provided is a method of manufacturing a semiconductor device that has a plurality of semiconductor components and a plurality of resin layers, the method including: a step in which resin layers and semiconductor components are laminated alternately on a substrate, and the same is adhered by being subjected to heating and pressurization at a temperature lower than the temperature at which the substrate and/or a solder layer of the semiconductor components melts; and a step in which heat and pressure are applied at a temperature at which the solder layer melts or a temperature higher than said temperature.

Package with Solder Regions Aligned to Recesses

A method includes forming a passivation layer over a portion of a metal pad, forming a polymer layer over the passivation layer, and exposing the polymer layer using a photolithography mask. The photolithography mask has an opaque portion, a transparent portion, and a partial transparent portion. The exposed polymer layer is developed to form an opening, wherein the metal pad is exposed through the opening. A Post-Passivation Interconnect (PPI) is formed over the polymer layer, wherein the PPI includes a portion extending into the opening to connect to the metal pad. 1. An integrated circuit structure comprising:a substrate;a dielectric layer over the substrate, wherein the dielectric layer comprises a top surface; a first portion over and contacting the top surface of the dielectric layer; and', 'a plurality of second portions extending from the top surface of the dielectric layer into the dielectric layer; and, 'a conductive pad comprisinga solder region overlying and contacting the conductive pad.2. The integrated circuit structure of claim 1 , wherein the first portion of the conductive pad encircles the second portions of the conductive pad.3. The integrated circuit structure of claim 1 , wherein the solder region overlaps the first portion and the plurality of second portions of the conductive pad.4. The integrated circuit structure of claim 1 , wherein the second portions of the conductive pad have substantially planar bottom surfaces and slanted sidewalls.5. The integrated circuit structure of claim 1 , wherein the solder region further overlaps a portion of the dielectric layer claim 1 , and the portion of the dielectric layer is between two of the plurality of second portions of the conductive pad.6. The integrated circuit structure of claim 1 , wherein the plurality of second portions of the conductive pad extend to an intermediate level of the dielectric layer claim 1 , with the intermediate level being between the top surface and a bottom surface of the ...

Electrical Connection for Chip Scale Packaging

A system and method for providing a post-passivation and underbump metallization is provided. An embodiment comprises a post-passivation layer that is larger than an overlying underbump metallization. The post-passivation layer extending beyond the underbump metallization shields the underlying layers from stresses generated from mismatches of the materials' coefficient of thermal expansion.

Method of Manufacturing Semiconductor Device and Semiconductor Device Manufacturing Apparatus

A method of manufacturing a semiconductor device according to the present invention comprises: a bump forming step of forming a bump electrode 100 on a semiconductor chip 1, the bump electrode 100 protruding in a substantially conical shape; a pad forming step of forming a pad electrode 200 on a substrate 10, the pad electrode 200 having a recess 210 with inner lateral surfaces thereof defining a substantially pyramidal shape or a prism shape; a pressing step of pressing the bump electrode 100 and the pad electrode 200 in a direction which brings them closer to each other, with the bump electrode 100 being inserted in the recess 210 so that the central axis of the bump electrode 100 and the central axis of the recess 210 coincide with each other; and an ultrasonic joining step of joining the bump electrode 100 and the pad electrode 200 by vibrating at least one of the bump electrode 100 and the pad electrode 200 using ultrasonic waves.

Methods of making printed structures

An example of a method of making a printed structure comprises providing a destination substrate, contact pads disposed on the destination substrate, and a layer of adhesive disposed on the destination substrate. A stamp with a component adhered to the stamp is provided. The component comprises a stamp side in contact with the stamp and a post side opposite the stamp side, a circuit, and connection posts extending from the post side. Each of the connection posts is electrically connected to the circuit. The component is pressed into contact with the adhesive layer to adhere the component to the destination substrate and to form a printed structure having a volume defined between the component and the destination substrate. The stamp is removed and the printed structure is processed to fill or reduce the volume.

Wafer Backside Interconnect Structure Connected to TSVs

An integrated circuit structure includes a semiconductor substrate having a front surface and a back surface; a conductive via passing through the semiconductor substrate; and a metal feature on the back surface of the semiconductor substrate. The metal feature includes a metal pad overlying and contacting the conductive via, and a metal line over the conductive via. The metal line includes a dual damascene structure. The integrated circuit structure further includes a bump overlying the metal line.

FINE PITCH COPPER PILLAR PACKAGE AND METHOD

An electronic component package includes a substrate having an upper surface. Traces on the upper surface of the substrate extend in a longitudinal direction. The traces have a first latitudinal width in a latitudinal direction, the latitudinal direction being perpendicular to the longitudinal direction. Rectangular copper pillars are attached to bond pads of an electronic component, the copper pillars having a longitudinal length and a latitudinal second width. The latitudinal second width of the copper pillars is equal to and aligned with the first latitudinal width of the traces. Further, the longitudinal length of the copper pillars is parallel with the longitudinal direction of the trace and equal to the length of the bond pads. The copper pillars are mounted to the traces with solder joints. 120-. (canceled)21. An electronic component assembly comprising:an electronic component comprising a pad, the pad comprising a longitudinal pad length and a latitudinal pad width; anda conductive pillar coupled to the pad, the conductive pillar comprising a longitudinal pillar length and a latitudinal pillar width, the latitudinal pillar width is less than the longitudinal pillar length;', 'the latitudinal pad width is different from the latitudinal pillar width by a first amount;', 'the longitudinal pad length is different from the longitudinal pillar length by a second amount that is different from the first amount; and', 'an end surface of the conductive pillar is covered with reflowed solder while a majority of a lateral side of the conductive pillar is free of solder., 'wherein22. The electronic component assembly of claim 21 , wherein the lateral side of the conductive pillar is substantially free of solder.23. The electronic component assembly of claim 21 , wherein the conductive pillar comprises a solder capped copper pillar.24. The electronic component assembly of claim 21 , wherein the electronic component comprises a chip claim 21 , and the pad comprises a bond- ...

SEMICONDUCTOR PACKAGE WITH RIGID UNDER BUMP METALLURGY (UBM) STACK

The invention provides a semiconductor package. The semiconductor package includes a semiconductor die and a conductive pillar bump structure and a conductive plug. The semiconductor die has a die pad thereon. The conductive pillar bump structure is positioned overlying the die pad. The conductive pillar bump structure includes an under bump metallurgy (UBM) stack having a first diameter and a conductive plug on the UBM stack. The conductive plug has a second diameter that is different than the first diameter. 1. A semiconductor package , comprising:a semiconductor die having a die pad thereon; and an under bump metallurgy (UBM) stack having a first diameter; and', 'a conductive plug on the UBM stack,', 'wherein the conductive plug has a second diameter that is different than the first diameter., 'a conductive pillar bump structure overlying the die pad, wherein the conductive pillar bump structure comprises2. The semiconductor package as claimed in claim 1 , wherein the first diameter and the second diameter are along a direction that is substantially parallel to a front-side surface of the semiconductor die.3. The semiconductor package as claimed in claim 1 , wherein the first diameter is greater than the second diameter.4. The semiconductor package as claimed in claim 1 , wherein an overlapping area between the conductive plug and a top surface of the UBM stack is less than an area of the top surface of the UBM stack.5. The semiconductor package as claimed in claim 1 , wherein the conductive plug is overlying a portion of the top surface of the UBM stack.6. The semiconductor package as claimed in claim 1 , wherein an interface between the conductive plug and the UBM stack is a planar surface.7. The semiconductor package as claimed in claim 1 , wherein the UBM stack comprises:a first metal layer in contact with the die pad of the semiconductor die; anda second metal pad overlying the first metal layer and in contact with the conductive plug.8. The semiconductor ...

Integrated wluf and sod process

This disclosure relates generally to a wafer having a plurality of semiconductor chips having a major surface, a metal contact positioned on one of the plurality of semiconductor chips and having a side surface and contact surface, the contact surface substantially parallel to the major surface, wherein the contact surface defines a thickness of the metal contact relative to the major surface, an underfill layer abutting the one of the plurality of semiconductor chips and the side surface of the metal contact, the underfill layer having a top surface substantially parallel to the major surface, wherein the top surface of the underfill layer defines a thickness of the underfill layer relative to the major surface, the thickness of the underfill layer being not greater than the thickness of the metal contact, and a solder bump formed in electrical contact with the contact surface of the metal contact.

Substrate structure, semiconductor package structure and method for manufacturing the same

A substrate structure includes a carrier, a first metal layer, a circuit layer and a dielectric layer. The carrier has a first surface and a second surface. The first metal layer is disposed on the first surface of the carrier. The circuit layer is disposed on the first metal layer. The dielectric layer covers the circuit layer and defines a plurality of openings to expose portions of the circuit layer and portions of the first metal layer.

ELECTRONIC PART, ELECTRONIC DEVICE, AND ELECTRONIC APPARATUS

An electronic part includes a substrate, an insulating film formed over the substrate, a first pillar electrode, a first solder formed over the first pillar electrode, a second pillar electrode, and a second solder formed over the second pillar electrode. The first pillar electrode over which the first solder is formed is formed over a first region of an insulating film including a level difference between a first opening portion and a peripheral portion of the first opening portion. The second pillar electrode over which the second solder is formed is formed over a second region of the insulating film including a second opening portion whose opening area is larger than that of the first opening portion. For example, the second pillar electrode over which the second solder is formed is formed over the second opening portion of the insulating film. 1. An electronic part comprising:a substrate;an insulating film formed over the substrate, having a first region including a first opening portion and a first peripheral portion of the first opening portion, and having a second region including a second opening portion whose opening area is larger than an opening area of the first opening portion;a first pillar electrode formed over the first region;a first solder formed over the first pillar electrode;a second pillar electrode formed over the second region; anda second solder formed over the second pillar electrode.2. The electronic part according to claim 1 , wherein upper ends of the first solder and the second solder are at a same level from the substrate.3. The electronic part according to claim 1 , wherein the first pillar electrode has a first concavity formed as a result of sinking of a portion corresponding to the first opening portion in an upper surface over which the first solder is formed.4. The electronic part according to claim 1 , wherein the second region is the second opening portion.5. The electronic part according to claim 1 , wherein the second region ...

Semiconductor Devices and Methods of Manufacture Thereof

Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method includes forming a contact pad over a semiconductor device. A passivation material is formed over the contact pad. The passivation material has a thickness and is a type of material such that an electrical connection may be made to the contact pad through the passivation material. 1. A semiconductor device comprising:a substrate;a contact pad disposed over the substrate;a passivation material disposed over the contact pad, wherein sidewalls of the passivation material are coterminous with sidewalls of the contact pad; anda wire, connector, or contact coupled to the contact pad through the passivation material, the passivation material being interposed between and separating the wire, connector, or contact from the contact pad.2. The semiconductor device of claim 1 , wherein the passivation material comprises a material that is adapted to prevent or reduce corrosion of the contact pad.3. The semiconductor device of claim 1 , further comprising an insulating material disposed over the substrate proximate the contact pad.4. The semiconductor device of claim 3 , wherein a portion of the insulating material is disposed over edges of the contact pad.5. The semiconductor device of claim 4 , wherein the contact pad comprises a first width claim 4 , wherein an opening in the insulating material proximate the contact pad comprises a second width claim 4 , and wherein the second width is less than the first width.6. The semiconductor device of claim 1 , further comprising a plurality of first contact pads disposed over the substrate claim 1 , wherein the plurality of first contact pads comprises the contact pad claim 1 , wherein the passivation material is disposed over each of the first contact pads claim 1 , and wherein a wire claim 1 , a connector claim 1 , or a contact is coupled to each of the first contact pads through the passivation material.7. The semiconductor device ...

COPPER PILLAR BUMP STRUCTURE AND MANUFACTURING METHOD THEREFOR

A method for manufacturing a metal bump device includes providing a substrate structure including a substrate and a metal layer having a recess on the substrate, forming a metal bump on the recess of the metal layer using a ball placement process, and forming a solder paste on the metal bump using a printing process. The manufacturing time is shorter, the manufacturing efficiency is higher, and the manufacturing cost is lower than conventional manufacturing methods. 1. A method for manufacturing a metal bump device , the method comprising:providing a substrate structure including a substrate and a metal layer having a recess on the substrate;forming a metal bump on the recess of the metal layer using a ball placement process; andforming a solder paste on the metal bump using a printing process.2. The method of claim 1 , further comprising performing a reflow process on the solder paste.3. The method of claim 1 , wherein the ball placement process comprising:forming a stencil having a first opening aligned with the recess on the metal layer;forming a flux in the recess through the first opening;bonding the metal bump to the recess through the first opening using the flux; andremoving the stencil.4. The method of claim 3 , wherein the first opening has a size that is in a range between 70% and 90% of a size of the recess.5. The method of claim 1 , wherein the printing process comprises:forming a printing screen having a second opening aligned with the metal bump on the metal bump;forming the solder paste on the metal bump through the second opening; andremoving the printing screen.6. The method of claim 1 , wherein:the metal bump comprises copper;the solder paste comprises tin or tin-silver.7. The method of claim 1 , wherein the metal bump has a diameter in a range between 60 μm and 100 μm claim 1 , and a length in a range between 60 μm and 150 μm.8. The method of claim 1 , wherein providing the substrate structure comprises:providing the substrate;forming a liner ...

MICRO-CONNECTION STRUCTURE AND MANUFACTURING METHOD THEREOF

A micro-connection structure is provided. The micro-connection structure includes an under bump metallurgy (UBM) pad, a bump and an insulating ring. The UBM pad is electrically connected to at least one metallic contact of a substrate. The bump is disposed on the UBM pad and electrically connected with the UBM pad. The insulating ring surrounds the bump and the UBM pad. The bump is separate from the insulating ring with a distance and the bump is isolated by a gap between the insulating ring and the bump. 1. A micro-connection structure , comprising:an under bump metallurgy (UBM) pad, electrically connected with at least one metallic contact of a substrate, wherein the UBM pad includes a first pattern and a second pattern, and the first pattern is disposed on and surrounded by the second pattern;a bump, disposed on the first pattern of the UBM pad and electrically connected with the UBM pad; andan insulating ring surrounding the bump and the UBM pad,wherein the bump is separate and isolated from the insulating ring by an open trench between the insulating ring and the bump.2. The structure of claim 1 , further comprising a barrier layer covering the insulating ring claim 1 , wherein the barrier layer is in contact with the UBM pad without being in contact with the bump.3. The structure of claim 2 , wherein the barrier layer is in contact with the second pattern of the UBM pad without being in contact with the first pattern of the UBM pad.4. The structure of claim 1 , further comprising a metallic pad disposed directly under the UBM pad and sandwiched between the UBM pad and the at least one metallic contact claim 1 , wherein the UBM pad is electrically connected with the at least one metallic contact through the metallic pad.5. The structure of claim 4 , wherein the second pattern of the UBM pad includes a protruded portion surrounding the first pattern of the UBM pad.6. The structure of claim 5 , wherein the protruded portion of the second pattern surrounds the ...

FABRICATION METHOD OF SEMICONDUCTOR STRUCTURE

The present invention provides a semiconductor structure and a method of fabricating the same. The method includes: providing a chip having conductive pads, forming a metal layer on the conductive pads, forming a passivation layer on a portion of the metal layer, and forming conductive pillars on the metal layer. Since the metal layer is protected by the passivation layer, the undercut problem is solved, the supporting strength of the conductive pillars is increased, and the product reliability is improved. 113-. (canceled)14. A method of fabricating a semiconductor structure , comprising:providing a chip having a plurality of conductive pads and a protective layer that has a plurality of protective-layer openings, with a portion of each of the conductive pads exposed from each of the protective-layer openings;forming a metal layer on the protective layer, and electrically connecting the metal layer to the conductive pads, with a portion of the protective layer exposed from the metal layer;forming on a portion of the metal layer and on the protective layer a first passivation layer that covers a lateral side of the metal layer, and forming a plurality of first openings in the first passivation layer, with a portion of the metal layer exposed from the first openings; andforming a plurality of conductive pillars on the exposed portion of the metal layer in the first openings.15. The method of claim 14 , wherein the first openings are positioned above the protective-layer opening claim 14 , and each of the first openings has a width greater than or equal to a width of each of the protective-layer openings.16. The method of claim 14 , wherein the metal layer is formed by:forming a metal material on the conductive pads and the protective layer;forming a resist layer on the metal material, with a portion of the metal material exposed therefrom;removing the exposed portion of the metal material, so as for a remaining portion of the metal material to form the metal layer; ...

Semiconductor Packages and Methods of Forming Same

In an embodiment, a package includes a first package structure including a first die having a first active side and a first back-side, the first active side including a first bond pad and a first insulating layer a second die bonded to the first die, the second die having a second active side and a second back-side, the second active side including a second bond pad and a second insulating layer, the second active side of the second die facing the first active side of the first die, the second insulating layer being bonded to the first insulating layer through dielectric-to-dielectric bonds, and a conductive bonding material bonded to the first bond pad and the second bond pad, the conductive bonding material having a reflow temperature lower than reflow temperatures of the first and second bond pads. 1. A device comprising:a first integrated circuit die comprising a first conductive feature, a first insulating layer around the first conductive feature, and a bond pad on the first conductive feature and the first insulating layer;a second integrated circuit die comprising a second conductive feature and a second insulating layer around the second conductive feature; anda conductive bonding layer connecting the bond pad to the second conductive feature, a reflow temperature of the conductive bonding layer being lower than a reflow temperature of the bond pad,wherein the second insulating layer is physically separated from the bond pad by a void, sidewalls of the conductive bonding layer being exposed to the void.2. The device of further comprising:a barrier layer disposed between the second conductive feature and the conductive bonding layer, sidewalls of the barrier layer being exposed to the void.3. The device of further comprising:a first polymer layer on the first insulating layer, the first polymer layer being disposed around the bond pad and the conductive bonding layer; anda second polymer layer on the second insulating layer, the second polymer layer being ...

Package with Solder Regions Aligned to Recesses

A method includes forming a passivation layer over a portion of a metal pad, forming a polymer layer over the passivation layer, and exposing the polymer layer using a photolithography mask. The photolithography mask has an opaque portion, a transparent portion, and a partial transparent portion. The exposed polymer layer is developed to form an opening, wherein the metal pad is exposed through the opening. A Post-Passivation Interconnect (PPI) is formed over the polymer layer, wherein the PPI includes a portion extending into the opening to connect to the metal pad.

Micro-connection structure and manufacturing method thereof

A micro-connection structure is provided. The micro-connection structure includes an under bump metallurgy (UBM) pad, a bump and an insulating ring. The UBM pad is electrically connected to at least one metallic contact of a substrate. The bump is disposed on the UBM pad and electrically connected with the UBM pad. The insulating ring surrounds the bump and the UBM pad. The bump is separate from the insulating ring with a distance and the bump is isolated by a gap between the insulating ring and the bump.

Connector Structure and Method of Forming Same

Connector structures and methods of forming the same are provided. A method includes forming a first patterned passivation layer on a workpiece, the first patterned passivation layer having a first opening exposing a conductive feature of the workpiece. A seed layer is formed over the first patterned passivation layer and in the first opening. A patterned mask layer is formed over the seed layer, the patterned mask layer having a second opening exposing the seed layer, the second opening overlapping with the first opening. A connector is formed in the second opening. The patterned mask layer is partially removed, an unremoved portion of the patterned mask layer remaining in the first opening. The seed layer is patterned using the unremoved portion of the patterned mask layer as a mask. 1. A structure comprising:a substrate comprising active devices;a metallization layer over the substrate, the metallization layer comprising a conductive feature, the conductive feature being electrically coupled to the active devices;a first passivation layer over the metallization layer, the first passivation layer contacting a first portion of the conductive feature, a second portion of the conductive feature being free from the first passivation layer, the second portion of the conductive feature having a first width;a seed layer over the second portion of the conductive feature, the seed layer being a continuous conductive material having a second width, the second width being less than the first width; anda connector over the seed layer, the connector having a third width, the third width being less than the second width.2. The structure of further comprising:a second passivation layer over the first passivation layer.3. The structure of further comprising:a protection layer having a first portion disposed between the conductive feature and the seed layer, and a second portion disposed between the first passivation layer and the second passivation layer.4. The structure of claim ...

Semiconductor package and method of manufacturing thereof

A semiconductor package comprises a semiconductor chip having an active surface with a conductive pad thereon; an electroplated Au—Sn alloy bump over the active surface; and a (glass) substrate comprising conductive traces electrically coupling with the electroplated Au—Sn alloy bump, wherein the electroplated Au—Sn alloy bump has a composition from about Au 0.85 Sn 0.15 to about Au 0.75 Sn 0.25 in weight percent uniformly distributed from an end in proximity to the active surface to an end in proximity to the substrate. A method of manufacturing a semiconductor package comprises forming patterns of conductive pads on an active surface of a semiconductor chip; electroplating Au—Sn alloy bump over the conductive pads; and bonding the semiconductor chip on a corresponding conductive trace on a substrate by a reflow operation or a thermal press operation.

Backmetal removal methods

Various implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; forming an organic material over the first side of the semiconductor substrate and the plurality of notches; thinning a second side of the semiconductor substrate opposite the first side one of to or into the plurality of notches; stress relief etching the second side of the semiconductor substrate; applying a backmetal over the second side of the semiconductor substrate; removing one or more portions of the backmetal through jet ablating the second side of the semiconductor substrate; and singulating the semiconductor substrate through the permanent coating material into a plurality of semiconductor packages.

Three-dimensional memory device having bonding structures connected to bit lines and methods of making the same

Three-dimensional memory devices in the form of a memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack, in which each of the memory stack structures includes a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. Bit lines are electrically connected to an end portion of a respective one of the vertical semiconductor channels. Bump connection via structures contact a top surface of a respective one of the bit lines, in which each of the bump connection via structures has a greater lateral dimension along a lengthwise direction of the bit lines than along a widthwise direction of the bit lines. Metallic bump structures of another semiconductor die contact respective ones of the bump connection via structures to make respective electrical connections between the two dies.

NOVEL 3D INTEGRATION METHOD USING SOI SUBSTRATES AND STRUCTURES PRODUCED THEREBY

A process and resultant article of manufacture made by such process comprises forming through vias needed to connect a bottom device layer in a bottom silicon wafer to the one in the top device layer in a top silicon wafer comprising a silicon-on-insulator (SOI) wafer. Through vias are disposed in such a way that they extend from the middle of the line (MOL) interconnect of the top wafer to the buried oxide (BOX) layer of the SOI wafer with appropriate insulation provided to isolate them from the SOI device layer. 123-. (canceled)24. A product made by the process of fabricating an enhanced 3D device stack comprising the steps of:fabricating silicon on insulator (SOI) circuits on a first SOI wafer having a silicon substrate with a buried oxide (BOX) layer, said buried oxide (BOX) layer having a bottom surface;providing a first set of middle of the line (MOL) interconnects for said SOI circuits said first set of middle of the line (MOL) interconnects having a top surface;patterning and etching a set of vias and alignment marks that extend from the top surface of said first set of MOL interconnects to the bottom surface of said BOX layer, said vias having exposed ends;filling and planarizing said vias and said alignment marks with metal;completing a first set of BEOL interconnects to connect said SOI circuits;providing a first set of bonding pads level atop said first set of BEOL interconnects;fabricating a second device wafer with a second set of circuits comprising a second set of MOL interconnects, a second set of BEOL interconnects and a second set of bonding pads;flipping said first SOI wafer, positioning it atop said second device wafer such that said first and said second set of bonding pads are aligned to each other;bonding said first SOI wafer and said second device wafer together by applying elevated temperature and pressure to bond said first and second set of bonding pads;removing the silicon substrate from said first SOI wafer by a grinding, polishing and ...

PACKAGE STRUCTURE HAVING BUMP WITH PROTECTIVE ANTI-OXIDATION COATING

A package structure includes a semiconductor substrate: a pad disposed on the semiconductor substrate; a conductive layer disposed on the pad; a protection coating; and a metal bump disposed on the conductive layer, and the metal bump covered with the protection coating so as to avoid oxidation of the metal bump. 1. A package structure , comprising:a semiconductor substrate;a pad disposed on the semiconductor substrate;a conductive layer disposed on the pad;a protection coating; anda metal bump disposed on the conductive layer, wherein the metal bump is covered with the protection coating so as to avoid oxidation of the metal bump, and a portion of the protection coating is in direct contact with a top surface of the metal bump.2. The package structure of claim 1 , further comprising:a passivation layer disposed on the semiconductor substrate,wherein the pad is disposed in the passivation layer, the passivation layer has an opening for partially exposing a surface of the pad, and the conductive layer is in contact with the surface of the pad and the passivation layer.3. The package structure of claim 1 , wherein the metal bump has a flat surface facing away from the semiconductor substrate.4. (canceled)5. The package structure of claim 1 , wherein the metal bump is formed from copper.6. The package structure of claim 1 , wherein the conductive layer is a under metal bump metallurgy (UBM) layer.7. The package structure of claim 1 , wherein the protection coating is an organic solderability preservative (OSP) layer.8. The package structure of claim 1 , further comprising:a layer of solder disposed on the protection coating and positioned directly over the metal bump.9. The package structure of claim 8 , wherein the layer of solder is formed from tin.10. The package structure of claim 1 , wherein the passivation layer is formed from SiO2.1120-. (canceled) The present invention relates to a package structure and a manufacturing method thereof.Reflow soldering is a ...

COPPER STRUCTURES WITH INTERMETALLIC COATING FOR INTEGRATED CIRCUIT CHIPS

An integrated circuit (IC) chip includes a copper structure with an intermetallic coating on the surface. The IC chip includes a substrate with an integrated circuit. A metal pad electrically connects to the integrated circuit. The copper structure electrically connects to the metal pad. A solder bump is disposed on the copper structure. The surface of the copper structure has a coating of intermetallic. The copper structure can be a redistribution layer and a copper pillar that is disposed on the redistribution layer. 1. An integrated circuit (IC) chip comprising:a substrate comprising an integrated circuit;a metal pad disposed on the substrate and electrically connects to the integrated circuit;a redistribution layer that electrically connects to the metal pad;a copper pillar that is disposed on and electrically connects to the redistribution layer;a solder bump that is disposed on and electrically connects to the copper pillar; anda tin-copper intermetallic coating that is formed on a surface of the copper pillar and the redistribution layer.2. The IC chip of claim 1 , wherein the metal pad comprises an input/output pad of the IC chip.3. The IC chip of claim 1 , wherein the solder bump comprises tin.4. The IC chip of claim 1 , wherein the metal pad comprises aluminum.5. The IC chip of claim 1 , further comprising a copper seed layer disposed between the metal pad and the redistribution layer.6. The IC chip of claim 5 , wherein the copper seed layer comprises a titanium-copper stack.7. The IC chip of claim 5 , wherein the tin-copper intermetallic is formed on a surface of the copper seed layer.8. An integrated circuit (IC) chip comprising:a substrate comprising an integrated circuit;a first copper structure comprising a first copper pillar formed on a first metal pad that electrically connects to the integrated circuit, a first solder bump formed on the first copper pillar, and a first intermetallic coating on a surface of the first copper structure; anda second ...

MULTILAYERS OF NICKEL ALLOYS AS DIFFUSION BARRIER LAYERS

A structure for a semiconductor device includes a copper (Cu) layer and a first nickel (Ni) alloy layer with a Ni grain size a. The structure also includes a second Ni alloy layer with a Ni grain size a, wherein a Подробнее

Fan-Out Interconnect Structure and Method for Forming Same

A method embodiment includes forming a sacrificial film layer over a top surface of a die, the die having a contact pad at the top surface. The die is attached to a carrier, and a molding compound is formed over the die and the sacrificial film layer. The molding compound extends along sidewalls of the die. The sacrificial film layer is exposed. The contact pad is exposed by removing at least a portion of the sacrificial film layer. A first polymer layer is formed over the die, and a redistribution layer (RDL) is formed over the die and electrically connects to the contact pad. 1. A method comprising:providing a die comprising a contact pad at a top surface thereof;forming a first polymer layer over the die;forming a molding compound surrounding the first polymer layer and the die;forming a second polymer layer over the molding compound and the first polymer layer; andforming a first opening through the second polymer layer and the first polymer layer, the first opening exposing the contact pad; andforming a redistribution layer in the first opening, the redistribution layer extending along top surfaces of the contact pad, the first polymer layer, and the second polymer layer.2. The method of claim 1 , further comprising:forming a second opening in the first polymer layer before forming the molding compound, the second opening exposing the contact pad; andforming a sacrificial material in the second opening.3. The method of claim 2 , further comprising planarizing the molding compound claim 2 , the sacrificial material claim 2 , and the first polymer layer.4. The method of claim 3 , further comprising removing the sacrificial material after planarizing the molding compound claim 3 , the sacrificial material claim 3 , and the first polymer layer.5. The method of claim 2 , further comprising attaching the die to a carrier after forming the sacrificial material and before forming the molding compound.6. The method of claim 1 , wherein forming the first opening ...

Copper structures with intermetallic coating for integrated circuit chips

An integrated circuit (IC) chip includes a copper structure with an intermetallic coating on the surface. The IC chip includes a substrate with an integrated circuit. A metal pad electrically connects to the integrated circuit. The copper structure electrically connects to the metal pad. A solder bump is disposed on the copper structure. The surface of the copper structure has a coating of intermetallic. The copper structure can be a redistribution layer and a copper pillar that is disposed on the redistribution layer.

NOVEL 3D INTEGRATION METHOD USING SOI SUBSTRATES AND STRUCTURES PRODUCED THEREBY

A process and resultant article of manufacture made by such process comprises forming through vias needed to connect a bottom device layer in a bottom silicon wafer to the one in the top device layer in a top silicon wafer comprising a silicon-on-insulator (SOI) wafer. Through vias are disposed in such a way that they extend from the middle of the line (MOL) interconnect of the top wafer to the buried oxide (BOX) layer of the SOI wafer with appropriate insulation provided to isolate them from the SOI device layer. 1. An article of manufacture comprising at least two bonded device layers of which at least one first device layer comprises silicon on insulator (SOI) circuits disposed on a buried oxide (BOX) layer having a BOX surface and a first set of middle of the line (MOL) interconnects and a first set of back end of the line (BEOL) interconnects disposed thereon , said at least one first device layer further being flipped and bonded atop a second device layer located on its parent wafer and comprising a second set of circuits , a second set of middle of line interconnects and a second set of BEOL interconnects , and said at least one first device layer and said second device layer being interconnected together by means of metal filled vias located within said first set of MOL interconnects and said BOX layer of said at least one first device layer and connecting on one end to bonding pads associated with said second device layer and on another end to metal features provided on a third set of BEOL interconnects located atop said BOX surface , where said third set of BEOL interconnects located atop said BOX surface is not directly in contact with said SOI circuits of said at least one first device layer , thus forming an enhanced 3D device stack.2. An article of manufacture according to further comprising input output terminals atop said third set of BEOL interconnects of said at least one first device layer to enable connection of the said enhanced 3D device stack ...

Semiconductor Devices, Methods of Manufacture Thereof, and Packaged Semiconductor Devices

Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a plurality of contact pads over a substrate, and forming an insulating material over the plurality of contact pads and the substrate. The insulating material is patterned to form an opening over each of the plurality of contact pads, and the plurality of contact pads is cleaned. The method includes forming an under-ball metallization (UBM) structure over the plurality of contact pads and portions of the insulating material. Cleaning the plurality of contact pads recesses a top surface of each of the plurality of contact pads.

Chip Packaging Structure and Related Inner Lead Bonding Method

A chip packaging structure includes a chip and a film substrate. The chip is formed with a gold bump, and the film substrate is formed with an inner lead, wherein the gold bump includes a first bonding surface and a plurality of side walls. The gold bump is electrically connected to the inner lead through a eutectic material coverage layer, and the first bonding surface and at least one of the plurality of side walls are covered by the eutectic material coverage layer. 1. A lead bonding method for a chip packaging structure , wherein the chip packaging structure comprises a chip and a film substrate , comprising:making a first bonding surface of a gold bump of the chip contact with a lead of the film substrate;heating the gold bump and the lead up to a temperature range to form a eutectic material coverage between the gold bump and the lead; andholding on for a predetermined period to make a first bonding surface, a second bonding surface and at least one of a plurality of side walls of the gold bump covered by the eutectic material coverage.2. The lead bonding method of claim 1 , further comprising:forming the gold bump on the chip; andforming the lead on the film substrate.3. The lead bonding method of claim 1 , wherein the lead and the gold bump extend along a first direction claim 1 , the gold bump contacts with the lead toward a second direction claim 1 , a width of the gold bump and a width of the lead are sizes along a third direction claim 1 , and the first direction claim 1 , the second direction and the third direction are perpendicular to one another.4. The lead bonding method of claim 3 , wherein the width of the gold bump is smaller than or equal to the width of the lead the gold bump.5. The lead bonding method of claim 3 , wherein the width of the gold bump is greater than the width of the lead.6. The lead bonding method of claim 1 , wherein the lead comprises a second bonding surface claim 1 , the second bonding surface faces toward the first bonding ...