СВЕТОИЗЛУЧАЮЩЕЕ УСТРОЙСТВО, ПРИСОЕДИНЕННОЕ К ОПОРНОЙ ПОДЛОЖКЕ

... 1. Структура, содержащая:опорную подложку, содержащую тело и множество сквозных отверстий, проходящих через всю толщину тела; иполупроводниковое светоизлучающее устройство, содержащее светоизлучающий слой, размещенный между областью n-типа и областью p-типа, причем полупроводниковое светоизлучающее устройство присоединено к опорной подложке посредством диэлектрического соединяющего слоя;при этом опорная подложка является не более широкой, чем полупроводниковое светоизлучающее устройство.2. Структура по п. 1, в которой область n-типа расположена с отступом от края полупроводникового светоизлучающего устройства.3. Структура по п. 2, которая дополнительно содержащая полимерный слой, размещенный между краем области n-типа и краем полупроводникового светоизлучающего устройства.4. Структура по п. 1 дополнительно содержащая металлический контакт, размещенный на области n-типа.5. Структура по п. 4, в которой металлический контакт проходит по боковой стенке на краю области n-типа.6. Структура по ...

Substrat-Bondingstruktur und Substrat-Bondingverfahren

Eine Vorrichtung (2) ist auf einer Hauptoberfläche eines Substrats (1) ausgebildet. Die Hauptoberfläche des Substrats (1) ist über das Bonding-Bauteil (11, 12, 13) in einem hohlen Zustand an die Unterseite des Gegensubstrats (14) gebondet. Eine Schaltung (17) und eine Höckerstruktur (26) sind auf der Oberseite des Gegensubstrats (14) ausgebildet. Die Höckerstruktur (26) ist in einem Bereich positioniert, der zumindest dem Bonding-Bauteil (11, 12, 13) entspricht, und weist eine größere Höhe als diejenige der Schaltungsstruktur (17) auf.

Chip size semiconductor component

The semiconductor chip (21) carries several beads (22) bonded to the inner ends of the conductive wires (16), in a vertical manner. The entire chip is embedded in synthetic resin (23) such that the outer ends of the conductive wires protrude outwards. Preferably the inner end of the bonded wires, in contact with the chip beads, are shaped as irregular, oval; bonding spheres (25). Typically the outer ends of the protruding conductive vires are bent, directed against the middle of the chip, such as to form L-shaped external conductors.

INTEGRIERTES SCHALTUNGSPACKAGE UND VERFAHREN

In einer Ausführungsform weist eine Struktur Folgendes auf: einen ersten integrierten Schaltungsdie, der erste Die-Anschlüsse aufweist; eine erste Dielektrikumsschicht auf den ersten Die-Anschlüssen; erste leitfähige Durchkontaktierungen, die sich durch die erste Dielektrikumsschicht hindurch erstrecken, wobei die ersten leitfähigen Durchkontaktierungen an eine erste Untergruppe der ersten Die-Anschlüsse angeschlossen sind; einen zweiten integrierten Schaltungsdie, der an eine zweite Untergruppe der ersten Die-Anschlüsse mit ersten aufschmelzbaren Anschlüssen gebondet ist; ein erstes Verkapselungsmaterial, das den zweiten integrierten Schaltungsdie und die ersten leitfähigen Durchkontaktierungen umgibt, wobei das erste Verkapselungsmaterial und der erste integrierte Schaltungsdie seitlich angrenzend sind; zweite leitfähige Durchkontaktierungen benachbart zu dem ersten integrierten Schaltungsdie; ein zweites Verkapselungsmaterial, das die zweiten leitfähigen Durchkontaktierungen, das erste ...

Bondpads mit unterschiedlich dimensionierten Öffnungen

Integrierter-Schaltkreis-Die (400), der Folgendes umfasst:mehrere Bondpads (401); undeine Die-Passivierungsschicht mit mehreren unterschiedlich dimensionierten Öffnungen (411, 421, 431, 441), die mehrere der Bondpads (401) freilegen, wobei die mehreren unterschiedlich dimensionierten Öffnungen (411, 421, 431, 441) zwei oder mehr Gruppen von Öffnungen umfassen, wobei jede Gruppe relativ zu der/den anderen Gruppe(n) eine unterschiedliche durchschnittliche Öffnungsgröße aufweist; und wobei Größen der mehreren unterschiedlich dimensionierten Öffnungen auf eine solche Weise variieren, dass Spannungen auf dem Die (400) aufgrund einer asymmetrischen Verteilung der mehreren Bondpads (401) wenigstens teilweise kompensiert werden.

Integration von Silicium-Photonik-IC für hohe Datenrate

Integrierte Komponentenbaugruppe, die umfasst:eine Leiterplatte (PCB);eine integrierte Photonikschaltung (PIC), die mit der PCB auf einer ersten Seite der PIC mechanisch gekoppelt ist; undeine Treiber-IC mit einer ersten Seite, wobei die erste Seite der Treiber-IC(i) mit einer zweiten Seite der PIC über einen ersten Satz von Höcker-Bondverbindungen direkt mechanisch und elektrisch gekoppelt ist, und(ii) mit der PCB über einen zweiten Satz von Höcker-Bondverbindungen elektrisch gekoppelt ist.

Verfahren zum Herstellen einer Halbleiteranordnung.

Verfahren zum Montieren von Halbleiterelementen

Wiring substrate for pressure sensors, acceleration sensors and ultrasonic sensors, comprises electrode cushion pad, which is arranged in opening, formed in protection insulation film

The wiring substrate has a wiring layer (15) formed on the surface of a silicon substrate (11), another wiring layer (16) formed on the surface of the former wiring layer. A protection insulation film (14) is so formed that it covers the latter wiring layer. An opening (14a) is formed in the protection insulation film, and an electrode cushion pad is arranged in the opening. The opening in the protection insulation film and the former wiring layer are formed at such positions that they do not overlap each other toward the card thickness of the substrate.

Verfahren und Vorrichtung zur "Flip-Chip" Montage eines elektronischen Bauteils

HALBLEITER-WAFERBEARBEITUNGSVERFAHREN

Ein Halbleiter-Waferbearbeitungsverfahren beinhaltet einen Schritt zum Ausbilden einer laserbearbeiteten Nut an der ersten vorderen Seite des Halbleiter-Wafers entlang jeder Teilungslinie, einen Schritt zum Ausbilden einer Maskenschicht an einer Schutzschicht mit Ausnahme eines Bereichs oberhalb einer Metallelektrode, die in jedem Bauelement an der vorderen Seite des Wafers ausgebildet ist, einen ersten Ätzschritt zum Ätzen der Schutzschicht unter Verwendung der Maskenschicht, um jede Metallelektrode freizulegen, einen zweiten Ätzschritt zum Ätzen der inneren Oberfläche von jeder laserbearbeiteten Nut unter Verwendung der Maskenschicht, die in dem ersten Ätzschritt verwendet wird, wodurch jede laserbearbeitete Nut freigelegt wird, und einen Teilungsschritt zum Teilen des Wafers entlang jeder laserbearbeiteten Nut, die in dem zweiten Ätzschritt ausgedehnt wurde.

Integrierte Schaltung oder Platine mit einer Höckerelektrode und Verfahren zu Ihrer Herstellung

Lötverfahren und Schaltung

Vorgeschlagen wird ein Lötverfahren zum Verbinden eines Halbleiterchips (1) mit einer Leiterplatte (2) über wenigstens einen Lötkontakt (7) und zum Herstellen einer Schaltung (14), wobei der Halbleiterchip wenigstens ein elektrisch leitendes Pad (5) aufweist und die Leiterplatte wenigstens einen Leiterbahnabschnitt (9) zur Kontaktierung mit wenigstens einem der Pads des Halbleiterchips umfasst, umfassend: eine Auftragung von Lötpaste (10) auf den wenigstens einen Leiterbahnabschnitt, einen Bondingprozess, bei dem ein Höcker (7) auf wenigstens einem Materialabschnitt (6) auf wenigstens eines der Pads gebondet wird, einen Bestückungsvorgang, bei dem die Leiterplatte so mit wenigstens einem der Halbleiterchips bestückt wird, dass wenigstens einer der Lötkontakte mit der Lötpaste in Berührung kommt, einen Heizprozess, bei dem eine elektrisch leitende Verbindung zwischen dem Leiterbahnabschnitt und dem Pad hergestellt wird. Zur Verbesserung des Lötverfahrens wird als Lötkontakt ausschließlich ...

Method for manufacturing semiconductor device

An amorphous Ni-P layer (10) which cancels crystallinity of a base metal layer is formed on the base metal layer, such as an FET electrode, by electroless gilding and then an electrolytic Au gilding layer (9) is formed on the amorphous Ni-P layer. Thus, luster nonuniformity of the electrolytic Au gilding layer formed on the base metal layer, such as the FET electrode, is avoided so that a position of an electrode pad can be mechanically detected in an easy manner, during auto- bonding, and its appearance is improved. Processing of MMICs is thus improved. ...

Forming electrical/mechanical connections

Devices and methods related to radio-frequency filters on silicon-on-insulator substrate

A semiconductor device and a method for its production

A semiconductor device wherein a coating film which is made of a polyimide resin or a polyimide isoindoloquinazolinedione resin and which is at least 10 mu m thick is disposed on at least an active region of a semiconductor substrate, and the resultant semiconductor substrate is encapsulated in a ceramic package. The semiconductor device has troubles relieved conspicuously, the troubles being ascribable to alpha-rays which come flying from impurities contained in the material of the package.

MULTILEVEL FOIL FOR SHARPENING A DISK BACK

PROCEDURE FOR SOLDERING ELECTRONIC ELEMENTS WITH SOLDERING PEAKS ON A SUBSTRATE

ELECTRICAL CONTACT FOR A CADMIUM TELLURIUM COMPONENT

PROCEDURE FOR THE PRODUCTION OF CONTACTLESS MAPS

Method for maintaining solder thickness in flipchip attach packaging processes

Electrical contact structures from flexible wire

METHOD OF PROVIDING RAISED CONTACT PORTIONS ON CONTACT AREAS OF AN ELECTRONIC MICROCIRCUIT

... : "Method of providing raised contact portions on contact areas of an electronic microcircuit". A method of providing raised contact portions on contact areas of an electronic microcircuit in which a ball is formed at one end of a metal wire by means of thermal energy, the ball is pressed against a contact area of the electronic microcircuit and is connected to said contact area, a weakening being provided in the wire near the ball and the wire being severed at the area of the weakening.

Verfahren zum Herstellen weichlötfähiger Metallkontakte

PROCEDURE FOR THE ATTACHMENT OF CONTACT CONTACTS TO CONTACT POINTS OF AN ELECTRONIC MICROCIRCUIT.

Joining method and device therefor

DUAL SOLDER METHODOLOGIES FOR ULTRAHIGH DENSITY FIRST LEVEL INTERCONNECTIONS

Semiconductor chip and method of manufacturing wafer stack package

The invention discloses a semiconductor chip and a method of manufacturing the wafer stack package. The method of manufacturing the semiconductor chip includes following steps: forming a first via hole in the front surface of the substrate; forming a first conductive plug in the first via hole using a first conductive material, the first conductive plug including a first portion in the substrate and a second portion protruding from the substrate; forming a second conductive plug on an upper surface of the first conductive plug using a second conductive material, the second conductive plug having a smaller cross-sectional area than the first conductive plug; back-lapping a rear surface of the substrate; and forming a second via hole in the back-lapped rear surface of the substrate, the second via hole aligned with the first via hole.

Flipchip method

For bare chip IC of warping reducing the assembly of the compensating TCE of the package substrate,

Wafer level system packaging method and packaging structure

Semiconductor device manufacturing method and semiconductor device

In a state wherein a plurality of protruding electrodes (4) on a semiconductor chip (1) abut a plurality of electrodes (13), which are formed on a semiconductor substrate (11), with a plurality of solder sections therebetween, the solder sections are melted, and a plurality of solder bonding sections (7), which are bonded to the protruding electrodes (4) of the semiconductor chip (1) and the electrodes (13) of the semiconductor substrate (11), are formed. Then, the interval (A) between a part of the semiconductor chip (1) and the semiconductor substrate (11) is made larger than the interval (B) between another part of the semiconductor chip (1) and the semiconductor substrate (11), and at least some solder bonding sections among the solder bonding sections (7) are stretched. Consequently, variance in the height of the solder bonding sections (7) is generated. Then, a hole (8) is formed in at least the solder bonding section (7a) having the maximum height among the solder bonding sections ...

Semiconductor package and method of manufacturing thereof

Semiconductor device free from short-circuit between bump electrodes and separation from circuit board and process of fabrication thereof

Semiconductor device having align mark layer and method of fabricating the same

Chip mounting, circuit board, data carrier and manufacture method thereof and electronic element assembly

The present invention is to quickly and electrically and mechanically reliably provide a method of mounting a semiconductor chip on a wiring board at a low cost, in a mountable flip-chip connection system. This mounting method comprises a step of pressing bumps of a semiconductor bare chip onto a thermoplastic resin film which is in a molten state in the condition of heating the thermoplastic resin film covering electrode regions on a wiring pattern with application of ultrasonic waves, thereby pushing the molten thermoplastic resin film aside to cause the bumps to contact the electrode regions, a step of successively applying ultrasonic waves to ultrasonically bond the bumps to the electrode regions in the condition of the bumps contacted to the electrode regions, and a step of cooling and hardening the molten thermoplastic resin to adhere the semiconductor bare chip to the wiring board.

Interconnection [...] structure and method

Multilayer substrate

Semiconductor device and manufacturing method thereof

Surface modification for handling wafer thinning process

A wafer is provided with a through hole via extending a portion of a substrate, an interconnect structure electrically connecting the through hole via, and a polyimide layer formed on the interconnect structure. Surface modification of the polyimide layer is the formation of a thin dielectric film on the polyimide layer by coating, plasma treatment, chemical treatment, or deposition methods. The thin dielectric film is adhered strongly to the polyimide layer, which can reduce the adhesion between the wafer surface and an adhesive layer formed in subsequent carrier attaching process. Surface modification for handling wafer thinning process is also disclosed in the invention.

A METHOD OF JOINING TWO ELECTRONIC COMPONENTS, FLIP-BY ANNEALING THE UV, OBTAINED ASSEMBLY

LSI circuit chip package with carrier and underlying substrate

La présente invention concerne un ensemble à dispositif électronique comprenant une puce à circuit intégré à grande échelle (LSI) ayant des parties centrale (4a) et périphérique (4b). Un circuit et des bornes sont formés dans les parties centrale (4a) et périphérique (4b), respectivement. Un substrat porteur est fixé à la partie centrale de la puce LSI. Le substrat porteur (3) a des parties centrale (4a) et périphérique (4b). Des gouttes et des bornes font prévues dans les parties centrale (4a) et périphérique (4b), respectivement du substrat porteur (3). Des fils connectent les bornes de la puce LSI et du substrat porteur (3). Le substrat porteur (3) est monté sur un substrat par l'intermédiaire des gouttes. Le coefficient de dilatation thermique est compris entre ceux de la puce LSI et du substrat.

A METHOD OF JOINING TWO ELECTRONIC COMPONENTS, FLIP UV BY ANNEALING, RESULTING ASSEMBLY

L'invention concerne un procédé d'assemblage de type Flip-Chip, entre un premier (1) et un deuxième (2) composants comportant chacun des plots de connexion (11, 21) sur une de leurs faces, dites faces d'assemblage, selon lequel on reporte les composants l'un sur l'autre par leurs faces d'assemblage de sorte à réaliser des interconnexions électriques entre les plots du premier et ceux du deuxième composant. Selon l'invention, on réalise une transformation de l'oxyde de cuivre en cuivre par recuit UV, très localement dans l'espacement entre composants au moins autour des zones au droit des plots de connexion. Le procédé selon l'invention peut être utilisé pour n'importe quel composant transparent aux UV, y compris pour des substrats en matière plastique tels que des substrats en PEN ou en PET.

ELECTRONICS COMPONENT HAS CONNECTIONS BY BALLS DECOUPLEES MECHANICALLY.

Composant électronique comportant au moins une puce et/ou un support, la puce étant destinée à être reportée sur le support et reliée, au niveau d'au moins un emplacement de connexion (102) de la puce formé par au moins une portion (108) d'une couche (104) de la puce, à au moins un emplacement de connexion du support formé par au moins une portion d'une couche du support, par au moins une bille, la puce et/ou le support comprenant des moyens de découplage mécanique de l'emplacement de connexion (102) de la puce et/ou du support par rapport à la puce et/ou au support, formés par au moins une cavité (110) réalisée dans la couche de la puce et/ou du support, sous l'emplacement de connexion de la puce et/ou du support, et au moins une tranchée (114), réalisée dans la couche de la puce et/ou du support, communiquant avec ladite cavité.

SUBSTRATE OF WIRING, ITS MANUFACTORING PROCESS AND ELECTRONIC DEVICE WHICH USES It

Un substrat de câblage multicouche en céramique (1) inclut un motif d'isolation en forme de ligne (8) qui est formé de façon à couvrir plusieurs motifs de câblage en surface (4) et à intersecter les motifs de câblage en surface respectifs, de telle sorte que des électrodes de plage (7) obtenues par soudage soinet définiies par les motifs d'isolation.

METHOD OF MANUFACTURING CHIP-SIZE PACKAGE TYPE SEMICONDUCTOR DEVICE

ELECTRIC DEVICE PRODUCING METHOD

이방성 도전 필름, 이방성 도전 필름의 제조 방법, 접속체의 제조 방법 및 접속 방법

... 본 발명은 이방성 도전 필름을 사용한 접속에 있어서, 접속 후의 기판 휨의 저감을 도모하는 것을 목적으로 한다. 이방성 도전 필름(23)은 제1 절연성 접착제층(30)과, 제2 절연성 접착제층(31)과, 제1 절연성 접착제층(30) 및 제2 절연성 접착제층(31)에 끼움 지지되고, 도전성 입자(32)가 절연성 접착제(33)에 함유된 도전성 입자 함유층(34)을 갖고, 도전성 입자 함유층(34)과 제1 절연성 접착제층(30) 사이에 기포(41)가 함유되고, 도전성 입자 함유층(34)은 제2 절연성 접착제층(31)과 접하는, 도전성 입자(32)의 하부의 경화도가 다른 부위의 경화도보다도 낮은 것이다.

Microelectronic device chip including hybrid bump, package thereof, LCD apparatus having the same and method for fabricating the microelectronic device chip

Integrated circuit device having through-silicon via structure and method of manufacturing the same

플립 칩형 반도체 이면용 필름, 다이싱 테이프 일체형 반도체 이면용 필름, 반도체 장치의 제조 방법 및 플립 칩형 반도체 장치

... 본 발명은, 피착체 상에 플립 칩-접속된 반도체 소자의 이면에 형성하기 위한 플립 칩형 반도체 이면용 필름으로서, 파장 532nm 또는 1064nm에서의 광선 투과율이 20% 이하이고, 레이저 마킹한 후의 마킹부와 마킹부 이외 부분 간의 콘트라스트가 20% 이상인 플립 칩형 반도체 이면용 필름에 관한 것이다.

광반사성 이방성 도전 페이스트 및 발광 장치

... 발광 다이오드 소자 (LED) 등의 발광 소자를 배선판에 플립 칩 실장하여 발광 장치를 제조할 때에 사용하는 이방성 도전 페이스트로서, 제조 비용의 증대를 초래하는 광반사층을 LED 에 형성하지 않고 발광 효율을 개선하기 위해서 광반사성 절연 입자를 배합한 경우에, 고온 환경하에서의 발광 소자의 배선판에 대한 접착 강도의 저하를 억제할 수 있고, 또한 TCT 후에도 도통 신뢰성의 저하를 억제할 수 있는 광반사성 이방성 도전 페이스트는, 도전 입자 및 광반사성 절연 입자가 열경화성 수지 조성물에 분산되어 이루어지는 것이다. 열경화성 수지 조성물은, 에폭시 화합물과 열촉매형 경화제를 함유한다.

SEMICONDUCTOR STORAGE UNIT, PROCESS FOR MANUFACTURING THE SAME, AND METHOD OF FORMING PACKAGE RESIN

마주보는（ＦＡＣＥ­ＴＯ­ＦＡＣＥ, Ｆ2Ｆ） 하이브리드 구조를 갖는 집적 회로(ＩＣ), ＩＣ 조립체, ＩＣ 제품 및 이들을 제조하는 방법, 그리고 이를 위한 컴퓨터-판독가능 매체

... 재분배 층(RDL)을 포함하는 집적 회로(IC) 제품이 제공되며, 재분배 층(RDL)은 IC 내에서 전기적 정보를 하나의 위치로부터 또 하나의 위치로 분배하도록 구성된 적어도 하나의 전도성 층을 갖는다. RDL은 또한 복수의 와이어 본드 패드들 및 복수의 솔더 패드들을 포함한다. 복수의 솔더 패드들 각각은 RDL과 직접적으로 전기적 통신을 하는 솔더 가용성 물질을 포함한다.

반도체 패키지 및 반도체 패키지 모듈

... 범프를 통하여 회로 기판과 연결되는 반도체 패키지가 제공된다. 본 발명의 일 실시예에 따른 반도체 패키지는, 복수개의 접속 패드가 노출되도록 형성된 반도체 칩; 상기 각 접속 패드 상에 형성되며, 제1 필라부 및 상기 제1 필라부 상측에 형성되는 제1 솔더부를 포함하는 연결용 범프들; 상기 접속 패드 주변에서 상기 접속 패드의 상부 표면 보다 높은 위치에 형성되며, 솔더 유도부가 형성되어 있는 제2 필라부 및 상기 제2 필라부 상측에 형성되는 제2 솔더부를 포함하는 지지용 범프들;을 포함한다.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

AN ELECTRONIC DEVICE AND A METHOD OF MANUFACTURING THE SAME

SEMICONDUCTOR CHIP PACKAGE AND FABRICATING METHOD THEREOF

마이크로 전자 패키지

... 마이크로 전자 패키지(100)는 기판(102)과 마이크로 전자 요소(130)를 포함하며, 마이크로 전자 요소는 면(134)과 이 면에서 노출되는 컨택(132)의 하나 이상의 컬럼(138, 139)을 가지며, 컨택(132)이 기판의 표면(120)에서 노출되는 대응하는 컨택을 바라보고 이 컨택에 연결된다. 축면(140)은 제1 방향(142)으로 연장하는 라인을 따라 마이크로 전자 요소의 면을 교차하고, 요소 컨택(132)의 컬럼에 대하여 센터링될 수 있다. 패키지 단자의 컬럼(104A, 104B)은 제1 방향으로 연장할 수 있다. 제2 표면의 중앙 영역(112)에서 노출된 제1 단자는 마이크로 전자 요소 내의 어드레스 가능 메모리 지점을 결정하기 위해 이용할 수 있는 어드레스 정보를 전달하도록 구성될 수 있다. 중앙 영역(112)은 패키지 단자의 컬럼들 간의 최소 피치(150)의 3.5배보다 크지 않은 폭(152)을 가질 수 있다. 축면은 중앙 영역을 교차할 수 있다.

DEVICE AND METHOD FOR FORMING BUMP

ELECTRONIC DEVICE

이방성 도전 필름, 이방성 도전 필름의 제조 방법, 접속체의 제조 방법 및 접속 방법

... 본 발명은 이방성 도전 필름을 사용한 접속에 있어서, 접속 후의 기판 휨의 저감을 도모하는 것을 목적으로 한다. 이방성 도전 필름(23)은 제1 절연성 접착제층(30)과, 제2 절연성 접착제층(31)과, 제1 절연성 접착제층(30) 및 제2 절연성 접착제층(31)에 끼움 지지되고, 도전성 입자(32)가 절연성 접착제(33)에 함유된 도전성 입자 함유층(34)을 갖고, 도전성 입자 함유층(34)과 제1 절연성 접착제층(30) 사이에 기포(41)가 함유되고, 도전성 입자 함유층(34)은 제2 절연성 접착제층(31)과 접하는, 도전성 입자(32)의 하부의 경화도가 다른 부위의 경화도보다도 낮은 것이다.

PROCESS FOR PRODUCTION OF ELECTRONIC DEVICE, ELECTRONIC DEVICE, AND DEVICE FOR PRODUCTION OF ELECTRONIC DEVICE

ELECTROCONDUCTIVE PARTICLE PLACEMENT SHEET AND ANISOTROPIC ELECTROCONDUCTIVE FILM

이방 도전성 필름 및 접속 구조체

... 이방 도전성 필름 (1A, 1B) 이, 절연 접착제층 (10) 과 그 절연 접착제층 (10) 에 격자상으로 배치된 도전 입자 (P) 를 포함한다. 임의의 도전 입자 (P0) 와 그 도전 입자 (P0) 에 인접하는 도전 입자의 중심간 거리에 대해, 도전 입자 (P0) 와 가장 짧은 거리를 제 1 중심간 거리 (d1) 로 하고, 그 다음으로 짧은 거리를 제 2 중심간 거리 (d2) 로 한 경우에, 이들 중심간 거리 (d1, d2) 가, 각각 도전 입자의 입자경의 1.5 ∼ 5 배이고, 임의의 도전 입자 (P0) 와, 그 도전 입자 (P0) 와 제 1 중심간 거리에 있는 도전 입자 (P1) 와, 그 도전 입자 (P0) 와 제 1 중심간 거리 (d1) 또는 제 2 중심간 거리 (d2) 에 있는 도전 입자 (P2) 로 형성되는 예각 삼각형에 대해서, 도전 입자 (P0, P1) 를 통과하는 제 1 배열 방향 (L1) 에 대하여 직교하는 직선 (L0) 과, 도전 입자 (P1, P2) 를 통과하는 제 2 배열 방향 (L2) 이 이루는 예각의 각도 (α) 가 18 ∼ 35°이다. 이 이방 도전성 필름 (1A, 1B) 은, COG 접속에 있어서도 안정된 접속 신뢰성을 갖는다.

SHEET-LIKE UNDERFILL MATERIAL AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD

A sheet-like underfill material to be adhered on a circuit plane of a semiconductor wafer (6) whereupon bumps (5) are formed. The underfill material is composed of a base material (1) and an adhesive layer (2) peelably formed on the base material, and is adhered so that the bumps (5) penetrate the adhesive layer (2) and the bump top sections intrude into the base material (1). The base material (1) has a storage elastic modulus of 1.0x10^6-4.0x10^9Pa, a rupture stress of 1.0x10^5-2.0x10^8Pa, and a Yong's modulus of 1.0x10^7-1.1x10^10Pa, and the adhesive layer (2) has a storage elastic modulus of 1.0x10^4-1.0x10^7Pa, and a rupture stress of 1.0x10^3-3.0x10^7Pa. © KIPO & WIPO 2008 ...

ALUMINUM BUMP BONDING FOR FINE ALUMINUM WIRE

The invention includes a packaged semiconductor device in which the bond wires are bonded to the leads with an aluminum bump bond. The semiconductor device is mounted on a lIadframc having leads with a nickel plating. To form the bump bond between a fine aluminum wire, such as a 2 mil diameter wire, and the lead, an aluminum bump is bonded to the nickel plating and the wire is bonded to the bump. The bump is aluminum doped with nickel and is formed from a large diameter wire, such as a 6 mil diameter wire. © KIPO & WIPO 2009 ...

ELECTRONIC DEVICE AND METHOD OF MANUFACTURING SAME

The device of the invention comprises a semiconductor element, a first connection element, a first patterned electrically conductive layer and a second patterned electrically conductive layer. The device is further provided with an encapsulation that encapsulates all except the first conductive layer, which is part of the substrate. The device can be suitably made in that the second conductive layer is provided, in pre-patterned form, with a permeable isolating layer as a foil. © KIPO & WIPO 2007 ...

SEMICONDUCTOR CAPABLE OF REDUCING PARASITIC RESISTANCE AND PARASITIC INDUCTANCE

PURPOSE: A semiconductor is provided to improve electrical characteristic by having a plate conductive member contacting to two semiconductor chips. CONSTITUTION: A semiconductor device comprises a first transistor(2) and a second transistor(3). The first transistor and the second transistor comprise an input electrode, a first output electrode, and a second output electrode. The first output electrode and second output electrode of the first transistor are connected to the first output electrode and second output electrode of the second transistor. The first conductor element is connected to one end of first output electrode and the second output electrode of the second transistor respectively. The second conductor element(5) is connected to one end of first output electrode and the second output electrode of the first transistor respectively. The third conductor element(6) is connected to the other side of the second transistor. The first conductor element, and the second conductor member ...

Preparation method of semiconductor device, and semiconductor device

Solder bump/under bump metallurgy structure for high temperature applications

Solder bump structures, which comprise a solder bump on a UBM structure, are provided for operation at temperatures of 250 DEG C and above. According to a first embodiment, the UBM structure comprises layers of Ni-P, Pd-P, and gold, wherein the Ni-P and Pd-P layers act as barrier and/or solderable/bondable layers. The gold layer acts as a protective layer. According to second embodiment, the UBM structure comprises layers of Ni-P and gold, wherein the Ni-P layer acts as a diffusion barrier as well as a solderable/bondable layer, and the gold acts as a protective layer. According to a third embodiment, the UBM structure comprises: (i) a thin layer of metal, such as titanium or aluminum or Ti/W alloy; (ii) a metal, such as NiV, W, Ti, Pt, TiW alloy or Ti/W/N alloy; and (iii) a metal alloy such as Pd-P, Ni-P, NiV, or TiW, followed by a layer of gold. Alternatively, a gold, silver, or palladium bump may be used instead of a solder bump in the UBM structure.

Epoxy resin composition for sealing packing of semiconductor, semiconductor device, and manufacturing method thereof

An epoxy resin composition for a underfilling of a semiconductor comprising an epoxy resin, an acid anhydride, a curing accelerator and a flux agent as essential components, wherein the curing accelerator is a quaternary phosphonium salt, as well as a semiconductor device and manufacturing method employing the same.

Semiconductor device and process for manufacturing the same

A semiconductor device has a pad structure with a ring-shaped stress buffer layer between a metal pad and an under-bump metallization (UBM) layer. The stress buffer layer is formed of a dielectric layer with a dielectric constant less than 3.5, a polymer layer, or an aluminum layer. The stress buffer layer is a circular ring, a square ring, an octagonal ring, or any other geometric ring.

Adhesive film, and connection structure and connecting method for circuit member

Disclosed is an adhesive film wherein a conductive adhesive layer containing a conductive particle and an insulating adhesive layer are laminated. When this adhesive film is heated and pressed in the lamination direction under certain conditions, the value C/D obtained by dividing the area C of the major surface of the cured insulating adhesive layer by the area D of the major surface of the cured conductive adhesive layer is 1.2-3.0.

Semiconductor element and a producing method for the same, and a semiconductor device and a producing method for the same

A columnar bump formed of copper etc. is formed on a wiring film of a semiconductor chip through an interconnected film and an adhesive film in a wafer unit by electrolytic plating in which package formation is possible. An oxidation prevention film is formed of such as gold on an upper surface or a part of the upper surface and side surface. A wet prevention film of such as an oxide film is formed on the columnar bump side as needed. If this bump is soldered to the pad on a packaging substrate, solder gets wet in the whole region of the columnar bump upper surface and only a part of the side surface. Stabilized and reliable junction form can be thus formed. Moreover, since the columnar bump does not fuse, the distance between a semiconductor board and a packaging board is not be narrowed by solder.

Method and apparatus for forming bumps for semiconductor interconnections using a wire bonding machine

The present invention is a method and apparatus for forming a bump for semiconductor interconnect applications, such as reverse wire bonding or stud bumping for flip chip interconnections. The bump is formed by (1 ) ball bonding at the bump site, (2) raising the capillary a predetermined height after forming the ball bond with the wire paying out of the capillary tip, (3) moving the capillary laterally a predetermined distance, preferably in a direction toward the site of other end of the wire loop, if the bump is to be used as the platform for a stitch bond of a wire loop, (4) raising the capillary further, and (5) moving the capillary diagonally downwardly and in the opposite direction of the first lateral motion. The wire is then severed by raising the capillary, closing the clamps and raising the capillary again to snap the wire pigtail off at the bump.

Wafer bumping process

A wafer bumping process is provided with follows steps. First, a first UBM layer 206 is formed covering the passivation layer 204 of a wafer 200 and the bonding pads 202 of the wafer 200. A first patterned photoresist layer 208 having first openings 208a is formed over the first UBM layer 206, wherein the first openings 208a corresponds with the bonding pads 202 and exposes partial of the first UBM layer 206. The first openings 208a is filled with a second UBM layer 210. A second patterned photoresist layer 212 having second openings 212a is formed over the first photoresist layer 208, wherein the second opening 212a is larger than the first opening 208a, so that the second UBM layer 210 is exposed. The second openings 212a is filled with a solder material. The solder material is reflow to become ball bumps 214a.

Semiconductor package and method of manufacturing the same

A semiconductor package of an embodiment includes: a semiconductor chip having a signal input terminal and a signal output terminal; and a cap unit that is formed on the semiconductor chip. The cap unit includes a concave portion forming a hollow structure between the semiconductor chip and the cap unit, a first through electrode electrically connected to the signal input terminal, and a second through electrode electrically connected to the signal output terminal. Of the inner side surfaces of the concave portion, a first inner side surface and a second inner side surface facing each other are not parallel to each other.

Semiconductor device and method of forming pad layout for flipchip semiconductor die

A semiconductor device has a semiconductor die with a die pad layout. Signal pads in the die pad layout are located primarily near a perimeter of the semiconductor die, and power pads and ground pads are located primarily inboard from the signal pads. The signal pads are arranged in a peripheral row or in a peripheral array generally parallel to an edge of the semiconductor die. Bumps are formed over the signal pads, power pads, and ground pads. The bumps can have a fusible portion and non-fusible portion. Conductive traces with interconnect sites are formed over a substrate. The bumps are wider than the interconnect sites. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surfaces of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate.

Die encapsulation in oxide bonded wafer stack

Structures and methods of fabricating semiconductor wafer assemblies that encapsulate one or die in a cavity etched into an oxide bonded semiconductor wafer stack. The methods generally include the steps of positioning the die in the cavity, mechanically and electrically mounting the die to the wafer stack, and encapsulating the die within the cavity by bonding a lid wafer to the wafer stack in one of multiple ways. Semiconductor processing steps are applied to construct the assemblies (e.g., deposition, annealing, chemical and mechanical polishing, etching, etc.) and connecting the die (e.g., bump bonding, wire interconnecting, ultrasonic bonding, oxide bonding, etc.) according to the embodiments described above.

Thin NiB or CoB capping layer for non-noble metallic bonding landing pads

The invention relates to a substrate having at least one main surface comprising at least one non-noble metallic bonding landing pad covered by a capping layer thereby shielding the non-noble metallic bonding landing pad from the environment. This capping layer comprises an alloy, the alloy being NiB or CoB and containing an atomic concentration percentage of boron in the range of 10% to 50%.

Method for forming the package structure

A method for forming the package structure is provided. The method includes forming a die structure over a first surface of a first substrate, and forming a plurality of electrical connectors below a second surface of the first substrate. The method also includes forming a first protruding structure below the second surface of the first substrate, and the electrical connectors are surrounded by the first protruding structure. The method further includes forming a second protruding structure over a second substrate, and bonding the first substrate to the second substrate. The electrical connectors are surrounded by the second protruding structure, and the first protruding structure does not overlap with the second protruding structure.

SEMICONDUCTOR DEVICE PACKAGE AND MANUFACTURING METHOD THEREOF

Semiconductor device and method of depositing encapsulant along sides and surface edge of semiconductor die in embedded wlcsp

SEMICONDUCTOR DEVICE AND METHOD OF FORMING ATHIN WAFER WITHOUT A CARRIER

Abstract SEMICONDUCTOR DEVICE AND METHOD OFFORMING A THIN WAFER WITHOUT A CARRIERA semiconductor device has a conductive via in a first surface of a substrate. A first interconnect structure is formed over the first surface of the substrate. A first bump is formed over the first interconnect structure. The first bump is formed over or offset from the conductive via. An encapsulant is deposited over the first bump and first interconnect structure. A portion of the encapsulant is removed to expose the first bump. A portion of a second surface of the substrate is removed to expose theconductive via. The encapsulant provides structural support and eliminates the need for a separate carrier wafer when thinning the substrate. A second interconnect structure is formed over the second surface of the substrate. A second bump is formed over the first bump. A plurality of semiconductor devices can be stacked and electrically connected through the conductive via.(Figure 5) ...

PTFE SHEET AND METHOD FOR MOUNTING DIE

Semiconductor device and method of forming an embedded sop fan-out package

Film for flip chip type semiconductor back surface, and its use

IC chip with improved pillar bumps

An IC chip with improved pillar bumps is disclosed. The chip has a plurality of bond pads on its active surface. A plurality of under bump metallurgy pads (UBM pad) are boned on the bond pads for connecting pillar bumps. A high wettability solder layer is formed between the pillar bumps and the UBM pads so as to melt and wet bottom surface of the pillar bumps through reflowing for improving bonding strength of the pillar bumps.

FLUX COMPOSITION, FORMING METHOD OF ELECTRICAL CONNECTING STRUCTURE, ELECTRICAL CONNECTING STRUCTURE AND SEMICONDUCTOR DEVICE

Chip package

A chip package including a die, a package substrate, and multiple bumps is provided. The die has an active surface, multiple die pads, and a first passivation layer. The die pads are disposed on the active surface. The first passivation layer is disposed on the active surface and has multiple first openings exposing the die pads respectively. The package substrate has a substrate surface, multiple substrate pads, and a second passivation layer. The substrate pads are disposed on the substrate surface. The second passivation layer is disposed on the substrate surface and has a second opening exposing the substrate pads and part of the substrate surface. The bumps are disposed on the die pads respectively. Each bump is connected to one of the substrate pads by a compression bonding process. The die is electrically connected to the package substrate via the bumps. The distance from the first passivation layer to the substrate pads is smaller than 50 micrometer.

Double molded chip scale package

Chip scale semiconductor packages and methods for making and using the same are described. The chip scale semiconductor packages (CSPs) contain a die with an integrated circuit device, a patterned plating layer, and a second interconnect structure formed from a Cu etched substrate that has a portion of an upper surface connected to the patterned plating layer, a side surface, and a bottom surface. The die can be attached to the patterned plating layer by a first interconnect structure that uses wirebonding or that uses a flip chip attachment process. The CSP contains a double molded structure where a first molding layer encapsulates the die, the patterned plating layer, the first interconnect structure, and the upper surface of the second interconnect structure. The second molding layer encapsulates the side surface of the second interconnect structure without encapsulating the bottom surface of the second interconnect structure. With such a configuration, the second molding layer helps control warpage during the manufacturing process and no printed circuit board (PCB) substrate is needed when the package is used in an electronic device since the signal routing is performed by the second interconnect structure. Other embodiments are described.

Method for manufacture of integrated circuit package system with protected conductive layers for pads

A method for manufacture of an integrated circuit package system includes: providing an integrated circuit die having a contact pad; forming a protection cover over the contact pad; forming a passivation layer having a first opening over the protection cover with the first opening exposing the protection cover; developing a conductive layer over the passivation layer; forming a pad opening in the protection cover for exposing the contact pad having the conductive layer partially removed; and an interconnect directly on the contact pad and only adjacent to the protection cover and the passivation layer.

Method of forming cu pillar capped by barrier layer

A nickel barrier layer is formed on an upper sidewall surface of a Cu pillar. A mask layer with an opening for defining the Cu pillar window has an upper portion and a lower portion. The upper portion of the mask layer is removed after the formation of the Cu pillar so as to expose the upper sidewall surface of the Cu pillar. The nickel barrier layer is then deposited on the exposed sidewall surface of the Cu pillar followed by removing and the lower portion of the mask layer.

Microelectronic packages with dual or multiple-etched flip-chip connectors

A packaged microelectronic element includes a microelectronic element having a front surface and a plurality of first solid metal posts extending away from the front surface. A substrate has a major surface and a plurality of conductive elements exposed at the major surface and joined to the first solid metal posts. In particular examples, the conductive elements can be bond pads or can be second posts having top surfaces and edge surfaces extending at substantial angles away therefrom. Each first solid metal post includes a base region adjacent the microelectronic element and a tip region remote from the microelectronic element, the base region and tip region having respective concave circumferential surfaces. Each first solid metal post has a horizontal dimension which is a first function of vertical location in the base region and which is a second function of vertical location in the tip region.

Semiconductor-encapsulating adhesive, semiconductor-encapsulating film-form adhesive, method for producing semiconductor device, and semiconductor device

The present invention relates to a semiconductor-encapsulating adhesive, a semiconductor-encapsulating film-form adhesive, a method for producing a semiconductor device, and a semiconductor device. The present invention provides a semiconductor-encapsulating adhesive comprising (a) an epoxy resin, and (b) a compound formed of an organic acid reactive with an epoxy resin and a curing accelerator.

Semiconductor Device and Method of Forming RDL Wider than Contact Pad along First Axis and Narrower than Contact Pad Along Second Axis

A semiconductor device has a semiconductor die and first conductive layer formed over a surface of the semiconductor die. A first insulating layer is formed over the surface of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. An opening is formed in the second insulating layer over the first conductive layer. A second conductive layer is formed in the opening over the first conductive layer and second insulating layer. The second conductive layer has a width that is less than a width of the first conductive layer along a first axis. The second conductive layer has a width that is greater than a width of the first conductive layer along a second axis perpendicular to the first axis. A third insulating layer is formed over the second conductive layer and first insulating layer.

Film for flip chip type semiconductor back surface, dicing tape-integrated film for semiconductor back surface, process for producing semiconductor device, and flip chip type semiconductor device

The present invention relates to a film for flip chip type semiconductor back surface to be formed on a back surface of a semiconductor element flip chip-connected onto an adherend, in which the film for flip chip type semiconductor back surface before thermal curing has, at the thermal curing thereof, a volume contraction ratio within a range of 23° C. to 165° C. of 100 ppm/° C. to 400 ppm/° C.

High-frequency switch

According to one embodiment, a high-frequency switch includes a high-frequency switch IC chip. The high-frequency switch IC chip has a high-frequency switching circuit section including an input terminal, a plurality of switching elements, a plurality of high-frequency signal lines, and a plurality of output terminals. The input terminal is connected to each of the plurality of output terminals via each of the plurality of switching elements with the high-frequency signal lines having the same lengths. The plurality of output terminals are arranged on a surface at an outer periphery of the high-frequency switch IC chip. The input terminal is arranged on the surface of the high-frequency switch IC chip at the center of the high-frequency switch IC circuit section.

Mechanisms for forming copper pillar bumps using patterned anodes

The mechanisms of preparing bump structures described by using patterned anodes may simplify bump-making process, reduce manufacturing cost, and improve thickness uniformity within die and across the wafer. In addition, the mechanisms described above allow forming bumps with different heights to allow bumps to be integrated with elements on a substrate with different heights. Bumps with different heights expand the application of copper post bumps to enable further chip integration.

Semiconductor device having pad structure with stress buffer layer

A semiconductor device has a pad structure with a ring-shaped stress buffer layer between a metal pad and an under-bump metallization (UBM) layer. The stress buffer layer is formed of a dielectric layer with a dielectric constant less than 3.5, a polymer layer, or an aluminum layer. The stress buffer layer is a circular ring, a square ring, an octagonal ring, or any other geometric ring.

Semiconductor device and manufacturing method thereof

Semiconductor devices of embodiments include a plurality of solder bumps electrically connected on a plurality of electrode pads disposed on a semiconductor substrate in parallel at a pitch of 40 μm or less via under bump metals. The ratio of the diameter (the top diameter) of the portion of each solder bump most away from the semiconductor substrate and the diameter (the bottom diameter) of the bottom side of each solder bump is 1:1 to 1:4.

Semiconductor assembly and semiconductor package including a solder channel

Semiconductor packages connecting a semiconductor chip to an external device by bumps are provided. The semiconductor packages may include a connection pad on a semiconductor chip, a connecting bump on and configured to be electrically connected to the connection pad and a supporting bump on the semiconductor chip and configured to be electrically isolated from the connection pad. The connection bump may include a first pillar and a first solder ball and the supporting bump may include a second pillar and a second solder ball. The semiconductor packages may further include a solder channel in the second pillar configured to allow a portion of the second solder ball to extend into the solder channel along a predetermined direction.

Semiconductor device, method for forming the same, and data processing system

A semiconductor device includes a semiconductor substrate, a first interlayer insulating film over the semiconductor substrate, a first interconnect over the first interlayer insulating film, and a via plug penetrating the semiconductor substrate and the first interlayer insulating film. The via plug is coupled to the first interconnect.

Microelectronic assemblies having compliancy and methods therefor

A microelectronic assembly is disclosed that includes a semiconductor wafer with contacts, compliant bumps of dielectric material overlying the first surface of the semiconductor wafer, and a dielectric layer overlying the first surface of the semiconductor wafer and edges of the compliant bumps. The compliant bumps have planar top surfaces which are accessible through the dielectric layer. Conductive traces may be electrically connected with contacts and extend therefrom to overlie the planar top surfaces of the compliant bumps. Conductive elements may overlie the planar top surfaces in contact with the conductive traces.

Structures and methods for improving solder bump connections in semiconductor devices

Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The structure includes a trench formed in a dielectric layer which has at least a portion thereof devoid of a fluorine boundary layer. The structure further includes a copper wire in the trench having at least a bottom portion thereof in contact with the non-fluoride boundary layer of the trench. A lead free solder bump is in electrical contact with the copper wire.

Semiconductor Device and Method of Forming an Inductor Within Interconnect Layer Vertically Separated from Semiconductor Die

A semiconductor device has an adhesive layer formed over a carrier. A semiconductor die has bumps formed over an active surface of the semiconductor die. The semiconductor die is mounted to the carrier with the bumps partially disposed in the adhesive layer to form a gap between the semiconductor die and adhesive layer. An encapsulant is deposited over the semiconductor die and within the gap between the semiconductor die and adhesive layer. The carrier and adhesive layer are removed to expose the bumps from the encapsulant. An insulating layer is formed over the encapsulant. A conductive layer is formed over the insulating layer in a wound configuration to exhibit inductive properties and electrically connected to the bumps. The conductive layer is partially disposed within a footprint of the semiconductor die. The conductive layer has a separation from the semiconductor die as determined by the gap and insulating layer.

Bonding pad structure and integrated circuit comprising a plurality of bonding pad structures

A bonding pad structure positioned on an integrated circuit includes a connecting pad, an insulation layer and a gold bump. The connecting pad is formed on the integrated circuit. The insulation layer is formed on the connecting pad, where the insulation layer has only one opening and a shape of the opening includes at least a bend. The gold bump is formed on the insulation layer, where the gold bump is electrically connected to the connecting pad through the opening of the insulation layer.

Semiconductor device and substrate

A semiconductor device of the invention include a rectangular semiconductor element mounted on a substrate formed with an external input terminal, an external output terminal, and a plurality of wiring patterns connected to each of the external input terminal and the external output terminal. The semiconductor element comprises, a plurality of first electrodes formed along a first edge of a surface thereof, a plurality of second electrodes formed along an edge opposite to the first edge of the surface, a plurality of third electrodes formed in the neighborhood of a functional block, and an internal wiring for connecting the first electrodes and the third electrodes. The substrate comprises, a first wiring pattern for connecting the external input terminal and the first electrodes, a second wiring pattern for connecting the external output terminal and the second electrodes, and a third wiring pattern for connecting the first electrodes and the third electrodes.

Semiconductor device and assembling method thereof

A semiconductor device and an assembling method thereof are provided. The semiconductor device includes a chip, a carrier, a plurality of first conductive elements and a plurality of second conductive elements. The chip has a plurality of first pads. The carrier has a plurality of second pads. The second pads correspond to the first pads. Each first conductive element is disposed between one of the first pads and one of the second pads. Each second conductive element is disposed between one of the first pads and one of the second pads. A volume ratio of intermetallic compound of the second conductive elements is greater than a volume ratio of intermetallic compound of the first conductive elements.

Packaging substrate with conductive structure

A packaging substrate with conductive structure is provided, including a substrate body having at least one conductive pad on a surface thereof, a stress buffer metal layer disposed on the conductive pad and a thickness of the stress buffer metal layer being 1-20 μm, a solder resist layer disposed on the substrate body and having at least one opening therein for correspondingly exposing a portion of top surface of the stress buffer metal layer, a metal post disposed on a central portion of the surface of the stress buffer metal layer, and a solder bump covering the surfaces of the metal post. Therefore, a highly reliable conductive structure is provided, by using the stress buffer metal layer to release thermal stresses, and using the metal post and the solder bump to increase the height of the conductive structure.

Compliant spring interposer for wafer level three dimensional (3d) integration and method of manufacturing

The present invention is an apparatus for integrating multiple devices. The apparatus includes a substrate having a first via and a second via, a semiconductor chip positioned on a top portion of the substrate and positioned between the first via and the second via, first and second bumps positioned on the semiconductor chip, and an interposer wafer having a first interposer spring assembly and a second interposer spring assembly, the first interposer spring assembly having a first interposer spring and a first electrical connection attached to the first interposer spring, and the second interposer spring assembly having a second interposer spring and a second electrical connection attached to the second interposer spring.

Semiconductor device and method of fabricating the semiconductor device

A semiconductor device includes a first device including a first substrate and a first external connection terminal for connecting outside the first device; a second device stacked on the first device, the second device including a second substrate and a second external connection terminal for connecting outside the second device; an adhesive pattern disposed between the first device and second device, the adhesive pattern disposed in locations other than locations where the first external connection terminal and second external connection terminal are disposed, and the adhesive pattern causing the first device and second device, when stacked, to be spaced apart by a predetermined distance; and a plated layer disposed between and electrically and physically connecting the first external connection terminal and the second external connection terminal.

Semiconductor Device and Method of Forming Narrow Interconnect Sites on Substrate with Elongated Mask Openings

A semiconductor device has a semiconductor die with a plurality of bumps formed over a surface of the semiconductor die. A plurality of conductive traces is formed over a surface of the substrate with interconnect sites. A masking layer is formed over the surface of the substrate. The masking layer has a plurality of parallel elongated openings each exposing at least two of the conductive traces and permitting a flow of bump material along a length of the plurality of conductive traces within the plurality of elongated openings while preventing the flow of bump material past a boundary of the plurality of elongated openings. One of the conductive traces passes beneath at least two of the elongated openings. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surface of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate.

Electroconductive bonding material, method for bonding conductor, and method for manufacturing semiconductor device

An electro-conductive bonding material includes: metal components of a high-melting-point metal particle that have a first melting point or higher; a middle-melting-point metal particle that has a second melting point which is first temperature or higher, and second temperature or lower, the second temperature is lower than the first melting point and higher than the first temperature; and a low-melting-point metal particle that has a third melting point or lower, the third melting point is lower than the first temperature.

Wireless ic device and electronic apparatus

A wireless IC device that is miniaturized, allows simple and low-cost mounting of a wireless IC, and eliminates the possibility of damage occurring to the wireless IC due to static electricity, and an electronic apparatus equipped with the wireless IC device, includes a wireless IC chip that processes transmission and reception signals, and a feeder circuit substrate that includes a resonant circuit having an inductance element. Feeder electrodes are provided on a surface of the feeder circuit substrate and are electromagnetically coupled to the resonant circuit. The feeder electrodes and are electromagnetically coupled to radiation plates and provided for a printed wiring board. The wireless IC chip is activated by a signal received by the radiation plates and a response signal from the wireless IC chip is radiated outward from the radiation plates.

Semiconductor Device and Method of Forming a Wafer Level Package Structure Using Conductive Via and Exposed Bump

A semiconductor device has a carrier. A semiconductor wafer including a semiconductor die is mounted to the carrier with an active surface of the semiconductor die facing away from the carrier. A plurality of bumps is formed over the active surface of the semiconductor die. An opening is formed in a periphery of the semiconductor die. An encapsulant is deposited over the carrier and semiconductor die, in the opening, and around the plurality of bumps such that an exposed portion of the plurality of bumps is devoid of encapsulant. A conductive via is formed through the encapsulant, within the opening, and extends to the carrier. A conductive layer is formed over the encapsulant and electrically connects to the conductive via and the exposed portion of the plurality of bumps. The carrier is removed to expose an end of the conductive via.

Semiconductor device and manufacturing method of the same

A semiconductor device, includes: a wiring substrate, a stacked body mounted on the wiring substrate, an underfill layer filled into gaps between respective semiconductor chips of the stacked body; and a molding body made up of a molding resin covered and formed at outside of the stacked body and so on. The underfill layer is made up of a cured product of a resin material containing an amine-based curing agent, and the cured product has a Tg of 65° C. or more and 100° C. or less.

Semiconductor Device and Method of Making a Semiconductor Device

A semiconductor device and a method of manufacturing a semiconductor device are disclosed. An embodiment comprises forming a bump on a die, the bump having a solder top, melting the solder top by pressing the solder top directly on a contact pad of a support substrate, and forming a contact between the die and the support substrate.

Method of manufacturing chip-stacked semiconductor package

A method of manufacturing a chip-stacked semiconductor package, the method including preparing a base wafer including a plurality of first chips each having a through-silicon via (TSV); bonding the base wafer including the plurality of first chips to a supporting carrier; preparing a plurality of second chips; forming stacked chips by bonding the plurality of second chips to the plurality of first chips; sealing the stacked chips with a sealing portion; and separating the stacked chips from each other.

Electrode arrays and methods of fabricating the same using printing plates to arrange particles in an array

Electrode arrays and methods of fabricating the same using a printing plate to arrange conductive particles in alignment with an array of electrodes are provided. In one embodiment, a semiconductor device comprises: a semiconductor topography comprising an array of electrodes disposed upon a semiconductor substrate; a dielectric layer residing upon the semiconductor topography; and at least one conductive particle disposed in or on the dielectric layer in alignment with at least one of the array of electrodes.

Layered chip package and method of manufacturing same

A layered chip package includes a main body and wiring. The main body includes: a main part having a top surface and a bottom surface and including three or more layer portions stacked on one another; a plurality of first terminals disposed on the top surface of the main part; and a plurality of second terminals disposed on the bottom surface of the main part. Each layer portion includes a semiconductor chip having first and second surfaces, and a plurality of electrodes electrically connected to the wiring. The plurality of electrodes are disposed on a side of the first surface of the semiconductor chip. A first layer portion located closest to the top surface of the main part and a second layer portion located closest to the bottom surface of the main part are arranged so that the second surfaces of their respective semiconductor chips face toward each other. The plurality of first terminals are formed by using the plurality of electrodes of the first layer portion. The plurality of second terminals are formed by using the plurality of electrodes of the second layer portion.

Method for producing reconstituted wafers and method for producing semiconductor devices

In order to provide a method for producing semiconductor devices that can use the highly productive W to W method, and achieve a high yield, a method for producing semiconductor devices comprises a step (S 401 ) in which a reconstituted wafer is prepared by replacing defective chips with non-defective chips, a step (S 403 ) in which the reconstituted wafer and the base wafer are connected to one another by laminating, a step (S 406 ) in which through-electrodes are formed in the reconstituted wafer, and a step (S 409 ) in which a separate reconstituted wafer is laminated onto and connected to the reconstituted wafer having through-electrodes.

Low profile package and method

In a method aspect, a multiplicity of ICs are attached to routing on a structurally supportive carrier (such as a wafer). The dice are encapsulated and then both the dice and the encapsulant layer are thinned with the carrier in place. A second routing layer is formed over the first encapsulant layer and conductive vias are provided to electrically couple the first and second routing layers as desired. External I/O contacts (e.g. solder bumps) are provided to facilitate electrical connection of the second routing layer (or a subsequent routing layer in stacked packages) to external devices. A contact encapsulant layer is then formed over the first encapsulant layer and the second routing layer in a manner that embeds the external I/O contacts at least partially therein. After the contact encapsulant layer has been formed, the carrier itself may be thinned significantly and singulated to provide a number of very low profile packages. The described approach can also be used to form stacked multi-chip packages.

Semiconductor chip and flip-chip package comprising the same

A semiconductor chip includes stress-relief to mitigate the effects of differences in coefficients of thermal expansion (CTE) between a printed circuit board (PCB) and a semiconductor chip and a flip-chip package including the semiconductor chip. The semiconductor chip includes a stress-relief buffer coupling a bump and a semiconductor chip pad.

TCE Compensation for Package Substrates for Reduced Die Warpage Assembly

A method for assembling die packages includes attaching contacts on a first side of a plurality of first die to substrate pads on a top surface of a composite carrier. The composite carrier includes a package substrate including at least one embedded metal layer having its bottom surface secured to a semiconductor wafer. The composite carrier minimizes effects of the CTE mismatch between the die and the package substrate during assembly reduces warpage of the die. After the attaching, the semiconductor wafer is removed from the package substrate. Electrically conductive connectors are attached to the bottom surface of the package substrate, and the package substrate is sawed to form a plurality of singulated die packages.

Three dimensional semiconductor assembly board with bump/flange supporting board, coreless build-up circuitry and built-in electronic device

A semiconductor assembly board includes a supporting board, a coreless build-up circuitry and a built-in electronic device. The supporting board includes a bump, a flange and a via hole in the bump. The built-in electronic device extends into the via hole and is electrically connected to the build-up circuitry. The build-up circuitry extends from the flange and the built-in electronic device and provides signal routing for the built-in electronic device. The supporting board provides mechanical support, ground/power plane and heat sink for the coreless build-up circuitry.

Solder cap bump in semiconductor package and method of manufacturing the same

A semiconductor package with improved height uniformity of solder cap bumps therein is disclosed. In one embodiment, the semiconductor package includes a semiconductor substrate comprising a plurality of pads spacedly disposed on a top surface of the substrate, and a passivation layer formed on top of the pads, wherein a plurality of pad openings are created to expose at least a portion of the pads; a plurality of solder cap bumps formed at the pad openings of the passivation layer; and a carrier substrate having a plurality of bond pads electrically connected to the solder caps of the solder cap bumps on the semiconductor substrate. The solder cap bump includes a solder cap on top of a conductive pillar, and a patternable layer can be coated and patterned on a top surface of the conductive pillar to define an area for the solder ball to be deposited. The deposited solder ball can be reflowed to form the solder cap.

Semiconductor Device and Method of Forming Interposer Frame Electrically Connected to Embedded Semiconductor Die

A semiconductor device has an interposer frame mounted over a carrier. A semiconductor die has an active surface and bumps formed over the active surface. The semiconductor die can be mounted within a die opening of the interposer frame or over the interposer frame. Stacked semiconductor die can also be mounted within the die opening of the interposer frame or over the interposer frame. Bond wires or bumps are formed between the semiconductor die and interposer frame. An encapsulant is deposited over the interposer frame and semiconductor die. An interconnect structure is formed over the encapsulant and bumps of the first semiconductor die. An electronic component, such as a discrete passive device, semiconductor die, or stacked semiconductor die, is mounted over the semiconductor die and interposer frame. The electronic component has an I/O count less than an I/O count of the semiconductor die.

Method to form solder deposits and non-melting bump structures on substrates

Described is a method of forming a metal or metal alloy layer onto a substrate comprising the following steps i) provide a substrate including a permanent resin layer on top of at least one contact area and a temporary resin layer on top of the permanent resin layer, ii) contact the entire substrate area including the at least one contact area with a solution suitable to provide a conductive layer on the substrate surface and i) electroplate a metal or metal alloy layer onto the conductive layer.

Semiconductor Device and Method of Forming Interposer Frame Over Semiconductor Die to Provide Vertical Interconnect

A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame. The interposer is mounted over the carrier and first die with the conductive pillars disposed around the die. A cavity can be formed in the interposer frame to contain a portion of the first die. An encapsulant is deposited through the opening in the interposer frame over the carrier and first die. Alternatively, the encapsulant is deposited over the carrier and first die and the interposer frame is pressed against the encapsulant. Excess encapsulant exits through the opening in the interposer frame. The carrier is removed. An interconnect structure is formed over the encapsulant and first die. A second semiconductor die can be mounted over the first die or over the interposer frame.

Semiconductor Device and Method of Forming a Metallurgical Interconnection Between a Chip and a Substrate in a Flip Chip Package

A method for forming metallurgical interconnections and polymer adhesion of a flip chip to a substrate includes providing a chip having a set of bumps formed on a bump side thereof and a substrate having a set of interconnect points on a metallization thereon, providing a measured quantity of a polymer adhesive in a middle region of the chip on the bump side, aligning the chip with the substrate so that the set of bumps aligns with the set of interconnect points, pressing the chip and the substrate toward one another so that a portion of the polymer adhesive contacts the substrate and the bumps contact the interconnect points, and heating the bumps to a temperature sufficiently high to form a metallurgical connection between the bumps and the interconnect points.

METHOD OF MANUFACTURING GaN-BASED SEMICONDUCTOR DEVICE

A method of manufacturing a GaN-based semiconductor device includes the steps of: preparing a composite substrate including: a support substrate having a thermal expansion coefficient at a ratio of not less than 0.8 and not more than 1.2 relative to a thermal expansion coefficient of GaN; and a GaN layer bonded to the support substrate, using an ion implantation separation method; growing at least one GaN-based semiconductor layer on the GaN layer of the composite substrate; and removing the support substrate of the composite substrate by dissolving the support substrate. Thus, the method of manufacturing a GaN-based semiconductor device is provided by which GaN-based semiconductor devices having excellent characteristics can be manufactured at a high yield ratio.

Packaging Process Tools and Systems, and Packaging Methods for Semiconductor Devices

Packaging process tools and systems, and packaging methods for semiconductor devices are disclosed. In one embodiment, a packaging process tool for semiconductor devices includes a mechanical structure for supporting package substrates or integrated circuit die during a packaging process for the integrated circuit die. The mechanical structure includes a low thermal conductivity material disposed thereon.

Method of processing solder bump by vacuum annealing

A method includes vacuum annealing on a substrate having at least one solder bump to reduce voids at an interface of the at least one solder bump. A die is mounted over the substrate.

Bump structure and electronic packaging solder joint structure and fabricating method thereof

A bump structure includes a substrate, a pad, an electrode and a protruding electrode. The pad is disposed on the substrate. The electrode is formed by a first metal material and disposed on the pad. The protruding electrode is formed by a second metal material and disposed on the electrode, wherein a cross-sectional area of the protruding electrode is less than a cross-sectional area of the electrode.

Semiconductor Packaging Structure and Method

A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections.

Semiconductor device and method of manufacturing the same

A semiconductor device includes a first bump that is located over a surface of a semiconductor element, and is formed on a first bump formation face distanced from a back surface of the semiconductor element at a first distance, and a second bump that is located over the surface of the semiconductor element, and is formed on a second bump formation face distanced from the back surface of the semiconductor element at a second distance being longer than the first distance, the second bump having a diameter larger than a diameter of the first bump.

Flip-chip packaging techniques and configurations

Embodiments of the present disclosure flip-chip packaging techniques and configurations. An apparatus may include a package substrate having a plurality of pads formed on the package substrate, the plurality of pads being configured to receive a corresponding plurality of interconnect structures formed on a die and a fluxing underfill material disposed on the package substrate, the fluxing underfill material comprising a fluxing agent configured to facilitate formation of solder bonds between individual interconnect structures of the plurality of interconnect structures and individual pads of the plurality of pads and an epoxy material configured to harden during formation of the solder bonds to mechanically strengthen the solder bonds. Other embodiments may also be described and/or claimed.

Method and system for ultra miniaturized packages for transient voltage suppressors

A method of forming a silicon carbide transient voltage suppressor (TVS) assembly and a system for a transient voltage suppressor (TVS) assembly are provided. The transient voltage suppressor (TVS) assembly includes a semiconductor die including a contact surface on a single side of the die, the die further including a substrate comprising a layer of at least one of an electrical insulator material, a semi-insulating material, and a first wide band gap semiconductor having a conductivity of a first polarity, at least a TVS device including a plurality of wide band gap semiconductor layers formed on the substrate; a first electrode coupled in electrical contact with the TVS device and extending to the contact surface, and a second electrode electrically coupled to the substrate extending to the contact surface.

Probing Chips during Package Formation

A method includes bonding a first package component on a first surface of a second package component, and probing the first package component and the second package component from a second surface of the second package component. The step of probing is performed by probing through connectors on the second surface of the second package component. The connectors are coupled to the first package component. After the step of probing, a third package component is bonded on the first surface of the second package component.

Lead frame, semiconductor device, and method for manufacturing lead frame

A lead frame includes a plurality of leads defined by an opening extending in a thickness direction. An insulating resin layer fills the opening to entirely cover side surfaces of each lead and to support the leads. A first surface of each lead is exposed from a first surface of the insulating resin layer.

Substrate and semiconductor device

A substrate includes a base member having a predetermined thickness, and an electrode array provided in one surface in a thickness direction of the base member and having a plurality of electrodes arranged two-dimensionally in a plan view, and the electrode array includes a central portion and an incremental region provided around the central portion in the planar view and is formed so that a height of the electrodes in the incremental region gradually increase as approaching toward the central portion.

Cleaning Methods and Compositions

Methods and chemical solvents used for cleaning residues on metal contacts during a semiconductor device packaging process are disclosed. A chemical solvent for cleaning a residue formed on a metal contact may comprise a reactive inorganic component and a reactive organic component. The method may comprise spraying a semiconductor device with a chemical solvent at a first pressure, and spraying the semiconductor device with the chemical solvent at a second pressure less than the first pressure.

Bump-on-Trace Interconnect

Disclosed herein is a bump-on-trace interconnect with a wetted trace sidewall and a method for fabricating the same. A first substrate having conductive bump with solder applied is mounted to a second substrate with a trace disposed thereon by reflowing the solder on the bump so that the solder wets at least one sidewall of the trace, with the solder optionally wetting between at least half and all of the height of the trace sidewall. A plurality of traces and bumps may also be disposed on the first substrate and second substrate with a bump pitch of less than about 100 μm, and volume of solder for application to the bump calculated based on at least one of a joint gap distance, desired solder joint width, predetermined solder joint separation, bump geometry, trace geometry, minimum trace sidewall wetting region height and trace separation distance.

Method and structure of sensors and mems devices using vertical mounting with interconnections

A method and structure for fabricating sensor(s) or electronic device(s) using vertical mounting with interconnections. The method includes providing a resulting device including at least one sensor or electronic device, formed on a die member, having contact region(s) with one or more conductive materials formed thereon. The resulting device can then be singulated within a vicinity of the contact region(s) to form one or more singulated dies, each having a singulated surface region. The singulated die(s) can be coupled to a substrate member, having a first surface region, such that the singulated surface region(s) of the singulated die(s) are coupled to a portion of the first surface region. Interconnections can be formed between the die(s) and the substrate member with conductive adhesives, solder processes, or other conductive bonding processes.

Semiconductor Device and Method of Forming Guard Ring Around Conductive TSV Through Semiconductor Wafer

A semiconductor device has a plurality of conductive vias formed into a semiconductor wafer. An insulating lining is formed around the conductive vias and a conductive layer is formed over the insulating lining. A portion of the semiconductor wafer is removed so the conductive vias extend above a surface of the semiconductor wafer. A first insulating layer is formed over the surface of the semiconductor wafer and conductive vias. A first portion of the first insulating layer is removed and a second portion of the first insulating layer remains as guard rings around the conductive vias. A conductive layer is formed over the conductive vias. A second insulating layer is formed over the surface of the semiconductor wafer, guard rings, and conductive vias. A portion of the second insulating layer is removed to expose the conductive vias and a portion of the guard rings.

Semiconductor integrated circuit device

In semiconductor integrated circuit devices for vehicle use, an aluminum pad on a semiconductor chip and an external device are coupled to each other by wire bonding using a gold wire for the convenience of mounting. Such a semiconductor integrated circuit device, however, causes a connection failure due to the interaction between aluminum and gold in use for a long time at a relatively high temperature (about 150 degrees C.). A semiconductor integrated circuit device can include a semiconductor chip as a part of the device, an electrolytic gold plated surface film (gold-based metal plated film) provided over an aluminum-based bonding pad on a semiconductor chip via a barrier metal film, and a gold bonding wire (gold-based bonding wire) for interconnection between the plated surface film and an external lead provided over a wiring board (wiring substrate).

Sapphire substrate configured to form light emitting diode chip providing light in multi-directions, light emitting diode chip, and illumination device

A sapphire substrate configured to form a light emitting diode (LED) chip providing light in multi-directions, a LED chip and an illumination device are provided in the present invention. The sapphire substrate includes a growth surface and a second main surface opposite to each other. A thickness of the sapphire substrate is thicker than or equal to 200 micrometers. The LED chip includes the sapphire substrate and at least one LED structure. The LED structure is disposed on the growth surface and forms a first main surface where light emitted from with a part of the growth surface without the LED structures. At least a part of light beams emitted from the LED structure pass through the sapphire substrate and emerge from the second main surface. The illumination device includes at least one LED chip and a supporting base. The LED chip is disposed on the supporting base.

Semiconductor chip with expansive underbump metallization structures

Methods and apparatus to protect fragile dielectric layers in a semiconductor chip are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first polymer layer over a conductor pad of a semiconductor chip where the conductor pad has a first lateral dimension. An underbump metallization structure is formed on the first polymer layer and in ohmic contact with the conductor pad. The underbump metallization structure has a second lateral dimension greater than the first lateral dimension. A second polymer layer is formed on the first polymer layer with a first opening exposing at least a portion of the underbump metallization structure.

Simultaneous wafer bonding and interconnect joining

Disclosed are a microelectronic assembly of two elements and a method of forming same. A microelectronic element includes a major surface, and a dielectric layer and at least one bond pad exposed at the major surface. The microelectronic element may contain a plurality of active circuit elements. A first metal layer is deposited overlying the at least one bond pad and the dielectric layer. A second element having a second metal layer deposited thereon is provided, and the first metal layer is joined with the second metal layer. The assembly may be severed along dicing lanes into individual units each including a chip.

Semiconductor manufacturing method and semiconductor structure thereof

A semiconductor manufacturing method includes providing a carrier; forming a first photoresist layer; forming plural core portions; removing the first photoresist layer; forming a second photoresist layer; forming a plurality of connection portions, each of the plurality of connection portions includes a first connection layer and a second connection layer and connects to each of the core portions to form a hybrid bump, wherein each of the first connection layers comprises a base portion, a projecting portion and an accommodating space, each base portion comprises an upper surface, each projecting portion is protruded to the upper surface and located on top of each core portion, each accommodating space is located outside each projecting portion, the second connection layers cover the projecting portions and the upper surfaces, and the accommodating spaces are filled by the second connection layers; removing the second photoresist layer to reveal the hybrid bumps.

Semiconductor device including a buffer layer structure for reducing stress

A semiconductor device includes a semiconductor chip, wiring that is included in the semiconductor chip and has a coupling part between parts with different widths, a pad being formed above the wiring and in a position overlapping the coupling part, a bump being formed on the pad, a buffer layer being formed in a position between the coupling part and the pad so as to cover the entire coupling part, and inorganic insulating layers being formed between the wiring and the buffer layer and between the buffer layer and the pad, respectively. The buffer layer is made of a material other than resin and softer than the inorganic insulating layer

Semiconductor device including through via structures and redistribution structures

Semiconductor device including through via structure and redistribution structures is provided. The semiconductor device may include internal circuits on a first side of a substrate, a through via structure vertically penetrating the substrate to be electrically connected to one of the internal circuits, a redistribution structure on a second side of the substrate and electrically connected to the through via structure, and an insulating layer between the second side of the substrate and the redistribution structure. The redistribution structure may include a redistribution barrier layer and a redistribution metal layer, and the redistribution barrier layer may extend on a bottom surface of the redistribution metal layer and may partially surround a side of the redistribution metal layer.

Methods and Apparatus of Packaging Semiconductor Devices

Methods and apparatuses for wafer level packaging (WLP) semiconductor devices are disclosed. A redistribution layer (RDL) is formed on a first passivation layer in contact with a conductive pad over a surface of a die. The RDL layer is on top of a first region of the first passivation layer. A second passivation layer is formed on the RDL layer with an opening to expose the RDL layer, and over the first passivation layer. An under bump metallization (UBM) layer is formed over the second passivation layer in contact with the exposed RDL layer. A second region of the first passivation layer disjoint from the first region is determined by projecting an outer periphery of a solder ball or other connector onto the surface.

Methods and Apparatus for Package on Package Structures

A package-on-package (“PoP”) structure and a method of forming are provided. The PoP structure may be formed by forming a first set of electrical connections on a first substrate. A first material may be applied to the first set of electrical connections. A second substrate may be provided having a second set of electrical connections formed thereon. The first set of electrical connections of the first substrate having the epoxy flux applied may be contacted to the second electrical connections of the second substrate. A reflow process may be performed to electrically connect the first substrate to the second substrate. The epoxy flux applied to the first electrical connections of the first substrate may prohibit electrical bridges or shorts from forming during the reflow process.

Method of manufacturing semiconductor device

In a semiconductor device formed by mounting a chip laminate including a semiconductor chip having a small diameter and a semiconductor chip having a large diameter over the top surface of a substrate, an excessive stress is prevented from being added to a joint of the two semiconductor chips. By mounting a first semiconductor chip having a large diameter over a support substrate and thereafter mounting a second semiconductor chip having a small diameter over the first semiconductor chip, it is possible to: suppress the inclination and unsteadiness of the second semiconductor chip mounted over the first semiconductor chip; and hence inhibit an excessive stress from being added to a joint of the first semiconductor chip and the second semiconductor chip.

Bump Structure and Method of Forming Same

An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal bump on the under bump metallurgy feature, and a substrate trace on a substrate, the substrate trace coupled to the metal bump through a solder joint and intermetallic compounds, a ratio of a first cross sectional area of the intermetallic compounds to a second cross sectional area of the solder joint greater than forty percent.

Metal Bump and Method of Manufacturing Same

An embodiment bump structure includes a contact element formed on a substrate, a passivation layer overlying the substrate, the passivation layer having a passivation opening exposing the contact element a polyimide layer overlying the passivation layer, the polyimide layer having a polyimide opening exposing the contact element an under bump metallurgy (UMB) feature electrically coupled to the contact element, the under bump metallurgy feature having a UBM width, and a copper pillar on the under bump metallurgy feature, a distal end of the copper pillar having a pillar width, the UBM width greater than the pillar width.

Solder interconnect with non-wettable sidewall pillars and methods of manufacture

A solder interconnect structure is provided with non-wettable sidewalls and methods of manufacturing the same. The method includes forming a nickel or nickel alloy pillar on an underlying surface. The method further includes modifying the sidewall of the nickel or nickel alloy pillar to prevent solder wetting on the sidewall.

Flip packaging device

Disclosed is a flip chip packaging device and structure of interconnections between a chip and a substrate. In one embodiment, a flip chip packaging device can include: (i) a chip and a substrate; (ii) a plurality of first connecting structures and a plurality of second connecting structures that are aligned and configured to electrically connect the chip and the substrate; and (iii) where each of the plurality of first connecting structures comprises a first metal, and each of the plurality of second connecting structures comprises a second metal, and where a hardness of the first metal is less than a hardness of the second metal.

Semiconductor device

Semiconductor device A1 includes: first terminal 201A and second terminal 201B; first switching element 1A including first gate electrode 12A, first source electrode 13A and first drain electrode 14A; and second switching element 1B including second gate electrode 12B, second source electrode 13B and second drain electrode 14B. First switching element 1A and second switching element 1B are connected in series to each other between first terminal 201A and second terminal 201B. Semiconductor device A1 includes first capacitor 3A connected in parallel to first switching element 1A and second switching element 1B between first terminal 201A and second terminal 201B. First switching element 1A and second switching element 1B are aligned in y direction. First capacitor 3A overlaps with at least one of first switching element 1A and second switching element 1B as viewed in z direction. These arrangements serve to suppress surge voltage.

SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME

A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP. 118-. (canceled)19. A semiconductor device comprising:a semiconductor substrate having a first side extending along a first direction, a second side extending along the first direction and being opposite to the first side, a third side extending along a second direction perpendicular to the first direction, and a fourth side extending along the second direction and being opposite to the third side;a multilayer wiring structure formed over the semiconductor substrate;a first pad electrode, a second pad electrode and dummy patterns formed in an uppermost layer of the multilayer wiring structure;a first insulating film formed over the first pad electrode, the second pad electrode and the dummy patterns;a first opening and a second opening formed in the first insulating film and located over the first pad electrode and the second pad electrode, respectively; anda first bump electrode and a second bump electrode formed over the first insulating film and electrically connected to the first pad electrode and the second pad electrode through the first opening and the second opening, respectively,wherein the first pad electrode and the second pad electrode are located near the first side and are ...

Bump-on-Trace Structures with High Assembly Yield

A package includes first package component, which further includes a first metal trace at a surface of the first package component, with the first metal trace having a trace width measured in a direction perpendicular to a lengthwise direction of the first metal trace. The first package component further includes a second metal trace at the surface of the first package component. The first metal trace and the second metal trace are parallel to each other. A second package component is overlying the first package component, wherein the second package component includes a metal bump. A solder region bonds the metal bump to the first metal trace, wherein the solder region contacts a top surface and sidewalls of the first portion of the first metal trace. A ratio of a volume of the solder region to the trace width is between about 1,100 μmand about 1,300 μm. 1. A package comprising: 'a first metal trace at a surface of the first package component, wherein the first metal trace has a trace width, with the trace width being measured in a direction perpendicular to a lengthwise direction of the first metal trace;', 'a first package component comprising a first portion, wherein the first portion has a first width smaller than the trace width; and', 'a second portion and a third portion on opposite sides of the first portion, wherein the second portion and the third portion have second widths greater than the first width; and, 'a second package component over the first package component, wherein the second package component comprises a metal bump, and the metal bump comprisesa solder region bonding the metal bump to the first metal trace.2. The package of claim 1 , wherein the second widths are further greater than the trace width.3. The package of claim 1 , wherein the solder region contacts a first portion of the first metal trace claim 1 , and a ratio of a volume of the solder region to the trace width is between about 1 claim 1 ,100 μmand about 1 claim 1 ,300 μm.4. The ...

Light conversion device

A light conversion device includes a light-emitting unit, a photoelectric conversion unit, and an electroconductive bonding layer. Each of the light-emitting unit and the photoelectric conversion unit includes a first-type region and a second-type region opposite to the first-type region. The electroconductive bonding layer is disposed between the light-emitting unit and the photoelectric conversion unit for connecting the photoelectric conversion unit with the light-emitting unit. When the light conversion device is operated to receive a bias and an external light, the light-emitting unit generates a modulated light having a frequency different from that of the external light.

Semiconductor devices having through electrodes, methods of manufacturing the same, and semiconductor packages including the same

A semiconductor device includes a semiconductor layer having a first surface and a second surface, a through electrode penetrating the semiconductor layer and having a protruding portion that protrudes over the second surface of the semiconductor layer, a front-side bump disposed on the first surface of the semiconductor layer and electrically coupled to the through electrode, a passivation pattern including a first insulation pattern that surrounds a sidewall of the protruding portion of the through electrode and extends onto the second surface of the semiconductor layer and a second insulation pattern that covers the first insulation pattern and has an etch selectivity with respect to the first insulation pattern, and a back-side bump covering an end surface of the protruding portion of the through electrode and extending onto the passivation pattern.

STUD BUMP STRUCTURE FOR SEMICONDUCTOR PACKAGE ASSEMBLIES

A semiconductor package structure comprises a substrate, a die bonded to the substrate, and one or more stud bump structures connecting the die to the substrate, wherein each of the stud bump structures having a stud bump and a solder ball encapsulating the stud bump to enhance thermal dissipation and reduce high stress concentrations in the semiconductor package structure. 116.-. (canceled)17. A method of forming a stud bump structure in a package structure , comprising:providing a conductive wire;pressing one end of the conductive wire to a bond pad and melting the conductive wire end to form a stud bump on the bond pad;severing the other end of the conductive wire close above the stud bump; andsoldering a solder ball to a top surface of the stud bump, the solder ball encapsulating the stud bump.18. The method of forming a stud bump structure of claim 17 , wherein the conductive wire comprises aluminum claim 17 , aluminum alloy claim 17 , copper claim 17 , copper alloy claim 17 , gold claim 17 , or gold alloy.19. The method of forming a stud bump structure of claim 17 , wherein the pressing and melting the conductive wire to form a stud bump on the bond pad is performed by wire bonding tool.20. The method of forming a stud bump structure of claim 17 , wherein the pressing and melting the conductive wire to form a stud bump on the bond pad is performed by a stud bump bonder.21. The method of forming a stud bump structure of claim 17 , wherein the severing the other end of the conductive wire leaves a tail extending from the bond pad.22. The method of forming a stud bump structure of claim 17 , further comprising applying ultrasonic energy to form the stud bump.23. The method of forming a stud bump structure of claim 17 , wherein the stud bump is disposed at a corner of a die.24. A method for forming a package structure claim 17 , the method comprising:providing a die wherein the die has a first periphery region adjacent a first edge of the die and a second ...

Method and apparatus for manufacturing array device

A method for manufacturing an array device includes a placing step of providing a plurality of elements in an array on a first surface of a substrate, an element separating step of separating a plurality of element chips from one another so that each element chip includes one or more elements, an inspecting step of inspecting the plurality of elements, a removing step of removing any element chip of the plurality of element chips from the surface of the substrate on the basis of a result of the inspecting step, and a mounting step of, after the removing step, mounting an element of at least the elements other than an element of the element chip thus removed onto a mounting substrate by transfer from the substrate, the mounting substrate being different from the substrate.

Semiconductor device

A semiconductor device includes a protective layer, a redistribution pattern, a pad pattern and an insulating polymer layer. The protective layer may be formed on a substrate. The redistribution pattern may be formed on the protective layer. An upper surface of the redistribution may be substantially flat. The pad pattern may be formed directly on the redistribution pattern. An upper surface of the pad pattern may be substantially flat. The insulating polymer layer may be formed on the redistribution pattern and the pad pattern. An upper surface of the insulating polymer layer may be lower than the upper surface of the pad pattern. The semiconductor device may have a high reliability.

Bonding apparatus and bonding method

[Solution] A bonding device 10 for thermally bonding an electronic component 100 to a substrate 110 or to another electronic component via an adhesive material 112, the bonding device being provided with: a bonding tool 40 comprising a bonding distal-end portion 42 which includes a bonding surface 44 and tapered side surfaces 46 formed in a tapering shape becoming narrower toward the bonding surface 44, the bonding surface 44 having a first suction hole 50 for suction-attaching the electronic component 100 via an individual piece of a porous sheet 130, the tapered side surfaces 46 having second suction holes 52, 54 for suction-attaching the porous sheet 130; and a bonding control unit 30 which controls the first suction hole 50 and the second suction holes 52, 54 independently from each other.

Semiconductor Device and Method of Forming Build-Up Interconnect Structures Over a Temporary Substrate

A semiconductor device has a first build-up interconnect structure formed over a substrate. The first build-up interconnect structure includes an insulating layer and conductive layer formed over the insulating layer. A vertical interconnect structure and semiconductor die are disposed over the first build-up interconnect structure. The semiconductor die, first build-up interconnect structure, and substrate are disposed over a carrier. An encapsulant is deposited over the semiconductor die, first build-up interconnect structure, and substrate. A second build-up interconnect structure is formed over the encapsulant. The second build-up interconnect structure electrically connects to the first build-up interconnect structure through the vertical interconnect structure. The substrate provides structural support and prevents warpage during formation of the first and second build-up interconnect structures. The substrate is removed after forming the second build-up interconnect structure. A portion of the insulating layer is removed exposing the conductive layer for electrical interconnect with subsequently stacked semiconductor devices. 1. A method of making a semiconductor device , comprising:providing a substrate;forming a first interconnect structure over the substrate;disposing a first semiconductor die over the first interconnect structure;disposing the substrate over a carrier with the first semiconductor die oriented away from the carrier;depositing an encapsulant over the carrier, substrate, and first semiconductor die;forming a second interconnect structure over the encapsulant and semiconductor die; andremoving the substrate to expose the first interconnect structure after forming the second interconnect structure.2. The method of claim 1 , further including forming a conductive column over the first interconnect structure.3. The method of claim 2 , wherein the conductive column extends from the first interconnect structure to the second interconnect structure ...

Light emitting diode device and manufacturing method thereof

An LED device includes: a first semiconductor layer of a first type; a second semiconductor layer of a second type; a light emitting layer formed between the first semiconductor layer and the second semiconductor layer and configured to emit light; and a filter formed on the second semiconductor layer and configured to transmit light in the second wavelength band within the first wavelength band. The filter includes a defect layer, first refractive layers, and second refractive layers having a refractive index greater than a refractive index of the first refractive layers, the first refractive layers and the second refractive layers are formed alternately on one side and other side of the defect layer. A thickness of the defect layer is determined based on a center wavelength of the first wavelength band, a peak wavelength of the second wavelength band and a refractive index of the defect layer.

Semiconductor structure and method for forming the same

A semiconductor structure includes a first substrate, a metallic pad disposed over the first substrate, a dielectric structure disposed over the first substrate and exposing a portion of the metallic pad, a bonding structure disposed over and electrically connected to the metallic pad, a barrier ring surrounding the bonding structure, and a through-hole penetrating the first substrate and the dielectric structure. The bonding structure includes a bottom and a sidewall, the bottom of the bonding structure is in contact with the metallic pad, a first portion of the sidewall of the bonding structure is in contact with the dielectric structure, and a second portion of the sidewall of the bonding structure is in contact with the barrier ring.

STRUCTURES FOR BONDING A GROUP III-V DEVICE TO A SUBSTRATE

Various embodiments of the present application are directed towards a method for forming an integrated chip in which a group III-V device is bonded to a substrate, as well as the resulting integrated chip. In some embodiments, the method includes: forming a chip including an epitaxial stack, a metal structure on the epitaxial stack, and a diffusion layer between the metal structure and the epitaxial stack; bonding the chip to a substrate so the metal structure is between the substrate and the epitaxial stack; and performing an etch into the epitaxial stack to form a mesa structure with sidewalls spaced from sidewalls of the diffusion layer. The metal structure may, for example, be a metal bump patterned before the bonding or may, for example, be a metal layer that is on an etch stop layer and that protrudes through the etch stop layer to the diffusion layer. 1. An integrated chip comprising:a substrate comprising a semiconductor substrate, complementary metal-oxide-semiconductor (CMOS) devices on the semiconductor substrate, and an interconnect structure covering the semiconductor substrate and the CMOS devices;a mesa structure on the substrate and comprising semiconductor material;a bump structure between the substrate and the mesa structure, wherein the bump structure comprises conductive material; anda diffusion layer recessed into the mesa structure, between the bump structure and the mesa structure;wherein the diffusion layer comprises semiconductor and conductive material respectively from the mesa structure and the bump structure, andsidewalls of the diffusion layer are spaced from sidewalls of the mesa structure.2. The integrated chip according to claim 1 , further comprising:an etch stop layer on the mesa structure, between the mesa structure and the substrate, wherein the bump structure protrudes through the etch stop layer to the diffusion layer.3. The integrated chip according to claim 2 , wherein the bump structure wraps around an adjoining corner of ...

SEMICONDUCTOR DEVICE AND BUMP FORMATION PROCESS

A semiconductor device includes a semiconductor substrate. A pad region is disposed on the semiconductor substrate. A micro bump is disposed on the pad region. The micro bump has a first portion on the pad region and a second portion on the first portion. The first portion and the second portion have different widths. The first portion has a first width and the second portion has a second width. The first width is larger or smaller than the second width. The micro bump includes nickel and gold. The semiconductor device also includes a passivation layer overlying a portion of the pad region. 115.-. (canceled)16. A method of fabricating a semiconductor device , the method comprising:forming a first sacrificial layer over a semiconductor substrate;forming a first opening in the first sacrificial layer to expose a conductive pad over the semiconductor substrate;forming a conductive bump in the first opening;forming a barrier layer on sidewalls of the first opening and on a top surface of the conductive bump;forming a conductive cap in the first opening with the barrier layer interposing in between the conductive bump and the conductive cap; andremoving the first sacrificial layer.17. The method of fabricating the semiconductor device of claim 16 , wherein the forming the barrier layer comprises:forming the barrier layer on a top surface of the first sacrificial layer and in the first opening; andremoving a portion of the barrier layer on the top surface of the first sacrificial layer.18. The method of fabricating the semiconductor device of claim 17 , wherein the portion of the barrier layer on the top surface of the first sacrificial layer is removed by chemical mechanical planarization.19. The method of fabricating the semiconductor device of claim 16 , further comprising:forming a second sacrificial layer over the first sacrificial layer after the forming the conductive cap in the first opening;forming a second opening in the second sacrificial layer exposing a top ...

Metal pad modification

The present invention provides a structure. In an exemplary embodiment, the structure includes a base material, at least one metal pad, where a first surface of the metal pad is in contact with the base material, and a metal pedestal, where the metal pedestal is in contact with the metal pad, where a radial alignment of the metal pad is shifted by an offset distance, with respect to the metal pedestal, such that the metal pad is shifted towards a center axis of the base material, where a first dimension of the metal pad is smaller than a second dimension of the metal pad, where the second dimension is orthogonal to a line running from a center of the metal pad to the center axis of the base material, where the first dimension is parallel to the line.

Semiconductor package and method for manufacturing a semiconductor package

A semiconductor package includes at least one semiconductor element, an encapsulant, a first circuitry, a second circuitry and at least one first stud bump. The encapsulant covers at least a portion of the semiconductor element. The encapsulant has a first surface and a second surface opposite to the first surface. The first circuitry is disposed adjacent to the first surface of the encapsulant. The second circuitry is disposed adjacent to the second surface of the encapsulant. The first stud bump is disposed in the encapsulant, and electrically connects the first circuitry and the second circuitry. The first stud bump contacts the second circuitry directly.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device includes a first semiconductor substrate, a second semiconductor substrate, a first metal layer located on the first semiconductor substrate, a second metal layer located on the second semiconductor substrate, a third metal layer, a first alloy layer, and a second alloy layer. The third metal layer extends between the first metal layer and the second metal layer. The first alloy layer comprises components of the first and third metal layers, and is provided between the first metal layer and the third metal layer. The second alloy layer comprises components of the second and third metal layers, and is provided between the second metal layer and the third metal layer. At least one of the first metal the second metal layers projects into the third metal layer at a circumferential edge portion thereof. 1. A semiconductor device comprising:a first semiconductor substrate;a second semiconductor substrate facing the first semiconductor substrate;a first pad electrode disposed on a surface of the first semiconductor substrate facing the second semiconductor substrate;a second pad electrode disposed on a surface of the second semiconductor substrate facing the first semiconductor substrate;a first insulating layer disposed on an edge portion of the first pad electrode and the first semiconductor substrate;a second insulating layer disposed on an edge portion of the second pad electrode and the second semiconductor substrate;a first metal layer disposed over the first pad electrode and facing the second semiconductor substrate;a second metal layer disposed over the second pad electrode and facing the first semiconductor substrate;a third metal layer disposed between the first metal layer and the second metal layer;a first alloy layer disposed between the first metal layer and the third metal layer and comprising a component of the first metal layer and a component of the third metal layer; anda second alloy layer disposed between the second metal layer ...

DEVICE PACKAGING WITH SUBSTRATES HAVING EMBEDDED LINES AND METAL DEFINED PADS

Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing. 1. A method of forming an integrated circuit (IC) package substrate , the method comprising:laminating a first dielectric layer over a first metal feature;laser drilling a via in the dielectric layer to expose the first metal feature;laminating a permanent photodefinable layer over the first dielectric layer;patterning a pad into the permanent photodefinable layer, the pad disposed over the via;electrolytically plating a fill metal into the via and the pad;planarizing the fill metal to a top surface of the permanent photodefinable layer; andperforming a self-aligned plating of a surface finish metal over a top surface of the fill metal.2. The method of claim 1 , wherein filling the pad and via further comprises:depositing a catalyst on the permanent photodefinable layer;electrolessly plating a seed layer on the catalyst; andwherein the method further comprises removing the catalyst, with a wet chemical treatment, from the permanent photodefinable layer that is exposed when the fill metal is planarized.3. The method of claim 2 , wherein plating a surface finish metal over the fill metal further comprises: forming a catalyst on an exposed surface of the fill metal and plating one or more metal layers.4. A method of forming an integrated circuit (IC) package substrate claim 2 , the method comprising:laminating a first dielectric layer over a first metal feature;laser drilling a via in the dielectric layer to expose the first metal feature;laser patterning a trace in the dielectric laterally ...

Single-Shot Encapsulation

A semiconductor device includes a semiconductor wafer. A plurality of pillar bumps is formed over the semiconductor wafer. A solder is deposited over the pillar bumps. The semiconductor wafer is singulated into a plurality of semiconductor die after forming the pillar bumps while the semiconductor wafer is on a carrier. An encapsulant is deposited around the semiconductor die and pillar bumps while the semiconductor die remains on the carrier. The encapsulant covers an active surface of the semiconductor die between the pillar bumps. 1. A method of making a semiconductor device , comprising:providing a semiconductor wafer;forming a plurality of pillar bumps over the wafer;singulating the semiconductor wafer into a plurality of semiconductor die; anddepositing an encapsulant over the semiconductor die with the pillar bumps exposed from the encapsulant.2. The method of claim 1 , wherein the pillar bumps include solder caps.3. The method of claim 2 , wherein the solder caps include lead-free solder.4. The method of claim 1 , further including transfer-mounting the semiconductor die prior to depositing the encapsulant.5. The method of claim 1 , further including singulating the semiconductor die through the encapsulant.6. The method of claim 5 , further including singulating the semiconductor die with a plurality of semiconductor die packaged together.7. A method of making a semiconductor device claim 5 , comprising:providing a semiconductor die;forming a pillar bump over the semiconductor die;forming a solder cap over the pillar bump; anddepositing an encapsulant over the semiconductor die, pillar bump, and solder cap.8. The method of claim 7 , wherein a surface of the encapsulant is coplanar with a surface of the solder cap.9. The method of claim 7 , further including disposing the semiconductor die over a substrate after depositing the encapsulant claim 7 , wherein the encapsulant contacts the substrate.10. The method of claim 9 , further including reflowing the ...

Semiconductor Device and Method of Depositing Encapsulant Along Sides and Surface Edge of Semiconductor Die in Embedded WLCSP

A semiconductor device has a semiconductor wafer including a plurality of semiconductor die. An insulating layer is formed over the semiconductor wafer. A portion of the insulating layer is removed by LDA to expose a portion of an active surface of the semiconductor die. A first conductive layer is formed over a contact pad on the active surface of the semiconductor die. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is disposed over a carrier with the active surface of the semiconductor die offset from the carrier. An encapsulant is deposited over the semiconductor die and carrier to cover a side of the semiconductor die and the exposed portion of the active surface. An interconnect structure is formed over the first conductive layer. Alternatively, a MUF material is deposited over a side of the semiconductor die and the exposed portion of the active surface. 1. A method of making a semiconductor device , comprising:providing a substrate;disposing a semiconductor die over the substrate;depositing a first encapsulant over the substrate and semiconductor die; andsingulating the first encapsulant.2. The method of claim 1 , further including:depositing a second encapsulant over the semiconductor die; andsingulating the second encapsulant and substrate prior to depositing the first encapsulant.3. The method of claim 2 , further including depositing the second encapsulant between the semiconductor die and substrate.4. The method of claim 1 , further including removing a portion of the first encapsulant to form a recess in the first encapsulant adjacent to the substrate prior to singulating the first encapsulant.5. The method of claim 4 , further including removing the portion of the first encapsulant using laser direct ablation (LDA).6. The method of claim 1 , further including depositing a mold underfill between the semiconductor die and substrate.7. The method of claim 1 , further including disposing an interconnect ...

Electronic apparatus and method for fabricating the same

An electronic apparatus includes a first electronic part with a first terminal, a second electronic part with a second terminal opposite the first terminal, and a joining portion which joins the first terminal and the second terminal. The joining portion contains a pole-like compound extending in a direction in which the first terminal and the second terminal are opposite to each other. The joining portion contains the pole-like compound, so the strength of the joining portion is improved. When the first terminal and the second terminal are joined, the temperature of one of the first electronic part and the second electronic part is made higher than that of the other. A joining material is cooled and solidified in this state. By doing so, the pole-like compound is formed.

Semiconductor device

A light-emitting element according to the present invention includes a semiconductor light-emitting element having a front surface and a rear surface so that light is extracted from the rear surface, and having a first n-side electrode and a first p-side electrode on the front surface, and a support element having a conductive substrate having a front surface and a rear surface as well as a second n-side electrode and a second p-side electrode formed on the front surface of the conductive substrate, the first n-side electrode and the second n-side electrode, and the first p-side electrode and the second p-side electrode are so bonded to one another respectively that the semiconductor light-emitting element is supported by the support element in a facedown posture downwardly directing the front surface, and the support element has an n-side external electrode and a p-side external electrode formed on the rear surface of the conductive substrate, a conductive via passing through the conductive substrate from the front surface up to the rear surface for electrically connecting the second n-side electrode and the n-side external electrode and/or the second p-side electrode and the p-side external electrode with each other, and an insulating film formed between the via and the conductive substrate to cover the side surface of the via.

Package assembly

In some embodiments, the present disclosure relates to a package assembly having a bump on a first substrate. A molding compound is on the first substrate and contacts sidewalls of the bump. A no-flow underfill layer is on a conductive region of a second substrate. The no-flow underfill layer and the conductive region contact the bump. A mask layer is arranged on the second substrate and laterally surrounds the no-flow underfill layer. The no-flow underfill layer contacts the substrate between the conductive region and the mask layer.

Tall and fine pitch interconnects

Representative implementations of devices and techniques provide interconnect structures and components for coupling various carriers, printed circuit board (PCB) components, integrated circuit (IC) dice, and the like, using tall and/or fine pitch physical connections. Multiple layers of conductive structures or materials are arranged to form the interconnect structures and components. Nonwettable barriers may be used with one or more of the layers to form a shape, including a pitch of one or more of the layers.

MICROELECTRONIC DEVICE WITH SOLDER-FREE PLATED LEADS

A microelectronic device has a solder-free package lead extending through an electrically non-conductive package structure to an exterior of the microelectronic device. The package lead includes a pillar contacting a terminal on a die and extending partway through the package structure, and an external lead electrically coupled to the pillar and extending to an exterior of the microelectronic device. The package lead is free of a solder joint. The microelectronic device may be formed by forming an access cavity package structure, to expose the pillar, and forming the external lead by a plating process. The microelectronic device may be formed by providing an external lead lamina containing the external lead, and forming a plated metal joint by a plating process that connects the external lead to the pillar. 1. A microelectronic device , comprising:a die having a component surface;a package structure on the component surface, the package structure being electrically non-conductive; the package lead is electrically conductive;', 'the package lead includes a pillar electrically coupled to the die and extending partway through the package structure, the pillar being electrically conductive;', 'the package lead includes an external lead electrically coupled to the pillar and extending to the exterior of the microelectronic device, the package lead being electrically conductive; and', 'the package lead is free of tin, lead, indium, and bismuth., 'a package lead directly contacting the die and extending through the package structure to an exterior of the microelectronic device; wherein2. The microelectronic device of claim 1 , wherein the package structure extends further from the component surface than the pillar.3. The microelectronic device of claim 1 , wherein the package lead includes an interface layer between the pillar and the external lead claim 1 , the interface layer being electrically conductive.4. The microelectronic device of claim 3 , wherein the interface ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE

Provided is a technique for improving the durability of a semiconductor device. A semiconductor device includes a semiconductor substrate, an electrode on the semiconductor substrate, a solder-joining metal Him on the electrode, an oxidation-inhibiting metal film on the solder-joining metal film, and a solder layer on the oxidation-inhibiting metal film. The solder-joining metal film includes a first portion that does not overlap the oxidation-inhibiting metal film in plan view when the solder-joining metal film and the oxidation-inhibiting metal film are viewed from the oxidation-inhibiting metal film. 1. A semiconductor device comprising:a semiconductor substrate;an electrode on the semiconductor substrate;a solder-joining metal film on the electrode;an oxidation-inhibiting metal film on the solder joining metal film; anda solder layer on the oxidation-inhibiting metal film,wherein the solder-joining metal film includes a first portion that does not overlap the oxidation-inhibiting metal film in plan view when the solder-joining metal film and the oxidation-inhibiting metal film are viewed from the oxidation-inhibiting metal film.2. The semiconductor device according to claim 1 , further comprising an insulating film that covers the first portion in plan view when the solder-joining metal film and the oxidation-inhibiting metal film are viewed from the oxidation-inhibiting metal film.3. The semiconductor device according to claim 2 , whereinthe insulating film includes an opening extending through in a thickness direction of the insulating film, andthe solder-joining metal film and the oxidation-inhibiting metal film are located in the opening.4. The semiconductor device according to claim 3 , whereinthe opening includes an inner wall having a reverse stair shape, andthe inner wall includes a stair that covers the first portion.5. The semiconductor device according to claim 3 , wherein the opening includes an inner wall having a reverse tapered shape.6. The ...

Semiconductor Device and Method

In an embodiment, a device includes: a first reflective structure including first doped layers of a semiconductive material, alternating ones of the first doped layers being doped with a p-type dopant; a second reflective structure including second doped layers of the semiconductive material, alternating ones of the second doped layers being doped with a n-type dopant; an emitting semiconductor region disposed between the first reflective structure and the second reflective structure; a contact pad on the second reflective structure, a work function of the contact pad being less than a work function of the second reflective structure; a bonding layer on the contact pad, a work function of the bonding layer being greater than the work function of the second reflective structure; and a conductive connector on the bonding layer.

USING AN INTERCONNECT BUMP TO TRAVERSE THROUGH A PASSIVATION LAYER OF A SEMICONDUCTOR DIE

A semiconductor die, which includes a first semiconductor device, a first passivation layer, and a first interconnect bump, is disclosed. The first passivation layer is over the first semiconductor device, which includes a first group of device fingers. The first interconnect bump is thermally and electrically connected to each of the first group of device fingers. Additionally, the first interconnect bump protrudes through a first opening in the first passivation layer. 1. A semiconductor die comprising:a first semiconductor device having a first plurality of device fingers;a second semiconductor device having a second plurality of device fingers;a first passivation layer over the first semiconductor device; anda first interconnect bump thermally and electrically connected to each of the first plurality of device fingers and to each of the second plurality of device fingers, wherein the first interconnect bump protrudes through a first opening in the first passivation layer.2. The semiconductor die of further comprising a second passivation layer over the first semiconductor device claim 1 , wherein:the first passivation layer is over the second passivation layer;the first semiconductor device has a plurality of sub-cells, wherein each of the plurality of sub-cells has a corresponding portion of the first plurality of device fingers; andthe second passivation layer has a plurality of openings, wherein the first interconnect bump protrudes through each of the plurality of openings.3. The semiconductor die of wherein the second passivation layer comprises Silicon Dioxide.4. The semiconductor die of wherein a thickness of the second passivation layer adjacent to each of the plurality of openings is between 150 nanometers and 5500 nanometers.5. The semiconductor die of wherein the first interconnect bump is configured to conduct heat away from the first semiconductor device.6. The semiconductor die of wherein the first interconnect bump is configured to provide an ...

Bump Structures for Multi-Chip Packaging

A multi-chip package includes a substrate having a plurality of first bump structures. A pitch between first bump structures of the plurality of first bump structures is uniform across a surface of the substrate. The multi-chip package includes a first chip bonded to the substrate and a second chip bonded to the substrate. The first chip includes a plurality of second bump structures, and the plurality of second bump structures are bonded to a first set of first bump structures of the plurality of first bump structures. The second chip includes a plurality of third bump structures, and the plurality of third bump structures are bonded to a second set of first bump structures of the plurality of first bump structures. A pitch between second bump structures of the plurality of second bump structures is different from a pitch between third bump structures of the plurality of third bump structures. 1. A method of forming a multi-chip package , the method comprising:bonding a first chip to a substrate, wherein the substrate has a plurality of first bump structures, wherein the first chip comprises a plurality of second bump structures, and bonding the first chip to the substrate comprises covering at least two first bump structures of the plurality of first bump structures with a second bump structure of the plurality of second bump structures, each of the plurality of first bump structures being coupled to different contact pads; andbonding a second chip to the substrate, wherein the second chip comprises a plurality of third bump structures, and bonding the second chip to the substrate comprises bonding the plurality of third bump structures to corresponding ones of a set of first bump structures of the plurality of first bump structures.2. The method of claim 1 , wherein bonding the first chip to the substrate comprises covering an entirety of each sidewall of the at least two first bump structures.3. The method of claim 1 , wherein the at least two first bump ...

CONDUCTIVE CONNECTIONS, STRUCTURES WITH SUCH CONNECTIONS, AND METHODS OF MANUFACTURE

A solder connection may be surrounded by a solder locking layer () and may be recessed in a hole () in that layer. The recess may be obtained by evaporating a vaporizable portion () of the solder connection. Other features are also provided. 1. A manufacturing method comprising: one or more first components each of which comprises solder and a material sublimatable or vaporizable when the solder is melted; and', 'a first layer comprising a top surface and one or more holes in the top surface, each hole containing at least a segment of a corresponding first component;, 'obtaining a first structure comprisingheating each first component to sublimate or vaporize at least part of each sublimatable or vaporizable material and provide an electrically conductive connection at a location of each first component;wherein in the heating operation at least part of each first component recedes down from the top surface to provide or increase a recess in each hole at the top surface.2. The method of wherein each hole is a through-hole.3. The method of wherein each hole's sidewall is a dielectric sidewall.4. The method of wherein the first layer is dielectric.5. The method of wherein the first layer is formed by molding.6. The method of further comprising:obtaining a second structure with one or more protruding conductive posts; andinserting each conductive post into a corresponding recess provided or increased in the heating operation, and forming a solder bond in each recess between the corresponding conductive post and the corresponding electrically conductive connection.7. The method of wherein before the heating operation claim 1 , at least a segment of each first component either:comprises of a solder core coated with the sublimatable or vaporizable material; orconsists of the sublimatable or vaporizable material.8. The method of wherein in obtaining the first structure claim 7 , the one or more first components are formed before the first layer.9. The method of wherein in ...