СПОСОБ И УСТРОЙСТВО ДЛЯ ОЧИСТКИ, РАЗДЕЛЕНИЯ, МОДИФИКАЦИИ И/ИЛИ ИММОБИЛИЗАЦИИ ХИМИЧЕСКИХ ИЛИ БИОЛОГИЧЕСКИХ ОБЪЕКТОВ, НАХОДЯЩИХСЯ В ТЕКУЧЕЙ СРЕДЕ, И ОПОРА ИЗ МИКРОПРОВОЛОКИ

... 1. Устройство для очистки, разделения, модификации и/или иммобилизации химических или биологических объектов, находящихся в текучей среде, посредством связывания химического или биологического объекта с функциональным покрытием или лигандами, находящимися на поверхности опор из микропроволоки при отсутствии воздействия магнитного поля, создаемого между опорами из микропроволоки и частицами, находящимися в текучей среде, на разделение названных частиц, которое содержит по меньшей мере одну опору из микропроволоки, закрепленную своими концами и имеющую многослойную структуру, состоящую из центрального стержня и по меньшей мере одного покрывающего слоя и пригодную для связывания химических или биологических объектов, при этом поверхность микропроволоки модифицирована путем присоединения лигандов или нанесением на нее функционального покрытия. ! 2. Устройство по п.1, в котором центральный стержень и покрывающие слои выполнены из материала, выбранного из группы, включающей стеклянный, металлический ...

Substrat-Bondingstruktur und Substrat-Bondingverfahren

Eine Vorrichtung (2) ist auf einer Hauptoberfläche eines Substrats (1) ausgebildet. Die Hauptoberfläche des Substrats (1) ist über das Bonding-Bauteil (11, 12, 13) in einem hohlen Zustand an die Unterseite des Gegensubstrats (14) gebondet. Eine Schaltung (17) und eine Höckerstruktur (26) sind auf der Oberseite des Gegensubstrats (14) ausgebildet. Die Höckerstruktur (26) ist in einem Bereich positioniert, der zumindest dem Bonding-Bauteil (11, 12, 13) entspricht, und weist eine größere Höhe als diejenige der Schaltungsstruktur (17) auf.

Power converters with integrated capacitors

ELECTRONIC DEVICE WITH INTEGRATED CIRCUIT

ELECTRONIC DEVICE, ARRANGEMENT AND PROCEDURE FOR MANUFACTURING AN ELECTRONIC DEVICE

Adhesive composition, electronic component-mounted substrate using the adhesive composition, and semiconductor device

RF IC package for improving heat transfer rate and for reducing height and size of package and assembly method thereof

ELECTRONIC COMPONENT AND CHARGED PARTICLE BEAM IRRADIATION APPARATUS

An electronic component according to an embodiment includes: a first substrate including first through holes, a first substrate surface and a second substrate surface; first electrodes provided on each of the first through holes, and including a first end and a second end; second electrodes provided on each of the first through holes, facing each of the first electrodes, and including a third end facing the first end and a fourth end facing the second end; third electrodes connected to the first end and extending toward the third end; fourth electrodes connected to the second end and extending toward the fourth end; fifth electrodes connected to the third end, provided separately from each of the third electrodes and extending toward the first end; sixth electrodes connected to the fourth end, provided separately from each of the fourth electrodes and extending toward the second end.

RF 증폭기 패키지

An integrated circuit device package includes a substrate, a first die comprising active electronic components attached to the substrate, and package leads configured to conduct electrical signals between the first die and an external device. At least one integrated interconnect structure is provided on the first die opposite the substrate. The at least one integrated interconnect structure extends from the first die to an adjacent die attached to the substrate and/or to at least one of the package leads, and provides electrical connection therebetween. Related devices and power amplifier circuits are also discussed.

Semiconductor device and method of fabricating the same

A stack of semiconductor chips, a semiconductor device, and a method of manufacturing are disclosed. The second chip is over the first chip. The conductive bumps may extend between an upper surface of the first chip and a lower surface of the second chip. The homogeneous integral underfill material may be interposed between the first chip and the second chip, encapsulate the conductive bumps, and extend along sidewalls of the second chip. The homogeneous integral underfill material may have an upper surface extending in a direction parallel to an upper surface of the second chip and located adjacent the upper surface of the second chip. The molding material may be on outer side surfaces of the homogeneous integral underfill material above the upper surface of the first chip, wherein, in view of a first cross sectional profile, the molding material is separated from sidewalls of the second chip by the homogeneous integral underfill material such that the molding material does not contact ...

Semiconductor device with capacitor

A semiconductor device comprises a carrier substrate, an integrated circuit chip mounted on the carrier substrate via bumps, and a capacitor provided to stabilize operation of the integrated circuit chip at high frequencies. In the semiconductor device, the capacitor is electrically connected to pads on bottom of the integrated circuit chip, and the capacitor is provided to have a height on the carrier substrate that is smaller than or equal to a height of the bumps on the carrier substrate.

Wiring board with built-in electronic component and method for manufacturing the same

A wiring board with a built-in electronic component includes a substrate having cavity, an insulating layer formed on the substrate such that the insulating layer is covering the cavity, a conductor layer formed on the insulating layer, and an electronic component accommodated in the cavity and including a rectangular cuboid body and terminal electrodes such that each electrode has a metal film form formed on outer surface of the body, and via conductors formed in the insulating layer such that the via conductors are connecting the conductor layer and electrodes. The electrodes are arrayed in a matrix having rows and columns such that adjacent electrodes in row and column directions have the opposite polarities, and the conductor layer includes a line pattern shunting first group of the electrodes in one polarity and a solid pattern shunting second group of the electrodes in the other polarity.

Interposing structure

A capacitive interposer (caposer) is disposed inside an integrated circuit package between a die and an inside surface of the package. Conductive layers within the caposer constitute a bypass capacitor. In a through-hole caposer, micro-bumps on the die pass through through-holes in the caposer and contact corresponding landing pads on the package. As they pass through the caposer, power and ground micro-bumps make contact with the plates of the bypass capacitor. In a via caposer, power and ground micro-bumps on the die are coupled to power and ground landing pads on the package as well as to the plates of the bypass capacitor by power and ground vias that extend through the caposer. In signal redistribution caposer, conductors within the caposer redistribute signals between die micro-bumps and package landing pads. In an impedance matching caposer, termination structures within the caposer provide impedance matching to a printed circuit board trace.

SWITCHED POWER STAGE WITH INTEGRATED PASSIVE COMPONENTS

A scalable switching regulator architecture has an integrated inductor. In some embodiments an area and current drive capability of switches of the switching regulator is matched with an inductor built within an area above the switches. In some embodiments the combined switches and inductor are constructed as a unit cell and can be combined to form larger elements as required for higher current drive capability and multiphase operation.

MICROELECTRONIC ASSEMBLIES HAVING AN INTEGRATED CAPACITOR

Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a die having a first surface and an opposing second surface; a capacitor having a surface, wherein the surface of the capacitor is coupled to the first surface of the die; and a conductive pillar coupled to the first surface of the die. In some embodiments, a microelectronic assembly may include a capacitor in a first dielectric layer; a conductive pillar in the first dielectric layer; a first die having a surface in the first dielectric layer; and a second die having a surface in a second dielectric layer, wherein the second dielectric layer is on the first dielectric layer, and wherein the surface of the second die is coupled to the capacitor, to the surface of the first die, and to the conductive pillar. 1. A microelectronic assembly , comprising:a die having a first surface and an opposing second surface;a capacitor having a surface, wherein the surface of the capacitor is coupled to the first surface of the die; anda conductive pillar having a first end and an opposing second end, wherein the second end of the conductive pillar is coupled to the first surface of the die.2. The microelectronic assembly of claim 1 , wherein the die is a central processing unit claim 1 , a radio frequency chip claim 1 , a power converter claim 1 , or a network processor.3. The microelectronic assembly of claim 1 , wherein the die is a first die claim 1 , and further comprising:a second die having a first surface and an opposing second surface, wherein the second surface of the second die is coupled to the first surface of the first die.4. The microelectronic assembly of claim 3 , wherein the second die is a composite die.5. The microelectronic assembly of claim 1 , further comprising:a package substrate, wherein the first end of the conductive pillar is coupled to the package substrate.6. The microelectronic assembly of claim 5 , wherein the ...

MICROELECTRONIC ASSEMBLIES WITH COMMUNICATION NETWORKS

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate, a first die coupled to the package substrate with first interconnects, and a second die coupled to the first die with second interconnects, wherein the second die is coupled to the package substrate with third interconnects, a communication network is at least partially included in the first die and at least partially included in the second die, and the communication network includes a communication pathway between the first die and the second die.

Vertical inductor for WLCSP

Embodiments of the invention include a microelectronic device and methods of forming a microelectronic device. In an embodiment the microelectronic device includes a semiconductor die and an inductor that is electrically coupled to the semiconductor die. The inductor may include one or more conductive coils that extend away from a surface of the semiconductor die. In an embodiment each conductive coils may include a plurality of traces. For example, a first trace and a third trace may be formed over a first dielectric layer and a second trace may be formed over a second dielectric layer and over a core. A first via through the second dielectric layer may couple the first trace to the second trace, and a second via through the second dielectric layer may couple the second trace to the third trace.

PACKAGED VOLTAGE REGULATOR AND INDUCTOR ARRAY

Inductors packaged with a voltage regulator for an integrated circuit within the same package are deposited to a sufficient thickness to reduce resistance and improve the quality factor. Furthermore, the voltage regulator switches currents through the inductors at a relatively high frequency such that the overall size and inductances of the inductors may be reduced. As a consequence, integrating both the integrated circuits including a voltage regulator and associated inductor array in a single package is facilitated. Other embodiments are described and claimed.

SEMICONDUCTOR DEVICE

A semiconductor device includes a semiconductor component and a silicon-based passive component. The silicon-based passive component is stacked on the semiconductor component in a thickness direction of the semiconductor component.

Multilayer power, converter with devices having reduced lateral current

This disclosure relates to embodiments that include an apparatus that may comprise a first layer including a first plurality of active devices, a second layer including a second plurality of active devices, and/or a third layer including a plurality of passive devices and disposed between the first and the second layers. An active device of the first plurality of active devices and an active device of the second plurality of active devices may influence a state of charge of a passive device of the plurality of passive devices.

Flexible electronic structure

A flexible electronic structure 100 suitable for bonding with an external circuit (Figure 5, 500), comprises a flexible substrate 102, having a first surface 108, configured for bonding with the external circuit (Figure 5, 500), and an opposing second surface 112 configured for engagement with a bonding tool. The structure 100 comprises at least one electronic component 104; at least one contact member 106, operatively coupled with the electronic component 104 and provided the first surface 108 of the flexible substrate 102 and adapted to interface with the external circuit (Figure 5, 500) after bonding. The structure 100 also comprises at least one shield member 110, provided at the first surface 108 to shieldingly overlap a portion of the electronic component 104, and is adapted to withstand a predetermined pressure applied to said first surface 108 and/or said opposing second surface 112 during bonding with the external circuit (Figure 5, 500).

Integrated circuit package with embedded bridge

Die package with superposer substrate for passive components

A semiconductor die package 100 includes active circuitry 104 on a front side of a die 102, such as a system on chip (SoC) die or radio frequency (RF) die which includes a silicon substrate, and a separate component substrate 110 near a back side of the die to carry passive components 112 which may include high Q inductors, transformers, capacitors and resistors. The component substrate may be bump bonded to the back surface of the die. A conductive path, which may comprise a through silicon via (TSV) 116 connects passive components to the active circuitry on the die. A package substrate 106 may be positioned over the front side of the die and connected through a mold compound 108 to the die 102. A multi-die stack may include a second die on the opposite side of the component substrate to the first die (see Fig. 2; 222). The component substrate may extend laterally beyond the die allowing direct connection between the component substrate and package substrate by through mold vias (TMVs) ...

적층된 전자 디바이스들을 포함하는 전자 어셈블리

... 제 1 전자 디바이스를 포함하는 전자 어셈블리가 개시된다. 제 1 전자 디바이스는 상기 제 1 전자 디바이스의 후면으로 연장되는 캐비티를 포함한다. 전자 어셈블리는 제 2 전자 디바이스를 더 포함한다. 제 2 전자 디바이스는 제 1 전자 디바이스의 캐비티 내에서 제 1 전자 디바이스에 장착된다. 전자 어셈블리의 몇몇 예시적 형태에서, 제 1 전자 디바이스 및 제 2 전자 디바이스는 각각 다이이다. 전다 어셈블리의 다른 형태에서는 제 1 전자 디바이스 및 제 2 전자 디바이스 중 하나 만이 다이인 경우가 고려될 수 있음에 유의해야 한다. 전자 어셈블리의 몇몇 형태에서, 제 2 전자 디바이스는 제 1 전자 디바이스에 납땜된다.

Package substrate having an embedded via hole medium layer and method of forming same

Disclosed is a package substrate having an embedded via hole medium layer, comprising a mold-sealing layer having opposing first and second surfaces; a via-hole medium layer embedded in the mold-sealing layer and flush with the second surface; a circuit rewiring layer embedded in the mold-sealing layer formed above the via-hole medium layer for exposing the first surface therefrom; and a build-up layer formed on the second surface of the mold-sealing layer and electrically connecting to the via-hole medium layer. The formation of the build-up layer eliminates the necessity of a core board and thus helps decreasing the size of the overall package structure while increasing reliability of thermal cycling tests of the package due to the similar thermal coefficient of expansion between the via-hole medium layer and the silicon wafer. This invention further discloses a method of forming a package substrate having an embedded via-hole medium layer as described above.

Semiconductor package and method of forming same

Package apparatus and manufacturing method thereof

Multi terminal capacitor within input output path of semiconductor package interconnect

An integrated circuit (IC) device, e.g., wafer, chip, die, interposer, carrier, etc., includes a patterned mask that includes a first opening that exposes a signal region of a first contact. The mask further includes a second opening that exposes a signal region of a second contact that neighbors the first contact. The mask further includes a first capacitor tab opening that extends from the first opening toward the second contact and further exposes an extension region of the first contact. The mask further includes a second capacitor tab opening that extends from the second opening toward the first contact and further exposes an extension region of the second contact. A multi terminal capacitor may be connected to the IC device such that a first terminal is connected to the extension region of the first contact and a second terminal is connected to the extension region of the second contact.

Capacitor and semiconductor device and method for fabricating the semiconductor device

A capacitor comprises a first conducting film 12 formed on a substrate 10, a first dielectric film 14 formed on the first conducting film, a second conducting film 18 formed on the first dielectric film, a second dielectric film 22 formed above the second conducting film, covering the edge of the second conducting film, a third conducting film 34 formed above the second dielectric film, covering a part of the second dielectric film covering the edge of the second conducting film. The capacitor further comprises an insulation film 28 covering the edge of the second conducting film or the part of the second dielectric film. An effective thickness of the insulation film between the second conducting film and the third conducting film in the region near the edge of the second conducting film can be increased, whereby concentration of electric fields in the region near the edge of the second conducting film. Consequently, the capacitor can have large capacitance without lowering voltage resistance ...

Structure for mounting a semiconductor device and a capacitor device on a substrate

A semiconductor device-mounting substrate is provided with a semiconductor device, a capacitor device, and a wiring substrate. The wiring substrate has a space in which the capacitor device should be located, and the capacitor device is locate in the space. Terminals of a driving power supply wiring for the semiconductor device are provided on a surface of the space, and the terminals are connected with the capacitor device.

Semiconductor chip stack having improved encapsulation

A stack of semiconductor chips, a semiconductor device, and a method of manufacturing are disclosed. The stack of semiconductor chips may comprise a first chip of the stack, a second chip of the stack over the first chip, conductive bumps, a homogeneous integral underfill material, and a molding material. The conductive bumps may extend between an upper surface of the first chip and a lower surface of the second chip. The homogeneous integral underfill material may be interposed between the first chip and the second chip, encapsulate the conductive bumps, and extend along sidewalls of the second chip. The homogeneous integral underfill material may have an upper surface extending in a direction parallel to an upper surface of the second chip and located adjacent the upper surface of the second chip. The molding material may be on outer side surfaces of the homogeneous integral underfill material above the upper surface of the first chip, wherein, in view of a first cross sectional profile ...

Multi-Stacked Package-on-Package Structures

A multi-stacked package-on-package structure includes a method. The method includes: adhering a first die and a plurality of second dies to a substrate, the first die having a different function from each of the plurality of second dies; attaching a passive device over the first die; encapsulating the first die, the plurality of second dies, and the passive device; and forming a first redistribution structure over the passive device, the first die, and the plurality of second dies, the passive device connecting the first die to the first redistribution structure.

3D PILLAR INDUCTOR

Base pads are spaced by a pitch on a support surface. Conducting members, optionally Cu or other metal pillars, extend up from the base pads to top pads. A top pad interconnector connects the top pads in a configuration establishing an inductor current path between the base pads.

ASSEMBLY OF 2XD MODULE USING HIGH DENSITY INTERCONNECT BRIDGES

Embodiments disclosed herein include electronic package and methods of forming such packages. In an embodiment, an electronic package comprises a mold layer (121) and a first die (125A) embedded in the mold layer. In an embodiment, the first die comprises first pads (P1) at a first pitch and second pads (P2) at a second pitch. In an embodiment, the electronic package further comprises a second die (125B) embedded in the mold layer, where the second die comprises third pads (P3) at the first pitch and fourth pads (P4) at the second pitch. In an embodiment, a bridge die (127) is embedded in the mold layer, and the bridge die electrically couples the second pads to the fourth pads.

Spacer for die-to-die communication in an integrated circuit

A multi-die integrated circuit device and a method of fabricating the multi-die integrated circuit device involve a substrate.Two or more dice include components that implement functionality of the multi-die integrated circuit.The components include logic gates.The multi-die integrated circuit device also includes a spacer disposed between the substrate and each of the two or more dice.Each of the two or more dice makes direct electrical contact with the substrate without making direct electrical contact with the spacer through holes in the spacer.

RESONATOR DEVICE, ELECTRONIC APPARATUS, AND VEHICLE

3D 필러 인덕터

... 베이스 패드들이 지지 표면 상에서 피치만큼 이격된다. 전도성 부재들, 선택적으로 Cu 또는 다른 금속 필러들은, 베이스 패드들로부터 상단 패드들로 위로 연장된다. 상단 패드 인터커넥터는 베이스 패드들 사이에 인덕터 전류 경로를 설정하는 구성으로 상단 패드들을 연결한다.

SEMICONDUCTOR PACKAGE HAVING A SUPPORTING PLATE AND A METHOD FOR FORMING THE SAME CAPABLE OF SHORTENING A SIGNAL TRANSMISSION PATH

PURPOSE: A semiconductor package having a supporting plate and a method for forming the same are provided to secure a stable structure by using a support stand, a bonding layer, and nine semiconductor chips. CONSTITUTION: A first conductive connection(41) connects a first semiconductor chip and a substrate(3). A chip stack(9) has second semiconductor chips, and a first bonding layer(51) and a second bonding layer(53). The first bonding layer is thicker than the second bonding layer. The second bonding layer is formed between the second semiconductor chips(11,12,13,14). The first conductive connection penetrates the first bonding layer. COPYRIGHT KIPO 2013 ...

ADHESIVE COMPOSITION, ELECTRONIC COMPONENT-MOUNTED SUBSTRATE USING THE ADHESIVE COMPOSITION, AND SEMICONDUCTOR DEVICE

Semiconductor package assembly and method for forming the same

Semiconductor package and method for fabricating the same

A method for fabricating a semiconductor package is provided, including providing a carrier provided with a circuit layer and a blocking member, forming on the carrier a packaging layer having a first surface and a second surface opposing the first surface and encapsulating the circuit layer and the blocking member, with the first surface coupled with the carrier, and removing the carrier and the blocking member to form on the first surface of the packaging layer an opening for an electronic component to be provided therein. Before the electronic component is provided in the opening, the circuit layer and the electronic component can be tested in advance, in order to retire the defectives. Therefore, no defective electronic component will be provided in the opening, and such a defective semiconductor package will not be fabricated.

COMPONENT MAGNETIC SHIELDING FOR MICROELECTRONIC DEVICES

A microelectronic device may include a substrate, a component, a first plate, a second plate, and a shield. The component may be disposed at least partially within the substrate. The first plate may be disposed on a first side of the component. The second plate may be disposed on a second side of the component. The shield may be disposed around at least a portion of a periphery of the component.

MULTI-LAYER POWER CONVERTER WITH DEVICES HAVING REDUCED LATERAL CURRENT

An apparatus having a power converter circuit having a first active layer having a first set of active devices disposed on a face thereof, a first passive layer having first set of passive devices disposed on a face thereof, and interconnection to enable the active devices disposed on the face of the first active layer to be interconnected with the non-active devices disposed on the face of the first passive layer, wherein the face on which the first set of active devices on the first active layer is disposed faces the face on which the first set of passive devices on the first passive layer is disposed.

PACKAGED DIE STACKS WITH STACKED CAPACITORS AND METHODS OF ASSEMBLING SAME

A stacked-die and stacked-capacitor package vertically arranged capacitors to mirror a semiconductive-device stack. The stacked capacitor can be electrically coupled to one or more semiconductive devices in the stacked architecture.

Semiconductor Package and Method of Forming the Same

According to an exemplary embodiment, a semiconductor package is provided. The semiconductor package includes: a chip having a plurality of joint pads; a component having a plurality of metal caps on one side and having a grinded surface on the other side, wherein the metal caps are in contact with the joint pads of the chip.

Capacitor and semiconductor device and method for fabricating the semiconductor device

A capacitor comprises a first conducting film 12 formed on a substrate 10, a first dielectric film 14 formed on the first conducting film, a second conducting film 18 formed on the first dielectric film, a second dielectric film 22 formed above the second conducting film, covering the edge of the second conducting film, a third conducting film 34 formed above the second dielectric film, covering a part of the second dielectric film covering the edge of the second conducting film. The capacitor further comprises an insulation film 28 covering the edge of the second conducing film or the part of the second dielectric film. An effective thickness of the insulation film between the second conducting film and the third conducing film in the region near the edge of the second conducting film can be increased, whereby concentration of electric fields in the region near the edge of the second conducting film. Consequently, the capacitor can have large capacitance without lowering voltage resistance ...

Capacitor having an anodic metal oxide substrate

In one embodiment, a structure and method including an anodic metal oxide substrate used to form a capacitor are described herein.

Wiring substrate for mounting semiconductor components

There is disclosed a wiring board comprising a core substrate 110, a build-up layer 130 a formed on at least one side of main surfaces the core substrate, wherein a cavity 120 for accommodating a chip-type decoupling capacitor 121 is formed in the build-up layer 130 a. The capacitor 121 includes electrode terminals on an upper surface thereof that are directly connected to a semiconductor component, and electrode terminals on a back surface of the capacitor 121 is connected to a wiring conductor layer 132 a on a bottom surface of the cavity 120. This structure enables decoupling capacitor and the semiconductor component 260 to be connected with low resistance and low inductance.

Multi-die fine grain integrated voltage regulation

A semiconductor device package is described that includes a power consuming device (such as an SOC device). The power consuming device may include one or more current consuming elements. A passive device may be coupled to the power consuming device. The passive device may include a plurality of passive elements formed on a semiconductor substrate. The passive elements may be arranged in an array of structures on the semiconductor substrate. The power consuming device and the passive device may be coupled using one or more terminals. The passive device and power consuming device coupling may be configured in such a way that the power consuming device determines functionally the way the passive device elements will be used.

PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME

A package structure and a method of forming the same are provided. The package structure includes a die, an encapsulant, a redistribution layer (RDL) structure, a passive device, and a plurality of dummy items. The encapsulant laterally encapsulates the die. The RDL structure is disposed on the die and the encapsulant. The passive device is disposed on and electrically bonded to the RDL structure. The plurality of dummy items are disposed on the RDL structure and laterally aside the passive device, wherein top surfaces of the plurality of dummy items are higher than a top surface of the passive device.

STRUCTURES FOR LOW TEMPERATURE BONDING USING NANOPARTICLES

A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements.

SEMICONDUCTOR PACKAGE

A semiconductor package includes a redistribution layer and a semiconductor chip provided on the redistribution layer having a first surface and a second surface opposite to the first surface. The semiconductor chip includes a first chip pad and a second chip pad which are exposed at the first surface. The semiconductor package further includes a capacitor chip disposed between the first surface and the redistribution layer and including a capacitor chip pad connected to the first chip pad, an insulating layer covering the first surface and the capacitor chip, and a conductive post being in contact with the second chip pad and penetrating the insulating layer so as to be connected to the redistribution layer. The conductive post may be spaced apart from the capacitor chip.

SEMICONDUCTOR PACKAGE WITH REDISTRIBUTION SUBSTRATE

Disclosed is a semiconductor package including: a redistribution substrate; at least one passive device in the redistribution substrate, the passive device including a first terminal and a second terminal; and a semiconductor chip on a top surface of the redistribution substrate, the semiconductor chip vertically overlapping at least a portion of the passive device, wherein the redistribution substrate includes: a dielectric layer in contact with a first lateral surface, a second lateral surface opposite to the first lateral surface, and a bottom surface of the passive device; a lower conductive pattern on the first terminal; a lower seed pattern provided between the first terminal and the conductive pattern, and directly connected to the first terminal; a first upper conductive pattern on the second terminal and a first upper seed pattern provided between the second terminal and the first upper conductive pattern, and directly connected to the second terminal.

Magnetische Komponentenabschirmung für mikroelektronische Bauelemente

Ein mikroelektronisches Bauelement kann ein Substrat, eine Komponente, eine erste Platte, eine zweite Platte und eine Abschirmung umfassen. Die Komponente kann zumindest teilweise innerhalb des Substrats angeordnet sein. Die erste Platte kann auf einer ersten Seite der Komponente angeordnet sein. Die zweite Platte kann auf einer zweiten Seite der Komponente angeordnet sein. Die Abschirmung kann um zumindest einen Abschnitt einer Peripherie der Komponente herum angeordnet sein.

Integrated circuit chip using top post-passivation technology and bottom structure technology

Adhesive composition, electronic component-mounted substrate using the adhesive composition, and semiconductor device

This invention provides an adhesive composition which, while maintaining storage stability, can form a metallic bond in such a state that the cured product wets components and is spread well between components, and is excellent in adhesion, electroconductivity, TCT resistance, and mounting reliability such as high-temperature standing resistance, and an electronic component-mounted substrate using the adhesive composition and a semiconductor device.The adhesive composition comprises electroconductive particles (A) and a binder component (B). The adhesive composition is characterized in that the electroconductive particles (A) comprise a metal (a1), which has a melting point equal to or above the reflow temperature and is free form lead, and a metal (a2), which has a melting point below the reflow temperature and is free from lead, and the binder component (B) comprises a heat curable resin composition (b1) and an aliphatic dihydroxycarboxylic acid (b2).

INTEGRATED CIRCUIT CHIP USING TOP POST-PASSIVATION TECHNOLOGY AND BOTTOM STRUCTURE TECHNOLOGY

CAPACITOR DIE DESIGN FOR SMALL FORM FACTORS

A semiconductor package has a capacitor die and a packaging substrate. The capacitor die is coupled to circuitry on a front or back side of a die coupled to the packaging substrate for providing decoupling capacitance. In one example, the capacitor die is coupled to a land side of the packaging substrate in an area depopulated of a packaging array and adjacent to the packaging array. In another example, the capacitor die may be stacked on the die and coupled through wire bonds to circuitry on the die. The capacitor die reduces impedance of the integrated circuit allowing operation at higher frequencies.

Internally decoupled integrated circuit package

A decoupling scheme is presented which is well suited for use with any type of integrated circuit package. In accordance with the present invention, a flat decoupling capacitor is attached directly to the top of an IC die and is electrically connected to the IC by means of raised conductive bumps provided either on the surface of the decoupling capacitor or on the IC die surface. These conductive bumps interconnect the internal electrodes of the capacitor to the power and ground circuits of the IC. The resulting decoupling scheme provides a decoupling loop with an inductance which is significantly lower than previously disclosed decoupling loops.

Capacitive element, method of manufacture of the same, and semiconductor device

A capacitive element is characterized by including: a base ( 12 ); a lower barrier layer ( 13 ) formed on the base ( 12 ); capacitors (Q₁ and Q₂) made by forming a lower electrode ( 14 a), capacitor dielectric layers ( 15 a), and upper electrodes ( 16 a) in this order on the lower barrier layer ( 13 ); and an upper barrier layer ( 20 ) covering at least the capacitor dielectric layers ( 15 a) and the lower barrier layer ( 13 ).

Through-chip conductors for low inductance chip-to-chip integration and off-chip connections

Through-chip conductors for low inductance chip-to-chip integration and off-chip connections in a semiconductor package is disclosed. A semiconductor device has active devices on the front surface, a first through-chip conductor having first electrical/physical characteristics passing from the front surface of the device to the back surface, a second through-chip conductor having second electrical/physical characteristics passing to the back surface, and an off-chip or chip-to-chip connector electrically connecting the active devices on the front surface to a different level of packaging.

PACKAGING SUBSTRATE HAVING THROUGH-HOLED INTERPOSER EMBEDDED THEREIN AND FABRICATION METHOD THEREOF

A packaging substrate having a through-holed interposer embedded therein is provided, which includes: a molding layer having opposite first and second surfaces; a through-holed interposer embedded in the molding layer and flush with the second surface; a redistribution-layer structure embedded in the molding layer and disposed on the through-holed interposer and having a plurality of electrode pads exposed from the first surface of the molding layer; and a built-up structure disposed on the second surface of the molding layer and electrically connected to the through-holed interposer. By embedding the through-holed interposer in the molding layer and forming the built-up structure on the second surface of the molding layer, the present invention eliminates the need of a core board and reduces the thickness of the overall structure. Further, since the through-holed interposer has a CIE close to or the same as that of a silicon wafer, the structural reliability during thermal cycle testing ...

INTEGRATED CIRCUIT PACKAGES AND METHODS OF FORMING SAME

Packages and methods of manufacture thereof are described. A package may include a first package and a die structure disposed over the first package. The first package may include: a first encapsulant; a first via structure within the first encapsulant; a first die within the first encapsulant, at least a portion of the first encapsulant being interposed between a sidewall of the first die and a sidewall of the first via structure; a second die within the first encapsulant, an active side of the second die facing an active side of the first die; and a first via chip within the first encapsulant, the first via chip comprising one or more through vias, wherein the first via chip is disposed at the active side of the first die, and between the second die and the first via structure.

Stack package

A stack package includes a first semiconductor chip first pads and second pads disposed thereon and a second semiconductor chip having third pads and fourth pads electrically connected with the second pads disposed thereon. Capacitors are interposed between the first semiconductor chip and the second semiconductor chip, and include first electrodes electrically connected with the first pads of the first semiconductor chip, second electrodes electrically connected with the third pads of the second semiconductor chip, and dielectrics interposed between the first electrodes and the second electrodes.

SWITCHED POWER STAGE WITH INTEGRATED PASSIVE COMPONENTS

A scalable switching regulator architecture has an integrated inductor. In some embodiments an area and current drive capability of switches of the switching regulator is matched with an inductor built within an area above the switches. In some embodiments the combined switches and inductor are constructed as a unit cell and can be combined to form larger elements as required for higher current drive capability and multiphase operation. 1. An integrated chip package comprising:a flip-chip type integrated circuit (IC) chip including a system-on-chip (SoC) and a switching voltage regulator, the switching voltage regulator including at least a first switch and a second switch coupled in series between a higher voltage level connection and a lower voltage level connection;a multi-layer substrate having a cavity with at least one inductor in the cavity, the at least one inductor having a plurality of upper layers of traces interspersed by ferrite material, the inductor including a first end and a second end; anda plurality of micro-bumps connecting the IC chip to the substrate including a micro-bump connecting a node between the first switch and the second switch to the first end of the inductor.2. The integrated chip package of claim 1 , wherein the voltage regulator is a multi-phase voltage regulator claim 1 , and the at least one inductor comprises a plurality of inductors.3. The integrated chip package of claim 2 , wherein the voltage regulator includes a plurality of pairs of switches claim 2 , the pairs of switches including the first switch and the second switch claim 2 , and an area of the plurality of inductors is the same as an area of the plurality of pairs of switches.4. The integrated chip package of claim 3 , wherein the plurality of inductors are arranged as an array of inductors claim 3 , with at least pairs of inductors of the arrays of inductors arranged such that direction of magnetic fields of the pairs of inductors are aligned when the pairs of ...

Integrated Circuit Package and Method

In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially encapsulating the integrated circuit die; a redistribution structure on the encapsulant, the redistribution structure being electrically connect to the integrated circuit die, the redistribution structure including a pad; a passive device including a conductive connector physically and electrically connected to the pad; and a protective structure disposed between the passive device and the redistribution structure, the protective structure surrounding the conductive connector, the protective structure including an epoxy flux, the protective structure having a void disposed therein.

ELECTRODELESS PASSIVE EMBEDDED SUBSTRATE

NESTED ARCHITECTURES FOR ENHANCED HETEROGENEOUS INTEGRATION

Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a base substrate. The base substrate may have a plurality of through substrate vias. In an embodiment, a first die is over the base substrate. In an embodiment a first cavity is disposed into the base substrate. In an embodiment, the first cavity is at least partially within a footprint of the first die. In an embodiment, a first component is in the first cavity.

HETEROGENEOUS NESTED INTERPOSER PACKAGE FOR IC CHIPS

Embodiments disclosed herein include electronic packages and methods of fabricating electronic packages. In an embodiment, an electronic package comprises an interposer, where a cavity passes through the interposer, and a nested component in the cavity. In an embodiment, the electronic package further comprises a die coupled to the interposer by a first interconnect and coupled to the nested component by a second interconnect. In an embodiment, the first and second interconnects comprise a first bump, a bump pad over the first bump, and a second bump over the bump pad.

Substratanordnung mit magnetischem Merkmal

Vorrichtungen, Systeme und Verfahren die einem Substratentwurf mit einem magnetischen Merkmal für einen vollständig integrierten Spannungsregler zugeordnet sind, sind hierin offenbart. Bei Ausführungsbeispielen kann eine Substratanordnung ein Basissubstrat und eines oder mehrere Verbindungselemente, die an einer ersten Seite des Basissubstrats positioniert sind, umfassen, wobei das eine oder die mehreren Verbindungselementen mit einem Halbleiter-Chip gekoppelt sollen werden, der einen integrierten Spannungsregler (IVR; integrated voltage regulator) aufweist. Die Substratanordnung kann ferner ein magnetisches Merkmal umfassen, das an einer zweiten Seite des Basissubstrats positioniert ist, wobei die zweite Seite gegenüber der ersten Seite ist, wobei das magnetische Merkmal sich entlang eines Abschnitts der zweiten Seite des Basissubstrats erstreckt, der gegenüber des Orts ist, wo der IVR positioniert werden soll, wenn der Halbleiter-Chip mit dem einen oder den mehreren Verbindungselementen ...

Halbleitervorrichtungen und Verfahren zum Steuern der Temperatur davon

Eine beispielhafte Ausführungsform bezieht sich auf eine Halbleitervorrichtung aufweisend ein Halbleiter-Package (10), in welchem ein Halbleiterchip (150) an einem Package-Substrat (100) angebracht ist. Das Halbleiter-Package (10) kann eine Temperaturmessvorrichtung (110) und eine Temperatursteuerschaltung (151) aufweisen. Die Temperaturmessvorrichtung (110) kann eine Temperatur des Halbleiter-Packages (10) messen. Die Temperatursteuerschaltung (151) kann eine Arbeitsgeschwindigkeit des Halbleiter-Packages (10) auf der Basis der Temperatur des Halbleiter-Packages (10) ändern, welche durch die Temperaturmessvorrichtung (110) gemessen wird.

A SURFACE MOUNT SOLDER METHOD AND APPARATUS FOR DECOUPLING CAPACITANCE AND PROCESS OF MAKING

RF MODULE PACKAGE HAVING IMPROVED HEAT RADIATION EFFICIENCY AND DECREASED THICKNESS AND SIZE AND ASSEMBLING METHOD THEREOF TO DECREASE HEIGHT OF RF MODULE PACKAGE AND IMPROVE HEAT RADIATION EFFICIENCY

PURPOSE: An RF(radio frequency) module package having improved heat radiation efficiency and decreased thickness and size is provided to decrease the height of an RF module package by mounting an RF IC on a depressed region of a leadframe and stacking the RF IC and an IPD(integrated passive device), and to improve heat radiation efficiency by radiating the heat generated in operating the RF IC through the leadframe and a heat sink plate. CONSTITUTION: A depressed region(409) is formed in the center of a leadframe(402). An RF IC chip(410) is mounted on the depressed region of the leadframe. An IPD chip(420) has the first electrode pads connected to the first bumps(430) formed on an input/output pads of the RF IC chip. Pattern formation portions(424) are stacked in the IPD chip so that the first electrode pads are bonded to the first bumps on the RF IC chip, confronting each other. The first filling space(432) between the RF IC chip and the IPD chip corresponding to the size of the RF IC ...

3d integrated circuit package with through-mold first level interconnects

Method for fabricating semiconductor package

Circuits incorporating integrated passive devices having inductances in 3D configurations and stacked with corresponding dies

A circuit including a die and an integrated passive device. The die includes a first substrate and at least one active device. The integrated passive device includes a first layer, a second substrate, a second layer and an inductance. The inductance includes vias, where the vias are implemented in the second substrate. The inductance is implemented on the first layer, the second substrate, and the second layer. A resistivity per unit area of the second substrate is greater than a resistivity per unit area of the first substrate. The third layer is disposed between the die and the integrated passive device. The third layer includes pillars, where the pillars respectively connect ends of the inductance to the at least one active device. The die, the integrated passive device and the third layer are disposed relative to each other to form a stack.

Flip chip assembly with connected component

A flip chip assembly is disclosed that includes a die with die circuitry and a plurality of electrical contacts electrically connected to the die circuitry. A substrate includes electrical contacts that are juxtaposed with and electrically connected to corresponding die electrical contacts. A passive component is disposed between the die and the substrate, and includes a dielectric disposed between a first electrode and a second electrode. The first electrode is electrically connected to a first of the die electrical contacts and a corresponding substrate electrical contact, and the second electrode is electrically connected to a second of the die electrical contacts and a corresponding substrate electrical contact.

Electronic assembly with sandwiched capacitors and methods of manufacture

To provide high-speed, low inductance capacitive decoupling, an integrated circuit (IC) package includes capacitors positioned within the mounting region between a die and an IC package substrate. A variety of types and sizes of capacitors and substrates can be employed in a variety of geometrical arrangements. In some embodiments, capacitors are sandwiched between die terminals or bumps and the substrate conductors or pads, while in other embodiments, capacitors are positioned between bar-type conductors on the surface of the IC package substrate. Methods of fabrication, as well as application of the package to an electronic assembly and to an electronic system, are also described.

Package with overhang inductor

This disclosure describes techniques to provide a regulator circuit using a component-on-top (CoP) package. The CoP package comprising a system-in-package (SIP) comprising regulator circuitry, the SIP having a top portion and a first side portion; and an inductor on the top portion of the SIP, wherein: the inductor is coupled to the regulator circuitry via the top portion of the SIP; and a first end of the inductor extends beyond the first side portion of the SIP.

Semiconductor package structure with reduced parasite capacitance and method of fabricating the same

A semiconductor package structure for improving electrical performance and a method for fabricating the same are proposed, in which a substrate having at least one pair of passive component pads is provided, wherein a semiconductor chip is attached on the substrate and a passive component is mounted to the passive component pads to locate between the substrate and the semiconductor chip. Thus, the passive component can electrically connect the chip and the substrate simultaneously without arranging an additional conductive trace layer, thereby improving the electrical performance of the semiconductor package structure and reducing the structure size.

Substrate structure having electronic components and method of manufacturing substrate structure having electronic components

The present invention relates to a substrate structure having electronic components and a method of manufacturing a substrate structure having electronic components and can reduce signal loss and internal resistance and improve process efficiency by bringing a first terminal of a first electronic component and a second terminal of a second electronic component in direct contact with each other or in direct contact with each other by solder to minimize a path between the electronic components.

3D INTEGRATED CIRCUIT PACKAGE WITH THROUGH-MOLD FIRST LEVEL INTERCONNECTS

... 3D integrated circuit packages with through-mold first level interconnects and methods to form such packages are described. For example, a semiconductor package includes a substrate. A bottom semiconductor die has an active side with a surface area. The bottom semiconductor die is coupled to the substrate with the active side distal from the substrate. A top semiconductor die has an active side with a surface area larger than the surface area of the bottom semiconductor die. The top semiconductor die is coupled to the substrate with the active side proximate to the substrate. The active side of the bottom semiconductor die is facing and conductively coupled to the active side of the top semiconductor die. The top semiconductor die is conductively coupled to the substrate by first level interconnects that bypass the bottom semiconductor die.

METHOD OF FABRICATING A CONDUCTIVE LAYER ON AN IC USING NON-LITHOGRAPHIC FABRICATION TECHNIQUES

WIRING BOARD WITH BUILT-IN SOLID STATE ELECTROLYTIC CAPACITOR AND METHOD OF MANUFACTURING THE SAME

PROBLEM TO BE SOLVED: To realize a wiring board with a built-in solid state electrolytic capacitor which can load, in a low stress, a solid state electrolytic capacitor having reduced a loop inductance and also a semiconductor chip in the higher accuracy. SOLUTION: The wiring board with built-in solid state electrolytic capacitor comprises a wiring board 1 provided with a semiconductor chip accommodating part 4 at the predetermined position on the wiring board 1, and a solid state electrolytic capacitor accommodating part 5 at the lower surface of the semiconductor chip accommodating part 4. A sheet type solid state electrolytic capacitor 2 providing, at the one surface thereof, a plurality of connection bumps 15 is allocated in the solid state electrolytic capacitor accommodating part 5. This capacitor 2 is provided with a porous part at the one surface of a valve metal sheet body 6. Moreover, at the surface of this porous part, a dielectric material film 7, a solid state electrolytic ...

СПОСОБ И УСТРОЙСТВО ДЛЯ ОЧИСТКИ, РАЗДЕЛЕНИЯ, МОДИФИКАЦИИ И/ИЛИ ИММОБИЛИЗАЦИИ ХИМИЧЕСКИХ ИЛИ БИОЛОГИЧЕСКИХ ОБЪЕКТОВ, НАХОДЯЩИХСЯ В ТЕКУЧЕЙ СРЕДЕ, И ОПОРА ИЗ МИКРОПРОВОЛОКИ

В изобретении раскрывается устройство на основе технологии SSB для очистки, разделения, модификации и/или иммобилизации химических объектов или биологических объектов в текучей среде. Устройство по изобретению содержит одну или несколько опор из микропроволоки, закрепленных своими концами и имеющих многослойную структуру, состоящую из центрального стержня и по меньшей мере одного покрывающего слоя, пригодных для связывания химических или биологических объектов с функциональным покрытием или лигандами, находящимися на поверхности опор из микропроволоки при отсутствии воздействия магнитного поля, создаваемого между опорами из микропроволоки и частицами, находящимися в текучей среде. Описан также способ очистки, разделения, модификации и/или иммобилизации химических или биологических объектов, находящихся в текучей среде посредством этого устройства. Изобретение позволяет осуществлять процесс очистки, разделения, модификации и/или иммобилизации объектов, находящихся в текучей среде, при более ...

ЭЛЕКТРОННЫЙ УЗЕЛ, КОТОРЫЙ ВКЛЮЧАЕТ В СЕБЯ УЛОЖЕННЫЕ ДРУГ НА ДРУГА ЭЛЕКТРОННЫЕ УСТРОЙСТВА

Integrated circuit package with embedded bridge

The IC package may include a bridge connector 120 having first and second electrical routing features coupled to a portion of the first and second I/O interconnect structures of semiconductor ICs 102a and 102b. The first and second electrical routing features may be disposed on one side of the bridge adjacent to the ICs. Third electrical routing features may be disposed on an opposite side of the bridge and connect to through substrate vias in the bridge and additional ICs can be stacked on the bridge. The first and second electrical routing features may be configured to route electrical signals between the first die and the second die and the third electrical routing features may be configured to route electrical signals between the one side and the opposite side of the bridge connector. The first die, the second die, and the bridge may be embedded in electrically insulating material. A system in package arrangement may comprise the first and second processor ICs 102a, b, the bridge may ...

Spacer for die-to-die communication in an integrated circuit

Flexible electronic structure

수동 부품용 중첩체 기판을 구비한 다이 패키지

... 수동 부품을 지닌 기판을 포함하는 다이 패키지가 기술된다. 일 예에서, 패키지는 반도체 다이의 전면 근처의 능동 회로 및 그 전면에 대향하는 배면을 갖는 반도체 다이, 및 다이의 배면 근처의 부품 기판을 구비한다. 복수의 수동 전기 부품이 부품 기판 상에 있으며, 도전성 경로가 수동 부품을 능동 회로에 접속한다. 다이는 전면과 배면 사이에 실리콘 기판을 구비하고, 도전성 경로는 배면으로부터 능동 회로까지 다이를 관통하는 실리콘 관통 비아이다.

INTEGRATED CIRCUIT ASSEMBLY WITH PASSIVE INTEGRATION SUBSTRATE FOR POWER AND GROUND LINE ROUTING ON TOP OF AN INTEGRATED CIRCUIT CHIP

CERAMIC PACKAGE SUBSTRATE WITH RECESSED DEVICE

Semiconductor device

A semiconductor device includes a semiconductor chip including a semiconductor substrate, an element formed in an element forming region of the semiconductor substrate, and a through-via penetrating across a front surface and a rear surface of the semiconductor substrate while avoiding the element forming region of the semiconductor substrate to form a conductive path between the front surface and the rear surface; a circuit component mounted on a circuit component connection surface at the same side as the front surface of the semiconductor substrate of the semiconductor chip; and an external connection members formed on the rear surface of the semiconductor substrate.

Microelectronic assemblies incorporating inductors

Inductors are provided in chip assemblies such as in packaged semiconductor chips. The inductors may be incorporated in a chip carrier which forms part of the package, and may include, for example, spiral or serpentine inductors formed from traces on the chip carrier. The chip carrier may include a flap bearing the inductive element, and this flap may be bent to tilt the inductive element out of the plane of the chip carrier to reduce electromagnetic interaction between the inductive element and surrounding electrical components. Other inductors include solenoids formed in part by leads on the chip carrier as, for example, by displacing leads out of the plane of the chip carrier to form loops in vertically-extensive planes transverse to the plane of the chip carrier. Additional features provide trimming of the inductor to a desired inductance value during by breaking or connecting leads during assembly.

3D pillar inductor

Base pads are spaced by a pitch on a support surface. Conducting members, optionally Cu or other metal pillars, extend up from the base pads to top pads. A top pad interconnector connects the top pads in a configuration establishing an inductor current path between the base pads.

Semiconductor package having supporting plate and method of forming the same

A semiconductor package may include a packaging substrate, a first semiconductor chip on the packaging substrate, and a support plate on the packaging substrate. The support plate may be spaced apart from the first semiconductor chip in a direction parallel with respect to a surface of the packaging substrate. A second semiconductor chip may be provided on the first semiconductor chip and on the support plate so that the first semiconductor chip is between the second semiconductor chip and the packaging substrate and so that the support plate is between the second semiconductor chip and the packaging substrate. An adhesion layer may bond the second semiconductor chip to the first semiconductor chip and may bond the second semiconductor chip to the support plate. In addition, an electrical coupling may be provided between the first semiconductor chip and the packaging substrate.

Methods for low temperature bonding using nanoparticles

A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements.

반도체 장치

... 본 발명은 반도체 장치 및 그의 온도 제어방법에 관한 것으로, 반도체 장치는 패키지 기판 상에 반도체 칩이 실장된 반도체 패키지를 포함한다. 상기 반도체 패키지는 상기 반도체 패키지의 온도를 측정하는 온도측정장치와, 상기 온도측정장치에서 측정된 상기 반도체 패키지의 온도를 기준으로 상기 반도체 패키지의 동작속도를 변화시키는 온도제어회로를 포함할 수 있다.

멀티-다이 미세 그레인 집적된 전압 조정

... 전력 소모 디바이스(예컨대, SOC 디바이스)를 포함하는 반도체 디바이스 패키지가 기술된다. 전력 소모 디바이스(120)는 하나 이상의 전류 소모 소자를 포함할 수 있다. 수동 디바이스(100)는 전력 소모 디바이스에 결합(110)될 수 있다. 수동 디바이스는 반도체 기판 상에 형성된 복수의 수동 소자를 포함할 수 있다. 수동 소자들은 반도체 기판 상에 구조체들의 어레이(102)로 배열될 수 있다. 전력 소모 디바이스 및 수동 디바이스는 하나 이상의 단자(110)를 사용하여 결합될 수 있다. 수동 디바이스 및 전력 소모 디바이스 결합은 전력 소모 디바이스가 수동 디바이스 소자들이 사용될 방식을 기능적으로 결정하는 그러한 방식으로 구성될 수 있다.

Integrated structures of high performance active devices and passive devices

Integrated structures having high performance CMOS active devices mounted on passive devices are provided. The structure includes an integrated passive device chip having a plurality of through wafer vias, mounted to a ground plane. The structure further includes at least one CMOS device mounted on the integrated passive device chip using flip chip technology and being grounded to the ground plane through the through wafer vias of the integrated passive device chip.

Semiconductor device and method of fabricating the same

A stack of semiconductor chips, a semiconductor device, and a method of manufacturing are disclosed. The stack of semiconductor chips may comprise a first chip of the stack, a second chip of the stack over the first chip, conductive bumps, a homogeneous integral underfill material, and a molding material. The conductive bumps may extend between an upper surface of the first chip and a lower surface of the second chip. The homogeneous integral underfill material may be interposed between the first chip and the second chip, encapsulate the conductive bumps, and extend along sidewalls of the second chip. The homogeneous integral underfill material may have an upper surface extending in a direction parallel to an upper surface of the second chip and located adjacent the upper surface of the second chip. The molding material may be on outer side surfaces of the homogeneous integral underfill material above the upper surface of the first chip, wherein, in view of a first cross sectional profile, the molding material is separated from sidewalls of the second chip by the homogeneous integral underfill material such that the molding material does not contact sidewalls of the second chip.

Three dimensional semiconductor assembly board with bump/flange supporting board, coreless build-up circuitry and built-in electronic device

A semiconductor assembly board includes a supporting board, a coreless build-up circuitry and a built-in electronic device. The supporting board includes a bump, a flange and a via hole in the bump. The built-in electronic device extends into the via hole and is electrically connected to the build-up circuitry. The build-up circuitry extends from the flange and the built-in electronic device and provides signal routing for the built-in electronic device. The supporting board provides mechanical support, ground/power plane and heat sink for the coreless build-up circuitry.

Fabrication method of packaging substrate having through-holed interposer embedded therein

A packaging substrate having a through-holed interposer embedded therein and a fabrication method of the packaging substrate are provided, where the packaging substrate includes: a molding layer having opposite first and second surfaces; a through-holed interposer embedded in the molding layer and flush with the second surface; a redistribution-layer structure embedded in the molding layer and disposed on the through-holed interposer and having a plurality of electrode pads exposed from the first surface of the molding layer; and a built-up structure disposed on the second surface of the molding layer and electrically connected to the through-holed interposer.

Power converters with integrated capacitors

An apparatus having a power converter circuit having a first active layer having a first set of active devices disposed on a face thereof, a first passive layer having first set of passive devices disposed on a face thereof, and interconnection to enable the active devices disposed on the face of the first active layer to be interconnected with the non-active devices disposed on the face of the first passive layer, wherein the face on which the first set of active devices on the first active layer is disposed faces the face on which the first set of passive devices on the first passive layer is disposed.

Multi-Stacked Package-on-Package Structures

A multi-stacked package-on-package structure includes a method. The method includes: adhering a first die and a plurality of second dies to a substrate, the first die having a different function from each of the plurality of second dies; attaching a passive device over the first die; encapsulating the first die, the plurality of second dies, and the passive device; and forming a first redistribution structure over the passive device, the first die, and the plurality of second dies, the passive device connecting the first die to the first redistribution structure.

SUBSTRATE INTEGRATED THIN FILM CAPACITORS USING AMORPHOUS HIGH-K DIELECTRICS

Embodiments include an electronic package that includes a dielectric layer and a capacitor on the dielectric layer. In an embodiment, the capacitor comprises a first electrode disposed over the dielectric layer and a capacitor dielectric layer over the first electrode. In an embodiment, the capacitor dielectric layer is an amorphous dielectric layer. In an embodiment, the electronic package may also comprise a second electrode over the capacitor dielectric layer. 1. An electronic package , comprising:a dielectric layer; and a first electrode disposed over the dielectric layer;', 'a capacitor dielectric layer over the first electrode, wherein the capacitor dielectric layer is an amorphous dielectric layer; and', 'a second electrode over the capacitor dielectric layer., 'a capacitor on the dielectric layer, wherein the capacitor comprises2. The electronic package of claim 1 , wherein the capacitor dielectric layer is a high-k dielectric layer.3. The electronic package of claim 2 , wherein the capacitor dielectric layer has a k-value that is 10 or greater.4. The electronic package of claim 2 , wherein the capacitor dielectric layer has a k-value that is 100 or greater.5. The electronic package of claim 1 , wherein the capacitor dielectric layer has a thickness that is less than 2 μm.6. The electronic package of claim 1 , wherein the capacitor dielectric layer has a thickness that is less than 50 nm.7. The electronic package of claim 1 , wherein the capacitor further comprises a first intermediate metal layer between the first electrode and the capacitor dielectric layer claim 1 , and a second intermediate metal layer between the capacitor dielectric layer and the second electrode.8. The electronic package of claim 7 , wherein the capacitor dielectric layer is TiO claim 7 , and wherein the first and second intermediate metal layers comprise titanium.9. The electronic package of claim 8 , wherein the first and second intermediate metal layers comprise titanium and ...

Method for manufacturing electrical interconnection structure

Provided is a method of manufacturing an electrical connection structure which includes a female connection structure having an inner conductive material inside an insertion hole of a female connection member, and a male connection structure having a conductive column configured to be inserted into and fixed to the insertion hole to be in contact with the inner conductive material, and formed to protrude from a male connection member. The method includes preparing insulating members used for the female connection member and the male connection member, and forming the inner conductive material and the column by patterning a conductive material on each of the insulating member using a photolithography process.

MAGNETIC SOLDER MASK ON PACKAGE SUBSTRATE ABOVE MAGNETIC INDUCTOR ARRAY

A microelectronics package, comprising a substrate that comprises a dielectric and an inductor component comprising one or more wires within a magnetic core over the dielectric. The inductor component is bonded to the substrate by one or more solder joints. A solder mask is between the inductor component and the dielectric. The one or more solder joints are surrounded by the solder mask, and wherein the solder mask comprises a magnetic material. 1. A microelectronics package , comprising:a substrate comprising a dielectric;an inductor component comprising one or more wires within a magnetic core over the dielectric, wherein the inductor component is bonded to the substrate by one or more solder joints; anda solder mask between the inductor component and the dielectric, wherein the one or more solder joints are surrounded by the solder mask, and wherein the solder mask comprises a magnetic material.2. The microelectronics package of claim 1 , wherein the inductor comprises one or more wires extending substantially parallel to one another within the magnetic core.3. The microelectronics package of claim 1 , wherein the magnetic core comprises magnetic particles in a dielectric matrix.4. The microelectronics package of claim 3 , wherein the magnetic particles comprise any one of iron claim 3 , nickel claim 3 , cobalt claim 3 , manganese claim 3 , samarium claim 3 , ytterbium claim 3 , gadolinium claim 3 , terbium claim 3 , or dysprosium.5. The microelectronics package of claim 3 , wherein the dielectric matrix comprises an epoxy resin or an acrylic resin.6. The microelectronics package of claim 1 , wherein the magnetic material of the solder mask comprises any one of any one of iron claim 1 , nickel claim 1 , cobalt claim 1 , manganese claim 1 , a lanthanide element or an actinide element.7. The microelectronics package of claim 1 , wherein the solder mask comprises a polymer matrix.8. The microelectronics package of claim 7 , wherein the polymer matrix comprises an ...

SOC WITH INTEGRATED VOLTAGE REGULATOR USING PREFORMED MIM CAPACITOR WAFER

In some embodiments, a method and/or a system may include an integrated circuit. The integrated circuit may include a semiconductor die. The integrated circuit may include a plurality of wiring layers. At least one metal-insulator-metal (MIM) capacitor may be formed within the plurality of wiring layers. The integrated circuit may include a circuit. The circuit may include at least an inductor and a voltage regulator which, with the MIM capacitor, forms a voltage regulator for the semiconductor die. The circuit may be coupled substantially below at least a portion of the MIM capacitor in the plurality of layers. The circuit may be electrically coupled to the capacitor through the plurality of wiring layers. The integrated circuit may include a plurality of electrical connectors, the plurality of electrical connectors coupled to the second surface at points separate from an area of the second surface that is occupied by the circuit. 110-. (canceled)11. A method of manufacturing an integrated circuit , comprising:forming a plurality of wiring layers on a base, wherein at least one metal-insulator-metal (MIM) capacitor is formed within the plurality of wiring layers;coupling a semiconductor die to a first surface of the plurality of wiring layers, wherein the plurality of wiring layers further include conductors to connect the semiconductor die from the first surface of the plurality of wiring layers to a second surface of the plurality of wiring layers that is opposite to the first surface;encapsulating at least a portion of the semiconductor die in an insulating material;exposing the second surface of the plurality of wiring layers by removing at least a portion of the base;coupling a redistribution layer to the second surface of the plurality of wiring layers;coupling a circuit substantially below at least a portion of the MIM capacitor in the plurality of layers, wherein the circuit is electrically coupled to the capacitor through the plurality of wiring layers, ...

THIN FILM CAPACITOR AND SEMICONDUCTOR DEVICE

The present invention provides a thin film capacitor including a first electrode layer, a second electrode layer, and a dielectric layer provided between the first electrode layer and the second electrode layer, wherein a ratio (S/S) of a surface area S of a surface of the first electrode layer on an opposite side to the dielectric layer to a projected area Sin a thickness direction of the first electrode layer is 1.01 to 5.00. 1. A thin film capacitor comprising:a first electrode layer;a second electrode layer; anda dielectric layer provided between the first electrode layer and the second electrode layer,{'sub': 0', '0, 'wherein a ratio (S/S) of a surface area S of a surface of the first electrode layer on an opposite side to the dielectric layer to a projected area Sin a thickness direction of the first electrode layer is 1.01 to 5.00.'}2. The thin film capacitor according to claim 1 ,wherein heat conductivity λ of the first electrode layer is 90 W/(m·K) or higher.3. The thin film capacitor according to claim 1 ,wherein ten-point average roughness Rz of the surface of the first electrode layer on the opposite side to the dielectric layer is 0.02 to 2.00 μm.4. A semiconductor device comprising:a support substrate;a semiconductor element mounted on one main surface of the support substrate; and{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'the thin film capacitor according to ,'}wherein the thin film capacitor is embedded inside the support substrate in such a way that the second electrode layer and the semiconductor element face each other. The present invention relates to a thin film capacitor and a semiconductor device.Conventionally, as described in Japanese Unexamined Patent Publication Application No. 2007-258430, a semiconductor device including a semiconductor element and a capacitor which functions as a bypass capacitor (decoupling capacitor) is known.In recent years, as a semiconductor element is highly functionalized and accelerated, the amount of ...

Substrate structure having electronic components and method of manufacturing substrate structure having electronic components

The present invention relates to a substrate structure having electronic components and a method of manufacturing a substrate structure having electronic components and can reduce signal loss and internal resistance and improve process efficiency by bringing a first terminal of a first electronic component and a second terminal of a second electronic component in direct contact with each other or in direct contact with each other by solder to minimize a path between the electronic components.

Wire bond wires for interference shielding

Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region.

Multi-Die Fine Grain Integrated Voltage Regulation

A semiconductor device package is described that includes a power consuming device (such as an SOC device). The power consuming device may include one or more current consuming elements. A passive device may be coupled to the power consuming device. The passive device may include a plurality of passive elements formed on a semiconductor substrate. The passive elements may be arranged in an array of structures on the semiconductor substrate. The power consuming device and the passive device may be coupled using one or more terminals. The passive device and power consuming device coupling may be configured in such a way that the power consuming device determines functionally the way the passive device elements will be used. 120-. (canceled)21. A semiconductor device , comprising:a semiconductor substrate;a plurality of passive structures arranged in a pattern of tiles on the semiconductor substrate, wherein the tiles include passive elements formed on the semiconductor substrate;at least one power supply rail formed on the semiconductor substrate; anda plurality of terminals formed on the semiconductor substrate, wherein at least one terminal is positioned inside of each tile in the pattern of tiles, the at least one terminal being associated with the passive elements in the tile;wherein at least two or more of the tiles are coupled to the at least one power supply rail, each of the at least two or more of the tiles including at least one terminal that couples the passive elements in the tile to the at least one power supply rail.22. The semiconductor device of claim 21 , wherein at least one of the passive elements is a capacitor.23. The semiconductor device of claim 21 , further comprising at least one additional power supply rail formed on the semiconductor substrate claim 21 , wherein the at least one additional power supply rail is positioned perpendicular to the at least one power supply rail on the semiconductor substrate.24. The semiconductor device of claim ...

BRIDGE INTERCONNECTION WITH LAYERED INTERCONNECT STRUCTURES

Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed. 1. An IC assembly , comprising:a package substrate having a cavity;a bridge embedded in the cavity of the package substrate, the bridge comprising silicon;a dielectric material over the bridge;a first joint over and electrically coupled to the bridge, the first joint in the dielectric material and extending above the dielectric material, and the first joint comprising copper;a first layer on the first joint, the first layer comprising nickel;a second joint over and electrically coupled to the bridge, the second joint in the dielectric material and extending above the dielectric material, and the second joint comprising copper;a second layer on the second joint, the second layer comprising nickel;a first interconnect structure in the package substrate, the first interconnect structure laterally spaced from a first side of the bridge;a second interconnect structure in the package substrate, the second interconnect structure laterally spaced from a second side of the bridge;a first die electrically coupled to the first joint and the first interconnect structure; anda second die electrically coupled to the second joint and the ...

Structures and methods for low temperature bonding

A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements.

Vertical power plane module for semiconductor packages

The present disclosure relates to a semiconductor package, that may include a package substrate, a base die arranged on and electrically coupled to the package substrate, and at least one power plane module arranged on the package substrate at a periphery of the base die. The power plane module may include a top surface and a bottom surface, and at least one vertical interleaving metal layer electrically coupled at the bottom surface to the package substrate. The semiconductor package may further include a semiconductor device including a first section disposed on the base die, and a second section disposed on the power plane module, wherein the second section of the semiconductor device may be electrically coupled to the at least one vertical interleaving metal layer at the top surface of the power plane module.

Wafer-Level Passive Array Packaging

Wafer level passive array packages, modules, and methods of fabrication are described. In an embodiment, a module includes a circuit board, and a package mounted on the circuit board in which the package includes a plurality of passive components bonded to a bottom side of the die and a plurality of landing pads of the circuit board. 1. A module comprising:a circuit board including a top side including a first plurality of landing pads; and a die; and', 'a plurality of passive components bonded to a bottom side of the die and the first plurality of landing pads of the circuit board;', 'wherein the plurality of passive components is directly underneath the die., 'a package mounted on the circuit board and bonded to the first plurality of landing pads, the package including2. The module of claim 1 , wherein the plurality of passive components is bonded to the die with a first solder material and bonded to the circuit board with a second solder material claim 1 , wherein the first solder material is characterized by a higher reflow temperature than the second solder material.3. The module of claim 1 , wherein the die includes a redistribution layer (RDL) formed on a back-end-of-the-line (BEOL) build-up structure.4. The module of claim 3 , wherein the RDL is formed on and in electrical connection with a plurality of BEOL pads of the BEOL build-up structure claim 3 , and the plurality of passive components is bonded to a plurality of contact pads of the RDL.5. The module of claim 3 , wherein the RDL covers a plurality of test pads of the BEOL build-up structure claim 3 , wherein the plurality of test pads is electrically open.6. The module of claim 1 , wherein each passive component of the plurality of passive components includes two terminals claim 1 , each terminal respectively coupled to both the die and the circuit board.7. The module of claim 6 , further comprising a first circuit connecting the die and the circuit board claim 6 , wherein a first passive component ...

POWER DECOUPLING ATTACHMENT

An embodiment of the invention may include a method, and resulting structure, of forming a semiconductor structure. The method may include forming a component hole from a first surface to a second surface of a base layer. The method may include placing an electrical component in the component hole. The electrical component has a conductive structure on both ends of the electrical component. The electrical component is substantially parallel to the first surface. The method may include forming a laminate layer on the first surface of the base layer, the second surface of the base layer, and between the base layer and the electrical component. The method may include creating a pair of via holes, where the pair of holes align with the conductive structures on both ends of the electrical component. The method may include forming a conductive via in the pair of via holes. 1. A semiconductor structure comprising:a base layer with a first surface and a second surface;a capacitor located in the base layer, wherein the capacitor is substantially parallel to the first surface, and wherein the capacitor comprises an electrical connection on each end of the capacitor;a laminate layer located on the first surface and the second surface of the base layer, and between the base layer and the capacitor; anda conductive via extending from each electrical connection to the first surface and the second surface.2. The structure of claim 1 , further comprising a semiconductor die electrically connected to the conductive via extending to the first surface.3. The structure of claim 2 , wherein the coefficient of thermal expansion of the base layer and the semiconductor die is substantially similar.4. The structure of claim 2 , further comprising a packaging substrate electrically connected to the conductive via extending to the second surface.5. The structure of claim 4 , further comprising an underfill layer between the second surface of the base layer and the packaging substrate.6. The ...

Wire Bond Wires for Interference Shielding

Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region. 1. An apparatus for a microelectronic package having interference protection , comprising:a substrate having an upper surface and a lower surface opposite the upper surface and having bond pads on the upper surface;a microelectronic device coupled to the upper surface of the substrate;wire bond wires having lower ends coupled to the bond pads, the wire bond wires extending away from the upper surface of the substrate and placed for one or more frequencies associated with the interference;the wire bond wires positioned on at least one side of the microelectronic device to provide a shielding region with respect to the interference;a conductive surface positioned above the wire bond wires for covering the shielding region; andthe wire bond wires having upper ends coupled to the conductive surface.2. The apparatus according to claim 1 , wherein the wire bond wires are place to shield the microelectronic device from the interference.3. The apparatus according to claim 2 , wherein the microelectronic device is an active device.4. The apparatus according to claim 2 ...

Integration of inductors with advanced-node system-on-chip (soc) using glass wafer with inductors and wafer-to-wafer joining

A voltage regulator having a coil inductor is integrated or embedded in a system-on-chip (SOC) device. The coil inductor is fabricated on an inductor wafer with through vias, and the inductor wafer is joined with an SOC wafer for integration with the SOC device.

Multi-Stacked Package-on-Package Structures

A multi-stacked package-on-package structure includes a method. The method includes: adhering a first die and a plurality of second dies to a substrate, the first die having a different function from each of the plurality of second dies; attaching a passive device over the first die; encapsulating the first die, the plurality of second dies, and the passive device; and forming a first redistribution structure over the passive device, the first die, and the plurality of second dies, the passive device connecting the first die to the first redistribution structure. 1. A device comprising:a first redistribution structure;a passive device disposed on the first redistribution structure, the passive device comprising a substrate and a through via (TV) extending through the substrate, the TV electrically connected to the first redistribution structure;a first encapsulant at least partially surrounding the passive device;a second redistribution structure disposed on the first encapsulant and the passive device, the second redistribution structure electrically connected to the TV of the passive device;integrated circuit dies disposed on the second redistribution structure, each of the integrated circuit dies electrically connected to the second redistribution structure; anda second encapsulant at least partially surrounding each of the integrated circuit dies.2. The device of claim 1 , wherein the passive device is an integrated voltage regulator.3. The device of claim 1 , wherein the integrated circuit dies comprise:a system-on-chip die; anda memory die adjacent the system-on-chip die.4. The device of further comprising:first conductive vias extending through the first encapsulant, the first conductive vias connecting the first redistribution structure to the second redistribution structure.5. The device of further comprising:a reflowable connector connecting the passive device to the second redistribution structure; andan underfill disposed around the reflowable connector, ...

Semiconductor Device

A semiconductor device includes a semiconductor chip including a semiconductor substrate, an element formed in an element forming region of the semiconductor substrate, and a through-via penetrating across a front surface and a rear surface of the semiconductor substrate while avoiding the element forming region of the semiconductor substrate to form a conductive path between the front surface and the rear surface; a circuit component mounted on a circuit component connection surface at the same side as the front surface of the semiconductor substrate of the semiconductor chip; and an external connection members formed on the rear surface of the semiconductor substrate. 1. A voltage generating apparatus that generates a predetermined output voltage from an input voltage , the apparatus comprising:a semiconductor substrate including an element formed in an element-forming region;an insulating layer provided at a side of a first surface of the semiconductor substrate;a plurality of circuit components mounted on the insulating layer; andan external connection member provided at a side of a second surface of the semiconductor substrate, which is opposite to the side of the first surface of the semiconductor substrate,wherein the external connection member includes an input voltage terminal to which the input voltage is input, a ground terminal connected to a ground potential, and an output terminal from which the output voltage is output,wherein the element includes a first transistor and a second transistor connected in series between the input voltage terminal and the ground terminal,wherein the plurality of circuit components includes an inductor connected between the output terminal and a connection point of the first transistor and the second transistor, and a first capacitor connected between the input voltage terminal and the ground terminal; and', 'a second capacitor connected between the output terminal and the ground terminal., 'wherein the plurality of ...

Semiconductor device

In a semiconductor device, a first semiconductor chip includes a first circuit and a first inductor, and a second semiconductor chip includes a second circuit and chip-side connecting terminals. An interconnect substrate is placed over the first semiconductor chip and the second semiconductor chip. The interconnect substrate includes a second inductor and substrate-side connecting terminals. The second inductor is located above the first inductor. The chip-side connecting terminals and the two substrate-side connecting terminals are connected through first solder balls.

THREE-D POWER CONVERTER IN THREE DISTINCT STRATA

A switching power supply in an integrated circuit, an integrated circuit comprising a switching power supply, and a method of assembling a switching power supply in an integrated circuit are disclosed. In one embodiment, the invention provides a three-dimensional switching power supply in an integrated circuit comprising a device layer. The switching power supply comprises three distinct strata arranged in series with the device layer, the three distinct strata including a switching layer including switching circuits, a capacitor layer including banks of capacitors, and an inductor layer including inductors. This switching power supply further comprises a multitude of connectors electrically and mechanically connecting together the device layer, the switching layer, the capacitor layer, and the inductor layer. The switching circuits, the capacitors and the inductors form a switching power supply for supplying power to the device layer. 1. A three-dimensional switching power supply in an integrated circuit stack comprising a device layer including a plurality of processor cores , the switching power supply comprising: a switching layer including switching circuits,', 'a capacitor layer including banks of capacitors, and', 'an inductor layer including inductors; and, 'three distinct strata arranged in series with the device layer, the three distinct strata including'}a multitude of connectors electrically and mechanically connecting together the device layer, the switching layer, the capacitor layer, and the inductor layer; and wherein:the switching circuits, the capacitors and the inductors form a plurality of switching power supplies, and the switching power supplies apply different voltages to different ones of the processor cores depending on a workload being run on the processor cores.2. The three-dimensional switching power supply according to claim 1 , wherein the switching power supplies apply a first voltage to one or more of the processor cores when the one ...

ADHESIVE COMPOSITION, ELECTRONIC-COMPONENT-MOUNTED SUBSTRATE AND

There are provided are an adhesive composition that keeps storage stability and further gives a cured product wherein metallic bonds are formed in the state that the cured product wets its components and is satisfactorily spread between the components (or parts), thereby turning excellent in adhesive property, electroconductivity, and reliability for mounting such as TCT resistance or high-temperature standing resistance; an electronic-component-mounted substrate using the same; and a semiconductor device. The adhesive composition comprises electroconductive particles (A) and a binder component (B), wherein the electroconductive particles (A) include a metal (a1) having a melting point equal to or higher than the reflow temperature and containing no lead, and a metal (a2) having a melting point lower than the reflow temperature and containing no lead, and the binder component (B) includes a thermosetting resin composition (b1) and an aliphatic dihydroxycarboxylic acid (b2). 2. The electronic component structure according to claim 1 , wherein R1 in the general formula (1) is an alkyl group having 1 to 5 carbon atom.3. The electronic component structure according to claim 1 , wherein the aliphatic dihydroxycarboxylic acid (b2) includes 2 claim 1 ,2-bishydroxymethylpropionic acid claim 1 , 2 claim 1 ,2-bishydroxymethylbutanoic acid claim 1 , and 2 claim 1 ,2-bishydroxymethylpentanoic acid.4. The electronic component structure according to claim 1 , wherein the reflow temperature is the temperature for mounting with SnAgCu cream solder.5. The electronic component structure according to claim 1 , wherein the reflow temperature is 260° C.6. The electronic component structure according to claim 1 , wherein the content of the aliphatic dihydroxycarboxylic acid (b2) is 0.1 part or more by weight and 20 parts or less by weight for 100 parts by weight of the metal (a2) having the melting point lower than the reflow temperature and containing no lead.7. The electronic component ...

Integrated circuit component and package structure having the same

An integrated circuit component including a semiconductor die, a plurality of conductive vias and a protection layer is provided. The semiconductor die includes an active surface and a plurality of conductive pads disposed on the active surface. The conductive vias are respectively disposed on and in contact with the conductive pads, wherein each conductive via of a first group of the conductive vias has a first maximum size, each conductive via of a second group of the conductive vias has a second maximum size, and the first maximum size is less than the second maximum size in a vertical projection on the active surface. The protection layer covers the active surface and is at least in contact with sidewalls of the conductive vias.

Circuit board comprising heat transfer structure

A circuit board comprises a first heat transfer structure including graphite or graphene, wherein at least a portion of the first heat transfer structure is disposed inside an insulating member and a primer layer is disposed on a surface of the first heat transfer structure. The first heat transfer structure may comprise a plurality of monomers, the monomers including a primer layer disposed on at least one surface of at least one layer of graphite or graphene.

METHODS AND SYSTEMS TO IMPROVE PRINTED ELECTRICAL COMPONENTS AND FOR INTEGRATION IN CIRCUITS

Methods and systems to improve printed electrical components and for integration in circuits are disclosed. Passive components, e.g., capacitors, resistors and inductors, can be printed directly into a solid ceramic block using additive manufacturing. A grounded conductive plane or a conductive cage may be placed between adjacent electrical components, or around each component, to minimize unwanted parasitic effects in the circuits, such as, e.g., parasitic capacitance or parasitic inductance. Resistors may be printed in non-traditional shapes, for example, S-shape, smooth S-shape, U-shape, V-shape, Z-shape, zigzag-shape, and any other acceptable alternative configurations. The flexibility in shapes and sizes of the printed resistors allows optimal space usage of the ceramic block. The present invention also discloses an electrical component comprising combined predetermined values of capacitance, resistance and inductance. The integration and adjustability of a multi-property device can provide significant advantages in electronics manufacturing. 1. An integrated circuit , comprising:a circuit die;a lid covering a top surface of the circuit die;a ceramic matrix packaging, andwherein the ceramic matrix packaging comprises at least one of an embedded resistor, a capacitor, an inductor, and a multi-property device disposed within the ceramic matrix packaging.2. The integrated circuit of claim 1 , further comprising:wherein the at least one of a resistor, a capacitor, an inductor, and a multi-property device is oriented to minimize a parasitic effect.3. The integrated circuit of claim 1 , further comprising:wherein the at least one of a resistor, a capacitor, an inductor, and a multi-property device is oriented to optimize space usage of the ceramic matrix.4. The integrated circuit of claim 1 , further comprising:wherein the multi-property device comprises at least one helical coil encased in a cylindrical housing, andwherein the cylindrical housing comprises barium ...

Semiconductor devices and methods of controlling temperature thereof

An example embodiment relates to a semiconductor device including a semiconductor package in which a semiconductor chip is mounted on the package substrate. The semiconductor package may include a temperature measurement device and a temperature control circuit. The temperature measurement device may measure a temperature of the semiconductor package. The temperature control circuit may change an operation speed of the semiconductor package on the basis of the temperature of the semiconductor package measured by the temperature measurement device.

MULTILAYER POWER, CONVERTER WITH DEVICES HAVING REDUCED LATERAL CURRENT

An apparatus having a power converter circuit having a first active layer having a first set of active devices disposed on a face thereof, a first passive layer having first set of passive devices disposed on a face thereof, and interconnection to enable the active devices disposed on the face of the first active layer to be interconnected with the non-active devices disposed on the face of the first passive layer, wherein the face on which the first set of active devices on the first active layer is disposed faces the face on which the first set of passive devices on the first passive layer is disposed. 1. (canceled)2. An apparatus comprising:a first layer including a first plurality of active devices;a second layer including a second plurality of active devices; anda third layer including a plurality of passive devices and disposed between the first and the second layers,wherein an active device of the first plurality of active devices and an active device of the second plurality of active devices influence a state of charge of a passive device of the plurality of passive devices.3. The apparatus of claim 2 , further comprising an interconnect layer to electrically connect the first plurality of active devices claim 2 , the second plurality of active devices claim 2 , and the plurality of passive devices claim 2 , wherein the interconnect layer is disposed between the first layer and the third layer.4. The apparatus of claim 3 , wherein the interconnect layer is disposed between the second layer and the third layer.5. The apparatus of claim 2 , wherein each of the first and the second plurality of active devices includes switches.6. The apparatus of claim 2 , wherein the first plurality of active devices includes a plurality of stack switches and the second plurality of active devices include a plurality of phase switches.7. The apparatus of claim 6 , wherein the plurality of stack switches is electrically connected to a positive terminal of the passive device.8. ...

PACKAGE STRUCTURE, FAN-OUT PACKAGE STRUCTURE AND METHOD OF THE SAME

A package structure includes a spiral coil, a redistribution layer (RDL) and a molding material. The molding material fills gaps of the spiral coil. The spiral coil is connected to the RDL. A fan-out package structure includes a spiral coil, an RDL and a die. The spiral coil has a depth-to-width ratio greater than about 2. The RDL is connected to the spiral coil. The die is coupled to the spiral coil through the RDL. A semiconductor packaging method includes: providing a carrier; adhering a spiral coil on the carrier; adhering a die on the carrier; dispensing a molding material on the carrier to fill gaps between the spiral coil and the die; and disposing a redistribution layer (RDL) over the carrier so as to connect the spiral coil with the die. 1. A package structure , comprising:a spiral coil comprising a plurality of turns;a redistribution layer (RDL); anda molding material fills gaps between adjacent turns of the spiral coil;wherein the spiral coil is connected to the RDL.2. The package structure of claim 1 , wherein a depth-to-width ratio of the spiral coil is greater than 2.3. The package structure of claim 1 , wherein the spiral coil comprises copper (Cu).4. The package structure of claim 1 , further comprising an upper spiral coil over the spiral coil.5. The package structure of claim 1 , further comprising a die connected to the RDL so that the die is connected to the spiral coil through the RDL.6. The package structure of claim 4 , further comprising a non-conductive film laid between the upper spiral coil and the spiral coil.7. The package structure of claim 4 , wherein the upper spiral coil at least partially overlaps the spiral coil.8. The package structure of claim 4 , wherein the upper spiral coil and the spiral coil are wound in a same direction.9. The package structure of claim 4 , wherein the upper spiral coil is connected to the spiral coil through a contact.10. The package structure of claim 4 , further comprising a die connected to the RDL so ...

CIRCUIT SYSTEM HAVING COMPACT DECOUPLING STRUCTURE

A circuit system having compact decoupling structure, including: a mother board; at least one circuit unit, each having a substrate, a logic-circuit die, a plurality of first metal contacts, and a plurality of second metal contacts, the substrate having a first surface and a second surface, the first metal contacts being formed on the first surface and soldered onto the mother board, the second metal contacts being formed on the logic-circuit die and soldered onto the second surface to form flip-chip pillars, and the flip-chip pillars determining a height of a gap between the die and the substrate; and at least one decoupling unit for providing an AC signals decoupling function for the at least one circuit unit; wherein each of the at least one decoupling unit is placed in the gap of one said circuit unit and includes a mother die and at least one stack-type integrated-passive-device die. 1. A circuit system having compact decoupling structure , including:a mother board;at least one circuit unit, each having a substrate, a logic-circuit die, a plurality of first metal contacts, and a plurality of second metal contacts, wherein the substrate has a first surface and a second surface opposing the first surface, the first metal contacts are formed on the first surface and soldered onto the mother board, the second metal contacts are formed on the logic-circuit die and soldered onto the second surface of the substrate to form flip-chip pillars, and the flip-chip pillars determine a height of a gap between the logic-circuit die and the substrate; andat least one decoupling unit for providing an AC signals decoupling function for the at least one circuit unit;wherein, each of the at least one decoupling unit is placed in the gap of one said circuit unit and includes a mother die, at least one stack-type integrated-passive-device die, and a plurality of third metal contacts, the third metal contacts being formed on the mother die and soldered onto the logic-circuit die, and ...

Wire bond wires for interference shielding

Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region.

Fabrication method of semiconductor package

A semiconductor package is provided. The semiconductor package includes a semiconductor chip having opposite first and second surfaces; an RDL structure formed on the first surface of the semiconductor chip and having opposite third and fourth surfaces and a plurality of first conductive through holes penetrating the third and fourth surfaces thereof, wherein the RDL structure is formed on the semiconductor chip through the fourth surface thereof and electrically connected to the semiconductor chip through a plurality of first conductive elements, and the third surface of the RDL structure has a redistribution layer formed thereon; a plurality of conductive bumps formed on the redistribution layer; and an encapsulant formed on the first surface of the semiconductor chip for encapsulating the RDL structure, wherein the conductive bumps are embedded in and exposed from the encapsulant. The invention effectively prevents warpage of the semiconductor package and improves the electrical connection significantly.

WIRE BOND WIRES FOR INTERFERENCE SHIELDING

Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region. 1. An apparatus , comprising:a substrate having an upper surface and a lower surface opposite the upper surface;a microelectronic device coupled to the upper surface of the substrate; andwire bond wires having first ends coupled to the upper surface and second ends extending away therefrom, the wire bond wires arranged to shield one or more frequencies.2. The apparatus according to claim 1 , wherein the first ends and the second ends respectively are lower ends and upper ends claim 1 , the apparatus further comprising a conductive layer positioned above the upper ends of the wire bond wires for covering at least a portion of a region to be shielded.3. The apparatus according to claim 2 , wherein the first ends are lower ends claim 2 , and wherein the upper ends of the wire bond wires are bonded to the conductive layer.4. The apparatus according to claim 3 , wherein the conductive layer is a first conductive layer claim 3 , the apparatus further comprising a second conductive layer formed on or in the substrate.5. The apparatus according to claim 4 , wherein ...

Laminate rf choke for flip-chip power amplifier

A circuit includes a flip-chip die and a laminate substrate. The flip-chip die includes a first bump and a second bump. A first metal layer is disposed on the laminate substrate. The first metal layer includes a first transmission line having a plurality of segments forming a first spiral inductor. A first end of the first transmission line is electrically coupled to the first bump. A second end of the first transmission line is electrically coupled to a first power supply pin.

PACKAGE STRUCTURE, FAN-OUT PACKAGE STRUCTURE AND METHOD OF THE SAME

A package structure includes a spiral coil, a redistribution layer (RDL) and a molding material. The molding material fills gaps of the spiral coil. The spiral coil is connected to the RDL. A fan-out package structure includes a spiral coil, an RDL and a die. The spiral coil has a depth-to-width ratio greater than about 2. The RDL is connected to the spiral coil. The die is coupled to the spiral coil through the RDL. A semiconductor packaging method includes: providing a carrier; adhering a spiral coil on the carrier; adhering a die on the carrier; dispensing a molding material on the carrier to fill gaps between the spiral coil and the die; and disposing a redistribution layer (RDL) over the carrier so as to connect the spiral coil with the die. 1. A semiconductor packaging method , comprising:providing a carrier;adhering a spiral coil on the carrier;adhering a die on the carrier;dispensing a molding material on the carrier to fill gaps between the spiral coil and the die; anddisposing a redistribution layer (RDL) over the carrier so as to connect the spiral coil with the die.2. The semiconductor packaging method of claim 1 , wherein the spiral coil is obtained by means of punching claim 1 , wet etching or laser-cutting.3. The semiconductor packaging method of claim 1 , wherein the adhering of the spiral coil on the carrier comprises vibrating an alignment pallet carrying the spiral coil and mounting the spiral coil onto the carrier.4. The semiconductor packaging method of claim 1 , further comprising planarizing the molding material until top ends of the spiral coil and metal pillars of the die are exposed.5. The semiconductor packaging method of claim 15 , further comprising disposing a higher spiral coil at least partially overlapping with the spiral coil.6. The semiconductor packaging method of claim 15 , further comprising removing the carrier.7. A semiconductor packaging method claim 15 , comprising:providing a carrier;adhering a first spiral coil including a ...

THIN-FILM CAPACITOR AND ELECTRONIC COMPONENT EMBEDDED SUBSTRATE

A thin-film capacitor includes a pair of electrode layers composed of a first electrode layer configured to store positive charges and a second electrode layer configured to store negative charges; and a dielectric layer sandwiched between the pair of electrode layers along a lamination direction. The first electrode layer includes a first main electrode layer in contact with the dielectric layer. The second electrode layer includes a second main electrode layer and a second sub-electrode layer, both of which are formed of different metallic materials. The second sub-electrode layer is sandwiched between the dielectric layer and the second main electrode layer along the lamination direction. The second main electrode layer is formed of a material having a melting point lower than both a melting point of a material of the first electrode layer, or the first main electrode layer, and that of a material of the second sub-electrode layer. 1. A thin-film capacitor , comprising:a pair of electrode layers composed of a first electrode layer configured to store a positive charge and a second electrode layer configured to store a negative charge; anda dielectric layer sandwiched between the pair of electrode layers along a lamination direction,wherein the first electrode layer includes a first vain electrode layer which is in contact with the dielectric layer, andthe second electrode layer includes a second main electrode layer and a second sub-electrode layer, both of which are formed of different metallic materials,wherein the second sub-electrode layer is sandwiched between the dielectric layer and the second main electrode layer along the lamination direction, andthe second main electrode layer is formed of a material having a melting point lower than both a melting point of a material of the first main electrode layer and a melting point of a material of the second sub-electrode layer.2. The thin-film capacitor according to claim 1 , wherein the first electrode layer ...

Multi-Die Fine Grain Integrated Voltage Regulation

A semiconductor device package is described that includes a power consuming device (such as an SOC device). The power consuming device may include one or more current consuming elements. A passive device may be coupled to the power consuming device. The passive device may include a plurality of passive elements formed on a semiconductor substrate. The passive elements may be arranged in an array of structures on the semiconductor substrate. The power consuming device and the passive device may be coupled using one or more terminals. The passive device and power consuming device coupling may be configured in such a way that the power consuming device determines functionally the way the passive device elements will be used. 1. A semiconductor device , comprising:a first semiconductor substrate;a plurality of passive structures formed into an array on a first side of the first semiconductor substrate, wherein the passive structures comprise one or more passive elements formed on the first semiconductor substrate, at least one of the passive elements being a capacitor;an array of terminals formed on the first side of the first semiconductor substrate, the array of terminals being associated with the array of passive structures on the first semiconductor substrate, wherein at least one terminal is distinctly associated with at least one passive structure;a second semiconductor substrate, a first side of the second semiconductor substrate being coupled to the first side of the first semiconductor substrate using one or more of the terminals; anda plurality of current consuming elements formed on the first side of the second semiconductor substrate, wherein at least one current consuming element is directly coupled to at least one passive structure facing the at least one current consuming element using at least one terminal distinctly associated with the at least one passive structure, and wherein the at least one current consuming element is configured to determine at ...

Printed circuit board, manufacturing method thereof, and semiconductor package

A printed circuit board may include a circuit pattern serving as a land. The circuit pattern may be embedded inside a via to forma larger amount of circuits within a limited region. Also, by implementing a shortest distance between an embedded electronic component and a surface mounting component, noise may be reduced and electrical characteristics may be enhanced.

Package structure and method of fabricating the same

A package structure is provided comprising a die, a redistribution layer, at least one integrated passive device (IPD), a plurality of solder balls and a molding compound. The die comprises a substrate and a plurality of conductive pads. The redistribution layer is disposed on the die, wherein the redistribution layer comprises first connection structures and second connection structures. The IPD is disposed on the redistribution layer, wherein the IPD is connected to the first connection structures of the redistribution layer. The plurality of solder balls is disposed on the redistribution layer, wherein the solder balls are disposed and connected to the second connection structures of the redistribution layer. The molding compound is disposed on the redistribution layer, and partially encapsulating the IPD and the plurality of solder balls, wherein top portions of the solder balls and a top surface of the IPD are exposed from the molding compound.

MULTIPLE PLATED VIA ARRAYS OF DIFFERENT WIRE HEIGHTS ON SAME SUBSTRATE

Apparatus(es) and method(s) relate generally to via arrays on a substrate. In one such apparatus, the substrate has a conductive layer. First plated conductors are in a first region extending from a surface of the conductive layer. Second plated conductors are in a second region extending from the surface of the conductive layer. The first plated conductors and the second plated conductors are external to the first substrate. The first region is disposed at least partially within the second region. The first plated conductors are of a first height. The second plated conductors are of a second height greater than the first height. A second substrate is coupled to first ends of the first plated conductors. The second substrate has at least one electronic component coupled thereto. A die is coupled to second ends of the second plated conductors. The die is located over the at least one electronic component. 1. An apparatus , comprising:a first substrate having a conductive layer;first plated conductors in a first region extending from a surface of the conductive layer;second plated conductors in a second region extending from the surface of the conductive layer;wherein the first plated conductors and the second plated conductors are external to the first substrate;wherein the first region is disposed at least partially within the second region;wherein the first plated conductors are of a first height;wherein the second plated conductors are of a second height greater than the first height;a second substrate coupled to first ends of the first plated conductors;the second substrate having at least one electronic component coupled thereto;a die coupled to second ends of the second plated conductors; andthe die located over the at least one electronic component.2. The apparatus according to claim 1 , wherein the at least one electronic component includes a discrete passive component.3. The apparatus according to claim 2 , wherein the second substrate includes a ...

Multiple bond via arrays of different wire heights on a same substrate

Apparatuses relating generally to a substrate are disclosed. In such an apparatus, first wire bond wires (“first wires”) extend from a surface of the substrate. Second wire bond wires (“second wires”) extend from the surface of the substrate. The first wires and the second wires are external to the substrate. The first wires are disposed at least partially within the second wires. The first wires are of a first height. The second wires are of a second height greater than the first height for coupling of at least one electronic component to the first wires at least partially disposed within the second wires. 1. An apparatus , comprising:a substrate;first wire bond wires (“first wires”) in a first region, the first wires extending from a surface of the substrate;second wire bond wires (“second wires”) in a second region, the second wires extending from the surface of the substrate;wherein the first wires and the second wires are external to the substrate;wherein the first region is disposed at least partially within the second region;wherein the first wires are of a first height;wherein the second wires are of a second height greater than the first height for coupling of at least one electronic component to the first wires;a first die and a second die are coupled to second ends of the second wires;the first die and the second die are disposed over the discrete passive component; anda third die coupled above the first die.2. The apparatus according to claim 1 , wherein:the at least one electronic component includes a discrete passive component; andthe discrete passive component is coupled to first ends of the first wires.3. The apparatus according to claim 2 , wherein the discrete passive component claim 2 , the first die and the second die are electrically coupled to one another.4. The apparatus according to claim 2 , wherein the discrete passive component is coupled to an interposer disposed at least partially within the second region.5. The apparatus according to ...

SEMICONDUCTOR DEVICE, PACKAGE, AND VEHICLE

A semiconductor device includes a metal plate capacitor that includes a heat-resistant metal plate and a capacitor unit including a sintered dielectric formed on at least one surface of the heat-resistant metal plate, a semiconductor chip disposed on the metal plate capacitor, a connector configured to electrically connect the semiconductor chip and the metal plate capacitor, and a protector configured to protect the semiconductor chip, the metal plate capacitor, and the connector. 1. A semiconductor device comprising:a metal plate capacitor including a heat-resistant metal plate and a capacitor unit including a sintered dielectric formed on at least one surface of the heat-resistant metal plate;a semiconductor chip disposed on the metal plate capacitor;a connector configured to electrically connect the semiconductor chip and the metal plate capacitor; anda protector configured to protect the semiconductor chip, the metal plate capacitor, and the connector.2. A semiconductor device comprising:a metal plate capacitor including a heat-resistant metal plate, and a lower electrode, a sintered dielectric, and an upper electrode that are formed on at least one surface of the heat-resistant metal plate;a semiconductor chip disposed on the metal plate capacitor;a resin substrate unit on which the heat-resistant metal plate and the semiconductor chip are disposed;an upper chip connector configured to electrically connect the semiconductor chip and the upper electrode;a lower chip connector configured to electrically connect the semiconductor chip and the lower electrode; anda protector configured to protect the semiconductor chip, the metal plate capacitor, the upper chip connector, the lower chip connector, and a surface of the resin substrate unit.3. A semiconductor device comprising:a lead frame;a metal plate capacitor including a heat-resistant metal plate, and a lower electrode, a sintered dielectric, and an upper electrode that are formed on at least one surface of the ...

Semiconductor Device

A semiconductor device includes a semiconductor chip including a semiconductor substrate, an element formed in an element forming region of the semiconductor substrate, and a through-via penetrating across a front surface and a rear surface of the semiconductor substrate while avoiding the element forming region of the semiconductor substrate to form a conductive path between the front surface and the rear surface; a circuit component mounted on a circuit component connection surface at the same side as the front surface of the semiconductor substrate of the semiconductor chip; and an external connection members formed on the rear surface of the semiconductor substrate. 1. A semiconductor device comprising:a semiconductor chip including a semiconductor substrate, an element formed in an element forming region of the semiconductor substrate, and a through-via penetrating across a front surface and a rear surface of the semiconductor substrate while avoiding the element forming region of the semiconductor substrate to form a conductive path between the front surface and the rear surface;a circuit component mounted on a circuit component connection surface at the same side as the front surface of the semiconductor substrate of the semiconductor chip; andan external connection member formed on the rear surface of the semiconductor substrate.2. The semiconductor device of claim 1 , further comprising a first surface wiring layer formed on the circuit component connection surface of the semiconductor chip to connect a circuit formed in the element forming region to the through-via.3. The semiconductor device of claim 1 , further comprising a second surface wiring layer formed on the circuit component connection surface of the semiconductor chip to connect a circuit formed in the element forming region to an electrode of the circuit component.4. The semiconductor device of claim 1 , further comprising a third surface wiring layer formed on the circuit component connection ...

Structures And Methods For Low Temperature Bonding Using Nanoparticles

A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements. 1a first component including a substrate having a first surface and a plurality of first conductive elements exposed at the first surface, each first conductive element having a top surface generally facing in a first direction, the top surface of each first conductive element exposed in a recess extending below the first surface; anda second component including a substrate having a major surface and a plurality of second conductive elements exposed at the major surface, each second conductive element having a top surface generally facing in a second direction opposite the first direction, the top surface of each second conductive element exposed in a recess extending below the major surface,the first conductive elements being joined with the second conductive elements, such that the top surfaces of the first conductive elements at least partially confront the top surfaces of the second conductive elements,each first conductive element being electrically interconnected with a corresponding one of the second conductive elements by a bond ...

Electronic device, assembly and methods of manufacturing an electronic device including a vertical trench capacitor and a vertical interconnect

A semiconductor substrate comprises both vertical interconnects and vertical capacitors with a common dielectric layer. The substrate can be suitably combined with further devices to form an assembly. The substrate can be made in etching treatments including a first step on the one side, and then a second step on the other side of the substrate. 2. A method as claimed in claim 1 , wherein the first trenches and the second trenches are etched in a single step claim 1 , said first trenches having a smaller diameter than the second trenches leading to the through-holes claim 1 , with the result that the second trenches will extend further into the substrate than the first trenches claim 1 , said trenches having inner faces.3. A method as claimed in claim 2 , characterized in that the step of applying conductive material in the second trenches comprises the steps of applying a seed layer and electroplating.4. A method as claimed in claim 2 , characterized in that a plurality of second trenches are neighbouring and mutually interconnected so as to form a single vertical interconnect.5. A method as claimed in claim 4 , wherein the electrically conductive material applied in the first and the second trenches is polysilicon.6. A method as claimed in claim 1 , wherein the step of removing material for opening the second trenches comprises the step of wet-chemical etching to form a cavity claim 1 , said cavity having a larger diameter than the second trenches.7. A method as claimed in claim 1 , wherein the second trenches are formed by wet-chemical etching from the second side of the substrate before provision of the first trenches claim 1 , said second trenches being shaped as cavities and have a larger diameter than the first trenches.8. A method as claimed in claim 7 , wherein the second trenches are opened by etching in the same step as the etching of the first trenches.9. A method as claimed in claim 7 , wherein the second trenches extend up to the first side of the ...

INDUCTOR APPARATUS AND METHOD OF FABRICATING

Some aspects pertain to an inductor apparatus that includes a first metal layer including a plurality of first interconnects, a second metal including a plurality of second interconnects, a first dielectric layer between the first metal layer and the second metal layer, and an inductor. The inductor includes a plurality of vias, where the plurality of vias are configured to couple the plurality of first interconnects to the plurality of second interconnects. The inductor includes a plurality of inductor loops formed by the plurality of vias, the plurality of first interconnects and the plurality of second interconnects. The inductor further includes a first magnetic layer and a second magnetic layer, located between the first interconnects and the second interconnects; and a third magnetic layer and an optional fourth magnetic layer outside of the plurality of inductor loops. 1. An inductor apparatus comprising:a first metal layer including a plurality of first interconnects;a second metal layer including a plurality of second interconnects;a first dielectric layer between the first metal layer and the second metal layer; and a plurality of vias, the plurality of vias configured to couple the plurality of first interconnects to the plurality of second interconnects;', 'a plurality of inductor loops formed by the plurality of vias, the plurality of first interconnects and the plurality of second interconnects;', 'a first magnetic layer and a second magnetic layer between the plurality of first interconnects and the plurality of second interconnects; and', 'a third magnetic layer outside of the plurality of inductor loops., 'an inductor, the inductor including2. The inductor apparatus of claim 1 , wherein the third magnetic layer is parallel to the plurality of first interconnects and at least partially aligned with the first interconnects.3. The inductor apparatus of claim 2 , wherein the third magnetic layer comprises a single sheet.4. The inductor apparatus of ...

Semiconductor package

A semiconductor package includes a first semiconductor chip on a substrate, a second semiconductor chip on the substrate and spaced apart from the first semiconductor device, a mold layer on the substrate and covering sides of the first and second semiconductor chips, and an image sensor unit on the first and second semiconductor chips and the mold layer. The image sensor unit is electrically connected to the first semiconductor chip.

Die package with superposer substrate for passive components

A die package is described that includes a substrate to carry passive components. In one example, the package has a semiconductor die having active circuitry near a front side of the die and having a back side opposite the front side, and a component substrate near the back side of the die. A plurality of passive electrical components are on the component substrate and a conductive path connects a passive component to the active circuitry. The die has a silicon substrate between the front side and the back side and the conductive path is a through-silicon via through the die from the back side to the active circuit.

SEMICONDUCTOR DEVICE

A semiconductor device which provides improved reliability. The semiconductor device includes: a wiring substrate having a first surface and a second surface opposite to the first surface; a chip condenser built in the wiring substrate, having a first electrode and a second electrode; a first terminal and a second terminal disposed on the first surface; and a third terminal disposed on the second surface. The semiconductor device further includes: a first conduction path for coupling the first terminal and the third terminal; a second conduction path for coupling the first terminal and the first electrode; a third conduction path for coupling the third terminal and the first electrode; and a fourth conduction path for coupling the second terminal and the first electrode. 1. A semiconductor device comprising:a wiring substrate having a first surface and a second surface opposite to the first surface;a semiconductor chip having a first chip electrode and a second chip electrode and being mounted over the wiring substrate;a chip condenser built in the wiring substrate, having a first electrode and a second electrode;a first terminal and a second terminal disposed on the first surface;a third terminal disposed on the second surface;a first conduction path for coupling the first terminal and the third terminal;a second conduction path for coupling the first terminal and the first electrode;a third conduction path for coupling the third terminal and the first electrode; anda fourth conduction path for coupling the second terminal and the first electrode,wherein the fourth conduction path is coupled to the first electrode electrically independently from the first conduction path, the second conduction path, and the third conduction path.2. The semiconductor device according to claim 1 , 'a first via electrode coupled to the first electrode,', 'the second conduction path further comprising 'a second via electrode coupled to the first electrode,', 'the fourth conduction path ...

SEMICONDUCTOR PACKAGE WITH BARRIER LAYER

A packaged integrated circuit device includes a frame having a cavity therein and an inner semiconductor chip within the cavity. A lower re-distribution layer is provided, which extends adjacent lower surfaces of the frame and the inner semiconductor chip. The lower re-distribution layer has an opening therein which at least partially exposes the lower surface of the inner semiconductor chip. A lower semiconductor chip is provided, which extends adjacent the lower surface of the inner semiconductor chip, and within the opening in the lower re-distribution layer. This lower re-distribution layer includes: (i) an insulating layer covering the lower surface of the frame, (ii) a re-distribution pattern disposed on the insulating layer, and (iii) a barrier layer, which is disposed on the insulating layer and surrounds at least a portion of the lower semiconductor chip. 1. A packaged integrated circuit device , comprising:a frame having a cavity therein;an inner semiconductor chip within the cavity;a lower re-distribution layer extending adjacent lower surfaces of the frame and the inner semiconductor chip, said lower re-distribution layer having an opening therein which at least partially exposes the lower surface of the inner semiconductor chip; anda lower semiconductor chip adjacent the lower surface of the inner semiconductor chip, and within the opening in the lower re-distribution layer, which comprises: (i) an insulating layer covering the lower surface of the frame, (ii) a re-distribution pattern disposed on the insulating layer, and (iii) a barrier layer, which is disposed on the insulating layer and surrounds at least a portion of the lower semiconductor chip.2. The device of claim 1 , wherein the barrier layer has a generally quadrangular rim shape when viewed from a top plan view perspective.3. The device of claim 1 , wherein the lower semiconductor chip comprises:a body disposed on the lower surface of the inner semiconductor chip;a solder ball electrically ...

Structures And Methods For Low Temperature Bonding Using Nanoparticles

A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements. 1. A method of making an assembly , comprising:juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate, the first surface of the first substrate and the major surface of the second substrate each comprising a dielectric material, wherein one of: the top surface of the first conductive element is recessed below the first surface of the first substrate, or the top surface of the second conductive element is recessed below the major surface of the second substrate, and electrically conductive nanoparticles are disposed between the top surfaces of the first and second conductive elements, the conductive nanoparticles having long dimensions smaller than 100 nanometers;directly bonding the dielectric material of the first surface with the dielectric material of the major surface; andelevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a ...

MAGNETIC SMALL FOOTPRINT INDUCTOR ARRAY MODULE FOR ON-PACKAGE VOLTAGE REGULATOR

An apparatus comprises an inductor module including: a module substrate including a magnetic dielectric material; a plurality of inductive circuit elements arranged in the module substrate, wherein an inductive circuit element includes conductive traces arranged as a coil including a first coil end, a second coil end and a coil core, wherein the coil core includes the magnetic dielectric material; and a plurality of conductive contact pads electrically coupled to the first and second coil ends. The contact pads electrically coupled to the first coil ends are arranged on a first surface of the inductor module, and the contact pads electrically coupled to the second coil ends are arranged on a second surface of the inductor module. 1. An apparatus comprising:an integrated circuit (IC); a module substrate including a magnetic dielectric material;', 'a plurality of inductive circuit elements arranged in the module substrate, wherein an inductive circuit element includes conductive traces arranged as a coil including a first coil end, a second coil end and a coil core, wherein the coil core includes the magnetic dielectric material; and', 'a plurality of conductive contact pads electrically coupled to first coil and second coil ends and arranged on one surface of the inductor module; and, 'an inductor module includinga package substrate of an electronic package assembly, wherein the package substrate includes conductive interconnect between the inductor module and the IC, and the IC is arranged on a separate surface of the package substrate from the inductor module.2. The apparatus of claim 1 , wherein the IC is arranged on a first surface of the package substrate and includes a voltage regulator circuit and a processor circuit claim 1 , and wherein the inductor module is arranged on a second surface of the package substrate.3. The apparatus of claim 1 , wherein the IC is arranged on a first surface of the package substrate and includes a voltage regulator circuit and a ...

PACKAGE ASSEMBLY AND METHOD FOR MANUFACTURING THE SAME

A package assembly and a method for manufacturing the same are disclosed. The package assembly includes a leadframe having at least two groups of leads and a plurality of electronic devices arranged in at least two levels. Each group of leads is electrically coupled to a respective level of electronic devices. The package assembly further includes an interconnect for coupling one or more leads of one group of leads to one or more leads of another group of leads. The package assembly results in increased packaging density, less usage of bonding wires in the package assembly, improves reliability, and prevents possible interference. 1. A package assembly comprising:a leadframe having at least two groups of leads; anda plurality of electronic devices stacked in at least two levels,wherein each group of leads is electrically coupled to a respective level of electronic devices, andsaid package assembly further comprises an interconnect for coupling one or more leads of one group of leads to one or more leads of another group of leads.2. The package assembly according to claim 1 , wherein said interconnect is formed integrally with at least two leads and electrically couples said at least two leads with each other.3. The package assembly according to claim 1 , further comprising a contact pad on at least one lead and being soldered to said electronic devices.4. The package assembly according to claim 3 , wherein said interconnect is formed integrally with said contact pad.5. The package assembly according to claim 4 , wherein said interconnect extends from a top surface of one lead to a side surface of another lead.6. The package assembly according to claim 4 , wherein said interconnect extends from a top surface of one lead to a side surface and a top surface of another lead.7. The leadframe according to claim 1 , whereinall of said at least two groups of leads are coplanar at bottoms in a plane perpendicular to a first direction along which said electronic devices are ...

CIRCUIT SYSTEM HAVING COMPACT DECOUPLING STRUCTURE

A circuit system having compact decoupling structure, including: a mother board; at least one circuit unit, each having a substrate, a logic-circuit die, a plurality of first metal contacts, and a plurality of second metal contacts, the substrate having a first surface and a second surface, the first metal contacts being formed on the first surface and soldered onto the mother board, the second metal contacts being formed on the logic-circuit die and soldered onto the second surface to form flip-chip pillars, and the flip-chip pillars determining a height of a gap between the die and the substrate; and at least one decoupling unit for providing an AC signals decoupling function for the at least one circuit unit; wherein each of the at least one decoupling unit is placed in the gap of one said circuit unit and includes a mother die and at least one stack-type integrated-passive-device die. 1. A circuit system having compact decoupling structure , including:a mother board;at least one circuit unit, each having a substrate, a logic-circuit die, a plurality of first metal contacts, and a plurality of second metal contacts, wherein the substrate has a first surface and a second surface opposing the first surface, the first metal contacts are formed on the first surface and soldered onto the mother board, the second metal contacts are formed on the logic-circuit die and soldered onto the second surface of the substrate to form flip-chip pillars, and the flip-chip pillars determine a height of a gap between the logic-circuit die and the substrate; andat least one decoupling unit for providing an AC signals decoupling function for the at least one circuit unit;wherein, each of the at least one decoupling unit is placed in the gap of one said circuit unit and includes a mother die, at least one stack-type integrated-passive-device die, and a plurality of third metal contacts, the third metal contacts being formed on the mother die and soldered onto the logic-circuit die, and ...

Chip package with embedded passive device

A chip package includes a first die encapsulated by a molding compound; a board comprising a chip mounting surface; a redistributed layer (RDL) structure on an active surface of the first die and between the die and the chip mounting surface; and a discrete passive device embedded in the molding compound and situated in close proximity to a side edge of the first die.

Apparatuses, multi-chip modules and capacitive chips

Some embodiments include a capacitive chip having a plurality of capacitive units. The individual capacitive units include alternating electrode layers and dielectric layers in a capacitor stack. The capacitor stack extends across an undulating topography. The undulating topography has peaks and valleys with the peaks being elevationally offset relative to the valleys by a distance within a range of from about 30 microns to about 100 microns. The capacitor stack includes at least about 10 total layers. Some embodiments include apparatuses and multi-chip modules having capacitor chips.

Substrate assembly with magnetic feature

Apparatuses, systems and methods associated with substrate design with a magnetic feature for fully integrated voltage regulator are disclosed herein. In embodiments, a substrate assembly may include a base substrate and one or more interconnect elements located at a first side of the base substrate, the one or more interconnect elements to be coupled to a semiconductor chip having an integrated voltage regulator (IVR). The substrate assembly may further include a magnetic feature located at a second side of the base substrate, the second side being opposite to the first side, wherein the magnetic feature extends along a portion of the second side of the base substrate that is opposite to where the IVR is to be located when the semiconductor chip is coupled to the one or more interconnect elements. Other embodiments may be described and/or claimed.

Power management system switched capacitor voltage regulator with integrated passive device

Power management systems are described. In an embodiment, a power management system includes a voltage source, a circuit load located within a chip, and a switched capacitor voltage regulator (SCVR) coupled to voltage source and the circuit load to receive an input voltage from the voltage source and supply an output voltage to the circuit load. The SCVR may include circuitry located within the chip and a discrete integrated passive device (IPD) connected to the chip.

STRUCTURES AND METHODS FOR LOW TEMPERATURE BONDING USING NANOPARTICLES

A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements. 1. An assembly , comprising:a first component including a substrate having a first surface and a plurality of substantially rigid first posts of metal at the first surface, the first posts extending away from the first surface in a first direction, each first post having a top surface generally facing in the first direction, the top surface of each of the first posts projecting a height above the first surface such that the top surface is remote from the first surface, each first post having edge surfaces extending at substantial angles away from the top surface thereof; anda second component including a substrate having a major surface and a plurality of second conductive elements exposed at the major surface, each second conductive element having a top surface generally facing in a second direction, the top surface of each second conductive element exposed in a recess extending below the major surface,the first posts being joined with the second conductive elements, such that the top surfaces of the first posts at least partially ...

VERTICAL CAPACITORS FOR MICROELECTRONICS

Vertical capacitors for microelectronics are provided. An example thin capacitor layer can provide one or numerous capacitors to a semiconductor chip or integrated circuit. In an implementation, a thin capacitor layer of 50-100 μm thickness may have 5000 vertically disposed capacitor plates per linear centimeter, while occupying only a thin slice of the package. Electrodes for each capacitor plate are accessible at multiple surfaces. Electrode density for very fine pitch interconnects can be in the range of 2-200 μm separation between electrodes. A redistribution layer (RDL) may be fabricated on one or both sides of the thin capacitor layer to provide fan-out ball grid arrays that occupy insignificant space. RDLs or through-vias can connect together sets of the interior vertical capacitor plates within a given thin capacitor layer to form various capacitors from the plates to meet the needs of particular chips, dies, integrated circuits, and packages. 1. An apparatus , comprising:a capacitor layer to underlie a semiconductor chip, a die, or an integrated circuit;vertical capacitor plates in the capacitor layer interleaved with vertical dielectric layers; andelectrodes of each vertical capacitor plate at a top surface and a bottom surface of the capacitor layer.2. The apparatus of claim 1 , wherein the capacitor layer has a thickness in a range of approximately 50-400 micrometers (μm) between the top surface and the bottom surface.3. The apparatus of claim 1 , wherein the capacitor layer comprises approximately 5000 vertical capacitor plates per linear centimeter of the capacitor layer.4. The apparatus of claim 1 , further comprising a direct-bond between the vertical capacitor plates.5. The apparatus of claim 4 , wherein a thickness of the capacitor layer is selected from the group consisting of a thickness in the range of approximately 50-100 μm claim 4 , a thickness in the range of approximately 100-200 μm claim 4 , and a thickness in the range of approximately ...

Contact bumps methods of making contact bumps

Contact bumps between a contact pad and a substrate can include a rough surface that can mate with the material of the substrate. The rough surface can enhance the bonding strength of the contacts, for example, against shear and tension forces, especially for flexible systems such as smart cards.

ANTENNA MODULE AND CIRCUIT MODULE

An antenna that is formed of a conductor pattern is disposed on a dielectric substrate. A high-frequency semiconductor device that supplies a high-frequency signal to the antenna is mounted on the bottom surface of the dielectric substrate. A plurality of conductor columns project from the bottom surface. The conductor columns are embedded in a dielectric member that is disposed on the bottom surface. An end of each of the conductor columns is exposed through the dielectric member. The dielectric member defines a mounting surface that faces a mounting substrate. A step is formed in a side surface of a composite structure that includes the dielectric substrate and the dielectric member, and a side surface extending from the mounting surface to the step is more recessed than a side surface that is located above the step. 1. An antenna module comprising:a dielectric substrate in which an antenna being disposed, the antenna comprising a conductor pattern;a high-frequency semiconductor device that is mounted on a bottom surface of the dielectric substrate and that supplies a high-frequency signal to the antenna;a plurality of conductor columns that projects from the bottom surface; anda dielectric member that is disposed on the bottom surface and in which the conductor columns are embedded such that an end of each of the conductor columns projects out from the dielectric member,wherein the dielectric member defines a mounting surface that faces a mounting substrate, andwherein a step is formed in a side surface of a composite structure that includes the dielectric substrate and the dielectric member, and a part of the side surface extending from the mounting surface to the step is more recessed than other part of the side surface that is located above the step.2. The antenna module according to claim 1 ,wherein the antenna has directivity in a direction parallel to a substrate surface of the dielectric substrate, and the step is disposed so as to be closer to the ...

VERTICAL INDUCTOR FOR WLCSP

Embodiments of the invention include a microelectronic device and methods of forming a microelectronic device. In an embodiment the microelectronic device includes a semiconductor die and an inductor that is electrically coupled to the semiconductor die. The inductor may include one or more conductive coils that extend away from a surface of the semiconductor die. In an embodiment each conductive coils may include a plurality of traces. For example, a first trace and a third trace may be formed over a first dielectric layer and a second trace may be formed over a second dielectric layer and over a core. A first via through the second dielectric layer may couple the first trace to the second trace, and a second via through the second dielectric layer may couple the second trace to the third trace. 1. A microelectronic device , comprising:a semiconductor die; andan inductor electrically coupled to the semiconductor die, wherein the inductor includes one or more conductive coils that extend away from a surface of the semiconductor die, wherein the one or more conductive coils comprise a plurality of traces electrically coupled to each other by one or more vias, and wherein a first trace and a third trace are formed over a first dielectric layer and a second trace is formed over the core, and wherein a first via through the core couples the first trace to the second trace and a second via through the core couples the second trace to the third trace.2. The microelectronic device of claim 1 , wherein the first via and the second via are also formed through a second dielectric layer.3. The microelectronic device of claim 1 , wherein the plurality of traces in the conductive coil comprises a first trace and a third trace formed over a first dielectric layer and a second trace formed over a second dielectric layer and over the core claim 1 , and wherein a first via through the second dielectric layer couples the first trace to the second trace claim 1 , and a second via ...

Semiconductor Device

A semiconductor device includes a semiconductor chip including a semiconductor substrate, an element formed in an element forming region of the semiconductor substrate, and a through-via penetrating across a front surface and a rear surface of the semiconductor substrate while avoiding the element forming region of the semiconductor substrate to form a conductive path between the front surface and the rear surface; a circuit component mounted on a circuit component connection surface at the same side as the front surface of the semiconductor substrate of the semiconductor chip; and an external connection members formed on the rear surface of the semiconductor substrate. 1. A voltage generating apparatus that generates a predetermined output voltage from an input voltage , the apparatus comprising: a semiconductor substrate; and', 'an element formed in an element-forming region on a front surface of the semiconductor substrate;, 'a semiconductor chip includingan insulating layer provided at a side of a first surface of the semiconductor chip;a circuit component mounted on the insulating layer; andan external connection member provided at a side of a second surface of the semiconductor substrate, which is opposite to the side of the first surface of the semiconductor chip,wherein the external connection member includes an input voltage terminal to which the input voltage is input, a ground terminal connected to a ground potential, and an output terminal from which the output voltage is output,wherein the element includes a first transistor and a second transistor connected in series between the input voltage terminal and the ground terminal,wherein the element further includes a control circuit that controls the first transistor and the second transistor,wherein the circuit component includes an inductor connected between the output terminal and a connection point of the first transistor and the second transistor, andwherein the inductor is disposed directly over the ...

Semiconductor package

A semiconductor package includes a redistribution layer and a semiconductor chip provided on the redistribution layer having a first surface and a second surface opposite to the first surface. The semiconductor chip includes a first chip pad and a second chip pad which are exposed at the first surface. The semiconductor package further includes a capacitor chip disposed between the first surface and the redistribution layer and including a capacitor chip pad connected to the first chip pad, an insulating layer covering the first surface and the capacitor chip, and a conductive post being in contact with the second chip pad and penetrating the insulating layer so as to be connected to the redistribution layer. The conductive post may be spaced apart from the capacitor chip.

Semiconductor Device

A semiconductor device includes a semiconductor chip including a semiconductor substrate, an element formed in an element forming region of the semiconductor substrate, and a through-via penetrating across a front surface and a rear surface of the semiconductor substrate while avoiding the element forming region of the semiconductor substrate to form a conductive path between the front surface and the rear surface; a circuit component mounted on a circuit component connection surface at the same side as the front surface of the semiconductor substrate of the semiconductor chip; and an external connection members formed on the rear surface of the semiconductor substrate.

3-D STACKING OF ACTIVE DEVICES OVER PASSIVE DEVICES

Single-die or multi-die packaged modules that incorporate three-dimensional integration of active devices with discrete passive devices to create a package structure that allows active devices (such as, silicon or gallium-arsenide devices) to share the same footprint area as an array of passive surface mount components. In one example, a module includes at least one active device stacked on top of an array of passive surface mount components on a substrate. A conductive or non-conductive adhesive can be used to adhere the active device to the array of passive devices. 1. A semiconductor packaged module comprising:a substrate having first and second conductive traces disposed thereon;at least one passive surface mount component having an upper surface and a lower surface, at least a portion of the lower surface being connected to the first conductive trace; andan active device adhered to the upper surface of the at least one passive surface mount component by an adhesive.2. The semiconductor packaged module as claimed in claim 1 , wherein the adhesive is an epoxy paste.3. The semiconductor packaged module as claimed in claim 1 , wherein the adhesive is non-conductive.4. The semiconductor packaged module as claimed in claim 1 , wherein the at least one passive surface mount component comprises a body and a connection terminal;wherein the connection terminal is electrically connected to the first conductive trace; andthe adhesive is conductive; andwherein the adhesive is disposed between a selected portion of the active device and the upper surface of the connection terminal.5. The semiconductor packaged module as claimed in claim 1 , further comprising a wire bond electrically connecting the active device to the second conductive trace.6. The semiconductor packaged module as claimed in claim 1 , further comprising a molding compound substantially encapsulating the active device.7. A method of packaging a semiconductor module claim 1 , the method comprising:connecting ...

THREE-D POWER CONVERTER IN THREE DISTINCT STRATA

A switching power supply in an integrated circuit, an integrated circuit comprising a switching power supply, and a method of assembling a switching power supply in an integrated circuit are disclosed. In one embodiment, the invention provides a three-dimensional switching power supply in an integrated circuit comprising a device layer. The switching power supply comprises three distinct strata arranged in series with the device layer, the three distinct strata including a switching layer including switching circuits, a capacitor layer including banks of capacitors, and an inductor layer including inductors. This switching power supply further comprises a multitude of connectors electrically and mechanically connecting together the device layer, the switching layer, the capacitor layer, and the inductor layer. The switching circuits, the capacitors and the inductors form a switching power supply for supplying power to the device layer. 1. A three-dimensional switching power supply in an integrated circuit stack comprising a device layer including a plurality of processor cores , the switching power supply comprising: a switching layer including switching circuits,', 'a capacitor layer including banks of capacitors, and', 'an inductor layer including inductors; and, 'three distinct strata arranged in series with the device layer, the three distinct strata including'}a multitude of connectors electrically and mechanically connecting together the device layer, the switching layer, the capacitor layer, and the inductor layer; and wherein:the switching circuits, the capacitors and the inductors form a plurality of switching power supplies, each of the switching power supplies supplying power to a respective one of the processor cores.2. The three-dimensional switching power supply according to claim 1 , wherein each of the switching power supplies applies a respective one voltage level to one of the processor cores.3. The three-dimensional switching power supply ...

Semiconductor Device

A semiconductor device includes a semiconductor chip including a semiconductor substrate, an element formed in an element forming region of the semiconductor substrate, and a through-via penetrating across a front surface and a rear surface of the semiconductor substrate while avoiding the element forming region of the semiconductor substrate to form a conductive path between the front surface and the rear surface; a circuit component mounted on a circuit component connection surface at the same side as the front surface of the semiconductor substrate of the semiconductor chip; and an external connection members formed on the rear surface of the semiconductor substrate. 1. A voltage generating apparatus that generates a predetermined output voltage from an input voltage , the apparatus comprising:a semiconductor chip including a semiconductor substrate and an element formed in an element-forming region on a front surface of the semiconductor substrate;a circuit component mounted on a circuit component connection surface that is on the same side as the front surface of the semiconductor substrate of the semiconductor chip; andan external connection member provided on a rear surface of the semiconductor substrate,wherein the external connection member includes an input voltage terminal to which the input voltage is input, a ground terminal connected to a ground potential, and an output terminal from which the output voltage is output,wherein the element includes a first transistor and a second transistor connected in series between the input voltage terminal and the ground terminal,wherein the semiconductor chip further includes a control circuit that controls the first transistor and the second transistor,wherein the circuit component includes an inductor chip connected between the output terminal and a connection point of the first transistor and the second transistor, andwherein the inductor chip is disposed directly over the first transistor or the second ...

Systems and Methods for Microelectronics Fabrication and Packaging Using a Magnetic Polymer

A magnetic polymer for use in microelectronic fabrication includes a polymer matrix and a plurality of ferromagnetic particles disposed in the polymer matrix. The magnetic polymer can be part of an insulation layer in an inductor formed in one or more backend wiring layers of an integrated device. The magnetic polymer can also be in the form of a magnetic epoxy layer for mounting contacts of the integrated device to a package substrate. 1. (canceled)2. A structure comprising:a semiconductor integrated circuit or an integrated passive device comprising a multilevel wiring network fabricated on a semiconductor die; and a planar magnetic core;', 'a conductive winding that turns around in a spiral manner on the outside of said magnetic core, said conductive winding including at least one level from said multilevel wiring network; and', 'an insulation layer disposed between the magnetic core and the conductive winding, the insulation layer including a magnetic polymer, the magnetic polymer comprising:', 'a polymer matrix; and', 'a plurality of ferromagnetic particles disposed in the polymer matrix, the ferromagnetic particles having an average size of less than or equal to ten (10) microns., 'an inductor integrated into said multilevel wiring network, wherein said inductor comprises3. The structure of claim 2 , wherein the inductor forms at least a portion of a switched inductor power converter.4. The structure of claim 3 , wherein the inductor is configured to induce a magnetic flux parallel to a plane defined by the insulation layer.5. The structure of claim 4 , wherein the magnetic polymer has a magnetic anisotropy and a hard axis of magnetization parallel to a plane defined by the magnetic core.6. The structure of claim 3 , wherein the inductor is configured to induce a magnetic flux orthogonal to a plane defined by the insulation layer.7. The structure of claim 6 , wherein the magnetic polymer has a magnetic anisotropy and a hard axis of magnetization parallel to a ...

WIRELESS CHIP AND ELECTRONIC DEVICE HAVING WIRELESS CHIP

It is an object to provide a wireless chip which can increase a mechanical strength, and a wireless chip with a high durability. A wireless chip includes a transistor including a field-effect transistor, an antenna including a dielectric layer sandwiched between conductive layers, and a conductive layer connecting the chip and the antenna. Further, a wireless chip includes a transistor including a field-effect transistor, an antenna including a dielectric layer sandwiched between conductive layers, a sensor device, a conductive layer connecting the chip and the antenna, and a conductive layer connecting the chip and the sensor device. Moreover, a wireless chip includes a transistor including a field-effect transistor, an antenna including a dielectric layer sandwiched between conductive layers, a battery, a conductive layer connecting the chip and the antenna, and a conductive layer connecting the chip and the battery. 1an antenna including a first conductive layer, a second conductive layer functioning as a ground contact body, and a dielectric layer sandwiched between the first conductive layer and the second conductive layer,a chip including a field-effect transistor, anda third conductive layer connecting the antenna and the chip to each other.. A wireless chip comprising: The present invention relates to a wireless chip which can communicate data by wireless communication and an electronic device having a wireless chip.In recent years, development of a wireless chip including a plurality of circuits and an antenna is advanced. Such a wireless chip is called as an ID tag, an IC tag, an IC chip, an RF (Radio Frequency) tag, a wireless tag, an electronic tag, and an RFID (Radio Frequency Identification) tag, and has already been introduced into some markets.Many of these wireless chips which are put into practical use at present, include a circuit (referred to as an IC (Integrated Circuit) chip) with the use of a semiconductor substrate such as a silicon and an ...

MULTI-LAYER POWER CONVERTER WITH DEVICES HAVING REDUCED LATERAL CURRENT

An apparatus having a power converter circuit having a first active layer having a first set of active devices disposed on a face thereof, a first passive layer having first set of passive devices disposed on a face thereof, and interconnection to enable the active devices disposed on the face of the first active layer to be interconnected with the non-active devices disposed on the face of the first passive layer, wherein the face on which the first set of active devices on the first active layer is disposed faces the face on which the first set of passive devices on the first passive layer is disposed. 1. An apparatus comprising an active layer comprising first, second, third, and fourth switches, a passive layer comprising a fly capacitor, and an electrical interconnection between said active and passive layers, wherein said switches define a switching network that, when connected to said fly capacitor, defines a circuit having a first node connected to said first and second switches and to a first terminal of said fly capacitor, a second node connected to said second switch and third switches, and a third node connected to said third switch and fourth switches and to a second terminal of said fly capacitor. This application is a continuation of U.S. application Ser. No. 16/139,583, filed Sep. 24, 2018, which is a continuation of U.S. application Ser. No. 15/277,056, filed on Sep. 27, 2016, now U.S. Pat. No. 10,083,947, issued on Sep. 25, 2018, which is a continuation of U.S. application Ser. No. 14/294,642, filed on Jun. 3, 2014, now U.S. Pat. No. 9,497,854, issued on Nov. 15, 2016, which is a divisional of U.S. application Ser. No. 13/654,113, filed on Oct. 17, 2012, now U.S. Pat. No. 8,743,553, issued on Jun. 3, 2014, which claims the benefit of the priority date of U.S. Provisional Application No. 61/548,360, filed on Oct. 18, 2011, the contents of which are herein incorporated by reference.The present invention relates to energy storage elements in power ...

ELECTRONIC COMPONENTS HAVING THREE-DIMENSIONAL CAPACITORS IN A METALLIZATION STACK

Disclosed herein are electronic components having three-dimensional capacitors disposed in a metallization stack, as well as related methods and devices. In some embodiments, for example, an electronic component may include: a metallization stack and a capacitor disposed in the metallization stack wherein the capacitor includes a first conductive plate having a plurality of recesses, and a second conductive plate having a plurality of projections, wherein individual projections of the plurality of projections extend into corresponding individual recesses of the plurality of recesses without contacting the first conductive plate. 1. An electronic component , comprising:a metallization stack; anda capacitor disposed in the metallization stack, wherein the capacitor includes:a first conductive plate having a plurality of recesses, anda second conductive plate having a plurality of projections, wherein individual projections of the plurality of projections of the second conductive plate extend into corresponding individual recesses of the plurality of recesses without contacting the first conductive plate.2. The electronic component of claim 1 , wherein the first conductive plate has a plurality of projections claim 1 , and the plurality of recesses and the plurality of projections of the first conductive plate alternate in the first conductive plate in a parallel ridge pattern.3. The electronic component of claim 2 , wherein the first conductive plate has a plurality of projections claim 2 , and the plurality of recesses and the plurality of projections of the first conductive plate alternate in the first conductive plate in a checkerboard pattern.4. The electronic component of claim 1 , further comprising:a dielectric material extending between the first conductive plate and the second conductive plate.5. The electronic component of claim 1 , wherein individual ones of the plurality of recesses are tapered.6. The electronic component of claim 5 , wherein individual ...

SOC WITH INTEGRATED VOLTAGE REGULATOR USING PREFORMED MIM CAPACITOR WAFER

In some embodiments, a method and/or a system may include an integrated circuit. The integrated circuit may include a semiconductor die. The integrated circuit may include a plurality of wiring layers. At least one metal-insulator-metal (MIM) capacitor may be formed within the plurality of wiring layers. The integrated circuit may include a circuit. The circuit may include at least an inductor and a voltage regulator which, with the MIM capacitor, forms a voltage regulator for the semiconductor die. The circuit may be coupled substantially below at least a portion of the MIM capacitor in the plurality of layers. The circuit may be electrically coupled to the capacitor through the plurality of wiring layers. The integrated circuit may include a plurality of electrical connectors, the plurality of electrical connectors coupled to the second surface at points separate from an area of the second surface that is occupied by the circuit. 1. An integrated circuit , comprising:a semiconductor die;a plurality of wiring layers, wherein at least one metal-insulator-metal (MIM) capacitor is formed within the plurality of wiring layers, and wherein the plurality of wiring layers further include conductors to couple the semiconductor die from a first surface of the plurality of wiring layers that abuts the semiconductor die to a second surface of the plurality of wiring layers that is opposite to the first surface;a circuit including at least an inductor and a voltage regulator which, with the MIM capacitor, forms a voltage regulator for the semiconductor die, the circuit arranged substantially below at least a portion of the MIM capacitor in the plurality of layers, wherein the circuit is electrically coupled to the capacitor through the plurality of wiring layers; anda plurality of electrical connectors to couple the integrated circuit to a circuit board, the plurality of electrical connectors coupled to the second surface at points separate from an area of the second surface ...

SEMICONDUCTOR DEVICE

A semiconductor device is provided with: a semiconductor integrated circuit having a bump mounting surface; and a thin-film capacitor portion connected to the bump mounting surface via a bump. The semiconductor integrated circuit includes a first power supply pad, and a second power supply pad. The thin-film capacitor portion includes a first electrode layer connected to the first power supply pad, a second electrode layer connected to the second power supply pad, and a dielectric layer formed between the first electrode layer and the second electrode layer. The semiconductor device is provided with an electric power supply path configured to supply electric power to the semiconductor integrated circuit, and a thin plate-shaped metal resistor portion provided in the electric power supply path and made from a metal based high-resistance material having a volume resistivity higher than a volume resistivity of the first electrode layer and the second electrode layer. 1. A semiconductor device comprising:a semiconductor integrated circuit having a bump mounting surface; anda thin-film capacitor portion connected to the bump mounting surface via a bump,wherein:the semiconductor integrated circuit includesa first power supply pad formed on the bump mounting surface and to which a power supply voltage of one polarity is applied, anda second power supply pad formed on the bump mounting surface and to which a power supply voltage of another polarity is applied; andthe thin-film capacitor portion includesa first electrode layer connected to the first power supply pads via the bump,a second electrode layer connected to the second power supply pads via the bump, anda dielectric layer formed between the first electrode layer and the second electrode layer,the semiconductor device comprisingan electric power supply path configured to supply electric power to the semiconductor integrated circuit, anda thin plate-shaped metal resistor portion provided in the electric power supply ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF

A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a semiconductor device comprising multiple encapsulating layers and multiple signal distribution structures, and a method of manufacturing thereof. 1. A semiconductor device comprising:a first signal distribution structure (SDS) having a top SDS side, a bottom SDS side, and a plurality of lateral SDS sides, wherein the first SDS comprises a first dielectric layer and a first conductive layer;a first electronic component coupled to the top SDS side;a first encapsulating material that covers at least a portion of the top SDS side and at least a portion of the first electronic component;a semiconductor die coupled to the bottom SDS side and positioned directly below the first electronic component;a plurality of conductive pillars coupled to the bottom SDS side and positioned laterally around the semiconductor die; anda second encapsulating material that covers at least a portion of the bottom SDS side, at least a portion of the semiconductor die, and at least a portion of the conductive pillars.2. The semiconductor device of claim 1 , wherein a bottom side of each of the conductive pillars and a bottom side of the semiconductor die are exposed from the second encapsulating material at a bottom side of the second encapsulating material.3. The semiconductor device of claim 2 , wherein the bottom side of each of the conductive pillars claim 2 , the bottom side of the semiconductor die claim 2 , and the bottom side of the second encapsulating material are coplanar.4. The semiconductor device of claim 1 , comprising a lower dielectric layer on a bottom side of the second encapsulating material claim 1 , wherein the lower dielectric layer comprises a plurality of apertures claim 1 , each of the apertures exposing a respective one of the conductive pillars through the lower dielectric layer.5. The semiconductor device of claim 4 , ...

BRIDGE INTERCONNECTION WITH LAYERED INTERCONNECT STRUCTURES

Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed. 1. An IC assembly , comprising:a package substrate, the package substrate comprising a dielectric material;a bridge in the package substrate, the bridge comprising silicon, wherein the dielectric material of the package substrate is over and in contact with the bridge;a first joint over and electrically coupled to the bridge, the first joint in the dielectric material and extending above the dielectric material, and the first joint comprising copper;a first layer on the first joint, the first layer comprising nickel;a second joint over and electrically coupled to the bridge, the second joint in the dielectric material and extending above the dielectric material, and the second joint comprising copper;a second layer on the second joint, the second layer comprising nickel;a first interconnect structure in the package substrate, the first interconnect structure laterally spaced from a first side of the bridge, and the first interconnect in the dielectric material;a second interconnect structure in the package substrate, the second interconnect structure laterally spaced from a second side of the bridge, and the second ...

SEMICONDUCTOR PACKAGE ASSEMBLY

In one implementation, a semiconductor package assembly includes a semiconductor die, a first molding compound covering a back surface of the semiconductor die, a redistribution layer (RDL) structure disposed on a front surface of the semiconductor die, wherein the semiconductor die is coupled to the RDL structure, and a passive device, embedded in the redistribution layer (RDL) structure and coupled to the semiconductor die. 1. A semiconductor package assembly , comprising:a semiconductor die;a first molding compound covering a back surface of the semiconductor die;a redistribution layer (RDL) structure disposed on a front surface of the semiconductor die, wherein the semiconductor die is coupled to the RDL structure;a passive device, embedded in the redistribution layer (RDL) structure and coupled to the semiconductor die.2. The semiconductor package assembly as claimed in claim 1 , further comprising:a second molding compound disposed on the front surface of the semiconductor die and embedded in the redistribution layer (RDL) structure.3. The semiconductor package assembly as claimed in claim 2 , further comprising:a conductive bump passing through the second molding compound, wherein the passive device is coupled to the semiconductor die through the conductive bump.4. The semiconductor package assembly as claimed in claim 2 , wherein a sidewall of the second molding compound is surrounded by the redistribution layer (RDL) structure.5. The semiconductor package assembly as claimed in claim 2 , wherein the first molding compound is separated from the second molding compound through the semiconductor die and the redistribution layer (RDL) structure.6. The semiconductor package assembly as claimed in claim 2 , wherein an interface between the passive device and the second molding compound is aligned to a first surface of the redistribution layer (RDL) structure claim 2 , which is away from the semiconductor die.7. The semiconductor package assembly as claimed in ...

Multi-Die Fine Grain Integrated Voltage Regulation

A semiconductor device package is described that includes a power consuming device (such as an SOC device). The power consuming device may include one or more current consuming elements. A passive device may be coupled to the power consuming device. The passive device may include a plurality of passive elements formed on a semiconductor substrate. The passive elements may be arranged in an array of structures on the semiconductor substrate. The power consuming device and the passive device may be coupled using one or more terminals. The passive device and power consuming device coupling may be configured in such a way that the power consuming device determines functionally the way the passive device elements will be used. 120-. (canceled)21. A switched capacitor circuit , comprising:a first semiconductor substrate;a plurality of passive structures formed on the first semiconductor substrate, wherein the plurality of passive structures is arranged in a tiled pattern on the first semiconductor substrate, and wherein at least two of the passive structures include at least one capacitor formed on the first semiconductor substrate;a second semiconductor substrate coupled to the first semiconductor substrate; andat least one current consuming element formed on the second semiconductor substrate;wherein the at least two passive structures are coupled to the at least one current consuming element in a particular manner to provide a voltage conversion circuit for the at least one current consuming element.22. The circuit of claim 21 , wherein the second semiconductor substrate is coupled to the first semiconductor substrate by a plurality of terminals.23. The circuit of claim 21 , wherein the at least two passive structures are coupled to the at least one current consuming element by at least two terminals.24. The circuit of claim 23 , wherein at least one terminal is positioned inside of each of the at least two passive structures claim 23 , wherein a terminal positioned ...

MAGNETIC SMALL FOOTPRINT INDUCTOR ARRAY MODULE FOR ON-PACKAGE VOLTAGE REGULATOR

An apparatus comprises an inductor module including: a module substrate including a magnetic dielectric material: a plurality of inductive circuit elements arranged in the module substrate, wherein an inductive circuit element includes conductive traces arranged as a coil including a first coil end, a second coil end and a coil core, wherein the coil core includes the magnetic dielectric material; and a plurality of conductive contact pads electrically coupled to the first and second coil ends. The contact pads electrically coupled to the first coil ends are arranged on a first surface of the inductor module, and the contact pads electrically coupled to the second coil ends are arranged on a second surface of the inductor module. 1. An apparatus comprising:an integrated circuit (IC); a module substrate including a magnetic dielectric material;', 'a plurality of inductive circuit elements arranged in the module substrate, wherein an inductive circuit element includes conductive traces arranged as a coil including a first coil end, a second coil end and a coil core, wherein the coil core includes the magnetic dielectric material; and', 'a plurality of conductive contact pads electrically coupled to first coil and second coil ends and arranged on one surface of the inductor module; and, 'an inductor module includinga package substrate of an electronic package assembly, wherein the package substrate includes conductive interconnect between the inductor module and the IC, and the IC is arranged on a separate surface of the package substrate from the inductor module.2. The apparatus of claim 1 , wherein the IC is arranged on a first surface of the package substrate and includes a voltage regulator circuit and a processor circuit claim 1 , and wherein the inductor module is arranged on a second surface of the package substrate.3. The apparatus of claim 1 , wherein the IC is arranged on a first surface of the package substrate and includes a voltage regulator circuit and a ...

Integrated circuit package and method of fabricating the same

An integrated circuit package including an integrated circuit component, a patterned dielectric liner, an insulating encapsulation, and a redistribution circuit structure is provided. The integrated circuit component includes an active surface and conductive vias distributed on the active surface. The patterned dielectric liner conformally covers the active surface of the integrated circuit component and sidewalls of the conductive vias. The insulating encapsulation encapsulates sidewalls of the integrated circuit component and covers the patterned dielectric liner. The insulating encapsulation includes a planar top surface. The planar top surface of the insulating encapsulation is substantially coplanar with top surfaces of the conductive vias. The insulating encapsulation and the conductive vias are spaced apart by the patterned dielectric liner. The redistribution circuit structure is disposed on the planar top surface of the insulating encapsulation, the top surfaces of the conductive vias and the patterned dielectric liner. The redistribution circuit structure is electrically connected to the conductive vias.

ENABLING MAGNETIC FILMS IN INDUCTORS INTEGRATED INTO SEMICONDUCTOR PACKAGES

Techniques for fabricating a semiconductor package comprising inductor features and a magnetic film are described. For one technique, fabricating a package includes: forming inductor features comprising a pad and a conductive line on a first build-up layer; forming a raised pad structure on the first build-up layer by fabricating a pillar structure on the pad, wherein a size of the pillar structure is approximately equal or equal to a corresponding size of the pad such that the pillar structure and the pad are aligned or minimally misaligned relative to each other; encapsulating the inductor features and the raised pad structure in a magnetic film; planarizing the magnetic film until top surfaces of the raised pad structure and magnetic film are co-planar; depositing an additional layer on the top surfaces; and forming a via on the raised pad structure by removing portions of the additional layer above the raised pad structure. 1. A semiconductor package , comprising:a plurality of inductor features on a first build-up layer, the plurality of inductor features comprising a pad and a conductive line;a raised pad structure on the first build-up layer, the raised pad structure comprising a pillar structure on the pad, wherein a size of the pillar structure is approximately equal or equal to a corresponding size of the pad such that the pillar structure and the pad are aligned or minimally misaligned relative to each other;a magnetic film encapsulating the plurality of inductor features and the raised pad structure in a magnetic film, the magnetic film comprising one or more magnetic fillers, wherein top surfaces of the raised pad structure and the magnetic film are co-planar;an additional layer on the top surfaces of the raised pad structure and the magnetic film; anda via on the top surface of the raised pad structure, the via being formed through the additional layer.2. The semiconductor package of claim 1 , wherein the raised pad structure has a z-height that is ...

Multiple bond via arrays of different wire heights on a same substrate

Apparatuses relating generally to a substrate are disclosed. In such an apparatus, first wire bond wires (“first wires”) extend from a surface of the substrate. Second wire bond wires (“second wires”) extend from the surface of the substrate. The first wires and the second wires are external to the substrate. The first wires are disposed at least partially within the second wires. The first wires are of a first height. The second wires are of a second height greater than the first height for coupling of at least one electronic component to the first wires at least partially disposed within the second wires.

Semiconductor chip package assembly with improved heat dissipation performance

A semiconductor chip package assembly includes a package substrate having a chip mounting surface; a plurality of solder pads disposed on the chip mounting surface; a first dummy pad and a second dummy pad spaced apart from the first dummy pad disposed on the chip mounting surface; a solder mask on the chip mounting surface and partially covering the solder pads, the first dummy pad, and the second dummy pad; a chip package mounted on the chip mounting surface and electrically connected to the package substrate through a plurality of solder balls on respective said solder pads; a discrete device having a first terminal and a second terminal disposed between the chip package and the package substrate; a first solder connecting the first terminal with the first dummy pad and the chip package; and a second solder connecting the second terminal with the second dummy pad and the chip package.

INTEGRATED ANTENNA ARRAY PACKAGING STRUCTURES AND METHODS

An apparatus includes an antenna array package cover comprising a radiating surface, a mating surface disposed opposite the radiating surface, and an array of antenna array sub-patterns wherein each antenna array sub-pattern comprises at least one antenna element. The antenna array package also includes an array of sub-pattern interface packages mated to the mating surface of the antenna array package cover. Each sub-pattern interface package of the array of sub-pattern interface packages comprises a package carrier, a sub-pattern integrated circuit electrically and mechanically coupled to the package carrier, and a set of interface lines corresponding to the antenna elements of the antenna array sub-pattern that corresponds to the sub-pattern interface package. Methods for mounting the above apparatus into a host circuit are also disclosed herein. 1. An apparatus comprising:an antenna array package cover comprising a radiating surface, a mating surface disposed opposite the radiating surface, and an array of antenna array sub-patterns wherein each antenna array sub-pattern comprises at least one antenna element;an array of sub-pattern interface packages mated to the mating surface of the antenna array package cover; andwherein each sub-pattern interface package of the array of sub-pattern interface packages comprises a package carrier, a sub-pattern integrated circuit electrically and mechanically coupled to the package carrier, and a set of interface lines corresponding to the antenna elements of the antenna array sub-pattern that corresponds to the sub-pattern interface package.2. The apparatus of claim 1 , wherein each sub-pattern interface package of the array of sub-pattern interface packages is disposed below a corresponding antenna array sub-pattern of the array of antenna array sub-patterns.3. The apparatus of claim 1 , wherein the sub-pattern integrated circuit is flip-chip bonded to the package carrier.4. The apparatus of claim 1 , wherein the antenna ...

Nanowires plated on nanoparticles

In some examples, a system comprises a set of nanoparticles and a set of nanowires extending from the set of nanoparticles.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

According to one embodiment, a semiconductor device includes an insulative resin, an interconnect, a plurality of semiconductor elements, and a first metal member. The insulative resin includes a first region and a second region. The interconnect is arranged with the first region in a first direction. The first direction intersects a direction from the first region toward the second region. The plurality of semiconductor elements is provided between the first region and the interconnect. At least one of the plurality of semiconductor elements is electrically connected to the interconnect. The first metal member includes a first through-portion and a first end portion. The first through-portion pierces the second region in the first direction. The first end portion is connected to the first through-portion. A width of the first end portion is wider than a width of the first through-portion in a second direction intersecting the first direction. 1. A semiconductor device , comprising:an insulative resin including a first region and a second region;an interconnect arranged with the first region in a first direction intersecting a direction from the first region toward the second region;a plurality of semiconductor elements provided between the first region and the interconnect, at least one of the plurality of semiconductor elements being electrically connected to the interconnect; anda first metal member including a first through-portion and a first end portion, the first through-portion piercing the second region in the first direction, the first end portion being connected to the first through-portion,a width of the first end portion being wider than a width of the first through-portion in a second direction intersecting the first direction.2. The device according to claim 1 , whereinthe first end portion is continuous with the first through-portion, anda material included in the first through-portion is the same as a material included in the first end portion.3. ...

Method of Manufacturing Semiconductor Device that Uses Bonding Layer to Join Semiconductor Substrates Together

Semiconductor devices are provided in which a first semiconductor device is bonded to a second semiconductor device. The bonding may occur at a gate level, a gate contact level, a first metallization layer, a middle metallization layer, or a top metallization layer of either the first semiconductor device or the second semiconductor device. 1. A semiconductor device comprising:a first interconnection structure adjacent to a first semiconductor substrate, wherein the first interconnection structure is in electrical contact with a first gate contact through at least a second interconnection structure;a first dielectric layer over the first interconnection structure;a second interconnection structure adjacent to a second semiconductor substrate, wherein the second interconnection structure is bonded to the first bonding layer;an encapsulant encapsulating the second interconnection structure; anda third interconnection structure located on an opposite side of the encapsulant from the first interconnection structure, wherein the third interconnection structure is in electrical connection with both the first interconnection structure and the second interconnection structure.2. The semiconductor device of claim 1 , further comprising a fourth interconnection structure adjacent to a third semiconductor substrate claim 1 , the fourth interconnection structure bonded to the first bonding layer.3. The semiconductor device of claim 2 , wherein the encapsulant encapsulates the fourth interconnection structure.4. The semiconductor device of claim 1 , further comprising a through via extending through the encapsulant.5. The semiconductor device of claim 1 , further comprising a through via extending through the second semiconductor substrate.6. The semiconductor device of claim 5 , wherein the through via is electrically connected to the third interconnection structure.7. The semiconductor device of claim 1 , wherein the encapsulant has a height of between about 500 nm and about ...

WIRELESS IC DEVICE, RESIN MOLDED BODY COMPRISING SAME, COMMUNICATION TERMINAL APPARATUS COMPRISING SAME, AND METHOD OF MANUFACTURING SAME

A wireless IC device includes an element body including first and second principal surfaces, an RFIC element buried in the element body, and an antenna coil disposed in the element body. The antenna coil includes a first wiring pattern provided on the second principal surface, a first metal pin reaching the first principal surface and the second principal surface, a second metal pin reaching the first principal surface and the second principal surface, and a second wiring pattern provided on the first principal surface. Terminal surfaces of the first input/output terminal and the second input/output terminal of the RFIC element face the second principal surface of the element body and are spaced away from the antenna coil while being connected to the first wiring pattern through first and second conductors extending from the second principal surface of the element body in a direction of the first primary surface. 1. A wireless IC device comprising:an element body including a first principal surface and a second principal surface opposite to the first principal surface;an RFIC element buried in the element body and including a first input/output terminal and a second input/output terminal; andan antenna coil disposed in the element body and including one end connected to the first input/output terminal and the other end connected to the second input/output terminal; wherein a first wiring pattern provided on the second principal surface side of the element body and connected to the first input/output terminal and the second input/output terminal of the RFIC element;', 'a first metal pin including a first end and a second end reaching the first principal surface and the second principal surface of the element body and connected at the first end to the first wiring pattern;', 'a second metal pin including a third end and a fourth end reaching the first principal surface and the second principal surface of the element body and connected at the third end to the first ...

Method of Manufacturing an Integrated Fan-out Package having Fan-Out Redistribution Layer (RDL) to Accommodate Electrical Connectors

A method includes forming a through-via from a first conductive pad of a first device die. The first conductive pad is at a top surface of the first device die. A second device die is adhered to the top surface of the first device die. The second device die has a surface conductive feature. The second device die and the through-via are encapsulated in an encapsulating material. The encapsulating material is planarized to reveal the through-via and the surface conductive feature. Redistribution lines are formed over and electrically coupled to the through-via and the surface conductive feature. 1. A package comprising:a first device die comprising a conductive pad;an adhesive film comprising a bottom surface adhere to a top surface of the first device die;a second device die comprising a bottom surface adhered to a top surface of the adhesive film;a through-via having a bottom surface in contact with the conductive pad of the first device die;an encapsulant encapsulating the second device die and the through-via therein; anda dielectric layer comprising a bottom surface in contact with top surfaces of the through-via, the encapsulant, and the second device die, wherein the through-via comprises a substantially straight edge extending from the dielectric layer to the conductive pad.2. The package of claim 1 , wherein the conductive pad extends from a level coplanar with the bottom surface of the adhesive film into the first device die.3. The package of claim 1 , wherein the encapsulant has edges aligned to respective edges of the first device die.4. The package of claim 1 , wherein the first device die is further encircled by the encapsulant.5. The package of claim 4 , wherein the second device die comprises a first portion overlapping a portion of the first device die claim 4 , and a second portion overlapping a portion of the encapsulant.6. The package of further comprising a third device die coplanar with the first device die claim 5 , wherein the second device die ...

Bridge interconnection with layered interconnect structures

Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.

POWER DECOUPLING ATTACHMENT

An embodiment of the invention may include a method, and resulting structure, of forming a semiconductor structure. The method may include forming a component hole from a first surface to a second surface of a base layer. The method may include placing an electrical component in the component hole. The electrical component has a conductive structure on both ends of the electrical component. The electrical component is substantially parallel to the first surface. The method may include forming a laminate layer on the first surface of the base layer, the second surface of the base layer, and between the base layer and the electrical component. The method may include creating a pair of via holes, where the pair of holes align with the conductive structures on both ends of the electrical component. The method may include forming a conductive via in the pair of via holes. 1. A method of forming a semiconductor structure , the method comprising:forming a component hole from a first surface to a second surface of a base layer;placing an electrical component in the component hole, wherein the electrical component comprises a conductive structure on both ends of the electrical component, and wherein the electrical component is substantially parallel to the first surface;forming a laminate layer on the first surface of the base layer, the second surface of the base layer, and between the base layer and the electrical component;forming conductive pads on the laminate layer, wherein each conductive pad is a separate structure on a surface of the laminate layer from the other conductive pads;creating via holes through each of the conductive pads, wherein the via holes extend from the conductive structures on both ends of the electrical component to the first surface of the base layer and the second surface of the base layer; andforming a conductive via in the via holes.2. The method of claim 1 , further comprising:forming a conductive layer on the laminate layer;forming a ...