Semiconductor-encapsulating adhesive, semiconductor-encapsulating film-form adhesive, method for producing semiconductor device, and semiconductor device

The present invention relates to a semiconductor-encapsulating adhesive, a semiconductor-encapsulating film-form adhesive, a method for producing a semiconductor device, and a semiconductor device. The present invention provides a semiconductor-encapsulating adhesive comprising (a) an epoxy resin, and (b) a compound formed of an organic acid reactive with an epoxy resin and a curing accelerator.

Semiconductor Device and Method of Making a Semiconductor Device

A semiconductor device and a method of manufacturing a semiconductor device are disclosed. An embodiment comprises forming a bump on a die, the bump having a solder top, melting the solder top by pressing the solder top directly on a contact pad of a support substrate, and forming a contact between the die and the support substrate.

Semiconductor package

A semiconductor package includes a plurality of connection pads, which are electrically connected to connection terminals of a mounted component that is mounted on the semiconductor package, and recognition marks. The recognition marks are formed respectively within the area of each of at least two of the connection pads. Each recognition mark has an area that is smaller than the area of the connection mark in which it is formed.

Bump-on-trace (bot) structures

A bump-on-trace (BOT) structure is described. The BOT structure includes a first work piece with a metal trace on a surface of the first work piece, wherein the metal trace has a first axis. The BOT structure further includes a second work piece with an elongated metal bump, wherein the elongated metal bump has a second axis, wherein the second axis is at a non-zero angle from the first axis. The BOT structure further includes a metal bump, wherein the metal bump electrically connects the metal trace and the elongated metal bump. A package having a BOT structure and a method of forming the BOT structure are also described.

Semiconductor device, electronic device, and semiconductor device manufacturing method

A semiconductor device, includes: a connection member including a first pad formed on a principal surface thereof; a semiconductor chip including a circuit-formed surface on witch a second pad is formed, the chip mounted on the connection member so that the circuit-formed surface faces the principal surface; and a solder bump that connects the first and second pads and is made of metal containing Bi and Sn, wherein the bump includes a first interface-layer formed adjacent to the second pad, a second interface-layer formed adjacent to the first pad, a first intermediate region formed adjacent to either one of the interface-layers, and a second intermediate region formed adjacent to the other one of the interface-layers and formed adjacent to the first intermediate region; Bi-concentration in the first intermediate region is higher than a Sn-concentration; and a Sn-concentration in the second intermediate region is higher than a Bi-concentration.

Flip packaging device

Disclosed is a flip chip packaging device and structure of interconnections between a chip and a substrate. In one embodiment, a flip chip packaging device can include: (i) a chip and a substrate; (ii) a plurality of first connecting structures and a plurality of second connecting structures that are aligned and configured to electrically connect the chip and the substrate; and (iii) where each of the plurality of first connecting structures comprises a first metal, and each of the plurality of second connecting structures comprises a second metal, and where a hardness of the first metal is less than a hardness of the second metal.

Planar integrated circuit package interconnects

Generally discussed herein are systems, methods, and apparatuses that include conductive pillars that are about co-planar. According to an example, a technique can include growing conductive pillars on respective exposed landing pads of a substrate, situating molding material around and on the grown conductive pillars, removing, simultaneously, a portion of the grown conductive pillars and the molding material to make the grown conductive pillars and the molding material about planar, and electrically coupling a die to the conductive pillars.

Semiconductor Package and Method

In an embodiment, a device includes: a back-side redistribution structure including: a metallization pattern on a first dielectric layer; and a second dielectric layer on the metallization pattern; a through via extending through the first dielectric layer to contact the metallization pattern; an integrated circuit die adjacent the through via on the first dielectric layer; a molding compound on the first dielectric layer, the molding compound encapsulating the through via and the integrated circuit die; a conductive connector extending through the second dielectric layer to contact the metallization pattern, the conductive connector being electrically connected to the through via; and an intermetallic compound at the interface of the conductive connector and the metallization pattern, the intermetallic compound extending only partially into the metallization pattern.

SEMICONDUCTOR DEVICE AND METHOD

Disclosed herein is a semiconductor device that includes a semiconductor die and a substrate including a first surface and a second surface. The substrate includes a conductive circuit and an insulative material over the conductive circuit. The semiconductor die is attached to the second surface. The semiconductor device further includes an interconnect joint structure in the substrate creating a capture pad including a middle copper layer, an adjacent top nickel layer, and an adjacent bottom nickel layer. A method for making a semiconductor device is further disclosed. 1. A semiconductor device comprising:a semiconductor die;a substrate including a first surface and a second surface, the substrate comprising a conductive circuit and an insulative material over the conductive circuit, wherein the semiconductor die is attached to the second surface; andan interconnect joint structure in the substrate creating a capture pad including a middle copper layer, an adjacent top nickel layer, and an adjacent bottom nickel layer.2. The semiconductor device of claim 1 , wherein the conductive circuit includes an etched layer of conductive foil that is located on the first surface of the substrate.3. The semiconductor device of claim 1 , wherein the interconnect joint structure is found in a single layer of the insulative material.4. The semiconductor device of claim 1 , wherein the semiconductor die is attached to the substrate without a via.5. The semiconductor device of claim 1 , wherein the substrate and interconnect joint structure are formed using a build-up process.6. The semiconductor device of claim 1 , wherein the substrate and interconnect joint structure are formed using a subtractive process.7. The semiconductor device of claim 1 , wherein the insulative material comprises a layer that is less than 12 μm thick.8. The semiconductor device of claim 1 , wherein the substrate further includes an etched foil layer claim 1 , and wherein the substrate further includes a ...

SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD

A semiconductor device, includes: a connection member including a first pad formed on a principal surface thereof; a semiconductor chip including a circuit-formed surface on which a second pad is formed, the chip mounted on the connection member so that the circuit-formed surface faces the principal surface; and a solder bump that connects the first and second pads and is made of metal containing Bi and Sn, wherein the bump includes a first interface-layer formed adjacent to the second pad, a second interface-layer formed adjacent to the first pad, a first intermediate region formed adjacent to either one of the interface-layers, and a second intermediate region formed adjacent to the other one of the interface-layers and formed adjacent to the first intermediate region; Bi-concentration in the first intermediate region is higher than a Sn-concentration; and a Sn-concentration in the second intermediate region is higher than a Bi-concentration. 110-. (canceled)11. A semiconductor device manufacturing method , comprising:forming a first connection pad on a first principal surface of a first connection member;forming a second connection pad on a circuit-formed surface of a fast semiconductor chip on which a semiconductor integrated circuit is formed;placing the fast semiconductor chip on the first connection member in such a manner that the circuit-formed surface faces the first principal surface and the first connection pad contacts the second connection pad through a solder bump containing a Sn—Bi alloy;reflowing the solder bump for joining the first connection pad and the second connection pad; andapplying a direct current after the joining between the first connection pad and the second connection pads using either one of the first or second connection pad as an anode and using the other one of the first and second connection pads as cathode, so as to concentrate Bi in the solder bump into a neighborhood of the anode and to concentrate Sn in the solder bump into a ...

Pre-package and methods of manufacturing semiconductor package and electronic device using the same

Methods of fabricating semiconductor packages are provided. One of the methods includes forming a protection layer including metal on a first surface of a substrate to cover a semiconductor device disposed on the first surface of the substrate, attaching a support substrate to the protection layer by using an adhesive member, processing a second surface of the substrate opposite to the protection layer to remove a part of the substrate, and detaching the support substrate from the substrate.

BRIDGE INTERCONNECTION WITH LAYERED INTERCONNECT STRUCTURES

Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed. 1. An IC assembly , comprising:a package substrate having a cavity;a bridge embedded in the cavity of the package substrate, the bridge comprising silicon;a dielectric material over the bridge;a first joint over and electrically coupled to the bridge, the first joint in the dielectric material and extending above the dielectric material, and the first joint comprising copper;a first layer on the first joint, the first layer comprising nickel;a second joint over and electrically coupled to the bridge, the second joint in the dielectric material and extending above the dielectric material, and the second joint comprising copper;a second layer on the second joint, the second layer comprising nickel;a first interconnect structure in the package substrate, the first interconnect structure laterally spaced from a first side of the bridge;a second interconnect structure in the package substrate, the second interconnect structure laterally spaced from a second side of the bridge;a first die electrically coupled to the first joint and the first interconnect structure; anda second die electrically coupled to the second joint and the ...

Integrated Circuit Structure Having Dies with Connectors of Different Sizes

An embodiment is a structure comprising a substrate, a first die, and a second die. The substrate has a first surface. The first die is attached to the first surface of the substrate by first electrical connectors. The second die is attached to the first surface of the substrate by second electrical connectors. A size of one of the second electrical connectors is smaller than a size of one of the first electrical connectors. 1. A structure comprising:an interposer;a first die on a first surface of the interposer, the first die being electrically and mechanically coupled to the interposer by first connectors, the first connectors having a first diameter and having a first pitch between adjacent ones of the first connectors; and a first under bump metal (UBM) structure on a lower side of the second die facing the interposer;', 'a first metal pillar electrically and mechanically coupled to the first UBM structure;', 'a second UBM structure on the first surface of the interposer;', 'a second metal pillar electrically and mechanically coupled to the second UBM structure; and', 'a solder material between and electrically coupling the first metal pillar and the second metal pillar, wherein sidewalls of the first metal pillar are free of the solder material., 'a second die on the first surface of the interposer, the second die being electrically and mechanically coupled to the interposer by second connectors, the second connectors having a second diameter and having a second pitch between adjacent ones of the second connectors, the first diameter being greater than the second diameter, and the first pitch being greater than the second pitch, wherein each of the second connectors comprises2. The structure of claim 1 , wherein the solder material extends along sidewalls of the second metal pillar toward the first surface of the interposer.3. The structure of claim 2 , wherein sidewalls of the second UBM structure are covered by the solder material.4. The structure of claim 1 ...

Semiconductor package structure and manufacturing method thereof

A semiconductor package structure including a circuit substrate, a redistribution layer, and at least two dies is provided. The circuit substrate has a first surface and a second surface opposite the first surface. The redistribution layer is located on the first surface. The redistribution layer is electrically connected to the circuit substrate. The spacing of the opposing sidewalls of the redistribution layer is less than the spacing of the opposing sidewalls of the circuit substrate. The redistribution layer is directly in contact with the circuit substrate. At least two dies are disposed on the redistribution layer. Each of the at least two dies has an active surface facing the circuit substrate. One of the at least two dies is electrically connected to the other of the at least two dies by the redistribution layer. A manufacturing method of a semiconductor package structure is also provided.

Chip-on-film package having bending part

A chip-on-film package comprises a film substrate comprising upper and lower surfaces, and a side having a bending part. A first output interconnection formed on the upper surface of the film substrate extends from a semiconductor chip disposed on the upper surface toward the bending part. A second output interconnection includes an upper output interconnection formed on the upper surface of the film substrate, and a lower output interconnection formed on the lower surface and extending onto the bending part. An input interconnection includes an upper input interconnection formed on the upper surface of the film substrate and a lower input interconnection formed on the lower surface and extending away from the bending part. Through-vias are formed to pass through the film substrate and electrically connect the upper output interconnection to the lower output interconnection, and the upper input interconnection to the lower input interconnection.

Elongated Bump Structures in Package Structure

A package structure includes a chip attached to a substrate. The chip includes a bump structure including a conductive pillar having a length (L) measured along a long axis of the conductive pillar and a width (W) measured along a short axis of the conductive pillar. The substrate includes a pad region and a mask layer overlying the pad region, wherein the mask layer has an opening exposing a portion of the pad region. The chip is attached to the substrate to form an interconnection between the conductive pillar and the pad region. The opening has a first dimension (d) measured along the long axis and a second dimension (d) measured along the short axis. In an embodiment, L is greater than d, and W is less than d 1. A method of forming a package structure , comprising:placing a conductive structure over an opening through a masking layer, the opening exposing a conductive element; andreflowing a portion of the conductive structure to bond the conductive structure to the conductive element, wherein after the reflowing the portion of the conductive structure the conductive structure extends in a first direction further than the opening and extends in a second direction less than the opening, the first direction being perpendicular to the second direction.2. The method of claim 1 , wherein the conductive structure comprises a first length along a first axis and a first width along a second axis perpendicular to the first axis claim 1 , the first length being longer than the first width.3. The method of claim 2 , wherein the first length is between about 70 μm and about 150 μm.4. The method of claim 3 , wherein the first width is between about 40 and about 100 μm.5. The method of claim 2 , wherein a ratio between the first length and the first width is between about 1.75 and about 1.5.6. The method of claim 1 , further comprising a molding compound located adjacent to the conductive structure.7. The method of claim 1 , wherein there is no molding compound adjacent to ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A flip-chip mounting technique with high reliability is provided in flip-chip mounting using a Cu pillar. In a semiconductor device to be coupled to a mounting board via a Cu pillar, the Cu pillar is caused to have a laminated structure including a pillar layer, a barrier layer, and a bump in this order from below, and the bump is formed to be smaller than the barrier layer. 1. A manufacturing method of a semiconductor device , comprising the steps of:(a) applying a resist film over a terminal pad formed over a main surface of a semiconductor substrate;(b) forming an opening in the resist film for exposing the terminal pad in the bottom thereof;(c) forming a Cu film, an Ni film, and an SnAg film in the opening in this order from below;(d) removing the resist film; and(e) etching an outer peripheries of the SnAg film.2. The manufacturing method of a semiconductor device according to claim 1 ,wherein, in the step (e), the etching is performed by using dilute hydrofluoric acid.3. The manufacturing method of a semiconductor device according to claim 1 ,wherein, in the step (b), the forming the opening is performed by using photolithography.4. The manufacturing method of a semiconductor device according to claim 1 ,wherein, in the step (c), the Cu film, the Ni film, and the SnAg film are formed by electrolytic plating.5. The manufacturing method of a semiconductor device according to claim 1 ,wherein, in the step (d), the resist film is removed by ashing.6. The manufacturing method of a semiconductor device according to claim 1 ,wherein, in the step (e), the outer peripheries of the SnAg film is wet etched.7. A manufacturing method of a semiconductor device claim 1 , comprising the steps of:(a) applying a first resist film over a terminal pad formed over a main surface of a semiconductor substrate;(b) forming a first opening in the first resist film for exposing the terminal pad in the bottom thereof;(c) forming a Cu film and an Ni film in this order from below;(d) ...

Imaging apparatus, imaging display system, and display apparatus

An imaging apparatus includes: a substrate; and a plurality of device sections each including a photoelectric converter and disposed on the substrate to be spaced from one another and to collectively form a concave shape.

PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

A package structure includes a redistribution layer having a first surface, a second surface disposed opposite to the first surface, and at least one sidewall connected to the first surface and the second surface, at least one bonding electrode disposed on the first surface of the redistribution layer, and a mounting layer disposed on the second surface of the redistribution layer. The mounting layer includes a plurality of conductive pads that are spaced apart from each other. At least one of the conductive pads is exposed by the sidewall of the redistribution layer. 1. A package structure , comprising:a redistribution layer, wherein the redistribution layer comprises a first surface, a second surface disposed opposite to the first surface, and at least one sidewall connected to the first surface and the second surface;at least one bonding electrode disposed on the first surface of the redistribution layer; anda mounting layer disposed on the second surface of the redistribution layer, the mounting layer comprising a plurality of conductive pads that are spaced apart from each other,wherein at least one of the conductive pads is exposed by the sidewall of the redistribution layer.2. The package structure of claim 1 , further comprising an electronic device electrically connected to the bonding electrode.3. The package structure of claim 2 , further comprising a bonding material disposed between the electronic device and the bonding electrode.4. The package structure of claim 1 , further comprising a plurality of solder balls electrically connected to the conductive pads.5. The package structure of claim 1 , wherein the redistribution layer further comprises a plurality of dielectric layers and a plurality of patterned conductive layers claim 1 , the dielectric layers having a plurality of through holes claim 1 , and a portion of the patterned conductive layers being disposed in the through holes.6. A method of manufacturing a package structure claim 1 , comprising: ...

Semiconductor package and method of fabricating the same

Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package comprises a first redistribution substrate and a first semiconductor device on the first redistribution substrate. The first redistribution substrate includes a first dielectric layer that includes a first hole, an under-bump that includes a first bump part in the first hole and a second bump part that protrudes from the first bump part onto the first dielectric layer, an external connection terminal on a bottom surface of the first dielectric layer and connected to the under-bump through the first hole, a wetting layer between the external connection terminal and the under-bump, and a first barrier/seed layer between the under-bump and the first dielectric layer and between the under-bump and the wetting layer.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device includes a first carrier including a first pad, a second carrier including a second pad disposed opposite to the first pad, a joint coupled with and standing on the first pad, a joint encapsulating the post and bonding the first pad with the second pad, a first entire contact interface between the first pad and the joint, a second entire contact interface between the first pad and the post, and a third entire contact interface between the joint and the second pad. The first entire contact interface, the second entire contact interface and the third entire contact interface are flat surfaces. A distance between the first entire contact interface and the third entire contact interface is equal to a distance between the second entire contact interface and the third entire contact interface. The second entire contact interface is a continuous surface. 1. A semiconductor device , comprising:a silicon substrate;a carrier;a first pad on the silicon substrate;a second pad on the carrier;a post on a surface of the first pad, wherein the post consists of a metal or a metal alloy;a joint disposed between the silicon substrate and the carrier, contacted with the first pad and the second pad, and encapsulating the post;a first entire contact interface between the first pad and the joint;a second entire contact interface between the first pad and the post; anda third entire contact interface between the joint and the second pad,wherein an outer surface of the joint is concaved and curved towards the post, and a height of the post is greater than or equal to ⅓ of a height of the joint between the first pad and the second pad, the first entire contact interface, the second entire contact interface and the third entire contact interface are flat surfaces, wherein a distance between the first entire contact interface and the third entire contact interface is equal to a distance between the second entire contact interface and the third entire contact interface, ...

Flip chip backside mechanical die grounding techniques

A semiconductor device includes an integrated circuit attached to a chip carrier in a flip chip configuration. A substrate extends to a back surface of the integrated circuit, and an interconnect region extends to a front surface of the integrated circuit. A substrate bond pad is disposed at the front surface, and is electrically coupled through the interconnect region to the semiconductor material. The chip carrier includes a substrate lead at a front surface of the chip carrier. The substrate lead is electrically coupled to the substrate bond pad. An electrically conductive compression sheet is disposed on the back surface of the integrated circuit, with lower compression tips making electrical contact with the semiconductor material in the substrate. The electrically conductive compression sheet is electrically coupled to the substrate lead of the chip carrier by a back surface shunt disposed outside of the integrated circuit.

NON-POROUS COPPER TO COPPER INTERCONNECT

A semiconductor structure which includes a first semiconductor substrate having a first plurality of copper connectors; a second semiconductor substrate having a second plurality of copper connectors; and a joining structure joining the first plurality of copper connectors to the second plurality of copper connectors, the joining structure including a copper intermetallic mesh having pores filled with silver. There is also a method for joining two semiconductor substrates. 1. A method of joining two semiconductor substrates comprising:dispersing nano-sized spheres within a liquid, the nano-sized spheres comprising a tin/silver core coated with a copper coating;dispensing the liquid and nano-sized spheres onto at least one of the semiconductor substrates;evaporating the liquid so that the nano-sized spheres remain on the at least one of the semiconductor substrates; andheating to a temperature sufficient to result in a copper intermetallic mesh having pores filled with silver, the copper intermetallic mesh joining the two semiconductor substrates.2. The method of wherein the tin/silver core comprises 0.5 to 3 weight percent silver claim 1 , remainder tin.3. The method of wherein the tin/silver core comprises 0.1 to 3 weight percent silver claim 1 , 0.1 to 1.0 weight percent copper claim 1 , remainder tin.4. The method of wherein the tin/silver core has a diameter of 20 to 100 nanometers and the copper coating has a thickness of 5 to 10 nanometers.5. The method of wherein the nano-sized spheres further comprising a coating of nickel on the copper and a second coating of copper on the nickel.6. The method of wherein the tin/silver core has a diameter of 20 to 100 nanometers claim 5 , the copper coating has a thickness 5 to 10 nanometers claim 5 , the nickel coating has a thickness of 5 to 10 nanometers and the second coating of copper has a thickness of 5 to 10 nanometers.7. The method of wherein the copper intermetallic mesh further comprising an alloy of copper and ...

Semiconductor Device and Method of Forming a POP Device with Embedded Vertical Interconnect Units

A semiconductor device has a substrate. A plurality of conductive vias is formed through the substrate. A conductive layer is formed over the substrate. An insulating layer is formed over conductive layer. A portion of the substrate is removed to expose the conductive vias. A plurality of vertical interconnect structures is formed over the substrate. A first semiconductor die is disposed over the substrate. A height of the vertical interconnect structures is less than a height of the first semiconductor die. An encapsulant is deposited over the first semiconductor die and the vertical interconnect structures. A first portion of the encapsulant is removed from over the first semiconductor die while leaving a second portion of the encapsulant over the vertical interconnect structures. The second portion of the encapsulant is removed to expose the vertical interconnect structures. A second semiconductor die is disposed over the first semiconductor die. 1. A semiconductor device , comprising:a substrate including a conductive via formed through the substrate;a modular interconnect unit including a vertical interconnect structure disposed over the substrate;a first semiconductor die disposed over the substrate adjacent to the modular interconnect unit; andan encapsulant deposited around the first semiconductor die and over modular interconnect unit with an opening in the encapsulant extending to the modular interconnect unit.2. The semiconductor device of claim 1 , further including a second semiconductor die disposed over the first semiconductor die with a bump of the second semiconductor die within the opening of the encapsulant to contact the vertical interconnect structure.3. The semiconductor device of claim 1 , further including a first interconnect structure disposed between the substrate and modular interconnect unit.4. The semiconductor device of claim 3 , further including a second interconnect structure disposed between the first interconnect structure and ...

Hybrid bonding structures, semiconductor devices having the same, and methods of manufacturing the semiconductor devices

Provided are a hybrid bonding structure, a solder paste composition, a semiconductor device, and a method of manufacturing the semiconductor device. The hybrid bonding structure includes a solder ball and a solder paste bonded to the solder ball. The solder paste includes a transient liquid phase. The transient liquid phase includes a core and a shell on a surface of the core. A melting point of the shell may be lower than a melting point of the core. The core and the shell are configured to form an intermetallic compound in response to the transient liquid phase at least partially being at a temperature that is within a temperature range of about 20° C. to about 190° C.

WAFER LEVEL INTEGRATION INCLUDING DESIGN/CO-DESIGN, STRUCTURE PROCESS, EQUIPMENT STRESS MANAGEMENT AND THERMAL MANAGEMENT

A multi-layer wafer and method of manufacturing such wafer are provided. The method comprises creating under bump metallization (UMB) pads on each of the two heterogeneous wafers; applying a conductive means above the UMB pads on at least one of the two heterogeneous wafers; and low temperature bonding the two heterogeneous wafers to adhere the UMB pads together via the conductive means. At least one stress compensating polymer layer may be applied to at least one of two heterogeneous wafers. The multi-layer wafer comprises two heterogeneous wafers, each of the heterogeneous wafer having UMB pads and at least one of the heterogeneous wafers having a stress compensating polymer layer and a conductive means applied above the UMB pads on at least one of the two heterogeneous wafers. The two heterogeneous wafers low temperature bonded together to adhere the UMB pads together via the conductive means. 115-. (canceled)16. A multi-layer wafer comprising:two heterogeneous wafers, each of the heterogeneous wafer having under bump metallization pads and at least one of the heterogeneous wafers having one of a stress compensating or adhesive polymer layer; anda conductive means applied above the under bump metallization pads on at least one of the two heterogeneous wafers;the two heterogeneous wafers low temperature bonded together to adhere the under bump metallization pads together via the conductive means to form a multi-layer wafer pair.17. The multi-layer wafer of claim 16 , wherein the conductive means is one of solder balls claim 16 , conductive paste claim 16 , or solder topped copper pillars.18. The multi-layer wafer of claim 16 , wherein the conductive means is formed from one of In claim 16 , InSn claim 16 , InBi claim 16 , Sn alloys claim 16 , other high Sn solder alloys claim 16 , Pb claim 16 , PbSn claim 16 , other high lead alloys claim 16 , Cu claim 16 , Ni claim 16 , Au claim 16 , Ag claim 16 , Pt claim 16 , Pd claim 16 , or combinations therein that can be ...

Integrated circuit packaging system with routable grid array lead frame

System and method of manufacturing an integrated circuit packaging system using routable grid array lead frame. Method includes providing a lead frame having top metal connector and bottom contact, and treating the top metal connector with an additive, or the bottom contact with an additive, or both. Concomitant to the treatment process, insulation cover or bottom encapsulation can be formed about the top metal connector or the bottom contact with respective openings. Upon coupling the interconnects to the lead frame the interconnects do not exceed the metal contacts by more than about 60% due to the treatment process.

Semiconductor package

A semiconductor package includes a first package substrate, a first semiconductor chip on the first package substrate, a plurality of first chip connection units to connect the first package substrate to the first semiconductor chip, an interposer on the first semiconductor chip, the interposer having a width greater than a width of the first semiconductor chip in a direction parallel to an upper surface of the first package substrate, and an upper filling layer including a center portion and an outer portion, the center portion being between the first semiconductor chip and the interposer, and the outer portion surrounding the center portion and having a thickness greater than a thickness of the center portion in a direction perpendicular to the upper surface of the first package substrate.

Micro-transfer printing with volatile adhesive layer

A method of making a micro-transfer printed structure includes providing a destination substrate and a source substrate having one or more micro-transfer printable components. A layer of volatile adhesive is formed over the destination substrate and one or more components are micro-transfer printed from the source substrate onto the volatile adhesive layer at a non-evaporable temperature of the volatile adhesive layer. The volatile adhesive layer is then heated to an evaporation temperature to evaporate at least a portion of the volatile adhesive after micro-transfer printing. In certain embodiments, a micro-transfer printed structure includes a destination substrate having one or more metal contacts and one or more micro-transfer printable components having one or more component contacts disposed on the destination substrate with the metal contact aligned with the component contact. The metal contact can form an intermetallic bond with the component contact.

Chip-on-Wafer Structures and Methods for Forming the Same

A package component includes a substrate, wherein the substrate has a front surface and a back surface over the front surface. A through-via penetrates through the substrate. A conductive feature is disposed over the back surface of the substrate and electrically coupled to the through-via. A first dielectric pattern forms a ring covering edge portions of the conductive feature. An Under-Bump-Metallurgy (UBM) is disposed over and in contact with a center portion of the conductive feature. A polymer contacts a sidewall of the substrate. A second dielectric pattern is disposed over and aligned to the polymer. The first and the second dielectric patterns are formed of a same dielectric material, and are disposed at substantially a same level.

Systems, methods, and apparatuses for implementing a pad on solder mask (posm) semiconductor substrate package

In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing a Pad on Solder Mask (PoSM) semiconductor substrate package. For instance, in accordance with one embodiment, there is a substrate package having embodied therein a functional silicon die at a top layer of the substrate package; a solder resist layer beneath the functional silicon die of the substrate package; a plurality of die bumps at a bottom surface of the functional silicon die, the plurality of die bumps electrically interfacing the functional silicon die to a substrate through a plurality of solder balls at a top surface of the solder resist layer; each of the plurality of die bumps electrically interfaced to a nickel pad at least partially within the solder resist layer and beneath the solder balls; each of the plurality of die bumps electrically interfaced through the nickel pads to a conductive pad exposed at a bottom surface of the solder resist layer; and in which each of the conductive pads exposed at the bottom surface of the solder resist layer are electrically interfaced to an electrical trace at the substrate of the substrate package. Other related embodiments are disclosed.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

A semiconductor device includes a first substrate, a pad array, a conductive bump, a first via and a dielectric. The pad array, formed on a surface of the first substrate, includes a first type pad and a second type pad at a same level. The conductive bump connects one of the first type pad of the second type pad to a second substrate. The first via, connected to a conductive feature at a different level to the first type pad, is located within a projection area of the first type pad and directly contacts the first type pad. The second type pad is laterally connected with a conductive trace on the same level. The conductive trace is connected to a second via at a same level with the first via. The dielectric in the first substrate contacts the second type pad. The second type pad is floated on the dielectric. 1. A semiconductor device , comprising:a first substrate including a surface;a pad array on the surface of the first substrate, wherein the pad array comprises a first type pad and a second type pad at a same level;a conductive bump connecting one of the first type pad of the second type pad to a second substrate;a first via connected to a conductive feature at a different level to the first type pad, the first via being located within a projection area of the first type pad and directly contacting the first type pad, wherein the second type pad is laterally connected with a conductive trace on the same level, and the conductive trace is connected to a second via that is at a same level with the first via; anda dielectric in the first substrate, the dielectric contacting the second type pad, wherein the second type pad is floated on the dielectric.2. The semiconductor device of claim 1 , wherein the second via is connected to the conductive feature.3. The semiconductor device of claim 1 , wherein the second type pad is arranged symmetrically to a geometric center of the pad array.4. The semiconductor device of claim 1 , wherein the first substrate is a printed ...

WAFER LEVEL INTEGRATION INCLUDING DESIGN/CO-DESIGN, STRUCTURE PROCESS, EQUIPMENT STRESS MANAGEMENT AND THERMAL MANAGEMENT

A method of manufacturing a multi-layer wafer is provided. The method comprises creating under bump metallization (UMB) pads on each of the two heterogeneous wafers; applying a conductive means above the UMB pads on at least one of the two heterogeneous wafers; and low temperature bonding the two heterogeneous wafers to adhere the UMB pads together via the conductive means. At least one stress compensating polymer layer may be applied to at least one of two heterogeneous wafers. The multi-layer wafer comprises two heterogeneous wafers, each of the heterogeneous wafer having UMB pads and at least one of the heterogeneous wafers having a stress compensating polymer layer and a conductive means applied above the UMB pads on at least one of the two heterogeneous wafers. The two heterogeneous wafers low temperature bonded together to adhere the UMB pads together via the conductive means. 1. A method of manufacturing a multi-layer wafer comprising:creating under bump metallization pads on each of the two heterogeneous wafers;applying a conductive means above the under bump metallization pads on at least one of the two heterogeneous wafers; andlow temperature bonding the two heterogeneous wafers to adhere the under bump metallization pads together via the conductive means to form a multi-layer wafer pair.2. The method of claim 1 , further comprising:applying at least one stress compensating polymer and/or adhesive layer to at least one of two heterogeneous wafers3. The method of claim 1 , wherein each of the two heterogeneous wafers are formed from at least one of: complementary metal-oxide semiconductor (CMOS) and GaN on Si claim 1 , CMOS and glass claim 1 , CMOS and sapphire claim 1 , CMOS and SiC on Si claim 1 , CMOS and diamond on Si claim 1 , or CMOS and sapphire on Si.4. The method of claim 1 , wherein the stress compensating polymer layer is formed on the at least one heterogeneous wafer by:applying a liquid polymer to the at least one of the two heterogeneous ...

Semiconductor device and method of manufacturing the same

A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises a substrate including a plurality of conductive traces and a semiconductor chip. The semiconductor chip comprises a surface facing the plurality of conductive traces and a plurality of conductive pads on the surface and correspondingly electrically connected with the plurality of conductive traces through a plurality of conductive bumps. A height of each of the plurality of conductive bumps is determined by a minimum distance between the plurality of conductive pads and the corresponding conductive traces thereof.

SOLDER IN CAVITY INTERCONNECTION STRUCTURES

The present disclosure relates to the field of fabricating microelectronic packages, wherein cavities are formed in a dielectric layer deposited on a first substrate to maintain separation between soldered interconnections. In one embodiment, the cavities may have sloped sidewalls. In another embodiment, a solder paste may be deposited in the cavities and upon heating solder structures may be formed. In other embodiments, the solder structures may be placed in the cavities or may be formed on a second substrate to which the first substrate may be connected. In still other embodiments, solder structures may be formed on both the first substrate and a second substrate. The solder structures may be used to form solder interconnects by contact and reflow with either contact lands or solder structures on a second substrate. 1. A microelectronic device , comprising:a first substrate having a plurality of bond pads proximate a first surface of the first substrate;a first dielectric layer disposed over the first substrate bond pads and the first substrate contact surface having a plurality of cavities extending therethrough to corresponding bond pads;a second substrate having a plurality of contact lands proximate a contact surface of the second substrate;a second dielectric layer on the second substrate surface adjacent the plurality of second substrate contact lands having a plurality of cavities extending therethrough to corresponding contact lands;a solder interconnection between the first substrate bond pads and the second substrate contact lands;an underfill material between the first dielectric layer and the second dielectric layer, wherein a portion of the underfill material extends into the plurality of cavities extending through the first dielectric layer and into the plurality of cavities extending through the second dielectric layer.2. The microelectronic device of claim 1 , wherein the plurality of cavities extending through the first dielectric layer each ...

Semiconductor Package and Method

In an embodiment, a device includes: a back-side redistribution structure including: a metallization pattern on a first dielectric layer; and a second dielectric layer on the metallization pattern; a through via extending through the first dielectric layer to contact the metallization pattern; an integrated circuit die adjacent the through via on the first dielectric layer; a molding compound on the first dielectric layer, the molding compound encapsulating the through via and the integrated circuit die; a conductive connector extending through the second dielectric layer to contact the metallization pattern, the conductive connector being electrically connected to the through via; and an intermetallic compound at the interface of the conductive connector and the metallization pattern, the intermetallic compound extending only partially into the metallization pattern.

No clean flux composition and methods for use thereof

A flux formulation includes an activator and a protic solvent. The activator may be glutaric acid, levulinic acid, 2-ketobutyric acid, 2-oxovaleric acid, or mixtures thereof. Suitable protic solvents include alkanediol, alkoxy propanol and alkoxy ethanol. The flux formulation may be a no-clean flux formulation that may be used in the soldering of electronic circuit board assemblies, for example, in conjunction with a support fixture having a planar back surface that minimizes vibrations during processing that might otherwise cause misalignment between a chip and a substrate prior to solder reflow.

Semiconductor package and method of manufacturing the same

A semiconductor package includes a substrate, a plurality of semiconductor devices stacked on the substrate, a plurality of underfill fillets disposed between the plurality of semiconductor devices and between the substrate and the plurality of semiconductor devices, and molding resin surrounding the plurality of semiconductor devices. At least one of the underfill fillets is exposed from side surfaces of the molding resin.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A method of manufacturing a semiconductor device includes providing a carrier, disposing a first pad on the carrier, forming a post on the first pad, and disposing a joint adjacent to the post and the first pad to form a first entire contact interface between the first pad and the joint and a second entire contact interface between the first pad and the post. The first entire contact interface and the second entire contact interface are flat surfaces. 1. A method of manufacturing a semiconductor device , comprising:providing a first carrier;disposing a first pad on the first carrier;forming a post on the first pad; anddisposing a joint adjacent to the post and the first pad to form a first entire contact interface between the first pad and the joint and a second entire contact interface between the first pad and the post, wherein the first entire contact interface and the second entire contact\ interface are flat surfaces.2. The method of manufacturing the semiconductor device of claim 1 , wherein the disposing of the joint is performed by pasting a solder over the post and the first pad through a stencil.3. The method of manufacturing the semiconductor device of claim 1 , further comprising providing a second carrier and disposing a second pad on the second carrier.4. The method of manufacturing the semiconductor device of claim 3 , wherein a height of the post is greater than or equal to ⅓ of a distance between the first pad and the second pad.5. The method of manufacturing the semiconductor device of claim 3 , further comprising disposing the joint between the first pad and the second pad to bond the first pad with the second pad and to form a third entire contact interface between the joint and the second pad claim 3 , wherein the third entire contact interface is a flat surface.6. The method of manufacturing the semiconductor device of claim 5 , further comprising disposing a pre-soldering bump on the second pad prior to disposing the joint between the first ...

Semiconductor device and method of manufacturing the same

An imaging device includes a first semiconductor element including at least one bump pad that has a concave shape. The at least one bump pad includes a first metal layer and a second metal layer on the first metal layer. The imaging device includes a second semiconductor element including at least one electrode. The imaging device includes a microbump electrically connecting the at least one bump pad to the at least one electrode. The microbump includes a diffused portion of the second metal layer, and first semiconductor element or the second semiconductor element includes a pixel unit.

SEMICONDUCTOR DEVICE AND METHOD

Disclosed herein is a semiconductor device that includes a semiconductor die and a substrate including a first surface and a second surface. The substrate includes a conductive circuit and an insulative material over the conductive circuit. The semiconductor die is attached to the second surface. The semiconductor device further includes a metal barrier layer plated onto a functional copper layer etched to form the conductive circuit. The conductive circuit has a thickness of less than or equal to 3 μm. Further disclosed is a method of making a semiconductor device. 1. A semiconductor device comprising:a semiconductor die;a substrate including a first surface and a second surface, the substrate comprising a conductive circuit and an insulative material over the conductive circuit, wherein the semiconductor die is attached to the second surface; anda metal barrier layer plated onto a functional copper layer etched to form the conductive circuit, wherein the conductive circuit has a thickness of less than or equal to 3 μm.2. The semiconductor device of claim 1 , wherein the conductive circuit includes an etched layer of conductive foil that is located on the first surface of the substrate.3. The semiconductor device of claim 1 , wherein the metal barrier layer has a thickness of less than or equal to 2 μm.4. The semiconductor device of claim 1 , wherein metal barrier layer is made of nickel.5. The semiconductor device of claim 1 , wherein the substrate is formed using a build-up process.6. The semiconductor device of claim 1 , wherein the substrate is formed using a subtractive process.7. The semiconductor device of claim 1 , wherein the conductive circuit has a thickness of less than or equal to 2 μm.8. The semiconductor device of claim 1 , wherein the substrate further includes an etched foil layer claim 1 , and wherein the substrate further includes a nickel layer etch stop barrier between the conductive circuit and the etched foil layer.9. The semiconductor device ...

Electrode connection structure and electrode connection method

An electrode connection structure includes: a first electrode of an electrical circuit; and a second electrode of the electrical circuit that is electrically connected to the first electrode. The first and second electrodes are oppositely disposed in direct or indirect contact with each other. A plated lamination is substantially uniformly formed by plating process from a surface of a contact region and opposed surfaces of the first and second electrodes. A void near the surface of the contact region is filled by formation of the plated lamination. Portions of the plated lamination formed from the opposed surfaces of the first and second electrodes in a region other than the contact region are not joined together.

Interconnect Structures and Methods of Forming Same

Embodiments of the present disclosure include interconnect structures and methods of forming interconnect structures. An embodiment is an interconnect structure including a post-passivation interconnect (PPI) over a first substrate and a conductive connector on the PPI. The interconnect structure further includes a molding compound on a top surface of the PPI and surrounding a portion of the conductive connector, a top surface of the molding compound adjoining the conductive connector at an angle from about 10 degrees to about 60 degrees relative to a plane parallel with a major surface of the first substrate, the conductive connector having a first width at the adjoining top surface of the molding compound, and a second substrate over the conductive connector, the second substrate being mounted to the conductive connector. 1. A method comprising:forming a contact pad on a top surface of a first substrate;depositing a first passivation layer on the top surface of the first substrate, the first passivation layer contacting a first portion of a top surface of the contact pad;depositing a second passivation layer on the first passivation layer, the second passivation layer contacting a second portion of the top surface of the contact pad;forming a post-passivation interconnect (PPI) extending along a top surface of the second passivation layer and extending through the second passivation layer to contact the top surface of the contact pad;forming a connector on the top surface of the PPI;forming a molding compound on the top surface of the PPI and around the connector, a topmost surface of the molding compound being below an upper portion of the connector;after the forming the molding compound, shaping the molding compound such that the molding compound covers a middle portion of the connector, the upper portion of the connector extending above the molding compound; andbonding a bond pad of a second substrate to the connector, the bond pad having a second width, the ...

Interconnect Structures and Methods of Forming Same

Embodiments of the present disclosure include interconnect structures and methods of forming interconnect structures. An embodiment is an interconnect structure including a post-passivation interconnect (PPI) over a first substrate and a conductive connector on the PPI. The interconnect structure further includes a molding compound on a top surface of the PPI and surrounding a portion of the conductive connector, a top surface of the molding compound adjoining the conductive connector at an angle from about 10 degrees to about 60 degrees relative to a plane parallel with a major surface of the first substrate, the conductive connector having a first width at the adjoining top surface of the molding compound, and a second substrate over the conductive connector, the second substrate being mounted to the conductive connector. 18.-. (canceled)9. An interconnect structure comprising:a contact pad on a surface of a first substrate;a post-passivation interconnect (PPI) contacting a surface of the contact pad;a first passivation layer on a surface of the PPI;a connector on the surface of the PPI, the first passivation layer directly adjoining a lower portion of the connector;a molding compound disposed on a surface of the first passivation layer, the molding compound covering a middle portion of the connector and exposing another portion of the connector; anda bond pad on a surface of a second substrate, the bond pad being bonded to the connector.10. The interconnect structure of further comprising:a second passivation layer on the contact pad and the surface of the first substrate; anda third passivation layer on the second passivation layer and the contact pad, the PPI extending through the second passivation layer and the third passivation layer, the first passivation layer being disposed on the third passivation layer.11. The interconnect structure of claim 10 , wherein the molding compound has a concave top surface adjoining the connector claim 10 , the connector ...

RELEASABLE CARRIER METHOD

A method for making a semiconductor device includes providing a releasable carrier attached to a conductive layer, patterning a conductive circuit on a surface of the conductive layer, applying an insulative material at least partially covering the conductive circuit, releasing the releasable carrier from the conductive layer, and facilitating the releasing with an activating source. A method of fabricating a releasable carrier includes providing a supporting carrier, attaching a releasable tape to the supporting carrier, providing a first conductive layer and a second conductive layer attached to the first conductive layer, and attaching the first conductive layer to the releasable tape, where the releasable tape is configured to release the supporting carrier from the first conductive layer after being exposed to an activating source. 1. A method for making a semiconductor device comprising:providing a releasable carrier attached to a conductive layer;patterning a conductive circuit on a surface of the conductive layer;applying an insulative material at least partially covering the conductive circuit;releasing the releasable carrier from the conductive layer; andfacilitating the releasing with an activating source.2. The method of claim 1 , the conductive layer further including a carrier conductive layer and a thin conductive layer claim 1 , the method further comprising:providing a releasable tape between the releasable carrier and the conductive layer;releasing the carrier conductive layer from the releasable tape;releasing the thin conductive layer from the carrier conductive layer; andreleasing the releasable carrier from the releasable tape.3. The method of claim 1 , wherein the activating source does not make physical contact with the releasable carrier.4. The method of claim 1 , wherein the activating source is a UV light source generating irradiation energy between 20 mW/cmand 40 mW/cm.5. The method of claim 1 , wherein the activating source is a heat ...

Semiconductor package

A semiconductor package includes a redistribution structure including an insulating layer having an upper surface and a lower surface, a redistribution pad and a redistribution pattern on the lower surface of the insulating layer and electrically connected to each other, and a passivation layer on the lower surface of the insulating layer and having an opening exposing at least a portion of the redistribution pad; a semiconductor chip on the redistribution structure and including a connection pad electrically connected to the redistribution pad; an encapsulant on the redistribution structure and encapsulating the semiconductor chip; and a connection bump and a dummy bump on the passivation layer, wherein the redistribution pattern has a width narrower than a width of the redistribution pad, the connection bump vertically overlaps the redistribution pad, and the dummy bump vertically overlaps the redistribution pattern.

Methods for Making Multi-Die Package With Bridge Layer

A device is provided. The device includes a bridge layer over a first substrate. A first connector electrically connecting the bridge layer to the first substrate. A first die is coupled to the bridge layer and the first substrate, and a second die is coupled to the bridge layer. 1. A device , comprising:a first substrate comprising a plurality of first contacts extending along a first surface of the first substrate;a bridge overlying the first substrate, the bridge comprising a plurality of second contacts extending along a second surface of the bridge, second contacts of the plurality of second contacts being positioned along one or more edges of the second surface of the bridge, and the second surface of the bridge facing away from the first surface of the first substrate;a plurality of electrical connectors, wherein the plurality of electrical connectors electrically connect the plurality of second contacts to the plurality of first contacts, and each of the plurality of electrical connectors extends along a sidewall of the bridge;a first die overlying the bridge, wherein a perimeter of the first die is within a perimeter of the bridge in a plan view; anda second die overlying the bridge, wherein the second die partially overlaps the bridge and extends beyond the bridge in the plan view.2. The device according to claim 1 , wherein the first die comprises a plurality of blocks claim 1 , and each of the plurality of blocks comprises a respective plurality of third contacts.3. The device according to claim 2 , wherein the second die is connected to the respective plurality of third contacts of each of the plurality of blocks of the first die by a plurality of redistribution layers of the bridge.4. The device according to claim 1 , wherein each of the plurality of electrical connectors is a conductive bump that contacts the sidewall of the bridge.5. The device according to claim 4 , wherein a height of the plurality of electrical connectors over the first substrate ...

Package structure with structure reinforcing element and manufacturing method thereof

A package structure includes a redistribution structure, a chip, one or more structural reinforcing elements, and a protective layer. The redistribution structure includes a first circuit layer and a second circuit layer disposed over the first circuit layer. The first circuit layer is electrically connected to the second circuit layer. The chip is disposed over the redistribution structure and electrically connected to the second circuit layer. The one or more structural reinforcing elements are disposed over the redistribution structure. The structural reinforcing element has a Young's modulus in a range of 30 to 200 GPa. The protective layer overlays the chip and a sidewall of the structural reinforcing element.

BRIDGE INTERCONNECTION WITH LAYERED INTERCONNECT STRUCTURES

Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed. 1. An IC assembly , comprising:a package substrate, the package substrate comprising a dielectric material;a bridge in the package substrate, the bridge comprising silicon, wherein the dielectric material of the package substrate is over and in contact with the bridge;a first joint over and electrically coupled to the bridge, the first joint in the dielectric material and extending above the dielectric material, and the first joint comprising copper;a first layer on the first joint, the first layer comprising nickel;a second joint over and electrically coupled to the bridge, the second joint in the dielectric material and extending above the dielectric material, and the second joint comprising copper;a second layer on the second joint, the second layer comprising nickel;a first interconnect structure in the package substrate, the first interconnect structure laterally spaced from a first side of the bridge, and the first interconnect in the dielectric material;a second interconnect structure in the package substrate, the second interconnect structure laterally spaced from a second side of the bridge, and the second ...

Semiconductor device

There is a need to improve reliability of the semiconductor device. A semiconductor device includes a printed circuit board and a semiconductor chip mounted over the printed circuit board. The semiconductor chip includes a pad, an insulation film including an opening to expose part of the pad, and a pillar electrode formed over the pad exposed from the opening. The printed circuit board includes a terminal and a resist layer including an opening to expose part of the terminal. The pillar electrode of the semiconductor chip and the terminal of the printed circuit board are coupled via a solder layer. Thickness h 1 of the pillar electrode is measured from the upper surface of the insulation film. Thickness h 2 of the solder layer is measured from the upper surface of the resist layer. Thickness h 1 is greater than or equal to a half of thickness h 2 and is smaller than or equal to thickness h 2 .

Semiconductor Device and Method of Forming Ultra Thin Multi-Die Face-to-Face WLCSP

A semiconductor device has a first semiconductor die stacked over a second semiconductor die which is mounted to a temporary carrier. A plurality of bumps is formed over an active surface of the first semiconductor die around a perimeter of the second semiconductor die. An encapsulant is deposited over the first and second semiconductor die and carrier. A plurality of conductive vias is formed through the encapsulant around the first and second semiconductor die. A portion of the encapsulant and a portion of a back surface of the first and second semiconductor die is removed. An interconnect structure is formed over the encapsulant and the back surface of the first or second semiconductor die. The interconnect structure is electrically connected to the conductive vias. The carrier is removed. A heat sink or shielding layer can be formed over the encapsulant and first semiconductor die. 1. A method of making a semiconductor device , comprising:providing a first semiconductor die;forming a plurality of bumps over an active surface of the first semiconductor die;disposing a second semiconductor die over the first semiconductor die between the bumps with an active surface of the second semiconductor die oriented toward the active surface of the first semiconductor die;depositing an encapsulant over the first semiconductor die, second semiconductor die, and bumps;forming a conductive via through the encapsulant around the first semiconductor die and second semiconductor die; andforming a first interconnect structure over a first surface of the encapsulant.2. The method of claim 1 , further including removing a portion of the encapsulant to the bumps.3. The method of claim 1 , further including removing a portion of the encapsulant to the conductive via.4. The method of claim 1 , further including forming a second interconnect structure over a second surface of the encapsulant opposite the first surface of the encapsulant.5. The method of claim 1 , further including ...

Lead frame

A lead frame includes, as an outermost plating layer, a roughened silver plating layer having acicular projections and covering the entire surface of a lead frame substrate made of a copper-based material. The roughened silver plating layer has a crystal structure in which the crystal direction <101> occupies a largest proportion among the crystal directions <001>, <111>, and <101>. The lead frame can be manufactured with improved productivity owing to reduction in cost and operation time, and achieves remarkably high adhesion to sealing resin while keeping the total thickness of plating layers including the silver plating layer to be thin.

Semiconductor Device and Method of Forming Conductive Vias to Have Enhanced Contact to Shielding Layer

A semiconductor device has a substrate with a plurality of conductive vias formed through the substrate in an offset pattern. An electrical component is disposed in a die attach area over a first surface of the substrate. The conductive vias are formed around the die attach area of the substrate. A first conductive layer is formed over the first surface of the substrate, and a second conductive layer is formed over the second surface. An encapsulant is deposited over the substrate and electrical component. The substrate is singulated through the conductive vias. A first conductive via has a greater exposed surface area than a second conductive via. A shielding layer is formed over the electrical component and in contact with a side surface of the conductive vias. The shielding layer may extend over a second surface of substrate opposite the first surface of the substrate.

Dielectric and metallic nanowire bond layers

In some examples, an electronic device comprises a first component having a surface, a second component having a surface, and a bond layer positioned between the surfaces of the first and second components to couple the first and second components to each other. The bond layer includes a set of metallic nanowires and a dielectric portion. The dielectric portion comprises a polymer matrix and dielectric nanoparticles.

Junction structure

A bonding structure is a bonding structure which bonds a light emitting element and a substrate and includes a first electrode formed on the light emitting element, a second electrode formed on the substrate, and a bonding layer which bonds the first electrode and the second electrode, and the bonding layer contains a first bonding metal component and a second bonding metal component different from the first bonding metal component.

Interconnect Crack Arrestor Structure and Methods

A system and method for preventing cracks is provided. An embodiment comprises placing crack stoppers into a connection between a semiconductor die and a substrate. The crack stoppers may be in the shape of hollow or solid cylinders and may be placed so as to prevent any cracks from propagating through the crack stoppers. 1. A semiconductor device comprising:a conductive pad on a substrate; anda first crack stopper extending from the conductive pad, the first crack stopper comprising a hollow tube, the first crack stopper located along an exterior region of the conductive pad; anda first conductive material surrounding the first crack stopper.2. The semiconductor device of claim 1 , wherein the wire comprises a cylindrical shape.3. The semiconductor device of claim 1 , wherein the conductive region is an underbump metallization.4. The semiconductor device of claim 1 , wherein the first crack stopper has an outer diameter between 15 microns and 60 microns.5. The semiconductor device of claim 1 , wherein the first crack stopper has an inner diameter between 5 microns and 20 microns.6. The semiconductor device of claim 1 , wherein the first crack stopper comprises one or more additional hollow tubes claim 1 , wherein each of the hollow tubes of the first crack stopper are spaced equidistant from each other along the exterior region of the conductive pad.7. The semiconductor device of claim 1 , wherein the first crack stopper comprises an additional hollow tube claim 1 , the additional hollow tube disposed at a center of the conductive pad.8. The semiconductor device of claim 1 , wherein the first conductive material is coupled to a second conductive pad on a second substrate.9. The semiconductor device of claim 8 , wherein the first conductive material is electrically coupled to a second crack stopper disposed on the second conductive pad.10. A semiconductor device comprising:a conductive pad on a substrate; anda first crack stopper extending from the conductive pad, ...

Bonding with Pre-Deoxide Process and Apparatus for Performing the Same

A method includes picking up a first package component, removing an oxide layer on an electrical connector of the first package component, placing the first package component on a second package component after the oxide layer is removed, and bonding the first package component to the second package component.

Bridge interconnection with layered interconnect structures

Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.

Reversed build-up substrate for 2.5d

A method of making an assembly can include forming a circuit structure defining front and rear surfaces, and forming a substrate onto the rear surface. The forming of the circuit structure can include forming a first dielectric layer coupled to the carrier. The first dielectric layer can include front contacts configured for joining with contacts of one or more microelectronic elements, and first traces. The forming of the circuit structure can include forming rear conductive elements at the rear surface coupled with the front contacts through the first traces. The forming of the substrate can include forming a dielectric element directly on the rear surface. The dielectric element can have first conductive elements facing the rear conductive elements and joined thereto. The dielectric element can include second traces coupled with the first conductive elements. The forming of the substrate can include forming terminals at a surface of the substrate.

Interconnect Structures and Methods of Forming Same

Embodiments of the present disclosure include interconnect structures and methods of forming interconnect structures. An embodiment is an interconnect structure including a post-passivation interconnect (PPI) over a first substrate and a conductive connector on the PPI. The interconnect structure further includes a molding compound on a top surface of the PPI and surrounding a portion of the conductive connector, a top surface of the molding compound adjoining the conductive connector at an angle from about 10 degrees to about 60 degrees relative to a plane parallel with a major surface of the first substrate, the conductive connector having a first width at the adjoining top surface of the molding compound, and a second substrate over the conductive connector, the second substrate being mounted to the conductive connector. 1. A device comprising:a contact pad on a substrate;a first dielectric layer on the contact pad;a post-passivation interconnect (PPI) extending through the first dielectric layer, the PPI connected to the contact pad;a second dielectric layer on the PPI and the first dielectric layer;a molding compound on the second dielectric layer, the molding compound having a concave top surface; anda conductive connector extending through the molding compound and the second dielectric layer, the conductive connector connected to the PPI, the conductive connector adjoining the concave top surface of the molding compound.2. The device of further comprising:a third dielectric layer between the first dielectric layer and each of the contact pad and the substrate, the PPI extending through the third dielectric layer.3. The device of claim 2 , wherein the first dielectric layer contacts a first portion of the contact pad and the third dielectric layer contacts a second portion of the contact pad.4. The device of claim 2 , wherein the first dielectric layer has a first thickness of between 2μm and 30μm claim 2 , the second dielectric layer has a second thickness of ...

Induction heating for underfill removal and chip rework

Underfill materials and methods for removing an underfill material from beneath a chip in relation to removal of the chip from a substrate. The underfill material may a plurality of particles dispersed in a bulk matrix. The material constituting the particles may be capable of generating heat energy when exposed to a time-varying magnetic field. The bulk matrix of the underfill material between the chip and a substrate may be heated with heat energy transferred from the particles. While heated, the underfill material is removed. The heating of the underfill material may also be used to heat solder bumps connecting the chip with the substrate so that the solder bumps are liquefied.

Die Features for Self-Alignment During Die Bonding

A semiconductor device assembly that includes a substrate having a first side and a second side, the first side having at least one dummy pad and at least one electrical pad. The semiconductor device assembly includes a first semiconductor device having a first side and a second side and at least one electrical pillar extending from the second side. The electrical pillar is connected to the electrical pad via solder to form an electrical interconnect. The semiconductor device assembly includes at least one dummy pillar extending from the second side of the first semiconductor device and a liquid positioned between an end of the dummy pillar and the dummy pad. The surface tension of the liquid pulls the dummy pillar towards the dummy pad. The surface tension may reduce or minimize a warpage of the semiconductor device assembly and/or align the dummy pillar and the dummy pad.

SUBSTRATE, ELECTRONIC SUBSTRATE, AND METHOD FOR PRODUCING ELECTRONIC SUBSTRATE

A substrate is capable of effectively reinforcing a connecting portion between an electronic component and the substrate. The substrate is a substrate on which a first electronic component having a plurality of bumps is to be mounted, and includes a base portion including an insulator and having, on the upper face thereof, at least one groove portion configured to store a tip portion of at least one of the bumps, and includes an electrode formed on at least the bottom face of the groove portion. 1. A substrate on which a first electronic component having a plurality of bumps is to be mounted , the substrate comprising:a base portion including an insulator and having, on an upper face thereof, at least one groove portion configured to receive a tip portion of at least one of the bumps of the first electronic component; andan electrode on at least a bottom face of the groove portion.2. The substrate according to claim 1 , wherein the electrode is on the bottom face and a side face of the groove portion.3. The electronic substrate according to claim 1 , wherein a respective groove portion corresponds to each bump.4. The substrate according to claim 1 , wherein a plurality of the groove portions are on the upper face in a grid pattern.5. The substrate according to claim 4 , wherein the groove portions include first groove portions in four corner areas on the base portion and include second groove portions having a smaller diameter than that of the first groove portions and are located in an area other than the four corner areas on the base portion.6. The substrate according to claim 1 , wherein:the plurality of groove portions are located in an outer peripheral area on the base portion,an upper face of an inside area from the outer peripheral area with the groove portions is a recessed portion that is recessed from an upper face of the outer peripheral area, and an upper face of the recessed portion has at least electrode configured to be connected to at least one of ...

Electrode connection method and electrode connection structure

Provided is an electrode connection method and the like which make it possible to connect tightly without leaving a gap, by connecting by plating while electrodes in an electrical circuit contact one another in a dot or linear pattern. Contact is made directly or indirectly in at least part of the interval between a plurality of electrically connected electrodes in an electrical circuit, and the interval between electrodes is plated and connected while a plating fluid flows around the periphery of the contact section. In addition, the contact section maintains a linear or dot pattern. Furthermore, nickel or a nickel alloy or copper or a copper alloy is used as the material for performing the plating, while the material for the surface of the electrodes to be connected is nickel or a nickel alloy, copper or a copper alloy, gold or a gold alloy, silver or a silver alloy, or palladium or a palladium alloy.

Light emitting device package and lighting apparatus having the same

본 발명의 일 실시 형태에 따른 발광소자 패키지는, 전극 패턴을 갖는 몸체부; 및 상기 몸체부 상에 장착되는 일면에 솔더 패드를 가져 상기 전극 패턴과 접속되는 복수의 발광소자;를 포함할 수 있다. 상기 전극 패턴은 상기 복수의 발광소자가 놓이는 실장 영역을 정의하는 복수의 셀을 가지며, 상기 셀은 상기 솔더 패드와 대응되는 형상의 전극 패드를 가질 수 있다. A light emitting device package according to an embodiment of the present invention includes a body portion having an electrode pattern; and a plurality of light emitting devices having a solder pad on one surface mounted on the body portion and connected to the electrode pattern. The electrode pattern may have a plurality of cells defining a mounting region in which the plurality of light emitting devices are placed, and the cells may have electrode pads having a shape corresponding to the solder pads.

반도체 패키지

본 발명의 일 실시예는, 절연층, 절연층의 하면 상에 배치되며 서로 전기적으로 연결된 재배선 패드와 재배선 패턴, 및 재배선 패드의 적어도 일부를 노출시키는 개구부를 갖는 패시베이션층을 포함하는 재배선 구조체, 상기 재배선 패드와 전기적으로 연결된 접속 패드를 포함하는 반도체 칩, 상기 반도체 칩을 봉합하는 봉합재 및 상기 패시베이션층 상에 배치되는 연결 범프와 더미 범프를 포함하며, 상기 재배선 패턴은 상기 재배선 패드의 폭 보다 작은 폭을 갖고, 상기 연결 범프는 상기 재배선 패드와 수직적으로 중첩되고, 상기 더미 범프는 상기 재배선 패턴과 수직적으로 중첩되는 반도체 패키지를 제공한다.

Package on package devices and methods of packaging semiconductor dies

패키지 온 패키지(package on package; PoP) 소자와, 반도체 다이를 패키징하는 방법이 개시된다. 일 실시예에서, PoP 소자는 제1 패키징된 다이와, 이러한 제1 패키징된 다이에 연결된 제2 패키징된 다이를 포함한다. 금속 기둥은 제1 패키징된 다이에 연결된다. 금속 기둥은 제1 패키징된 다이에 근접한 제1 부분과, 제1 부분 위에 배치된 제2 부분을 갖는다. 금속 기둥 각각은 제2 패키징된 다이에 근접한 솔더 조인트(solder joint)에 연결된다. A package on package (PoP) device and a method of packaging a semiconductor die are disclosed. In one embodiment, the PoP device includes a first packaged die and a second packaged die coupled to the first packaged die. The metal pillar is connected to the first packaged die. The metal pillar has a first portion proximate the first packaged die and a second portion disposed over the first portion. Each of the metal posts is connected to a solder joint proximate to the second packaged die.

반도체 패키지 제조 방법 및 이를 이용한 반도체 패키지

본 발명은 반도체 제조 공정 중 발생하는 뒤틀림이나 휨 현상(warpage)을 방지할 수 있는 반도체 패키지 제조 방법 및 이를 이용한 반도체 패키지를 제공한다. 이를 위해 본 발명의 일 실시예에 따른 반도체 패키지 제조 방법은 적어도 2개의 반도체 다이를 준비하는 단계(A), 인터포저를 준비하는 단계(B), 상기 적어도 2개의 반도체 다이를 상기 인터포저 상에 본딩하는 단계(C), 상기 인터포저와 적어도 2개의 반도체 다이 사이로 언더필을 충진하는 단계(D) 및 상기 적어도 2개의 반도체 다이 사이의 언더필의 적어도 일부를 제거하는 단계(E)를 포함한다.

Semiconductor device and method of forming fine pitch rdl over semiconductor die in fan-out package

本发明涉及在半导体管芯上形成细节距的RDL的半导体器件和方法。半导体器件具有包括多个导电迹线的第一导电层。第一导电层形成在衬底上。利用窄节距形成导电迹线。在第一导电层上放置第一半导体管芯和第二半导体管芯。在第一和第二半导体管芯上沉积第一密封剂。移除衬底。在第一密封剂上沉积第二密封剂。在第一导电层和第二密封剂上形成堆积互连结构。堆积互连结构包括第二导电层。在第一密封剂中放置第一无源器件。在第二密封剂中放置第二无源器件。在第二密封剂中放置垂直互连单元。第三导电层形成在第二密封剂上并且经由垂直互连单元电气连接到堆积互连结构。

Multi-layer ceramic circuit board, fabrication method of the same and electric device module

본 발명은 복수의 세라믹층이 적층되어 이루어지며 상기 복수의 세라믹층 각각에 형성된 도전성 비아와 도전성 패턴으로 이루어진 층간회로를 갖는 세라믹 본체와, 상기 복수의 세라믹층 표면에 인접한 적어도 하나의 표층 세라믹층에 형성되며 상부를 향해 경사진 측벽을 갖는 범프 수용부와, 상기 범프 수용부의 경사진 측벽과 저면에 형성되며 상기 층간회로에 연결된 본딩패드를 포함하는 다층 세라믹 회로 기판을 제공한다. According to an aspect of the present invention, there is provided a ceramic body having a plurality of ceramic layers stacked therein and having an interlayer circuit including conductive vias and conductive patterns formed in each of the plurality of ceramic layers, and at least one surface layer ceramic layer adjacent to the surfaces of the plurality of ceramic layers. Provided is a multi-layer ceramic circuit board including a bump receiving portion having a sidewall inclined toward the top, and a bonding pad formed on the inclined sidewall and bottom of the bump receiving portion and connected to the interlayer circuit.

Semiconductor device and manufacturing method thereof

반도체 디바이스는, 반도체 기판, 반도체 기판 상의 도전성 패드 및 도전성 패드 위에 있는 도전체를 포함한다. 반도체 디바이스는 반도체 기판 위에 배치되고 도전체를 둘러싸는 폴리머 재료를 더 갖는다. 반도체 디바이스는 도전체와 폴리머 재료 사이에 전기 도전층도 또한 포함한다. 반도체 디바이스에서, 전기 도전층과 폴리머 재료 간의 접착 강도는 폴리머 재료와 도전체 간의 접착 강도보다 크다.

Multiple die packaging interposer structure and method

다중 다이 인터포저 구조를 제공하기 위한 시스템 및 방법이 개시된다. 일 실시예는 몰딩된 인터포저의 복수의 인터포저 스터드들을 포함하고, 재지향 층은 인터포저의 각각의 측 상에 있다. 부가적으로, 인터포저 스터드들은 우선 인터포저를 몰딩하기 이전에 와이어 본드 용접 또는 솔더링에 의해 전도성 장착 플레이트에 부착될 수 있으며, 장착 플레이트는 재지향 층들 중 하나를 형성하도록 에칭된다. 집적 회로 다이들은 인터포저의 각각의 측 상의 재지향 층들 및 제 3 집적 회로를 갖는 상부 패키지를 인터포저 어셈블리에 장착하고 전기적으로 연결하는데 이용되는 레벨간 연결 구조들에 부착될 수 있다. A system and method for providing a multi-die interposer structure is disclosed. One embodiment includes a plurality of interposer studs of a molded interposer, wherein the redirection layer is on each side of the interposer. Additionally, the interposer studs may first be attached to the conductive mounting plate by wire bond welding or soldering prior to molding the interposer, and the mounting plate is etched to form one of the redirection layers. The integrated circuit dies can be attached to the inter-level connection structures used to mount and electrically connect the top package with the redirection layers on each side of the interposer and the third integrated circuit to the interposer assembly.

Semiconductor device having bump and method of forming the same

필라 범프(pillar bump)를 갖는 반도체 소자에 관한 것이다. 기판 상에 도전성 패드가 형성된다. 상기 도전성 패드 상에 필라(pillar)가 형성된다. 상기 필라 상에 금속간 화합물 층(IMC layer)이 형성된다. 상기 금속간 화합물 층 상에 솔더 층이 형성된다. 상기 필라는 상기 금속간 화합물 층보다 좁은 폭을 갖는다. It relates to a semiconductor device having a pillar bump. A conductive pad is formed on the substrate. A pillar is formed on the conductive pad. An intermetallic compound layer (IMC layer) is formed on the pillar. A solder layer is formed on the intermetallic compound layer. The pillar has a narrower width than the intermetallic layer.

Semiconductor device and method of forming embedded die substrate, and system-in-package modules with the same

반도체 디바이스는 제1 기판을 가진다. 제1 반도체 부품은 제1 기판의 제1 표면 상에 배치된다. 제2 기판은 제2 기판의 제1 표면 상에 수직 상호연결 구조물을 포함한다. 제2 반도체 부품은 제2 기판의 제1 표면 상에 배치된다. 제1 반도체 부품 또는 제2 반도체 부품은 반도체 패키지이다. 제1 반도체 부품과 제2 반도체 부품은 제1 기판과 제2 기판 사이에 있도록 제1 기판은 제2 기판 위에 배치된다. 제1 인캡슐란트는 제1 기판과 제2 기판 사이에 증착된다. SiP 서브모듈은 인캡슐란트 반대편의 제1 기판 또는 제2 기판 위에 배치된다. 쉴딩층은 SiP 서브모듈 위에 형성된다. The semiconductor device has a first substrate. A first semiconductor component is disposed on a first surface of a first substrate. The second substrate includes a vertical interconnect structure on a first surface of the second substrate. A second semiconductor component is disposed on the first surface of the second substrate. The first semiconductor component or the second semiconductor component is a semiconductor package. The first substrate is disposed over the second substrate such that the first semiconductor component and the second semiconductor component are between the first substrate and the second substrate. A first encapsulant is deposited between the first and second substrates. The SiP submodule is disposed on the first or second substrate opposite the encapsulant. A shielding layer is formed over the SiP submodule.

Connection structure embedded substrate

본 개시는 1 절연바디, 및 상기 제1 절연바디의 외부 및 내부 중 적어도 하나에 배치된 복수 층의 제1 배선층을 포함하는 인쇄회로기판; 및 상기 제1 절연바디 내에 매립되며, 제1 및 제2 기판을 포함하는 연결구조체; 를 포함하며, 상기 제1 및 제2 기판은 인접하여 배치되는, 연결구조체 내장기판에 관한 것이다.

Semiconductor encapsulation device and its manufacturing method

一种半导体封装装置，其包括钝化层、导电元件、重新分布层RDL和电子组件。所述钝化层具有第一表面和与所述第一表面相对的第二表面。所述导电元件在所述钝化层内。所述导电元件界定面向所述钝化层的所述第二表面的凹槽。所述RDL在所述钝化层上且与所述导电元件电连接。所述电子组件安置于所述RDL上且与所述RDL电连接。

Chip package structure with integrated device integrated beneath the semiconductor chip

A package structure and a method of forming the same are provided. The package structure includes a package substrate, a semiconductor chip over the package substrate, and at least one integrated device integrated with the semiconductor chip. The integrated device is integrated directly beneath the semiconductor chip in order to facilitate signal transmission.

Electrode connection method and electrode connection structure

Die underfill structure and method

本申请涉及管芯底部填充结构和方法。一种将具有从其一个面112突出的多个铜柱（CuP）114的IC晶片100附接到在其一个面132上具有多个接触焊盘134的衬底130的方法包括：将其中具有大量填料颗粒126的膜层124施加到晶片100的所述一个面112；将其中基本不具有填料颗粒的甲阶树脂122施加到衬底130的所述一个面132；以及将所述膜层124与所述甲阶树脂122接合。

Semiconductor Device And Fabricating Method Thereof

본 발명은 기판의 하부에 결합되는 전자 소자의 높이를 보상하여, 전체적인 두께를 줄일 수 있고, 파인 피치의 구현이 가능한 반도체 디바이스 및 그 제조 방법을 제공한다. 일 실시예로서, 하면에 도전성 패드가 노출된 기판; 상기 기판에 적어도 일부가 삽입되어 형성된 전자 소자; 상기 기판의 상면에 결합되어 형성된 반도체 다이; 및 상기 반도체 다이를 감싸도록 상기 기판의 상면에 형성된 인캡슐런트를 포함하는 반도체 디바이스가 개시된다.

Circuit board with anchored underfill

公开了各种电路板和利用该电路板的制造方法。一方面，提供一种制造方法，其包括在电路板（20）的面（17）上施加焊接掩膜（90）和在焊接掩膜（90）中形成至少一个通向所述面（17）的开口（105）。将底部填充（25）定位在阻焊膜（90）上以使其中的一部分（100）突入至少一个开口（105）中。

Three-dimensional memory device and method of forming a three-dimensional memory device

Semiconductor package and method

실시예에서, 디바이스는, 제1 유전체층 상의 금속화 패턴과 금속화 패턴 상의 제2 유전체층을 포함하는 후면 재배선 구조물; 금속화 패턴에 접촉하도록 제1 유전체층을 관통해 연장되는 관통 비아; 제1 유전체층 상의 관통 비아에 인접한 집적 회로 다이; 제1 유전체층 상의 몰딩 화합물 - 몰딩 화합물은 관통 비아와 집적 회로 다이를 캡슐화함 -; 금속화 패턴에 접촉하도록 제2 유전체층을 관통해 연장되는 전도성 커넥터 - 전도성 커넥터는 관통 비아에 전기적으로 접속됨 -; 및 전도성 커넥터와 금속화 패턴의 계면에 있는 금속간 화합물을 포함하며, 금속간 화합물은 금속화 패턴 내로 단지 부분적으로만 연장된다. In an embodiment, a device includes: a rear surface redistribution structure comprising a metallization pattern on a first dielectric layer and a second dielectric layer on the metallization pattern; A through via extending through the first dielectric layer to contact the metallization pattern; An integrated circuit die adjacent the through via on the first dielectric layer; A molding compound on the first dielectric layer, the molding compound encapsulating the through via and the integrated circuit die; A conductive connector extending through the second dielectric layer to contact the metallization pattern, the conductive connector electrically connected to the through via; And an intermetallic compound at the interface of the conductive connector and the metallization pattern, wherein the intermetallic compound extends only partially into the metallization pattern.

Semiconductor package and method of manufacturing the same

在本发明实施例中，一种半导体封装包括中介件、管芯、保护层、多个第一电连接件及第一模制材料。管芯包括第一表面及与第一表面相对的第二表面，且管芯通过第一表面结合到中介件。保护层设置在管芯的第二表面上。第一电连接件设置在管芯旁边。第一模制材料设置在管芯、保护层及第一电连接件旁边。

Adhesives for semiconductors, semiconductor devices and methods of manufacturing the same

본 발명에서는 반도체 칩과, 기판 및/또는 다른 반도체 칩과, 이들 사이에 개재된 접착제층을 구비하는 반도체 장치의 제조 방법이 개시된다. 이 방법은, 반도체 칩과, 기판, 다른 반도체 칩 또는 반도체 웨이퍼와, 접착제층을 갖는 적층체를 가압착용 압박 부재 사이에 둠으로써 가열 및 가압하고, 이것에 따라 반도체 칩에 기판, 다른 반도체 칩 또는 반도체 웨이퍼를 가압착하는 공정과, 적층체를, 가압착용 압박 부재와는 별도로 준비된 본압착용 압박 부재 사이에 둠으로써 가열 및 가압하고, 이것에 따라 반도체 칩의 접속부와 기판 또는 다른 반도체 칩의 접속부를 접속하는 공정을 포함한다. In this invention, the manufacturing method of the semiconductor device provided with a semiconductor chip, a board | substrate and / or another semiconductor chip, and the adhesive bond layer interposed therebetween is disclosed. This method heats and pressurizes by placing a semiconductor chip, a board | substrate, another semiconductor chip or a semiconductor wafer, and the laminated body which has an adhesive bond layer between the pressing members for press bonding, and accordingly, a board | substrate, another semiconductor chip or The process of press-bonding a semiconductor wafer and the laminated body between the main press members prepared separately from the press-fitting press member are heated and pressurized, thereby connecting the connecting portion of the semiconductor chip and the connecting portion of the substrate or other semiconductor chip. It includes the step of connecting.

The bump pad of joint technology on trace

本发明提供了一种管芯和一种衬底。该管芯包括至少一个集成电路芯片，且该衬底包括至少部分延伸穿过该衬底的导电柱的第一子集和第二子集。导电柱的第一子集的每个都包括突出于衬底的表面的凸块焊盘，且导电柱的第二子集的每个都部分形成凹进衬底的表面中的迹线。通过多个导电凸块将管芯连接到衬底，多个导电凸块的每个都延伸到凸块焊盘的一个焊盘和管芯之间。

Semiconductor device with the etching groove for embedded equipment

一种具有用于嵌入式装置的蚀刻的沟槽的半导体装置被揭示，并且例如可以包含基板，其包括顶表面以及底表面；沟槽，从所述底表面延伸到所述基板中；以及在所述基板中的重分布结构，其是在所述基板的所述顶表面与所述底表面之间。半导体裸片可以是耦合至所述基板的所述顶表面。电子装置可以是至少部分地在所述沟槽之内，并且电耦合至所述重分布结构。导电垫可以是在所述基板的所述底表面上。导电凸块可以是在所述导电垫上。在所述沟槽中的所述电子装置可以延伸超出所述基板的所述底表面一段距离，所述距离小于所述导电凸块从所述基板的所述底表面起算的高度。囊封剂可以封入所述半导体裸片以及所述基板的所述顶表面。所述电子装置可以包括电容器。

Light emitting device package and lighting apparatus including the same

Alight emitting device package may include a printed circuit board and a plurality of light emitting devices mounted on the printed circuit board, wherein a first light emitting device of the plurality of light emitting devices may comprise first to fourth conductor pads formed discretely on the bottom surface of the light emitting device, the printed circuit board comprises first to fourth conductor patterns formed discretely on the top surface of the printed circuit board, and the first to fourth conductor patterns are connected to respective first to fourth conductor pads by respective first to fourth solders.

Fingerprint sensor and manufacturing method thereof

A fingerprint sensor device and a method of making a fingerprint sensor device. As non-limiting examples, various aspects of this disclosure provide various fingerprint sensor devices, and methods of manufacturing thereof, that comprise a sensing area on a bottom side of a die without top side electrodes that senses fingerprints from the top side, and/or that comprise a sensor die directly electrically connected to conductive elements of a plate through which fingerprints are sensed.

METHOD OF ASSEMBLING TWO ELECTRONIC COMPONENTS OF FLIP-CHIP TYPE BY UV-COATING, ASSEMBLY OBTAINED

L'invention concerne un procédé d'assemblage de type Flip-Chip, entre un premier (1) et un deuxième (2) composants comportant chacun des plots de connexion (11, 21) sur une de leurs faces, dites faces d'assemblage, selon lequel on reporte les composants l'un sur l'autre par leurs faces d'assemblage de sorte à réaliser des interconnexions électriques entre les plots du premier et ceux du deuxième composant. Selon l'invention, on réalise une transformation de l'oxyde de cuivre en cuivre par recuit UV, très localement dans l'espacement entre composants au moins autour des zones au droit des plots de connexion. Le procédé selon l'invention peut être utilisé pour n'importe quel composant transparent aux UV, y compris pour des substrats en matière plastique tels que des substrats en PEN ou en PET. The invention relates to a method of assembly of Flip-Chip type, between a first (1) and a second (2) components each having connection pads (11, 21) on one of their faces, said assembly faces , according to which the components are reported to one another by their assembly faces so as to achieve electrical interconnections between the pads of the first and those of the second component. According to the invention, a conversion of copper oxide to copper is carried out by UV annealing, very locally in the spacing between components at least around the zones to the right of the connection pads. The process according to the invention can be used for any UV-transparent component, including for plastic substrates such as PEN or PET substrates.

MICROELECTRONIC DEVICE FOR WIRELESS TRANSMISSION

Dispositif microélectronique (100) de transmission sans fil, comprenant : - un substrat (102) apte à être traversé par des ondes radio (103) destinées à être émises par le dispositif, - une antenne (106), - une alimentation électrique (112), - un circuit intégré (108), relié électriquement à l'antenne et à l'alimentation électrique, et apte à transmettre à l'antenne des signaux électriques destinés à être émis par l'antenne sous la forme desdites ondes radio, - un capot (116) solidarisé au substrat et formant, avec le substrat, au moins une cavité (114) dans laquelle sont disposés l'antenne et le circuit intégré, le capot étant composé d'un matériau électriquement conducteur, relié électriquement à un potentiel électrique de l'alimentation électrique et/ou du circuit intégré, et apte à former un réflecteur vis-à-vis des ondes radio destinées à être émises par l'antenne. Microelectronic device (100) for wireless transmission, comprising: - a substrate (102) capable of being traversed by radio waves (103) intended to be transmitted by the device, - an antenna (106), - a power supply (112) an integrated circuit (108), electrically connected to the antenna and to the power supply, and capable of transmitting to the antenna electrical signals intended to be emitted by the antenna in the form of said radio waves; a cover (116) secured to the substrate and forming, with the substrate, at least one cavity (114) in which are arranged the antenna and the integrated circuit, the cover being composed of an electrically conductive material, electrically connected to a potential electrical power supply and / or integrated circuit, and adapted to form a reflector vis-à-vis the radio waves to be emitted by the antenna.

Multiple die packaging interposer structure and method

다중 다이 인터포저 구조를 제공하기 위한 시스템 및 방법이 개시된다. 일 실시예는 몰딩된 인터포저의 복수의 인터포저 스터드들을 포함하고, 재지향 층은 인터포저의 각각의 측 상에 있다. 부가적으로, 인터포저 스터드들은 우선 인터포저를 몰딩하기 이전에 와이어 본드 용접 또는 솔더링에 의해 전도성 장착 플레이트에 부착될 수 있으며, 장착 플레이트는 재지향 층들 중 하나를 형성하도록 에칭된다. 집적 회로 다이들은 인터포저의 각각의 측 상의 재지향 층들 및 제 3 집적 회로를 갖는 상부 패키지를 인터포저 어셈블리에 장착하고 전기적으로 연결하는데 이용되는 레벨간 연결 구조들에 부착될 수 있다.

Junction structure

A bonding structure is a bonding structure which bonds a light emitting element and a substrate and includes a first electrode formed on the light emitting element, a second electrode formed on the substrate, and a bonding layer which bonds the first electrode and the second electrode, and the bonding layer contains a first bonding metal component and a second bonding metal component different from the first bonding metal component.

Interconnection structure including a metal post encapsulated by solder joint having a concave outer surface

A semiconductor device includes a carrier, an under bump metallurgy (UBM) pad on the carrier, and a post on a surface of the UBM pad. In some embodiments, a height of the post to a longest length of the UBM pad is between about 0.25 and about 0.7. A method of manufacturing a semiconductor device includes providing a carrier, disposing a UBM pad on the carrier and forming a post on the UBM pad.

Semiconductor package

반도체 패키지가 제공된다. 상기 반도체 패키지는, 패시베이션막, 패시베이션막 상의 몰드층, 패시베이션을 관통하는 제1 부분과 제1 부분 상에 몰드층의 일부를 관통하는 제2 부분을 포함하여 T자 형상을 갖는 연결 패드, 연결 패드의 제1 부분 상에 배치되는 솔더볼, 연결 패드의 제2 부분 상에 배치되는 소자, 몰드층 상에, 절연층 및 절연층 내 배선 패턴을 포함하는 배선 구조체, 및 배선 구조체 상에 배치되는 반도체 칩을 포함한다.

Surface acoustic wave filter package structure and method of manufacturing the same

一種表面聲波濾波器封裝結構，其包括一介電基板，具有一介電層、一第一圖案化導電層、一第二圖案化導電層及一導電連接層，其中導電連接層係設於介電層內，並且電性連接分設於介電層二側之第一圖案化導電層及第二圖案化導電層，且第二圖案化導電層至少具有一指叉電極部；一晶片，係以主動面面對於指叉電極部而設置；一高分子密封框體，係設置於晶片與介電基板之間，並圍設於晶片周緣，以與晶片及介電基板共同形成一密閉腔體；模封層係設置於介電基板之上，並且覆蓋晶片及高分子密封框體。本發明復提供表面聲波濾波器封裝結構之製法。

Package of finger print sensor

본 발명은 지문센서 패키지에 관한 것으로, 해결하고자 하는 기술적 과제는 도전성 범프와 지문센싱부가 반도체 다이의 일면에 구비되고, 타면에 구비된 보호판이나 보호막에 지문이 인접할 경우, 정전용량 변화를 통해 지문을 센싱할 수 있고, 지문센싱부가 구비된 반도체 다이가 기판에 플립칩 타입으로 안착되므로, 공정을 간소화하는데 있다. The present invention relates to a fingerprint sensor package. The technical problem to be solved is that the conductive bump and the fingerprint sensing part are provided on one side of the semiconductor die, and when the fingerprint is adjacent to the protection plate or the protection film provided on the other side, And the semiconductor die having the fingerprint sensing unit is mounted on the substrate as a flip chip type, thereby simplifying the process.

Integrated circuit packaging system with substrate and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; mounting a stack substrate over the base substrate with an inter-substrate connector directly on the stack substrate and the base substrate, the inter-substrate connector having an inter-substrate connector pitch; mounting an integrated circuit over the stack substrate, the integrated circuit having an internal connector directly on the stack substrate; and attaching an external connector directly on the base substrate, the external connector having an external connector pitch greater than the inter-substrate connector pitch.

Bump structure with barrier layer on post-passivation interconnect

A semiconductor device includes a barrier layer between a solder bump and a post-passivation interconnect (PPI) layer. The barrier layer is formed of at least one of an electroless nickel (Ni) layer, an electroless palladium (Pd) layer or an immersion gold (Au) layer.

Method for fabricating semiconductor package and semiconductor package using the same

One embodiment of the present invention provides a method for fabricating a semiconductor package capable of forming a thin semiconductor package, and a semiconductor package using the same. To this end, one embodiment of the present invention discloses the method including the following steps of: (A) forming an interposer on a wafer; (B) forming at least one conductive pad and at least one post on the interposer; (C) placing at least one semiconductor die on the interposer to be electrically connected with the conductive pad; (D) forming a cover layer on the exterior surface of the semiconductor die and the post; (E) encapsulating the post and the semiconductor die together on the interposer with an encapsulant; and (F) exposing the post to the exterior of the cover layer.