Contactless chip card manufacturing method

The manufacturing method has a conductive adhesive (9) applied via a dosing device to the surface of an antenna contact surface (20) incorporated in the card body, for securing a chip module contact surface, the height of the applied conductive adhesive measured via an electrode (35) displaced perpendicular to the chip card surface, with a voltage applied across the antenna contact surface and the measuring electrode, for providing a voltage discharge in the gas-filled space between the measuring electrode and the deposited conductive adhesive. An Independent claim for a device for a manufacture of chip cards is also provided.

Halbleitervorrichtung, Substrat zum Herstellen einer Halbleitervorrichtung und Verfahren zum Herstellen derselben

Halbleitervorrichtung, umfassend: eine Chipkontaktstelle; ein Halbleiterelement, das auf die Chipkontaktstelle geladen ist, das Elektroden aufweist; eine Mehrzahl von elektrisch leitfähigen bzw. leitenden Abschnitten, die um die Chipkontaktstelle angeordnet sind; Drähte zum Verbinden der Elektroden des Halbleiterelements und der elektrisch leitfähigen Abschnitte; und ein Dichtharz zum Dichten von wenigstens dem Halbleiterelement, den elektrisch leitfähigen Abschnitten und Drähten; wobei jeder der elektrisch leitfähigen Abschnitte eine Metallfolie enthält, wobei den elektrisch leitfähigen Abschnitt plattierende Schichten bzw. Lagen sowohl am oberen als auch unteren Ende der Metallfolie zur Verfügung gestellt sind; wobei die Chipkontaktstelle eine Chipkontaktstellen-Plattierschicht beinhaltet, die in derselben Ebene wie untere, den elektrisch leitfähigen Abschnitt plattierende Schichten der elektrisch leitfähigen Abschnitte vorgesehen ist; und wobei die unteren, den elektrisch leitfähigen ...

Mehrchip-Halbleitermodul und Herstellungsverfahren dafür

Ein Mehrchip-Halbleitermodul weist auf: ein Chipmontageteil mit einem ersten und zweiten Substrat, wobei das erste Substrat hat: eine entgegengesetzte erste und zweite Oberfläche, mehrere erste leitende Kontaktlöcher, die sich durch die erste und zweite Oberfläche erstrecken, und eine erste Schaltungsanordnung, die auf der zweiten Oberfläche strukturiert und mit den ersten leitenden Kontaktlöchern elektrisch verbunden ist, wobei das zweite Substrat hat: eine entgegengesetzte erste und zweite Oberfläche, mehrere zweite leitende Kontaktlöcher, die sich durch die erste und zweite Oberfläche des zweiten Substrats erstrecken, eine zweite Schaltungsanordnung, die auf der zweiten Oberfläche des zweiten Substrats strukturiert und mit den zweiten leitenden Kontaktlöchern elektrisch verbunden ist, und eine darin ausgebildete erste Chipaufnahmeöffnung, wobei die erste Oberfläche des zweiten Substrats auf der zweiten Oberfläche des ersten Substrats verbunden ist, so daß die zweite Schaltungsanordnung ...

Semiconductor component especially for low voltage power components has chip with contact bumps surrounded by conductive adhesive and electrodes shorted to a metal contact layer

A semiconductor component comprises housing (2) and chip (3) with a large surface contact between contact metal (5) on the chip and external contacts (6). Many small chip electrodes (7) are shorted to the contact metal and a transition layer (9) has contact bumps (11) surrounded by electrically conductive adhesive (12) on the contact metal.

Verfahren zum Verbinden einer integrierten Schatung mit einem Substrat und elektronische Schaltungsanordnung

Assembly structure of electronic parts prevents the formation of cracks in adhesive substrate

The assembly structure has the electronic part (11), which has first and second electrodes (13), a substrate on which the part is mounted, first and second solder eyes (15) on the substrate and a conducting adhesive (16) between the first electrode and first solder eye and between the second electrode and second solder eye to electrically connect them. Part of the conducting adhesive spreads out from one of the electrodes and solder eyes. An Independent claim is also included for a method of assembling electronic parts.

Verfahren zum Verbinden eines Chips mit einem Substrat unter Verwendung einer isotropen Verbindungsschicht und Verbundsystem aus Chip und Substrat

The invention relates to a method and a system whereby a chip (1) is coupled to a substrate (4), said chip having at least two bond pads (2) arranged on the same side at a distance from each other, and said substrate having at least two contact bond pads (5) arranged on the same side. An isotropic adhesive is applied to the side of the chips (1) where the bond pads (2) are arranged, or to the side of the substrate (4) where the contact bond pads (5) are arranged. The chip (1) and the substrate (4) are aligned in relation to each other so that the bond pads (2) of the chip (1) and the contact bond pads (5) of the substrates (4) are opposite each other. After the coupling, which occurs by bringing together the chip (1) and the substrate (2), a totally flat isotropic coupling layer (3) of adhesive is formed.

Semiconductor package for e.g. integrated circuit card in e.g. mobile phone, has external contact terminal provided within through-hole, which electrically connects conductive pattern to semiconductor chip

The semiconductor package (20) has a conductive pattern (24) provided on the substrate (23) and extended over the through-hole (23a). A semiconductor chip (22) is arranged within the through-hole. An external contact terminal (21) provided within the through-hole, electrically connects the conductive pattern to the semiconductor chip. Independent claims are included for the following: (1) semiconductor package formation method; and (2) electronic system formation method.

Production of conducting pathways on a substrate e.g. in microelectronics comprises applying a defined conducting adhesive on the substrate, partially hardening and repeating the previous steps

Production of conducting pathways on a substrate comprises applying a defined conducting adhesive on the substrate; partially hardening; and repeating the previous steps. An Independent claim is also included for a device for producing conducting pathways on a substrate (1) comprising a dispensing arrangement (5) for structuring and applying the conducting adhesive (7) on the substrate, and a hardening arrangement (8) for hardening the adhesive.

Method for manufacturing semiconductor component, involves applying electronic component on flexible carrier substrate, and determining reference point at flexible carrier substrate

The method involves applying an electronic component (2) on a flexible carrier substrate (3). A reference point is determined at the flexible carrier substrate, by which another structures are arranged on or at the flexible carrier substrate. The reference point is marked on the flexible carrier substrate by a metallic structure (20). An independent claim is also included for a semiconductor component, which has a flexible foil substrate.

LEADING METAL, CONNECTING METAL PARTICLES AND THEIR APPLICATIONS OF PRODUCTS

PROCEDURE FOR STICKING SUBSTRATES USING A LIGHT-ACTIVATE-CASH ADHESIVE FOIL

PROCEDURE FOR THE FLIP CHIP ASSEMBLY OF SEMICONDUCTOR DEVICES WITH ADHESIVES

HIGHLY RELIABLE ONES NOT CONDUCTIVE ADHESIVES FOR SOLDERING LOTS FLIP CHIP BONDINGS AND FLIP CHIPBONDVERFAHREN THEREBY

Semiconductor device, wiring board for mounting semiconducto r and method of production of semiconductor device

Adhesive agent, method for connecting wiring terminals and wiring structure

Method for processing semiconductor wafer, method for manufacturing ic card, and carrier

Method for adhering substrates using light activatable adhesive film

Leadless pad array chip carrier

Electroconductive connection between a chip and a coupling element in addition to a security element, security document and a valuable document containing a connection of said type

Method and materials for printing particle-enhanced electrical contacts

Conductive epoxy flip-chip

REACTIVE FOIL ASSEMBLY

METHOD FOR PRODUCTION OF MICROCAPSULE TYPE CONDUCTIVE FILLER

A novel and practical method for coating a conductive filler is disclosed. A microcapsule (MC) type conductive filler of this invention is produced by a method that comprises dispersing minute conductive particles (oil phase) allowing the presence of either both a solvent and a reactive substance A or the aforementioned reactive substance A alone on the surface thereof in water having dissolved therein a reactive substance B capable of reacting with the reactive substance A (aqueous phase) thereby forming a suspension or causing either both a solvent and at least one reactive substance or, as aforementioned, at least one reactive substance alone to be present on the surface of minute conductive particles toil phase) and dispersing the minute conductive particles in water thereby forming a suspension and applying heat or adding a catalyst to the suspension thereby inducing the reactive substance to react on the surface of the minute conductive particles thereby forming a thermosetting, thermoplastic ...

Device for pressing semiconductor chips located on a substrate.

Eine Vorrichtung zum Anpressen von auf einem Substrat (1) angeordneten Halbleiterchips (2) umfasst eine Substratauflage (3) und ein relativ zur Substratauflage in einer vorbestimmten Bewegungsrichtung (4) bewegbares Werkzeug (5), das mehrere in Bewegungsrichtung des Werkzeugs verschiebbar gelagerte Anpressstempel (13) zum Anpressen der Halbleiterchips aufweist. Das Werkzeug weist eine mit Druckluft beaufschlagbare Druckkammer (10) auf. Alle Anpressstempel sind entlang einer Geraden (12) angeordnet. Jeder der Anpressstempel weist einen an seinem der Druckkammer zugewandten Ende einen senkrecht zur Bewegungsrichtung des Werkzeugs und senkrecht zur genannten Geraden verlaufenden Balken (17) auf. Im Bereich zwischen der Druckkammer und den Anpressstempeln sind Kolben (14) angeordnet, die in Bewegungsrichtung des Werkzeugs verschiebbar sind. Die eine Seite der Kolben (14) ist dem in der Druckkammer herrschenden Druck ausgesetzt und die andere Seite liegt auf einem der Balken der Anpressstempel ...

Positioning device.

Die Erfindung betrifft eine Positionierungsvorrichtung (100) zum Positionieren eines Substrats (101), insbesondere eines Wafers, mit: einer Prozesskammer; einem Grundkörper (105); einem Trägerelement (107), welches eine Auflage (109) zum Auflegen des Substrats (101) umfasst, wobei das Trägerelement (107) über dem Grundkörper (105) angeordnet und hinsichtlich seines Abstandes vom Grundkörper (105) bewegbar ausgebildet ist; und einer Halterung (111) für ein weiteres Substrat (103), insbesondere für einen weiteren Wafer oder eine Maske, wobei die Halterung (111) gegenüber dem Trägerelement (107) angeordnet ist. Zwischen dem Grundkörper (105) und dem Trägerelement (107) liegt ein abgedichteter Hohlraum (113) vor, welcher mit einem Druck, insbesondere einem Unterdruck, beaufschlagbar ist, um eine ungewollte Bewegung des Trägerelements (107) aufgrund einer externen Krafteinwirkung zu verhindern.

Semiconductor device and manufacturing method of the same

The outflow of die bond material is prevented and the quality and the reliability of a semiconductor device are improved. A tab, a plurality of leads arranged around the tab, silver paste arranged on the chip supporting surface of the tab, and a semiconductor chip mounted via silver paste on the tab are included. Furthermore, a plurality of wires which electrically connect a pad of the semiconductor chip, and a lead, and a sealing body which does the resin seal of the semiconductor chip and the wires are included. By forming a step part whose height is lower than the chip supporting surface in the edge part of the chip supporting surface of the tab, the silver paste protruded from the tab can be stopped to this step part. As a result, an outflow to the back surface of the sealing body of silver paste can be prevented.

Sealing material

Semiconductor device and semiconductor device producing substrate and production method for semiconductor device producing substrate

DEVICE AND MANUFACTORING PROCESS OF ELECTRONIC DEVICES COMPRISING AUMOINS A CHIP FIXEE ON A SUPPORT

Method for implantation of a chip on a smart card and/or to memory, and card comprising a microcircuit for implanting.

MANUFACTORING PROCESS OF CONDUCTING POLYMERIC FILM ANISOTROPIC ON SECTION DESEMI-CONDUCTEUR

Making electrically conducting adhesive connection between module and electronic component e.g. for chip card, involves first introducing conducting body arranged in compressible fixing structure between them

Dans le procédé, on place des corps conducteurs entre les contacts de raccordement du module et du composant et l'on presse ensemble l'un contre l'autre, le module, le corps conducteur et le composant. Les corps conducteurs (16, 17) destinés à être placés entre le module (25) et le composant électrique (26), pour raccorder leurs contacts correspondants (20, 21), sont disposés dans une structure de fixation (10) compressible. Application à la fabrication fiable et économique de cartes à puce.

FLIP CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME

ADHESIVE COMPOSITION FOR SEMICONDUCTOR AND SEMICONDUCTOR DEVICE PRODUCED USING THE ADHESIVE COMPOSITION

AN ELECTRONIC DEVICE AND A METHOD OF MANUFACTURING THE SAME

MOUNTING STRUCTURE AND MOUNTING METHOD OF A SEMICONDUCTOR DEVICE, AND LIQUID CRYSTAL DISPLAY DEVICE

Structure and method of depositing tungsten by using polysilicon deposition, the structure liquid crystal display device and an electronic appliance using the same

ADHESIVE COMPOSITION, CIRCUIT CONNECTING MATERIAL USING THE SAME, METHOD FOR CONNECTING CIRCUIT MEMBERS, AND CIRCUIT CONNECTION STRUCTURE

ADHESIVE COMPOSITION, CIRCUIT CONNECTING MATERIAL AND CONNECTING STRUCTURE OF CIRCUIT MEMBER

Provided is an adhesive composition which contains an adhesive ingredient, conductive particles and insulating particles. The ratio (Ri/Rc) of the average particle diameter (Ri) of the insulating particle to the average particle diameter (Rc) of the conductive particle is 120-300%. © KIPO & WIPO 2008 ...

METHOD FOR FABRICATING SUBSTRATE JOINT BODY, SUBSTRATE JOINT BODY AND ELECTRO-OPTICAL APPARATUS TO SECURE CONDUCTION OF DEVICE AND INTERCONNECTION SUBSTRATE WITHOUT DAMAGING DEVICE AND INTERCONNECTION SUBSTRATE

PURPOSE: A method for fabricating a substrate joint body is provided to secure conduction of a device and an interconnection substrate without damaging the device and the interconnection substrate by increasing the pressurizing quantity of heat. CONSTITUTION: An electrode pad(17) of an interconnection substrate(3) is separated from an electrode pad(13a) of an electrical device(13) by a predetermined interval so that the interconnection substrate is mechanically connected to the electrical device. A bump(52) is grown from the electrode pad of the interconnection substrate and/or the electrode pad of the electrical device to electrically interconnect the interconnection substrate and the electrical device. © KIPO 2006 ...

ELECTROCONDUCTIVE PARTICLE PLACEMENT SHEET AND ANISOTROPIC ELECTROCONDUCTIVE FILM

ADHESIVE SHEET

SUBMOUNT AND METHOD FOR MANUFACTURING SAME

A submount provided with an electrode layer having excellent wettability for solder bonding, and a method for manufacturing such submount are provided. In the submount (1) whereupon a semiconductor device is to be mounted, a substrate protecting layer (3) is formed on a surface of a submount substrate (2), the electrode layer (4) is formed on the substrate protecting layer (3), and a solder layer (5) is formed on the electrode layer (4). The average roughness of the surface of the electrode layer (4) is smaller than 0.1μm. Since the surface average roughness of the electrode layer (4) is small, the wettability of the solder layer (5) is improved, and the solder layer (5) can be firmly bonded with the semiconductor device without flux. The submount (1) having a small thermal resistance when the semiconductor device is mounted is provided, thus, temperature increase in the semiconductor device is permitted to be small and the performance and life of the semiconductor device are improved.

ANISOTROPIC CONDUCTIVE FILM

PURPOSE: To provide an anisotropic conductive film enabled to create a good conductive state by strongly adhering to an electronic component and circuit board by thermal bonding with low temperature which does not cause any deterioration of the circuit board. CONSTITUTION: For the anisotropic conductive film composed of a film board 1A having a plurality of conduction paths 2 running in the direction of the thickness of the film board, and both ends of the conduction paths 2a, 2b, exposed on the front and back side of the film board, the film board 1A is mainly composed of a copolymer of polycarbodiimide with a structure expressed by formula (1). In the formula (1), m represents integer of 2-50, n represents integer of 1-30, z represents integer of 1-10, A represents urethane bond, R1 represents alkylene group, R2 represents aromatic diisocyanate residue, and R3 represents aromatic monoisocyanate residue. © KIPO & JPO 2003 ...

CONDUCTIVE METAL PARTICLES, CONDUCTIVE COMPOSITE METAL PARTICLES AND APPLIED PRODUCTS USING THE SAME

PURPOSE: Conductive metal particles and conductive composite metal particles by which conductive materials having stable conductivity can be provided are provided, and applied products using the conductive metal particles and conductive composite metal particles are provided. CONSTITUTION: The conductive metal particles have a number average particle diameter of 5 to 100μm, a BET specific surface area of 0.01×10^3 to 0.7×10^3 m/kg, a sulfur element content of at most 0.1% by mass, an oxygen element content of at most 0.5% by mass and a carbon element content of at most 0.1% by mass, wherein the coefficient of variation of the particle diameter is at most 50%, the saturation magnetization of the particles is at least 0.1 Wb/m^2, the conductive composite metal particles are obtained by coating the surfaces of the conductive metal particles with a high-conductive metal. © KIPO 2002 ...

Adhesive film, connecting method, and connected structure

Disclosed are: an adhesive film which enables to connect an electronic component to a substrate without causing short-circuiting; a connection method; and an assembly. The adhesive film comprises a first adhesive layer and a second adhesive layer closely adhered to the first adhesive layer. The first adhesive layer has a minimum viscosity higher than that of the second adhesive layer, wherein the minimum viscosity is measured at a temperature equal to or lower than the curing start temperature at which the first or second adhesive layer starts to cure. The first and second adhesive layers are faced toward a substrate and an electronic member, respectively, so that the electronic member can be connected to the substrate by pressing against the substrate and the electronic member while heating.; The first adhesive layer has an electrically conductive particle dispersed therein, and has a thickness less than twice the average particle diameter of the electrically conductive particle.

Method for permanent bonding of wafers

This invention relates to a method for bonding of a first solid substrate (1) to a second solid substrate (2) which contains a first material with the following steps, especially the following sequence: formation or application of a function layer (5) which contains a second material to the second solid substrate (2), making contact of the first solid substrate (1) with the second solid substrate (2) on the function layer (5), pressing together the solid substrates (1, 2) for forming a permanent bond between the first and second solid substrate (1, 2), at least partially reinforced by solid diffusion and/or phase transformation of the first material with the second material, an increase of volume on the function layer being caused.

Electric circuit board

The present invention provides an electric circuit board capable of connecting an IC or a semiconductor chip with high reliability. An electrode part 20 to which the metal electrode (bump) of an IC circuit will be connected from an upper part is formed on the glass substrate 11 of a liquid crystal display device. The electrode part 20 is constituted by opening an inter-layer insulating film 23 in a part corresponding to metal wiring 22 and forming a land-like electrode pad 25 in this opened part. In the present invention, the plane shape of the electrode pad 25 is made smaller than the opened part of the inter-layer insulating film 23. Thus the flatness of the peripheral surface of the electrode 20 is improved.

Manufacturing method for semiconductor wafer and IC card and its bearer

A kind of manufacturing method for semiconductor wafer whose features are - the first engineering process: preparing the planklike or filmy bearer which is composed of the substrate and the connection element installed on one surface of the substrate - the second engineering process: let the inner surface without electric circuit element forming face oppositely to said bearer and form the wafer composite by connecting the semiconductor wafer to said bearer. - the third engineering process: let the side of said wafer composite of semiconductor wafer face upward and hold the wafer composite letting the etching liquid be rotately spreading on the inner surface of said wafer composite to apply the thinly processing on it.

Mounting device for electric components

Circuit-connecting material and circuit terminal connected structure and connecting method

A circuit-connecting material which is interposed between circuit electrodes facing each other and electrically connects the electrodes in the pressing direction by pressing the facing electrodes against each other; the circuit-connecting material comprising as essential components (1) a curing agent capable of generating free radicals upon heating, (2) a hydroxyl-group-containing resin having a molecular weight of 10,000 or more and (3) a radical-polymerizable substance. Also provided are a circuit terminal connected structure and a circuit terminal connecting method which make use of such a material.

Flip chip interconnection structure and method for forming same

A flip chip interconnection structure is formed by mechanically interlocking joining surfaces of a first and second element. The first element, which may be a bump on an integrated circuit chip, includes a soft, deformable material with a low yield strength and high elongation to failure. The surface of the second element, which may for example be a substrate pad, is provided with asperities into which the first element deforms plastically under pressure to form the mechanical interlock.

METAL FILLED THROUGH VIA STRUCTURE FOR PROVIDING VERTICAL WAFER-TO WAFER INTERCONNECTION

A method of fabricating a through via connection useful in providing a vertical wafer- to-wafer interconnect structure is provided as well as the vertical interconnect structure that is formed by this method. The method of the present invention using only a metal stud for the vertical connection therefore no alpha radiation is generated by the metal stud. The method of the present invention includes an inserting step, a heating step, a thinning step and backside processing.

PRINTING SEMICONDUCTOR ELEMENTS BY SHEAR-ASSISTED ELASTOMERIC STAMP TRANSFER

Provided are methods and devices for transfer printing of semiconductor elements to a receiving surface. In an aspect, the printing is by conformal contact between an elastomeric stamp inked with the semiconductor elements and a receiving surface, and during stamp removal, a shear offset is applied between the stamp and the receiving surface. The shear-offset printing process achieves high printing transfer yields with good placement accuracy. Process parameter selection during transfer printing, including time varying stamp-backing pressure application and vertical displacement, yields substantially constant delamination rates with attendant transfer printing improvement.

MIXED ALLOY SOLDER PASTE

A solder paste comprises an amount of a first solder alloy powder between about 60 wt% to about 92 wt%; an amount of a second solder alloy powder greater than 0 wt% and less than about 12 wt%; and a flux; wherein the first solder alloy powder comprises a first solder alloy that has a solidus temperature above about 260°C; and wherein the second solder alloy powder comprises a second solder alloy that has a sol idus temperature that is less than about 250°C.

CONNECTING MATERIAL, SEMICONDUCTOR DEVICE, AND PROCESS FOR PRODUCING SAME

Lead-free connecting materials having satisfactory wetting properties and high heat resistance have come to be required as a result of increases in the temperature of element connection parts due to increases in the capacity of power modules. A Sn-based layer (11a) is formed by cladding or press forming as an outermost layer of an alloy foil (13) which comprises Sn (11b) and Al (12) as major components and which has an Al content of 40 mass% or less, thereby removing an oxide film from the alloy surface layer. Since the Al content of the alloy foil is 40 mass% or less, separation between the Sn and the Al is inhibited and wetting properties can be ensured. Thus, a connecting material and a connection which each has high heat resistance and is lightweight are possible.

MOUNTING METHOD USING THERMOCOMPRESSION HEAD

Provided is a mounting method using a thermocompression head which can mount an electric component in a short time with high connection reliability. The method is provided for mounting an electronic component (20) on a wiring board (10) by using a thermocompression head (3) having an elastic pressure bonding member (7) composed of an elastomer on a heatable metal head main body (5). In the method, after arranging an adhesive on a mounting region on the wiring board (10), an electric component (20) is arranged on a mounting region, and the electric component (20) is bonded on the wiring board (10) by thermocompression by using the thermocompression head (3). At the time of performing thermocompression bonding, while pressing a top region (21) of the electric component (20) by a metal portion of the head main body (5), an adhesive (30) in the vicinity of a side portion region (22) of the electric component (20) is pressed by a taper section (7a) of the elastic adhesive member (7).

THERMAL INTERCONNECT SYSTEMS METHODS OF PRODUCTION AND USES THEREOF

Layered interface materials described herein include at least one pulse-plated thermally conductive material, such as an interconnect material, and at least one heat spreader component coupled to the at least one pulse-plated thermally conductive material. A plated layered interface material having a migration component is also described herein and includes at least one pulse-plated thermally conductive material; and at least one heat spreader component, wherein the migration component of the plated layered interface material is reduced by at least 51% as compared to the migration component of a reference layered interface material. Another layered interface material described herein includes: a) a thermal conductor; b) a protective layer; c) a layer of material to accept solder and prevent the formation of oxides; and d) a layer of solder material. Methods of forming layered interface materials are described herein that include: a) providing a pulse-plated thermally conductive interface ...

CONNECTING STRUCTURE, LIQUID CRYSTAL DEVICE, ELECTRONIC EQUIPMENT, ANISOTROPIC CONDUCTIVE ADHESIVE, AND METHOD FOR MANUFACTURING THE ADHESIVE

An anisotropic conductive adhesive which can improve the secured and reliable continuity between terminals to be connected to each other by surely interposing a prescribed number of conductive particles. In the adhesive (1), a plurality of conductive particles (3) contained in an insulating adhesive material (2) of the adhesive (1) is unevenly distributed to one adhesive surface side of the material (2) having two adhesive surfaces. When the adhesive surface of the material (3) to which the conductive particles (3) are distributed is directed to one of the two terminals which is less protruded toward the adhesive (1) at the time of arranging the adhesive (1) between the two terminals, the conductive particles (3) are not pushed out even when the adhesive (1) is pushed out in the lateral direction by the other terminal which is largely protruded toward the adhesive (1) at the time of thermocompression bonding, because the particles (3) are not distributed to the other terminal side. Therefore ...

HYBRID CONDUCTIVE COATING METHOD FOR ELECTRICAL BRIDGING CONNECTION OF RFID DIE CHIP TO COMPOSITE ANTENNA

A radio frequency identification device (RFID) includes a non-conductive first substrate, an integrated circuit device mounted to the carrier substrate and having at least one conductive terminal and a patterned conductive coating applied to the non- 5 conductive substrate and in contact with the at least one conductive terminal. The patterned conductive coating includes a polymeric matrix and a conductive particulate filler, the polymeric matrix being capable of undergoing at least 2% deformation elastically and without significant change in the conductive properties of the patterned conductive coating serving as an antenna. The RFID can be fabricated by affixing an IC 0 chip to a surface of a substrate having a patterned conductive coating and applying a bridging coating to connect terminals of the IC chip to the antenna.

ADHESIVE COMPOSITION, CIRCUIT CONNECTING MATERIAL, CONNECTING STRUCTURE FOR CIRCUIT MEMBER, AND SEMICONDUCTOR DEVICE

Disclosed is an adhesive composition containing a thermoplastic resin, a radically polymerizable compound, a radical polymerization initiator and a radical polymerization modifier. The adhesive composition can be cured sufficiently quickly at low temperatures while exhibiting sufficiently stable adhesion strength, and has a wide process margin for curing. Also disclosed are a circuit connecting material, a connecting structure for circuit members and a semiconductor device.

Semiconductor device and method for producing a semiconductor device

A semiconductor device exhibits a first metal layer, made of a first metal, with at least one contiguous subsection. At least one second metal layer, made of a second metal, is placed on the contiguous subsection of the first metal layer. The second metal is harder than the first metal. The second metal layer is structured to form at least two layer regions, which are disposed on the contiguous subsection of the first metal layer. The second metal exhibits a boron-containing or phosphorus-containing metal or a boron-containing or phosphorus-containing metal alloy.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

It is an object of the present invention to provide a method of separating a thin film transistor, and circuit or a semiconductor device including the thin film transistor from a substrate by a method different from that disclosed in the patent document 1 and transposing the thin film transistor, and the circuit or the semiconductor device to a substrate having flexibility. According to the present invention, a large opening or a plurality of openings is formed at an insulating film, a conductive film connected to a thin film transistor is formed at the opening, and a peeling layer is removed, then, a layer having the thin film transistor is transposed to a substrate provided with a conductive film or the like. A thin film transistor according to the present invention has a semiconductor film which is crystallized by laser irradiation and prevents a peeling layer from exposing at laser irradiation not to be irradiated with laser light.

Die-in heat spreader microelectronic package

Microelectronic packages including a microelectronic die disposed within a recess in a heat spreader and build-up layers of dielectric materials and conductive traces are then fabricated on the microelectronic die and the heat spreader to form the microelectronic package, and methods for the fabrication of the same, including methods to align the microelectronic die within the heat spreader. In another embodiment, a microelectronic die is disposed on a heat spreader which has a filler material disposed therearound and build-up layers of dielectric materials and conductive traces are then fabricated on the microelectronic die and the filler material to form the microelectronic package, and methods for the fabrication of the same, including methods to align the microelectronic die on the heat spreader.

Flip chip interconnection structure

A flip chip interconnection structure is formed by mechanically interlocking joining surfaces of a first and second element. The first element, which may be a bump on an integrated circuit chip, includes a soft, deformable material with a low yield strength and high elongation to failure. The surface of the second element, which may for example be a substrate pad, is provided with asperities into which the first element deforms plastically under pressure to form the mechanical interlock.

Flip chip MLP with conductive ink

The invention provides a flip chip molded leadless package (MLP) with electrical paths printed in conducting ink. The MLP includes a taped leadframe with a plurality of leads and a non-conducting tape placed thereon. The electrical paths are printed on the tape to connect the features of the semiconductor device to the leads and an encapsulation layer protects the package. In a second embodiment, the MLP includes a pre-molded leadframe with the electrical paths printed directly thereon. The present invention also provides a method of fabricating the semiconductor package according to each embodiment.

Semiconductor substrate with conductive bumps having a stress relief buffer layer formed of an electrically insulating organic material

A microelectronic structure is provided having a semi-conducting substrate comprising circuits therein and a top surface, and at least one first conductive bump situated on the top surface. The conductive bump provides electrical communication to the circuits. The at least one conductive bump has a stress relief buffer layer formed of an electrically insulating organic material. The portions of the at least one conductive bump other than the stress relief buffer layer are a unitary structure. The top surface of the conductive bump is uncovered and directly exposed to its surroundings.

Semiconductor device with intermediate connector

A semiconductor element and a circuit substrate each having electrodes disposed at narrow pitch are electrically connected with high reliability by conductive paste. A semiconductor device with a semiconductor section and a circuit substrate electrically connected and a method for manufacturing such semiconductor device are provided. The manufacturing method includes processes of: forming semiconductor electrodes at the semiconductor section; forming substrate electrodes at the circuit substrate; firstly affixing one part of the semiconductor section and circuit substrate to an intermediate connector made of insulating material; forming via holes at intermediate connector according to positions of the semiconductor electrodes and positions of the substrate electrodes; electrically connecting each semiconductor electrode and each substrate electrode via each via hole; and secondly affixing the other part of the semiconductor section and circuit substrate to the intermediate connector.

Method of planarizing a curved substrate and resulting structure

According to the present invention a technique for providing a planarized substrate with dendritic connections of solder balls, especially a multi-layer ceramic substrate is provided. In the case where the substrate has a raised central portion on the top surface on which are disposed top surface metallurgy pads, a layer of conformable photoimagable material is placed over the top surface. The photoimagable material is exposed and developed in a pattern corresponding to the pattern of the top surface metallurgy pads to form vias in the photoimagable material. Copper is plated in the vias in contact with the top surface metallurgy pads. The exposed surface of the photoimagable surface is then planarized, preferably by mechanical polishing to form a flat planar surface, with the ends of the vias exposed. Dendritic connector pads are then grown on the exposed ends of the vias to which solder ball connections of an I/C chip are releasably connected.

Flexible printed polymer lead frame

A polymer lead frame is made from a flexible substrate with flexible conductive traces. The generally square lead frame has diagonal cutouts partially extending from the corners towards the center, as well as a central hole that lies within a footprint of the die. The die is bonded directly to the lead frame, preferably with anisotropic, electrically conductive adhesive. The die is placed with the lead frame in a fixture. A holding force is applied to secure the die and, if necessary, a curing force is applied during a cure cycle. The fixture allows transport of the assembly to a curing oven and allows application of the curing force. The die has contact pads characterized by a non-planar, non-bump-like surface with concavities having depths of at least about one-seventh the diameter of conductive particles in the anisotropic conductive adhesive.

Interconnections with electrically conductive adhesives: structures, materials, method and their applications

A new interconnection scheme is disclosed for a tape automated bonding (TAB) package, a flip chip package and an active matrix liquid crystal display (AMLCD) panel, where an electrically conducting adhesive is used to form an electrical interconnection between an active electronic device and its components. The electrically conducting adhesive can be a mixture comprising a polymer resin, a no-clean solder flux, a plurality of electrically conducting particles with an electrically conducting fusible coating which provides a metallurgical bond between the conducting particles as well as to the substrates. The advantages of using the electrically conducting adhesives include reduction in bonding pressure and/or bonding temperature, control of interfacial reactions, promotion of stable metallurgical bonds, enhanced reliability of the joints, and others.

Lead-on-chip type semiconductor device having thin plate and method for manufacturing the same

In a semiconductor device having a lead-on-chip structure, a thin plate is arranged in an outer peripheral area of a semiconductor element and has a thickness substantially the same as that of the semiconductor element.

Apparatuses and methods for high speed bonding

Apparatuses and methods for high speed bonding for an RFID device are provided. A first substrate includes an antenna and is coupled to a strap assembly by an adhesive material. The adhesive material is substantially inert thermally for a predetermined temperature range, or it otherwise lacks a heat flow variation greater than 0.05 W/g for the predetermined temperature range. Such an adhesive material provides a reliable bond. In a specific embodiment, the predetermined temperature range is about 30° Celsius to about 85° Celsius. In an alternative embodiment, the adhesive material can be exposed to water or steam to reduce its heat flow variation to less than 0.05 W/g for the temperature range.

ADHESIVE FOR BONDING CIRCUIT MEMBERS, CIRCUIT BOARD AND PROCESS FOR ITS PRODUCTION

An adhesive for bonding and securing a semiconductor chip to a circuit board and electrically connecting the electrodes of the two, and containing an adhesive resin composition and an inorganic filler being contained in an amount of 10 to 200 parts by weight of 100 parts by weight of the adhesive resin composition.

Circuit board and process for producing the same

The invention includes: applying an anisotropic conductive resin including conductive particles only to a plurality of bumps of an electronic component; placing the electronic component above a main surface of a flexible wiring board via the anisotropic conductive resin; and pressurizing the electronic component to the wiring board and curing the anisotropic conductive resin applied to the plurality of bumps to join the plurality of bumps to the electrodes of the wiring board. This can prevent a defective mounting of the electronic component.

Horizontal Carbon Nanotubes by Vertical Growth and Rolling

Horizontal carbon nanotubes may be used for on-die routing and other applications. In one example, a catalyst is applied to a plurality of different points on a substrate. Carbon nanotubes are then grown vertically on the plurality of different points to form a plurality of vertical carbon nanotube structures on the substrate. The vertical carbon nanotuhe structures are then rolled to form horizontal carbon nanotube structures.

Use of palladium in IC manufacturing with conductive polymer bump

An apparatus and a method for forming a substrate having a palladium metal layer over at least one contact point of the substrate and having a flexible conductive polymer bump, preferably a two-stage epoxy, on the palladium plated contact point, are provided. The present invention also relates to assemblies comprising one or more of these substrates.

Method of Dissipating heat, Packaging and Shaping for Light Emitting Diodes

A method of dissipating heat, packaging and shaping for light emitting diodes enhances the heat dissipation performance of light emitting diodes, and its structure includes a substrate and a light emitting diode chip. An antioxidation is performed at a high temperature at a predetermined position for installing a chip on the surface of the substrate; a layer of intermetallic layer is coated; a solder material is placed on the intermetallic layer and at the predetermined position of the chip; an intermetallic layer is also coated onto the adhering surface of the chip; the adhering surface of the chip is coupled with the solder material; meanwhile the intermetallic layer and the solder material are heated by furnace to form a stable metal alloy structure, so that the chip can be fixed onto the substrate; and finally the light emitting diode structure is completed by a wirebond process.

Semiconductor device with intermediate connector

A semiconductor element and a circuit substrate each having electrodes disposed at narrow pitch are electrically connected with high reliability by conductive paste. A semiconductor device with a semiconductor section and a circuit substrate electrically connected and a method for manufacturing such semiconductor device are provided. The manufacturing method includes processes of: forming semiconductor electrodes at the semiconductor section; forming substrate electrodes at the circuit substrate; firstly affixing one part of the semiconductor section and circuit substrate to an intermediate connector made of insulating material; forming via holes at intermediate connector according to positions of the semiconductor electrodes and positions of the substrate electrodes; electrically connecting each semiconductor electrode and each substrate electrode via each via hole; and secondly affixing the other part of the semiconductor section and circuit substrate to the intermediate connector.

VERTICALLY INTEGRATED WAFERS WITH THERMAL DISSIPATION

Technologies are generally described related to three-dimensional integration of integrated circuits (ICs) with spacing for heat dissipation. According to some examples, a self-aligned silicide may be formed in a temporary silicon layer and removed subsequent to bonding of the wafers to achieve improved contact between the combined ICs and enhanced heat dissipation through added spacing between the ICs.

Thin-film semiconductor device and method of manufacturing the same

A thin-film semiconductor device with a reduced influence on a device formation layer in separation and a method of manufacturing the device are provided. The manufacturing method includes the step of preparing a member having a semiconductor film with a semiconductor element and/or semiconductor integrated circuit on a separation layer, the separation step of separating the member at the separation layer by a pressure of a fluid, and the chip forming step of, after the separation step, forming the semiconductor film into chips.

Method for mounting a driver IC chip and a FPC board/TCP/COF device using a single anisotropic conductive film

A method for bonding integrated circuit chips and other devices to a liquid crystal display panel. The method involves using a single anisotropic conductive film that is sized to bond at least one integrated circuit chip and at least one other device, such as a flexible printed circuit board, a tape carrier package and a chip-on-film, to the liquid crystal display panel.

DRIVER CHIP AND DISPLAY APPARATUS HAVING THE SAME

A driver chip includes a base body, input terminals, first output terminals and dummy terminals. The base body includes a face having first to fourth edge portions. The first and second edge portions are disposed in substantially parallel along a longitudinal side of the face, and the third and fourth edge portions are disposed in substantially parallel along a horizontal side of the face. The input terminals are formed on the first edge portion such that the input terminals are arranged along the longitudinal side. The first output terminals are formed on the second edge portion such that the first output terminals are arranged along the longitudinal side. The dummy terminals are formed such that the dummy terminals are disposed between the input terminals and the first output terminals. A warpage and defects of electrical connection between the driver chip and a display panel of the display apparatus are prevented.

CIRCUIT DEVICE, METHOD OF MANUFACTURING THE CIRCUIT DEVICE, DEVICE MOUNTING BOARD AND SEMICONDUCTOR MODULE

A circuit device includes an insulating base provided with a resin layer mixed with a fibrous filler, bumps provided in the insulating base and functioning as electrodes for connection, a semiconductor device that is flip-chip mounted, and an underfill filling a gap between the semiconductor device and the insulating base. By allowing the fibrous filler projecting through the top surface of the resin layer to be in contact with the underfill, strength of adhesion between the underfill and the insulating base is improved.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

The present invention provides a method for manufacturing a semiconductor device which includes at least supplying an adhesive for bonding an electronic component which has a plurality of bumps with a substrate which has a plurality of bonding pads corresponding to the bumps, to at least a portion of the substrate, between the electronic component and the substrate, flow-casting the adhesive on the substrate by a flow-casting unit, in such a manner that the expression S₁/S₀>1 is satisfied, where S₀ is the total contact surface area with the substrate of the adhesive supplied to the substrate, and S₁ is the total contact surface area with the substrate of the adhesive after the flow-casting, and curing the adhesive while making the adhesive contact with the electronic component and the substrate in a state where the bumps are abutted against the bonding pads.

ELECTRONIC COMPONENT STRUCTURE AND METHOD OF MAKING

An external component, typically a surface mount passive, is attached to a semiconductor die. In some embodiments the passive is placed directly over exposed pads on the semiconductor die and attached using conductive tape or conductive epoxy. In some embodiments the passive is attached to the semiconductor die using non-conductive adhesive and wire bonded to bond pads on the semiconductor die and/or to pads on a substrate to which the semiconductor die is attached.

Method of mounting an electronic component on a circuit board

When mounting an IC chip (1) on a circuit board (4), bumps (3) are formed on electrodes (2) on the IC chip, and the bumps and the electrodes (5) of the circuit board are aligned in position with each other with interposition of an insulative thermosetting resin (6). The resin sheet (6) is provided with through holes (15) in which are embedded conductive particles (14). The bumps (3), the through holes (15) and the electrodes are aligned. The IC chip is pressed against the circuit board with a pressure force of not smaller than 20 gf per bump by a heated head (8) so as to perform warp correction of the IC chip and the board, while the resin interposed between the IC chip and the circuit board is hardened to bond the IC chip and the circuit board together.

CONDUCTIVE PARTICLE, ADHESIVE COMPOSITION, CIRCUIT-CONNECTING MATERIAL, CIRCUIT-CONNECTING STRUCTURE, AND METHOD FOR CONNECTION OF CIRCUIT MEMBER

The conductive particle of the invention each comprises a conductive nucleus particle and an insulating coating containing an organic high molecular compound on the surface of the nucleus particle, and the coverage factor as defined by the following formula (1) is in the range of 20-40%.

Low stress conductive adhesive

A low stress conductive film or paste adhesive that comprises a) one or more functional acrylic copolymers or terpolymers; b) epoxy; and c) conductive filler. Additional ingredients, such as adhesion promoters and conductivity enhancers may also be utilized. The conductive film or paste adhesive provides higher adhesion strength than traditional flexible conductive film adhesives and a lower stress between the bonded components than existing high adhesion strength conductive films.

POLYMERIZABLE FLUXING AGENTS AND FLUXING ADHESIVE COMPOSITIONS THEREFROM

A thermally curable adhesive composition that includes a fluxing agent that also acts as an adhesive is provided. The composition includes: (a) a fluxing agent represented by the formula RCOOH, wherein R comprises a moiety having two or more carbon-carbon double bonds wherein in one embodiment, at least one is within an acrylate or methacrylate group, and which may further contain at least one aromatic moiety; (b) a carboxylic acid neutralizing agent; (c) optionally, an effective amount of a cross-linkable diluent; (d) optionally, an effective amount of a source of free radical initiators; and (e) optionally, an effective amount of a resin. By employing an acrylate, methacrylate, or phenol in the structure of the adhesive flux, the cure temperature and moisture absorption characteristics can be significantly improved. The composition can be applied directly onto the surface(s) of devices that are to be joined electrically and mechanically. These devices include, printed circuit substrates ...

Particle material, anisotropic conductive connection and anisotropic conductive connection material

A bump forming apparatus which carries out a temperature control of a type different from the conventional art in forming bumps to a semiconductor wafer, and a bump formation method executed by the bump forming apparatus are provided. A bonding stage (110), a load and transfer device (140) and a control device (180) are comprised, whereby a wafer (202) after having bumps formed thereon which is held by the load and transfer device is disposed to above the bonding stage through control by the control device, so that a temperature drop of the wafer is controlled. Accordingly, generation of troubles such as a crack because of a thermal stress and the like can be prevented to even compound semiconductor wafers sensitive to a temperature change.

SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To effectively eliminate heat generated by an operation of an IC chip and the like without cost increase. SOLUTION: The semiconductor device 1 includes: a substrate 10; the IC chip 3 fixed onto the substrate 10; a conductor 11 arranged to a surface of the substrate 10; a solder resist 12 covering the surface of the substrate 10 and the conductor 11 and formed with an opening 17 for exposing the conductor 11 in a portion corresponding to the fixed surface of the IC chip 3; and an adhesive 5 contacting the fixed surface and an exposed portion 18 of the conductor 11 by the opening 17. COPYRIGHT: (C)2011,JPO&INPIT ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of improving the reliability, and the method for manufacturing the same. SOLUTION: The semiconductor device comprises a base material 103; and a semiconductor element 100 joined to the base material 103 via a junction layer 11. The junction layer comprises a first layer 11a; and a second layer 11b with a viscosity lower than that of the first layer at a junction temperature, and the first layer has a part in which an edge of the first layer is inside an edge of the semiconductor element, and the part which is inside the edge of the semiconductor element is at least partly filled with a part of the second layer outwardly pushed from a circumference of the first layer to outside. COPYRIGHT: (C)2012,JPO&INPIT ...

導電性接着剤

... 多孔質基材の中を通って延びる多数の通路を有する多孔質基材から作成された導電性接着剤が開示される。通路を画定する基材の壁は、導電性金属でコーティングされる。これは、多孔質基材の1つの面から他の面に連続したコーティングを与える。残りの通路の空間は、接着剤樹脂で実質的に満たされる。この接着剤は、2つの金属表面を電気的に接続するために使用されることができる。 ...

CONNECTION STRUCTURE OF SEMICONDUCTOR CHIP

PURPOSE: To obtain connection which stabilizes continuity at the fine area and improves reliability by directly providing a semiconductor chip having a pad at the lower surface onto a substrate through a conductive anisotropic bonding agent. CONSTITUTION: A conductive anisotropic bonding agent layer 9 which allows mixing and dispersion of conductive fine particles into the bonding agent having insulation property and has conductivity in the thickness direction is arranged between an IC chip 8 and a conductive lead layer 10 formed on a substrate corresponding to a pad of IC chip by the etching. It is then pressurized for making continuity of the required part to the conductive lead layer 10 with the pad of IC chip 8 and simultaneously the IC chip 8 is fixed to the substrate 11 with the bonding layer 9. In case the pad of IC chip 8 is formed as the protruded part, the conductive anisotropic effect is further increased. COPYRIGHT: (C)1985,JPO&Japio ...

METHOD OF MOUNTING SEMICONDUCTOR CHIP

PURPOSE: To enable a semiconductor chip to be simplified in mounting process and easily mounted by a method wherein an anisotropically conductive thermoplastic sheet where a discriminating mark that indicates the position of a pad electrode is applied is arranged on a mounting substrate, and a semiconductor chip is aligned thereon and bonded by thermocompression. CONSTITUTION: An anisotropically conductive thermoplastic sheet 3 where discriminating marks 4 that indicate the positions of pad electrodes 11 respectively are applied is arranged on a mounting board 1, and then the discriminating marks 4 applied onto the regions of the anisotropically conductive thermoplastic sheet 3 are aligned with electrodes 21 of a semiconductor chip 2. The semiconductor chip 2 is pressed against the mounting substrate 1, and the thermoplastic 3 is heated, whereby the pad electrodes 11 and the electrodes 21 of the semiconductor chip 2 are bonded together through the intermediary of the conductive thermoplastic ...

PACKAGING METHOD AND APPARATUS OF ELECTRICAL COMPONENT

PROBLEM TO BE SOLVED: To provide a packaging apparatus of electrical components capable of greatly reducing the amount of warpage in the electrical components owing to thermo compression bonding by a non-conductive adhesive that does not include any conductive particles and has low melt viscosity, when packaging electrical components having thicknesses of not larger than 200 μm to a wiring board. SOLUTION: In the packaging apparatus, a non-conductive adhesive film 300 having a minimum melt viscosity of not higher than 1.0×103 Pa s is placed on a wiring board 100 placed on a substrate 11, and an IC chip 200 having a thickness of not larger than 200 μm is placed on the non-conductive adhesive film 300. In the packaging apparatus, the IC chip 200 is pressed by a thermo compression head 12 having a thermo compression bonding section 14 formed of an elastomer having a rubber hardness of not higher than 60, and the IC chip 200 is thermally compressed to the wiring board 100. COPYRIGHT: (C)2009 ...

СПОСОБ И УСТРОЙСТВО ДЛЯ ВЫПУСКА ФИКСИРОВАННОГО КОЛИЧЕСТВА ЖИДКОСТИ

Способ выпуска фиксированного количества жидкости использует устройство, обеспеченное: декомпрессионным клапаном для уменьшения давления сжатого газа, подаваемого источником сжатого газа; выпускным клапаном для управления скоростью потока газа, декомпрессированного в декомпрессионном клапане; хранящим жидкость резервуаром для выпуска жидкости из сопла посредством силы давления газа, подаваемого через выпускной клапан; и буферной емкостью, расположенной между декомпрессионным клапаном и выпускным клапаном, которая имеет объем, который больше объема хранящего жидкость резервуара. Способ и устройство для выпуска фиксированного количества жидкости характеризуются подавлением уменьшения давления, которое возникает в пути потока для подачи сжатого газа в указанный хранящий жидкость резервуар во время работы указанного декомпрессионного клапана за счет увеличения сопротивления потоку в пути потока, который соединяет указанную буферную емкость с указанным резервуаром хранения так, чтобы быть больше ...

Active energy ray-curable pressure-sensitive adhesive for re-release and dicing die-bonding film

Provided is an active energy ray-curable pressure-sensitive adhesive for re-release, which has a small influence on an environment or a human body, can be easily handled, can largely change its pressure-sensitive adhesiveness before and after irradiation with an active energy ray, and can express high pressure-sensitive adhesiveness before the irradiation with the active energy ray and express high releasability after the irradiation with the active energy ray. The active energy ray-curable pressure-sensitive adhesive for re-release includes an active energy ray-curable polymer (P), in which the polymer (P) includes one of a polymer obtained by causing a carboxyl group-containing polymer (P3) and an oxazoline group-containing monomer (m3) to react with each other, and a polymer obtained by causing an oxazoline group-containing polymer (P4) and a carboxyl group-containing monomer (m2) to react with each other.

Power semiconductor module and fabrication method

A power semiconductor module includes: an interconnect layer including an electrical conductor patterned on a dielectric layer, the electrical conductor including a power coupling portion having a thickness sufficient to carry power currents and a control coupling portion having a thickness thinner than that of the power coupling portion; and a semiconductor power device physically coupled to the interconnect layer and electrically coupled to the power coupling portion of the electrical conductor.

Stacked semiconductor package and method of fabricating the same

A stacked semiconductor package and an electronic system, the stacked semiconductor package including a plurality of semiconductor chips, a set of the semiconductor chips being stacked such that an extension region of a top surface of each semiconductor chip of the set extends beyond an end of a semiconductor chip stacked thereon to form a plurality of extension regions; and a plurality of protection layers on the extension regions and on an uppermost semiconductor chip of the plurality of semiconductor chips.

Laminated semiconductor substrate, laminated chip package and method of manufacturing the same

In a laminated semiconductor substrate, a plurality of semiconductor substrates are laminated. Each of the semiconductor substrate has a plurality of scribe-groove parts formed along scribe lines. Further, each of the semiconductor substrate has a plurality of device regions insulated from each other and has a semiconductor device formed therein. Further, an uppermost substrate and a lowermost substrate have an electromagnetic shielding layer formed using a ferromagnetic body. The electromagnetic shielding layer is formed in a shielding region except the extending zone. The extending zone is set a part which the wiring electrode crosses, in a peripheral edge part of the device region.

Chip package and fabricating method thereof

A chip package and a fabrication method thereof are provided. The chip package includes a substrate and a chip disposed over the substrate. A solder layer is disposed between the chip and the substrate. A conductive pad is disposed between the solder layer and the substrate, wherein the conductive pad includes a first portion disposed under the solder layer, a second portion disposed away from the first portion and a connective portion disposed between the first portion and the second portion. The connective portion has a width which is narrower than a width of the first portion along a first direction perpendicular to a second direction extending from the first portion to the connective portion.

Power Semiconductor Module, Method for Producing a Power Semiconductor Module and a Housing Element for a Power Semiconductor Module

A power semiconductor module includes a housing element into which one or more connecting lugs are inserted. Each connecting lug has a foot region on the topside of which one or more bonding connections can be produced. In order to fix the foot regions, press-on elements are provided, which press against the end of the connecting lug.

Method and electrostatic transfer stamp for transferring semiconductor dice using electrostatic transfer printing techniques

A transfer stamp that can be charged with a spatial pattern of electrostatic charge for picking up selected semiconductor dice from a host substrate and transferring them to a target substrate. The stamp may be bulk charged and then selectively discharged using irradiation through a patterned mask. The technique may also be used to electrostatically transfer selected semiconductor dice from a host substrate to a target substrate.

Semiconductor device and method for producing such a device

A semiconductor device and method for producing such a device is disclosed. One embodiment provides a semiconductor functional wafer having a first and second main surface. Component production processes are performed for producing a component functional region at the first main surface, wherein the component production processes produce an end state that is stable up to at least a first temperature. A carrier substrate is fitted to the first main surface. Access openings are produced to the first main surface. At least one further component production process is performed for producing patterned component functional regions at the first main surface of the functional wafer in the access openings. The end state produced in this process is stable up to a second temperature, which is less than the first temperature.

Method for molecular adhesion bonding at low pressure

The present invention relates to a method for molecular adhesion bonding between at least a first wafer and a second wafer involving aligning the first and second wafers, placing the first and second wafers in an environment having a first pressure (P 1 ) greater than a predetermined threshold pressure; bringing the first wafer and the second wafer into alignment and contact; and initiating the propagation of a bonding wave between the first and second wafer after the wafers are aligned and in contact by reducing the pressure within the environment to a second pressure (P 2 ) below the threshold pressure. The invention also relates to the three-dimensional composite structure that is obtained by the described method of adhesion bonding.

Stitch bump stacking design for overall package size reduction for multiple stack

A method for die stacking is disclosed. In one embodiment a first die is formed overlying a substrate. A first wire is bonded to the first die and to a bond finger of the substrate, wherein the first wire is bonded to the bond finger with a first bond. A first stitch bump is formed overlying the first stitch bond, wherein the first stitch bump is formed from a molten ball of conductive material. A second die is formed overlying the first die. A second wire is bonded to the second die and to the first stitch bump, wherein the second wire is bonded to the first stitch bump with a second bond.

Process for assembling two parts of a circuit

A three-dimensional integrated structure is fabricated by assembling at least two parts together, wherein each part contains at least one metallic line covered with a covering region and having a free side. A cavity is formed in the covering region of each part, that cavity opening onto the metallic line. The two parts are joined together with the free sides facing each other and the cavities in each covering region aligned with each other. The metallic lines are then electrically joined to each other through an electromigration of the metal within at least one of the metallic lines, the electromigrated material filling the aligned cavities.

Power Semiconductor Chip Package

A device includes a vertical power semiconductor chip having an epitaxial layer and a bulk semiconductor layer. A first contact pad is arranged on a first main face of the power semiconductor chip and a second contact pad is arranged on a second main face of the power semiconductor chip opposite to the first main face. The device further comprises an electrically conducting carrier attached to the second contact pad.

Semiconductor device and manufacturing method of the same

A semiconductor chip is mounted on a heat sink disposed inside a through-hole of a wiring board, electrodes of the semiconductor chip and connecting terminals of the wiring board are connected by bonding wires, a sealing resin is formed to cover the semiconductor chip and the bonding wires, and solder balls are formed on the lower surface of the wiring board, thereby constituting the semiconductor device. The heat sink is thicker than the wiring board. The heat sink has a protruded portion protruding to outside from the side surface of the heat sink, the protruded portion is located on the upper surface of the wiring board outside the through-hole, and the lower surface of the protruded portion contacts to the upper surface of the wiring board. When the semiconductor device is manufactured, the heat sink is inserted from the upper surface side of the wiring board.

Method of manufacture of integrated circuit packaging system with stacked integrated circuit

A method of manufacture of an integrated circuit packaging system includes: forming a base lead having an outer protrusion and an inner protrusion with a recess in between; forming a stack lead having an elongated portion; mounting a base integrated circuit over the inner protrusion or under the elongated portion; mounting the stack lead over the base lead and the base integrated circuit; connecting a stack integrated circuit and the stack lead with the stack integrated circuit over the base integrated circuit; and encapsulating at least a portion of both the base integrated circuit and the stack integrated circuit with the base lead and the stack lead exposed.

Integrated circuit packaging system with stack interconnect and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: forming a connection carrier having base device pads and base interconnect pads on a carrier top side of the connection carrier; connecting a base integrated circuit to the base device pads and mounted over the carrier top side; mounting base vertical interconnects directly on the base interconnect pads; attaching a base package substrate to the base integrated circuit and directly on the base vertical interconnects; forming a base encapsulation on the base package substrate, the base device pads, and the base interconnect pads; and removing a portion of the connection carrier with the base device pads and the base interconnect pads partially exposed opposite the base package substrate.

Substrate bonding with metal germanium silicon material

In one embodiment, a semiconductor structure including a first substrate, a semiconductor device on the first substrate, a second substrate, and a conductive bond between the first substrate and the second substrate that surrounds the semiconductor device to seal the semiconductor device between the first substrate and the second substrate. The conductive bond comprises metal, silicon, and germanium. A percentage by atomic weight of silicon in the conductive bond is greater than 5%.

Integrated circuit packaging system with warpage control and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit device having chip interconnects; applying an attachment layer directly on the integrated circuit device; attaching a device stiffener to the integrated circuit device with the attachment layer; attaching a chip carrier to the chip interconnects with the device stiffener attached to the integrated circuit device for controlling warpage of the integrated circuit device to prevent the warpage from causing some of the chip interconnects to separate from the chip carrier during attachment of the chip interconnects to the chip carrier; and applying an underfill between the chip carrier and the integrated circuit device for controlling connectivity of all the chip interconnects to the chip carrier.

Semiconductor die package including low stress configuration

A semiconductor die package. The semiconductor die package comprises a semiconductor die and a molded clip structure comprising a clip structure and a first molding material covering at least a portion of the clip structure. The first molding material exposes an outer surface of the clip structure. The clip structure is electrically coupled to the semiconductor die. The semiconductor die package further comprises a leadframe structure comprising a die attach pad and a plurality of leads extending from the die attach pad. The semiconductor die is on the die attach pad of the leadframe structure. A second molding material covers at least a portion of the semiconductor die and the leadframe structure. The semiconductor die package also includes a heat slug and a thermally conductive material coupling the heat slug to the exposed surface of the clip structure.

Package systems and manufacturing methods thereof

A package system includes a first substrate and a second substrate. The second substrate is electrically coupled with the first substrate. The second substrate includes at least one first opening. At least one electrical bonding material is disposed between the first substrate and the second substrate. A first portion of the at least one electrical bonding material is at least partially filled in the at least one first opening.

Package systems and manufacturing methods thereof

A package system includes a first substrate. A second substrate is electrically coupled with the first substrate. At least one electrical bonding material is disposed between the first substrate and the second substrate. The at least one electrical bonding material includes a eutectic bonding material. The eutectic bonding material includes a metallic material and a semiconductor material. The metallic material is disposed adjacent to a surface of the first substrate. The metallic material includes a first pad and at least one first guard ring around the first pad.

Semiconductor chip assembly with bump/base/ledge heat spreader, dual adhesives and cavity in bump

A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and dual adhesives. The heat spreader includes a bump, a base and a ledge. The conductive trace includes a pad and a terminal. The semiconductor device is mounted on the bump in a cavity in the bump, is electrically connected to the conductive trace and is thermally connected to the heat spreader. The bump extends into an opening in the first adhesive and is aligned with and spaced from an opening in the second adhesive. The base and the ledge extend laterally from the bump. The first adhesive is sandwiched between the base and the ledge, the second adhesive is sandwiched between the conductive trace and the ledge and the ledge is sandwiched between the adhesives. The conductive trace is located outside the cavity and provides signal routing between the pad and the terminal.

Method of die bonding onto dispensed adhesives

A method of bonding semiconductor dice onto a substrate first uses an optical assembly to perform pattern recognition of a die bonding section of the substrate in which multiple die pads are located so as to identify positions of the multiple die pads simultaneously during such pattern recognition step. After pattern recognition of the said die bonding section, an adhesive is dispensed with an adhesive dispenser onto at least one of the die pads located in the die bonding section. While the adhesive dispenser is dispensing the adhesive to further die pads located in the die bonding section, a pick-and-place arm concurrently bonds a die onto each die pad where the adhesive has already been dispensed.

Semiconductor package device with a heat dissipation structure and the packaging method thereof

The present invention provide a heat dissipation structure on the active surface of the die to increase the performance of the heat conduction in longitude direction of the semiconductor package device, so that the heat dissipating performance can be improved when the semiconductor package device is associated with the exterior heat dissipation mechanism.

Method for manufacturing semiconductor device

In QFN packages for vehicles which are required to have high reliability, the side surface of leads is mostly covered with lead-to-lead resin protrusions, which prevent smooth formation of solder fillets during reflow mounting. When the lead-to-lead protrusions are mechanically removed using a punching die, there is a high possibility of causing cracks of the main body of the package or terminal deformation. When a spacing is provided between the punching die and the main body of the package in order to avoid such damages, a resin residue is produced to hinder complete removal of this lead-to-lead resin protrusion. The present invention provides a method for manufacturing semiconductor device of a QFN type package using multiple leadframes having a dam bar for tying external end portions of a plurality of leads. This method includes a step of removing a sealing resin filled between the circumference of a mold cavity and the dam bar by using laser and then carrying out surface treatment, for example, solder plating.

Electronic element unit and reinforcing adhesive agent

It is an object of the present invention to provide an electronic element unit and a reinforcing adhesive agent in which a bonding strength can be improved between an electronic element and a circuit board and a repairing work can be carried out without giving a thermal damage to the electronic element or the circuit board. In an electronic element unit ( 1 ) including an electronic element ( 2 ) having a plurality of connecting terminals ( 12 ) on a lower surface thereof, a circuit board ( 3 ) having a plurality of electrodes ( 22 ) corresponding to the connecting terminals ( 12 ) on an upper surface thereof. The connecting terminals ( 12 ) and the electrodes ( 22 ) are connected by solder bumps ( 23 ), and the electronic element ( 2 ) and the circuit board ( 3 ) are partly bond by a resin bond part ( 24 ) made of a thermosetting material of a thermosetting resin, and a metal powder ( 25 ) is included in the resin bond parts ( 24 ) in a dispersed state. The metal powder ( 25 ) has a melting point lower than a temperature at which the resin bond parts ( 24 ) are heated when a work (a repairing work) is carried out for removing the electronic element ( 2 ) from the circuit board ( 3 ).

Connecting and Bonding Adjacent Layers with Nanostructures

An apparatus, comprising two conductive surfaces or layers and a nanostructure assembly bonded to the two conductive surfaces or layers to create electrical or thermal connections between the two conductive surfaces or layers, and a method of making same.

Copper conductor film and manufacturing method thereof, conductive substrate and manufacturing method thereof, copper conductor wiring and manufacturing method thereof, and treatment solution

Provided are a copper conductor film and manufacturing method thereof, and patterned copper conductor wiring, which have superior conductivity and wiring pattern formation, and with which there is no decrease in insulation between circuits, even at narrow wiring widths and narrow inter-wiring spacing. Disclosed are a copper conductor film and manufacturing method thereof in which a copper-based particle-containing layer, which contains both a metal having catalytic activity toward a reducing agent and copper oxide, is treated using a treatment solution that contains a reagent that ionizes or complexes copper oxide and a reducing agent that reduces copper ions or copper complex to form metallic copper in a single solution, and patterned copper conductor wiring that is obtained by patterning a copper-based particle-containing layer using printing and by said patterned particle-containing layer being treated by a treatment method using a solution that contains both a reagent that ionizes or complexes copper oxide and a reducing agent that reduces copper ions or copper complexes to form metallic copper in a single solution.

System comprising a semiconductor device and structure

A method of manufacturing a semiconductor device, the method including, providing a first monocrystalline layer including semiconductor regions, overlaying the first monocrystalline layer with an isolation layer, transferring a second monocrystalline layer comprising semiconductor regions to overlay the isolation layer, wherein the first monocrystalline layer and the second monocrystalline layer are formed from substantially different crystal materials; and subsequently etching the second monocrystalline layer as part of forming at least one transistor in the second monocrystalline layer.

Semiconductor Device

The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other.

Bonding pad structure and integrated circuit comprising a plurality of bonding pad structures

A bonding pad structure positioned on an integrated circuit includes a connecting pad, an insulation layer and a gold bump. The connecting pad is formed on the integrated circuit. The insulation layer is formed on the connecting pad, where the insulation layer has only one opening and a shape of the opening includes at least a bend. The gold bump is formed on the insulation layer, where the gold bump is electrically connected to the connecting pad through the opening of the insulation layer.

Semiconductor component, semiconductor wafer component, manufacturing method of semiconductor component, and manufacturing method of joining structure

A semiconductor component of the present invention includes a semiconductor element and a joining layer formed on one surface of the semiconductor element and consisting of a joining material containing Bi as an essential ingredient, and projecting sections are formed on a surface of the joining layer on a side opposite to a surface in contact with the semiconductor element. By joining the semiconductor component to an electrode arranged so as to face the joining layer, the generation of a void can be suppressed.

Chip scale surface mounted semiconductor device package and process of manufacture

A semiconductor device package die and method of manufacture are disclosed. The device package die may comprise a device substrate having one or more front electrodes located on a front surface of the device substrate and electrically connected to one or more corresponding device regions formed within the device substrate proximate the front surface. A back conductive layer is formed on a back surface of the device substrate. The back conductive layer is electrically connected to a device region formed within the device substrate proximate a back surface of the device substrate. One or more conductive extensions are formed on one or more corresponding sidewalls of the device substrate in electrical contact with the back conductive layer, and extend to a portion of the front surface of the device substrate. A support substrate is bonded to the back surface of the device substrate.

Trap Rich Layer for Semiconductor Devices

An integrated circuit chip is formed with an active layer and a trap rich layer. The active layer is formed with an active device layer and a metal interconnect layer. The trap rich layer is formed above the active layer. In some embodiments, the active layer is included in a semiconductor wafer, and the trap rich layer is included in a handle wafer.

Bond package and approach therefor

Lead-free or substantially lead-free structures and related methods are implemented for manufacturing electronic circuits. In accordance with various example embodiments, circuit components are joined using a copper-tin (Cu—Sn) alloy, which is melted and used to form a Cu—Sn compound having a higher melting point than the Cu—Sn alloy and both physically and electrically coupling circuit components together.

Semiconductor package and method of fabricating the same

A semiconductor package and a method of manufacturing the same, and more particularly, to a package of a power module semiconductor and a method of manufacturing the same. The semiconductor package includes a substrate including a plurality of conductive patterns spaced apart from one another; a plurality of semiconductor chips disposed on the conductive patterns; a connecting member for electrically connecting the conductive patterns to each other, for electrically connecting the semiconductor chips to each other, or for electrically connecting the conductive pattern and the semiconductor chip; and a sealing member for covering the substrate, the semiconductor chips, and the connecting member, wherein a lower surface of the substrate and an upper surface of the connecting member are exposed to the outside by the sealing member.

Substrate bonding method and semiconductor device

A first Sn absorption layer is formed on a principal surface of a first substrate, the first Sn absorption layer being made of metal absorbing Sn from AuSn alloy and lowering a relative proportion of Sn in the AuSn alloy. A second Sn absorption layer is formed on a principal surface of a second substrate, the second Sn absorption layer being made of metal absorbing Sn from AuSn alloy and lowering a relative proportion of Sn in the AuSn alloy. A solder layer made of AuSn alloy is formed at least on one Sn absorption layer of the first and second Sn absorption layers. The first and second substrates are bonded together by melting the solder layer in a state that the first and second substrates are in contact with each other, with the principal surfaces of the first and second substrates facing each other.

Alignment marks to enable 3d integration

Disclosed are a structure including alignment marks and a method of forming alignment marks in three dimensional (3D) structures. The method includes forming apertures in a first surface of a first semiconductor substrate; joining the first surface of the first semiconductor substrate to a first surface of a second semiconductor substrate; thinning the first semiconductor on a second surface of the first semiconductor substrate to provide optical contrast between the apertures and the first semiconductor substrate; and aligning a feature on the second surface of the first semiconductor substrate using the apertures as at least one alignment mark.

Semiconductor Device and Method of Forming Bond Wires and Stud Bumps in Recessed Region of Peripheral Area around the Device for Electrical Interconnection to Other Devices

A semiconductor wafer contains a plurality of semiconductor die each having a peripheral area around the die. A recessed region with angled or vertical sidewall is formed in the peripheral area. A conductive layer is formed in the recessed region. A first stud bump is formed over a contact pad of the semiconductor die. A second stud bump is formed over the first conductive layer within the recessed region. A bond wire is formed between the first and second stud bumps. A third stud bump is formed over the bond wire and first stud bump. A dicing channel partially formed through the peripheral area. The semiconductor wafer undergoes backgrinding to the dicing channel to singulate the semiconductor wafer and separate the semiconductor die. The semiconductor die can be disposed in a semiconductor package with other components and electrically interconnected through the bond wire and stud bumps.

Ohmic connection using widened connection zones in a portable electronic object

The invention relates to portable electronic objects comprising an integrated circuit chip, and a mounting having two connection terminals for a circuit, as well as to a method for manufacturing such objects. The invention is characterized in that the chip is provided, on the active surface thereof, with two widened connection zones, in particular connection plates, said connection plates being positioned opposite said terminals and electrically connected, by ohmic contact, to the latter, and in that the surface defined by the connection plates, at the surface of the active integrated circuit having said plates, is greater than ½ of the surface of said surface. The invention can be used, in particular, for RFID objects.

Semiconductor device and method of fabricating the semiconductor device

A semiconductor device includes a first device including a first substrate and a first external connection terminal for connecting outside the first device; a second device stacked on the first device, the second device including a second substrate and a second external connection terminal for connecting outside the second device; an adhesive pattern disposed between the first device and second device, the adhesive pattern disposed in locations other than locations where the first external connection terminal and second external connection terminal are disposed, and the adhesive pattern causing the first device and second device, when stacked, to be spaced apart by a predetermined distance; and a plated layer disposed between and electrically and physically connecting the first external connection terminal and the second external connection terminal.

Semiconductor device and method for manufacturing semiconductor device

A semiconductor device includes: a support base material, and a semiconductor element bonded to the support base material with a binder, the binder including: a porous metal material that contacts the support base material and the semiconductor element, and a solder that is filled in at least one part of pores of the porous metal material.

Semiconductor apparatus, method for manufacturing the same and electric device

A semiconductor apparatus includes: a semiconductor device including a first electrode; a substrate including a second electrode and a recess; and a heat-dissipating adhesive material to set the semiconductor device in the recess so as to arrange the first electrode close to the second electrode, wherein the first electrode is coupled to the second electrode and the heat-dissipating adhesive material covers a bottom surface and at least part of a side surface of the semiconductor device.

Method of manufacturing film for semiconductor device

The present invention aims to provides a method of manufacturing a film for a semiconductor device in which a dicing film, a die bond film, and a protecting film are laminated in this order, including the steps of: irradiating the die bond film with a light ray having a wavelength of 400 to 800 nm to detect the position of the die bond film based on the obtained light transmittance and punching the dicing film out based on the detected position of the die bond film, and in which T 2 /T 1 is 0.04 or more, wherein T 1 is the light transmittance of the portion where the dicing film and the protecting film are laminated and T 2 is the light transmittance of the portion where the dicing film, the die bond film, and the protecting film are laminated.

Semiconductor apparatus and method for manufacturing the same

According to one embodiment, a semiconductor apparatus includes a semiconductor device, a heat spreader, a regulating unit, a containing unit, and a holding unit. The heat spreader is bonded to the semiconductor device with an interposed solder layer. The regulating unit is configured to regulate a dimension between the semiconductor device and the heat spreader. The containing unit is configured to contain melted solder in an interior of the containing unit. The holding unit is configured to allow melted solder held in an interior of the holding unit. The holding unit is configured to replenish the melted solder in the case where an amount of the melted solder contained in the containing unit is insufficient. The holding unit is configured to recover the melted solder in the case where the amount of the melted solder contained in the containing unit is excessive.

Anisotropic conductive film, joined structure, and connecting method

To provide an anisotropic conductive film, which contains: an electric conductive layer containing Ni particles, metal-coated resin particles, a binder, a polymerizable monomer, and a curing agent; and an insulating layer containing a binder, a monofunctional polymerizable monomer, and a curing agent, wherein the metal-coated resin particles are resin particles each containing a resin core coated at least with Ni.

Chip package and manufacturing method thereof

An embodiment of the invention provides a manufacturing method of a chip package including: providing a semiconductor wafer having a plurality of device regions separated by a plurality of scribe lines; bonding a package substrate to the semiconductor wafer wherein a spacer layer is disposed therebetween and defines a plurality of cavities respectively exposing the device regions and the spacer layer has a plurality of through holes neighboring the edge of the semiconductor wafer; filling an adhesive material in the through holes wherein the material of the spacer layer is adhesive and different from the adhesive material; and dicing the semiconductor wafer, the package substrate and the spacer layer along the scribe lines to form a plurality of chip packages separated from each other.

Bridging arrangement and method for manufacturing a bridging arrangement

A bridging arrangement for coupling a first terminal to a second terminal includes a plurality of particles of a first type forming at least one path between the first terminal and the second terminal, wherein the particles of the first type are attached to each other; a plurality of particles of a second type arranged in a vicinity of a contact region between a first particle of the first type and a second particle of the first type, wherein at least a portion of the plurality of particles of the second type is attached to the first particle of the first type and the second particle of the first type.

Semiconductor device

A semiconductor device in which the wiring resistance and parasitic inductance of a semiconductor package configuring a power semiconductor module is reduced. In the semiconductor device, a semiconductor chip with an IGBT formed therein and a diode chip are mounted over the upper surface of a die pad. An emitter pad of the semiconductor chip and an anode pad of the diode chip are coupled with a lead by an Al wire. One end of the lead is located in a higher position than the upper surface of the die pad in order to shorten the length of the Al wire for coupling the emitter pad and the lead.

Die attach film

Provided are a die attach film, a semiconductor wafer, and a semiconductor packaging method. The die attach film can prevent generation of burrs or scattering of chips in a dicing process, and exhibits excellent expandability and pick-up characteristics in a die pressure-sensitive adhesive process. Further, the die attach film can prevent release, shifting, or deflection of a chip in a wire pressure-sensitive adhesive or molding process. Thus, it is possible to improve embeddability, inhibit warpage of a wafer or wiring substrate, and enhance productivity in a semiconductor packaging process.

Heating apparatus and implemented body manufacturing method

To improve the tact time of a heating apparatus, provided is a heating apparatus comprising a first pressing member that heats a heating target; a second pressing member that includes an elastic body, and sandwiches the heating target between the first pressing member and the elastic body; and a floating jig that thermally separates the first pressing member from the heating target, holds the heating target between the first pressing member and the second pressing member, and when one of the first pressing member and the second pressing member presses the heating target toward the other of the first pressing member and the second pressing member, thermally connects the heating target and the first pressing member.

Method of manufacturing chip-stacked semiconductor package

A method of manufacturing a chip-stacked semiconductor package, the method including preparing a base wafer including a plurality of first chips each having a through-silicon via (TSV); bonding the base wafer including the plurality of first chips to a supporting carrier; preparing a plurality of second chips; forming stacked chips by bonding the plurality of second chips to the plurality of first chips; sealing the stacked chips with a sealing portion; and separating the stacked chips from each other.

Solar cell assembly ii

The present invention relates to a solar cell assembly that includes a solar cell attached to a bonding pad and a cooling substrate, wherein the bonding pad is attached to a surface of the cooling substrate by a thermally conductive adhesive and electrically contacted to the bonding pad and cooling substrate by a bonding wire. Alternatively, the bonding pad is attached to a surface of the cooling substrate by a thermally and electrically conductive adhesive.

Method for Making Solder-top Enhanced Semiconductor Device of Low Parasitic Packaging Impedance

A solder-top enhanced semiconductor device is proposed for packaging. The solder-top device includes a device die with a top metal layer patterned into contact zones and contact enhancement zones. At least one contact zone is electrically connected to at least one contact enhancement zone. Atop each contact enhancement zone is a solder layer for an increased composite thickness thus lowered parasitic impedance. Where the top metal material can not form a uniform good electrical bond with the solder material, the device die further includes an intermediary layer sandwiched between and forming a uniform electrical bond with the top metal layer and the solder layer. A method for making the solder-top device includes lithographically patterning the top metal layer into the contact zones and the contact enhancement zones; then forming a solder layer atop each of the contact enhancement zones using a stencil process for an increased composite thickness.

Methods and structures for forming integrated semiconductor structures

The invention provides methods and structures for fabricating a semiconductor structure and particularly for forming a semiconductor structure with improved planarity for achieving a bonded semiconductor structure comprising a processed semiconductor structure and a number of bonded semiconductor layers. Methods for forming semiconductor structures include forming a dielectric layer over a non-planar surface of a processed semiconductor structure, planarizing a surface of the dielectric layer on a side thereof opposite the processed semiconductor structure, and attaching a semiconductor structure to the planarized surface of the dielectric layer. Semiconductor structures include a dielectric layer overlaying a non-planar surface of a processed semiconductor structure, and a masking layer overlaying the dielectric layer on a side thereof opposite the processed semiconductor structure. The masking layer includes a plurality of mask openings over conductive regions of the non-planar surface of the processed semiconductor structure.

Method for Producing a Metal Layer on a Substrate and Device

A method produces a metal layer on a semiconductor substrate. A metal layer is produced on the semiconductor substrate by depositing metal particles. The metal particles include cores made of a first metal material and shells surrounding the cores. The shells are made of a second metal material that is resistant to oxidation.

Apparatus for restricting moisture ingress

Apparatus and methods to protect circuitry from moisture ingress, e.g., using a metallic structure as part of a moisture ingress barrier.

Layered chip package and method of manufacturing same

A layered chip package includes a main body and wiring. The main body includes: a main part having a top surface and a bottom surface and including three or more layer portions stacked on one another; a plurality of first terminals disposed on the top surface of the main part; and a plurality of second terminals disposed on the bottom surface of the main part. Each layer portion includes a semiconductor chip having first and second surfaces, and a plurality of electrodes electrically connected to the wiring. The plurality of electrodes are disposed on a side of the first surface of the semiconductor chip. A first layer portion located closest to the top surface of the main part and a second layer portion located closest to the bottom surface of the main part are arranged so that the second surfaces of their respective semiconductor chips face toward each other. The plurality of first terminals are formed by using the plurality of electrodes of the first layer portion. The plurality of second terminals are formed by using the plurality of electrodes of the second layer portion.

Method for producing reconstituted wafers and method for producing semiconductor devices

In order to provide a method for producing semiconductor devices that can use the highly productive W to W method, and achieve a high yield, a method for producing semiconductor devices comprises a step (S 401 ) in which a reconstituted wafer is prepared by replacing defective chips with non-defective chips, a step (S 403 ) in which the reconstituted wafer and the base wafer are connected to one another by laminating, a step (S 406 ) in which through-electrodes are formed in the reconstituted wafer, and a step (S 409 ) in which a separate reconstituted wafer is laminated onto and connected to the reconstituted wafer having through-electrodes.

Semiconductor module manufacturing method, semiconductor module, and manufacturing device

In the disclosed method for manufacturing a semiconductor module, a metal layer and a cooler, which have different coefficients of thermal expansion from each other, are joined into a single unit via an insulating resin sheet. A work, comprising a semiconductor element placed on the metal layer with solder interposed therebetween, is fed into a reflow furnace. The work, in that state, is heated in the reflow furnace, thereby mounting the semiconductor element to the metal layer. The heating is carried out such that the temperature of the cooler and the temperature of the metal layer differ by an amount that make the cooler and the metal layer undergo the same amount of thermal expansion as each other.

Hermetically sealed wafer packages

Hermetically sealed semiconductor wafer packages that include a first bond ring on a first wafer facing a complementary surface of a second bond ring on a second wafer. The package includes first and second standoffs of a first material, having a first thickness, formed on a surface of the first bond ring. The package also includes a eutectic alloy (does not have to be eutectic, typically it will be an alloy not specific to the eutectic ratio of the elements) formed from a second material and the first material to create a hermetic seal between the first and second wafer, the eutectic alloy formed by heating the first and second wafers to a temperature above a reflow temperature of the second material and below a reflow temperature of the first material, wherein the eutectic alloy fills a volume between the first and second standoffs and the first and second bond rings, and wherein the standoffs maintain a prespecified distance between the first bond ring and the second bond ring.

Dc/dc convertor power module package incorporating a stacked controller and construction methodology

Methods and systems are described for enabling the efficient fabrication of small form factor power converters and also the small form factor power converter devices.

Fabrication method of semiconductor integrated circuit device

Productivity is to be improved in assembling a semiconductor integrated circuit device. A matrix substrate is provided and semiconductor chips are disposed on a first heating stage, then the matrix substrate is disposed above the semiconductor chips on the first heating stage, subsequently the semiconductor chips and the matrix substrate are bonded to each other temporarily by thermocompression bonding while heating the chips directly by the first heating stage, thereafter the temporarily bonded matrix substrate is disposed on a second heating stage adjacent to the first heating stage, and then on the second heating stage the semiconductor chips are thermocompression-bonded to the matrix substrate while being heated directly by the second heating stage.

Semiconductor device and method for manufacturing same

A dug portion ( 50 ) in which a die-bonding material is filled is provided to a lower surface of a stamping nozzle ( 42 ) used in a step of applying the die-bonding material onto a chip mounting portion of a wiring board. Planar dimensions of the dug portion ( 50 ) are smaller than external dimensions of a chip to be mounted on the chip mounting portion. In addition, a depth of the dug portion ( 50 ) is smaller than a thickness of the chip. When the thickness of the chip is 100 μm or smaller, a problem of crawling up of the die-bonding material to an upper surface of the chip is avoided by applying the die-bonding material onto the chip mounting portion using the stamping nozzle ( 42 ).

Alignment mark, semiconductor having the alignment mark, and fabricating method of the alignment mark

An alignment mark with a sheet or a layer of copper, which is compatible with a copper process, is provided herein. In one embodiment, a whole sheet of copper (Cu) is used as a background of the alignment mark, by which the color of the background of the alignment mark is stable and reliable. By such arrangement, the contrast between colors of a main pattern and the background of the alignment mark can be significantly improved, without considering a problem the homogeneity of manufacturing process. If the alignment mark is applied for manufacturing of a display, a recognition successful rate of alignment to attach an integrated circuit (IC) to a panel of the display is increased.

Three dimensional semiconductor assembly board with bump/flange supporting board, coreless build-up circuitry and built-in electronic device

A semiconductor assembly board includes a supporting board, a coreless build-up circuitry and a built-in electronic device. The supporting board includes a bump, a flange and a via hole in the bump. The built-in electronic device extends into the via hole and is electrically connected to the build-up circuitry. The build-up circuitry extends from the flange and the built-in electronic device and provides signal routing for the built-in electronic device. The supporting board provides mechanical support, ground/power plane and heat sink for the coreless build-up circuitry.

Package-on-package structures

Embodiments of the present disclosure provide a package on package arrangement comprising a bottom package and a second package. The first package includes a substrate layer including (i) a top side and (ii) a bottom side that is opposite to the top side. Further, the top side defines a substantially flat surface. The first package also includes a die coupled to the bottom side of the substrate layer. The second package includes a plurality of rows of solder balls, and the second package is attached to the substantially flat surface of the substrate layer via the plurality of rows of solder balls.

Method for manufacturing semiconductor device and semiconductor device

According to one embodiment, between the mounting substrate and the semiconductor chip, there is a joint support layer including a metal or its alloy selected from the group of Cu, Al, Ag, Ni, Cr, Zr and Ti and a melt layer laminated across the joint support layer, and formed of a metal selected from the group of Sn, Zn and In or of an alloy of at least two metals selected from the same metals. The process of joining the mounting substrate and the semiconductor chip includes intervening a joining layer which is formed, at least for its outermost layer, by the melt layer, maintaining the temperature to be higher than the melting point of the melt layer, then forming an alloy layer which has a higher melting point than the melt layer by liquid phase diffusion.

Semiconductor laser mounting with intact diffusion barrier layer

A first contact surface of a semiconductor laser chip can be formed to a target surface roughness selected to have a maximum peak to valley height that is substantially smaller than a barrier layer thickness. A barrier layer that includes a non-metallic, electrically-conducting compound and that has the barrier layer thickness can be applied to the first contact surface, and the semiconductor laser chip can be soldered to a carrier mounting along the first contact surface using a solder composition by heating the soldering composition to less than a threshold temperature at which dissolution of the barrier layer into the soldering composition occurs. Related systems, methods, articles of manufacture, and the like are also described.

Power Module and Power Converter Containing Power Module

A power module includes a semiconductor chip, a first coupling conductor with one main surface coupled to one main surface of the semiconductor chip, a second coupling conductor with one main surface coupled to the other main surface of the semiconductor chip, a coupling terminal supplied with electrical power from the direct current power source, and resin material to seal the semiconductor chip, and in which the resin member has a protruding section that protrudes from the space where the first and second coupling conductors are formed opposite each other, and the coupling terminal is clamped on the protruding section, and at least one of the first or second coupling conductors is coupled to a coupling terminal by way of a metallic material that melts at a specified temperature.

Semiconductor device including cladded base plate

A semiconductor device includes a semiconductor chip coupled to a substrate and a base plate coupled to the substrate. The base plate includes a first metal layer clad to a second metal layer. The second metal layer is deformed to provide a pin-fin or fin cooling structure.

Paste and method for connecting electronic component to substrate

A paste may be used to connect at least one electronic component to at least one substrate through contact regions, wherein at least one of the contact regions contains a non-noble metal. The paste contains (a) metal particles, (b) at least one activator that bears at least two carboxylic acid units in the molecule, and (c) a dispersion medium. A method for connecting at least one electronic component to at least one substrate through the contact regions includes steps of providing a substrate having a first contact region and an electronic component having a second contact region; providing the above paste; generating a structure, wherein the first contact region of the substrate contacts the second contact region of the electronic component through the paste; and sintering the structure while producing a module including at least the substrate and the electronic component connected to each other through the sintered paste.

Curable Amine, Carboxylic Acid Flux Composition And Method Of Soldering

A curable flux composition is provided, comprising, as initial components: a resin component having at least two oxirane groups per molecule; a carboxylic acid; and, an amine fluxing agent represented by formula I: and, optionally, a curing agent. Also provided is a method of soldering an electrical contact using the curable flux composition.

Power semiconductor arrangement and method for producing a power semiconductor arrangement

In a method for producing a power semiconductor arrangement, an insulation carrier with a top side, a metallization, and a contact pin with a first end are provided. The metallization is attached to the top side and a target section of the metallization is determined. After the metallization is attached to the top side of the insulation carrier, the first end of the contact pin is pressed into the target section such that the first end is inserted in the target section. Thereby, an interference fit and an electrical connection are established between the first end of the contact pin and the target section of the metallization.

Power management applications of interconnect substrates

Various applications of interconnect substrates in power management systems are described.

Semiconductor device, electronic device, and semiconductor device manufacturing method

A semiconductor device, includes: a connection member including a first pad formed on a principal surface thereof; a semiconductor chip including a circuit-formed surface on witch a second pad is formed, the chip mounted on the connection member so that the circuit-formed surface faces the principal surface; and a solder bump that connects the first and second pads and is made of metal containing Bi and Sn, wherein the bump includes a first interface-layer formed adjacent to the second pad, a second interface-layer formed adjacent to the first pad, a first intermediate region formed adjacent to either one of the interface-layers, and a second intermediate region formed adjacent to the other one of the interface-layers and formed adjacent to the first intermediate region; Bi-concentration in the first intermediate region is higher than a Sn-concentration; and a Sn-concentration in the second intermediate region is higher than a Bi-concentration.

Multilayer adhesive sheet and method for manufacturing electronic component

Provided is a multilayer adhesive sheet which enables easy separation between an adhesive layer and a die attach film during the pick-up even in cases where an acrylate ester copolymer is used in the die attach film, thereby making the pick-up work of semiconductor chips after the dicing easy. The multilayer adhesive sheet comprises a base film, an adhesive layer that is disposed on one surface of the base film, and a die attach film that is disposed on an exposed surface of the adhesive layer. The adhesive that constitutes the adhesive layer contains: (A) a (meth)acrylate ester copolymer; (B) an ultraviolet polymerizable compound; (C) a multifunctional isocyanate curing agent; (D) a photopolymerization initiator; and (E) a silicone polymer.

Top-side Cooled Semiconductor Package with Stacked Interconnection Plates and Method

A top-side cooled semiconductor package with stacked interconnection plate is disclosed. The semiconductor package includes a circuit substrate with terminal leads, a semiconductor die atop the circuit substrate, a low thermal resistance intimate interconnection plate for bonding and interconnecting a top contact area of the semiconductor die with the circuit substrate, a low thermal resistance stacked interconnection plate atop the intimate interconnection plate for top-side cooling, a molding encapsulant for encapsulating the package except for exposing a top surface of the stacked interconnection plate to maintain effective top-side cooling. The top portion of the stacked interconnection plate can include a peripheral overhang above the intimate interconnection plate. The peripheral overhang allows for a maximized exposed top surface area for heat dissipation independent of otherwise areal constraints applicable to the intimate interconnection plate. The stacked interconnection plate can be partially etched or three dimensionally formed to create the peripheral overhang.

Semiconductor Device and Method of Forming Interposer Frame Over Semiconductor Die to Provide Vertical Interconnect

A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame. The interposer is mounted over the carrier and first die with the conductive pillars disposed around the die. A cavity can be formed in the interposer frame to contain a portion of the first die. An encapsulant is deposited through the opening in the interposer frame over the carrier and first die. Alternatively, the encapsulant is deposited over the carrier and first die and the interposer frame is pressed against the encapsulant. Excess encapsulant exits through the opening in the interposer frame. The carrier is removed. An interconnect structure is formed over the encapsulant and first die. A second semiconductor die can be mounted over the first die or over the interposer frame.

Miniaturized Electrical Component Comprising an MEMS and an ASIC and Production Method

The invention relates to a miniaturized electrical component comprising an MEMS chip and an ASIC chip. The MEMS chip and the ASIC chip are disposed on top of each other; an internal mounting of MEMS chip and ASIC chip is connected to external electrical terminals of the electrical component by means of vias through the MEMS chip or the ASIC chip.

Connecting material, method for manufacturing connecting material and semiconductor device

In a connecting material of the present invention, a Zn series alloy layer is formed on an outermost surface of an Al series alloy layer. In particular, in the connecting material, an Al content of the Al series alloy layer is 99 to 100 wt.% or a Zn content of the Zn series alloy layer is 90 to 100 wt.%. By using this connecting material, the formation of an Al oxide film on the surface of the connecting material at the time of the connection can be suppressed, and preferable wetness that cannot be obtained with the Zn—Al alloy can be obtained. Further, a high connection reliability can be achieved when an Al series alloy layer is left after the connection, since the soft Al thereof functions as a stress buffer material.

Semiconductor device and manufacturing method therefor

A semiconductor device includes a substrate having a main surface and a back surface opposite to the main surface, a first semiconductor chip having an upper surface and a lower surface opposite to the first surface with a side surface provided therebetween, the first semiconductor chip being mounted on the main surface of the substrate, a plurality of bumps provided between the main surface of the substrate and the lower surface of the first semiconductor chip, a second semiconductor chip having an upper surface and a lower surface opposite to the first surface with a side surface provided therebetween, the second semiconductor chip being mounted on the upper surface of the first semiconductor chip such that the side surface of the second semiconductor chip is positioned outward from the side surface of the first semiconductor chip.

Power Converter Device

A power converter device includes first through third semiconductor modules provided for phases of a three-phase inverter circuit, and incorporating upper and lower arms series circuit, and a flow path forming cabinet in a rectangular prism shape having an electric equipment containing space and a coolant flow path formed to surround the electric equipment containing space, the coolant flow path includes a first flow path provided along a first side face of the flow path forming cabinet, a second flow path provided along a second side face contiguous to one side of the first side face and connected to one end of the first flow path, and a third flow path provided along a third side face contiguous to other side of the first side face and connected to other end of the first flow path.

Manufacturing method for semiconductor integrated device

In a chip pick-up process after dicing in an assembly process during manufacture of a semiconductor integrated circuit device it is an important subject to diminish a pick-up defect caused by the reduction in thickness of each chip which is proceeding in quick tempo. Particularly, bending of the chip peripheral portion caused by a peeling operation is very likely to induce cracking and chipping of the chip. In the present invention, to solve these problems, in case of peeling a chip from a dicing tape (adhesive tape) or the like while vacuum-chucking the chip by a chucking collet, the flow rate of a vacuum chucking system in the chucking collet is monitored to check a bent state of the chip before complete separation of the first chip from the adhesive tape.

Electronic Device and a Method for Fabricating an Electronic Device

The electronic device includes a carrier, a semiconductor substrate attached to the carrier, and a layer system disposed between the semiconductor substrate and the carrier. The layer system includes an electrical contact layer disposed on the semiconductor substrate. A functional layer is disposed on the electrical contact layer. An adhesion layer is disposed on the functional layer. A solder layer is disposed between the adhesion layer and the carrier.

Solderable Contact and Passivation for Semiconductor Dies

A silver-containing solderable contact on a semiconductor die has its outer edge spaced from the confronting edge of an epoxy passivation layer so that, after soldering, silver ions are not present and are not therefor free to migrate under the epoxy layer to form dendrites.

Power module for electric power steering and electric power steering drive control apparatus using the same

An object is to release heat efficiently to heat-resistance abilities of individual components by enhancing a heat-radiation performance of power circuit components forming a power module ( 100 ) and by enhancing a heat generation balance. The power circuit components formed of power switching elements ( 107 and 108 ) forming a bridge circuit and a motor relay switching element ( 109 ) are mounted on conductive members ( 102 ) while a heat generation balance is maintained. Then, the conductive members ( 102 ) are disposed on a heat-releasing heat sink ( 30 ) by abutment, and the power circuit components and the heat sink ( 30 ) are integrally molded using mold resin ( 101 ).

Method for Forming a Reliable Solderable Contact

A silver-containing solderable contact on a semiconductor die has its outer edge spaced from the confronting edge of an epoxy passivation layer so that, after soldering, silver ions are not present and are not therefor free to migrate under the epoxy layer to form dendrites.

Semiconductor device

The reliability of a semiconductor device is improved. A package of a semiconductor device internally includes a first semiconductor chip and a second semiconductor chip in which power MOS•FETs are formed and a third semiconductor chip in which a control circuit controlling the first and second semiconductor chips is formed. The first to third semiconductor chips are mounted on die pads respectively. Source electrode bonding pads of the first semiconductor chip on a high side are electrically connected with a first die pad of the die pads via a metal plate. On a top surface of the die pad 7 D 2 , a plated layer formed in a region where the second semiconductor chip is mounted, and another plated layer formed in a region where the metal plate is joined are provided and the plated layers are separated each other with a region where no plated layer is formed in between.

Semiconductor package, packaging substrate and fabrication method thereof

A packaging substrate and a semiconductor package using the packaging substrate are provided. The packaging substrate includes: a substrate body having a die attach area, a circuit layer formed around the die attach area and having a plurality of conductive traces each having a wire bonding pad, and a surface treatment layer formed on the wire bonding pads. Therein, only one of the conductive traces is connected to an electroplating line so as to prevent cross-talk that otherwise occurs between conductive traces due to too many electroplating lines in the prior art.

Group III-V and Group IV Composite Diode

In one implementation, a group III-V and group IV composite diode includes a group IV diode in a lower active die, the group IV diode having an anode situated on a bottom side of the lower active die. The group III-V and group IV composite diode also includes a group III-V transistor in an upper active die stacked over the lower active die, the group III-V transistor having a drain, a source, and a gate situated on a top side of the upper active die. The source of the group III-V transistor is electrically coupled to a cathode of the group IV diode using a through-semiconductor via (TSV) of the upper active die.

DC/DC Converter Power Module Package Incorporating a Stacked Controller and Construction Methodology

Methods and systems are described for enabling the efficient fabrication of small form factor power converters and also the small form factor power converter devices.

Metal bonding method and metal bonded structure

The gap between first and second bonding portions is filled with a disperse solution obtained by dispersing copper micro-particles into a solution for copper oxide elution, so as to elute copper oxide configured as the outermost layer of the first bonding portion and copper oxide configured as the outermost layer of the second bonding portion, and copper oxide formed on the surface of each copper micro-particle. Pressure is applied to the first and second bonding portions using a press machine so as to raise the pressure of the disperse solution. At the same time, heat is applied under a relatively low temperature condition of 200° C. to 300° C., so as to remove the components contained in the disperse solution except for copper, thereby depositing copper. Thus, a first base portion and a second base portion are bonded via a copper bonded portion containing copper derived from the copper micro-particles.

Starting material for a sintered bond and process for producing the sintered bond

The invention relates to a starter material for a sintering compound, said starter material comprising first particles of at least one metal having a first coating which is applied to the first particles and consists of an organic material, and second particles which contain an organic metal compound and/or a precious metal oxide, the organic metal compound and/or the precious metal oxide being converted during heat treatment of the starter material into the fundamental elemental metal and/or precious metal. The invention is characterized in that the second particles have a core of at least one metal and a second coating which is applied to the core and contains the organic metal compound and/or precious metal oxide. Furthermore, the first coating contains a reducing agent by means of which the organic metal compound and/or the precious metal oxide is/are reduced to the elemental metal and/or precious metal at a temperature below the sintering temperature of the elemental metal and/or precious metal.

Flip-chip packaging techniques and configurations

Embodiments of the present disclosure flip-chip packaging techniques and configurations. An apparatus may include a package substrate having a plurality of pads formed on the package substrate, the plurality of pads being configured to receive a corresponding plurality of interconnect structures formed on a die and a fluxing underfill material disposed on the package substrate, the fluxing underfill material comprising a fluxing agent configured to facilitate formation of solder bonds between individual interconnect structures of the plurality of interconnect structures and individual pads of the plurality of pads and an epoxy material configured to harden during formation of the solder bonds to mechanically strengthen the solder bonds. Other embodiments may also be described and/or claimed.

Device and Method for Chip Pressing

Disclosed are embodiments related to chip pressing devices. One such chip pressing device includes a bottom portion and a top portion, which is configured to be attached to or separated from the bottom portion, and has a compartment portion, an upper chamber, and a lower chamber, wherein the upper chamber is spaced apart from the lower chamber by the compartment portion. The upper chamber has one or more gas passages, the lower chamber has one or more gas inlets and one or more gas outlets, and the compartment portion has one or more through-holes. One or more pressing heads movably fit into the through-holes; one or more gas pressure sources connected to at least one of the gas passages of the upper chamber, wherein the upper chamber is pressurized, and one or more heated gas sources are connected to the one or more gas inlets of the lower chamber.

Manufacturing method of semiconductor device

A manufacturing yield of a semiconductor device including a power transistor is improved. When forming a tip portion LE 1 c of a first lead, a tip portion LE 2 c of a second lead, and a tip portion LE 3 c of a third lead by using a spanking die SDM 1 , the tip portion LE 1 c of the first lead, the tip portion LE 2 c of the second lead, and the tip portion LE 3 c of the third lead are pressed by an upper surface of a protrusion portion provided on a pressing surface of a lower die SD 1 and a bottom surface of a groove portion provided in a pressing surface of an upper die SU 1 , and a bent portion of the second lead and a bent portion of the third lead are pressed by a flat pressing surface of the lower die SD 1 and a flat pressing surface of the upper die SU 1.

Circuit package, an electronic circuit package, and methods for encapsulating an electronic circuit

A circuit package is provided, the circuit package including: an electronic circuit; a metal block next to the electronic circuit; encapsulation material between the electronic circuit and the metal block; a first metal layer structure electrically contacted to at least one first contact on a first side of the electronic circuit; a second metal layer structure electrically contacted to at least one second contact on a second side of the electronic circuit, wherein the second side is opposite to the first side; wherein the metal block is electrically contacted to the first metal layer structure and to the second metal layer structure by means of an electrically conductive medium; and wherein the electrically conductive medium includes a material different from the material of the first and second metal layer structures or has a material structure different from the material of the first and second metal layer structures.

Bonded processed semiconductor structures and carriers

Methods of fabricating semiconductor structures include implanting atom species into a carrier die or wafer to form a weakened region within the carrier die or wafer, and bonding the carrier die or wafer to a semiconductor structure. The semiconductor structure may be processed while using the carrier die or wafer to handle the semiconductor structure. The semiconductor structure may be bonded to another semiconductor structure, and the carrier die or wafer may be divided along the weakened region therein. Bonded semiconductor structures are fabricated using such methods.

Alloy formation control of transient liquid phase bonding

A bonding structure enabling fast and reliable methods to fabricate a substantially homogeneous bondline with reduced dependency of a thickness limitation is disclosed. Also, this system creates a bondline targeted for performance in power electronics. This system is highly adaptable as various structures and fabrication options may be implemented. This enables diverse fabrication selection and creates less dependency on outside conditions. The disclosed system is at least applicable to wafer-to-wafer, die-to-wafer, die-to-substrate, or die-to-die bonding.

Improvements of long term bondline reliability of power electronics operating at high temperatures

Alloy formation systems and methods and a mechanism, strategy and design for power electronics having high operating temperatures. The system creates a bondline targeted for performance in power electronics. The system provides for sequential alloy growth in high temperature operating power electronics. The system is at least applicable to wafer-to-wafer, die-to-wafer, die-to-substrate, or die-to-die bonding.