ПЕЧАТНАЯ ПЛАТА, В ЧАСТНОСТИ, ДЛЯ СИЛЬНОТОЧНОГО ЭЛЕКТРОННОГО МОДУЛЯ, СОДЕРЖАЩЕГО ЭЛЕКТРОПРОВОДЯЩУЮ ПОДЛОЖКУ

Изобретение относится к печатной плате, в частности, для сильноточного электронного модуля. Технический результат - достижение непосредственного электрического контакта проводящих поверхностей или соответственно токопроводящих дорожек с самой подложкой и использование подложки в качестве электрического проводника. Достигается тем, что в печатной плате, в частности, для сильноточного электронного модуля, содержащего электропроводную подложку, подложка, по меньшей мере, частично, предпочтительно, полностью, выполнена из алюминия или из алюминиевого сплава. Причем, по меньшей мере, на одной поверхности электропроводной подложки расположена, по меньшей мере, одна проводящая поверхность в виде электропроводящего слоя, нанесенного, предпочтительно, методом печати, особенно предпочтительно, методом трафаретной печати. Причем проводящая поверхность непосредственно контактирует с электропроводной подложкой. 2 н. и 13 з.п. ф-лы, 11 ил.

Leistungsmodul

Ein Leistungsmodul ist so aufgebaut, dass ein Leistungsvorrichtungschip (5) innerhalb eines äußeren Gehäuses (1) angeordnet ist und eine Elektrode des Leistungsvorrichtungschips (5) mit einer externen Elektrode (10a) verbunden ist, die in dem äußeren Gehäuse (1) integriert ist. Das Leistungsmodul enthält: einen Wärmeverteiler (3), der in dem äußeren Gehäuse (1) befestigt ist, den Leistungsvorrichtungschip (5), der mit Lot auf den Wärmeverteiler (3) gebondet ist, einen isolierenden Damm (4), der auf dem Wärmeverteiler (3) so gebildet ist, dass er den Leistungsvorrichtungschip (5) umgibt, und eine interne Hauptelektrode (7), deren eines Ende mit Lot auf die Elektrode des Leistungsvorrichtungschips (5) gebondet ist und deren anderes Ende an einer oberen Oberfläche des Dammes befestigt ist. Die externe Elektrode (10a) und das andere Ende der internen Hauptelektrode (7) sind durch Drahtbonden elektrisch miteinander verbunden.

Halbleitereinheit und Verfahren zur Herstellung einer Halbleitereinheit

Eine Halbleitereinheit weist Folgendes auf: ein isolierendes Substrat (1), das durch Integrieren einer keramischen Basisplatte (1b) und einer Kühlrippe (1a) gebildet wird; mehrere Plattenzwischenverbindungselemente (5); sowie eine Mehrzahl von Halbleiterelementen (3a). Die einen Seiten der Halbleiterelemente (3a) sind mit einem Lot (4) an der Chip-Unterseite an die keramische Basisplatte (lb) des isolierenden Substrats (1) gebondet, und die anderen Seiten derselben sind mit einem Lot (6) an der Chip-Oberseite so an die Plattenzwischenverbindungselemente (5) gebondet, dass die Plattenzwischenverbindungselemente (5) jeweils den Halbleiterelementen (3a) entsprechen. Das Lot (4) an der Chip-Unterseite und das Lot (6) an der Chip-Oberseite enthalten beide vorwiegend Sn und 0,3 Gew.% bis 3 Gew.% Ag sowie 0,5 Gew.% bis 1 Gew.% Cu. Dadurch wird eine Reduzierung der Abmessungen der Halbleitereinheit ermöglicht, ohne die Wärmeabführung zu beeinträchtigen.

Halbleitermodul, Halbleitervorrichtung und Fahrzeug

Eine Basisplatte (1) weist eine fixierte Oberfläche und eine abstrahlende Oberfläche, die eine der fixierten Oberfläche gegenüberliegende Oberfläche ist, auf. Ein isolierendes Substrat (3) ist mit der fixierten Oberfläche der Basisplatte (1) verbunden. Leitfähige Muster (4, 5) sind auf dem isolierenden Substrat (3) vorgesehen. Halbleiter-Chips (7, 8) sind mit dem leitfähigen Muster (4) verbunden. Ein Al-Draht (12) verbindet obere Oberflächen des Halbleiter-Chips (8) mit dem leitfähigen Muster (5). Das isolierende Substrat (3), die leitfähigen Muster (4, 5), die Halbleiter-Chips (7 bis 10) und die Al-Drähte (11 bis 13) sind mit einem Harz (16) eingeschlossen. Die Basisplatte (1) weist ein Metallteil (19) und ein verstärkendes Teil (20), das in dem Metallteil (19) vorgesehen ist, auf. Ein Youngscher Modul des verstärkenden Teils (20) ist größer als ein Youngscher Modul des Metallteils (19).

Halbleitervorrichtung mit Wärmeabstrahlplatte und Anheftteil

Eine Halbleitervorrichtung mit: einem Wärmeerzeugungselement (10), das durch einen IGBT bereitgestellt wird; einem Anheftteil (50); ersten und zweiten Wärmeabstrahlplatten (20, 30), welche auf ersten und zweiten Seiten (12, 13) des Wärmeerzeugungselementes (10) entsprechend über das Anheftteil (50) angeordnet sind; einem Wärmeabstrahlblock (40), der zwischen der ersten Wärmeabstrahlplatte (30) und dem Wärmeerzeugungselement (10) über das Anheftteil (50) angeordnet ist; und einem Kunstharzverguss (60), der praktisch die gesamte Vorrichtung eingießt, wobei die ersten und zweiten Wärmeabstrahlplatten (20, 30) in der Lage sind, von dem Wärmeerzeugungselement (10) erzeugte Wärme abzustrahlen; das Wärmeerzeugungselement (10) elektrisch und thermisch mit der ersten Wärmeabstrahlplatte (30) über das Anheftteil (50) und den Wärmeabstrahlblock (40) verbunden ist; das Wärmeerzeugungselement (10) elektrisch und thermisch mit der zweiten Wärmeabstrahlplatte (20) über das Anheftteil (50) verbunden ist ...

Verfahren zum Herstellen einer Halbleiteranordnung sowie entsprechende Halbleiteranordnung

Die Erfindung betrifft ein Verfahren zum Herstellen einer Halbleiteranordnung (1), mit wenigstens einem Basiselement (2) und einem Halbleiter (3), wobei der Halbleiter (3) mittels einer Sinterschicht (4) an dem Basiselement (2) befestigt wird. Dabei ist vorgesehen, dass ein an der Sinterschicht (4) unmittelbar anliegender Bereich (9) des Basiselements (2) zumindest bereichsweise perforiert wird. Die Erfindung betrifft weiterhin eine Halbleiteranordnung (1).

Schaltungsträger, Leistungsschaltungsanordnung mit einem Schaltungsträger, Verfahren zum Herstellen eines Schaltungsträgers

Offenbart wird ein Schaltungsträger (ST) zum Halten eines elektrischen Leistungsbauelements (BE), umfassend: – einen Kühlkörper (KK) aus einem Metall oder einer Metalllegierung zum Halten und zum Kühlen des Leistungsbauelements (BE); – eine Isolierschicht (IS) aus einer elektrisch isolierenden Keramik, welche auf einer Oberfläche (OF1) des Kühlkörpers (KK) ausgebildet ist und zur elektrischen Isolation zwischen dem Leistungsbauelement (BE) und dem Kühlkörper (KK) dient; – eine Leiterbahnschicht (LS) aus Aluminium oder einer Aluminiumlegierung, welche auf einer von dem Kühlkörper (KK) abgewandten Oberfläche (OF2) der Isolierschicht (IS) ausgebildet ist und zur Herstellung flächiger, mechanischer und elektrischer Verbindung zu dem Leistungsbauelement (BE) dient; – eine elektrisch leitende Kontaktschicht (KS) aus Kupfer oder einer Kupferlegierung, welche auf einer vom Kühlkörper (KK) abgewandten Oberfläche (OF3) der Leiterbahnschicht (LS) ausgebildet ist und zur Herstellung flächiger, mechanischer ...

VERKAPSELTES, ANSCHLUSSLEITERLOSES PACKAGE MIT ZUMINDEST TEILWEISE FREILIEGENDER INNENSEITENWAND EINES CHIPTRÄGERS, ELEKTRONISCHE VORRICHTUNG, VERFAHREN ZUM HERSTELLEN EINES ANSCHLUSSLEITERLOSEN PACKAGES UND VERFAHREN ZUM HERSTELLEN EINER ELEKTRONISCHEN VORRICHTUNG

Anschlussleiterloses Package (100) mit:- einem zumindest teilweise elektrisch leitenden Träger (102), der einen Aufbaubereich (104) und einen Anschlussleiterbereich (106) aufweist;- einem elektronischen Chip (108), der an dem Aufbaubereich (104) angebracht ist,- einer Verkapselung (110), die zumindest teilweise den elektronischen Chip (108) verkapselt und teilweise den Träger (102) verkapselt, so dass zumindest ein Teil einer Innenseitenwand (112, 130, 132) des Anschlussleiterbereichs (106) freiliegt, die nicht einen Teil einer Außenseitenwand (115) des Packages (100) bildet, wobeider Anschlussleiterbereich (106) eine Mehrzahl von beabstandeten Anschlussleiterkörpern (118) aufweist, von denen zumindest einer eine zumindest teilweise freiliegende Innenseitenwand (112, 130, 132) hat, die nicht einen Teil der Außenseitenwand (115) des Packages (100) bildet, undeine Bodenfläche (116') der Verkapselung (110) zumindest eine Ausnehmung (198) hat, die zumindest teilweise zumindest eine der Innenseitenwände ...

Mesa semiconductor device with insulating surface film - has at least one pn-junction provided at chip surface and support element on one main surface

The chip of the mesa semiconductor device has one main surface, with at least one p-n junction (12) reaching the surface. The latter is coated by an insulating film (18). A supporting element is fastened to the other main surface. The insulating film (18) thickness increases with the distance from the chip main surface. Preferably, the semiconductor chip has two opposite mesa sections, succh as grooves and the insulating film covers a peripheral or edge surface of each mesa section. The insulating film may be of low melting point glass.

Cooling for power thyristor - has copper base insert and internal coil spring

Thepower thyristors in flat based metal encapsulation usually have a central integral bolt for mounting and require a critically flat metal surface for efficient cooling. A novel method of keeping thermal resistance to a minimum, yet with reduced overall dimension, is to employ a copper base insert and a internal spring to cause the base to bulge slightly so as to make close contact with the surface on which it is mounted eventually. The flat base (12) of the thyristor consists of thin steel in the form of an equilateral triangle with a hole in its centre in which a copper disc (120) about 3mm thick is soldered. On the disc is mounted the semiconductor assembly. Between this assembly and the cover is the flat coil spring (17) which exerts strong downward pressure.

Halbleitervorrichtung mit Metallplatten und Halbleiterchip

Es wird eine Halbleitervorrichtung geschaffen, die aufweist: einen Halbleiterchip (10); eine erste Metallplatte (20), die mittels einer ersten Lötschicht (51) auf einer Seite des Chips (10) angeordnet ist; eine zweite Metallplatte (40), die mittels einer zweiten Lötschicht (52) auf der anderen Seite des Chips (10) angeordnet ist; eine dritte Metallplatte (30), die mittels einer dritten Lötschicht (53) auf der zweiten Metallplatte (40) angeordnet ist; eine Stützeinrichtung (80, 85, 87) zum Halten eines Abstands zwischen dem Chip (10) und der ersten Metallplatte (20) und/oder zwischen dem Chip (10) und der zweiten Metallplatte (40); und eine Aufnahmeeinrichtung (90) zum Aufnehmen von überschüssigem Lot, wenn die dritte Lötschicht (53) das überschüssige Lot aufweist.

Leistungshalbleitermodul mit einem Sandwich mit einem Leistungshalbleitermodul

Die Erfindung beschreibt ein Leistungshalbleitermodul mit mindestens einem ersten und einem zweiten Lastanschlusskörper, mit mindestens einem zwischen diesen Lastanschlusskörpern angeordnetem Sandwich mit einem ersten Metallformkörper, einem Leistungshalbleiterbauelement und einem zweiten Metallformkörper. Hierbei sind die Komponenten des Sandwiches stoffschlüssig miteinander verbunden und ein Randbereich des Leistungshalbleiterbauelements ist umschlossen von einem elektrisch isolierenden, hoch wärmeleitfähigen Polymermaterial. Wesentlich hierbei ist, dass dieses Polymermaterial in thermisch leitendem Kontakt zu mindestens einem dem ersten oder zweiten Metallformkörper ist.

Reconstituted device including die and functional material

Dies from a wafer are reassembled with passive components and encapsulated to form a reconstituted electronic device 10 comprising a die 11, a passive, functioning component 13 and a metallic redistribution layer 15 which defines an electronic component in an area at least partially above the functioning material. The electronic component may be a metal-oxide-metal capacitor, an inductor or an antenna. The functioning material may be ceramic or it may be a ferrite. The functioning material may surround the die. In one embodiment the functioning material is a ceramic body with a metallic coating 110 (figure 10) on a face opposite that of the surface of the substrate on which the die and functioning material are embedded, a metallic via 102 (figure 9) is included through the ceramic body to contact the metal coating, the redistribution layer/ceramic body/metal coating structure forms a capacitor. In another embodiment the functioning material may be a metal carrier 120 (figure 11) with an ...

SEMICONDUCTORS

... 1535195 Semi-conductor devices GENERAL ELECTRIC CO 19 Dec 1975 [23 Dec 1974] 52131/75 Heading H1K A semi-conductor device comprises a planar semi-conductor device chip 22 bonded to substantially co-extensive planar regions of metallic mounting plates 32, 33 which have peripheral edges that are not coplanar with said planar region so as to alleviate the effects of burrs 37 formed during manufacture of the mounting plates 32, 33. The mounting plates may be of Cu or Mo and they may be soldered to the device chip 22. The edges of the mounting plates are separated from the planar regions by transition regions 36 which may be straight, stepped or arcuate. One face of the device chip 22 may have ribbon contacts that bend away from the device chip 22 and terminate in flat portions that are coplanar with the outer face of the mounting plate on the opposite face of the chip 22, to facilitate attachment to a printed circuit board.

MANUFACTURING PROCESS OF AN ARRANGEMENT WITH POWER SEMICONDUCTOR ELEMENTS, WHICH CONTAINS A STEP PRINTINGINTERNALLY

SEMICONDUCTOR BODY WITH PLUMB BOB MATERIAL LAYER AND PROCEDURE FOR THE AUFLÖTEN OF THE SEMICONDUCTOR BODY ON A METALLIC MOTHER BOARD

PACKAGE FOR INTEGRATED CIRCUIT DIE

A circuit package for housing semiconductor or other integrated circuit devices ("die") includes a high-copper flange, one or more high-copper leads and a liquid crystal polymer frame molded to the flange and the leads. The flange includes a dovetail-shaped groove or other frame retention feature that mechanically interlocks with the molded frame. During molding, a portion of the frame forms a key that freezes in or around the frame retention feature. The leads include one or more lead retention features to mechanically interlock with the frame. During molding, a portion of the frame freezes in or adjacent these lead retention features. The frame includes compounds to prevent moisture infiltration and match its coefficient of thermal expansion (CTE) to the CTE of the leads and flange. The frame is formulated to withstand die-attach temperatures. A lid is ultrasonically welded to the frame after a die is attached to the flange.

Verfahren zur Herstellung einer Halbleiteranordnung

Dispositif semiconducteur

Halbleiterbauelement mit einer Hülle, zwei Anschlüsse aufweist

SEMICONDUCTOR ARRANGEMENT.

Chip Carriers And Semiconductor Devices Including Redistribution Structures With Improved Thermal And Electrical Performance

Semiconductor device

Semiconductor device

Packaging method of flip chip

Chip-scale package

A method for manufacturing a semiconductor package that includes forming a frame inside a conductive can, the frame being unwettable by liquid solder.

INTEGRATED CIRCUIT COMPRISING a SOURCE Of WAVES MILLIMETRE-LENGTH, AND MANUFACTORING PROCESS OF THE AFORESAID CIRCUIT

ELECTRODES FOR SEMICONDUCTOR PASTILLE OF POWER

A method of manufacturing a silicon semiconductor device

Semiconductor device and method of mounting of the same

Device semiconductor

ASSEMBLING AN INTEGRATED CIRCUIT DIE AND A PLATE

Improvement brought to the manufacture of electronics components, such as tansistors and diodes, including/understanding a cap welded onto a support of a base plate

Power diode for vehicle alternator bridge rectifier - comprises semiconductor element mounted inside cylindrical casing sealed with resin

이미지 센싱 칩을 위한 패키징 방법 및 패키지 구조

... 이미지 센싱 칩의 패키징 방법 및 패키지 구조가 제공된다. 패키징 방법은, 제 1 면 (101) 및 제 1 면 (101)에 대향하는 제 2 면 (102)을 갖는 웨이퍼 (100)를 제공하는 단계로서, 웨이퍼 (100)는 그리드의 형태로 배열된 복수의 이미지 센싱 칩 (110)을 가지며, 이미지 센싱 칩 (110)은 이미지 센싱 영역 (111) 및 솔더 패드 (112)를 가지고, 이미지 센싱 영역 (111)과 솔더 패드 (112)는 제 1 면측에 위치하는 단계; 웨이퍼의 제 2면에 커팅 리세스 (cutting recess) (103)를 형성하고 솔더 패드 (112)에 대응하는 개구부 (113)를 형성하는 단계로서, 개구부 (113)는 솔더 패드 (112)를 노출시키는 단계; 커팅 리세스 (103) 내에 제 1 감광성 잉크 (117)를 충전하는 단계; 및 제 2 감광성 잉크 (118)가 개구부 (113)를 덮고 개구부 (113)에 캐비티 (119)를 형성하도록, 웨이퍼 (100)의 제 2면 (102) 상에 제 2 감광성 잉크 (118)를 코팅하는 단계;를 포함한다. 이와 같은 방법으로 형성된 이미지 센싱 칩 패키지 구조는 제 2 감광성 잉크가 개구부의 바닥과 접촉하는 것을 효과적으로 방지함으로써 이미지 칩의 패키지 수율을 향상시키고, 이미지 칩 패키지 구조의 신뢰성을 향상시킨다.

Method for making a direct chip attach device and structure

A method for forming a direct chip attach device (1) includes attaching an electronic chip (3) to a lead frame structure (2), which includes a flag (18). Next, conductive studs (22) are attached to bond pads (13) on electronic chip (3) and flag (18) to form a sub-assembly (24). Sub-assembly (24) is then placed in a molding apparatus (27, 47), which includes a first plate (29, 49) and second plate (31, 51). Second plate (31, 51) includes a cavity (32, 52) for receiving electronic chip (3) and flag (18), and pins (36, 56). During a molding step, pins (36, 56) contact conductive studs (22) to prevent encapsulating material (4) from covering studs (22). This forms openings (6) to receive solder balls (9) during a subsequent processing step.

Hybrid-core through holes and vias

A semiconductor device substrate includes a front section and back section that are laminated cores disposed on a front- and back surfaces of a first core. The first core has a cylindrical plated through hole that has been metal plated and filled with air-core material. The front- and back sections have laser-drilled tapered vias that are filled with conductive material and that are coupled to the plated through hole. The back section includes an integral inductor coil that communicates to the front section. The first core and the laminated-cores form a hybrid-core semiconductor device substrate with an integral inductor coil.

Method and system for packing optimization of semiconductor devices

Provided is a disclosure for optimizing the number of semiconductor devices on a wafer/substrate. The optimization comprises laying out, cutting, and packaging the devices efficiently.

CHIP INTERFACE MESA.

SEMICONDUCTOR DEVICE

This semiconductor device (1) contains the following: a metal substrate; a semiconductor element disposed on the metal substrate; and a flexible circuit board that is electrically connected to the semiconductor element and extends outwards past an edge of the metal substrate, one end of said flexible circuit board being disposed on the metal substrate. This semiconductor device is characterized in that a thickness-increasing member is joined to the metal-substrate side of the flexible circuit board in the region of the flexible circuit board located above the aforementioned edge of the metal substrate.

THREE-DIMENSIONAL PRINTED CIRCUIT BOARD, ELECTRONIC CIRCUIT PACKAGE USING THIS BOARD, AND METHOD FOR MANUFACTURING THIS BOARD

A metallic base board is used for mounting electronic components thereon. The board is formed by laminating a plurality of copper foils on a metallic board through thermoplastic polyimide. On the copper foils circuit patterns are formed. The metallic base board having such circuit patterns is bent and deeply drawn in order to configure a box having an open face. The area of the open face is nearly equal to that of the bottom face. On the edges of the open face flanges are formed. On the flanges, by patterning, there are formed leads which are used for connecting this board to another wiring board. The three-dimensional printed circuit board thus prepared is mounted on another wiring board with its open face down. The leads are soldered to the circuit pattern on the wiring board. Electronic components are mounted on the bottom face of the three-dimensional printed circuit board. Hence, an electronic circuit package is constructed.

Chip scale surface mounted device and process of manufacture

A chip scale package has a semiconductor MOSFET die which has a top electrode surface covered with a layer of a photosensitive liquid epoxy which is photolithographically patterned to expose portions of the electrode surface and to act as a passivation layer and as a solder mask. A solderable contact layer is then formed over the passivation layer. The individual die are mounted drain side down in a metal clip or can with the drain electrode disposed coplanar with a flange extending from the can bottom.

SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor package structure includes a base, at least one semiconductor element, a first dielectric layer, a second dielectric layer and a circuit layer. The semiconductor element is disposed on the base and has an upper surface. The first dielectric layer covers at least a portion of a peripheral surface of the semiconductor element and has a top surface. The top surface is non-coplanar with the upper surface of the semiconductor element. The second dielectric layer covers the semiconductor element and the first dielectric layer. The circuit layer extends through the second dielectric layer to electrically connect the semiconductor element.

Thermoplastic material

A circuit package for housing semiconductor or other integrated circuit devices (“die”) includes a high-copper flange, one or more high-copper leads and a liquid crystal polymer frame molded to the flange and the leads. The flange includes a dovetail-shaped groove or other frame retention feature that mechanically interlocks with the molded frame. During molding, a portion of the frame forms a key that freezes in or around the frame retention feature. The leads include one or more lead retention features to mechanically interlock with the frame. During molding, a portion of the frame freezes in or adjacent these lead retention features. The frame includes compounds to prevent moisture infiltration and match its coefficient of thermal expansion (CTE) to the CTE of the leads and flange. The is frame is formulated to withstand die-attach temperatures. A lid is ultrasonically welded to the frame after a die is attached to the flange.

SEMI-CONDUCTOR DIODE UNITS

Carrier with a metal area and at least one chip configured on the metal area

A carrier has a metal area that is essentially composed of copper. A chip has a rear side metallization layer. A buffer layer, essentially composed of nickel and having a thickness of between 5 mum and 10 mum, is arranged on the metal area. The chip does not have a chip housing and is arranged on the metal area, which has been provided with the buffer layer, such that only one connecting medium is arranged between the rear side metallization layer of the chip and the buffer layer.

Rectification chip terminal structure

A rectification chip terminal structure for soldering a rectification chip on a terminal filled with a packaging material to form a secured mounting for the rectification chip is to be inserted in a coupling bore of a circuit board. The structure includes a helical buffer portion, a spacer zone containing a space, a tapered section inclining towards the center of the terminal, a bend spot having latch rings to provide coupling, and a deck having a bulged ring. The structure can prevent bending and deformation under external forces, and form a stress buffer zone to prevent the chip from being damaged and moisture from entering. It can be installed easily in the coupling bore of the circuit board and hold the packaging material securely without breaking away.

Autoclave capable chip-scale package

A power semiconductor package that includes a power semiconductor device having a threshold voltage that does not vary when subjected to an autoclave test.

Embedded die redistribution layers for active device

Embedded die packages are described that employ one or more substrate redistribution layers (RDL) to route electrode nodes and/or for current redistribution. In one or more implementations, an integrated circuit die is embedded in a copper core substrate. A substrate RDL contacts a surface of the embedded die, with at least one via (e.g., thermal via) in contact with the surface RDL to furnish electrical interconnection between the embedded die and an external contact. Additional substrate RDL or WLP RDL can be incorporated into the package to provide varying current distribution between the embedded die and external contacts.

Semiconductor Package And Fabrication Method Thereof

A method of making a semiconductor packaged device comprises mounting onto a lead frame a bottom of a molded semiconductor chip having a first plastic package body covering a top face of a semiconductor chip, encapsulating the lead frame and the semiconductor chip with a second plastic package body with top surfaces of conductive contact bodies electrically connected to electrodes on the top surface of the semiconductor chip exposed and plating conductive pads on a top surface of the assembly structure to provide external electrical connections to the electrodes through the conductive contact bodies.

SEMICONDUCTOR DEVICE

In a semiconductor device in which a semiconductor chip is cooled by a cooler, an insulating member between a semiconductor chip and a cooler is omitted in order to simplify the configuration. A cooler (23, 24, 25) for performing heat exchange between a semiconductor chip (21, 22) and a refrigerant is provided. The refrigerant is non-conductive. The semiconductor chip (21, 22) and the cooler (23, 24, 25) are connected to each other through a conductive connection component (28) or are directly connected to each other.

DIE ASSEMBLIES

An embodiment of a die assembly includes a flange, lip walls, and leads for electrical contact with one or more die mounted on the flange. The flange has first and second opposed flange surfaces and flange sidewalls extending between the surfaces. The lip walls have first and second opposed lip surfaces and lip sidewalls extending between the first and second lip surfaces. The lip sidewalls are positioned adjacent to the flange sidewalls. The leads, which have inboard end portions and outboard end portions, are configured to preserve a seating plane. The seating plane is spaced apart from a plane of the second flange surface. The inboard end portions of the leads are embedded in the lip walls, and extend from the seating plane upward through the lip walls toward the first lip surfaces. The outboard end portions are aligned substantially within the seating plane.

Stacked package, method of fabricating stacked package, and method of mounting stacked package fabricated by the method

Provided are a stacked package, method of fabricating a stacked package, and method of mounting a stacked package. A method includes providing an upper semiconductor package including an upper package substrate, upper semiconductor chips formed on a top surface of the upper package substrate, and first solders formed on a bottom surface of the upper package substrate and having a first melting temperature, providing a lower semiconductor package including a lower package substrate, lower semiconductor chips formed on a top surface of the lower package substrate, and solder paste nodes formed on the top surface of the lower package substrate and having a second melting temperature lower than the first melting temperature, and forming inter-package bonding units by attaching respective first solders and solder paste nodes to each other by performing annealing at a temperature higher than the second melting temperature and lower than the first melting temperature.

SEMICONDUCTOR PACKAGE WITH UNDER BUMP METALLIZATION ROUTING

A semiconductor package includes a semiconductor substrate a semiconductor substrate having source and drain regions formed therein, an intermediate routing structure to provide electrical interconnects to the source and drain regions, a dielectric layer formed over the intermediate routing structure, and an under-bump-metallization (UBM) stack. The intermediate routing structure includes an outermost conductive layer, and the dielectric layer has an opening positioned over a portion of the intermediate layer routing structure. The UBM stack includes a conductive base layer formed over the dielectric layer and electrically connected to the outermost conductive layer through the opening, and a thick conductive layer formed on the base layer. A conductive bump is positioned on the UBM stack and laterally spaced from the opening.

Device Including Two Power Semiconductor Chips and Manufacturing Thereof

A device includes a first power semiconductor chip with a first contact pad and a second contact pad on a first face and a third contact pad on the second face. The device further includes a second power semiconductor chip with a first contact pad and a second contact pad on a first face and a third contact pad on the second face. The first and second power semiconductor chips are arranged one above another, and the first face of the first power semiconductor chip faces in the direction of the first face of the second power semiconductor chip. In addition, the first power semiconductor chip is located laterally at least partially outside of the outline of the second power semiconductor chip.

Power semiconductor module and method of manufacturing a power semiconductor module

The present invention relates to a power semiconductor module comprising a semiconductor device (12), in particular an insulated gate bipolar transistor, a reverse conductive insulated gate bipolar transistor, or a bi-mode insulated gate transistor, with an emitter electrode and a collector electrode, wherein an electrically conductive upper layer (14) is sintered to the emitter electrode, the upper layer (14) at least partly being capable of forming an eutecticum with the semiconductor of the semiconductor device (12) and at least partly having a coefficient of thermal expansion which differs from the coefficient of thermal expansion of the semiconductor in a range of ≤ 250%, in particular ≤ 50%, and wherein an electrically conductive base plate (20) is sintered to the collector electrode, and wherein the semiconductor module (10) further comprises an electrically conductive area (24) being electrically isolated from the base plate (20) and being connected to the upper layer (14) via a ...

Bondwireless Power Module with Three-Dimensional Current Routing

According to an exemplary embodiment, a bondwireless power module includes a common output pad coupling an emitter/anode node of a high side device to a collector/cathode node of a low side device. The bondwireless power module also includes a high side conductive clip connecting a collector of the high side device to a cathode of the high side device, and causing current to traverse through the high side conductive clip to another high side conductive clip in another power module. The bondwireless power module further includes a low side conductive clip connecting an emitter of the low side device to an anode of the low side device, and causing current to traverse through the low side conductive clip to another low side conductive clip in the another power module. The bondwireless power module can be a motor drive inverter module.

PACKAGE APPARATUS COMPRISING CAPACITOR DISPOSED OPPOSITE DIE BASED ON SUBSTRATE

A package device includes a substrate, a plurality of upper lands disposed on one surface of the substrate, a plurality of upper solder balls disposed on the plurality of upper lands, a die connected to the plurality of upper solder balls, a plurality of lower lands disposed on the other surface of the substrate, a plurality of lower solder balls disposed on some of the plurality of lower lands, and a capacitor connected to the lower lands on which the lower solder balls are not disposed among the plurality of lower lands, provided on an opposite side of the die, and including a height greater than the height of the lower solder ball.

METHOD OF MANUFACTURING BASE FOR PRESSURE CONTACT TYPE SEMICONDUCTOR

Fügehilfe für ein Leistungsmodul

Die Erfindung bezieht sich auf eine Leistungsmodul mit einem Metall-Keramik-Verbundwerkstoffschicht zwischen dem Leistungshalbleiter und dem Schaltungsträger.

Chipanordnungen

Chipanordnung (310), welche aufweist:eine Leiterplatte (362), welche aufweist:• ein Durchgangsloch (364), das in der Leiterplatte (362) ausgebildet ist,• und ein oder mehrere Leiterplattenkontaktgebiete (366S, 366G, 366D) , die in der Nähe des Durchgangslochs (364) angeordnet sind, undein Chipgehäuse (210, 160) mit einem Chip (104), das innerhalb des Durchgangslochs (364) angeordnet ist, wobei mindestens ein Leiterplattenkontaktgebiet (366S, 366G) elektrisch mit einem oder mit mehreren elektrisch leitenden Verbindungsstrukturen (144, 146) verbunden ist, die über einer Oberseite (152) des Chipgehäuses (210, 160) ausgebildet sind und in elektrischem Kontakt mit einer Chipoberseite (122) stehen, undwobei mindestens ein weiteres Leiterplattenkontaktgebiet (366D) elektrisch mit einer elektrisch leitenden Verbindungsstruktur (148) verbunden ist, die über einer Unterseite (154) des Chipgehäuses (210, 160) ausgebildet ist und in elektrischem Kontakt mit einer Chipunterseite (124) steht,wobei das ...

VERFAHREN ZUR HERSTELLUNG EINER HALBLEITERVORRICHTUNG

"ELEKTRODEN FUER LEISTUNGS-HALBLEITERZELLE"

Elektronischer Schaltkreis

Elektronische Komponente

In einer Ausführungsform schließt eine elektronische Komponente eine dielektrische Schicht, ein in die dielektrische Schicht eingebettetes Halbleiterbauelement, ein elektrisch leitendes Substrat, eine Umverteilungsschicht mit einer ersten Oberfläche und einer zweiten Oberfläche, die mindestens einen Außenkontakt vorsieht, und ein erstes elektrisch leitendes Bauteilelement ein. Das Halbleiterbauelement weist eine erste Oberfläche, die mindestens ein erstes Kontaktpad einschließt, und eine zweite Oberfläche, die mindestens ein zweites Kontaktpad einschließt, auf. Das zweite Kontaktpad ist auf dem elektrisch leitenden Substrat montiert. Das erste elektrisch leitende Bauteilelement schließt mindestens einen Bolzenhöcker ein und erstreckt sich zwischen dem elektrisch leitenden Substrat und der ersten Oberfläche der Umverteilungsschicht.

HALBLEITERVORRICHTUNG UND VERFAHREN ZUM HERSTELLEN EINER HALBLEITERVORRICHTUNG

Eine Halbleitervorrichtung umfasst ein Klemmengehäuse kombiniert mit einer gestapelten Baugruppe, die ein Halbleiterelement, ein gestapeltes Substrat, auf dem ein Elektrodenmuster bereitgestellt wird und das Halbleiterelement montiert ist, eine Leiterrahmen-Zusammenschaltung, die das Halbleiterelement und das Elektrodenmuster elektrisch verbindet, und ein Metallsubstrat, auf dem das gestapeltes Substrat montiert ist, umfasst. Die Leiterrahmen-Zusammenschaltung besteht aus einem Bondabschnitt in Kontakt mit dem Halbleiterelement, einem Bondabschnitt in Kontakt mit dem Elektrodenmuster und einem Zusammenschaltungsabschnitt, der die Bondabschnitte verbindet. Die Breite der Bondabschnitte ist breiter als die Breite des Zusammenschaltungsabschnitts.

PRESSURE CONTACT TYPE SEMICONDUCTOR DEVICES

... 1492707 Semiconductor devices AGENCY OF INDUSTRIAL SCIENCE & TECHNOLOGY 7 Jan 1976 [17 April 1975 (2)] 00435/76 Heading H1K A pressure contact type transistor has elongate mesa-like emitter region portions 46 extending substantially radially outwards from points on a circle, preferably located at the centre of the circular upper transistor surface, each portion 46 carrying an emitter electrode 47, the electrodes 47 all being pressure contacted by a common conductive plate 50. A base electrode 48 and a collector electrode 69-72 are provided on the upper and lower surfaces respectively. In the structure shown a second transistor forming a Darlington pair with the first is integrated in the same wafer, and comprises a mesa-like emitter region 55/56/57 around a central base electrode 62 pressure contacted by member 66. Metallization 63 interconnects emitter electrode 58 on region 55/56/57 and the base electrode 48 of the main transistor. In a modification a conductive bridge of greater current-carrying ...

Semiconductor contact shim and attachment method

A contact shim for insertion between an electrode and a contact surface of a semiconductor element in a semiconductor device assembly has a generally continuous body (2) provided with a number of apertures (4, 5, 6, 7) having a land (1) 2 or finger extending at least partially thereacross. Preferably a land comprises a bar which bisects an aperture (4, 5, 6, 7). The apertures and bisecting lands may be used as visual guides in aligning the shim with reference marks on the contact surface of the semiconductor element and, the means of attaching the shim to the element may be applied to the lands in order that any distortion consequent upon attachment is confined to the lands leaving the body of the shim undistorted. ...

BONDING DEVICES

Elektrische Bauteilanordnung

Bei einer elektrischen Bauteilanordnung (1) mit wenigstens einem ersten diskreten Halbleiterbauelement (2), welches erste diskrete Halbleiterbauelement (2) ein erstes Gehäuse (3) mit einer ersten Gehäuseaußenfläche (4) aufweist, wobei die erste Gehäuseaußenfläche (4) als elektrischer Kontakt des ersten Halbleiterbauelements (2) ausgebildet ist, wird vorgeschlagen, dass die erste Gehäuseaußenfläche (4) elektrisch leitend mit einer elektrisch leitenden Platte (5) der elektrischen Bauteilanordnung (1) verbunden ist, und dass die elektrisch leitende Platte (5) elektrisch isoliert mit einem Kühlkörper (6) der elektrischen Bauteilanordnung (1) verbunden ist.

Leiterplatte, insbesondere für ein Leistungselektronikmodul, umfassend ein elektrisch leitfähiges Substrat

Leiterplatte (1a, 1b, 1c), insbesondere für ein Leistungselektronikmodul (2), umfassend ein elektrisch leitfähiges Substrat (3), wobei das Substrat (3) zumindest teilweise, vorzugsweise vollständig, aus Aluminium und/oder einer Aluminiumlegierung besteht, wobei auf wenigstens einer Oberfläche (3a, 3b) des elektrisch leitfähigen Substrats (3) wenigstens eine Leiterfläche (4a, 4b) in Form einer, vorzugsweise durch ein Druckverfahren, besonders bevorzugt durch ein Siebdruckverfahren, aufgebrachten, elektrisch leitfähigen Schicht angeordnet ist, wobei die Leiterfläche (4a, 4b) direkt mit dem elektrisch leitfähigen Substrat (3) elektrisch kontaktiert ist.

Leiterplatte, insbesondere für ein Leistungselektronikmodul, umfassend ein elektrisch leitfähiges Substrat

Leiterplatte (1a, 1b, 1c), insbesondere für ein Leistungselektronikmodul (2), umfassend ein elektrisch leitfähiges Substrat (3), wobei das Substrat (3) zumindest teilweise, vorzugsweise vollständig, aus Aluminium und/oder einer Aluminiumlegierung besteht, wobei auf wenigstens einer Oberfläche (3a, 3b) des elektrisch leitfähigen Substrats (3) wenigstens eine Leiterfläche (4a, 4b) in Form einer, vorzugsweise durch ein Druckverfahren, besonders bevorzugt durch ein Siebdruckverfahren, aufgebrachten, elektrisch leitfähigen Schicht angeordnet ist, wobei die Leiterfläche (4a, 4b) direkt mit dem elektrisch leitfähigen Substrat (3) elektrisch kontaktiert ist.

SUB-MOUNT AND SEMICONDUCTOR DEVICE

SEMICONDUCTOR DEVICE WITH LOW IMPEDANCE BOND AND PROCESS FOR ITS FABRICATION

Semiconductor package and method of manufacturing semiconductor package

SEMICONDUCTOR DEVICE AND AMPLIFIER

The invention provides a semiconductor device and an amplifier which reduce inductance of a connecting wire. The semiconductor device includes a ground plane, a capacitor disposed on the ground plane and having a first top surface, a semiconductor chip disposed on the ground plane and having a second top surface, a bonding wire connecting the first top surface and the second top surface, and a conductive member disposed on the ground plane. The conductive member is electrically connected to the ground plane. The bonding wire extends in a first direction in a planar view normal to the ground plane. The conductive member is positioned apart from the bonding wire in a second direction orthogonally intersecting in the planar view with the first direction.

Embedded system for automobile industry, has cupel with cavity and flooring that is connected to semiconductor device, and body-forming stopper fixed on cupel and conductor

Le boîtier incorporé pour dispositif à semi-conducteur (20) comprend, un conducteur (10), une coupelle (30), un dispositif à semi-conducteur (20) et un corps formant tampon (60). La coupelle (30) présente une cavité et un étagement de montage en matrice (34) logée dans la cavité. Le dispositif à semi-conducteur (20) assure la connexion au conducteur (10) et à l'étagement de montage en matrice (34) de la coupelle (30). La coupelle (30) empêche que le moule du dispositif à semi-conducteur (20) se rompe pendant le fonctionnement sous haute température.

MODULATE ELECTRONICS COMPONENTS OF POWER AND PROCESS Of ASSEMBLY Of SO-AND-SO MODULATES

Mfr. of mesa diodes - uses deposition and surface erosion to avoid deterioration resulting from thermocompression

Socket connecting semiconductor chip to metallic frame - has elevations on area where chip is contacted with solder surrounding contact point

METHOD FOR MAKING A COMPOSITE STRUCTURE COMPRISING A CONDUCTIVE STRUCTURE AND A SEMICONDUCTOR STRUCTURE COMPRISING A STEP OF CUTTING AND ELECTRO-EROSION

ELECTRONIC POWER MODULE

CARRIER WITH METAL BUMPS FOR SEMICONDUCTOR DIE PACKAGES

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

The present invention provides a semiconductor device having improved reliability. The semiconductor device comprises: a pad provided on a substrate; and a bump structure electrically connected to the pad. The bump structure includes: a first copper layer and a second copper layer sequentially laminated on the pad; and a solder ball on the second copper layer. A ratio of a surface (111) and a surface (200) in the first copper layer is larger than that in the second copper layer. COPYRIGHT KIPO 2018 ...

POWER MODULE STRUCTURE AND SOLID STATE RELAY USING THE SAME, CAPABLE OF CONSTRAINING BENDING OF TERMINAL

PURPOSE: A power module structure and a solid state relay using the same are provided to solve a heat dissipation problem by improving close adhesion of a heat plate on a heat sink. CONSTITUTION: A power module structure includes a heat plate includes a heat plate(1), an insulation unit(2), a terminal(4), a semiconductor chip(3), and a stress lessening unit which are sequentially bonded by solder. The heat plate(1) is contacted with a heat sink. The terminal(4) is connected to a contact point of the semiconductor chip(3). The terminal(4) is connected to the contact point of the corresponding semiconductor chip(3). The stress lessening unit to lessen a stress generated by a difference of a thermal expansion coefficient of the corresponding terminal and the insulation unit(2) is installed on the terminal(4). A stress constraining unit as a solder bonding region which solders the terminal(4) to the insulation unit(2) is partially formed. © KIPO 2007 ...

A packaging method and structure for an image sensing chip

A packaging method and structure for an image sensing chip is provided. The packaging method includes: providing a wafer having a first surface and a second surface opposite to the first surface, the wafer including multiple image sensing chips arranged in a grid, and the image sensing chip including an image sensing region and a pad which are located at the side of the first surface; forming a cutting groove and a hole corresponding to the pad on the second surface of the wafer, the pad being exposed through the hole; filling the cutting groove with a first photosensitive ink; coating the second surface of the wafer with a second photosensitive ink to cause the second photosensitive ink to cover the hole with a cavity being formed in the hole. The packaging structure of the image sensing chip formed by the method can effectively avoid contact of the second photosensitive ink with the bottom of the hole, which improves the yield of packaging the image sensing chip and improves the reliability ...

Semiconductor package including a semiconductor die having redistributed pads

A semiconductor package that includes a semiconductor die, an insulation around the die, and a conforming conductive pad coupled to an electrode of the die.

CHIP-SCALE PACKAGE

A method for manufacturing a semiconductor package that includes forming a frame inside a conductive can, the frame being unwettable by liquid solder.

SEMICONDUCTOR DIE PACKAGE INCLUDING MULTIPLE DIES AND A COMMON NODE STRUCTURE

A semiconductor die package capable of being mounted to a motherboard is disclosed. The semiconductor die package includes a substrate, and a first semiconductor die mounted on the substrate, where the first semiconductor die includes a first vertical device comprising a first input region and a first output region at opposite surfaces of the first semiconductor die. The semiconductor die package includes a second semiconductor die mounted on the substrate, where second semiconductor die comprises a second vertical device comprising a second input region and a second output region at opposite surfaces of the second semiconductor die. A substantially planar conductive node clip electrically communicates the first output region in the first semiconductor die and the second input region in the second semiconductor die. The first semiconductor die and the second semiconductor die are between the substrate and the conductive node clip.

SEMICONDUCTOR DEVICE

The purpose is to eliminate the insulating member between the semiconductor chip and the cooler in a semiconductor device in which a semiconductor chip is cooled by a cooler, simplifying the structure of the device. The device is furnished with semiconductor chips (21, 22), and coolers (23, 24, 25) for heat exchange from the semiconductor chips (21, 22) to a coolant. The coolant is non-conductive. The semiconductor chips (21, 22) and the coolers (23, 24, 25) are connected directly, or by conductive connecting members (28) therebetween.

METHOD AND RESULTING STRUCTURE FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE

A semiconductor wafer composite is used as a basis for fabricating semiconductor chips, especially compound semiconductor devices. The semiconductor wafer composite advantageously comprises a metallic substrate (210) and multiple semiconductor tiles (220) bonded to the surface of the metallic substrate (210). The semiconductor wafer composite is effectively used as a single large semiconductor wafer for volume fabrication, and can be used to fabricate semiconductor devices in a similar manner.

Surface mounted package with die bottom spaced from support board

A semiconductor package according to the present invention includes a metal can which receives in its interior space a MOSFET. The MOSFET so received is oriented such that its drain electrode is facing the bottom of the can and is electrically connected to the same by a layer of conductive epoxy or a solder or the like. The edges of the MOSFET so placed are spaced from the walls of the can. The space between the edges of the MOSFET and the walls of the can is filled with an insulating layer. A surface of the MOSFET is sub-flush below the plane of a substrate by 0.001-0.005 inches to reduce temperature cycling failures.

Structure and method for power field effect transistor

A packaged semiconductor device has a metal plate (1200) with sawed sides (1200c), a flat first surface (1200a) and a parallel second surface (1200b); the plate is separated into a first section (1201) and a second section (1202) spaced apart by a gap (1230). The plate has on the second surface (1200b) at least one insular mesa (1205) of the same metal in each section, the mesas raised from the second plate surface. The device further has an insulating member (1231), which adheres to the first plate surface, bridges the gap, and thus couples the first and second sections together. The device further has a vertical stack (1270) of two power FET chips (1210) and (1220), each having a pair of terminals on the first chip surface (1211 and 1212; 1221 and 1222 respectively) and a single terminal on the second chip surface. The single terminals of chip (1210) and chip (1220) are attached to each other to form the common terminal (1240). The terminal pair (1221) and (1222) is conductively attached ...

Connection terminal and circuit component

A conductive connection terminal having a planar joining surface joined to a joining target surface by a soldering material interposed between the joining surface and the joining target surface. The conductive connection terminal is configured such that, on either side across a predetermined reference straight line which, as well as passing through a center of gravity of the joining surface, extends along the joining surface, the joining surface includes indented portions indented from outer edge portions of the joining surface toward the reference straight line side.

Semiconductor apparatus and method for manufacturing the same

According to one embodiment, a semiconductor apparatus includes a semiconductor device, a heat spreader, a regulating unit, a containing unit, and a holding unit. The heat spreader is bonded to the semiconductor device with an interposed solder layer. The regulating unit is configured to regulate a dimension between the semiconductor device and the heat spreader. The containing unit is configured to contain melted solder in an interior of the containing unit. The holding unit is configured to allow melted solder held in an interior of the holding unit. The holding unit is configured to replenish the melted solder in the case where an amount of the melted solder contained in the containing unit is insufficient. The holding unit is configured to recover the melted solder in the case where the amount of the melted solder contained in the containing unit is excessive.

System and Method for Wafer Level Packaging

In an embodiment, a semiconductor device includes a semiconductor substrate. The semiconductor substrate has a first cavity disposed through it, and conductive material covers at least the bottom portion of the first cavity. An integrated circuit is disposed on the top surface of the conductive material. The device further includes a cap disposed on the top surface of the substrate, such that a cavity disposed on a surface of the cap overlies the first cavity in the substrate.

Power Module and Power Converter Containing Power Module

A power module includes a semiconductor chip, a first coupling conductor with one main surface coupled to one main surface of the semiconductor chip, a second coupling conductor with one main surface coupled to the other main surface of the semiconductor chip, a coupling terminal supplied with electrical power from the direct current power source, and resin material to seal the semiconductor chip, and in which the resin member has a protruding section that protrudes from the space where the first and second coupling conductors are formed opposite each other, and the coupling terminal is clamped on the protruding section, and at least one of the first or second coupling conductors is coupled to a coupling terminal by way of a metallic material that melts at a specified temperature.

Power Module with Current Routing

According to an exemplary embodiment, a bondwireless power module includes a common output pad coupling an emitter/anode node of a high side device to a collector/cathode node of a low side device. The bondwireless power module also includes a high side conductive clip connecting a collector of the high side device to a cathode of the high side device, and causing current to traverse through the high side conductive clip to another high side conductive clip in another power module. The bondwireless power module further includes a low side conductive clip connecting an emitter of the low side device to an anode of the low side device, and causing current to traverse through the low side conductive clip to another low side conductive clip in the another power module. The bondwireless power module can be a motor drive inverter module.

MULTIPLE DIE FACE-DOWN STACKING FOR TWO OR MORE DIE

A microelectronic assembly can include a substrate having first and second surfaces each extending in first and second transverse directions, a peripheral edge extending in the second direction, first and second openings extending between the first and second surfaces, and a peripheral region of the second surface extending between the peripheral edge and one of the openings. The assembly can also include a first microelectronic element having a front surface facing the first surface, a rear surface opposite therefrom, and an edge extending between the front and rear surfaces. The assembly can also include a second microelectronic element having a front surface facing the rear surface of the first microelectronic element and projecting beyond the edge of the first microelectronic element. The assembly can also include a plurality of terminals exposed at the second surface, at least one of the terminals being disposed at least partially within the peripheral region. 1. A microelectronic assembly , comprising: first and second opposed surfaces each extending in first and second transverse directions;', 'a peripheral edge extending between the first and second surfaces and in the second direction;', 'first and second openings extending between the first and second surfaces, each of the openings having an elongated first dimension extending in the first direction, and a second dimension in the second direction shorter than the first dimension; and', 'a peripheral region of the second surface extending between the peripheral edge and one of the openings;, 'a substrate havinga first microelectronic element having a front surface facing toward the first surface and bond pads at the front surface aligned with the first opening, a rear surface opposite from the front surface, and an edge extending between the front and rear surfaces;a second microelectronic element having a front surface facing toward the rear surface of the first microelectronic element and projecting ...

Semiconductor device

The reliability of a semiconductor device is improved. A package of a semiconductor device internally includes a first semiconductor chip and a second semiconductor chip in which power MOS•FETs are formed and a third semiconductor chip in which a control circuit controlling the first and second semiconductor chips is formed. The first to third semiconductor chips are mounted on die pads respectively. Source electrode bonding pads of the first semiconductor chip on a high side are electrically connected with a first die pad of the die pads via a metal plate. On a top surface of the die pad 7 D 2 , a plated layer formed in a region where the second semiconductor chip is mounted, and another plated layer formed in a region where the metal plate is joined are provided and the plated layers are separated each other with a region where no plated layer is formed in between.

Discrete power transistor package having solderless dbc to leadframe attach

A packaged power transistor device includes a Direct-Bonded Copper (“DBC”) substrate. Contact pads of a first lead are attached with solderless welds to a metal layer of the DBC substrate. In a first example, the solderless welds are ultrasonic welds. In a second example, the solderless welds are laser welds. A single power transistor realized on a single semiconductor die is attached to the DBC substrate. In one example, a first bond pad of the die is wire bonded to a second lead, and a second bond pad of the die is wire bonded to a third lead. The die, the wire bonds, and the metal layer of the DBC substrate are covered with an amount of plastic encapsulant. Lead trimming is performed to separate the first, second and third leads from the remainder of a leadframe, the result being the packaged power transistor device.

CHIP ASSEMBLY SYSTEM

An assembly of semiconductor wafers/chips wherein the adjacent surfaces of the two wafers/chips comprise an insulating layer having opposite copper pads inserted therein. The insulating layer is made of a material selected from the group including silicon nitride and silicon carbon nitride. 112. An assembly of semiconductor wafers/chips wherein the adjacent surfaces of two wafers/chips (W , W) each comprise a silicon oxide layer having copper pads formed therein , wherein the silicon oxide layer is coated , outside of regions in which the copper pads are formed , with a silicon nitride or silicon carbon nitride layer thinner than the thickness of the copper pads.212. The assembly of semiconductor wafers/chips of claim 1 , wherein the opposite surfaces of the copper pads (Pi claim 1 , Pi) are nitrided-silicided.312. The assembly of semiconductor wafers/chips of claim 1 , wherein the opposite surfaces of the copper pads (Pi claim 1 , Pi) are coated with CoWP.4. The assembly of semiconductor chips/wafers of claim 1 , wherein the pads are regularly distributed on each of the wafers/chips claim 1 , at least some of the pads being electrically unconnected.5. The assembly of claim 1 , wherein several first chips are associated with a same second chip.6. The assembly of claim 5 , wherein the second Chip belongs to a semiconductor wafer comprising an assembly of second chips. This application is a translation of and claims the priority benefit of French patent application number 12/51362, filed on Feb. 14, 2012, entitled “CHIP ASSEMBLY SYSTEM,” which is hereby incorporated by reference to the maximum extent allowable by law.The present disclosure relates to the field of three-dimensional integrated circuits. Indeed, to increase the integration level of semiconductor components, there is a tendency to form integrated circuits made of a stack of chips.very schematically show a three-dimensional assembly of semiconductor components. A first semiconductor element (chip or wafer) ...

SEMICONDUCTOR DEVICE

A semiconductor device includes a semiconductor element having a substrate of GaAs, InP, or GaN, and an element securing member bonded to the semiconductor element by solder. The element securing member is a composite material of Cu and carbon or a composite of Al and carbon. 1. A semiconductor device comprising:a semiconductor element having a substrate of one of GaAs, InP, and GaN; andan element securing member bonded to said semiconductor element by solder and composed of a composite of Cu and carbon.2. The semiconductor device according to claim 1 , wherein said composite material is obtained by sintering Cu and carbon fiber.3. The semiconductor device according to claim 1 , further comprising a barrier metal layer of Ti or Pt on a surface of said element securing member and an Au layer on a surface of said barrier metal layer claim 1 , wherein said solder is located between said Au layer and said semiconductor element.4. The semiconductor device according to claim 1 , further comprising:a radiator block connected to said element securing member,a stem connected to said radiator block, anda cap secured to said stem and covering said semiconductor element, saidelement securing member, and said radiator block.5. The semiconductor device according to claim 1 , further comprising a stem connected to said element securing member claim 1 , and a cap secured to said stem and covering said semiconductor element and said element securing member.6. The semiconductor device according to claim 4 , wherein said stem is the same material as said element securing member.7. The semiconductor device according to claim 5 , wherein said stem and said element securing member are integral and the same material.8. The semiconductor device according to claim 6 , further comprising an iron layer on a surface of said stem claim 6 , wherein said cap is welded to said iron layer and thereby secured to said stem.9. The semiconductor device according to claim 1 , further comprising a frame ...

Rectifierarrangement having schottky diodes

A rectifier system having press-in diodes that contain a Schottky diode as semiconductor element. The Schottky diodes are operated in an operating range in which the diode losses increase as the temperature increases.

Method of Manufacturing a Semiconductor Device with a Carrier Having a Cavity and Semiconductor Device

A method includes providing a carrier having a first cavity, providing a dielectric foil with a metal layer attached to the dielectric foil, placing a first semiconductor chip in the first cavity of the carrier, and applying the dielectric foil to the carrier.

SUBSTRATE STRUCTURE, METHOD OF MOUNTING SEMICONDUCTOR CHIP, AND SOLID STATE RELAY

This invention provides a substrate structure that can effectively prevent scattering of solder balls which are produced due to explosion attributable to evaporation of flux during reflow soldering, and spreading of molten solder to the surroundings. On a substrate, a semiconductor chip is mounted via solder paste. The substrate is provided with a groove portion which continuously or discontinuously surrounds the solder paste. 1. A substrate structure comprising:a substrate;a groove portion on said substrate for surrounding a solder paste, said groove portion and solder paste for mounting a semiconductor device.2. The substrate structure according to claim 1 , wherein the groove portion is formed within an area of the substrate to be occupied by the semiconductor chip.3. The substrate structure according to claim 2 , wherein the groove portion has a depth equal to or less than ½ of a thickness of the substrate.4. The substrate structure according to claim 2 , wherein a width of an opening in a surface of the substrate is larger than a depth of the groove portion.5. The substrate structure according to claim 4 , wherein the groove portion has a depth equal to or less than ½ of a thickness of the substrate.6. The substrate structure according to claim 1 , wherein the groove portion has a depth equal to or less than ½ of a thickness of the substrate.7. The substrate structure according to claim 1 , wherein a total volume of the groove portion in the substrate is larger than a volume of flux to be evaporated when the solder paste melts.8. The substrate structure according to claim 1 , wherein a volume of a portion of the groove portion which corresponds to a corner of the semiconductor chip to be mounted is larger than any other portions.9. The substrate structure according to claim 1 , wherein the substrate is a Direct Copper Bonding substrate or a Direct Bonding Copper substrate.10. A method of mounting a semiconductor chip claim 1 , the method comprising:forming a ...

Power semiconductor module

A power semiconductor module includes a first power device on a substrate, a first electrode on an upper surface of the first power device, a first nickel plating layer on the first electrode, and a copper wire connected to the first nickel plating layer.

SEMICONDUCTOR DEVICE

In a semiconductor device, a first metal plate faces a first semiconductor element and a second semiconductor element and is electrically connected to a second terminal. A second metal plate faces the first metal plate while interposing the first semiconductor element between the first and second metal plates, and is electrically connected to a first terminal. A third metal plate faces the first metal plate while interposing the second semiconductor element between the first and third metal plates. The first semiconductor element has an electrode on a surface adjacent to the second metal plate and electrically connected to the second metal plate, and an electrode on a surface adjacent to the first metal plate and electrically connected to the third metal plate. The first semiconductor element is thermally connected to the first metal plate while being electrically insulated from the first metal plate by an insulator. 1. A semiconductor device comprising:a first semiconductor element;a second semiconductor element connected in series with the first semiconductor element;a first terminal;a second terminal, the second terminal and the first terminal allowing a current to flow between the second terminal and the first terminal;a first metal plate arranged to face both the first semiconductor element and the second semiconductor element and electrically connected to the second terminal;a second metal plate arranged to face the first metal plate and to interpose the first semiconductor element between the first metal plate and the second metal plate, and electrically connected to the first terminal;a third metal plate arranged to face the first metal plate and to interpose the second semiconductor element between the first metal plate and the third metal plate; anda sealing resin body covering the first semiconductor element, the second semiconductor element, the first metal plate, the second meal plate and the third metal plate, whereinthe second semiconductor element ...

METHOD FOR CAPPING CU LAYER USING GRAPHENE IN SEMICONDUCTOR

An interconnect structure includes a substrate, a dielectric layer on the substrate, a metal interconnect layer in the dielectric layer and in contact with the substrate, the metal interconnect layer having an upper surface flush with an upper surface of the dielectric layer, and a graphene layer on the metal interconnect layer. The graphene layer insulates a metal from air and prevents the metal from being oxidized by oxygen in the air, thereby increasing the queue time for the CMP process and the device reliability. 1. A method of manufacturing an interconnect structure , the method comprising:providing a semiconductor structure comprising a substrate, a dielectric layer on the substrate, and a metal interconnect layer in the dielectric layer and in contact with the substrate; andforming a graphene layer on the metal interconnect layer.2. The method of claim 1 , wherein forming the graphene layer comprises forming an amorphous carbon layer on the dielectric layer claim 1 , the amorphous carbon layer being adjacent to the graphene layer.3. The method of claim 1 , wherein forming the graphene layer comprises introducing methane and a carrier gas into a reaction chamber to form a mixed gas claim 1 , the mixed gas having a volume ratio of methane in a range between 0.1% and 50% claim 1 , at a temperature in a range between 300° C. and 450° C. claim 1 , under a pressure in a range between 0.1 mTorr and 10 Torr claim 1 , and a radio frequency power in a range between 10 W and 1000 W.4. The method of claim 3 , wherein the carrier gas comprises nitrogen claim 3 , or hydrogen claim 3 , or nitrogen and hydrogen.5. The method of claim 1 , further comprising claim 1 , prior to forming the graphene layer: performing a hydrogen plasma cleaning process on an upper surface of the metal interconnect layer.6. The method of claim 5 , wherein performing the hydrogen plasma cleaning process comprises: introducing a hydrogen gas into a reaction chamber at a flow rate in a range between ...

CORE-SHELL PARTICLES FOR MAGNETIC PACKAGING

A package substrate may include a build-up layer. The build-up layer may include a dielectric material and one or more microspheres. The one or more microspheres may include a magnetic core that includes a first material that is a first oxidation-resistant material. Further, the one or more microspheres may include a shell to encapsulate the core, and the shell may include a second material that is a second oxidation-resistant material. The package substrate may further include a metal layer coupled with the build-up layer. 1. A package substrate , comprising: a dielectric material; and', 'one or more microspheres, wherein the one or more microspheres include a magnetic core that includes a first material that is a first oxidation-resistant material,, 'a build-up layer comprisingwherein the one or more microspheres include a shell to encapsulate the core, andwherein the shell includes a second material that is a second oxidation-resistant material; anda metal layer coupled with the build-up layer.2. The package substrate of claim 1 , wherein the first material is cobalt-tantalum-zirconium claim 1 , neodymium-iron-carbon claim 1 , or cobalt-iron-carbon.3. The package substrate of claim 1 , wherein the first material is iron claim 1 , cobalt claim 1 , or nickel.4. The package substrate of claim 1 , wherein the first material is a polymer that includes iron claim 1 , and wherein the polymer is a polyimide claim 1 , polyester claim 1 , polyphenol claim 1 , or poly cyclic-olefin.5. The package substrate of claim 1 , wherein the second material is copper claim 1 , silver claim 1 , gold claim 1 , platinum claim 1 , palladium claim 1 , titanium claim 1 , or chromium.6. The package substrate of claim 1 , wherein the build-up layer further comprises silica filler material.7. The package substrate of claim 1 , wherein the metal layer is copper claim 1 , tungsten claim 1 , or aluminum.8. A build-up layer claim 1 , comprising:a dielectric material; andone or more microspheres, ...

Apparatus and Method for Processing a Semiconductor Substrate

A method includes placing a semiconductor substrate on a first curved surface of a first bending tool, using a second bending tool with a second surface to apply pressure to the semiconductor substrate, thereby pressing the semiconductor substrate onto the first curved surface and bending the semiconductor substrate, and removing the bended semiconductor substrate from the first bending tool.

Power semiconductor device and method for manufacturing power semiconductor device

This power semiconductor device is provided with: a substrate; and a semiconductor element which is bonded onto the substrate using a sinterable metal bonding material. The semiconductor element comprises: a base; a first conductive layer that is provided on a first surface of the base, said first surface being on the substrate side; and a second conductive layer that is provided on a second surface of the base, said second surface being on the reverse side of the first surface. The thickness of the first conductive layer is from 0.5 times to 2.0 times (inclusive) the thickness of the second conductive layer.

SEMICONDUCTOR DEVICE

A semiconductor device according to the present invention includes a base plate, an insulating layer provided on an upper surface of the base plate, a metal pattern provided on an upper surface of the insulating layer, a semiconductor element bonded to the metal pattern, and an insulating substrate disposed to be in contact with an upper surface of the semiconductor element. An end of the insulating substrate is located outside the semiconductor element in plan view. The end of the insulating substrate and the metal pattern are directly or indirectly bonded. The semiconductor element includes an electrode on the upper surface. A portion of the insulating substrate, in which the electrode on the upper surface of the semiconductor element overlaps in plan view, is provided with a through-hole. 1. A semiconductor device , comprising:a base plate;an insulating layer provided on an upper surface of said base plate;a metal pattern provided on an upper surface of said insulating layer;at least one semiconductor element bonded to said metal pattern; andan insulating substrate disposed to be in contact with an upper surface of said at least one semiconductor element, whereinan end of said insulating substrate is located outside said at least one semiconductor element in plan view,said end of said insulating substrate and said metal pattern are directly or indirectly bonded,said at least one semiconductor element includes an electrode on the upper surface of said at least one semiconductor element, anda portion of said insulating substrate, in which said electrode on the upper surface of said at least one semiconductor element overlaps in plan view, is provided with a through-hole.2. The semiconductor device according to claim 1 , further comprising a metal frame provided on an upper surface of said metal pattern claim 1 , whereinsaid metal frame is provided so as to surround said at least one semiconductor element in plan view, andsaid end of said insulating substrate and ...

Power Semiconductor Package with Multiple Dies

A semiconductor package that includes a substrate having a metallic back plate, an insulation body and a plurality of conductive pads on the insulation body, and a semiconductor die coupled to said conductive pads, the conductive pads including regions readied for direct connection to pads external to the package using a conductive adhesive. 112-. (canceled)13. A semiconductor package comprising:a first power semiconductor die that includes a first electrode on a surface thereof;a second power semiconductor die that includes a first electrode on a surface thereof;a support plate having a first surface and a second surface opposite said first surface;an insulation body disposed on said first surface of said support plate; anda plurality of laterally spaced conductive pads on said insulation body, a first one of said conductive pads including a first region electrically and mechanically coupled to said first electrode of said first semiconductor die with a conductive adhesive body interposed between said first electrode and said first region and a second region readied for connection using a conductive adhesive body to a conductive pad external to said package, and a second one of said conductive pads including a first region electrically and mechanically coupled to said first electrode of said second semiconductor die with a conductive adhesive body interposed between said first electrode and said first region and a second region readied for connection using a conductive adhesive body to a conductive pad external to said package.14. The package of claim 13 , wherein each said first and second semiconductor die includes a second electrode lateral to said first electrode on said first surface thereof claim 13 , each said second electrode being electrically and mechanically coupled to a first region of a respective conductive pad with a conductive adhesive body interposed between said second electrode and said first region of said respective conductive pad claim 13 , ...

Semiconductor module

A semiconductor module includes a semiconductor device having a gate runner extending in a first direction at an upper surface of the semiconductor device, and a metal wiring plate having a first bonding portion with a bonding surface to which the upper surface of the semiconductor device is bonded via a first bonding material. The first bonding portion has a plurality of first protrusions at the bonding surface. Each first protrusion protrudes toward the semiconductor device, and is provided in a position away from the gate runner by a first distance in a plan view of the semiconductor module.

SEMICONDUCTOR DEVICE

The semiconductor device includes a semiconductor element, a main lead and a resin package. The semiconductor element includes an obverse surface and a reverse surface spaced apart from each other in a thickness direction. The main lead supports the semiconductor element via the reverse surface of the semiconductor element. The resin package covers the entirety of the semiconductor element. The resin package covers the main lead in such a manner that a part of the main lead is exposed from the resin package. The semiconductor element includes a part that does not overlap the main lead as viewed in the thickness direction. 172-. (canceled)73. A semiconductor device comprising:a semiconductor element;a main lead on which the semiconductor element is disposed;a first sublead spaced apart from the main lead and electrically connected to the semiconductor element; anda resin package covering the semiconductor element, the main lead and the first sublead and having a rectangular shape as viewed in a thickness direction of the semiconductor element;wherein the resin package has a first surface and the second surface, the first surface having a normal direction parallel to the thickness direction, the second surface having a normal direction crossing the thickness direction,the main lead and the first sublead are exposed from the first surface of the resin package,the main lead and the first sublead have a first portion and a second portion, respectively, that are exposed from the second surface of the resin package, and the first portion and the second portion are different from each other in size measured in the thickness direction.74. The semiconductor device according to claim 73 , wherein the semiconductor element includes a part that does not overlap with the main lead as viewed in the thickness direction.75. The semiconductor device according to claim 73 , wherein the main lead has a main-lead obverse surface and a main-lead reverse surface claim 73 ,the ...

Semiconductor Package with Integrated Semiconductor Devices and Passive Component

According to one exemplary embodiment, a semiconductor package includes a substrate having lower and upper surfaces. The semiconductor package further includes at least one passive component coupled to first and second conductive pads on the upper surface of the substrate. The semiconductor package further includes at least one semiconductor device coupled to a first conductive pad on the lower surface of the substrate. The at least one semiconductor device has a first electrode for electrical and mechanical connection to a conductive pad external to the semiconductor package. The at least one semiconductor device can have a second electrode electrically and mechanically coupled to the first conductive pad on the lower surface of the substrate. 110-. (canceled)11. A semiconductor package comprising:a substrate having lower and upper surfaces;at least one passive component coupled to first and second conductive pads on said upper surface of said substrate;a first semiconductor device coupled to a first conductive pad on said lower surface of said substrate;a second semiconductor device coupled to a second conductive pad on said lower surface of said substrate;said first semiconductor device having a first electrode for electrical and mechanical connection to a conductive pad external to said semiconductor package using a conductive adhesive.12. The semiconductor package of claim 11 , wherein said second semiconductor device has a first electrode for electrical and mechanical connection to another conductive pad external to said semiconductor package.13. The semiconductor package of claim 11 , wherein said first semiconductor device has a second electrode electrically and mechanically coupled to said first conductive pad on said lower surface of said substrate.14. The semiconductor package of claim 13 , wherein said first semiconductor device has a third electrode situated adjacent to said first electrode.15. The semiconductor package of claim 12 , wherein said second ...

SEMICONDUCTOR PACKAGE WITH CONDUCTIVE CLIP

A semiconductor package that includes a conductive can, a power semiconductor device electrically and mechanically attached to the inside surface of the can, and an IC semiconductor device copackaged with the power semiconductor device inside the can. 117-. (canceled)18. A method comprising:forming at least one terminal for a semiconductor package;forming a dielectric body to electrically insulate said at least one terminal from a conductive clip of said semiconductor package;connecting a power electrode of a power semiconductor device to said conductive clip.19. The method of further comprising depositing a solder resist over at least a portion of said at least one terminal.20. The method of further comprising forming a conductive pad for said semiconductor package.21. The method of further comprising forming a track to connect said conductive pad to said at least one terminal.22. The method of claim 18 , wherein said conductive clip is plated with either gold or silver.23. The method of claim 18 , wherein said dielectric body comprises polymer.24. The method of claim 18 , wherein said dielectric body comprises dielectric particles in an organic base.25. The method of claim 24 , wherein said organic base comprises one of epoxy claim 24 , acrylate claim 24 , polyimide and organopolysiloxane.26. The method of claim 24 , wherein said dielectric particles comprise a metal oxide.27. The method of claim 26 , wherein said metal oxide is alumina. This application is a continuation of U.S. application Ser. No. 11/799,140, filed May 1, 2007, entitled Semiconductor Package which is a division of U.S. application Ser. No. 11/405,825, filed Apr. 18, 2006, entitled Semiconductor Package which is based on and claims benefit of U.S. Provisional Application No. 60/674,162, filed on Apr. 21, 2005, entitled Semiconductor Package, to which a claim of priority is hereby made and the disclosure of which is incorporated by reference.The present invention relates to semiconductor packages ...

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME

A semiconductor device includes a base and a conductive layer to form a composite substrate. The conductive layer covers a surface of the base. The semiconductor device also includes a dielectric layer covering the conductive layer. The conductive layer is disposed between the dielectric layer and the base. The semiconductor device further includes a GaN-containing composite layer, a gate electrode disposed over the GaN-containing composite layer, a source electrode and a drain electrode disposed on the GaN-containing composite layer. The source electrode and the drain electrode are disposed at two opposite sides of the gate electrode. In addition, a method for manufacturing the semiconductor device with a composite substrate is provided. 1. A semiconductor device , comprising:a composite substrate comprising a base and a conductive layer, wherein the conductive layer continuously contacts and covers a surface of the base;a dielectric layer covering the conductive layer, wherein the conductive layer is disposed between the dielectric layer and the base;a GaN-containing composite layer disposed on the composite substrate;a gate electrode disposed on the GaN-containing composite layer;a source electrode and a drain electrode disposed on the GaN-containing composite layer and at two opposite sides of the gate electrode.2. The semiconductor device as claimed in claim 1 , wherein the conductive layer comprises a metal claim 1 , an alloy claim 1 , a metal nitride claim 1 , polysilicon or a combination thereof.3. The semiconductor device as claimed in claim 1 , wherein the conductive layer comprises Ti claim 1 , Ta claim 1 , W claim 1 , Nb claim 1 , Mo claim 1 , V claim 1 , an alloy or a nitride comprising a metal thereof.4. The semiconductor device as claimed in claim 1 , wherein the conductive layer comprises Ti claim 1 , Ta claim 1 , W claim 1 , Nb claim 1 , Mo claim 1 , V claim 1 , TaAl claim 1 , TiW claim 1 , TiN claim 1 , TaN claim 1 , TiAlN claim 1 , TaAlN claim 1 , ...

ELECTRONIC APPARATUS

An electronic apparatus includes: a first metal layer; an electronic component that is provided on the first metal layer; a second metal layer that is provided on the first metal layer and on the electronic component; and an insulating resin that fills a space between the first metal layer and the second metal layer so as to cover the electronic component. The second metal layer includes: a sheet-like electrode pad portion; and a connection portion that is disposed along a peripheral edge of the electrode pad portion, and that protrudes from the electrode pad portion toward the first metal layer so as to electrically connect the second metal layer to the first metal layer. 1. An electronic apparatus comprising:a first metal layer;an electronic component that is provided on the first metal layer;a second metal layer that is provided on the first metal layer and on the electronic component; andan insulating resin that fills a space between the first metal layer and the second metal layer so as to cover the electronic component,wherein the second metal layer comprises:a sheet-like electrode pad portion; anda connection portion that is disposed along a peripheral edge of the electrode pad portion, and that protrudes from the electrode pad portion toward the first metal layer so as to electrically connect the second metal layer to the first metal layer.2. The electronic apparatus according to claim 1 , whereinthe connection portion is higher in height than the electronic component.3. The electronic apparatus according to claim 1 , whereinthe electrode pad portion overlaps with the electronic component in plan view, and has a face exposed from the insulating resin.4. The electronic apparatus according to claim 1 , whereinthe electrode pad portion is formed into a rectangular shape, andthe connection portion is disposed along one side of the electrode pad portion.5. The electronic apparatus according to claim 1 , whereinthe first metal layer comprises:a placement portion ...

Package for mounting light-emitting device

A light-emitting device mounting package includes a substrate, a lead pin supported on the substrate, and an insulating member having a facing front surface which faces the front surface of the substrate and a facing back surface. The substrate has a first through hole and the ceramic plate has a second through hole. The lead pin has a shaft portion which penetrates the first and second through holes, a head portion provided at one end of the shaft portion, and a collar portion which extends from the shaft portion in the radial direction. The lead pin is fixed, via the collar portion, to a region of the facing back surface of the ceramic plate around an opening of the second through hole, and the ceramic plate is fixed to a region of the front surface of the substrate around an opening of the first through hole.

NON-EMBEDDED SILICON BRIDGE CHIP FOR MULTI-CHIP MODULE

A semiconductor structure includes a free-floating silicon-bridge chip electrically joined on a top portion to two or more semiconductor chips and electrically joined on a bottom portion to a substrate structure that includes a plurality of metal interconnect structures and a plurality of metal layers disposed on an interlevel dielectric. The silicon bridge chip is aligned with and extends into a recess located in a region of the substrate structure away from the plurality of metal interconnect structures and the plurality of metal layers such that a top surface of the silicon bridge chip is substantially flush with a top surface of the substrate structure. 1. A semiconductor structure comprising:a silicon-bridge chip comprising a free-floating device electrically joined on a top portion to two or more semiconductor chips and electrically joined on a bottom portion to a substrate structure, the substrate structure comprising a plurality of metal interconnect structures and a plurality of metal layers disposed on an interlevel dielectric,a region of the substrate structure having a recess, the silicon bridge chip being aligned with and extending into the recess, the region of the substrate structure being away from the plurality of metal interconnect structures and the plurality of metal layers such that a top surface of the silicon bridge chip is substantially flush with a top surface of the substrate structure.2. The semiconductor structure of claim 1 , further comprising:a lid attached to the top surface of the substrate structure and a bottom surface of the two or more semiconductor chips; anda plurality of solder bumps on a bottom surface of the substrate structure.3. The semiconductor structure of claim 1 , further comprising:an adhesive material between a bottom surface of the silicon bridge chip and a top surface of the substrate structure located directly below the silicon bridge chip, wherein the adhesive material physically joins the silicon bridge chip to ...

Semiconductor power device including wire or ribbon bonds over device active region

A semiconductor power device including a base plate; an input lead; an output lead; a field effect transistor (FET) power die disposed over the base plate, wherein the FET power die includes a set of source fingers, a set of drain fingers, and a set of gate fingers disposed directly over an active region, wherein the gate fingers are configured to receive an input signal from the input lead, and wherein the FET power die is configured to process the input signal to generate an output signal at the drain fingers for routing to the output lead; and electrical conductors (wirebonds or ribbons) bonded to the source and/or drain directly over the active region of the FET power die. The electrical conductors produce additional thermal paths between the active region and the base plate for thermal management of the FET power die.

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD

A semiconductor device includes a semiconductor element; an insulating substrate formed from stacking a rectangular shaped circuit plate, insulating plate, and metal plate, wherein the semiconductor element is fixed to the circuit plate, and the metal plate has at least one first groove portion in four corners thereof; a radiating member made of metal and having a predetermined arrangement area to dispose the insulating substrate, the radiating member having at least one second groove portion provided in four corners of the arrangement area; four positioning members disposed between the four corners of the metal plate and the four corners of the radiating member, each of the four positioning members being fitted to each of the first groove portions and second groove portions; and a solder filling a space between the insulating substrate and the radiating member, and covering the positioning members.

SEMICONDUCTOR DEVICE AND CASING OF THE SEMICONDUCTOR DEVICE

A semiconductor device includes a box-shaped casing including a ceiling wall with a first window, a semiconductor chip having an output electrode and assembled in the casing, a first conductive block disposed in the casing, and a first connection terminal being bent so as to implement an elongated U-shape. The semiconductor device is adapted for electrical connection to a circuit board having a first land. The circuit board is placed on the ceiling wall. The first window is at a position corresponding to the first land. A lower end of the first conductive block is connected to a surface of the output electrode and the first connection terminal contacts to the first conductive block. 1. A semiconductor device for electrical connection to a circuit board having a first land , comprising:a box-shaped casing including a ceiling wall, on which the circuit board is placed, the ceiling wall is provided with a first window at a position corresponding to the first land;a semiconductor chip assembled in the casing, the semiconductor chip having an output electrode;a first conductive block disposed in the casing, a lower end of the first conductive block being connected to a surface of the output electrode; anda first connection terminal being bent so as to implement an elongated U-shape in a cross-sectional view, configured to provide a pair of opposite surfaces in the U-shape, the first connection terminal is scheduled to be connected to the first land through an upper end implemented by a bottom of the U-shape via the first window, both sides of an upper part of the first conductive block being interposed between the opposite surfaces at a lower end implemented by a top of the U-shape, the first connection terminal contacts to the first conductive block through the opposite surfaces.2. The semiconductor device according to claim 1 , further comprising:a pair of supporting side-walls fixed to the casing of the semiconductor device, the supporting side-walls covering the ...

Chip packaging and composite system board

A chip packaging includes a substrate, a first chip, a molding material, a first circuit, and a second circuit. The substrate includes a bottom surface, a first top surface disposed above the bottom surface with a first height, and a second top surface disposed above the bottom surface with a second height. The first height is smaller than the second height. The first chip is disposed on the first top surface. The molding material is disposed on the substrate and covers the first chip. The first and second circuits are disposed on the molding material, and are respectively and electrically connected to the first chip and the second top surface of the substrate. The substrate is made of copper material with huge area and has the properties of high current withstand capacity and high thermal efficiency. The second top surface protects the first chip from damage.

Packaging structure of a semiconductor device

A method of making a semiconductor packaged device comprises mounting onto a lead frame a bottom of a molded semiconductor chip having a first plastic package body covering a top face of a semiconductor chip, encapsulating the lead frame and the semiconductor chip with a second plastic package body with top surfaces of conductive contact bodies electrically connected to electrodes on the top surface of the semiconductor chip exposed and plating conductive pads on a top surface of the assembly structure to provide external electrical connections to the electrodes through the conductive contact bodies.

CONDUCTIVE BUMP AND ELECTROLESS Pt PLATING BATH

The present invention provides a bump that can prevent diffusion of a metal used as a base conductive layer of the bump into a surface of an Au layer or an Ag layer. A conductive bump of the present invention is a conductive bump formed on a substrate. The conductive bump comprises, at least in order from the substrate: a base conductive layer; a Pd layer; a Pt layer; and an Au layer or an Ag layer having directly contact with the Pd layer, wherein a diameter of the conductive bump is 20 μm or less.

POWER SEMICONDUCTOR MODULE, METHOD FOR MANUFACTURING THE SAME, AND POWER CONVERTER

A power semiconductor module includes a metal plate having a through hole with an eaves; an insulated metal block including a metal block having an element mounting region on an upper surface, and an insulating layer on surfaces other than the upper surface and a portion of the upper surface other than the element mounting region; a circuit pattern disposed over the metal plate with the insulating material interposed therebetween; a power semiconductor element fixed to the element mounting region of the upper surface of the metal block; and a connection conductor connecting the power semiconductor element and the circuit pattern. The insulated metal block is fitted into the through hole in the metal plate so that the insulating layer on the upper surface of the insulated metal block contacts the eaves of the through hole to electrically insulate between the metal block and the metal plate. 1. A power semiconductor module comprising:a metal plate having a through hole with an eaves;an insulated metal block including a metal block having an element mounting region on an upper surface, and an insulating layer made of a ceramic material directly formed on surfaces other than the upper surface of the metal block and a portion other than the element mounting region on the upper surface, the insulated metal block being fitted into the through hole with the eaves in the metal plate so that an upper portion of the insulated metal block contacts the eaves of the through hole to electrically insulate between the metal block and the metal plate by the insulating layer;a circuit pattern disposed over the metal plate with the insulating material interposed therebetween;a power semiconductor element fixed to the element mounting region of the upper surface of the metal block; anda connection conductor connecting the power semiconductor element and the circuit pattern.2. The power semiconductor module according to claim 1 , wherein the insulated metal block further comprises a ...

SEMICONDUCTOR MODULE, SEMICONDUCTOR MODULE PACKAGE AND SEMICONDUCTOR APPARATUS

A semiconductor module comprising a plurality of electrically conductive top plates, an electrically conductive base plate, a plurality of semiconductor chips installed on the base plate, a first power supply connected to the plates, a second power supply connected to the plates and an electrically insulating outer casing component. The semiconductor chips are individually in contact with the top plates. Each semiconductor chip comprises a first electrode electrically coupled with the base plate, and a second electrical pole electrically coupled with the corresponding top plate. The first power supply connecting plate is equipped with protruding parts that are individually in electrical contact with the top plates. The second power supply connecting plate is electrically connected to the base plate. The outer casing component is used to integrate the first power supply connecting plate and the second power supply connecting plate. The outer casing component comprises at least one opening. 1. A semiconductor module , comprising:a plurality of conductive top plates;a conductive base plate;a plurality of semiconductor chips installed on the conductive base plate and contacting the conductive top plates respectively, each of the semiconductor chips comprising a first electrode electrically coupled to the conductive base plate and a second electrode electrically coupled to the corresponding conductive top plate;a first power supply connection plate;a plurality of protrusions extending from the first power supply connection plate and electrically connecting respective conductive top plates;a second power supply connection plate electrically connecting the conductive base plate; anda housing element for holding together the first power supply connection plate and the second power supply connection plate,wherein the housing element defines at least one opening.2. The semiconductor module of claim 1 , wherein an internal space of the semiconductor module is filled with an ...

SEMICONDUCTOR MODULE

A semiconductor module includes a printed circuit board having an insulating plate, first and fourth wiring layers disposed on a principal surface of the insulating plate, second and third wiring layers disposed on another surface opposite to the principal surface, a first via disposed in the insulating plate and electrically and mechanically connected to the first and third wiring layers, and a second via disposed in the insulating plate and electrically and mechanically connected to the second and fourth wiring layers; a first insulating substrate disposed with a first circuit plate; a second insulating substrate disposed with a second circuit plate; a first semiconductor chip; a second semiconductor chip; a first heat release member fixed between the third wiring layer and the third circuit plate; and a second heat release member fixed between the fourth wiring layer and the first circuit plate. 1. A semiconductor module , comprising: an insulating plate,', 'a first wiring layer and a fourth wiring layer disposed on a principal surface of the insulating plate,', 'a second wiring layer and a third wiring layer disposed on a surface opposite to the principal surface,', 'a first via disposed in the insulating plate, and electrically and mechanically connected to the first wiring layer and third wiring layer, and', 'a second via disposed in the insulating plate, and electrically and mechanically connected to the second wiring layer and the fourth wiring layer;, 'a printed circuit board having'}a first insulating substrate disposed facing the first wiring layer, and having a first circuit plate on a surface facing the first wiring layer and the fourth wiring layer;a second insulating substrate disposed facing the second wiring layer, and having a second circuit plate facing the second wiring layer and a third circuit plate facing the third wiring layer;a first semiconductor chip sandwiched between the first wiring layer and the first circuit plate, and having a ...

Power Semiconductor Module

A power semiconductor module includes a first main electrode, a second main electrode and a control terminal. The power semiconductor module includes controllable power semiconductor components arranged between the first main electrode and the second main electrode. At least some of the controllable power semiconductor components are arranged in a ring arrangement, wherein the controllable power semiconductor components of the ring arrangement are arranged at least approximately along a first circular line of the ring arrangement, and a control conductor track of the ring arrangement is arranged on the first main electrode, wherein the control conductor track runs at least approximately along a second circular line of the ring arrangement, and the second circular line runs concentrically relative to the first circular line. 1. A power semiconductor module comprising a first main electrode , a second main electrode , and a control terminal , and comprising controllable power semiconductor components arranged between the first main electrode and the second main electrode , wherein each controllable power semiconductor component has a first electrode , a second electrode and a control electrode , and the first electrode of each controllable power semiconductor component is electrically connected to the first main electrode , the second electrode of each controllable power semiconductor component is electrically connected to the second main electrode , and the control electrode of each controllable power semiconductor component is electrically connected to the control terminal , wherein at least some of the controllable power semiconductor components are arranged in a plurality of ring arrangements , characterized in that the controllable power semiconductor components of each ring arrangement of the plurality of ring arrangements are arranged at least approximately along a first circular line of the respective ring arrangement , and a control conductor track of the ...

Semiconductor Package Including Conductive Carrier Coupled Power Switches

In one implementation, a semiconductor package including conductive carrier coupled power switches includes a first vertical FET in a first active die having a first source and a first gate on a source side of the first active die and a first drain on a drain side of the first active die. The semiconductor package also includes a second vertical FET in a second active die having a second source and a second gate on a source side of the second active die and a second drain on a drain side of the second active die. The semiconductor package includes a conductive carrier attached to the source side of the first active die and to the drain side of the second active die, the conductive carrier coupling the first source to the second drain.

Semiconductor device

A semiconductor device includes: a first element formed of a first constituent as a main constituent; a second element formed of a second constituent as a main constituent; a heat sink on which the first element and the second element are disposed; a first connection layer electrically connecting the first element to the heat sink; a second connection layer electrically connecting the second element to the heat sink; and a mold resin covering and protecting the first element, the second element and the heat sink. Sizes of the first element and the second element are set so that an equivalent plastic strain increment of the first connection layer is greater than the second connection layer. Accordingly, in the semiconductor device including semiconductor elements formed of different constituents, the elements are thermally protected without providing a temperature detector to the semiconductor element formed of one of the constituents.

SOLDERING STRUCTURE AND POWER MODULE COMPRISING THE SAME

A soldering structure configured for preventing solder overflow during soldering and a power module, may include a component to be soldered; and a metal layer having a bonding area, to which the component to be soldered is bonded by solder, and a groove portion formed around the bonding area. 1. A soldering structure comprising:a component to be soldered; anda metal layer having a bonding area, to which the component to be soldered is bonded by solder, and a groove portion formed around the bonding area.2. The soldering structure of claim 1 , wherein the groove portion has a plurality of dimples surrounding the bonding area.3. The soldering structure of claim 2 , wherein a space between each of the plurality of dimples is smaller than a diameter of each of the plurality of dimples.4. The soldering structure of claim 2 , wherein a space between each of the plurality of dimples is smaller than or equal to half a diameter of each of the plurality of dimples.5. The soldering structure of claim 1 , wherein the component to be soldered is made of a metal material including copper (Cu) claim 1 , silver (Ag) claim 1 , gold (Au) or nickel (Ni).6. The soldering structure of claim 1 , wherein the component to be soldered has a surface plated with a metal material including copper (Cu) claim 1 , silver (Ag) claim 1 , gold (Au) or nickel (Ni).7. The soldering structure of claim 1 , wherein the component to be soldered has one surface facing the bonding area and a side surface perpendicular to the one surface claim 1 , and the solder extends to the side surface of the component to be soldered.8. A power module comprising:a component to be soldered; anda first substrate including a first metal layer, a dielectric layer and a second metal layer,wherein the first metal layer incudes an upper surface having a bonding area, to which the component to be soldered is bonded by solder, and a groove portion formed around the bonding area,wherein the dielectric layer is bonded to a lower ...

Apparatus and Method for Bending a Substrate

A method includes placing a substrate on a first curved surface of a first bending tool, using a second bending tool with a second surface to apply pressure to the substrate, thereby pressing the substrate onto the first curved surface and bending the substrate, and removing the bended substrate from the first bending tool.

SEMICONDUCTOR PACKAGE

Provided is a semiconductor package including a substrate; at least one semiconductor chip mounted on the substrate; a molding element, which is arranged on the substrate and encapsulates the at least one semiconductor chip; and a lattice element, which is arranged inside the molding element, where the lattice element includes a body having a plurality of openings. 1. A semiconductor package comprising:a substrate;at least one semiconductor chip mounted on the substrate;a molding element encapsulating the at least one semiconductor chip; anda lattice element arranged inside the molding element,wherein the lattice element comprises a rigid body comprising a plurality of openings.2. The semiconductor package of claim 1 , wherein the lattice element further comprises a plurality of supports extending from the substrate to the body.3. The semiconductor package of claim 2 , wherein the lattice element comprises a conductive material claim 2 , andwherein the supports are electrically connected to the substrate.4. The semiconductor package of claim 2 , wherein the plurality of openings are defined by first ribs and second ribs that intersect with each other substantially perpendicularly claim 2 , andwherein the supports and the body contact each other substantially perpendicularly.5. The semiconductor package of claim 2 , wherein the plurality of openings exist in an area between adjacent supports.6. The semiconductor package of claim 5 , wherein an area of each of the openings is smaller than an area of a top surface of the at least one semiconductor chip.7. The semiconductor package of claim 1 , wherein a mechanical strength of the lattice element is greater than a mechanical strength of the molding element.8. The semiconductor package of claim 1 , wherein a distance between the top surface of substrate to the body is greater than a distance between the top surface of substrate to the at least one semiconductor chip.9. A semiconductor package comprising:a substrate;at ...

Encapsulated electronic chip device with mounting provision and externally accessible electric connection structure

An electronic device comprising a carrier having a mounting surface, at least one electronic chip mounted on the mounting surface, at least one electric connection structure mounted on the mounting surface, an encapsulant at least partially encapsulating the carrier and the at least one electronic chip, and partially encapsulating the at least one electric connection structure so that part of a surface of the at least one electric connection structure is exposed to an environment, and a mounting provision configured for mounting the electronic device at a periphery device. 1. An electronic device , the device comprising:a carrier having a mounting surface;at least one electronic chip mounted on the mounting surface;at least one electric connection structure mounted on the mounting surface;an encapsulant at least partially encapsulating the carrier and the at least one electronic chip, and partially encapsulating the at least one electric connection structure so that part of a surface of the at least one electric connection structure is exposed to an environment;a mounting provision configured for mounting the electronic device at a periphery device.2. The device according to claim 1 , wherein the mounting provision is exclusively defined by the encapsulant.3. The device according to claim 1 , wherein the mounting provision is at least partially claim 1 , in particular exclusively claim 1 , defined by a separate reinforcement body.4. The device according to claim 3 , wherein the reinforcement body is at least partially encapsulated within the encapsulant.5. The device according to claim 3 , wherein the reinforcement body is connected to the carrier claim 3 , in particular is electrically coupled with the carrier.6. The device according to claim 3 , wherein the reinforcement body is configured as a sleeve.7. The device according to claim 3 , wherein the reinforcement body is configured as a profile claim 3 , in particular as one of the group consisting of an at least ...

Semiconductor Package Having Symmetrically Arranged Power Terminals and Method for Producing the Same

A double-sided coolable semiconductor package includes an upper electrically conductive element having an outwardly exposed metal surface, a lower carrier substrate having an upper electrically conductive layer, a lower electrically conductive layer having an outwardly exposed surface, and an electrical insulation layer arranged between the electrically conductive layers, a first electrically conductive spacer arranged between the upper electrically conductive element and the upper electrically conductive layer, a power semiconductor chip arranged between the upper electrically conductive element and the upper electrically conductive layer, a second electrically conductive spacer arranged between the upper electrically conductive element and the chip, and power terminals arranged along a first side of the package. A second power terminal is arranged between first and third power terminals. The first and third power terminals are configured to apply a first supply voltage. The second power terminal is configured to apply a second supply voltage. 1. A double-sided coolable semiconductor package , comprising:an upper electrically conductive element having an outwardly exposed metal surface;a lower carrier substrate having an upper electrically conductive layer, a lower electrically conductive layer having an outwardly exposed surface, and an electrical insulation layer arranged between the upper and lower electrically conductive layers;a first electrically conductive spacer arranged between the upper electrically conductive element and the upper electrically conductive layer;a power semiconductor chip arranged between the upper electrically conductive element and the upper electrically conductive layer;a second electrically conductive spacer arranged between the upper electrically conductive element and the power semiconductor chip; anda first power terminal, a second power terminal and a third power terminal arranged along a first side of the double-sided coolable ...

SEMICONDUCTOR PACKAGE HAVING OVERLAPPING ELECTRICALLY CONDUCTIVE REGIONS AND METHOD FOR PRODUCING THE SAME

A semiconductor package includes an upper electrically conductive element having a lower carrier substrate having an upper electrically conductive layer, a lower electrically conductive layer having an outwardly exposed surface, and an electrical insulation layer arranged between the electrically conductive layers, a first electrically conductive spacer arranged between the upper electrically conductive element and the upper electrically conductive layer, a power semiconductor chip arranged between the upper electrically conductive element and the upper electrically conductive layer, and a second electrically conductive spacer arranged between the upper electrically conductive element and the chip. A first carrier region of the upper electrically conductive layer is configured to apply a positive supply voltage. A second carrier region alongside the first carrier region is configured as a phase. A first region of the upper electrically conductive element is configured to apply a negative supply voltage, and at least partly overlaps the first carrier region. 1. A double-sided coolable semiconductor package , comprising:an upper electrically conductive element having an outwardly exposed metal surface;a lower carrier substrate having an upper electrically conductive layer, a lower electrically conductive layer having an outwardly exposed surface, and an electrical insulation layer arranged between the upper and lower electrically conductive layers;a first electrically conductive spacer arranged between the upper electrically conductive element and the upper electrically conductive layer;a power semiconductor chip arranged between the upper electrically conductive element and the upper electrically conductive layer; anda second electrically conductive spacer arranged between the upper electrically conductive element and the power semiconductor chip,wherein a first carrier region of the upper electrically conductive layer of the lower carrier substrate is configured to ...

THROUGH-BODY-VIA ISOLATED COAXIAL CAPACITOR AND TECHNIQUES FOR FORMING SAME

Techniques are disclosed for forming a through-body-via (TBV) isolated coaxial capacitor in a semiconductor die. In some embodiments, a cylindrical capacitor provided using the disclosed techniques may include, for example, a conductive TBV surrounded by a dielectric material and an outer conductor plate. The TBV and outer plate can be formed, for example, so as to be self-aligned with one another in a coaxial arrangement, in accordance with some embodiments. The disclosed capacitor may extend through the body of a host die such that its terminals are accessible on the upper and/or lower surfaces thereof. Thus, in some cases, the host die can be electrically connected with another die to provide a die stack or other three-dimensional integrated circuit (3D IC), in accordance with some embodiments. In some instances, the disclosed capacitor can be utilized, for example, to provide integrated capacitance in a switched-capacitor voltage regulator (SCVR). 1. An integrated circuit comprising:a semiconductor layer; and an electrically conductive through-body via (TBV);', 'an electrically conductive plate surrounding the TBV and arranged coaxially therewith; and', 'a dielectric layer disposed between the TBV and the plate., 'a capacitor formed within the semiconductor layer, the capacitor comprising2. The integrated circuit of claim 1 , wherein the capacitor extends through the semiconductor layer from an upper surface thereof to a lower surface thereof.3. The integrated circuit of claim 1 , wherein the capacitor has a width/diameter in the range of about 6-30 μm.4. The integrated circuit of claim 1 , wherein the TBV has a width/diameter in the range of about 2-10 μm claim 1 , and wherein the dielectric layer has a thickness in the range of about 50-200 nm.5. The integrated circuit of claim 1 , wherein the dielectric layer has a dielectric constant (κ-value) greater than or equal to about 3.9.6. The integrated circuit of claim 1 , wherein the dielectric layer has a ...

PACKAGE WITH COMPONENT CONNECTED WITH CARRIER VIA SPACER PARTICLES

A package and method of making a package. In one example, the package includes an at least partially electrically conductive carrier, a passive component mounted on the carrier, and an at least partially electrically conductive connection structure electrically connecting the carrier with the component and comprising spacer particles configured for spacing the carrier with regard to the component. 1. A package , comprising:an at least partially electrically conductive carrier;a passive component mounted on the carrier;an at least partially electrically conductive connection structure electrically connecting the carrier with the component and comprising spacer particles configured for spacing the carrier with regard to the component;wherein the connection structure comprises an at least partially electrically conductive material in which the spacer particles are embedded; andwherein the carrier comprises a first carrier section and a second carrier section separated by a recess, wherein the component has a first surface portion electrically connected with the first carrier section by a first portion of the connection structure and has a second surface portion electrically connected with the second carrier section by a separate second portion of the connection structure.2. The package according to claim 1 , comprising where the spacer particles are made of an electrically conductive material.3. The package according to claim 2 , wherein the spacer particles are made of a polymeric material having an electrically conductive coating.4. The package according to claim 1 , wherein the at least partially electrically conductive material is solder with spacer particles therein.5. The package according to claim 4 , wherein the spacer particles comprise at least one of the group consisting of fully electrically conductive spacer particles claim 4 , fully electrically insulating spacer particles claim 4 , and spacer particles having an electrically insulating core and an ...

High-Power Electronic Device Packages and Methods

A high power electronic device package constructed to include a high power electronic device having an epitaxial surface attached to a thermally conductive submount by a thermally conductive interface layer having a eutectic metal contact therein. A gallium nitride high electron mobility transistor (GaN HEMT) having a transistor structure formed of a GaN thin film layer bonded to a thermally conductive host substrate via a thermally conductive interface layer disposed therebetween, and a method of forming the GaN HEMT. The GaN HEMTs can be used in such applications as, for example, power amplifiers with x-band radio frequency (RF) power outputs for micro-radar applications. 1. A high-power electronic device package , comprising:a thermally conductive submount having an upper surface and a lower surface;a first thermally conductive interface layer disposed on the upper surface of the thermally conductive submount;a metal frame and a diamond head bonded to the upper surface of the thermally conductive submount via the first thermally conductive interface layer;a second thermally conductive interface layer disposed on the metal frame and the diamond head;at least one eutectic metal contact positioned in at least one via in the second thermally conductive interface layer; anda high-power electronic device having an epitaxial surface,wherein the epitaxial surface is in contact with the at least one eutectic metal contact, andwherein the epitaxial surface is secured to the eutectic metal contact and to the thermally conductive submount by the second thermally conductive interface layer.2. The high-power electronic device package of claim 1 , further comprising a ground plate bonded to a second surface of the high-power electronic device via a eutectic metal bonding layer.3. The high-power electronic device package of claim 2 , further comprising a heat sink bonded to the ground plate by a second eutectic metal bonding layer.4. The high-power electronic device package of ...

Semiconductor device and electronic apparatus

The present disclosure relates to a semiconductor device and an electronic apparatus which is capable of reducing variations and deterioration of transistor characteristics. A first connection pad connected with a first wiring and a first floating metal greater than the first connection pad are formed at a bonding surface of a first substrate, whereas a second connection pad connected with a second wiring and a second floating metal greater than the second connection pad are formed at a bonding surface of a second substrate. The, and the first floating metal and the second floating metal formed at the first substrate and the second substrate are bonded to each other. The present disclosure is applicable to a CMOS solid-state imaging device used for an imaging apparatus such as a camera, for example.

ELECTRIONIC DEVICES WITH INTERPOSER AND REDISTRIBUTION LAYER

In one example, an electronic device comprises a base substrate comprising a base substrate conductive structure, a first electronic component over a first side of the base substrate, an encapsulant over the first side of the base substrate, wherein the encapsulant contacts a lateral side of the electronic component, an interposer substrate over a first side of the encapsulant and comprising an interposer substrate conductive structure, and a vertical interconnect in the encapsulant and coupled with the base substrate conductive structure and the interposer substrate conductive structure. A first one of the base substrate or the interposer substrate comprises a redistribution layer (RDL) substrate, and a second one of the base substrate or the interposer substrate comprises a laminate substrate. Other examples and related methods are also disclosed herein.

Method of fabricating a semiconductor device

A semiconductor device and a semiconductor package, the device including a first buffer dielectric layer on a first dielectric layer; a second dielectric layer and a second buffer dielectric layer sequentially disposed on the first buffer dielectric layer, the second buffer dielectric layer being in contact with the first buffer dielectric layer; and a pad interconnection structure that penetrates the first buffer dielectric layer and the second buffer dielectric layer, wherein the pad interconnection structure includes copper and tin.

Cold Plate, Device Comprising a Cold Plate and Method for Fabricating a Cold Plate

A cold plate includes a single piece member and a channel. A top side of the channel is open. A bottom side of the channel opposite the top side has an inlet and an outlet. 1. A device , comprising:a semiconductor module; anda cold plate comprised of a single piece member.2. The device of claim 1 , wherein the cold plate comprises a channel.3. The device of claim 2 , wherein a main face of the semiconductor module forms a top part of an inner surface of the channel.4. The device of claim 1 , wherein the semiconductor module is a power semiconductor module.5. The device of claim 1 , wherein the cold plate is coupled to the semiconductor module via one or more of a sintering bond claim 1 , a solder bond claim 1 , a welded joint claim 1 , and an active metal brazing bond.6. The device of claim 1 , wherein the cold plate comprises one or more of aluminum claim 1 , an aluminum alloy claim 1 , copper claim 1 , and a copper alloy.7. The device of claim 3 , wherein the semiconductor module comprises a base plate claim 3 , and wherein the main face of the semiconductor module forming the top part of the inner surface of the channel is a main face of the base plate.8. The device of claim 3 , wherein the semiconductor module comprises a substrate comprising a stack of more than one material layers claim 3 , and wherein the main face of the semiconductor module forming the top part of the inner surface of the channel comprises an outer layer of the stack.9. The device of claim 1 , wherein the single piece member comprises one or more of a stamped metal plate claim 1 , a rolled metal plate claim 1 , and a pressed metal plate.10. The device of claim 2 , wherein the channel comprises structures configured to cause turbulences in a cooling fluid flowing through the channel.11. The device of claim 10 , wherein a main face of the semiconductor module forms a top part of an inner surface of the channel claim 10 , and wherein the structures are arranged in a bottom part of the inner ...

POWER DEVICE CASSETTE WITH AUXILIARY EMITTER CONTACT

A press pack module includes a collector module terminal, an emitter module terminal, a gate module terminal, and an auxiliary module terminal. Each IGBT cassette within the module includes a set of shims, two contact pins, and an IGBT die. The first contact pin provides part of a first electrical connection between the gate module terminal and the IGBT gate pad. The second contact pin provides part of a second electrical connection between the auxiliary module terminal and a shim that in turn contacts the IGBT emitter pad. The electrical connection between the auxiliary emitter terminal and each emitter pad of the many IGBTs is a balanced impedance network. The balanced network is not part of the high current path through the module. By supplying a gate drive signal between the gate and auxiliary emitter terminals, simultaneous IGBT turn off in high speed and high current switching conditions is facilitated. 111-. (canceled)12. A power semiconductor device module comprising:a top plate member;a bottom plate member having a plurality of pedestals;a plurality of semiconductor device dice, where each of the semiconductor device dice is positioned above a corresponding one of the plurality of pedestals between the bottom plate member and the top plate member, wherein each of the semiconductor device dice has an emitter pad and a gate pad;an auxiliary emitter terminal, wherein the auxiliary emitter terminal is coupled via a branched network to the emitter pads of the semiconductor device dice; anda main emitter terminal, wherein the main emitter terminal is coupled through the pedestals to the emitter pads of the semiconductor device dice, and wherein the branched network does not extend through any of the pedestals.13. The power semiconductor device module of claim 12 , wherein the branched network extends through a first plurality of spring loaded contact pins claim 12 , and wherein the main emitter terminal is coupled through no spring loaded contact pin to the ...

GLASS INTERPOSER INTEGRATED ANTENNA FOR INTRACHIP, INTERCHIP AND BOARD COMMUNICATIONS

Various examples are provided for glass interposer integrated antennas for intrachip, interchip and board communications. In one example, a reflector through-glass via (TGV) antenna includes a TGV or group of TGVs extending through a glass substrate. The TGV can extend from a feeding line disposed on a first side of the glass substrate to a loading disc disposed on a second side of the glass substrate. An array of reflector pillars extending through the glass substrate from a ground plane on the first side of the glass substrate to the second side of the glass substrate can also be provided with the array of reflector pillars distributed beyond an outer edge of the loading disc. The TGV antenna can be implemented as a dual mode design and excited at a first frequency to generate an omni-directional radiation pattern and at a second frequency to generate a broadside radiation pattern. 1. A reflector through-glass via (TGV) antenna , comprising:a TGV extending through a glass substrate, the TGV comprising a metal core extending from a feeding line disposed on a first side of the glass substrate to a loading disc disposed on a second side of the glass substrate; andan array of reflector pillars extending through the glass substrate from a ground plane on the first side of the glass substrate to the second side of the glass substrate, the array of reflector pillars distributed beyond an outer edge of the loading disc.2. The reflector TGV antenna of claim 1 , wherein the array of reflector pillars are distributed about the outer edge of the loading disc.3. The reflector TGV antenna of claim 2 , wherein the array of reflector pillars are distributed in a semi-circular (or parabolic) pattern about the outer edge of the loading disc.4. The reflector TGV antenna of claim 2 , wherein the array of reflector pillars are evenly spaced about the outer edge of the loading disc.5. The reflector TGV antenna of claim 4 , wherein adjacent pillars of the array of reflector pillars are ...

High-frequency, high-output device unit

A high-frequency, high-output device unit includes a lead intended to be soldered to a circuit board and the lead includes concave portions only in a planar portion intended to be joined to the circuit board.

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD

Provided are a semiconductor device manufacturing method and semiconductor device such that manufacturing can be simplified and the thickness of the semiconductor device can be reduced. The semiconductor device includes an insulated circuit substrate having on one main surface thereof a first metal layer and a second metal layer, a metal plate conductively connected to the first metal layer, a first semiconductor element including on front and rear surfaces thereof a plurality of metal electrodes, a first insulating member disposed on a side surface of the first semiconductor element, a second insulating member disposed on the first insulating member and on the first semiconductor element, and a third metal layer, in which at least one portion thereof is disposed on the second insulating member and which conductively connects the metal electrode of the first semiconductor element and the second metal layer on the insulated circuit substrate. 1. A semiconductor device , comprising:an insulated circuit substrate having on one main surface thereof a first metal layer and a second metal layer;a metal plate conductively connected to the first metal layer;a first semiconductor element including on front and rear surfaces thereof a plurality of metal electrodes;a first insulating member disposed on a side surface of the first semiconductor element;a second insulating member disposed on the first insulating member and on the first semiconductor element; anda third metal layer, in which at least one portion thereof is disposed on the second insulating member and which conductively connects the metal electrode of the first semiconductor element and the second metal layer on the insulated circuit substrate.2. The semiconductor device according to claim 1 , whereinthe metal plate has a first through hole,at least one of the metal electrodes of the first semiconductor element is disposed in a position blocking the first through hole, anda fourth metal layer that conductively ...

Semiconductor Arrangement, Method for Producing a Number of Chip Assemblies, Method for Producing a Semiconductor Arrangement and Method for Operating a Semiconductor Arrangement

A semiconductor arrangement includes top and bottom contact plates, a plurality of chip assemblies, a dielectric embedding compound, and a control electrode interconnection structure. Each chip assembly has a semiconductor chip having a semiconductor body. The semiconductor body has a top side and an opposing underside. The top side is spaced apart from the underside in a vertical direction. Each semiconductor chip has a top main electrode arranged on the top side, a bottom main electrode arranged on the underside, a control electrode arranged at the top side, and an electrically conductive top compensation die, arranged on the side of the top main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the top main electrode by means of a top connecting layer. An electric current between the top main electrode and the bottom main electrode can be controlled by means of the control electrode. 2. The semiconductor arrangement of claim 1 , wherein:(a) each of the chip assemblies has an electrically conductive bottom compensation die, which is arranged on the side of the bottom main electrode facing away from the semiconductor body and is cohesively and electrically conductively connected to the bottom main electrode by means of a bottom connecting layer; or(b) the chip assemblies have a common electrically conductive bottom compensation die, which in the case of each of the chip assemblies is arranged on the side of the bottom main electrode facing away from the semiconductor body and is cohesively and electrically conductively connected to the bottom main electrode by means of a bottom connecting layer.3. The semiconductor arrangement of claim 2 , wherein the bottom connecting layer is embodied as a solder layer claim 2 , or as an adhesive layer claim 2 , or as a sintered layer.4. The semiconductor arrangement of claim 2 , wherein:in case (a) the bottom compensation dies each have a coefficient of linear thermal ...

LEADFRAME CAPACITORS

An electronic device having a package structure with conductive leads, first and second dies in the package structure, as well as first and second conductive plates electrically coupled to the respective first and second dies and having respective first and second sides spaced apart from and directly facing one another with a portion of the package structure extending between the first side of the first conductive plate and the second side of the second conductive plate to form a capacitor. No other side of the first conductive plate directly faces a side of the second conductive plate, and no other side of the second conductive plate directly faces a side of the first conductive plate. 112-. (canceled)13. A method , comprising:positioning a lead frame such that: a first side of a first conductive plate is spaced apart from and directly facing a second side of a second conductive plate; no other side of the first conductive plate directly faces a side of the second conductive plate; and no other side of the second conductive plate directly faces a side of the first conductive plate;performing a connection process that electrically connects a first bond wire to a first die and to the first conductive plate, and electrically connects a second bond wire to a second die and to the second conductive plate;performing a molding process that forms a package structure which encloses: the first die; the second die; the first bond wire; the second bond wire; a portion of the first conductive plate; and a portion of the second conductive plate; andseparating the first conductive plate, the second conductive plate, and conductive leads from a remaining portion of the lead frame.14. The method of claim 13 , wherein positioning the lead frame comprises:positioning a first lead frame relative to a second lead frame or relative to a dielectric insert such that: the first side of the first conductive plate of the first lead frame is spaced apart from and directly facing the second ...

WIRING SUBSTRATE AND METHOD FOR MANUFACTURING WIRING SUBSTRATE

A wiring substrate includes an insulating layer, a wiring layer, a via wiring, and a solder resist layer. The wiring layer includes a pad body that constitutes a part of a pad and a wiring pattern including an upper surface. The pad includes the pad body, a first metal layer formed on an upper surface of the pad body and including an embedded part embedded in the insulating layer and a projecting part including upper and side surfaces and projecting from the upper surface of the insulating layer, and a second metal layer including an upper surface and covering the upper and side surfaces of the projecting part. The upper surface of the pad body and the upper surface of the wiring pattern are on the same plane. The upper surface of the second metal layer is positioned lower than the upper surface of the solder resist layer. 1. A wiring substrate comprising:an insulating layer including upper and lower surfaces;a wiring layer including upper, lower, and side surfaces and being in a position that is recessed relative to the upper surface of the insulating layer;a via wiring formed in the insulating layer and connected to the lower surface of the wiring layer; anda solder resist layer formed on the upper surface of the insulating layer;wherein the via wiring includes a first part contacting the lower surface of the wiring layer and a second part exposed from the lower surface of the insulating layer, the first part having an area smaller than an area of the second part,wherein the wiring layer includes a pad body that constitutes a part of a pad and a wiring pattern including an upper surface,wherein the solder resist layer includes an upper surface and an opening that exposes the pad and a part of the upper surface of the insulating layer,wherein the solder resist layer buries a step part formed by the upper surface of the insulating layer and the upper surface of the wiring pattern, the pad body including upper and lower surfaces, the lower surface of the pad body ...

Semiconductor Device with Plated Lead Frame

A semiconductor device includes an insulating carrier structure comprised of an insulating inorganic material. The carrier structure has a receptacle in which a semiconductor chip is disposed. The semiconductor chip has a first side, a second side and a lateral rim. The carrier structure laterally surrounds the semiconductor chip and the lateral rim. The semiconductor device also includes a metal structure on and in contact with the second side of the semiconductor chip and embedded in the carrier structure. 1. A semiconductor device , comprising:an insulating carrier structure comprised of an insulating inorganic material, the carrier structure comprising a receptacle;a semiconductor chip comprising a first side, a second side and a lateral rim, the semiconductor chip being disposed in the receptacle, wherein the carrier structure laterally surrounds the semiconductor chip and the lateral rim; anda metal structure on and in contact with the second side of the semiconductor chip and embedded in the carrier structure.2. The semiconductor device of claim 1 , wherein the metal structure has a thickness between about 30 μm to about 500 μm.3. The semiconductor device of claim 1 , wherein the insulating carrier structure comprises a carrier substrate and a cover substrate joined with the carrier substrate by an adhesive bond.4. The semiconductor device of claim 3 , wherein the carrier substrate comprises at least one of glass and ceramic.5. The semiconductor device of claim 3 , wherein the cover substrate comprises at least one of glass and ceramic.6. The semiconductor device of claim 1 , wherein the insulating carrier structure comprises a circumferential groove encompassing a peripheral region of the semiconductor chip.7. The semiconductor device of claim 1 , wherein the semiconductor chip comprises a semiconductor material comprising a first doping region formed in the semiconductor material at a first side of the semiconductor material and a second doping region ...

Module Mount Interposer

A module mount interposer may include one or more fastener receivers configured to mechanically couple with one or more fasteners so as to mechanically and electrically couple a module to the interposer. The module mount interposer may also include a core configured to electrically couple with the module, wherein each of the fastener receivers are mechanically coupled to the core. The module mount interposer may additionally include a solder layer electrically coupled to the core and configured to electrically couple with a printed circuit board (PCB) so as to provide an electrical signal from the module to the PCB and to provide an electrical signal from the PCB to the module.

Flip chip backside mechanical die grounding techniques

A semiconductor device includes an integrated circuit attached to a chip carrier in a flip chip configuration. A substrate extends to a back surface of the integrated circuit, and an interconnect region extends to a front surface of the integrated circuit. A substrate bond pad is disposed at the front surface, and is electrically coupled through the interconnect region to the semiconductor material. The chip carrier includes a substrate lead at a front surface of the chip carrier. The substrate lead is electrically coupled to the substrate bond pad. An electrically conductive compression sheet is disposed on the back surface of the integrated circuit, with lower compression tips making electrical contact with the semiconductor material in the substrate. The electrically conductive compression sheet is electrically coupled to the substrate lead of the chip carrier by a back surface shunt disposed outside of the integrated circuit.

APPARATUS EXHIBITING ENHANCED STRESS RESISTANCE AND PLANARITY, AND RELATED MICROELECTRONIC DEVICES, MEMORY DEVICES, AND METHODS

An apparatus comprises conductive segments comprising an uneven topography comprising upper surfaces of the conductive segments protruding above an upper surface of underlying materials, a first passivation material substantially conformally overlying the conductive segments, and a second passivation material overlying the first passivation material. The second passivation material is relatively thicker than the first passivation material. The apparatus also comprises structural elements overlying the second passivation material. The second passivation material has a thickness sufficient to provide a substantially flat surface above the uneven topography of the underlying conductive segments at least in regions supporting the structural elements. Microelectronic devices, memory devices, and related methods are also disclosed. 1. An apparatus , comprising:conductive segments comprising an uneven topography comprising upper surfaces of the conductive segments protruding above an upper surface of underlying materials;a first passivation material substantially conformally overlying the conductive segments;a second passivation material overlying the first passivation material, wherein the second passivation material is relatively thicker than the first passivation material; andstructural elements overlying the second passivation material, the second passivation material having a thickness sufficient to provide a substantially flat surface above the uneven topography of the underlying conductive segments at least in regions supporting the structural elements.2. The apparatus of claim 1 , further comprising recessed regions between laterally adjacent portions of the conductive segments claim 1 , portions of the second passivation material intervening between the laterally adjacent portions of the conductive segments and substantially completely filling the recessed regions therebetween.3. The apparatus of claim 1 , wherein the first passivation material comprises an oxide ...

Electronic power module with enhanced thermal dissipation and manufacturing method thereof

An electronic power module comprising a case that houses a stack, which includes: a first substrate of a DBC type or the like; a die, integrating an electronic component having one or more electrical-conduction terminals, mechanically and thermally coupled to the first substrate; and a second substrate, of a DBC type or the like, which extends over the first substrate and over the die and presents a conductive path facing the die. The die is mechanically and thermally coupled to the first substrate by a first coupling region of a sintered thermoconductive paste, and the one or more conduction terminals of the electronic component are mechanically, electrically, and thermally coupled to the conductive path of the second substrate by a second coupling region of sintered thermoconductive paste.

Electric Power Conversion Apparatus

An electric power conversion apparatus includes a channel case in which a cooling water channel is formed; a double side cooling semiconductor module that has an upper and lower arms series circuit of an inverter circuit; a capacitor module; a direct current connector; and an alternate current connector. The semiconductor module includes first and second heat dissipation metals whose outer surfaces are heat dissipation surfaces, the upper and lower arms series circuit is disposed tightly between the first heat dissipation metal and the second heat dissipation metal, and the semiconductor module further includes a direct current positive terminal, a direct current negative terminal, and an alternate current terminal which protrude to outside. The channel case is provided with the cooling water channel which extends from a cooling water inlet to a cooling water outlet, and a first opening which opens into the cooling water channel.

SEMICONDUCTOR DEVICE

A semiconductor device includes: a semiconductor element that includes an electrode layer on a surface of the semiconductor element; a low-strength layer that is provided on a surface of the electrode layer; a bonding layer that is provided on a surface of the low-strength layer; and a conductive plate that is provided on a surface of the bonding layer. Strength of the bonding layer is higher than strength of the electrode layer, and strength of the low-strength layer is lower than the strength of the electrode layer. 1. A semiconductor device comprising:a semiconductor element that includes an electrode layer on a surface of the semiconductor element;a low-strength layer that is provided on a surface of the electrode layer;a bonding layer that is provided on a surface of the low-strength layer; anda conductive plate that is provided on a surface of the bonding layer,wherein strength of the bonding layer is higher than strength of the electrode layer, and strength of the low-strength layer is lower than the strength of the electrode layer.2. The semiconductor device according to claim 1 ,wherein the electrode layer is made of AlSi, and the low-strength layer is made of Al. The disclosure of Japanese Patent Application No. 2012-261126 filed on Nov. 29, 2012 including the specification, drawings and abstract is incorporated herein by reference in its entirety.1. Field of the InventionThe present invention relates to a semiconductor device.2. Description of Related ArtFor example, Japanese Patent Application Publication No. 2011-129619 (JP 2011-129619 A) discloses a semiconductor device in which a conductive plate is fixed on an electrode layer provided on a surface of a semiconductor element with a solder layer therebetween.When the conductive plate is fixed on a semiconductor element driven at high temperatures with the solder layer therebetween, the solder layer can be a high-melting point solder material. However, the high-melting point solder material has higher ...

SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR DEVICE

Each of a plurality of semiconductor elements included in a semiconductor package includes a front-surface electrode being provided on a semiconductor substrate on a side opposite to a conductor substrate, a back-surface electrode being joined to the conductor substrate, a control pad configured to control current flowing between the front-surface electrode and the back-surface electrode, a frame being electrically connected to the front-surface electrode, a portion of the frame being exposed from a surface of a sealing material from which a lower surface of the conductor substrate is exposed, and a plurality of terminal blocks being electrically connected to a plurality of first pads, a portion of the plurality of terminal blocks being exposed from a surface of the sealing material, the surface being provided on a side opposite to the surface of the sealing material from which the lower surface of the conductor substrate is exposed. 1. A semiconductor package comprising:a conductor substrate;a plurality of semiconductor elements having a switching function and being joined to an upper surface of the conductor substrate;at least one wiring element being joined to the upper surface of the conductor substrate, a number of the at least one wiring element being less than a number of the plurality of semiconductor elements; anda sealing material sealing a portion of the conductor substrate except for a lower surface of the conductor substrate, the plurality of semiconductor elements, and the at least one wiring element, wherein{'claim-text': ['a first substrate,', 'a first main electrode part being provided on the first substrate on a side opposite to the conductor substrate,', 'a second main electrode part being provided on a side of the conductor substrate of the first substrate, and being joined to the conductor substrate, and a control pad configured to control current flowing between the first main electrode part and the second main electrode part,'], '#text': 'each ...

MOLDED WAFER LEVEL PACKAGING

In a general aspect, an apparatus can include a metal layer, a first semiconductor die, a second semiconductor die, a molding compound, a first electrical contact and a second electrical contact. The first semiconductor die can have a first side disposed on the metal layer. The second semiconductor die can have a first side disposed on the metal layer. The metal layer can electrically couple the first side of the first semiconductor die with the first side of the second semiconductor die. The molding compound can at least partially encapsulate the metal layer, the first semiconductor die and the second semiconductor die. The first electrical contact can be to a second side of the first semiconductor die and disposed on a surface of the apparatus. The second electrical contact can be to a second side of the second semiconductor die and disposed on the surface of the apparatus. 1. An apparatus comprising:a metal layer;a first semiconductor die having a first side and a second side that is opposite the first side, the first side of the first semiconductor die being disposed on the metal layer;a second semiconductor die having a first side and a second side that is opposite the first side, the first side of the second semiconductor die being disposed on the metal layer, the metal layer electrically coupling the first side of the first semiconductor die with the first side of the second semiconductor die;a molding compound at least partially encapsulating the metal layer, the first semiconductor die and the second semiconductor die;a first electrical contact, the first electrical contact being to the second side of the first semiconductor die, the first electrical contact being disposed on a surface of the apparatus; anda second electrical contact, the second electrical contact being to the second side of the second semiconductor die, the second electrical contact being disposed on the surface of the apparatus.2. The apparatus of claim 1 , wherein the first electrical ...

Semiconductor device and fabrication method thereof

A semiconductor device including a connection terminal that is electrically connected to a semiconductor chip, a bus bar with an opening through which the connection terminal passes, and a fusing portion including a jointing portion, which is provided over an upper surface of the bus bar from an upper part of the connection terminal that is positioned above the upper surface of the bus bar by making the connection terminal pass through the opening of the bus bar, is provided.

Component structure, power module and power module assembly structure

The present disclosure relates to a component structure, a power module and a power module assembly structure having the component structure. The component structure comprises: a first bus bar, having one end extending to a first plane to form a first connecting terminal; a second bus bar, comprising a front portion of the second bus bar and a rear portion of the second bus bar, wherein the front portion of the second bus bar is laminated in parallel with the first bus bar, and the rear portion of the second bus bar is extended to a second plane to form a second connecting terminal; and an external circuit comprising a third bus bar, wherein the third bus bar is settled in parallel with the rear portion of the second bus bar, to reduce a parasitic inductance between the first connecting terminal and the second connecting terminal.

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE

A semiconductor package includes a first metal plate having a first surface, a semiconductor chip including a first electrode and a second electrode, on the first surface, and a second metal plate on the semiconductor chip. The first metal plate has a first surface. The first electrode is connected to the first metal plate. The second metal plate includes a second surface and first and second side surfaces respectively on opposite sides of the second metal plate and connected to the second surface. The first side surface has a first recessed portion extending in a direction which crosses the first and second surfaces, and the second side surface has a second recessed portion extending in the second direction that crosses the first and second surfaces. 1. A semiconductor package comprising:a first metal plate having a first surface;a semiconductor chip on the first surface, the semiconductor chip including a first electrode and a second electrode, wherein the first electrode is connected to the first metal plate; anda second metal plate on the semiconductor chip, wherein the second metal plate has a second surface and first and second side surfaces respectively on opposite sides of the second metal plate and connected to the second surface, and is connected to the second electrode, the first side surface having a first recessed portion extending in a direction which crosses the first and second surfaces, and the second side surface having a second recessed portion extending in the second direction that crosses the first and second surfaces.2. The package according to claim 1 , wherein the first recessed portion extends inwardly of the first side surface and the second recessed portion extends inwardly of the second side surface.3. The package according to claim 2 , wherein a portion of the semiconductor chip is exposed by each of the first and second recessed portions.4. The package according to claim 3 , whereinthe semiconductor chip has sidewalls and at least two ...

Carbon nanotube-based thermal interface materials and methods of making and using thereof

Single-layer CNT composites and multilayered or multitiered structures formed therefrom, by stacking of vertically aligned carbon nanotube (CNT) arrays, and methods of making and using thereof are described herein. Such multilayered or multitiered structures can be used as thermal interface materials (TIMs) for a variety of applications, such as burn-in testing.

SEMICONDUCTOR PACKAGE HAVING AN ISOLATION WALL TO REDUCE ELECTROMAGNETIC COUPLING

A system and method for packaging a semiconductor device that includes a wall to reduce electromagnetic coupling is presented. A semiconductor device has a substrate on which a first circuit and a second circuit are formed proximate to each other. An isolation wall of electrically conductive material is located between the first circuit and the second circuit, the isolation wall being configured to reduce inductive coupling between the first and second circuits during an operation of the semiconductor device. Several types of isolation walls are presented. 1. A semiconductor device comprising:a ground plane with a surface and an aperture in the surface;a first circuit on a first portion of the surface of the ground plane that is located at a first side of the aperture, wherein the first circuit comprises a first plurality of electrical components, including a first transistor, and a first wire bond array electrically coupled between the first transistor and a first lead, wherein the first lead is located at a first side of the device;a second circuit on a second portion of the ground plane that is located at a second side of the aperture that is opposite the first side, wherein the second circuit comprises a second plurality of electrical components, including a second transistor, and a second wire bond array electrically coupled between the second transistor and a second lead, wherein the second lead is located at the first side of the device; andan isolation wall formed of electrically conductive material inserted into the aperture between the first circuit and the second circuit and electrically connected to the ground plane, the isolation wall formed of a rectangular body of material that extends perpendicularly from the surface of the ground plane between the first and second wire bond arrays and above a height of the first and second wire bond arrays, the isolation wall being configured to reduce electromagnetic coupling between the first circuit and the ...

STRESS-RESILIENT CHIP STRUCTURE AND DICING PROCESS

A substrate includes a plurality of semiconductor chips arranged in a grid pattern and laterally spaced from one another by channel regions. The substrate includes a vertical stack of a semiconductor layer and at least one dielectric material layer embedding metal interconnect structures. The at least one dielectric material layer are removed along the channel regions and around vertices of the grid pattern so that each semiconductor chip includes corner surfaces that are not parallel to lines of the grid pattern. The corner surfaces can include straight surfaces or convex surfaces. The semiconductor chips are diced and subsequently bonded to a packaging substrate employing an underfill material. The corner surfaces reduce mechanical stress applied to the metal interconnect layer during the bonding process and subsequent thermal cycling processes. 1. A method of manufacturing a semiconductor structure , said method comprising:forming at least one dielectric material layer embedding metal semiconductor structures on a semiconductor substrate, whereby a plurality of semiconductor chip cores and inter-chip regions are formed, wherein each of said plurality of semiconductor chip cores comprises a portion of said semiconductor substrate and a portion of said at least one dielectric material layer, and each of said plurality of semiconductor chip cores is arranged in a grid pattern;removing portions of said at least one dielectric material layer from said inter-chip regions to form grooves in said at least one dielectric layer and to form corner surfaces of said plurality of semiconductor chip cores around vertices of said grid pattern, wherein each corner surface is not parallel to any of said two sets of parallel lines; anddicing said semiconductor substrate along said grooves to form a plurality of semiconductor chips.2. The method of claim 1 , wherein said corner surfaces are planar vertical surfaces that are not parallel to lines connecting said vertices of said grid ...

Conductive compositions and methods of using them

A conductive composition includes a mono-acid hybrid that includes an unprotected, single reactive group. The mono-acid hybrid may include substantially non-reactive groups elsewhere such that the mono-acid hybrid is functional as a chain terminator. Methods and devices using the compositions are also disclosed.

SEMICONDUCTOR DEVICE

A base plate, and a plurality of unit structures formed on the base plate are provided. Each of the unit structures including an insulating substrate fixed on the base plate, a metal pattern formed on the insulating substrate, a semiconductor element electrically connected to the metal pattern, and a main electrode having an upper end portion exposed to the outside and a lower end portion connected to a peripheral portion of the metal pattern closest to an outer edge of the base plate. 1. A semiconductor device comprising:a base plate formed into a rectangular shape as viewed in plan; anda plurality of unit structures formed nearer to a first side of the base plate and a plurality of unit structures formed nearer to a second side of the base plate opposite from the first side, each of the unit structures including:an insulating substrate fixed on the base plate;a metal pattern formed on the insulating substrate;a semiconductor element electrically connected to the metal pattern; anda main electrode having an upper end portion exposed to the outside and a lower end portion connected to a peripheral portion of the metal pattern closest to an outer edge of the base plate.2. A semiconductor device comprising:a base plate formed into a rectangular shape as viewed in plan; anda plurality of unit structures formed on the base plate, each of the unit structures including:an insulating substrate fixed on the base plate;a metal pattern formed on the insulating substrate;a semiconductor element electrically connected to the metal pattern; anda main electrode having an upper end portion exposed to the outside and a lower end portion connected to a peripheral portion of the metal pattern closest to an outer edge of the base plate, whereinthe plurality of unit structures include a first unit structure formed on a first side of the base plate, and a second unit structure formed on a second side of the base plate opposite from the first side, andthe main electrode includes a first ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

A semiconductor device including a stacked assembly. The stacked assembly includes a metal substrate, a stacked substrate mounted on the metal substrate and having an electrode pattern, a semiconductor element mounted on the stacked substrate, and a lead frame interconnection electrically connecting the semiconductor element and the electrode pattern. The lead frame interconnection includes a first bonding portion in contact with the semiconductor element, a second bonding portion in contact with the electrode pattern, and an interconnect portion connecting the first and second bonding portions. At least one of the first bonding portion and the second bonding portion is wider than the interconnect portion. 1. A semiconductor device , comprising: a metal substrate;', 'a stacked substrate mounted on the metal substrate, the stacked substrate having an electrode pattern;', 'a semiconductor element mounted on the stacked substrate; and', a first bonding portion in contact with the semiconductor element,', 'a second bonding portion in contact with the electrode pattern, and', 'an interconnect portion connecting the first and second bonding portions,, 'a lead frame interconnection electrically connecting the semiconductor element and the electrode pattern, the lead frame interconnection including'}], 'a stacked assembly includingat least one of the first bonding portion and the second bonding portion being wider than the interconnect portion.2. The semiconductor device according to claim 1 , wherein the interconnect portion is connected to one of the first and second bonding portions at a position away from an end of said one bonding portion.3. The semiconductor device according to claim 1 , whereina threshold width of the interconnect portion is determinable by a targeted lifespan of the semiconductor device and at least one of a width of the first bonding portion and a width of the second bonding portion, anda width of the interconnect portion is set to be narrower than ...

Semiconductor device

A semiconductor device includes an insulating substrate having an insulating plate and a circuit plate; a semiconductor chip having a front surface provided with a gate electrode and a source electrode, and a rear surface fixed to the circuit plate; a printed circuit board facing the insulating substrate, and including a first metal layer and a second metal layer; a first conductive post having two ends electrically and mechanically connected to the gate electrode and the first metal layer; a second conductive post having two ends electrically and mechanically connected to the source electrode and the second metal layer; and a circuit impedance reducing element electrically connected between the gate electrode and the source electrode through the first conductive post and the second conductive post.

WIRING SUBSTRATE

A wiring substrate includes a first insulating layer, a pad on a surface of the first insulating layer, a reinforcement wiring pattern in or on the surface of the first insulating layer, and a second insulating layer on the surface of the first insulating layer. The reinforcement wiring pattern surrounds the pad without contacting the pad in a plan view. The second insulating layer includes an opening in which the pad is exposed without contacting the second insulating layer. The second insulating layer includes an inner side surface defining the opening. The inner side surface is on the reinforcement wiring pattern. 1. A wiring substrate comprising:a first insulating layer;a pad on a surface of the first insulating layer;a reinforcement wiring pattern surrounding the pad without contacting the pad in a plan view, the reinforcement wiring pattern being in or on the surface of the first insulating layer; anda second insulating layer on the surface of the first insulating layer, the second insulating layer including an opening in which the pad is exposed without contacting the second insulating layer, the second insulating layer including an inner side surface defining the opening, the inner side surface being positioned on the reinforcement wiring pattern.2. The wiring substrate as claimed in claim 1 , wherein an end of the inner side surface toward the first insulating layer is in contact with the reinforcement wiring pattern.3. The wiring substrate as claimed in claim 1 , wherein the reinforcement wiring pattern is in a groove famed in the surface of the first insulating layer.4. The wiring substrate as claimed in claim 1 , wherein a height of the reinforcement wiring pattern is smaller than a height of the pad with reference to the surface of the first insulating layer.5. The wiring substrate as claimed in claim 1 , wherein the reinforcement wiring pattern protrudes from the surface of the first insulating layer.6. The wiring substrate as claimed in claim 1 , ...

Hybrid bonding structures, semiconductor devices having the same, and methods of manufacturing the semiconductor devices

Provided are a hybrid bonding structure, a solder paste composition, a semiconductor device, and a method of manufacturing the semiconductor device. The hybrid bonding structure includes a solder ball and a solder paste bonded to the solder ball. The solder paste includes a transient liquid phase. The transient liquid phase includes a core and a shell on a surface of the core. A melting point of the shell may be lower than a melting point of the core. The core and the shell are configured to form an intermetallic compound in response to the transient liquid phase at least partially being at a temperature that is within a temperature range of about 20° C. to about 190° C.

CAPACITORS AND RESISTORS AT DIRECT BONDING INTERFACES IN MICROELECTRONIC ASSEMBLIES

Disclosed herein are capacitors and resistors at direct bonding interfaces in microelectronic assemblies, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component, wherein a direct bonding interface of the second microelectronic component is direct bonded to a direct bonding interface of the first microelectronic component, the microelectronic assembly includes a sensor, the sensor includes a first sensor plate and a second sensor plate, the first sensor plate is at the direct bonding interface of the first microelectronic component, and the second sensor plate is at the direct bonding interface of the second microelectronic component. 1. A microelectronic assembly , comprising:a first microelectronic component; anda second microelectronic component, wherein a direct bonding interface of the second microelectronic component is direct bonded to a direct bonding interface of the first microelectronic component;wherein the microelectronic assembly includes a capacitor, the capacitor includes a first conductive plate and a second conductive plate, the first conductive plate is at the direct bonding interface of the first microelectronic component, and the second conductive plate is at the direct bonding interface of the second microelectronic component.2. The microelectronic assembly of claim 1 , wherein a footprint of the second conductive plate is within a footprint of the first conductive plate.3. The microelectronic assembly of claim 1 , wherein a footprint of the second conductive plate is not within a footprint of the first conductive plate.4. The microelectronic assembly of claim 1 , wherein the capacitor is a first capacitor claim 1 , the microelectronic assembly includes a second capacitor claim 1 , the second capacitor includes the second conductive plate and a third conductive plate claim 1 , and the third conductive plate is ...

BUS BAR AND POWER ELECTRONIC DEVICE WITH CURRENT SHAPING TERMINAL CONNECTOR AND METHOD OF MAKING A TERMINAL CONNECTOR

A bus bar includes a load terminal connector comprising a conductive plate that extends from a first edge to an opposite second edge and extends from a third edge to an opposite fourth edge. The third and fourth edges extend from the first edge to the second edge. The plate includes a window opening located between the first and second edges and between the third and fourth edges. The plate also includes a slot extending into the plate from the first edge to the window opening. The plate includes first and second sets of openings configured to receive connections with first and second power terminals of switch packages. The first set of openings and the second set of openings are located on opposite sides of the slot. 1. A bus bar comprising:a supply terminal connector assembly extending from a first lateral side to an opposite second lateral side, the supply terminal connector assembly including one or more first holes configured for connection with one or more collector terminals of a high potential switch element and one or more second holes for connection with one or more emitter terminals of a low potential switch element,the supply terminal connector assembly also including first and second tabs protruding from the supply terminal connector assembly , the first tab including one or more third holes configured for connection with a direct current (DC) high potential bus, the second tab including one or more fourth holes configured for connection with a DC low potential bus,the first and second tabs offset from each other such that the first tab is closer to the first lateral side of the supply terminal connector assembly than the second tab and the second tab is closer to the second lateral side of the supply terminal connector assembly than the first tab.2. The bus bar of claim 1 , wherein the supply terminal connector assembly includes one or more L-shaped slots between (a) the one or more first holes or the one or more second holes and (b) the one or more ...

SEMICONDUCTOR DEVICE

A semiconductor device of embodiments includes a first semiconductor chip; a metal plate having a first plane and a second plane facing the first plane and including a first ceramic plate provided between the first plane and the second plane; and a first insulating board provided between the first semiconductor chip and the metal plate and facing the first plane, in which the first ceramic plate does not exist between the first semiconductor chip and the second plane. 1. A semiconductor device comprising:a first semiconductor chip;a metal plate having a first plane and a second plane facing the first plane, the metal plate including a first ceramic plate provided between the first plane and the second plane; anda first insulating board provided between the metal plate and the first semiconductor chip, the first insulating board facing the first plane,wherein the first ceramic plate does not exist between the first semiconductor chip and the second plane.2. The semiconductor device according to claim 1 , wherein the metal plate includes a second ceramic plate provided between the first plane and the second plane.3. The semiconductor device according to claim 2 , wherein a first distance between the second plane and the first ceramic plate and a second distance between the second plane and the second ceramic plate are substantially equal to each other.4. The semiconductor device according to claim 2 , wherein a first distance between the second plane and the first ceramic plate and a second distance between the second plane and the second ceramic plate are different from each other.5. The semiconductor device according to claim 4 , wherein the first ceramic plate and the second ceramic plate are at least partially overlapped with each other in a direction normal to the first plane.6. The semiconductor device according to claim 1 , further comprising a second semiconductor chip claim 1 , the first insulating board being located between the second semiconductor chip and ...

SEMICONDUCTOR PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF

A method of fabricating a semiconductor package structure is provided. The structure is configured to include a base substrate, a die placed on the base substrate, the die including a semiconductor device, a solder bump placed on one surface of the die to exhaust heat generated in the die to an outside; and a solder ball placed on other surface of the die facing the one surface to transmit a signal, which is produced by the semiconductor device of the die, to an external device. 120-. (canceled)21. A semiconductor package structure , comprising:a re-distribution substrate;a die mounted on the re-distribution substrate, the die including a joining pattern;a solder bump joined to the joining pattern on the die;a polymer resin layer embedding the die on the re-distribution substrate, the solder bump being exposed to an upper surface of the polymer resin layer;a base substrate on the polymer resin layer;a contact plug connecting the re-distribution substrate and the base substrate on a side of the die; andan upper package mounted on the base substrate and including an upper substrate and an upper die mounted on the upper substrate,wherein the base substrate includes a heat dissipation plug penetrating the base substrate, andwherein the solder bump connects the heat dissipation plug and the joining pattern to each other.22. The semiconductor package structure of claim 21 , wherein the base substrate includes a solder mask disposed on the base substrate claim 21 , the solder mask defining an opening area that corresponds to the heat dissipation plug claim 21 , andwherein the solder bump disposed in the opening area between the heat dissipation plug and the die, and configured to discharge heat generated in the die to an outside.23. The semiconductor package structure of claim 22 , wherein the solder bump is coupled to the base substrate through the opening area.24. The semiconductor package structure of claim 21 , wherein a direction of heat claim 21 , which is generated ...

SEMICONDUCTOR DEVICE AND METHOD OF MEASURING THE SAME

A semiconductor device includes first and second contact parts that are disposed close to each other with an interval therebetween and form a screw hole (connection area) to which an external connection terminal is connected. The first contact part extends from a side of a case via a first linkage part that extends from the side, and the second contact part extends from the side via a second linkage part that extends from the side. The first and second linkage parts are disposed away from each other by at least a certain interval. In this way, the semiconductor device is allowed to have first and second semiconductor chips connected in parallel with each other and function as a semiconductor device. In addition, electrical characteristics of the first and second semiconductor chips of the semiconductor device are individually measured. 1. A semiconductor device comprising:a first semiconductor chip and a second semiconductor chip that are disposed on a metal plate;a first electrode terminal that is electrically connected to a main electrode of the first semiconductor chip; anda second electrode terminal that is electrically connected to a main electrode of the second semiconductor chip,wherein the first electrode terminal includes a first contact part, and the second electrode terminal includes a second contact part, andwherein the first contact part and the second contact part are disposed close to each other with an interval therebetween and form a connection area to which an external connection terminal is connected.2. The semiconductor device according to claim 1 , further comprising:a multi-layer substrate including the metal plate and an insulating plate having a front side on which the metal plate is formed,wherein the multi-layer substrate, the first semiconductor chip, and the second semiconductor chip are held inside a case,wherein the first contact part and the second contact part extend from a side of the case,wherein the first electrode terminal is ...

SEMICONDUCTOR DEVICE

An inventive semiconductor device includes: a semiconductor chip including an integrated circuit; a plurality of electrode pads provided on the semiconductor chip and connected to the integrated circuit; a rewiring to which the electrode pads are electrically connected together, the rewiring being exposed on an outermost surface of the semiconductor chip and having an exposed surface area greater than the total area of the electrode pads; and a resin package which seals the semiconductor chip. 1. A semiconductor device comprising:a semiconductor chip including an integrated circuit;a plurality of electrode pads provided on the semiconductor chip and connected to the integrated circuit;a rewiring to which the electrode pads are electrically connected together, the rewiring being exposed on an outermost surface of the semiconductor chip and having an exposed surface area greater than a total area of the electrode pads; anda resin package which seals the semiconductor chip.2. The semiconductor device according to claim 1 , wherein the rewiring covers the plurality of electrode pads.3. The semiconductor device according to claim 1 , wherein the rewiring includes a plurality of rewirings provided on the semiconductor chip and spaced from each other along the surface of the semiconductor chip.4. The semiconductor device according to claim 1 , further comprising:a lead selectively sealed in the resin package; anda connection member sealed in the resin package for electrical connection between the rewiring and the lead.5. The semiconductor device according to claim 4 , wherein the connection member includes an electrically conductive plate.6. The semiconductor device according to claim 4 , wherein the semiconductor chip is connected to the connection member in an attitude such that a surface of the semiconductor chip formed with the rewiring faces up.7. The semiconductor device according to claim 6 , wherein the rewiring is connected to the connection member via solder.8. ...

ELEMENT MODULE

An element module includes a cooler, a plurality of elements, and a conductive member. The cooler includes a first element disposition portion and a second element disposition portion which are provided on both sides in a predetermined direction. The plurality of elements are disposed in each of the first element disposition portion and the second element disposition portion. The conductive member is disposed in a space portion of the cooler. The space portion penetrates the cooler between the plurality of elements in each of the first element disposition portion and the second element disposition portion. The space portion allows the first element disposition portion and the second element disposition portion to communicate with each other. The conductive member is connected to the element of the first element disposition portion and the element of the second element disposition portion. 13-. (canceled)4. An element module , comprising:a cooler including a first element disposition portion and a second element disposition portion which are provided on both sides in a predetermined direction, and including at least one refrigerant storage portion configured to internally store a refrigerant between the first element disposition portion and the second element disposition portion;a plurality of elements disposed in each of the first element disposition portion and the second element disposition portion, and including transistors;a conductive member disposed in a space portion through which the first element disposition portion and the second element disposition portion are allowed to communicate with each other by penetrating the cooler between the plurality of elements in each of the first element disposition portion and the second element disposition portion, and connected to the element of the first element disposition portion and the element of the second element disposition portion;a plurality of conductor plates disposed on a side opposite to each facing side of ...

POWER MODULE, ELECTRIC POWER CONVERSION DEVICE, AND METHOD FOR PRODUCING POWER MODULE

An object is to provide a power module in which adhesion of a sealing resin is sufficient and which is highly reliable. The power module includes: an insulative board in which a pattern of a conductor layer is formed on a ceramic plate; power semiconductor elements placed on the insulative board; lead frames each in a plate shape connecting from electrodes of the power semiconductor elements to screw-fastening terminal portions; and a sealing resin portion that seals connection portions between the power semiconductor elements and the lead frames, and regions around the connection portions; wherein, in the lead frames, opening portions are formed at positions where each of the lead frames at least partly overlaps, in planar view, with a portion of the insulative board on which the conductor layer is not formed. 111-. (canceled)12. A power module , comprising:an insulative board in which a conductor layer is formed on ceramic plate;a semiconductor element placed on the insulative board;an electrode plate in a plate shape connected to a front-surface electrode of the semiconductor element: anda sealing resin portion that seals tale semiconductor element and at least a part of the electrode plate;wherein an opening portion is formed in the electrode plate at a position where the opening portion at least partly overlaps, in planar view,with a portion of the insulative board where the conductor layer is not formed; andwherein the opening portion in the electrode plate has an area equivalent to a circle having a diameter not less than 160% of a thickness of the electrode plate, and is sealed in the sealing resin portion.13. A power module , comprising:an insulative board in which a conductor layer is formed on a ceramic plate;a semiconductor element placed on the insulative board;an electrode plate in a plate shape electrically connected to the conductor layer; anda sealing resin portion that seals the conductor layer and at feast a part of the electrode plate;wherein an ...

SEMICONDUCTOR DEVICE AND ELECTRIC POWER CONVERSION APPARATUS

A semiconductor device according to the present invention includes a relay substrate provided on a plurality of semiconductor chips. The relay substrate includes an insulating plate in which a through hole is formed, a lower conductor provided on a lower surface of the insulating plate and having a first lower conductor and a second lower conductor, an upper conductor provided on an upper surface of the insulating plate, a connection part provided in the through hole and connecting the second lower conductor and the upper conductor together, and a protruding part which is a part of one of the first lower conductor and the upper conductor and protrudes outward from the insulating plate, the protruding part is connected to a first external electrode, and another of the first lower conductor and the upper conductor is connected to a second external electrode and is positioned inside the insulating plate. 11. A semiconductor device comprising: P a substrate;a plurality of semiconductor chips provided on the substrate;a relay substrate provided on the plurality of semiconductor chips;a first external electrode; anda second external electrode, whereinthe relay substrate includesan insulating plate in which a through hole is formed,a lower conductor provided on a lower surface of the insulating plate and having a first lower conductor electrically connected to any of the plurality of semiconductor chips and a second lower conductor electrically connected to any of the plurality of semiconductor chips,an upper conductor provided on an upper surface of the insulating plate,a connection part provided in the through hole and electrically connecting the second lower conductor and the upper conductor together, anda protruding part which is a part of one of the first lower conductor and the upper conductor and protrudes outward from the insulating plate in plan view,the protruding part is electrically connected to the first external electrode, andthe other of the first lower ...

Packaged semiconductor devices with laser grooved wettable flank and methods of manufacture

In a general aspect, a method for producing a packaged semiconductor device can include coupling a semiconductor device to a leadframe structure having a signal lead that is electrically coupled with the semiconductor device. The method can also include forming, with a laser, a groove in the signal lead, the groove having a first sidewall and a second sidewall, and applying solder plating to the signal lead, including the first sidewall and the second sidewall of the groove. The method can further include separating, at the groove, the signal lead into a first portion and a second portion, such that the second portion of the signal lead is separated from the metal leadframe structure,

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

A method for manufacturing a semiconductor device includes forming a bonding layer on a back-surface of a semiconductor element, mounting the semiconductor element on a base member, and bonding the semiconductor element to the base member by pressing the semiconductor element on the base member. The bonding layer includes tin. The base member includes a plating layer that includes silver and tin. The base member is heated at a prescribed temperature. The semiconductor element is placed on the base member so that the bonding layer contacts the plating layer on the base member. 1. A method for manufacturing a semiconductor device , the method comprising:forming a bonding layer on a back-surface of a semiconductor element, the bonding layer including tin;mounting the semiconductor element on a base member, the base member including a plating layer and being heated at a prescribed temperature, the plating layer including silver and tin, the semiconductor element being placed on the base member so that the bonding layer contacts the plating layer on the base member; andbonding the semiconductor element to the base member by pressing the semiconductor element on the base member.2. The method according to claim 1 , whereinthe base member includes copper, andthe plating layer is selectively formed on the base member.3. The method according to claim 1 , whereinthe bonding layer of the semiconductor element includes a first layer and a second layer, the first layer being in contact with the back-surface and being electrically connected to the semiconductor element, the first layer including metal other than tin, the second layer including tin, andthe first layer and the second layer are stacked in order on the back-surface, the second layer contacting the plating layer when the semiconductor element is mounted on the base member.4. The method according to claim 3 , whereinthe bonding layer further includes a third layer provided between the first layer and the second layer, ...

Power module

A power module includes: a base plate having a first surface; electrode plate provided at the first surface; a wire connected to a semiconductor chip and the electrode plate; a metal member connected to the electrode plate; a terminal plate; a first resin layer, a connection portion of the wire and the semiconductor chip being disposed inside the first resin layer; and a second resin layer provided on the first resin layer and having a lower elastic modulus than the first resin layer. The terminal plate includes a bonding portion contacting an upper surface of the metal member, a curved portion curved upward from the bonding portion. The curved portion is disposed inside the second resin layer, and a length from the first surface of a lower surface of the bonding portion is greater than a length from the first surface of the connection portion.

POWER ELECTRONICS MODULE

A power electronics module includes a substrate with a substrate metallization layer, which is separated into conducting areas for providing conducting paths for the power electronics module; a semiconductor switch chip bonded with a first power electrode to a first conducting area of the substrate metallization layer; a conductor plate bonded to a second power electrode of the semiconductor switch chip opposite to the first power electrode. 115-. (canceled)16. A power electronics module , comprising:a substrate with a substrate metallization layer, which is separated into conducting areas for providing conducting paths for the power electronics module;a semiconductor switch chip bonded with a first power electrode to a first conducting area of the substrate metallization layer;a conductor plate bonded to a second power electrode of the semiconductor switch chip opposite to the first power electrode;a gate conductor bonded to a gate electrode of the semiconductor switch chip besides the second power electrode;wherein the conductor plate extends to a second conducting area of the substrate metallization layer and the gate conductor runs through an opening in the conductor plate arranged above the gate electrode;wherein the gate conductor comprises a bond wire;wherein the conductor plate is a metal clip;wherein a bonding preform is bonded onto the metal clip; andwherein a second semiconductor chip is bonded with a first power electrode onto the bonding preform.17. The power electronics module of claim 16 , wherein the opening in the conductor plate is a through-hole.18. The power electronics module of claim 16 , wherein the gate conductor extends over the conductor plate.19. The power electronics module of claim 16 , wherein the metal clip is bonded with a first end to the second power electrode and the metal clip is bonded with a second end to the second conducting area of the substrate metallization layer; andwherein a gate conductor substrate is attached onto the ...

NON-INSULATED POWER SEMICONDUCTOR MODULE AND METHOD OF MANUFACTURING THE SAME

A non-insulated power semiconductor module may include a housing, at least a pair of lead frames fixedly seated in the housing and having a plurality of power semiconductor chips mounted on surfaces thereof, and an insulation member disposed between the housing and the pair of lead frames. 1. A non-insulated power semiconductor module comprising:a housing;at least a pair of lead frames fixedly seated in the housing and having a plurality of power semiconductor chips mounted on surfaces thereof; andan insulation member disposed between the housing and the pair of lead frames.2. The non-insulated power semiconductor module of claim 1 , wherein the pair of lead frames is configured such that electrode terminals and a base plate are integrated with each other.3. The non-insulated power semiconductor module of claim 1 , wherein the pair of lead frames is configured of a copper bus bar.4. The non-insulated power semiconductor module of claim 1 , wherein each of the power semiconductor chips is one of an Field Effect Transistor (FET) claim 1 , a Metal Oxide Semiconductor FET (MOSFET) claim 1 , an Insulated Gate Bipolar Mode Transistor (IGBT) claim 1 , and a power rectification diode.5. The non-insulated power semiconductor module of claim 1 , wherein a plurality of lead application layers is formed on the surfaces of the pair of lead frames for assembly of the power semiconductor chips claim 1 , and the power semiconductor chips and the lead application layers are bonded to each other in a lead soldering manner.6. The non-insulated power semiconductor module of claim 1 , wherein the pair of lead frames is configured such that input electrode terminals and an output electrode terminal have an integral connection portion.7. The non-insulated power semiconductor module of claim 1 , wherein the pair of lead frames is configured of an N-type lead frame and a P-type lead frame claim 1 , a plurality of upper-side power semiconductor chips of the power semiconductor chips is ...

APPARATUS FOR MANUFACTURING SEMICONDUCTOR DEVICE AND THE SEMICONDUCTOR DEVICE

An apparatus for a manufacturing semiconductor device including a plate member and a joint member. The apparatus includes a plate-type tool having the plate member mounted thereon, a first fixing tool and a second fixing tool having an inclined surface for abutting an upper edge of an end part in a width direction of plate member. The second fixing tool is fixed onto the plate-type tool adjacent to the end part. An ultrasonic horn applies ultrasonic vibration in the width direction of plate member while pressing the joint member toward the plate member. 1. An apparatus for manufacturing a semiconductor device including a plate member and a joint member , the plate member having a first end part which is an end of the plate member in a width direction of the plate member , the apparatus comprising:a plate-type tool for having the plate member to be mounted thereon; and a first fixing tool, and', 'a second fixing tool having an inclined surface for abutting an upper edge of the first end part of the plate member, the second fixing tool configured to be fixed onto the plate-type tool at a position adjacent to the first end part; and, 'a plurality of fixing tools including'}an ultrasonic horn for applying an ultrasonic vibration in the width direction of the plate member while pressing the joint member toward the plate member.2. The apparatus for manufacturing a semiconductor device according to claim 1 , wherein the second fixing tool has another inclined surface extending from a lower end of the second fixing tool to a side of the second fixing tool opposite to the plate member.3. The apparatus for manufacturing a semiconductor device according to claim 1 , wherein an angle formed by the inclined surface is 20° to 70° against a vertical direction.4. The apparatus for manufacturing a semiconductor device according to claim 2 , wherein an angle formed by the another inclined surface is 3° to 45° against a vertical direction.5. The apparatus for manufacturing a ...

THERMOSONICALLY BONDED CONNECTION FOR FLIP CHIP PACKAGES

A method of making a package is disclosed. The method may include forming bond pads on a first surface of a substrate, forming leads in the substrate by etching recesses in a second surface of the substrate, the second surface being opposite the first surface, and plating at least a portion of a top surface of the leads with a layer of finish plating. The method may also include thermosonically bonding the leads to a die by thermosonically bonding the finish plating to the die and encapsulating the die and the leads in an encapsulant. 1. A semiconductor package comprising:a semiconductor die having an active surface, a passivation layer on the active surface of the semiconductor die, the passivation layer having openings that expose portions of the active surface;leads having first and second opposing ends;a finish plating layer on the first ends of the leads, the leads being coupled directly to the semiconductor die by the finish plating layer through the openings in the passivation layer and without conductive bumps or conductive bonding wires therebetween; andan encapsulant that encapsulates the die and the leads and exposes the second ends of the leads.2. (canceled)3. The semiconductor package of claim 1 , wherein the openings in the passivation layer have a first shape and the finish plating layer has a second shape that corresponds to the first shape.4. The semiconductor package of claim 3 , wherein the finish plating layer is smaller in size than the openings in the passivation layer.5. The semiconductor package of claim 1 , wherein the openings in the passivation layer have a first thickness and the finish plating layer has a second thickness that corresponds to the first thickness.6. The semiconductor package of claim 5 , wherein the first thickness is less than the second thickness.7. The semiconductor package of claim 1 , wherein the finish plating layer on the first ends of the leads fully covers the first ends of the leads.8. A device claim 1 , ...

SEMICONDUCTOR MODULE

A semiconductor module includes a semiconductor element having one and the other surface, a lead terminal connected electrically and thermally to the semiconductor element, a first solder which bonds the lead terminal and the one surface of the semiconductor element together, a circuit layer over which the semiconductor element is disposed and a second solder which bonds the other surface of the semiconductor element and the circuit layer together. The inequality 1. A semiconductor module comprising:a semiconductor element having one surface and another surface opposite to the one surface;an external connection terminal connected electrically and thermally to the semiconductor element;a first solder which bonds the external connection terminal and the one surface of the semiconductor element together, the first solder having a first tensile strength;a metal substrate over which the semiconductor element is disposed; anda second solder which bonds said another surface of the semiconductor element and the metal substrate together, the second solder having a second tensile strength, a tensile strength ratio of the first tensile strength to the second tensile strength being less than 1.2. The semiconductor module according to claim 1 , wherein the tensile strength ratio is less than 0.8.3. The semiconductor module according to claim 1 , wherein the tensile strength ratio is greater than 0.2.4. The semiconductor module according to claim 1 , wherein when the tensile strength ratio is less than 1 claim 1 , a temperature is greater than or equal to 25° C. and less than or equal to 125° C.5. The semiconductor module according to claim 1 , wherein the first solder and the second solder are Sn—Sb based solders.6. The semiconductor module according to claim 5 , wherein an Sb content of the first solder is lower than an Sb content of the second solder.7. The semiconductor module according to claim 1 , wherein the first solder is an Sn—Cu based solder and the second solder is an ...

SEMICONDUCTOR DEVICE

In this semiconductor device, a positioning protrusion is formed at a side surface of a sealing resin from which one end of a main electrode wire protrudes. Thus, the outer size of the sealing resin can be reduced as compared to a case where a positioning protrusion is formed at the bottom of the sealing resin. In addition, a thickness regulating protrusion is provided with a space from solder. Thus, it is possible to prevent interface separation or crack that would occur starting from a contact part between the thickness regulating protrusion and the solder, whereby the life of a joining part between a semiconductor module and a cooler can be ensured. Accordingly, a semiconductor device having enhanced heat dissipation property and reliability is obtained without increase in the outer size of the semiconductor module.