Rippenfeldeffekttransistoren und Verfahren zur Herstellung derselben

Rippenfeldeffekttransistor (FinFET), umfassend:- ein Substrat (202) mit einer oberen Oberfläche (202s);- eine erste Rippe (212_1) und eine zweite Rippe (212_2), die sich über der oberen Substratoberfläche (202s) erstrecken, wobei die erste Rippe (212_1) eine obere Oberfläche (222t_1) und Seitenwände (222s_1) aufweist und die zweite Rippe (212_2) eine obere Oberfläche (222t_2) und Seitenwände (222s_2) aufweist;- eine Isolationsschicht (217) zwischen der ersten und der zweiten Rippe (212_1, 212_2), die sich teilweise von der oberen Substratoberfläche (202s) aus die Rippen (212_1, 212_2) hinauf erstreckt;- ein erstes Gate-Dielektrikum (224a), das die obere Oberfläche (222t_1) und die Seitenwände (222s_1) der ersten Rippe (212_1) mit einer ersten Dicke (t) bedeckt, wobei das erste Gate-Dielektrikum (224a) in direktem Kontakt mit der ersten Rippe (212_1) ist,- ein zweites Gate-Dielektrikum (234) mit einer zweiten Dicke (t), die kleiner als die erste Dicke (t) ist, wobei das zweite Gate-Dielektrikum ...

Halbleitervorrichtung mit verbessertem isoliertem Gate-Transistor

HALBLEITERVORRICHTUNG UND HERSTELLUNGSVERFAHREN

Es werden ein Halbleiter-Bauelement und ein Verfahren bereitgestellt, mit dem eine Mehrzahl von Abstandshaltern in einem ersten Bereich und einem zweiten Bereich eines Substrats hergestellt wird. Die Mehrzahl von Abstandshaltern in dem ersten Bereich wird strukturiert, während die Mehrzahl von Abstandshaltern in dem zweiten Bereich geschützt wird, um die Eigenschaften der Abstandshalter in dem ersten Bereich von den Eigenschaften der Abstandshalter in dem zweiten Bereich zu trennen.

Steuerung einer Rückseitenfinnenaussparung mit Möglichkeit mehrerer HSI

... [00119] Ausführungsformen der vorliegenden Erfindung betreffen eine Ausbildung von Finnen mit unterschiedlichen aktiven Kanalhöhen in einer Tri-Gate- oder einer Fin-FET-Vorrichtung. In einer Ausführungsform werden mindestens zwei Finnen an einer Vorderseite des Substrats ausgebildet. Eine Gatestruktur erstreckt sich über eine obere Fläche und ein Paar Seitenwände von zumindest einem Teil der Finnen. In einer Ausführungsform wird das Substrat ausgedünnt, um die untere Fläche der Finnen freizulegen. Als nächstes kann eine Rückseitenätzung an jeder Finne durchgeführt werden, um aktive Kanalregionen auszubilden. Die Finnen können in unterschiedlichen Tiefen ausgespart werden, wodurch aktive Kanalregionen mit unterschiedlichen Höhen ausgebildet werden.

Finnendiodenstruktur und deren Verfahren

Verfahren und Struktur zum Ausbilden einer Finnenbodendiode schließt die Bereitstellung eines Substrats ein, aus dem sich mehrere Finnen erstrecken. Jede der mehreren Finnen enthält einen Substratanteil und einen Epitaxialschichtanteil über dem Substratanteil. Eine erste Dotiersubstanzschicht wird auf Seitenwänden eines ersten Bereichs des Substratanteils von jeder der mehreren Finnen ausgebildet. Nach Ausbilden der ersten Dotiersubstanzschicht wird ein erster Temperprozess ausgeführt, um einen ersten Diodenbereich innerhalb des ersten Bereichs des Substratanteils zu bilden. Eine zweite Dotiersubstanzschicht wird auf Seitenwänden eines zweiten Bereichs des Substratanteils von jeder der mehreren Finnen ausgebildet. Nach Ausbilden der zweiten Dotiersubstanzschicht wird ein zweiter Temperprozess ausgeführt, um einen zweiten Diodenbereich innerhalb des zweiten Bereichs des Substratanteils von jeder der mehreren Finnen auszubilden.

Integrierte Schaltung und zugehöriges Herstellungsverfahren zur Verringerung von Funkelrauschen

Eine integrierte Schaltung, umfassend: ein Halbleitersubstrat (104); eine Vielzahl von auf dem Halbleitersubstrat (104) angeordneten Finnen (102A, 102B, 102C, 102D); einen Gateisolator (110; 302, 304), der auf der Vielzahl von Finnen angeordnet ist; und einen Gatestapel (112), der auf dem Gateisolator (110; 304) angeordnet ist, wobei jede der Vielzahl der Finnen (102A, 102B, 102C, 102D) ein Kanalgebiet an zumindest zwei Seitenflächen umfasst, wobei das Kanalgebiet zur Verringerung von Funkelrauschen ein Dotiermittel an den Seitenflächen beinhaltet, dessen Höchstkonzentration in der Mitte jeder Finne liegt, und wobei der Gateisolator (110; 302, 304) über den Seitenflächen von jeder der Finnen (102A, 102B, 102C, 102D) angeordnet ist, wobei der Gateisolator das Dotiermittel beinhaltet.

Transistor mit reduzierter Ladungsträgermobilität und assoziierte Verfahren

Ein Bauelement enthält einen ersten Transistor mit einem Steg und einen zweiten Transistor mit einem Steg, wobei der Steg des ersten Transistors eine niedrigere Ladungsträgermobilität als der Steg des zweiten Transistors aufweist. Bei einem Verfahren wird der Steg des ersten Transistors so behandelt, dass er eine niedrigere Ladungsträgermobilität als der Steg des zweiten Transistors aufweist.

Semiconductor arrangement with active drift zone

Structure and method to fabricate resistor on finfet processes

Varying carrier mobility on finfet active surfaces to achieve overall design goals

Semiconductor arrangement with active drift zone

Varying carrier mobility on finfet active surfaces to achieve overall design goals

Semiconductor devices and methods for forming the same

METHOD OF MANUFACTURING A TRANSISTOR MOS FIN

STRUCTURE AND METHOD FOR FinFET DEVICE

FIELD EFFECT TRANSISTOR AND SEMICONDUCTOR DEVICE INCLUDING THE SAME

양쪽 사이드들 상의 금속화가 있는 반도체 디바이스들에 대한 후면 콘택트 저항 감소

MOBS(metallization on both sides)가 있는 반도체 디바이스들에 대한 후면 콘택트 저항 감소를 위한 기술들이 개시된다. 일부 실시예들에서, 본 명세서에서 설명되는 기술들은 후면 콘택트들을 이루는 것에 있어서 그렇지 않으면 존재할 낮은 콘택트 저항을 복구하는 방법들을 제공하고, 그렇게 함으로써 트랜지스터 성능을 저하시키는 기생 외부 저항을 감소시키거나 또는 제거한다. 일부 실시예들에서, 이러한 기술들은 후면 콘택트 트렌치들에서의 고도로 도핑된 결정질 반도체 재료의 에피택셜 퇴적을 추가하여 강화된 오믹 콘택트 특성들을 제공하는 것을 포함한다. 일부 경우들에서, 후면 S/D(source/drain) 에칭 정지 층은 (전면 처리 동안) 전사 웨이퍼 상에 형성되는 하나 이상의 트랜지스터의 대체 S/D 영역들 아래에 형성될 수 있어, 후면 콘택트 트렌치들이 형성될 때, 후면 S/D 에칭 정지 층은 S/D 재료의 일부 또는 전부를 소비하기 이전에 후면 콘택트 에칭 프로세스를 정지하는데 도움이 될 수 있다. 다른 실시예들이 설명 및/또는 개시될 수 있다.

SEMICONDUCTOR DEVICE INCLUDING FIN AND DRAIN EXTENSION REGION AND MANUFACTURING METHOD

Provided is a semiconductor device with a fin and a drain extension region. An embodiment of the semiconductor device includes a fin on a first side of a semiconductor body. At least part of the fin of the semiconductor device further includes a body region of a second conductivity type. The semiconductor device further includes a drain extension region of a first conductivity type, a source and drain region of the first conductivity type, and a gate structure touching the opposite wall of the fin. The body region and the drain extension region are successively arranged between the source region and the drain region. COPYRIGHT KIPO 2016 ...

SEMICONDUCTOR DEVICE INCLUDING A FIN AND A DRAIN EXTENSION REGION AND MANUFACTURING METHOD

집적회로 장치

... 집적회로 장치는, 핀형 활성 영역을 갖는 기판; 상기 기판 상에서 상기 핀형 활성 영역과 교차하는 게이트 구조물; 상기 게이트 구조물의 양 측벽 상에 배치되는 스페이서 구조물로서, 상기 게이트 구조물의 양 측벽의 적어도 일부분과 접촉하는 제1 스페이서층과, 상기 제1 스페이서층 상에 배치되며 상기 제1 스페이서층보다 낮은 유전 상수를 갖는 제2 스페이서층을 포함하는 스페이서 구조물; 상기 게이트 구조물 양 측에 배치되는 소스/드레인 영역; 및 상기 소스/드레인 영역과 전기적으로 연결되는 제1 콘택 구조물로서, 상기 소스/드레인 영역 상에 배치되는 제1 콘택 플러그와, 상기 제1 콘택 플러그 상에 배치되는 제1 금속성 캡핑층을 포함하는 상기 제1 콘택 구조물을 포함한다.

VOLTAGE CONTROLLED OSCILLATOR WITH A MULTIPLE GATE TRANSISTOR AND METHOD THEREFOR

A voltage controlled oscillator (VCO) (40) has a plurality (42, 44, 46) of series-connected inverters. Within each inverter a first transistor (48) has a first current electrode coupled to a first power supply voltage terminal (VDD), a second current electrode, a first control electrode coupled to an output terminal of another inverter of the plurality of series-connected inverters, and a second control electrode for receiving a first bias signal. A second transistor (50) has a first current electrode coupled to the second current electrode of the first transistor, a second current electrode coupled to a second power supply voltage terminal (VSS), and a first control electrode coupled to the first control electrode of the first transistor. The second control electrode of the first transistor of each inverter receives a same or separate analog control signal (VGP, VPP OR DNP) to adjust the threshold voltage of the first transistors thereof to affect frequency and phase of the VCO's signal ...

Semiconductor device and manufacturing method therefor

A memory gate electrode and a control gate electrode are formed to cover a fin projecting from the upper surface of a semiconductor substrate. A part of the fin which is covered by the memory gate electrode and the control gate electrode is sandwiched by a silicide layer as a part of a source region and a drain region of a memory cell. This silicide layer is formed as a silicide layer.

Vertically stacked complementary-FET device with independent gate control

A method includes forming a stack of semiconductor material layers. A first spacer is formed adjacent a lower region at a first end of the stack, and a second spacer is formed adjacent an upper region positioned at a second end of the stack. A gate structure and sidewall spacer are formed above the stack. The gate structure and a first subset of the semiconductor layers are removed to define inner cavities and a gate cavity. A gate insulation layer is formed. A first conductive material is formed in the inner cavities. The first conductive material is selectively removed from the inner cavities in the upper region. The first conductive material in the inner cavities in the lower region remains as a first gate electrode. A second conductive material is formed in the inner cavities in the upper region to define a second gate electrode.

Semiconductor device

Method of forming field effect transistor(s), and an integrated circuit including field effect transistors

INTEGRATED CIRCUIT USING FINFETS AND HAVING A STATIC RANDOM ACCESS MEMORY (SRAM)

An integrated circuit (10) includes a logic circuit and a memory cell (21). The logic circuit includes a P-channel transistor (18), and the memory cell includes a P-channel transistor. The P-channel transistor of the logic circuit includes a channel region. The channel region has a portion located along a sidewall of a semiconductor structure having a surface orientation of (110). The portion of the channel region located along the sidewall has a first vertical dimension that is greater than a vertical dimension of any portion of the channel region of the P-channel transistor of the memory cell located along a sidewall of a semiconductor structure having a surface orientation of (110).

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Disclosed are a semiconductor device and manufacturing method thereof, an exemplary device comprising: a substrate; a back gate formed on the substrate; fins formed on the two sides of the back gate; and a dielectric layer sandwiched between the back gate and each fin; the end portions on the two opposite sides of the back gate are recessed relative to the middle portion between the end portions, so that the overlap area between the end portion and each fin is less than the overlap area between the middle portion and the fin.

TECHNIQUES FOR FORMING GE/SIGE-CHANNEL AND III-V-CHANNEL TRANSISTORS ON THE SAME DIE

Techniques are disclosed for forming Ge/SiGe-channel and III-V-channel transistors on the same die. The techniques include depositing a pseudo-substrate of Ge/SiGe or III-V material on a Si or insulator substrate. The pseudo-substrate can then be patterned into fins and a subset of the fins can be replaced by the other of Ge/SiGe or III-V material. The Ge/SiGe fins can be used for p-MOS transistors and the III-V material fins can be used for n-MOS transistors, and both sets of fins can be used for CMOS devices, for example. In some instances, only the channel region of the subset of fins are replaced during, for example, a replacement gate process. In some instances, some or all of the fins may be formed into or replaced by one or more nanowires or nanoribbons.

Semiconductor structure and manufacturing method thereof

A method for manufacturing a semiconductor structure includes forming a plurality of dummy semiconductor fins on a substrate. The dummy semiconductor fins are adjacent to each other and are grouped into a plurality of fin groups. The dummy semiconductor fins of the fin groups are recessed one group at a time.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

A semiconductor device in which parasitic capacitance is reduced is provided. A first oxide insulating layer and a first oxide semiconductor layer are sequentially formed over a first insulating layer. A first conductive layer is formed over the first oxide semiconductor layer and etched to form a second conductive layer. The first oxide insulating layer and the first oxide semiconductor layer are etched with the second conductive layer as a mask to form a second oxide insulating layer and a second oxide semiconductor layer. A planarized insulating layer is formed over the first insulating layer and the second conductive layer. A second insulating layer, a source electrode layer, and a drain electrode layer are formed by etching the planarized insulating layer and the second conductive layer. A third oxide insulating layer, a gate insulating layer, and a gate electrode layer are formed over the second oxide semiconductor layer.

Method of forming non-planar FET

A method of forming a Non-planar FET is provided. A substrate is provided. An active region and a peripheral region are defined on the substrate. A plurality of VSTI is formed in the active region of the substrate. A part of each VSTI is removed to expose a part of sidewall of the substrate. Then, a conductor layer is formed on the substrate which is then patterned to form a planar FET gate in the peripheral region and a Non-planar FET gate in the active region simultaneously. Last, a source/drain region is formed on two sides of the Non-planar FET gate.

Semiconductor device and method for manufacturing same

There is provided a semiconductor device having excellent device characteristics and reliability in which Vth values of an nMOS transistor and a pMOS transistor are controlled to be values necessary for a low-power device. The semiconductor device includes a pMOS transistor and an nMOS transistor formed by using an SOI substrate. The pMOS transistor is a fully depleted MOS transistor including a first gate electrode comprising at least one type of crystalline phase selected from the group consisting of a WSi2 crystalline phase, an MoSi2 crystalline phase, an NiSi crystalline phase, and an NiSi2 crystalline phase as silicide region (1). The nMOS transistor is a fully depleted MOS transistor comprising at least one type of crystalline phase selected from the group consisting of a PtSi crystalline phase, a Pt2Si crystalline phase, an IrSi crystalline phase, an Ni2Si crystalline phase, and an Ni3Si crystalline phase as silicide region (2).

Epitaxial structures for fin-like field effect transistors

Epitaxial structures of a fin-like field effect transistor (FinFET) device includes a substrate, a fin structure including two fins, inner and outer fin spacers formed along both sidewalls of the fins, and isolation regions formed around the fins. The FinFET device further includes a gate structure formed over the fin structure and an epitaxial structure formed over the fin structure in a source/drain region. The epitaxial structure is formed by merging the fins with at least one epitaxial semiconductor layer and includes an air gap having a volume determined by the height and separation distance of the inner fin spacers.

Ge/SiGe-channel and III-V-channel transistors on the same die

Techniques are disclosed for forming Ge/SiGe-channel and III-V-channel transistors on the same die. The techniques include depositing a pseudo-substrate of Ge/SiGe or III-V material on a Si or insulator substrate. The pseudo-substrate can then be patterned into fins and a subset of the fins can be replaced by the other of Ge/SiGe or III-V material. The Ge/SiGe fins can be used for p-MOS transistors and the III-V material fins can be used for n-MOS transistors, and both sets of fins can be used for CMOS devices, for example. In some instances, only the channel region of the subset of fins are replaced during, for example, a replacement gate process. In some instances, some or all of the fins may be formed into or replaced by one or more nanowires or nanoribbons.

Method to form a 3D semiconductor device and structure

A method to form a 3D semiconductor device, the method including: providing a first level including first circuits, the first circuits including first transistors and first interconnection; preparing a second level including a silicon layer; forming second circuits over the second level, the second circuits including second transistors and second interconnection; transferring with bonding the second level on top of the first level; and then thinning the second level to a thickness of less than ten microns, where the bonding includes oxide to oxide bonds, and where the bonding includes metal to metal bonds.

Semiconductor device and manufacturing method of the same

An aspect of the present invention provides a semiconductor device that includes a first transistor including a source region, a drain region provided in the same device region as the source region, and a loop-shaped gate electrode region, and a second transistor sharing, with the first transistor, the loop-shaped gate electrode region and the source region or the drain region.

POWER RAILS FOR STACKED SEMICONDUCTOR DEVICE

The present disclosure describes a method to form a stacked semiconductor device with power rails. The method includes forming the stacked semiconductor device on a first surface of a substrate. The stacked semiconductor device includes a first fin structure, an isolation structure on the first fin structure, and a second fin structure above the first fin structure and in contact with the isolation structure. The first fin structure includes a first source/drain (S/D) region, and the second fin structure includes a second S/D region. The method also includes etching a second surface of the substrate and a portion of the first S/D region or the second S/D region to form an opening. The second surface is opposite to the first surface. The method further includes forming a dielectric barrier in the opening and forming an S/D contact in the opening.

FORMING A COMBINATION OF LONG CHANNEL DEVICES AND VERTICAL TRANSPORT FIN FIELD EFFECT TRANSISTORS ON THE SAME SUBSTRATE

A method of forming a vertical transport fin field effect transistor and a long-channel field effect transistor on the same substrate, including, forming a recessed region in a substrate and a fin region adjacent to the recessed region, forming one or more vertical fins on the fin region, forming a long-channel pillar from the substrate in the recessed region, where the long-channel pillar is at a different elevation than the one or more vertical fins, forming two or more long-channel source/drain plugs on the long-channel pillar, forming a bottom source/drain plug in the fin region, where the bottom source/drain plug is below the one or more vertical fins, forming a gate structure on the long-channel pillar and a gate structure on the one or more vertical fins, and forming a top source/drain on the top surface of the one or more vertical fins.

Method for Patterning a Plurality of Features For Fin-Like Field-Effect Transistor (FINFET) Devices

A method for patterning fins for FinFET devices are disclosed. The method includes forming elongated protrusions on a semiconductor substrate and forming a mask covering a first portion of the elongated protrusions. The method further includes forming a spacer surrounding the mask. The mask and the spacer together cover a second portion of the elongated protrusions. The method further includes removing a portion of the elongated protrusions not covered by the mask and the spacer. In an embodiment, an outer boundary of the spacer and the mask corresponds to an outer boundary of a non-rectangular pattern.

Semiconductor structure with multiple fins having different channel region heights and method of forming the semiconductor structure

Disclosed are embodiments of a semiconductor structure with fins that are positioned on the same planar surface of a wafer and that have channel regions with different heights. In one embodiment the different channel region heights are accomplished by varying the overall heights of the different fins. In another embodiment the different channel region heights are accomplished by varying, not the overall heights of the different fins, but rather by varying the heights of a semiconductor layer within each of the fins. The disclosed semiconductor structure embodiments allow different multi-gate non-planar FETs (i.e., tri-gate or dual-gate FETs) with different effective channel widths to be formed of the same wafer and, thus, allows the beta ratio in devices that incorporate multiple FETs (e.g., static random access memory (SRAM) cells) to be selectively adjusted.

Complementary metal oxide semiconductor device with III-V optical interconnect having III-V epitaxial semiconductor material formed using lateral overgrowth

An electrical device that includes a first semiconductor device positioned on a first portion of a substrate and a second semiconductor device positioned on a third portion of the substrate, wherein the first and third portions of the substrate are separated by a second portion of the substrate. An interlevel dielectric layer is present on the first, second and third portions of the substrate. The interlevel dielectric layer is present over the first and second semiconductor devices. An optical interconnect is positioned over the second portion of the semiconductor substrate. At least one material layer of the optical interconnect includes an epitaxial material that is in direct contact with a seed surface within the second portion of the substrate through a via extending through the least one interlevel dielectric layer.

Formation of capacitor having a Fin structure

Device designs and methods are described for incorporating capacitors commonly used in planar CMOS technology into a FinFET based technology. A capacitor includes at least one single-crystal Fin structure having a top surface and a first side surface opposite a second side surface. Adjacent the top surface of the at least one Fin structure is at least one insulator structure. Adjacent the at least one insulator structure and over a portion of the at least one Fin structure is at least one conductor structure. Decoupling capacitors may be formed at the circuit device level using simple design changes within the same integration method, thereby allowing any number, combination, and/or type of decoupling capacitors to be fabricated easily along with other devices on the same substrate to provide effective decoupling capacitance in an area-efficient manner with superior high-frequency response.

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

A semiconductor device comprises a first fin-type pattern comprising a first long side extending in a first direction, and a first short side extending in a second direction. A second fin-type pattern is arranged substantially parallel to the first fin-type pattern. A first gate electrode intersects the first fin-type pattern and the second fin-type pattern. The second fin-type pattern comprises a protrusion portion that protrudes beyond the first short side of the first fin-type pattern. The first gate electrode overlaps with an end portion of the first fin-type pattern that comprises the first short side of the first fin-type pattern. At least part of a first sidewall of the first fin-type pattern that defines the first short side of the first fin-type pattern is defined by a first trench having a first depth. The first trench directly adjoins a second trench having a second, greater, depth.

Method of co-integration of strained silicon and strained germanium in semiconductor devices including fin structures

A method of forming a semiconductor device that includes forming an at least partially relaxed semiconductor material, and forming a plurality of fin trenches in the partially relaxed semiconductor material. At least a portion of the plurality of fin trenches is filled with a first strained semiconductor material that is formed using epitaxial deposition. A remaining portion of the at least partially relaxed semiconductor material is removed to provide a plurality of fin structure of the first strained semiconductor material.

FinFET with embedded MOS varactor and method of making same

Embodiments of the present disclosure are a semiconductor device, a FinFET device, and a method of forming a FinFET device. An embodiment is semiconductor device including a first FinFET over a substrate, wherein the first FinFET includes a first set of semiconductor fins. The semiconductor device further includes a first body contact for the first FinFET over the substrate, wherein the first body contact includes a second set of semiconductor fins, and wherein the first body contact is laterally adjacent the first FinFET.

Integrated circuit with capacitors having a fin structure

Device designs and methods are described for incorporating capacitors commonly used in planar CMOS technology into a FinFET based technology. A capacitor includes at least one single-crystal Fin structure having a top surface and a first side surface opposite a second side surface. Adjacent the top surface of the at least one Fin structure is at least one insulator structure. Adjacent the at least one insulator structure and over a portion of the at least one Fin structure is at least one conductor structure. Decoupling capacitors may be formed at the circuit device level using simple design changes within the same integration method, thereby allowing any number, combination, and/or type of decoupling capacitors to be fabricated easily along with other devices on the same substrate to provide effective decoupling capacitance in an area-efficient manner with superior high-frequency response.

METAL ON BOTH SIDES OF THE TRANSISTOR INTEGRATED WITH MAGNETIC INDUCTORS

An apparatus and a system including an apparatus including a circuit structure including a device stratum including a plurality of transistor devices each including a first side and an opposite second side; an inductor disposed on the second side of the structure; and a contact coupled to the inductor and routed through the device stratum and coupled to at least one of the plurality of transistor devices on the first side. A method including forming a plurality of transistor devices on a substrate, the plurality of transistor devices defining a device stratum including a first side and an opposite second side, wherein the second side is coupled to the substrate; removing a portion of the substrate; forming at least one inductor on the second side of the device stratum; and coupling the at least one inductor to at least one of the plurality of transistor devices.

Connection structure for vertical gate all around (VGAA) devices on semiconductor on insulator (SOI) substrate

A vertical gate all around (VGAA) nanowire device circuit routing structure is disclosed. The circuit routing structure comprises a plurality of VGAA nanowire devices including a NMOS and a PMOS device. The devices are formed on a semiconductor-on-insulator substrate. Each device comprises a bottom plate and a top plate wherein one of the bottom and top plates serves as a drain node and the other serves as a source node. Each device further comprises a gate layer. The gate layer fully surrounds a vertical channel in the device. In one example, a CMOS circuit is formed with an oxide (OD) block layer that serves as a common bottom plate for the NMOS and PMOS devices. In another example, a CMOS circuit is formed with a top plate that serves as a common top plate for the NMOS device and the PMOS devices. In another example, a SRAM circuit is formed.

P-FET with graded silicon-germanium channel

A method of forming a semiconductor structure includes forming a silicon-germanium layer on a semiconductor region of a substrate having a specific concentration of germanium atoms. The semiconductor region and the silicon-germanium layer are annealed to induce a non-homogenous thermal diffusion of germanium atoms from the silicon-germanium layer into the semiconductor region to form a graded silicon-germanium region. Another method of forming a semiconductor structure includes etching a semiconductor region of the substrate to form a thinned semiconductor region. A silicon-germanium layer is formed on the thinned semiconductor region having a graded germanium concentration profile.

FIN FIELD-EFFECT TRANSISTOR STRUCTURE AND METHOD FOR FORMING THE SAME

A fin field-effect transistor (FinFET) structure and a method for forming the same are provided. The FinFET structure includes a first fin structure that protrudes from a first region of a substrate. A second fin structure protrudes from a second region of the substrate. Isolation regions cover lower portions of the first fin structure and the second fin structure and leave upper portions of the first fin structure and the second fin structure above the isolation regions. A first liner layer is positioned between the lower portion of the first fin structure and the isolation regions in the first region. A second liner layer covers the lower portion of the second fin structure and is positioned between the second fin structure and the isolation regions in the second region. The first liner layer and the second liner layer are formed of different materials.

Porous silicon relaxation medium for dislocation free CMOS devices

A method for forming CMOS devices includes masking a first portion of a tensile-strained silicon layer of a SOI substrate, doping a second portion of the layer outside the first portion and growing an undoped silicon layer on the doped portion and the first portion. The undoped silicon layer becomes tensile-strained. Strain in the undoped silicon layer over the doped portion is relaxed by converting the doped portion to a porous silicon to form a relaxed silicon layer. The porous silicon is converted to an oxide. A SiGe layer is grown and oxidized to convert the relaxed silicon layer to a compressed SiGe layer. Fins are etched in the first portion from the tensile-strained silicon layer and the undoped silicon layer and in the second portion from the compressed SiGe layer.

COMPRESSIVE STRAINED III-V COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) DEVICE

A semiconductor device including a first lattice dimension III-V semiconductor layer present on a semiconductor substrate, and a second lattice dimension III-V semiconductor layer that present on the first lattice dimension III-V semiconductor layer, wherein the second lattice dimension III-V semiconductor layer has a greater lattice dimension than the first lattice dimension III-V semiconductor layer, and the second lattice dimension III-V semiconductor layer has a compressive strain present therein. A gate structure is present on a channel portion of the second lattice dimension III-V semiconductor layer, wherein the channel portion of second lattice dimension III-V semiconductor layer has the compressive strain. A source region and a drain region are present on opposing sides of the channel portion of the second lattice dimension III-V semiconductor layer.

FINFET STRUCTURE AND METHOD TO ADJUST THRESHOLD VOLTAGE IN A FINFET STRUCTURE

FinFET structures and methods of manufacturing the FinFET structures are disclosed. The method includes performing an oxygen anneal process on a gate stack of a FinFET structure to induce Vt shift. The oxygen anneal process is performed after sidewall pull down and post silicide.

STACKED SHORT AND LONG CHANNEL FINFETS

An analog integrated circuit is disclosed in which short channel transistors are stacked on top of long channel transistors, vertically separated by an insulating layer. With such a design, it is possible to produce a high density, high power, and high performance analog integrated circuit chip including both short and long channel devices that are spaced far enough apart from one another to avoid crosstalk. In one embodiment, the transistors are FinFETs and the long channel devices are multi-gate FinFETs. In one embodiment, single and dual damascene devices are combined in a multi-layer integrated circuit cell. The cell may contain various combinations and configurations of the short and long-channel devices. A high density cell can be made by simply shrinking the dimensions of the cells and replicating two or more cells in the same size footprint as the original cell.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device includes plurality of fin structures extending in first direction on semiconductor substrate. Fin structure's lower portion is embedded in first insulating layer. First gate electrode and second gate electrode structures extend in second direction substantially perpendicular to first direction over of fin structures and first insulating layer. The first and second gate electrode structures are spaced apart and extend along line in same direction. First and second insulating sidewall spacers are arranged on opposing sides of first and second gate electrode structures. Each of first and second insulating sidewall spacers contiguously extend along second direction. A second insulating layer is in region between first and second gate electrode structures. The second insulating layer separates first and second gate electrode structures. A third insulating layer is in region between first and second gate electrode structures. The third insulating layer is formed of different ...

Fin field effect transistors (FETs) (FinFETs) employing dielectric material layers to apply stress to channel regions

Fin Field Effect transistors (FETs) (FinFETs) employing dielectric material layers to apply stress to channel regions are disclosed. In one aspect, a FinFET is provided that includes a substrate and a Fin disposed over the substrate. The Fin includes a source, a drain, and a channel region between the source and drain. A gate is disposed around the channel region. To apply stress to the channel region, a first dielectric material layer is disposed over the substrate and adjacent to one side of the Fin. A second dielectric material layer is disposed over the substrate and adjacent to another side of the Fin. The dielectric material layers apply stress along the Fin, including the channel region. The level of stress applied by the dielectric material layers is not dependent on the volume of each layer.

Uniform height tall fins with varying silicon germanium concentrations

A method of making a semiconductor device includes forming a first fin in a first semiconducting material layer disposed over a substrate, the first semiconducting material layer comprising an element in a first concentration; and forming a second fin in a second semiconducting material layer disposed over the substrate and adjacent to the first semiconducting material layer, the second semiconducting material layer comprising the element in a second concentration; wherein the first concentration is different than the second concentration.

CARBON-DOPED CAP FOR A RAISED ACTIVE SEMICONDUCTOR REGION

After formation of a disposable gate structure, a raised active semiconductor region includes a vertical stack, from bottom to top, of an electrical-dopant-doped semiconductor material portion and a carbon-doped semiconductor material portion. A planarization dielectric layer is deposited over the raised active semiconductor region, and the disposable gate structure is replaced with a replacement gate structure. A contact via cavity is formed through the planarization dielectric material layer by an anisotropic etch process that employs a fluorocarbon gas as an etchant. The carbon in the carbon-doped semiconductor material portion retards the anisotropic etch process, and the carbon-doped semiconductor material portion functions as a stopping layer for the anisotropic etch process, thereby making the depth of the contact via cavity less dependent on variations on the thickness of the planarization dielectric layer or pattern factors.

System, apparatus, and method for N/P tuning in a fin-FET

The n-type to p-type fin-FET strength ratio in an integrated logic circuit may be tuned by the use of cut regions in the active and dummy gate electrodes. In some examples, separate cut regions for the dummy gate electrodes and the active gate electrode may be used to allow for different lengths of gate pass-active regions resulting in appropriately tuned integrated logic circuits.

FinFET source-drain merged by silicide-based material

A method includes conducting a laser-based anneal treatment on a metal layer positioned above and in direct contact with a top portion of a silicon cap layer located in direct contact with a first diamond shaped epitaxial layer surrounding a first fin and a second diamond shaped epitaxial layer surrounding a second fin. The metal layer extends from the top portion of the silicon cap layer in direct contact with the first diamond shaped epitaxial layer to the top portion of the silicon cap layer in direct contact with the second diamond shaped epitaxial layer. The conducted laser-based anneal treatment forms a silicide layer, a portion of the silicide layer between the first and the second diamond shaped epitaxial layers is substantially thicker than a portion of the silicide layer in contact with the first and the second diamond shaped epitaxial layers.

ENHANCED CHANNEL STRAIN TO REDUCE CONTACT RESISTANCE IN NMOS FET DEVICES

A semiconductor device includes a substrate, a fin structure and an isolation layer formed on the substrate and adjacent to the fin structure. The semiconductor device includes a gate structure formed on at least a portion of the fin structure and the isolation layer. The semiconductor device includes an epitaxial layer including a strained material that provides stress to a channel region of the fin structure. The epitaxial layer has a first region and a second region, in which the first region has a first doping concentration of a first doping agent and the second region has a second doping concentration of a second doping agent. The first doping concentration is greater than the second doping concentration. The epitaxial layer is doped by ion implantation using phosphorous dimer.

POROUS SILICON RELAXATION MEDIUM FOR DISLOCATION FREE CMOS DEVICES

A method for forming CMOS devices includes masking a first portion of a tensile-strained silicon layer of a SOI substrate, doping a second portion of the layer outside the first portion and growing an undoped silicon layer on the doped portion and the first portion. The undoped silicon layer becomes tensile-strained. Strain in the undoped silicon layer over the doped portion is relaxed by converting the doped portion to a porous silicon to form a relaxed silicon layer. The porous silicon is converted to an oxide. A SiGe layer is grown and oxidized to convert the relaxed silicon layer to a compressed SiGe layer. Fins are etched in the first portion from the tensile-strained silicon layer and the undoped silicon layer and in the second portion from the compressed SiGe layer. 1. A method for forming complementary metal oxide semiconductor devices , comprising:masking a first portion of a tensile-strained silicon layer of a silicon on insulator substrate with a hard mask;doping a second portion of the tensile-strained silicon layer outside the first portion;removing the hard mask;growing an undoped silicon layer on the doped portion and the first portion, wherein the undoped silicon layer becomes a tensile-strained undoped silicon layer;relaxing strain in the undoped silicon layer over the doped portion by converting the doped portion to a porous silicon to form a relaxed silicon layer;converting the porous silicon to an oxide;growing a SiGe layer on the relaxed silicon layer;oxidizing the SiGe layer to convert the relaxed silicon layer to a compressed SiGe layer; andetching fins in the first portion from the tensile-strained silicon layer and the undoped silicon layer and in the second portion from the compressed SiGe layer.2. The method as recited in claim 1 , wherein doping the second portion of the tensile-strained silicon layer includes boron doping the second portion.3. The method as recited in claim 1 , wherein relaxing strain in the undoped silicon layer over ...

Semiconductor device comprising transistor structures and methods for forming same

A method for forming an opening within a semiconductor material comprises forming a neck portion, a rounded portion below the neck portion and, in some embodiments, a protruding portion below the rounded portion. This opening may be filled with a conductor, a dielectric, or both. Embodiments to form a transistor gate, shallow trench isolation, and an isolation material separating a transistor source and drain are disclosed. Device structures formed by the method are also described.

Semiconductor device and method for manufacturing the same

Disclosed is a semiconductor device comprising an underlying insulating film having a depression, a semiconductor structure which includes a first semiconductor portion having a portion formed on the underlying insulating film and a first overlap portion which overlaps the depression, a second semiconductor portion having a portion formed on the underlying insulating film and a second overlap portion which overlaps the depression, and a third semiconductor portion disposed between the first and second semiconductor portions and having a portion disposed above the depression, wherein overlap width of the first overlap portion and overlap width of the second overlap portion are equal to each other, a gate electrode including a first electrode portion covering upper and side surfaces of the third semiconductor portion and a second electrode portion formed in the depression, and a gate insulating film interposed between the semiconductor structure and the gate electrode.

Semiconductor structures with deep trench capacitor and methods of manufacture

An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins.

Sеmiсоnduсtоr dеviсе аnd mеthоd fоr mаnufасturing sаmе

Тhеrе is prоvidеd а sеmiсоnduсtоr dеviсе hаving ехсеllеnt dеviсе сhаrасtеristiсs аnd rеliаbilitу in whiсh Vth vаluеs оf аn nМОS trаnsistоr аnd а pМОS trаnsistоr аrе соntrоllеd tо bе vаluеs nесеssаrу fоr а lоw-pоwеr dеviсе. Тhе sеmiсоnduсtоr dеviсе inсludеs а pМОS trаnsistоr аnd аn nМОS trаnsistоr fоrmеd bу using аn SОI substrаtе. Тhе pМОS trаnsistоr is а fullу dеplеtеd МОS trаnsistоr inсluding а first gаtе еlесtrоdе соmprising аt lеаst оnе tуpе оf сrуstаllinе phаsе sеlесtеd frоm thе grоup соnsisting оf а WSi2 сrуstаllinе phаsе, аn МоSi2 сrуstаllinе phаsе, аn NiSi сrуstаllinе phаsе, аnd аn NiSi2 сrуstаllinе phаsе аs siliсidе rеgiоn (1). Тhе nМОS trаnsistоr is а fullу dеplеtеd МОS trаnsistоr соmprising аt lеаst оnе tуpе оf сrуstаllinе phаsе sеlесtеd frоm thе grоup соnsisting оf а РtSi сrуstаllinе phаsе, а Рt2Si сrуstаllinе phаsе, аn IrSi сrуstаllinе phаsе, аn Ni2Si сrуstаllinе phаsе, аnd аn Ni3Si сrуstаllinе phаsе аs siliсidе rеgiоn (2).

SEMICONDUCTOR DEVICES

A semiconductor device includes a substrate including an active region that extends in a first direction; a gate structure that intersects the active region and that extends in a second direction; a source/drain region on the active region on at least one side of the gate structure; a contact plug on the source/drain region on the at least one side of the gate structure; and a contact insulating layer on sidewalls of the contact plug, wherein a lower end of the contact plug is closer to the substrate than a lower end of the source/drain region.

Back side processing of integrated circuit structures to form insulation structure between adjacent transistor structures

Techniques are disclosed for forming integrated circuit structures having a plurality of non-planar transistors. An insulation structure is provided between channel, source, and drain regions of neighboring fins. The insulation structure is formed during back side processing, wherein at least a first portion of the isolation material between adjacent fins is recessed to expose a sub-channel portion of the semiconductor fins. A spacer material is then deposited at least on the exposed opposing sidewalls of the exposed sub-channel portion of each fin. The isolation material is then further recessed to form an air gap between gate, source, and drain regions of neighboring fins. The air gap electrically isolates the source/drain regions of one fin from the source/drain regions of an adjacent fin, and likewise isolates the gate region of the one fin from the gate region of the adjacent fin. The air gap can be filled with a dielectric material.

Semiconductor device having epitaxy source/drain regions

A device includes first and second semiconductor fins, first, second, third and fourth fin sidewall spacers, and first and second epitaxy structures. The first and second fin sidewall spacers are respectively on opposite sides of the first semiconductor fin. The third and fourth fin sidewall spacers are respectively on opposite sides of the second semiconductor fin. The first and third fin sidewall spacers are between the first and second semiconductor fins and have smaller heights than the second and fourth fin sidewall spacers. The first and second epitaxy structures are respectively on the first and second semiconductor fins and merged together.

SEMICONDUCTOR DEVICE HAVING EPITAXY SOURCE/DRAIN REGIONS

An IC structure includes a first fin structure, a first epitaxial structure, first sidewall spacers, a second fin structure, a second epitaxial structure, and second sidewall spacers. The first epitaxial structure is on the first structure. The first sidewall spacers are respectively on opposite sidewalls of the first epitaxial structure. The second epitaxial structure is on the second fin structure. The second sidewall spacers are respectively on opposite sidewalls of the second epitaxial structure. A height difference between the second sidewall spacers is greater than a height difference between the first sidewall spacers.

Semiconductor devices and methods of manufacture thereof

Semiconductor devices and methods of manufacture thereof are disclosed. A complimentary metal oxide semiconductor (CMOS) device includes a PMOS transistor having at least two first gate electrodes comprising a first parameter, and an NMOS transistor having at least two second gate electrodes comprising a second parameter, wherein the second parameter is different than the first parameter. The first parameter and the second parameter may comprise the thickness or the dopant profile of the gate electrode materials of the PMOS and NMOS transistors. The first and second parameter of the at least two first gate electrodes and the at least two second gate electrodes establish the work function of the PMOS and NMOS transistors, respectively.

Hochspannungshalbleiterbauelemente

Bei einer Ausführungsform enthält das Halbleiterbauelement (10) eine erste Sourceelektrode (120) von einem ersten Dotiertyp, in einem Substrat (100) angeordnet. Eine erste Drainelektrode (130) vom ersten Datiertyp ist in dem Substrat (100) angeordnet. Eine erste Gateelektrode (140) ist zwischen der ersten Sourceelektrode (120) und der ersten Drainelektrode (130) angeordnet. Ein erstes Kanalgebiet (160) von einem zweiten Dotiertyp ist unter dem ersten Gategebiet (140) angeordnet. Der zweite Dotiertyp ist dem ersten Dotiertyp entgegengesetzt. Ein erstes Erweiterungsgebiet vom ersten Dotiertyp ist zwischen der ersten Gateelektrode (140) und der ersten Drainelektrode (130) angeordnet. Das erste Erweiterungsgebiet ist Teil einer in oder über dem Substrat (100) angeordneten ersten Finne (190). Ein erstes Isolationsgebiet ist zwischen dem ersten Erweiterungsgebiet und der ersten Drainelektrode angeordnet. Ein erstes Wannengebiet vom ersten Dotiertyp ist unter dem ersten Isolationsgebiet angeordnet ...

3D-Halbleiterbauelement und Verfahren zur Herstellung desselben

Die vorliegende Erfindung betrifft ein Halbleiterbauelement und ein Verfahren zu dessen Herstellung. Ein derartiges Halbleiterbauelement umfasst ein Substrat und eine 3D-Struktur, die über dem Substrat angeordnet ist. Das Halbleiterbauelement umfasst ferner eine dielektrische Schicht, die über der 3D-Struktur angeordnet ist, eine Austrittsarbeitsmetallgruppenschicht (WFMG-Schicht), die über der dielektrischen Schicht angeordnet ist, und eine Gate-Struktur, die über der WFMG-Schicht angeordnet ist. Die Gate-Struktur durchdringt die 3D-Struktur und trennt einen Source-Bereich von einem Drain-Bereich der 3D-Struktur. Der Source-Bereich und der Drain-Bereich begrenzen einen Kanalbereich zwischen sich. Die Gate-Struktur induziert eine Spannung in dem Kanalbereich.

Zellen-Layout für SRAM-FinFET-Transistoren

Es ist ein SRAM-Array und ein Verfahren zu Herstellung desselben offenbart. Jede der SRAM-Zellen umfasst zwei Pull-up-(PU)-, zwei Pass-Gate-(PG)- und zwei Pull-down-(PD)-FinFETs. Die PU-Transistoren liegen angrenzend an einander und umfassen einen aktiven Grat, der eine erste Gratbreite aufweist. Jeder der PG-Transistoren nutzt mindestens einen aktiven Grat gemeinsam mit einem PD-Transistor. Der mindestens eine aktive Grat, der von einem PG- und einem PD-Transistor gemeinsam genutzt wird, weist eine zweite Gratbreite auf, die kleiner als die erste Gratbreite ist. Das Verfahren umfasst das Strukturieren einer Mehrzahl von Graten, die aktive Grate und Hilfsgrate umfassen, und das Strukturieren und Entfernen mindestens eines Anteils der Hilfsgrate. Kein Hilfsgrat ist zwischen PU-FinFETs in einer Speicherzelle angeordnet. Ein Hilfsgrat ist zwischen einem PU-FinFET und dem mindestens einen aktiven Grat, der von einem PG- und einem PD-Transistor gemeinsam genutzt wird, angeordnet. Mindestens ...

Verfahren zur Herstellung von Doppelgate- und Trigate-Transistoren mit unabhängigem Zugriff in demselben Prozeßfluß sowie eine diese umfassende integrierte Schaltung

Verfahren, umfassend: Bilden von mindestens zwei Siliziumkörpern (15, 16) mit darüberliegenden Isolierelementen (17, 18); Bilden einer Opferschicht über den Siliziumkörpern mit darüberliegenden Isolierelementen; Strukturieren der Opferschicht, wobei Gatebereiche (20, 22) definiert werden, welche die Siliziumkörper (15, 16) kreuzen; Umgeben der strukturierten Opferschicht und der Siliziumkörper (15, 16) mit darüberliegenden Isolierelementen (17, 18) mit einer dielektrischen Schicht (30), so dass die Isolierelemente (17, 18) freigelegt werden, Bedecken eines der Isolierelemente (17) zum Schutz gegen Ätzen; Ätzen des anderen Isolierelements (18) während das eine Isolierelement (17) bedeckt ist; Entfernen der strukturierten Opferschicht, ohne die dieletrische Schicht (30) zu entfernen; Bilden einer Gate-Isolationsschicht (60) und Gate-Metallschicht (61) innerhalb der Gatebereiche.

Verfahren, Vorrichtung und System zum Reduzieren einer Gate-Schnitt-Aushöhlung und/oder eines Gate-Höhenverlusts in Halbleitervorrichtungen

Verfahren, umfassend ein Bereitstellen eines Halbleitersubstrats; einer auf dem Halbleitersubstrat angeordneten Finne; eines Dummy-Gates, das über der Finne angeordnet ist, wobei das Dummy-Gate eine Oberseite auf einer ersten Höhe über dem Substrat aufweist; und eines Zwischenschichtdielektrikums (ILD), das über der Finne und neben dem Dummy-Gate angeordnet ist, wobei die ILD eine Oberseite auf einer zweiten Höhe über dem Substrat aufweist, wobei die zweite Höhe unter der ersten Höhe liegt; und ein Abdecken der ILD mit einer dielektrischen Kappe, wobei die dielektrische Kappe eine Oberseite auf der ersten Höhe aufweist. Systeme, die zur Implementierung der Methoden konfiguriert sind. Halbleitervorrichtungen, die durch die Verfahren hergestellt werden.

Finfet structure and method to adjust threshold voltage in a finfet structure

Varying carrier mobility on finfet active surfaces to achieve overall design goals

A semiconductor device (100) may include a substrate (110) and an insulating layer (120) formed on the substrate (110). A first device (710) maybe formed on the insulating layer (120), including a first fin (130). The first fin (130) maybe formed on the insulating layer (120) and may have a first fin aspect ratio. A second device (720) may be formed on the insulating layer (120), including a second fin (130). The second fin (130) may be formed on the insulating layer (120) and may have a second fin aspect ratio different from the first fin aspect ratio.

Monolithic three-dimensional (3D) ICs with local inter-level interconnects

SEMICONDUCTOR COMPONENTS AND PROCEDURES FOR THE PRODUCTION

Integrated circuit with standard cell

Integrated circuit structure and methods of electrically connecting same

Semiconductor device

Comprises a source/drain electrode and the gate channel of semiconductor device

For SRAM circuit structure and method

METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURES INCLUDING STRUCTURES WITH BLADES HAVING DIFFERENT STRESS CONDITIONS, AND RELATED SEMICONDUCTOR STRUCTURES

Des procédés de formation d'une structure semi-conductrice incluent la fourniture d'un substrat multi-couches, ayant une couche de base épitaxiale recouvrant une couche semiconductrice primaire contrainte au-dessus d'une couche d'oxyde enterrée. Des éléments de la couche de base épitaxiale sont utilisés pour modifier un état de contrainte dans la couche semiconductrice primaire, à l'intérieur d'une première région du substrat multi-couches, sans modifier un état de contrainte de la couche semi-conductrice primaire, à l'intérieur d'une seconde région du substrat multi-couches. Une première pluralité de structures à canal de transistor est formée pour que chacune d'elles comprenne une partie de la couche semiconductrice primaire, à l'intérieur de la première région du substrat multi-couches, et une seconde pluralité de structures à canal de transistor est formée pour que chacune d'elles comprenne une partie de la couche semi-conductrice primaire à l'intérieur de la seconde région du substrat ...

FINFET STRUCTURE WITH NOVEL EDGE FINS

MONOLITHIC THREE-DIMENSIONAL(3D) ICS WITH LOCAL INTER-LEVEL INTERCONNECTS

반도체 장치 및 그 제조 방법

... 반도체 장치의 게이트 메탈 제조 방법이 제공된다. 반도체 장치의 게이트 메탈 제조 방법은 기판, 및 기판의 상면으로부터 돌출되고, 기판과 일체로 형성된 제1 및 제2 액티브 핀을 제공하고, 제1 및 제2 액티브 핀 상에 제1 일함수(work function)를 갖는 제1 게이트 메탈을 형성하고, 제1 액티브 핀 상의 제1 게이트 메탈은 노출하고, 상기 제2 액티브 핀 상의 제1 게이트 메탈은 덮는 제1 마스크막을 형성하고, 제1 불순물을 도핑하는 제1 등방성 도핑(isotropic doping)을 수행하여, 제1 액티브 핀 상의 제1 게이트 메탈을 제1 일함수와 다른 제2 일함수를 갖는 제2 게이트 메탈로 형성하는 것을 포함한다.

6T FINFET CMOS SRAM CELL WITH AN INCREASED CELL RATIO

The present invention is a CMOS SRAM cell comprising two access devices, each access device comprised of a tri- gate transistor (400) having a single fin (410); two pull-up devices, each pull-up device comprised of a tri-gate transistor (400) having a single fin (410); and two pull-down devices, each pull-down device comprised of a trigate transistor (500) having multiple fins (410). A method for manufacturing the CMOS SRAM cell, including the dual fin tri- gate transistor is also provided. Due to the fins, the gate length is increased with respect to a planar transistor having the same area. Therefore, the cell ratio and static noise margin are increased, providing improved stability without increasing the cell area on the supply voltage. © KIPO & WIPO 2009 ...

A CMOS FINFET DEVICE AND METHOD OF FORMING THE SAME

Field effect transistor for fully controlling electrical conductivity for a channel

STRUCTURE AND METHOD FOR FINFET DEVICE

The present disclosure provides an embodiment of a fin-like field-effect transistor (FinFET) device. The device includes a substrate having a first gate region, a first fin structure over the substrate in the first gate region. The first fin structure includes an upper semiconductor material member, a lower semiconductor material member surrounded by an oxide feature part, and a liner covering the circumference of the oxide feature part of the lower semiconductor material member, and upwardly extended to cover the circumference of a lower portion of the upper semiconductor material member. The device also includes a dielectric layer transversely proximate to an upper portion of the upper semiconductor material member. Therefore, the upper semiconductor material member includes an intermediate portion which is neither laterally proximate to the dielectric layer nor covered by the liner. COPYRIGHT KIPO 2016 (102) Provide a substrate having NEET and PEET (104) Form a first pin structure and ...

MULTI-TIME PROGRAMMABLE MEMORY

SEMICONDUCTOR DEVICE AND ITS FABRICATION METHOD

A semiconductor device exhibiting excellent device characteristics in which the V of an nMOS transistor and a pMOS transistor is controlled to a desired value. The semiconductor device has a pMOS transistor and an nMOS transistor formed by using an SOI substrate, characterized in that the pMOS transistor is a complete depletion type transistor having an n-type region, a first gate electrode, a first gate insulation film, and a source/drain region, the nMOS transistor is a complete depletion type transistor having a p-type region, a second gate electrode, a second gate insulation film, and a source/drain region, the first gate electrode has a silicide region (1) including an NiSi crystal phase containing n-type impurities touching the first gate insulation film, and the second gate electrode has a silicide region (2) including an NiSi crystal phase containing p-type impurities touching the second gate insulation film.th © KIPO & WIPO 2009 ...

Fabricating method of fin field effect transistor

A substrate is patterned to form trenches and a semiconductor fin between the trenches. Insulators are formed in the trenches and a first dielectric layer is formed to cover the semiconductor fin and the insulators. A dummy gate strip is formed on the first dielectric layer. Spacers are formed on sidewalls of the dummy gate strip. The dummy gate strip and the first dielectric layer underneath are removed until sidewalls of the spacers, a portion of the semiconductor fin and portions of the insulators are exposed. A second dielectric layer is selectively formed to cover the exposed portion of the semiconductor fin, wherein a thickness of the first dielectric layer is smaller than a thickness of the second dielectric layer. A gate is formed between the spacers to cover the second dielectric layer, the sidewalls of the spacers and the exposed portions of the insulators.

Source and drain doping using doped raised source and drain regions

A method comprises providing a semiconductor structure comprising a substrate, an electrically insulating layer on the substrate and a semiconductor feature on the electrically insulating layer. A gate structure is formed on the semiconductor feature. An in-situ doped semiconductor material is deposited on portions of the semiconductor feature adjacent the gate structure. Dopant is diffused from the in-situ doped semiconductor material into the portions of the semiconductor feature adjacent the gate structure, the diffusion of the dopant into the portions of the semiconductor feature adjacent the gate structure forming doped source and drain regions in the semiconductor feature.

Signal converters with multiple gate devices

An analog to digital converter (10) including a plurality of multiple independent gate field effect transistors (MIGFET) (14, 16, 18, 20) that provide a plurality of digital output signals, is provided. Each MIGFET (14) of the plurality of MIGFETs (14, 16, 18, 20) may have first gate (60) for receiving an analog signal, a second gate (62) for being biased, and a current electrode for providing a digital output signal from among the plurality of the digital output signals. Each MIGFET of the plurality of MIGFETs may have a combination of body width, channel length that is unique among the plurality of MIGFETs to result in a threshold voltage that is unique among the plurality of MIGFETs. A digital to analog converter including a plurality of MIGFETs is also provided.

Non-planar mos structure with a strained channel region

Highly conformal extension doping in advanced multi-gate devices

Semiconductor device

A semiconductor device with a novel structure in which stored data can be retained even when power is not supplied, and does not have a limitation on the number of write cycles. The semiconductor device includes a memory cell including a first transistor, a second transistor, and an insulating layer placed between a source region or a drain region of the first transistor and a channel formation region of the second transistor. The first transistor and the second transistor are provided to at least partly overlap with each other. The insulating layer and a gate insulating layer of the second transistor satisfy the following formula: (t a /t b )×(ε ra /ε rb )<0.1, where t a represents the thickness of the gate insulating layer, t b represents the thickness of the insulating layer, ε ra represents the dielectric constant of the gate insulating layer, and ε rb represents the dielectric constant of the insulating layer.

Sea-of-fins structure on a semiconductor substrate and method of fabrication

A semiconductor device and a method of fabricating a semiconductor device, wherein the method comprises forming, on a substrate, a plurality of planarized fin bodies to be used for customized fin field effect transistor (FinFET) device formation; forming a nitride spacer around each of the plurality of fin bodies; forming an isolation region in between each of the fin bodies; and coating the plurality of fin bodies, the nitride spacers, and the isolation regions with a protective film. The fabricated semiconductor device is used in customized applications as a customized semiconductor device.

Methods of forming memory cells, memory cells, and semiconductor devices

A memory device and method of making the memory device. Memory device may include a storage transistor at a surface of a substrate. The storage transistor comprises a body portion between first and second source/drain regions, wherein the source/drain regions are regions of a first conductivity type. The storage transistor also comprises a gate structure that wraps at least partially around the body portion in at least two spatial planes. A bit line is connected to the first source/drain region and a word line is connected to the gate structure.

High Voltage Semiconductor Devices

In one embodiment, the semiconductor device includes a first source of a first doping type disposed in a substrate. A first drain of the first doping type is disposed in the substrate. A first gate region is disposed between the first source and the first drain. A first channel region of a second doping type is disposed under the first gate region. The second doping type is opposite to the first doping type. A first extension region of the first doping type is disposed between the first gate and the first drain. The first extension region is part of a first fin disposed in or over the substrate. A first isolation region is disposed between the first extension region and the first drain. A first well region of the first doping type is disposed under the first isolation region. The first well region electrically couples the first extension region with the first drain.

Semiconductor Device Comprising Transistor Structures and Methods for Forming Same

A method for forming an opening within a semiconductor material comprises forming a neck portion, a rounded portion below the neck portion and, in some embodiments, a protruding portion below the rounded portion. This opening may be filled with a conductor, a dielectric, or both. Embodiments to form a transistor gate, shallow trench isolation, and an isolation material separating a transistor source and drain are disclosed. Device structures formed by the method are also described.

Non-volatile finfet memory array and manufacturing method thereof

An electronic device includes a substrate with a semiconducting surface having a plurality of fin-type projections coextending in a first direction through a memory cell region and select gate regions. The electronic device further includes a dielectric isolation material disposed in spaces between the projections. In the electronic device, the dielectric isolation material in the memory cell regions have a height less than a height of the projections in the memory cell regions, and the dielectric isolation material in the select gate regions have a height greater than or equal to than a height of the projections in the select gate regions. The electronic device further includes gate features disposed on the substrate within the memory cell region and the select gate regions over the projections and the dielectric isolation material, where the gate features coextend in a second direction transverse to the first direction.

Integrated circuit device with series-connected field effect transistors and integrated voltage equalization and method of forming the device

Disclosed is an integrated circuit device having series-connected planar or non-planar field effect transistors (FETs) with integrated voltage equalization and a method of forming the device. The series-connected FETs comprise gates positioned along a semiconductor body to define the channel regions for the series-connected FETs. Source/drain regions are located within the semiconductor body on opposing sides of the channel regions such that each portion of the semiconductor body between adjacent gates comprises one source/drain region for one field effect transistor abutting another source/drain region for another field effect transistor. Integrated voltage equalization is achieved through a conformal conductive layer having a desired resistance and positioned over the series-connected FETs such that it is electrically isolated from the gates, but in contact with the source/drain regions within the semiconductor body.

Transistor with reduced charge carrier mobility and associated methods

One or more embodiments relate to an apparatus comprising: a first transistor including a fin; and a second transistor including a fin, the fin of the first transistor having a lower charge carrier mobility than the fin of the second transistor.

Transistor with reduced charge carrier mobility and associated methods

One or more embodiments of the invention relate to a method comprising: treating a fin of a first n-channel access transistor in a static random access memory cell to have a lower charge carrier mobility than a fin of a first n-channel pull-down transistor in a first inverter in the memory cell, the first n-channel access transistor being coupled between a first bit line and a first node of the first inverter; and treating a fin of a second n-channel access transistor in the memory cell to have a lower charge carrier mobility than a fin of a second n-channel pull-down transistor in a second inverter in the memory cell, the second n-channel access transistor being coupled between a second bit line and a second node of the second inverter.

High density six transistor finfet sram cell layout

Dual orientation of finFET transistors in a static random access memory (SRAM) cell allows aggressive scaling to a minimum feature size of 15 nm and smaller using currently known masking techniques that provide good manufacturing yield. A preferred layout and embodiment features inverters formed from adjacent, parallel finFETs with a shared gate and different conductivity types developed through a double sidewall image transfer process while the preferred dimensions of the inverter finFETs and the pass transistors allow critical dimensions of all transistors to be sufficiently uniform despite the dual transistor orientation of the SRAM cell layout.

Spacer as hard mask scheme for in-situ doping in cmos finfets

A method of fabricating a semiconductor device that includes at least two fin structures, wherein one of the at least two fin structures include epitaxially formed in-situ doped second source and drain regions having a facetted exterior sidewall that are present on the sidewalls of the fin structure. In another embodiment, the disclosure also provides a method of fabricating a finFET that includes forming a recess in a sidewall of a fin structure, and epitaxially forming an extension dopant region in the recess that is formed in the fin structure. Structures formed by the aforementioned methods are also described.

Fin field-effect transistor and method for manufacturing the same

Embodiments of the present invention disclose a method for manufacturing a Fin Field-Effect Transistor. When a fin is formed, a dummy gate across the fin is formed on the fin, a spacer is formed on sidewalls of the dummy gate, and a cover layer is formed on the first dielectric layer and on the fin outside the dummy gate and the spacer, then, an self-aligned and elevated source/drain region is formed at both sides of the dummy gate by the spacer, wherein the upper surfaces of the gate and the source/drain region are in the same plane. The upper surfaces of the gate and the source/drain region are in the same plane, making alignment of the contact plug easier; and the gate and the source/drain region are separated by the spacer, thereby improving alignment accuracy, solving inaccurate alignment of the contact plug, and improving device AC performance.

Cmos with channel p-finfet and channel n-finfet having different crystalline orientations and parallel fins

An integrated circuit fabrication apparatus is configured to fabricate an integrated circuit with at least one p-FinFET device and at least one n-FinFET device. A bonding control processor is configured to bond a first silicon layer having a first crystalline orientation to a second silicon layer having a second crystalline orientation that is different from the first crystalline orientation. A material growth processor is configured to form a volume of material extending through the first silicon layer from the second layer up to the surface of first layer. The material has a crystalline orientation that substantially matches the crystalline orientation of second layer. An etching processor is configured to selectively etch areas of the surface of the first layer that are outside of the region to create a first plurality of fins and areas inside the region to create a second plurality of fins.

Integrated circuit device and method for manufacturing same

An integrated circuit device includes a plurality of fins on an upper surface of a semiconductor substrate and extending in a first direction, a device isolation insulating film placed between the fins, a gate electrode extending in a second direction crossing the first direction on the insulating film; and an insulating film insulating the fin from the gate electrode. In a first region where a plurality of the fins are consecutively arranged, an upper surface of the device isolation insulating film is located at a first position below an upper end of the fin. In a second region located in the second direction as viewed from the first region, the upper surface of the device isolation insulating film is located at a second position above the upper end of the fin. In the second region, the device isolation insulating film covers entirely a side surface of the fin.

Method to enable compressively strained pfet channel in a finfet structure by implant and thermal diffusion

A method of making a semiconductor device patterns a first fin in a pFET region, and patterns a second fin in an nFET region. A plurality of conformal microlayers containing a straining material are deposited on the first and second fins. A protective cap material is formed on the first fin, and the conformal layers are selectively removed from the second fin. The straining material is then thermally diffused into the first fin. The protective cap material is removed from the first fin after the thermal annealing and after the conformal micro layers are selectively removed from the second fin.

Semiconductor structure and process thereof

A semiconductor structure includes a substrate, a recess and a material. The recess is located in the substrate, wherein the recess has an upper part and a lower part. The minimum width of the upper part is larger than the maximum width of the lower part. The material is located in the recess.

DEVICES AND METHODS RELATED TO FIELD-EFFECT TRANSISTOR STRUCTURES FOR RADIO-FREQUENCY APPLICATIONS

Disclosed are devices and methods related to field-effect transistor (FET) structures configured to provide reduced per-area values of resistance in the linear operating region (Rds-on). Typical FET devices such as silicon-on-insulator (SOI) device require larger device sizes to desirably lower the Rds-on values. However, such increases in size result in undesirably larger die sizes. Disclosed are various examples of shapes of source, drain, and corresponding gate that yield reduced Rds-on values without having to increase the device size. In some implementations, such FET devices can be utilized in high power radio-frequency (RF) switching applications. 1. A transistor , comprising:a semiconductor substrate;a plurality of first diffusion regions formed on the semiconductor substrate;a plurality of second diffusion regions formed on the semiconductor substrate; anda gate layer disposed over the first and second diffusion regions, the gate layer defining a first opening over each of the first diffusion regions and a second opening over each of the second diffusion regions, at least some of the first and second openings having a shape other than a rectangle.2. The transistor of further comprising a contact feature formed on each the first and second diffusion regions.3. The transistor of further comprising a first conductor that electrically connects the contact features on the first diffusion regions claim 2 , and a second conductor that electrically connects the contact features on the second diffusion regions.4. The transistor of wherein the first conductor is further connected to a source terminal and the second conductor is further connected to a drain terminal.5. The transistor of wherein at least some of the first and second openings have a first shape defined by an outline of an elongate shape having a center and an elongation axis along a first direction and a diamond shape having its center positioned approximately at the center of the elongate shape claim 4 ...

Fin-type field effect transistor

A fin-type field effect transistor including at least one fin-type semiconductor structure, a gate strip and a gate insulating layer is provided. The fin-type semiconductor structure is doped with a first type dopant and has a block region with a first doping concentration and a channel region with a second doping concentration. The first doping concentration is larger than the second doping concentration. The blocking region has a height. The channel region is configured above the blocking region. The gate strip is substantially perpendicular to the fin-type semiconductor structure and covers above the channel region. The gate insulating layer is disposed between the gate strip and the fin-type semiconductor structure.

Method of Forming CMOS FinFET Device

A CMOS FinFET device and method for fabricating a CMOS FinFET device is disclosed. An exemplary CMOS FinFET device includes a substrate including a first region and a second region. The CMOS FinFET further includes a fin structure disposed over the substrate including a first fin in the first region and a second fin in the second region. The CMOS FinFET further includes a first portion of the first fin comprising a material that is the same material as the substrate and a second portion of the first fin comprising a III-V semiconductor material deposited over the first portion of the first fin. The CMOS FinFET further includes a first portion of the second fin comprising a material that is the same material as the substrate and a second portion of the second fin comprising a germanium (Ge) material deposited over the first portion of the second fin.

Semiconductor Arrangement with Active Drift Zone

A semiconductor device arrangement includes a first semiconductor device having a load path and a plurality of second semiconductor devices, each having a load path between a first and a second load terminal and a control terminal. The second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device. Each of the second semiconductor devices has its control terminal connected to the load terminal of one of the other second semiconductor devices, and one of the second semiconductor devices has its control terminal connected to one of the load terminals of the first semiconductor device. Each of the second semiconductor devices has at least one device characteristic. At least one device characteristic of at least one of the second semiconductor devices is different from the corresponding device characteristic of others of the second semiconductor devices.

SEMICONDUCTOR DEVICE, AND METHOD FOR PRODUCING SAME

Disclosed is a semiconductor device including a substrate a thin film diode A that is supported by the substrate and that includes a first semiconductor layer having a p-type region () and an n-type region (), a first wiring line RST disposed so as to overlap with the first semiconductor layer of the thin film diode A and connected to the p-type region (), a second wiring line RWS disposed so as to overlap with the first semiconductor layer of the thin film diode A and connected to the n-type region (), and a thin film transistor B that is supported by the substrate that includes a second semiconductor layer a gate electrode, a source electrode, and a drain electrode. The first wiring line RST and the second wiring line RWS are formed of the same conductive film as the gate electrode. 1. A semiconductor device , comprising:a substrate;a thin film diode supported by the substrate, the thin film diode including a first semiconductor layer that has a p-type region and an n-type region;a first wiring line disposed so as to overlap with the first semiconductor layer of the thin film diode, the first wiring line being connected to the p-type region;a second wiring line disposed so as to overlap with the first semiconductor layer of the thin film diode, the second wiring line being connected to the n-type region; anda thin film transistor supported by the substrate, the thin film transistor including a second semiconductor layer, a gate electrode, a source electrode, and a drain electrode,wherein the first wiring line and the second wiring line are formed of a same conductive film as the gate electrode.2. The semiconductor device according to claim 1 , wherein the first semiconductor layer and the second semiconductor layer are formed of a same semiconductor film.3. The semiconductor device according to claim 1 , wherein the gate electrode is formed above the second semiconductor layer.4. A method of manufacturing a semiconductor device claim 1 , comprising:(a) preparing a ...

Same-Chip Multicharacteristic Semiconductor Structures

In one exemplary embodiment, a semiconductor structure includes: a semiconductor-on-insulator substrate with a top semiconductor layer overlying an insulation layer and the insulation layer overlies a bottom substrate layer; at least one first device at least partially overlying and disposed upon a first portion of the top semiconductor layer, where the first portion has a first thickness, a first width and a first depth; and at least one second device at least partially overlying and disposed upon a second portion of the top semiconductor layer, where the second portion has a second thickness, a second width and a second depth, where at least one of the following holds: the first thickness is greater than the second thickness, the first width is greater than the second width and the first depth is greater than the second depth. 1. A semiconductor structure comprising:a semiconductor-on-insulator substrate comprised of a top semiconductor layer overlying an insulation layer, where the insulation layer overlies a bottom substrate layer;at least one first device at least partially overlying and disposed upon a first portion of the top semiconductor layer, where the first portion of the top semiconductor layer has a first thickness, a first width and a first depth; andat least one second device at least partially overlying and disposed upon a second portion of the top semiconductor layer, where the second portion of the top semiconductor layer has a second thickness, a second width and a second depth, where the first thickness and the second thickness are along a common first axis, where the first width and the second width are along a common second axis, where the first depth and the second depth are along a common third axis, where at least one of the following holds: the first thickness is greater than the second thickness, the first width is greater than the second width and the first depth is greater than the second depth.2. The semiconductor structure of claim 1 ...

CMOS FINFET DEVICE AND METHOD OF FORMING THE SAME

A CMOS FinFET device and method for fabricating a CMOS FinFET device is disclosed. An exemplary CMOS FinFET device includes a substrate including a first region and a second region. The CMOS FinFET further includes a fin structure disposed over the substrate including a first fin in the first region and a second fin in the second region. The CMOS FinFET further includes a first portion of the first fin comprising a material that is the same material as the substrate and a second portion of the first fin comprising a III-V semiconductor material deposited over the first portion of the first fin. The CMOS FinFET further includes a first portion of the second fin comprising a material that is the same material as the substrate and a second portion of the second fin comprising a germanium (Ge) material deposited over the first portion of the second fin. 1. A CMOS FinFET device comprising:a substrate including a first region and a second region;a fin structure disposed over the substrate including a first fin in the first region and a second fin in the second region;an insulation material disposed on the substrate and between the first and second fins;a first portion of the first fin comprising a material that is the same material as the substrate;a second portion of the first fin comprising a III-V semiconductor material deposited over the first portion of the first fin;a first portion of the second fin comprising a material that is the same material as the substrate;a second portion of the second fin comprising a germanium (Ge) material deposited over the first portion of the second fin; anda gate structure disposed on a central portion of the first fin including the semiconductor material separating source and drain regions of a N-type metal-oxide-semiconductor (NMOS) fin-like field effect transistor (FinFET) device of the CMOS FinFET device and disposed on a central portion of the second fin including the Ge material separating source and drain regions of a P-type ...

Passive devices for finfet integrated circuit technologies

Device structures, design structures, and fabrication methods for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A portion of a device layer of a semiconductor-on-insulator substrate is patterned to form a device region. A well of a first conductivity type is formed in the epitaxial layer and the device region. A doped region of a second conductivity type is formed in the well and defines a junction with a portion of the well. The epitaxial layer includes an exterior sidewall spaced from an exterior sidewall of the device region. Another portion of the device layer may be patterned to form fins for fin-type field-effect transistors.

Nonplanar device with thinned lower body portion and method of fabrication

A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

FinFET Design with Reduced Current Crowding

An integrated circuit structure includes an integrated circuit structure includes a substrate, insulation regions over the substrate, and a fin field-effect transistor (FinFET). The FinFET includes a plurality of fins over the substrate, wherein each of the plurality of fins comprises a first fin portion and a second fin portion, a gate stack on a top surface and sidewalls of the first fin portion of each of the plurality of fins, an epitaxial semiconductor layer comprising a portion directly over the second fin portion of each of the plurality of fins, and sidewall portions directly over the insulation regions, and a silicide layer on, and having an interface with, the epitaxial layer, wherein a peripheral ratio of a total length of an effective silicide peripheral of the FinFET to a total length of peripherals of the plurality of fins is greater than 1. 1. An integrated circuit structure comprising:a substrate;insulation regions over the substrate; and a plurality of fins over the substrate, wherein each of the plurality of fins comprises a first fin portion and a second fin portion;', 'a gate stack on a top surface and sidewalls of the first fin portion of each of the plurality of fins;', 'an epitaxial semiconductor layer comprising a portion directly over the second fin portion of each of the plurality of fins, and sidewall portions directly over the insulation regions; and', 'a silicide layer on, and having an interface with, the epitaxial layer, wherein a peripheral ratio of a total length of an effective silicide peripheral of the FinFET to a total length of peripherals of the plurality of fins is greater than 1., 'a fin field-effect transistor (FinFET) comprising2. The integrated circuit structure of claim 1 , wherein the peripheral ratio is greater than about 1.1.3. The integrated circuit structure of claim 1 , wherein the effective silicide peripheral comprises sidewall portions on outer sidewalls of the plurality of fins.4. The integrated circuit ...

Complementary metal-oxide-semiconductor (cmos) device and method

A complementary metal-oxide-semiconductor (CMOS) device and methods of formation thereof are disclosed. In a particular embodiment, a CMOS device includes a silicon substrate, a dielectric insulator material on the silicon substrate, and an extension layer on the dielectric insulator material. The CMOS device further includes a gate in contact with a channel and in contact with an extension region. The CMOS device also includes a source in contact with the extension region and a drain in contact with the extension region. The extension region includes a first region in contact with the source and the gate and includes a second region in contact with the drain and the gate.

Transistor With Reduced Charge Carrier Mobility And Associated Methods

One or more embodiments relate to an apparatus comprising: a first transistor including a channel in a fin; and a second transistor including a channel in a fin, the channel of the first transistor being doped with a first dopant of a first polarity and counter-doped with a second dopant of a second polarity opposite to the first polarity, a concentration of the first dopant being approximately equal to a concentration of the second dopant, wherein the first transistor and the second transistor are of a same conductivity type. 1. An apparatus comprising:a first transistor including a channel in a fin; anda second transistor including a channel in a fin, the channel of the first transistor being doped with a first dopant of a first polarity and counter-doped with a second dopant of a second polarity opposite to the first polarity, a concentration of the first dopant being approximately equal to a concentration of the second dopant, wherein the first transistor and the second transistor are of a same conductivity type.2. The apparatus of claim 1 , wherein a ratio of the first dopant to the second dopant in the channel of the first transistor is approximately 1:1.3. The apparatus of claim 1 , wherein:the first dopant is phosphorus (P) or arsenic (As) or antimony (Sb); andthe second dopant is boron (B).4. The apparatus of claim 1 , wherein:the first transistor includes a plurality of fins; andthe second transistor includes a plurality of fins, channels in the fins of the first transistor being doped with the first dopant and counter-doped with the second dopant, a ratio of the first dopant to the second dopant in the channels of the first transistor being approximately 1:1.5. The apparatus of claim 1 , wherein the channel of the second transistor is doped with the first dopant and counter-doped with the second dopant claim 1 , a ratio of the first dopant to the second dopant in the channel of the second transistor being greater than 10:1.6. The apparatus of claim 1 , ...

Adjusting configuration of a multiple gate transistor by controlling individual fins

In a sophisticated semiconductor device, FINFET elements may be provided with individually accessible semiconductor fins which may be connected to a controllable interconnect structure for appropriately adjusting the transistor configuration, for instance with respect to current drive capability, replacing defective semiconductor fins and the like. Consequently, different transistor configurations may be obtained on the basis of a standard transistor cell architecture, which may result in increased production yield of highly complex manufacturing strategies in forming non-planar transistor devices.

Mask free protection of work function material portions in wide replacement gate electrodes

In a replacement gate scheme, after formation of a gate dielectric layer, a work function material layer completely fills a narrow gate trench, while not filling a wide gate trench. A dielectric material layer is deposited and planarized over the work function material layer, and is subsequently recessed to form a dielectric material portion overlying a horizontal portion of the work function material layer within the wide gate trench. The work function material layer is recessed employing the dielectric material portion as a part of an etch mask to form work function material portions. A conductive material is deposited and planarized to form gate conductor portions, and a dielectric material is deposited and planarized to form gate cap dielectrics.

Fin isolation for multigate transistors

Multigate transistor devices and methods of their fabrication are disclosed. In one method, a substrate including a semiconductor upper layer and a lower layer beneath the upper layer is provided. The lower layer has a rate of transformation into a dielectric that is higher than a rate of transformation into a dielectric of the upper layer when the upper and lower layers are subjected to dielectric transformation conditions. Fins are formed in the upper layer, and the lower layer beneath the fins is transformed into a dielectric material to electrically isolate the fins. In addition, a gate structure is formed over the fins to complete the multigate transistor device.

High voltage three-dimensional devices having dielectric liners

High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric composed of a first dielectric layer disposed on the first fin active region, and a second, different, dielectric layer disposed on the first dielectric layer. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric composed of the second dielectric layer disposed on the second fin active region.

Forming Inter-Device STI Regions and Intra-Device STI Regions Using Different Dielectric Materials

An integrated circuit structure includes a substrate having a first portion in a first device region and a second portion in a second device region; and two insulation regions in the first device region and over the substrate. The two insulation regions include a first dielectric material having a first k value. A semiconductor strip is between and adjoining the two insulation regions, with a top portion of the semiconductor strip forming a semiconductor fin over top surfaces of the two insulation regions. An additional insulation region is in the second device region and over the substrate. The additional insulation region includes a second dielectric material having a second k value greater than the first k value.

Complementary Metal-Oxide-Semiconductor Device Comprising Silicon and Germanium and Method for Manufacturing Thereof

Disclosed are complementary metal-oxide-semiconductor (CMOS) devices and methods of manufacturing such CMOS devices. In some embodiments, an example CMOS device may include a substrate, and a buffer layer formed on the substrate, where the buffer layer comprises Si 1-x Ge x , where x is less than 0.5. The example CMOS device may further include one or more pMOS channel layer elements, where each pMOS channel layer element comprises Si 1-y Ge y , and where y is greater than x. The example CMOS device may still further include one or more nMOS channel layer elements, where each nMOS channel layer element comprises Si 1-z Ge z , and where z is less than x. In some embodiments, the example CMOS device may be a fin field-effect transistor (FinFET) CMOS device and may further include a first fin structure including the pMOS channel layer element(s) and a second fin structure including the nMOS channel layer element(s).

Nanowire FET and FINFET Hybrid Technology

Hybrid nanowire FET and FinFET devices and methods for fabrication thereof are provided. In one aspect, a method for fabricating a CMOS circuit having a nanowire FET and a finFET includes the following steps. A wafer is provided having an active layer over a BOX. A first region of the active layer is thinned. An organic planarizing layer is deposited on the active layer. Nanowires and pads are etched in the first region of the active layer using a first hardmask. The nanowires are suspended over the BOX. Fins are etched in the second region of the active layer using a second hardmask. A first gate stack is formed that surrounds at least a portion of each of the nanowires. A second gate stack is formed covering at least a portion of each of the fins. An epitaxial material is grown on exposed portions of the nanowires, pads and fins. 1. A CMOS circuit , comprising:a wafer having a BOX; nanowires and pads attached at opposite ends of the nanowires in a ladder-like configuration, wherein the nanowires are suspended over the BOX;', 'a first gate stack that surrounds at least a portion of each of the nanowires, wherein the portions of the nanowires surrounded by the first gate stack serve as a channel region of the nanowire FET;', 'an epitaxial material on portions of the nanowires and pads that serve as source and drain regions of the nanowire FET;, 'a nanowire FET on the BOX comprising a plurality of fins;', 'a second gate stack covering at least a portion of each of the fins, wherein the portions of the fins covered by the second gate stack serve as a channel region of the finFET; and', 'an epitaxial material on portions of the fins that serve as source and drain regions of the finFET., 'a finFET on the BOX comprising2. The CMOS circuit of claim 1 , further comprising spacers on opposite sides of the first gate stack and on opposite sides of the second gate stack.3. The CMOS circuit of claim 1 , further comprising a contact material on the epitaxial material. This ...

Cmos with channel p-finfet and channel n-finfet having different crystalline orientations and parallel fins

An integrated circuit includes at least one single-crystal fin having a first crystal orientation. The integrated circuit also includes at least one single-crystal fin having a second crystal orientation. The single-crystal fin having the first crystal orientation and the single-crystal fin having the second crystal orientation are substantially parallel.

JUNCTIONLESS SEMICONDUCTOR DEVICE HAVING BURIED GATE, APPARATUS INCLUDING THE SAME, AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE

A junctionless semiconductor device having a buried gate, a module and system each having the same, and a method for forming the semiconductor device are disclosed. A source, a drain, and a body of a semiconductor device having a buried gate are doped with the same type of impurities, so that the junctionless semiconductor device does not include a PN junction between the source and the body or between the body and the drain. As a result, a leakage current caused by GIDL is reduced so that operation characteristics of the semiconductor device are improved and the size of a current-flowing region is increased, resulting in an increased operation current. 1. A junctionless semiconductor device comprising:an active region disposed over an underlying substrate and defined by a device isolation film over the underlying substrate;an insulation layer disposed between the active region and the underlying substrate; anda plurality of buried gates formed in the device isolation film and the active region,wherein source and drain regions and a body in the active region around a buried gate are doped with the same-type impurities.2. The junctionless semiconductor device according to claim 1 , wherein the impurities are implanted into the active region with substantially uniform density.3. The junctionless semiconductor device according to claim 1 , wherein the active region is formed of a silicon layer claim 1 , and the impurities are N-type impurities.4. The junctionless semiconductor device according to claim 1 , wherein the active region is formed using any of a silicon germanium (SiGe) substrate claim 1 , a germanium (Ge) substrate claim 1 , and a group 3 compound semiconductor substrate or a group 5 compound semiconductor substrate claim 1 , and the impurities are P-type impurities.5. The junctionless semiconductor device according to claim 1 , wherein the active region is isolated from the underlying substrate by the insulation layer.6. The junctionless semiconductor ...

Reducing Resistance in Source and Drain Regions of FinFETs

A semiconductor structure includes a semiconductor fin on a top surface of a substrate, wherein the semiconductor fin includes a middle section having a first width; and a first and a second end section connected to opposite ends of the middle section, wherein the first and the second end sections each comprises at least a top portion having a second width greater than the first width. The semiconductor structure further includes a gate dielectric layer on a top surface and sidewalls of the middle section of the semiconductor fin; and a gate electrode on the gate dielectric layer.

SEMICONDUCTOR DEVICE

The semiconductor device includes a plurality of first flat plates containing a material that absorbs an electromagnetic wave at a high frequency. Any of the first flat plates is disposed above the first connecting wire, and any other of the first flat plates is disposed above the second connecting wire. 1. A semiconductor device , comprising:an insulating substrate;a first electrode disposed on the insulating substrate;a second electrode disposed on the insulating substrate;a third electrode disposed on the insulating substrate;a first switch element disposed on the first electrode and electrically connected to the first electrode at a first terminal thereof;a first connecting wire that electrically connects a second terminal of the first switch element to the third electrode;a second switch element disposed on the second electrode and electrically connected to the second electrode at a first terminal thereof;a second connecting wire that electrically connects a second terminal of the second switch element to the third electrode so that the second switch element is connected in parallel with the first switch element;a first gate wire electrically connected to a gate of the first switch element;a second gate wire electrically connected to a gate of the second switch element;a third connecting wire electrically connected to the first electrode and the second electrode;a fourth connecting wire electrically connected to the third electrode; anda plurality of first flat plates containing a material that absorbs an electromagnetic wave at a high frequency,wherein any of the first flat plates is disposed above the first connecting wire, and any other of the first flat plates is disposed above the second connecting wire.2. The semiconductor device according to claim 1 , wherein any of the first flat plates is disposed above the first electrode claim 1 , and any other of the first flat plates is disposed above the second electrode.3. The semiconductor device according to ...

FIELD-EFFECT-TRANSISTOR WITH SELF-ALIGNED DIFFUSION CONTACT

Embodiments of the present invention provide an array of fin-type transistors formed on top of an oxide layer. At least a first and a second of the fin-type transistors have their respective source and drain contacts being formed inside the oxide layer, with one of the contacts of the first fin-type transistor being conductively connected to one of the contacts of the second fin-type transistor by an epitaxial silicon layer, wherein the epitaxial silicon layer is formed on top of a first and a second fin of the first and second fin-type transistors respectively. 1. A semiconductor structure comprising:an array of fin-type transistors formed on top of an oxide layer, at least a first and a second of said fin-type transistors having their respective source and drain contacts formed inside said oxide layer, one of said contacts of said first fin-type transistor being conductively connected to one of said contacts of said second fin-type transistor by an epitaxial silicon layer, said epitaxial silicon layer being formed on top of a first and a second fin of said first and second fin-type transistors respectively.2. The semiconductor structure of claim 1 , wherein said contacts of said first and second fin-type transistors are self-aligned claim 1 , respectively claim 1 , to said first and second fins of said first and second fin-type transistors.3. The semiconductor structure of claim 1 , wherein said contacts of said first and second fin-type transistors are self-aligned claim 1 , respectively claim 1 , to a first and a second gate of said first and second fin-type transistors.4. The semiconductor structure of claim 1 , wherein said contacts have a silicide bottom surface claim 1 , said silicide bottom surface being coplanar with a bottom surface of said oxide layer.5. The semiconductor structure of claim 1 , further comprising a contact structure conductively connected to a gate of at least one of said array of fin-type transistors claim 1 , said contact structure ...

CELLS INCLUDING AT LEAST ONE FIN FIELD EFFECT TRANSISTOR AND SEMICONDUCTOR INTEGRATED CIRCUITS INCLUDING THE SAME

A semiconductor integrated circuit (IC) may comprise at least one cell comprising at least one fin field-effect transistor (FET). The at least one cell may comprise a plurality of fins that extend in a first direction and are arranged in parallel to each other in a second direction that is perpendicular to the first direction. A size of the at least one cell in the second direction may correspond to a number and a pitch of the plurality of fins. 1. A semiconductor integrated circuit (IC) , comprising:at least one cell comprising at least one fin field-effect transistor (FET);wherein the at least one cell comprises a plurality of fins that extend in a first direction and are arranged in parallel to each other in a second direction that is perpendicular to the first direction, andwherein a size of the at least one cell in the second direction corresponds to a number and a pitch of the plurality of fins.2. The semiconductor IC of claim 1 , wherein the plurality of fins comprises:a plurality of active fins; anda plurality of dummy fins.3. The semiconductor IC of claim 1 , wherein the plurality of fins comprises:a plurality of active fins adjacent to each other; anda plurality of dummy fins adjacent to each other.4. The semiconductor IC of claim 1 , wherein the at least one cell further comprises:a plurality of metal lines extending in the first direction and arranged in parallel to each other in the second direction.5. The semiconductor IC of claim 4 , wherein the plurality of metal lines comprises:two power lines arranged at both ends of the at least one cell in the second direction; anda plurality of wires disposed between the two power lines.6. The semiconductor IC of claim 5 , wherein the plurality of metal lines have a same width.7. The semiconductor IC of claim 5 , wherein the plurality of wires have a same width.8. The semiconductor IC of claim 5 , wherein a width of each of the two power lines is greater than a width of each of the plurality of wires.9. A ...

Single fin cut employing angled processing methods

Fin-defining spacers are formed on an array of mandrel structure. Mask material portions can be directionally deposited on fin-defining spacers located on one side of each mandrel structure, while not deposited on the other side. A photoresist layer is subsequently applied and patterned to form an opening, of which the overlay tolerance increases by a pitch of fin-defining spacers due to the mask material portions. Alternately, a conformal silicon oxide layer can be deposited on fin-defining spacers and structure-damaging ion implantation is performed only on fin-defining spacers located on one side of each mandrel structure. A photoresist layer is subsequently applied and patterned to form an opening, from which a damaged silicon oxide portion and an underlying fin-defining spacer are removed, while undamaged silicon oxide portions are not removed. An array of semiconductor fins including a vacancy can be formed by transferring the pattern into a semiconductor layer.

Semiconductor Arrangement with Active Drift Zone

A semiconductor device arrangement includes a semiconductor layer and at least one series circuit with a first semiconductor device and a plurality of n second semiconductor devices, with n>1. The first semiconductor device has a load path and active device regions integrated in the semiconductor layer. Each second semiconductor device has active device regions integrated in the semiconductor layer and a load path between a first and second load terminal and a control terminal. The second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device. Each second semiconductor device has its control terminal connected to the load terminal of one of the other second semiconductor devices. One of the second semiconductor devices has its control terminal connected to one of the load terminals of the first semiconductor device. The arrangement further includes an edge termination structure. 128-. (canceled)29. A semiconductor device arrangement , comprising:a semiconductor layer;at least one series circuit with a first semiconductor device and with a plurality of n second semiconductor devices where n>1, the first semiconductor device having a load path and having active device regions integrated in the semiconductor layer, each of the second semiconductor devices having active device regions integrated in the semiconductor layer and having a load path between a first and a second load terminal and a control terminal, the second semiconductor devices having their load paths connected in series and connected in series to the load path of the first semiconductor device, each of the second semiconductor devices having its control terminal connected to the load terminal of one of the other second semiconductor devices or to one of the load terminals of the first semiconductor device; andan edge termination structure,wherein the active device regions of the first semiconductor device and the active ...

SEMICONDUCTOR DEVICE HAVING A NECKED SEMICONDUCTOR BODY AND METHOD OF FORMING SEMICONDUCTOR BODIES OF VARYING WIDTH

Semiconductor devices having necked semiconductor bodies and methods of forming semiconductor bodies of varying width are described. For example, a semiconductor device includes a semiconductor body disposed above a substrate. A gate electrode stack is disposed over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack. Source and drain regions are defined in the semiconductor body on either side of the gate electrode stack. Sidewall spacers are disposed adjacent to the gate electrode stack and over only a portion of the source and drain regions. The portion of the source and drain regions under the sidewall spacers has a height and a width greater than a height and a width of the channel region of the semiconductor body. 1. An integrated circuit structure , comprising:a semiconductor body having a semiconductor channel, the semiconductor channel having a first side opposite a second side;a gate electrode over the semiconductor body, the gate electrode comprising a first gate electrode portion proximate the first side of the semiconductor channel, and the gate electrode comprising a second gate electrode portion proximate the second side of the semiconductor channel, the second gate electrode portion in alignment with the first gate electrode portion, wherein the semiconductor channel has a first width at a first location between the first gate electrode portion and the second gate electrode portion, and wherein the semiconductor channel has a second width at a second location between the first gate electrode portion and the second gate electrode portion, the second width different than the first width;a source or drain region adjacent to the semiconductor channel;a first sidewall spacer portion proximate a first portion of the source or drain region and proximate the first gate electrode portion;a second sidewall spacer portion proximate the first portion of the source or drain region and proximate ...

STACKED SHORT AND LONG CHANNEL FINFETS

An analog integrated circuit is disclosed in which short channel transistors are stacked on top of long channel transistors, vertically separated by an insulating layer. With such a design, it is possible to produce a high density, high power, and high performance analog integrated circuit chip including both short and long channel devices that are spaced far enough apart from one another to avoid crosstalk. In one embodiment, the transistors are FinFETs and the long channel devices are multi-gate FinFETs. In one embodiment, single and dual damascene devices are combined in a multi-layer integrated circuit cell. The cell may contain various combinations and configurations of the short and long-channel devices. A high density cell can be made by simply shrinking the dimensions of the cells and replicating two or more cells in the same size footprint as the original cell. 1. A method of fabricating an integrated circuit having finFET transistors therein , the method comprising:forming, overlying a silicon substrate, long channel epitaxial fin;forming an insulating layer overlying the long channel epitaxial fin;forming, overlying the insulating layer, short channel epitaxial fin;implanting source and drain regions while a gate region for the transistors is covered by a mask;etching recesses in the silicon substrate while the source and drain regions of the transistors are covered by a mask;depositing a gate dielectric layer over the epitaxial fins; anddepositing metal into the recesses to form a recessed metal gate for the long channel fin and a recessed metal gate for the short channel fin, the long and short channel transistors having portions that vertically overlap each other.2. The method of wherein the short channel epitaxial fins are substantially orthogonal to the long channel epitaxial fins.3. The method of wherein metal gates of short channel and the long channel devices are formed in a same layer.4. The method of wherein the silicon substrate includes a ...

INTEGRATED CIRCUIT STRUCTURE WITH METHODS OF ELECTRICALLY CONNECTING SAME

Embodiments of the present disclosure provide an integrated circuit (IC) structure and methods of electrically connecting multiple IC structures. An IC structure according to embodiments of the present disclosure can include: a first conductive region; a second conductive region laterally separated from the first conductive region; a first vertically-oriented semiconductor fin formed over and contacting the first conductive region; a second vertically-oriented semiconductor fin formed over and contacting the second conductive region; and a first gate contacting each of the first vertically-oriented semiconductor fin and the second conductive region, wherein the first gate includes: a substantially horizontal section contacting the first vertically-oriented semiconductor fin, and a substantially vertical section contacting the second conductive region. 1. An integrated circuit (IC) structure comprising:a first conductive region;a second conductive region laterally separated from the first conductive region;a first vertically-oriented semiconductor fin formed over and contacting the first conductive region;a second vertically-oriented semiconductor fin formed over and contacting the second conductive region; and a substantially horizontal section contacting the first vertically-oriented semiconductor fin, and', 'a substantially vertical section contacting the second conductive region., 'a first gate contacting each of the first vertically-oriented semiconductor fin and the second conductive region, wherein the first gate includes2. The IC structure of claim 1 , further comprising a second gate contacting each of the second vertically-oriented semiconductor fin and the first conductive region claim 1 , wherein the second gate includes:a substantially horizontal section contacting the second vertically-oriented semiconductor fin, anda substantially vertical section contacting the first conductive region.3. The IC structure of claim 2 , further comprising:a third ...

IMPLEMENTING A HYBRID FINFET DEVICE AND NANOWIRE DEVICE UTILIZING SELECTIVE SGOI

A silicon-on-insulator substrate which includes a semiconductor substrate, a buried oxide layer, and a semiconductor layer is provided. A hard mask layer is formed over a first region of the silicon-on-insulator substrate. A first silicon-germanium layer is epitaxially grown on the semiconductor layer within a second region of the silicon-on-insulator substrate. The second region is at least a portion of the semiconductor layer not covered by the hard mask layer. A thermal annealing process is performed, such that germanium atoms from the first silicon-germanium layer are migrated to the portion of the semiconductor layer to form a second silicon-germanium layer. The hard mask layer is removed. A layer of semiconductor material is epitaxially grown on top of the semiconductor layer and the second silicon-germanium layer, where the layer of semiconductor material composed of the same material as semiconductor layer. 1. A silicon-on-insulator substrate having selectively formed regions , the silicon-on-insulator substrate comprising:a first region having an epitaxially grown silicon layer formed on a buried oxide layer, without an intervening layer, the first region serving as an active silicon region for a formation of one or more finFET devices; anda second region having an epitaxially grown silicon layer formed on a silicon-germanium layer, wherein the silicon-germanium layer is formed on the buried oxide layer and is formed by thermally annealing a deposited silicon-germanium layer, the second region serving as a designated region for a formation of one or more nanowire devices.2. The silicon-on-insulator substrate of claim 1 , wherein thermally annealing the deposited silicon-germanium layer comprises performing a thermal anneal in an oxidizing environment.3. The silicon-on-insulator substrate of claim 2 , wherein the oxidizing environment comprises one or more of: oxygen claim 2 , nitrous oxide claim 2 , or water vapor.4. The silicon-on-insulator substrate of ...

FINFET DEVICES WITH MULTIPLE CHANNEL LENGTHS

A continuous fin having a first segment and a second segment in a semiconductor layer, the first segment is arranged at an angle relative to the second segment, and a first gate and a second gate substantially parallel to each other, the first gate substantially covering sides and a top of a portion of the first segment of the continuous fin, the second gate substantially covering sides and a top of a portion of the second segment of the continuous fin. 1. A structure comprising:a continuous fin having a first segment and a second segment in a semiconductor layer, the first segment is arranged at an angle relative to the second segment; anda first gate and a second gate substantially parallel to each other, the first gate substantially covering sides and a top of a portion of the first segment of the continuous fin, the second gate substantially covering sides and a top of a portion of the second segment of the continuous fin.2. The structure of claim 1 , wherein the continuous fin further comprises a third segment and a third gate substantially covering sides and a top of the third segment claim 1 , the third segment is parallel to the first segment and the third gate is substantially parallel to both the first gate and the second gate.3. The structure of claim 1 , wherein the first gate is substantially perpendicular to the first segment of the continuous fin.4. The structure of claim 1 , wherein an angle between the first segment and the second segment is greater than 90 degrees.5. The structure of claim 1 , wherein a width of the continuous fin is sublithographic in dimension.6. The structure of claim 1 , wherein a length of the portion of the second segment covered by the second gate is greater than a length of the portion of the first segment covered by the first gate claim 1 , the lengths being measured between opposite sides of the first and second gates.7. A structure comprising:a continuous fin having a first segment and a second segment in a semiconductor ...

SEMICONDUCTOR DEVICE AND RELATED MANUFACTURING METHOD

A semiconductor device may include a substrate, an n-channel field-effect transistor positioned on the substrate, and a p-channel field-effect transistor positioned on the substrate. The n-channel field-effect transistor may include an n-type silicide source portion, an n-type silicide drain portion, and a first n-type channel region. The first n-type channel region may be positioned between the n-type silicide source portion and the n-type silicide drain portion and may directly contact each of the n-type silicide source portion and the n-type silicide drain portion. 1. A method for manufacturing a semiconductor device , the method comprising:preparing a substrate;providing an n-channel field-effect transistor positioned on the substrate, wherein the n-channel field-effect transistor comprises an n-type silicide source portion, an n-type silicide drain portion, and a first n-type channel region, and wherein the first n-type channel region is positioned between the n-type silicide source portion and the n-type silicide drain portion and directly contacts each of the n-type silicide source portion and the n-type silicide drain portion; andproviding a p-channel field-effect transistor positioned on the substrate.2. The method of claim 1 , wherein the first n-type channel region is a first potion of a fin structure claim 1 , wherein the p-channel field-effect transistor comprises a second n-type channel region claim 1 , wherein the second n-type channel region is a second portion of the fin structure claim 1 , and wherein the fin structure is formed of or comprises at least one of germanium claim 1 , silicon-germanium claim 1 , and a III-V compound semiconductor material.3. The method of claim 2 , wherein a doping concentration value of the second n-type channel region is less than a doping concentration value of the first n-type channel region.4. The method of claim 1 , wherein a doping concentration value at a gate-channel interface of the first n-type channel region ...

STRAINED AND UNSTRAINED SEMICONDUCTOR DEVICE FEATURES FORMED ON THE SAME SUBSTRATE

Embodiments of the invention are directed to a configuration of semiconductor devices having a substrate and a first feature formed on the substrate, wherein the first feature includes a first preserve region having compressive strain that extends throughout the first preserve region, and wherein the first feature further includes a cut region comprising a dielectric. 1. A configuration of semiconductor devices comprising:a substrate; anda first feature formed on the substrate;wherein the first feature comprises a first preserve region having compressive strain that extends throughout the first preserve region;wherein the first feature further comprises a first cut region comprising a dielectric.2. The semiconductor devices of further comprising a second feature formed on the substrate.3. The semiconductor devices of claim 2 , wherein the second feature comprises a second preserve region having substantially no compressive strain.4. The semiconductor devices of claim 1 , wherein the first feature comprises a first fin.5. The semiconductor devices of claim 4 , wherein the first preserve region comprises a channel region of the first fin.6. The semiconductor devices of claim 5 , wherein the second feature comprises a second fin.7. The semiconductor devices of claim 6 , wherein the second preserve region comprises a channel region of the second fin.8. The semiconductor devices of further comprising a first gate formed over the channel region of the first fin.9. The semiconductor devices of further comprising a second gate formed over the channel region of the second fin.10. The semiconductor devices of claim 3 , wherein the substrate comprises silicon.11. The semiconductor devices of claim 10 , wherein the first preserve region comprises silicon germanium.12. The semiconductor devices of claim 11 , wherein the dielectric of the first cut region comprises an oxide.13. The semiconductor devices of claim 12 , wherein the second preserve region comprises silicon.14. A ...

FORMING FINS UTILIZING ALTERNATING PATTERN OF SPACERS

A method of forming a semiconductor structure includes forming a first pattern of alternating spacers of a first material and a second material on a semiconductor substrate, forming a second pattern of the alternating spacers of the first material and the second material by selectively removing at least a portion of at least one of one or more of the spacers of the first material and one or more of the spacers of the second material to form a remaining pattern of spacers of the first material and the second material on the semiconductor substrate, and transferring the second pattern of the spacers of the first material and the second material to the semiconductor substrate to form two or more fins in the semiconductor substrate by etching the semiconductor substrate selective to the first material and the second material. 1. A semiconductor structure , comprising:a substrate; andtwo or more fins formed in the substrate in a given pattern, each of the two or more fins having a pad layer formed on a top surface thereof and a spacer formed over a top of the pad layer;wherein the given pattern comprises alternating spacers of a first material and a second material with at least a portion of one of the spacers removed via a cut mask.2. The semiconductor structure of claim 1 , wherein a fin pitch between at least two of the fins is less than 30 nanometers.3. The semiconductor structure of claim 1 , wherein the first material comprises a nitride and the second material comprises an oxide.4. The semiconductor structure of claim 1 , wherein the substrate comprises one of bulk semiconductor and a semiconductor-on-insulator.5. The semiconductor structure of claim 1 , wherein the pad layer comprises silicon oxynitride.6. The semiconductor structure of claim 1 , wherein the pad layer comprises at least one of silicon carbide nitride claim 1 , silicon oxy carbide nitride and silicon boron carbide nitride.7. The semiconductor structure of claim 1 , wherein the first material ...

SEMICONDUCTOR CONTACT

A method for forming a semiconductor device comprises forming a gate stack on a channel region of a semiconductor, forming a source/drain region adjacent to the channel region, depositing a first insulator layer over the source/drain region, and removing a portion of the first insulator layer to form a first cavity that exposes a portion of the source/drain region. A first conductive material is deposited in the first cavity, and a conductive extension is formed from the first conductive material over the first insulator layer. A protective layer is deposited over the extension and a second insulator layer is deposited over the protective layer. A portion of the second insulator layer is removed to form a second cavity that exposes the protective layer, and an exposed portion of the protective layer is removed to expose a portion of the extension. A second conductive material is deposited in the second cavity. 1. A method for forming a semiconductor device , the method comprising:forming a gate stack on a channel region of a semiconductor, the gate stack including sidewalls extending from a gate stack upper surface to a gate stack base that contacts the channel region, and including gate spacers formed on the sidewalls;forming a source/drain region adjacent to the channel region;depositing a first insulator layer over the source/drain region;removing a portion of the first insulator layer to form a first cavity that exposes a portion of the source/drain region;depositing a first conductive material in the first cavity, the first conductive material including conductive sidewalls extending from a conductive base that contacts the source/drain region to a conductive upper surface, the conductive upper surface being flush with the gate stack upper surface;forming a conductive extension from the first conductive material over the first insulator layer and over the gate spacers;depositing a protective layer over the conductive extension and over the gate stack upper ...

INTEGRATED METAL GATE CMOS DEVICES

A semiconductor device comprises a first semiconductor fin arranged on a substrate, the first semiconductor fin having a first channel region, and a second semiconductor fin arranged on the substrate, the second semiconductor fin having a second channel region. A first gate stack is arranged on the first channel region. The first gate stack comprises a first metal layer arranged on the first channel region, a work function metal layer arranged on the first metal layer, and a work function metal arranged on the work function metal layer. A second gate stack is arranged on the second channel region, the second gate stack comprising a work function metal arranged on the second channel region. 1. A semiconductor device comprising:a first semiconductor fin arranged on a substrate, the first semiconductor fin having a first channel region;a second semiconductor fin arranged on the substrate, the second semiconductor fin having a second channel region; a first metal layer arranged on the first channel region;', 'a work function metal layer arranged on the first metal layer; and', 'another work function metal arranged on the work function metal layer; and, 'a first gate stack arranged on the first channel region, the first gate stack comprisinga second gate stack arranged on the second channel region, the second gate stack comprising a work function metal arranged on the second channel region.2. The device of claim 1 , wherein the first gate stack further comprises a sacrificial patterning layer arranged on the work function metal layer.3. The device of claim 1 , further comprising a third channel region.4. The device of claim 3 , further comprising a fourth channel region.5. The device of claim 4 , further comprising an interfacial layer on the first channel region claim 4 , the second channel region claim 4 , the third channel region claim 4 , and the fourth channel region.6. The device of claim 1 , wherein the substrate is doped.7. The device of claim 1 , wherein the ...

FIN-TYPE FIELD-EFFECT TRANSISTOR

This invention relates to a fin field-effect transistor semiconductor structure. The method of forming the semiconductor structure can include patterning a plurality of precursor fins on a semiconductor layer having a layer portion A and a layer portion B. The semiconductor layer can be located on a substrate. The layer portion B can be selectively etched to form B fins and a top half of precursor fins. The layer portion A can be selectively etched to form A fins and the substrate can be etched to form a bottom half of the decoupling fins. The precursor fins can be removed to expose the A fins, the decoupling fins, and the B fins. One of the A fins and the B fins can form n-type fins and the other can form p-type fins. 1. A method of forming a semiconductor structure , the method comprising:patterning a plurality of precursor fins on a semiconductor layer comprising a layer portion A and a layer portion B; wherein the layer portion A and the layer portion B have one or both of a different strain level and a different chemical composition; and wherein the semiconductor layer is located on a substrate;selectively etching into the layer portion B to concurrently form a plurality of B fins and a top half of a plurality of decoupling fins;selectively etching into the layer portion A and the substrate to concurrently form a plurality of A fins and a bottom half of the plurality of decoupling fins; andremoving the plurality of precursor fins to expose the plurality of A fins, the plurality of decoupling fins, and the plurality of B fins;wherein the plurality of A fins form a plurality of NFET fins and the plurality of B fins form a plurality of PFET fins; or wherein the plurality of A fins form the plurality of PFET fins and the plurality of B fins form the plurality of NFET fins.2. The method of claim 1 , wherein a height y of the plurality of decoupling fins is greater than one or both of a height x of the plurality of NFET fins and a height z of the plurality of PFET ...

SEMICONDUCTOR DEVICE AND FINFET TRANSISTOR

The present disclosure provides semiconductor devices, fin field-effect transistors and fabrication methods thereof. An exemplary fin field-effect transistor includes a semiconductor substrate; an insulation layer configured for inhibiting a short channel effect and increasing a heat dissipation efficiency of the fin field-effect transistor formed over the semiconductor substrate; at least one fin formed over the insulation layer; a gate structure crossing over at least one fin and covering top and side surfaces of the fin formed over the semiconductor substrate; and a source formed in the fin at one side of the gate structure and a drain formed in the fin at the other side of the gate structure. 114-. (canceled)15. A semiconductor device , comprising:a semiconductor substrate;a plurality of fins over the semiconductor substrate; andan insulation layer, including a first insulation layer and a second insulation layer,wherein the first insulation layer has a first portion under a lower portion of each fin and a second portion in the substrate between adjacent fins, andthe second insulation layer is on the first insulation layer between adjacent fins.16. The semiconductor device according to claim 15 , wherein:the insulation layer is made of nitrogen-doped silicon oxide.17. The semiconductor device according to claim 15 , wherein:a thickness of the insulation layer is in a range of approximately 2 Å-200 Å.18. A fin field-effect transistor claim 15 , comprising:a semiconductor substrate;a plurality of fins over the semiconductor substrate;an insulation layer, including a first insulation layer and a second insulation layer,wherein the first insulation layer has a first portion under a lower portion of each fin and a second portion in the substrate between adjacent fins, andthe second insulation layer is on the first insulation layer between adjacent fins;a gate structure crossing over at least one fin and covering top and side surfaces of the fin formed over the ...

Hybrid Fin Field-Effect Transistor Cell Structures and Related Methods

In one embodiment, an integrated circuit cell includes a first circuit component and a second circuit component. The first circuit component includes fin field-effect transistors (finFETs) formed in a high fin portion of the integrated circuit cell, the high fin portion of the integrated circuit including a plurality of fin structures arranged in rows. The second circuit component that includes finFETs formed in a less fin portion of the integrated circuit cell, the less fin portion of the integrated circuit including a lesser number of fin structures than the high fin portion of the integrated circuit cell. 1. An circuit cell , comprising:a first circuit component that includes fin field-effect transistors (finFETs) formed in a first fin portion of the circuit cell, the first fin portion of the circuit including a plurality of first fin structures arranged in a plurality of first rows; anda second circuit component that includes finFETs formed in a second fin portion of the circuit cell, the second fin portion of the circuit including a plurality of second fin structures arranged in a plurality of second rows, wherein each of the second rows, in the second fin portion, contain a lesser number of fin structures than each of the first rows, in the first fin portion of the circuit cell.2. The circuit cell of claim 1 , wherein the circuit cell is optimized for speed based on inclusion of the first circuit component in the first fin portion claim 1 , wherein the first fin portion is a high fin portion.3. The circuit cell of claim 1 , wherein the circuit cell is optimized for power consumption based on inclusion of the second circuit component in the second fin portion claim 1 , wherein the second fin portion is a less fin portion.4. The circuit cell of claim 1 , wherein the circuit cell is arranged in a double height cell layout with the first fin portion and the second fin portion being arranged in adjacent rows.5. The circuit cell of claim 1 , wherein the first ...

Hybrid Fin Field-Effect Transistor Cell Structures and Related Methods

In one embodiment, an integrated circuit cell includes a first circuit component and a second circuit component. The first circuit component includes fin field-effect transistors (finFETs) formed in a high fin portion of the integrated circuit cell, the high fin portion of the integrated circuit including a plurality of fin structures arranged in rows. The second circuit component that includes finFETs formed in a less fin portion of the integrated circuit cell, the less fin portion of the integrated circuit including a lesser number of fin structures than the high fin portion of the integrated circuit cell. 1. A method of fabricating an circuit cell , comprising:accessing a logic design for implementing a function of the circuit cell, the logic design including a plurality of logic components; a first circuit structure comprising a first circuit component that includes fin field-effect transistors (finFETs) formed in a first fin portion of the circuit cell, the first fin portion including a plurality of first fin structures arranged in first rows, and', 'a second circuit structure comprising a second circuit component that includes finFETs formed in a second fin portion of the circuit cell, the second fin portion of the circuit including a plurality of second fin structures arranged in a plurality of second rows, wherein each of the second rows, in the second fin portion, contain a lesser number of fin structures than each of the first rows, in the first fin portion of the circuit cell;, 'accessing a plurality of circuit structures for implementing one or more of the logic components, the plurality of circuit structures including,'}generating a plurality of circuit designs that use different combinations of the plurality of circuit structures that implement the function;filtering the generated circuit designs that do not meet a first circuit criterion; andselecting a remaining circuit design that has an optimum value for a second circuit criterion.2. The method of ...

Integrated circuit structure having gate contact and method of forming same

One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include: a gate stack having a gate conductor therein over a substrate, the gate stack being within a dielectric layer; a source/drain contact to a source/drain region over the substrate and adjacent to the gate stack within the dielectric layer; an upper conductor extending above, without contacting, the source/drain contact, wherein the upper conductor extends within the dielectric layer to contact the gate conductor within the gate stack.

PEDESTAL FIN STRUCTURE FOR STACKED TRANSISTOR INTEGRATION

Stacked transistor structures and methods of forming same. In an embodiment, a stacked transistor structure has a wide central pedestal region and at least one relatively narrower channel region above and/or below the wider central pedestal region. The upper and lower channel regions are configured with a non-planar architecture, and include one or more semiconductor fins, nanowires, and/or nanoribbons. The top and bottom channel regions may be configured the same or differently, with respect to shape and/or semiconductor materials. In some cases, an outermost sidewall of one or both the top and/or bottom channel region structures, is collinear with an outermost sidewall of the wider central pedestal region. In some such cases, the outermost sidewall of the top channel region structure is collinear with the outermost sidewall of the bottom channel region structure. Top and bottom transistor structures (NMOS/PMOS) may be formed using the top and bottom channel region structures. 1. An integrated circuit structure , comprising:a body comprising one or more semiconductor materials and having a first width defined by a distance between opposing sidewalls of the body;a first transistor above the body and including a first fin, nanowire, or nanoribbon, the first fin, nanowire, or nanoribbon having a second width defined by a distance between opposing sidewalls of the first fin, nanowire, or nanoribbon; anda second transistor below the body and including a second fin, nanowire, or nanoribbon, the second fin, nanowire, or nanoribbon having a third width defined by a distance between opposing sidewalls of the second fin, nanowire, or nanoribbon;wherein one or both of the second and third widths is at least 1.5 times less than the first width.2. The integrated circuit structure of claim 1 , wherein one or both of the second and third widths is at least 2 times less than the first width.3. The integrated circuit structure of claim 1 , wherein the body includes first and second ...

ENHANCED CHANNEL STRAIN TO REDUCE CONTACT RESISTANCE IN NMOS FET DEVICES

A semiconductor device includes a substrate, a fin structure and an isolation layer formed on the substrate and adjacent to the fin structure. The semiconductor device includes a gate structure formed on at least a portion of the fin structure and the isolation layer. The semiconductor device includes an epitaxial layer including a strained material that provides stress to a channel region of the fin structure. The epitaxial layer has a first region and a second region, in which the first region has a first doping concentration of a first doping agent and the second region has a second doping concentration of a second doping agent. The first doping concentration is greater than the second doping concentration. The epitaxial layer is doped by ion implantation using phosphorous dimer. 1. A method of fabricating a fin field-effect transistor (Fin FET) device , the method comprising:forming a first gate structure over a channel region in a first portion of a first fin structure on a semiconductor substrate;forming first source/drain regions on a second portion of the first fin structure on opposing sides of the gate structure;implanting a first dopant in a first region of the first source/drain regions, the first region having a first doping concentration of the first dopant, the first doping concentration being greater than a second doping concentration of a second dopant in a second region of the first source/drain regions; andapplying a thermal anneal operation to at least the first fin structure and the first source/drain regions, the channel region of the first fin structure having greater channel mobility than a channel region of a second fin structure on the substrate.2. The method of claim 1 , further comprising:forming a second gate structure over a channel region in a first portion of a second fin structure on the semiconductor substrate; andforming second source/drain regions on a second portion of the second fin structure on opposing sides of the second gate ...

Integrated Circuit Structure and Method with Hybrid Orientation for FinFET

The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first fin active region of a first semiconductor material disposed within the first region, oriented in a first direction, wherein the first fin active region has a <100> crystalline direction along the first direction; and a second fin active region of a second semiconductor material disposed within the second region and oriented in the first direction, wherein the second fin active region has a <110> crystalline direction along the first direction.

HYBRID FINFET STRUCTURE

A semiconductor device includes a first fin field effect transistor (FinFET) device, the first FinFET device including a plurality of fins formed in a substrate, an epitaxial layer of semiconductor material formed on the fins forming non-planar source/drain regions, and a first gate structure traversing across the plurality of fins. The semiconductor device includes a second FinFET device, the second FinFET device including a substantially planar fin formed in the substrate, an epitaxial layer of the semiconductor material formed on the substantially planar fin and forming substantially planar source/drain regions, and a second gate structure traversing across the substantially planar fin. 1. A semiconductor device comprising:a first fin field effect transistor (FinFET) device, the first FinFET device comprising a plurality of fins extending from a substrate, an epitaxial layer of semiconductor material formed on the fins forming non-planar source/drain regions, and a first gate structure traversing across the plurality of fins; anda second FinFET device, the second FinFET device comprising a substantially planar fin extending from the substrate, an epitaxial layer of the semiconductor material formed on the substantially planar fin and forming substantially planar source/drain regions, and a second gate structure traversing across the substantially planar fin.2. The semiconductor device of claim 1 , further comprising:a third gate structure traversing across the substantially planar fin and spaced from the second gate structure; anda contact, the contact landing on the epitaxial layer formed over the substantially planar fin between the second and third gate structures.3. The semiconductor device of claim 1 , wherein the substantially planar fin has a width in a direction parallel to the second gate structure that is at least 100 nm.4. The semiconductor device of claim 1 , wherein the epitaxial layer of semiconductor material includes silicon phosphorous (SiP).5. ...

Semiconductor structure and fabrication method thereof

A semiconductor structure and a method for fabricating the semiconductor structure are provided. The method includes forming a gate structure and a dielectric layer on a substrate; and forming a sidewall spacer on a sidewall surface of the gate structure. The method also includes forming a source and drain doped region in the substrate on both sides of the gate structure. The dielectric layer covers a surface of the sidewall spacer. In addition, the method includes forming a source-drain plug in the dielectric layer. The source-drain plug is connected to the source and drain doped region. Moreover, the method includes forming an isolation opening in the dielectric layer by at least partially removing the sidewall spacer. Further, the method includes forming an isolation structure in the isolation opening, wherein the isolation structure has a dielectric constant less than the sidewall spacer.

Memory device comprising an electrically floating body transistor and methods of operating

A semiconductor memory cell comprising an electrically floating body having two stable states is disclosed. A method of operating the memory cell is disclosed.

Semiconductor devices with sidewall spacers of equal thickness

Semiconductor structures with different devices each having spacers of equal thickness and methods of manufacture are disclosed. The method includes forming a first gate stack and a second gate stack. The method further includes forming sidewall spacers of equal thickness for both the first gate stack and the second gate stack by depositing a liner material over spacer material on sidewalls of the first gate stack and the second gate stack and within a space formed between the spacer material and source and drain regions of the first gate stack.

BRIDGING LOCAL SEMICONDUCTOR INTERCONNECTS

A semiconductor device includes a plurality of gates formed upon a semiconductor substrate that includes a plurality of outer active areas (e.g. CMOS/PMOS areas, source/drain regions, etc.) and one or more inner active areas. An isolator is formed upon one or more inner gates associated with the one or more inner active areas. A contact bar electrically connects the outer active areas and/or outer gates and is formed upon the isolator. The isolator electrically insulates the contact bar from the one or more inner active areas and/or the one or more inner gates. 1. A semiconductor device comprising:a plurality of transistor gates comprising one or more inner gates and a plurality of outer gates, the plurality of transistor gates at least directly upon a buried-dielectric layer of a semiconductor substrate, the semiconductor substrate comprising a plurality of outer active areas and one or more inner active areas, wherein the plurality of outer active areas are of opposite polarity relative to at least one inner active area;an isolator directly upon the one or more inner gates associated with the one or more inner active areas and offset from the plurality of outer active areas, the isolator comprising a protective barrier portion directly upon a dielectric layer, the dielectric layer directly upon the one or more inner gates; anda monolithic contact bar electrically connecting the plurality of outer active areas, the monolithic contact bar directly upon the protective barrier portion, wherein the isolator electrically insulates the monolithic contact bar from the one or more inner gates.2. The semiconductor device of claim 1 , wherein the isolator also insulates the monolithic contact bar from the one or more inner active areas.3. The semiconductor device of claim 1 , further comprising an interlayer dielectric claim 1 , wherein a top surface of the monolithic contact bar and a top surface of the interlayer dielectric are coplanar.4. The semiconductor device of claim ...

FinFET Having Isolation Structure and Method of Forming the Same

A transistor includes a substrate having an upper surface, a fin structure protruding from the upper surface of the substrate, an isolation structure over the upper surface of the substrate and surrounding a lower portion of the fin structure, and a first doped region at least partially embedded in an upper portion of the fin structure. The fin structure extends along a first direction. The first doped region has a first type doping different from that of the fin structure. 1. A method of making a transistor , comprising:forming a fin structure over a substrate, wherein the fin structure protrudes above upper surfaces of isolations structures on opposing sides of the fin structure, wherein the fin structure has a source region, a drain region, and a channel region, the channel region being disposed between the source region and the drain region;doping the source region and the drain region using a first type of doping;doping exterior portions of the channel region using a second type of doping different from the first type of doping, wherein the exterior portions comprise portions of the channel region along an upper surface of the fin structure in the channel region and portions of the channel region along sidewalls of the fin structure in the channel region;forming a gate structure over the channel region of the fin structure, wherein the source region and the drain region extend to opposing sides of the gate structure;forming a first doped region in the drain region, wherein the first doped region has the second type of doping; andforming a drain contact to the drain region, wherein the first doped region is disposed between the gate structure and the drain contact.2. The method of claim 1 , further comprising doping interior portions of the channel region of the fin structure using the first type of doping.3. The method of claim 1 , wherein the forming the first doped region comprises forming the first doped region using an ion implantation process.4. The method ...

FinFET CIRCUIT

A capacitor includes a semiconductor substrate. The capacitor also includes a first terminal having a fin disposed on a surface of the semiconductor substrate. The capacitor further includes a dielectric layer disposed onto the fin. The capacitor still further includes a second terminal having a FinFET compatible high-K metal gate disposed proximate and adjacent to the fin.

FINFET WITH CONSTRAINED SOURCE-DRAIN EPITAXIAL REGION

A method includes forming a plurality of fins on a substrate, a gate is formed over a first portion of the plurality of fins with a second portion of the plurality of fins remaining exposed. Spacers are formed on opposite sidewalls of the second portion of the plurality of fins. The second portion of the plurality fins is removed to form a trench between the spacers. An epitaxial layer is formed in the trench. The spacers on opposite sides of the epitaxial layer constrain lateral growth of the epitaxial layer. 1. A method comprising:forming a plurality of fins on a substrate;forming a gate over a first portion of the plurality of fins, a second portion of the plurality of fins remains exposed;forming spacers on opposite sidewalls of the second portion of the plurality of fins;removing the second portion of the plurality fins to form a trench between the spacers; andforming an epitaxial layer in the trench, wherein lateral growth of the epitaxial layer is constrained by the spacers.2. The method of claim 1 , wherein forming the epitaxial layer comprises:epitaxially growing an in-situ doped semiconductor material including silicon or silicon-germanium.3. The method of claim 1 , wherein the substrate comprises a bulk semiconductor substrate or a semiconductor-on-insulator (SOI) substrate.4. The method of claim 1 , wherein removing the second portion of the plurality of fins to form the trench between the spacers comprises:removing an upper region of the second portion of the plurality of fins while a lower region of the second portion of the plurality of fins remains in the trench,wherein the lower region of the second portion of the plurality of fins provides a seed for growing the epitaxial layer on SOI substrates.5. The method of claim 1 , further comprising:forming an extended epitaxial region directly on top of the epitaxial layer and above the trench.6. The method of claim 5 , wherein the extended epitaxial region comprises epitaxial growth on a {111} plane.7. ...

SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF

A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a third metal connect in contact with a first metal connect in a first active region and a second metal connect in a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes forming a first opening over the first metal connect, the STI region, and the second metal connect, and forming the third metal connect in the first opening. Forming the third metal connect over the first metal connect and the second metal connect mitigates RC coupling. 1. A semiconductor device , comprising:a first metal connect overlying a first active region;a second metal connect overlying a second active region;a gate overlying the first active region and the second active region; and a longest dimension of the gate extends in a first direction, and', 'a longest dimension of the third metal connect extends in the first direction., 'a third metal connect overlying the first metal connect and the second metal connect and electrically coupling the first metal connect to the second metal connect, wherein2. The semiconductor device of claim 1 , further comprising a first dielectric layer disposed between the first metal connect and the second metal connect and disposed between the first metal connect and the gate.3. The semiconductor device of claim 2 , further comprising a second dielectric layer overlying the first dielectric layer claim 2 , wherein the third metal connect is in contact with the second dielectric layer.4. The semiconductor device of claim 1 , wherein the first metal connect and the third metal connect overlie a first source/drain region of the first active region.5. The semiconductor device of claim 1 , further comprising:a metal contact in contact with the gate; anda first dielectric layer disposed between the metal contact and the ...

MERGED TAPERED FINFET

According to a structure herein, parallel fins comprise channel regions and source and drain regions. Parallel gate conductors are over and intersecting the channel regions of the fins. Electrical insulator material surrounds sides of the gate conductors. Each of the fins has a main fin body and wider regions extending from the main fin body between the electrical insulator material surrounding the sides of the gate conductors. The wider regions comprise a first wider region extending a first width from the main fin body and a second wider region extending a second width from the main fin body. The material of the second wider region is continuous between adjacent fins. 1. A structure comprising:parallel fins comprising channel regions and source and drain regions;parallel gate conductors over and intersecting said channel regions of said fins; and each of said fins having a main fin body and wider regions extending from said main fin body between said electrical insulator material surrounding said sides of said gate conductors,', a first wider region extending a first width from said main fin body; and', 'a second wider region extending a second width from said main fin body, and', 'material of said second wider region being continuous between adjacent fins., 'said wider regions comprising], 'electrical insulator material surrounding sides of said gate conductors,'}2. The structure according to claim 1 , said first wider region comprising a first material claim 1 , and said second wider region comprising a second material claim 1 ,said first material and said second material having different impurity qualities.3. The structure according to claim 2 , said first material and said second material comprising one of:silicon (Si),silicon-germanium (SiGe), and{'sub': x', '(1-x), 'silicon compounds (SiC).'}4. The structure according to claim 2 , further comprising:a dielectric material between said first material and said second material.5. The structure according to claim ...

TRAP LAYER SUBSTRATE STACKING TECHNIQUE TO IMPROVE PERFORMANCE FOR RF DEVICES

Some embodiments of the present disclosure are directed to a device. The device includes a substrate comprising a silicon layer disposed over an insulating layer. The substrate includes a transistor device region and a radio-frequency (RF) region. An interconnect structure is disposed over the substrate and includes a plurality of metal layers disposed within a dielectric structure. A handle substrate is disposed over an upper surface of the interconnect structure. A trapping layer separates the interconnect structure and the handle substrate. 1. A device , comprising:a substrate comprising a semiconductor layer disposed over an insulating layer, wherein the substrate includes a first region and a second region;an interconnect structure disposed over the substrate and including a plurality of metal layers disposed within a dielectric structure;a handle substrate disposed over an upper surface of the interconnect structure; anda trapping layer separating the interconnect structure and the handle substrate.2. The device of claim 1 , further comprising:a contact pad disposed in direct physical contact with a surface of the insulating layer of the substrate; anda through substrate via extending through the semiconductor layer and insulating layer and electrically coupling the contact pad to a metal layer of the interconnect structure.3. The device of claim 1 , wherein the handle substrate comprises a silicon substrate and the trapping layer comprises a polysilicon layer that meets the silicon substrate at a non-planar interface.4. The device of claim 3 , wherein the non-planar interface comprises a series of peaks extending downwardly from the silicon substrate into the trapping layer.5. The device of claim 4 , wherein a peak has a height ranging from approximately 10 nanometers (nm) to approximately 1 micron and has a width ranging from approximately 10 nm to approximately 10 microns.6. The device of claim 4 , wherein a peak is a flat-topped peak.7. The device of claim ...

Semiconductor devices having lower and upper fins and method for fabricating the same

Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes a lower fin that protrudes from a substrate and extends in a first direction, an oxide film the lower fin, an upper fin that protrudes from the oxide film and that is spaced apart from the lower fin at a position corresponding to the lower fin, and a gate structure the upper fin that extends in a second direction to intersect the upper fin, wherein germanium (Ge) is included in a portion of the oxide film located between the lower fin and the upper fin.

Semiconductor device and method of forming the semiconductor device

A semiconductor device includes: a substrate; an ion-implanted silicon layer disposed in the substrate; a first insulator layer disposed over the ion-implanted silicon layer; an active device disposed over the first insulator layer; and a conductive via configured to penetrate the first insulator layer for coupling the ion-implanted silicon layer and the active device.

Semiconductor integrated circuit device having a standard cell which includes a fin

Disclosed herein is a semiconductor integrated circuit device including a standard cell with a fin extending in a first direction. The fin and a gate line extending in a second direction perpendicular to the first direction and provided on the fin constitute an active transistor. The fin and a dummy gate line provided in parallel with the gate line constitute a dummy transistor. The active transistor shares a node as its source or drain with the dummy transistor.

SEMICONDUCTOR DEVICES WITH SIDEWALL SPACERS OF EQUAL THICKNESS

Semiconductor structures with different devices each having spacers of equal thickness and methods of manufacture are disclosed. The method includes forming a first gate stack and a second gate stack. The method further includes forming sidewall spacers of equal thickness for both the first gate stack and the second gate stack by depositing a liner material over spacer material on sidewalls of the first gate stack and the second gate stack and within a space formed between the spacer material and source and drain regions of the first gate stack. 1. A structure , comprising:a first gate structure and a second gate structure formed over a fin structure;raised source and drain regions formed adjacent to the first gate structure; andraised source and drain regions formed adjacent to the second gate structure,wherein side surfaces of the raised source and drain regions of the first gate structure contact a first liner material covering a portion of the first gate structure, which first liner material extends to an upper surface of the fin structure,wherein the side surfaces of the raised source and drain regions of the first gate structure are separated from a first spacer material formed on the first gate structure by the first liner material covering the portion of the first gate structure, andwherein side surfaces of the raised source and drain regions of the second gate structure contact a side surface of a second liner material covering a portion of the second gate structure and a side surface of a second spacer material formed on the second gate structure which is not covered by the second liner material.2. The structure of claim 1 , wherein the first gate structure is a gate structure of an N-type FET (NFET) and the second gate structure is a gate structure of a P-type FET (PFET).3. The structure of claim 2 , wherein:the first liner material and first spacer material formed on the first gate structure form a first sidewall spacer on a side surface of the first ...

Fin cut and fin trim isolation for advanced integrated circuit structure fabrication

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. A first isolation structure separates a first end of a first portion of the fin from a first end of a second portion of the fin, the first end of the first portion of the fin having a depth. A gate structure is over the top of and laterally adjacent to the sidewalls of a region of the first portion of the fin. A second isolation structure is over a second end of a first portion of the fin, the second end of the first portion of the fin having a depth different than the depth of the first end of the first portion of the fin.

Semiconductor device and fabricating method thereof

A semiconductor device is provided. A substrate includes a first region and a second region. A first wire pattern, extending in a first direction, is formed at a first height from the substrate of the first region. A second wire pattern, extending in a second direction, is formed at a second height from the substrate of the second region. The first height is different from the second height. A first gate electrode, surrounding the first wire pattern, extends in a third direction crossing the first direction. A second gate electrode, surrounding the second wire pattern, extends in a fourth direction crossing the second direction. A first gate insulation layer is formed along a circumference of the first wire pattern and a sidewall of the first gate electrode. A second gate insulation layer is formed along a circumference of the second wire pattern and a sidewall of the second gate electrode.

SILICON GERMANIUM AND SILICON FINS ON OXIDE FROM BULK WAFER

A method for forming fins includes growing a SiGe layer and a silicon layer over a surface of a bulk Si substrate, patterning fin structures from the silicon layer and the SiGe layer and filling between the fin structures with a dielectric fill. Trenches are formed to expose end portions of the fin structures. A first region of the fin structures is blocked off. The SiGe layer of the fin structures of a second region is removed by selectively etching the fin structures from the end portions to form voids, which are filled with dielectric material. The silicon layer of the fin structures is exposed. The SiGe layer in the first region is thermally oxidized to drive Ge into the silicon layer to form SiGe fins on an oxide layer in the first region and silicon fins on the dielectric material in the second region. 1. A method for forming fins for complementary metal oxide semiconductor (CMOS) devices , comprising:filling, with a dielectric fill, areas between fin structures formed on a substrate, the fin structures including a silicon layer formed on a SiGe layer;forming trenches through the dielectric fill, the fin structures and into the substrate, the trenches including a cut perpendicular to the fin structures to expose end portions of the fin structures;removing the SiGe layer of a first region of the fin structures by selectively etching the fin structures from the end portions of the fin structures to form voids;filling the voids with a first dielectric material;exposing the silicon layer of the fin structures in the first region and a second regions; andthermally oxidizing the SiGe layer in the second region, forming SiGe fins on a second dielectric material in the second region and silicon fins on the first dielectric material in the first region.2. The method as recited in claim 1 , wherein the second region is configured for P-type field effect transistors (PFETs) and the first region is configured for N-type field effect transistors (NFETs).3. The method as ...

SILICON-GERMANIUM FINFET DEVICE WITH CONTROLLED JUNCTION

Embodiments of the invention include a method for and the resulting structure. A semiconductor device including a substrate, a silicon-germanium fin formed on the substrate, a dummy gate formed on the fin, and a first set of spacers formed on the exposed sidewalls of the dummy gate is provided. Xenon is implanted into the exposed portions of the fin. A second set of spacers are formed on the exposed sidewalls of the first set of spacer. A dopant is implanted into the exposed portions of the fin. The semiconductor device is thermally annealed, such that the dopants diffuse into the adjacent portions of the fin. The dummy gate is replaced with a gate structure. 1. A method for forming a FinFET device , the method comprising: a substrate;', 'a fin formed on the substrate, wherein the fin comprises silicon-germanium;', 'a dummy gate formed on the fin;', 'a first set of spacers formed on exposed sidewalls of the dummy gate;, 'providing a semiconductor device, wherein the semiconductor device is an NFET device comprising;'}implanting xenon into exposed portions of the fin;forming a second set of spacers on exposed sidewalls of the first set of spacers;subsequent to forming the second set of spacers on the exposed sidewalls of the first set of spacers, implanting a dopant into exposed portions of the fin;forming a source/drain region on the fin laterally adjacent to each spacer of the second set of spacers;thermally annealing the semiconductor device, wherein thermally annealing the semiconductor device causes the dopant to diffuse into at least a first portion of the fin; andreplacing the dummy gate with a gate structure.2. The method of claim 1 , wherein the gate structure comprises a metal gate and a high-k gate dielectric layer.3. The method of claim 1 , wherein the first portion of the fin comprises at least a portion of the fin located beneath each spacer of the first set of spacers.4. The method of claim 1 , wherein the fin has a composition of at least ...

Semiconductor device and method of fabricating the same

A semiconductor device is provided. A fin is disposed on a substrate. The fin, including a first material and a second material, includes a first fin area and a second fin area. A gate structure is disposed on the first fin area. A source region is in contact with the second fin area. The first fin area includes the first material at a first concentration, the second fin area includes the first material at a second concentration which is greater than the first concentration.

Isolation components for transistors formed on fin features of semiconductor substrates

In an embodiment, an apparatus includes a substrate including a surface having a planar portion and a fin feature extending in a direction substantially perpendicular to the planar portion and having a thickness less than a thickness of the substrate. The apparatus also includes a first transistor that includes a first gate region formed over the fin feature, a first source region formed from a body of the fin feature, and a first drain region formed from the body of the fin feature. Additionally, the apparatus includes a second transistor that includes a second gate region formed over the fin feature, a second source region formed from the body of the fin feature, and a second drain region formed from the body of the fin feature. Further, the apparatus includes an isolation component formed between the first transistor and the second transistor, where the isolation component has a width less than 30 nm.

CMOS Anti-Fuse Cell

A CMOS anti-fuse cell is disclosed. In one aspect, an apparatus includes an N− well and an anti-fuse cell formed on the N− well. The anti-fuse cell includes a drain P+ diffusion deposited in the N− well, a source P+ diffusion deposited in the N− well, and an oxide layer deposited on the N− well and having an overlapping region that overlaps the drain P+ diffusion. A control gate is deposited on the oxide layer. A data bit of the anti-fuse cell is programmed when a voltage difference between the control gate and the drain P+ diffusion exceeds a voltage threshold of the oxide layer and forms a leakage path from the control gate to the drain P+ diffusion. The leakage path is confined to occur in the overlapping region. 1. A circuit able to perform an anti-fuse function , comprising:a first P+ diffusion layer deposited over an N− well substrate and configured to have a first lip extending underneath of a first portion of a first gate oxide;a second P+ diffusion layer deposited over the N− well substrate and configured to have a first lip extending underneath of a second portion of the first gate oxide and a second lip extending underneath of a first portion of a second gate oxide;a polysilicon select gate (“PSG”) situated over the first gate oxide and configured to receive a voltage; anda polysilicon control gate (“PCG”) situated over the second gate oxide and able to breakdown at least a part of the first portion of second gate oxide near the second lip of the second P+ diffusion layer when a high voltage is applied to the PCG.2. The circuit of claim 1 , wherein the high voltage has a voltage range from 3 volts to 7 volts.3. The circuit of claim 1 , wherein the PCG is able to create a short between the PCG and the first portion of second gate oxide when the second P+ diffusion layer has a low voltage.4. The circuit of claim 3 , wherein the low voltage has a voltage range from negative voltage to zero voltage.5. The circuit of claim 1 , wherein the second P+ diffusion ...

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

The present disclosure provides a semiconductor structure having a semiconductor layer; a gate with a conductive portion and a sidewall spacer; an interlayer dielectric (ILD) surrounding the sidewall spacer; and a nitrogen-containing protection layer, positioning at least on the top surface of the conductive portion of the gate. A top surface of the conductive portion and a top surface of the sidewall spacer are substantially coplanar. The nitrogen-containing protection layer is not covering the sidewall surface of the sidewall spacer. The present disclosure provides a method for manufacturing a semiconductor structure. The method includes forming a metal gate structure having a conductive portion and a sidewall spacer surrounded by a first ILD; forming a protection layer over the metal gate structure, and the protection layer is formed to cover at least the conductive portion of the metal gate structure; and forming a second ILD over the metal gate structure. 1. A semiconductor structure , comprising:a semiconductor layer;a gate comprising a conductive portion and a sidewall spacer, wherein a top surface of the conductive portion and a top surface of the side-wall spacer are substantially coplanar, and the gate is positioned over the semiconductor layer;an interlayer dielectric (ILD) surrounding a sidewall surface of the sidewall spacer, positioning over the semiconductor layer; anda protection layer, positioning on the top surface of the conductive portion and the top surface of the sidewall spacer, the protection layer comprising a tapered sidewall.2. The semiconductor structure in claim 1 , wherein the protection layer comprises at least one of sulfur nitride claim 1 , silicon nitride claim 1 , silicon oxynitride claim 1 , silicon carbonitride claim 1 , or combinations thereof.3. The semiconductor structure in claim 1 , wherein the protection layer is further extending to a top surface of the ILD.4. The semiconductor structure in claim 1 , further comprisinga ...

SEMICONDUCTOR STRUCTURES WITH DEEP TRENCH CAPACITOR AND METHODS OF MANUFACTURE

An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins. 1. A structure , comprising:a plurality of deep trench capacitors formed in a silicon on insulator (SOI) substrate, each of the plurality of deep trench capacitors having a fin structure;a plurality of SOI fins each of which having ends in contact with respective fin structures of the deep trench capacitors;an insulator material on the fin structures of the plurality of deep trench capacitors; anda gate structure extending over the insulator material and the SOI fins.2. The structure of claim 1 , further comprising an epitaxial material connecting the plurality of SOI fins with the respective fin structures of the deep trench capacitors.3. The structure of claim 1 , wherein the deep trench capacitors are eDRAM structures.4. The structure of claim 1 , wherein the SOI fins comprise portions of FinFETs.5. The structure of claim 1 , wherein the fin structures are polysilicon fins.6. The structure of wherein the polysilicon fins and the SOI fins are formed in contact with one another.7. The structure of claim 6 , wherein the insulator layer is oxide material blanket deposited on the polysilicon fins.8. The structure of claim 6 , further comprising an epitaxial material over a connection between the polysilicon fins and the SOI fins.9. The structure of claim 8 , wherein the connection is provided by material of the polysilicon fins and semiconductor material of the SOI fins.10. The structure of claim 9 , wherein the ...

STRUCTURES AND METHODS INTEGRATING DIFFERENT FIN DEVICE ARCHITECTURES

Semiconductor structures and fabrication methods are provided integrating different fin device architectures on a common wafer, for instance, within a common functional device area of the wafer. The method includes: facilitating fabricating multiple fin device architectures within a common functional device wafer area by: providing a wafer with at least one fin disposed over a substrate, the fin including an isolation layer; modifying the fin(s) in a first region of the fin(s), while protecting the fin in a second region of the fin(s); and proceeding with forming one or more fin devices of a first architectural type in the first region and one or more fin devices of a second architectural type in the second region. The first architectural type and the second architectural type are different fin device architectures, such as different fin device isolation architectures, different fin type transistor architectures, or different fin-type devices or structures. 1. A method comprising: providing a wafer with at least one fin disposed over a substrate, the at least one fin including an isolation layer;', 'modifying the at least one fin in a first fin region, while protecting the at least one fin in a second fin region thereof; and', 'proceeding with forming at least one fin device of a first architectural type in the first fin region and at least one fin device of a second architectural type in the second fin region, wherein the first architectural type and the second architectural type comprise different fin device architectures., 'facilitating fabricating multiple fin device architectures, the facilitating fabricating comprising2. The method of claim 1 , wherein the at least one fin device of the first architectural type comprises at least one fin transistor of the first architectural type.3. The method of claim 2 , wherein the at least one fin device of the second architectural type comprises at least one fin transistor of the second architectural type.4. The method of ...

Semiconductor devices with sidewall spacers of equal thickness

Semiconductor structures with different devices each having spacers of equal thickness and methods of manufacture are disclosed. The method includes forming a first gate stack and a second gate stack. The method further includes forming sidewall spacers of equal thickness for both the first gate stack and the second gate stack by depositing a liner material over spacer material on sidewalls of the first gate stack and the second gate stack and within a space formed between the spacer material and source and drain regions of the first gate stack.

Method and Structure for FinFET Device

The present disclosure provides a method, which includes forming a first fin structure and a second fin structure over a substrate, which has a first trench positioned between the first and second fin structures. The method also includes forming a first dielectric layer within the first trench, recessing the first dielectric layer to expose a portion of the first fin structure, forming a first capping layer over the exposed portion of the first fin structure and the recessed first dielectric layer in the first trench, forming a second dielectric layer over the first capping layer in the first trench while the first capping layer covers the exposed portion of the first fin feature and removing the first capping layer from the first fin structure. 1. A method , comprising:forming a first fin structure and a second fin structure over a substrate, wherein a first trench is position between the first and second fin structures;forming a first dielectric layer within the first trench;recessing the first dielectric layer to expose a portion of the first fin structure;forming a first capping layer over the exposed portion of the first fin structure and the recessed first dielectric layer in the first trench, wherein a portion of the first capping layer extends from the first fin structure to the second fin structure;forming a second dielectric layer over the first capping layer in the first trench while the first capping layer covers the exposed portion of the first fin structure and the portion of the first capping layer extends from the first fin structure to the second fin structure; andremoving the first capping layer from the first fin structure.2. The method of claim 1 , wherein forming the first fin structure and the second fin structure over the substrate claim 1 , includes:epitaxially growing a first semiconductor material layer over the substrate;epitaxially growing a second semiconductor material layer on top of the first semiconductor material layer;etching the ...

Integrated circuit, semiconductor device based on integrated circuit, and standard cell library

An integrated circuit (IC) may include at least one cell including a plurality of conductive lines that extend in a first direction and are in parallel to each other in a second direction that is perpendicular to the first direction, first contacts respectively disposed at two sides of at least one conductive line from among the plurality of conductive lines, and a second contact disposed on the at least one conductive line and the first contacts and forming a single node by being electrically connected to the at least one conductive line and the first contacts.

Densely spaced fins for semiconductor fin field effect transistors

A method of forming a fin-based field-effect transistor device includes forming one or more first fins comprising silicon on a substrate, forming epitaxial layers on sides of the one or more first fins, and removing the one or more first fins to form a plurality of second fins.

Method of Forming a FinFET Having an Oxide Region in the Source/Drain Region

Embodiments of the present disclosure include a semiconductor device, a FinFET device, and methods for forming the same. An embodiment is a semiconductor device including a first semiconductor fin extending above a substrate, the first semiconductor fin having a first lattice constant, an isolation region surrounding the first semiconductor fin, and a first source/drain region in the first semiconductor fin, the first source/drain having a second lattice constant different from the first lattice constant. The semiconductor device further includes a first oxide region along a bottom surface of the first source/drain region, the first oxide region extending into the isolation region.

FinFET DEVICE WITH ABRUPT JUNCTIONS

A plurality of semiconductor fins is formed on a surface of an insulator layer. Gate structures are then formed that are orientated perpendicular and straddle each semiconductor fin. A dielectric spacer is then formed on vertical sidewalls of each gate structure. Next, an etch is performed that removes exposed portions of each semiconductor fin and a portion of the insulator layer not protected by the dielectric spacers and the gate structures. The etch provides semiconductor fin portions that have exposed vertical sidewalls. A doped semiconductor material is then formed from each exposed vertical sidewall of each semiconductor fin portion, followed by an anneal which causes diffusion of dopants from the doped semiconductor material into each semiconductor fin portion and the formation of source/drain regions. The source/drain regions are present along the sidewalls of each semiconductor fin portion and are located beneath the dielectric spacers.

DESIGNABLE CHANNEL FINFET FUSE

On-chip, doped semiconductor fuse regions compatible with FinFET CMOS fabrication are formed from the channel regions of selected fins. One or more fin dimensions are optionally reduced in selected channel regions of the fins following dummy gate removal, such as height and/or width. The channel regions from which the fuse regions are formed are doped to provide electrical conductivity, amorphized using ion implantation, and then annealed to form substantially polycrystalline fuse regions. Source/drain regions function as terminals for the fuse regions. 1. A monolithic structure , comprising:a substrate including a plurality of parallel, monocrystalline semiconductor fins, the fins including one or more channel regions and outer fin portions integral with and adjoining the channel regions;source/drain regions on the outer fin portions of one or more of the fins, each of the channel regions being adjoined by a pair of the source/drain regions; anda gate structure adjoining each channel region;wherein the channel region of at least one of the parallel semiconductor fins includes a substantially polycrystalline, doped fuse region operatively associated with a pair of the source/drain regions.2. The monolithic structure of claim 1 , wherein the gate structure adjoining the channel region including the doped fuse region includes a dielectric layer adjoining the doped fuse region.3. The monolithic structure of claim 2 , further including spacers adjoining each of the gate structures claim 2 , the dielectric layer adjoining a pair of the spacers.4. The monolithic structure of claim 3 , wherein the source/drain regions include doped epitaxial structures extending from the fin portions and have the same doping type as the fuse region.5. The monolithic structure of claim 4 , wherein the fuse region has one or more dimensions smaller than corresponding dimensions of the fin portions.6. The monolithic structure of claim 5 , wherein the one or more dimensions includes width.7. ...

CMOS Anti-Fuse Cell

A CMOS anti-fuse cell is disclosed. In one aspect, an apparatus includes an N− well and an anti-fuse cell formed on the N− well. The anti-fuse cell includes a drain P+ diffusion deposited in the N− well, a source P+ diffusion deposited in the N− well, and an oxide layer deposited on the N− well and having an overlapping region that overlaps the drain P+ diffusion. A control gate is deposited on the oxide layer. A data bit of the anti-fuse cell is programmed when a voltage difference between the control gate and the drain P+ diffusion exceeds a voltage threshold of the oxide layer and forms a leakage path from the control gate to the drain P+ diffusion. The leakage path is confined to occur in the overlapping region. 1. An apparatus , comprising:a P-well; and an oxide layer deposited on the P-well;', 'a control gate deposited on the oxide layer; and', 'a drain N+ diffusion deposited in the P-well and below an overlapping region of the oxide layer, and wherein a bit of the anti-fuse cell is programmed when a voltage difference between the control gate and the drain N+ diffusion exceeds a voltage threshold of the oxide layer and forms a leakage path through the oxide layer that is confined to occur in the overlapping region., 'an anti-fuse cell formed on the P-well and comprising2. The apparatus of claim 1 , wherein the anti-fuse cell forms an NMOS transistor.3. The apparatus of claim 1 , wherein the voltage threshold of the oxide layer is approximately 4 volts.4. The apparatus of claim 1 , further comprising a second transistor that comprises:a second drain N+ diffusion deposited in the P-well;a second oxide layer deposited on the P-well and having end regions that overlap the second drain N+ diffusion and the drain N+ diffusion of the anti-fuse cell; anda select gate deposited on the second oxide layer.5. The apparatus of claim 4 , wherein the second drain N+ diffusion is connected to a bit line.6. The apparatus of claim 1 , further comprising a source N+ diffusion ...

BACKSIDE FIN RECESS CONTROL WITH MULTI-HSI OPTION

Embodiments of the present invention are directed to formation of fins with different active channel heights in a tri-gate or a Fin-FET device. In an embodiment, at least two fins are formed on a front side of the substrate. A gate structure extends over a top surface and a pair of sidewalls of at least a portion of the fins. In an embodiment, the substrate is thinned to expose the bottom surface of the fins. Next, backside etching may be performed on each fin to form active channel regions. The fins may be recessed to different depths, forming active channel regions with differing heights. 1. A semiconductor device , comprising: a first active channel region on a top portion of the first fin;', 'a first sub-channel region underneath the first active channel region; and', 'a first active channel height from a top surface of the first active channel region to a top surface of the first sub-channel region; and, 'a first fin comprising a second active channel region on a top portion of the second fin;', 'a second sub-channel region underneath the second active channel region of the second fin; and', 'a second active channel height from a top surface of the second active channel region to a top surface of the second sub-channel region,, 'a second fin comprisingwherein the first and second fins have a same height and the first active channel height is substantially different from the second active channel height.2. The semiconductor device of further comprises etch stop layers between the active channel regions and the sub-channel regions.3. The semiconductor of claim 2 , wherein the etch stop layers include epitaxial material.4. The semiconductor of claim 2 , wherein the etch stop layers include ion impurities.5. The semiconductor of claim 4 , wherein the ion impurities comprise a material selected from the group consisting of phosphorous (P) claim 4 , arsenic (As) claim 4 , antimony (Sb) claim 4 , and boron (B).6. The semiconductor device of claim 1 , wherein the first ...

Vertical fin field effect transistor with air gap spacers

A fin field effect transistor device with air gaps, including a source/drain layer on a substrate, one or more vertical fin(s) in contact with source/drain layer, a gate metal fill that forms a portion of a gate structure on each of the one or more vertical fin(s), and a bottom void space between the source/drain layer and the gate metal fill.

SHARED METAL GATE STACK WITH TUNABLE WORK FUNCTION

Semiconductor devices include at least one semiconductor fin in each of a first region and a second region. A first work function stack includes a bottom layer and a middle layer formed over the at least one semiconductor fin in the first region. A second work function stack includes a first layer and a second layer formed over the at least one semiconductor fin in the second region. The first layer is continuous with the bottom layer of the first work function stack and the second layer is continuous with the middle layer of the first work function stack, but has a smaller thickness than the middle layer. 1. A semiconductor device , comprising:at least one semiconductor fin in each of a first region and a second region;a first work function stack, comprising a bottom layer and a middle layer formed over the at least one semiconductor fin in the first region; anda second work function stack, comprising a first layer and a second layer, formed over the at least one semiconductor fin in the second region, the first layer being continuous with the bottom layer of the first work function stack and the second layer being continuous with the middle layer of the first work function stack but having a smaller thickness than the middle layer.2. The semiconductor device of claim 1 , further comprising a continuous gate dielectric layer between the first work function stack and the one or more semiconductor fins of the first region and between the second work function stack and the one or more semiconductor fins of the second region.3. The semiconductor device of claim 1 , further comprising a continuous gate formed over the first and the second work function stack.4. The semiconductor device of claim 1 , wherein the bottom layer and the first layer are formed from titanium nitride claim 1 , the middle layer and the second layer are formed from titanium aluminum carbide claim 1 , and the top layer is formed from titanium nitride.5. The semiconductor device of claim 1 , further ...

Semiconductor device

A semiconductor device includes a substrate having a first surface and a second surface opposite to each other, and having an active region located on the first surface and defined by a first isolation region; a plurality of active fins arranged on the active region, extending in a first direction, and defined by a second isolation region having a second depth smaller than a first depth of the first isolation region; a buried conductive wiring in a trench adjacent to the plurality of active fins, and extending in a direction of the trench; a filling insulation portion in the trench, and having the buried conductive wiring therein; an interlayer insulation layer on the first and second isolation regions and on the buried conductive wiring; a contact structure penetrating the interlayer insulation layer, and contacting the buried conductive wiring; and a conductive through structure extending through the substrate from the second surface to the trench, and contacting the buried conductive wiring.

SEMICONDUCTOR DEVICE

A semiconductor device includes a substrate that includes a first active region and a second active region, a device isolation layer between the first active region and the second active region, a gate structure that extends in a first direction and runs across the first active region and the second active region, a first active contact pattern on the first active region on one side of the gate structure, a second active contact pattern on the second active region on another side of the gate structure, and a connection pattern that is on the device isolation layer and connects the first active contact pattern and the second active contact pattern to each other. The connection pattern extends in a second direction and runs across the gate structure. Portions of the first active contact pattern and the second active contact pattern extend in the first direction and overlap the device isolation layer. 1. A semiconductor device , comprising:a substrate that includes a first active region and a second active region;a device isolation layer between the first active region and the second active region;a gate structure that extends in a first direction and runs across the first active region and the second active region;a first active contact pattern on the first active region on one side of the gate structure;a second active contact pattern on the second active region on another side of the gate structure; anda connection pattern that is on the device isolation layer and connects the first active contact pattern and the second active contact pattern to each other, the connection pattern extending in a second direction and running across the gate structure,wherein portions of the first active contact pattern and the second active contact pattern extend in the first direction and overlap the device isolation layer.2. The semiconductor device of claim 1 , wherein the connection pattern overlaps a portion of the first active contact pattern and a portion of the second active ...