Feldeffekttransistor mit isolierter Steuerelektrode

Planar power semiconductor with protective ring structure - has two concentric rings obtained by diffusion process with doping concentration increasing moving inwards from outside

The power semiconductor has the protective ring structure divided into two concentric zones (3, 4) enclosing the controlled pn junction (2) formed in the surface of the semiconductor chip (1), with the doping concentration gradually increasing from the outside inwards. Pref. the ring zones (3, 4) are provided by a diffusion process using a SiO2 mark, to provide a surface doping concentration of 10<17> cm<-3> and a penetration depth of 35 mu m, each zone incorporating further diffused zones (7, 8) of different doping concentration and penetration depth. ADVANTAGE - Improved voltage blocking characteristics without increased size.

HALBLEITERANORDNUNG MIT EINEM LEISTUNGSTRANSISTOR UND EINEM HOCHSPANNUNGSBAUELEMENT, DIE IN EINEM GEMEINSAMEN HALBLEITERKÖRPER INTEGRIERT SIND

Halbleiteranordnung, die aufweist: einen Halbleiterkörper (100); einen vertikalen Leistungstransistor, der ein Sourcegebiet (12), ein Draingebiet (11), ein Bodygebiet (13) und ein Driftgebiet (14), die in dem Halbleiterkörper (100) angeordnet sind, und eine Gateelektrode (15), die benachbart zu dem Bodygebiet (13) und durch ein Gatedielektrikum (16) dielektrisch von dem Bodygebiet (13) isoliert ist, aufweist; und ein laterales Hochspannungsbauelement, das innerhalb einer wannenartigen dielektrischen Struktur (50) in dem Halbleiterkörper (100) angeordnet ist und ein weiteres Driftgebiet (62) aufweist, wobei der Leistungstransistor als vertikaler Leistungstransistor ausgebildet ist, der weiterhin einen Randabschluss (40) aufweist, der im Bereich einer ersten Oberfläche (101) des Halbleiterkörpers (100) angeordnet ist, wobei der Randabschluss (40) einen Ring definiert und wobei wenigstens das Sourcegebiet (12) des Leistungstransistors innerhalb des Rings angeordnet ist.

High temperature change-fixed insertion diode e.g. trench junction barrier schottky diode, for use in motor vehicle-generator system, has isolating plastic layer overlapping radial inner-lying end area of another isolating plastic layer

The diode (1) has a semiconductor chip (3) fixed between a socket and a head wire (6) by an interconnection layer i.e. solder layer (5), and made from semiconductor material e.g. silicon carbide or gallium nitride. The layer is arranged on a chip front side relative to a chip outer edge, and a circulating, isolating plastic layer (10) is arranged above an interconnection layer-free area of the chip. Another completely circulating, isolating plastic layer (11) overlaps a radial inner-lying end area of the former plastic layer, where the latter plastic layer is made from polyimide.

Halbleiteranordnung für einen Stromsensor in einem Leistungshalbleiter

Die Erfindung betrifft eine Halbleiteranordnung für einen Stromsensor in einem Leistungshalbleiter, die auf einem Substrat (1) eine Mehrfachanordnung von Transistorzellen (2) mit isolierter Gate-Elektrode umfasst, deren Emitteranschlüsse (10) in einem ersten Bereich (12) über eine erste leitfähige Schicht (16) mit wenigstens einem Ausgangsanschluss (25) verbunden sind und deren Emitteranschlüsse (10) in einem zweiten Bereich (13) über eine zweite leitfähige Schicht (17) mit wenigstens einem Sensoranschluss (18) verbunden sind, der außerhalb einer ersten Zellengebietsgrenze (14) angeordnet ist, die die Transistorzellen (2) des ersten Bereichs (12) und die Transistorzellen (2) des zweiten Bereichs (13) umschließt, wobei zwischen den Transistorzellen (2) des zweiten Bereichs (13) und dem Sensoranschluss (18) eine zur ersten Zellengebietsgrenze (14) gehörende Grabenstruktur ausgebildet ist, an die sich in Richtung zu einem Außenrand des Substrats (1) ein mit der ersten leitfähigen Schicht ( ...

Schaltvorrichtung

Eine Schaltvorrichtung umfasst eine Elektronentransportschicht; eine Elektronenzufuhrschicht, die auf der Elektronentransportschicht bereitgestellt ist und in Kontakt mit der Elektronentransportschicht durch einen Heteroübergang ist; eine Sourceelektrode, die in Kontakt mit der Elektronenzufuhrschicht ist; eine Drainelektrode, die in Kontakt mit der Elektronenzufuhrschicht bei einer Position ist, die von der Sourceelektrode beabstandet ist; und eine erste Gateelektrode, die über der Elektronenzufuhrschicht bereitgestellt ist und zwischen der Sourceelektrode und der Drainelektrode bereitgestellt ist, wenn sie in einer Draufsicht von oben betrachtet werden. Die erste Gateelektrode ist elektrisch über der Elektronenzufuhrschicht mit der Drainelektrode verbunden. Ein Einschaltwiderstand bzw. Durchlasswiderstand der Schaltvorrichtung ist niedriger als ein elektrischer Widerstand zwischen der ersten Gateelektrode und der Drainelektrode.

IGBT mit dV/dt-Steuerbarkeit und Verfahren zum Verarbeiten eines IGBT

Ein IGBT (1), umfassend:- einen Halbleiterkörper (10), der an einen ersten Lastanschluss (11) und einen zweiten Lastanschluss (12) des IGBT (1) gekoppelt ist und ein Driftgebiet (100) umfasst, das konfiguriert ist zum Leiten eines Laststroms zwischen den Anschlüssen (11, 12), wobei das Driftgebiet (100) Dotierstoffe von einem ersten Leitfähigkeitstyp umfasst:- mindestens eine Leistungseinheitszelle (1-1), die Folgendes enthält- mindestens einen Steuergraben (14) mit einer Steuergrabenelektrode (141) und mindestens einem Dummy-Graben (15) mit einer Dummy-Grabenelektrode (151);- mindestens ein aktives Mesa (18), umfassend ein Sourcegebiet (101) mit Dotierstoffen vom ersten Leitfähigkeitstyp und elektrisch mit dem ersten Lastanschluss (11) verbunden, und ein Kanalgebiet (102) mit Dotierstoffen von einem zweiten Leitfähigkeitstyp und das Sourcegebiet (101) und das Driftgebiet (100) trennend, wobei in dem aktiven Mesa (18) mindestens eine jeweilige Sektion jedes Sourcegebiets (101), des Kanalgebiets ...

Halbleitervorrichtung

Eine Halbleitervorrichtung (100) weist ein Halbleitersubstrat (10), eine erste Anodenelektrode (1), und eine zweite Anodenelektrode (2) auf. Die erste Anodenelektrode (1) ist auf dem Halbleitersubstrat (10) angeordnet. Die zweite Anodenelektrode (2) ist von der ersten Anodenelektrode (1) auf dem Halbleitersubstrat (10) um die erste Anodenelektrode (1) herum beabstandet. Wenigstens ein erstes Ende (1E) der ersten Anodenelektrode (1) auf einer Seite der zweiten Anodenelektrode (2) oder ein zweites Ende (2E) der zweiten Anodenelektrode (2) auf einer Seite der ersten Anodenelektrode (1), ist mit einer SInSiN-Schicht (3) überdeckt.

Schaltvorrichtung zum Stromrichten und Stromrichtvorrichtung

Die vorliegende Erfindung schafft eine Schaltvorrichtung (100) zum Stromrichten, in der eine erste Gate-Elektrode (6), eine p-Kanalschicht (2) mit einem n-Emittergebiet (3), eine zweite Gate-Elektrode (13) und eine erdfreie p-Schicht (15) auf der Oberflächenseite eines n-Halbleitersubstrats (1) der Reihe nach wiederholt angeordnet sind. Ein Abstand a zwischen den zwei Gates (6, 13), zwischen denen die p-Kanalschicht (2) liegt, ist kleiner als ein Abstand b zwischen den zwei Gates (13, 6), zwischen denen die erdfreie p-Schicht (15) liegt, konfiguriert. Sowohl der ersten Gate-Elektrode (6) als auch der zweiten Gate-Elektrode (13) werden Ansteuersignale mit einer Zeitdifferenz des Ansteuerzeitpunkts zugeführt.

Planarer Randabschluss für hohe Spannungen unter Benutzung eines durchgriffshemmenden Implantates.

Halbleitervorrichtung und Verfahren zu ihrer Herstellung

Es wird eine Technik bereitgestellt, die die Latch-up-Festigkeit eines IGBT oder einer Halbleitervorrichtung, die ähnlich dem IGBT arbeitet, verbessert und eine Ein-Spannung verringert. Eine Halbleitervorrichtung (1A) enthält eine Driftschicht (3) eines ersten Leitfähigkeitstyps, eine Mesa-Region (5), die zwischen benachbarten Gräben (4) auf der Driftschicht (3) angeordnet ist, eine Gate-Elektrode (8), die in jedem Graben (4) durch einen Gate-Isolierfilm (6) vergraben ist, eine Basisregion (9) eines zweiten Leitfähigkeitstyps, die in der Mesa-Region (5) vergraben ist, mehrere Emitterregionen (11) des ersten Leitfähigkeitstyps, die periodisch in einem Oberflächenschichtabschnitt der Basisregion (9) entlang einer längeren Richtung des Grabens (4) vergraben sind, und Kontaktregionen (12) des zweiten Leitfähigkeitstyps, die abwechselnd in der längeren Richtung zusammen mit den Emitterregionen (11) dergestalt vergraben sind, dass jede Emitterregion (11) zwischen den Kontaktregionen (12) angeordnet ...

Halbleitervorrichtung

Halbleiterbauteil und Verfahren zu dessen Herstellung

Eine elektrische Feld-Pufferschicht (13) wird eine aktive Zone (12) umgebend ausgebildet. Die elektrische Feld-Pufferschicht (13) umfasst mehrere Fremdstoffschichten des P-Typs (21 bis 25). Jede der Fremdstoffschichten des P-Typs (21 bis 25) umfasst Implantationsschichten des P-Typs (21a bis 25a) und Diffusionsschichten des P-Typs (21b bis 25b), die so ausgebildet werden, dass sie jeweils die Implantationsschichten des P-Typs (21a bis 25a) umgeben und Fremdstoffe des P-Typs in einer Konzentration enthalten, die geringer ist als diejenige der Implantationsschichten des P-Typs (21a bis 25a). Eine erste Implantationsschicht des P-Typs (21a) wird in Kontakt mit der oder die aktive Zone (12) teilweise überlagernd ausgebildet. Jede der Diffusionsschichten des P-Typs (21b bis 25b) wird mit einer Ausdehnung in einem Ausmaß ausgebildet, in dem die erste Diffusionsschicht des P-Typs (21b) mit der zweiten Diffusionsschicht des P-Typs (22b) in Kontakt steht oder diese überlagert. Abstände (s2 bis s5 ...

Halbleitervorrichtung mit elektrostatischer Entladungsschutzstruktur

Eine Halbleiterkörper (10) umfasst einen Halbleiterkörper (100), der eine erste Oberfläche (101) und eine zweite Oberfläche (102) entgegengesetzt zu der ersten Oberfläche (101) hat. Die Halbleitervorrichtung (10) umfasst weiterhin eine erste Isolationsschicht (200) auf der ersten Oberfläche (101) des Halbleiterkörpers (100) und eine elektrostatische Entladungsschutzstruktur (310) auf der ersten Isolationsschicht (200). Die elektrostatische Entladungsschutzstruktur (310) umfasst einen ersten Anschluss (312) und einen zweiten Anschluss (314). Die Halbleitervorrichtung (10) umfasst weiterhin eine Wärmeabfuhrstruktur (700), die ein erstes Ende (701) in direktem Kontakt mit der elektrostatischen Entladungsschutzstruktur (310) und ein zweites Ende (702) in direktem Kontakt mit einem elektrisch isolierenden Bereich hat. Die elektrostatische Entladungsschutzstruktur (310) umfasst erste und zweite Ausdiffusionsbereiche (320, 322) des gleichen Leitfähigkeitstyps, die zu der Wärmeabfuhrstruktur (700 ...

Trenched-Gate-Feldeffekttransistoren und Verfahren zum Bilden derselben

Struktur mit einem Trench-Feldeffekttransistor (FET) und einer Schottky-Diode, die monolithisch integriert sind, wobei die Struktur ferner umfasst:einen Gate-Graben (1106, 1206, 1306, 1406, 1506, 1606), der sich in einen Halbleiterbereich erstreckt;eine Gate-Elektrode (1110, 1210, 1310, 1410, 1510), die in dem Gate-Graben (1106, 1206, 1306, 1406, 1506, 1606) angeordnet ist;ein Dielektrikummaterial (1108, 1208, 1308, 1408, 1508, 1608), das über der Gate-Elektrode (1110, 1210, 1310, 1410, 1510) angeordnet ist;einen Halbleiter-Source-Spacer (1114, 1214, 1314, 1415, 1517, 1615), der derart an einer Seite des Gate-Grabens (1106, 1206, 1306, 1406, 1506, 1606) angeordnet ist, dass der Halbleiter-Source-Spacer (1114, 1214, 1314, 1415, 1517, 1615) zumindest einen Abschnitt einer Kontaktöffnung definiert, wobei der Halbleiter-Source-Spacer (1114, 1214, 1314, 1415, 1517, 1615) Polysilizium enthält; undeine Leiterschicht (1120, 1220, 1320, 1421, 1621), die in der Kontaktöffnung angeordnet ist und den ...

Halbleitervorrichtung

IGBT mit:einem Halbleitersubstrat mit einer ersten Hauptoberfläche und einer zweiten Hauptoberfläche, die einander gegenüberliegen; undeinem Element mit einer Gateelektrode (5a), die auf einer Seite der ersten Hauptoberfläche ausgebildet ist, einer ersten Elektrode (11), die auf der Seite der ersten Hauptoberfläche ausgebildet ist, und einer zweiten Elektrode (12), die in Kontakt mit der zweiten Hauptoberfläche ausgebildet ist, und einer Kollektorregion, die auf der zweiten Hauptoberfläche ausgebildet ist, wobei die Kollektorregion eine Kollektordiffusionsschicht (8) eines ersten Leitungstyps in Kontakt zu der zweiten Elektrode (12) beinhaltet sowie eine Pufferdiffusionsschicht (7) eines zweiten Leitungstyps, die näher zu der ersten Hauptoberfläche hin ausgebildet ist als die Kollektordiffusionsschicht, wobeidie Kollektorregion weiterhin eine Driftdiffusionsschicht (1) des zweiten Leitungstyps aufweist und die Driftdiffusionsschicht niedriger in der Verunreinigungskonzentration ist als ...

Halbleitervorrichtung

Diese Halbleitervorrichtung (100) verfügt über ein auf einem n-Driftgebiet (2) angeordnetes p-Anodengebiet (4) und ein p-Diffusionsgebiet (5), welches so angeordnet ist, dass es mit dem p-Anodengebiet (4) auf dem n-Driftgebiet (2) in Kontakt steht. Ein Widerstandsgebiet (6), das so angeordnet ist, dass es mit dem p-Diffusionsgebiet (5) auf einem n-Gebiet (3) in Kontakt steht, eine Vielzahl von p-Schutzringgebieten (8) und ein entfernt von den p-Schutzringgebieten (8) angeordnetes Stoppergebiet (9) sind vorgesehen. Durch Vorsehen des p-Diffusionsgebiets (5) wird das Abziehen von Löchern, welche sich zur Zeit der Sperrverzögerung im p-Anodengebiet konzentrieren, unterdrückt, so dass die Halbleitervorrichtung mit einer hohen Sperrverzögerungstoleranz bereitgestellt werden kann.

Halbleiteranordnung

Ein Planar-MOSFET (5) ist an der Oberseite des N–-Halbleitersubstrats (1) in einem Mesa-Abschnitt zwischen den Gräben (2) vorhanden. Eine P+-Emitterschicht (6) ist zwischen dem Graben (2) und dem Planar-MOSFET (5) in dem Mesa-Abschnitt vorhanden. Eine P-Kollektorschicht (8) ist an einer Unterseite des N–-Halbleitersubstrats (1) vorhanden. Der Planar-MOSFET (5) umfasst eine N+-Emitterschicht (10), einen oberen Abschnitt des N–-Halbleitersubstrats (1), eine P-Basisschicht (12) und ein Planar-Gate (14) an dem vorhergehenden, mit einer Gate-Isolationsschicht (13) dazwischen angeordnet. Das Planar-Gate (14) ist mit dem Gate-Graben (4) verbunden. Die P+-Emitterschicht (6) hat eine höhere Störstellenkonzentration als die P-Basisschicht (12) und hat ein elektrisches Potenzial gleich einem Emitterpotenzial der N+-Emitterschicht (10). Die N+-Emitterschicht (10) ist nicht in Kontakt mit dem Graben (2). Ein Trench-MOSFET ist nicht ausgebildet.

Siliziumkarbid-Halbleitervorrichtung

Es wird eine Siliziumkarbid-Halbleitervorrichtung offenbart. Die Siliziumkarbid-Halbleitervorrichtung weist ein Substrat, eine Driftschicht, die einen ersten Leitfähigkeitstyp aufweist und sich auf einer ersten Oberfläche des Substrats befindet, und ein Halbleiterelement eines vertikalen Typs auf. Das Halbleiterelement des vertikalen Typs weist eine Störstellenschicht, die einen zweiten Leitfähigkeitstyp aufweist und sich in einem Oberflächenabschnitt der Driftschicht befindet, und einen Bereich eines ersten Leitfähigkeitstyps auf, der sich in der Driftschicht befindet, von der Störstellenschicht entfernt ist, näher als die Störstellenschicht an dem Substrat angeordnet ist und eine Störstellenkonzentration aufweist, die höher als die der Driftschicht ist.

VIERSCHICHTTRIODE

Reverse blocking semiconductor device, has spacing between emitter electrode and isolating region greater than thickness of drift layer in depth direction

The semiconductor device has a MOS control electrode structure. The spacing (W) between an outermost point of part of an emitter electrode (8) that is in contact with the base layer (4), and an innermost point of a isolating region (11) is greater than the thickness (d) in the depth direction of a drift layer (3). An independent claim is included for a method of manufacturing a reverse-blocking semiconductor device.

Nitridhalbleitervorrichtung und deren Herstellungsverfahren

Nitridhalbleitervorrichtung, die einen IIIV Nitridhalbleiter umfasst, der aus zumindest einem Element der Gruppe III aus einer Gallium, Aluminium, Bor und Indium enthaltenden Gruppe und zumindest Stickstoff als Element der Gruppe V aus einer Stickstoff, Phosphor und Arsen enthaltenden Gruppe zusammengesetzt ist, die Nitridhalbleitervorrichtung umfasst dabei: eine erste Nitridhalbleiterschicht, die den auf einem Substrat abgeschiedenen IIIV Nitridhalbleiter aufweist, wobei die erste Nitridhalbleiterschicht als Ladungszufuhrschicht eingerichtet ist; eine zweite Nitridhalbleiterschicht, die den IIIV Nitridhalbleiter aufweist, der auf der ersten Nitridhalbleiterschicht abgeschieden ist und kein Aluminium enthält; und eine Steuerelektrode, die einen Schottky-Kontakt mit der zweiten Nitridhalbleiterschicht ausbildet, wobei die erste Nitridhalbleiterschicht eine Epitaxieschicht ist, und die zweite Nitridhalbleiterschicht eine Schicht mit einer Kristallinität mit winzigen Körnern ist, die durch ...

HALBLEITERANORDNUNG MIT EINEM GLEICHRICHTENDEN METALL-HALBLEITER- UEBERGANG

Halbleiterleistungsschalter mit verbesserter Steuerbarkeit

Leistungshalbleiterschalter (1), der einen ersten Lastanschluss (11) und einen zweiten Lastanschluss (12) umfasst, wobei der Halbleiterschalter (1) dazu konfiguriert ist, einen Laststrom entlang einer vertikalen Richtung (Z) zwischen den Anschlüssen (11, 12) zu leiten, und Folgendes umfasst:- ein aktives Zellengebiet (1-2) mit einem Driftgebiet (100) eines ersten Leitfähigkeitstyps;- ein Randabschlussgebiet (1-3) mit einem Wannengebiet (109) eines zweiten Leitfähigkeitstyps, das elektrisch mit dem ersten Lastanschluss (11) verbunden ist;- mehrere IGBT-Zellen (1-1), die innerhalb des aktiven Zellengebiets (1-2) angeordnet sind, wobei jede der IGBT-Zellen (1-1) mehrere Gräben (14, 15, 16) umfasst, die sich entlang der vertikalen Richtung (Z) in das Driftgebiet (100) erstrecken und die mehrere Mesas (18, 19) lateral begrenzen; wobei die mehreren Gräben Folgendes beinhalten:- wenigstens einen Steuergraben (14) mit einer Steuerelektrode (141) zum Steuern des Laststroms;- wenigstens einen Dummy-Graben ...

Halbleiteranordnung

Es wird eine Halbleiteranordnung mit einer Trench-erter PN-Diode als Klammerelement, die sich insbesondere als Z-Diode mit einer Druchbruchspannung von ca. 20V zum Einsatz in Kfz-Generatorsystem eignet, beschrieben. Dabei besteht die TJBS aus einer Kombination von Schottky-Diode und PN-Diode. Für die Durchbruchspannungen gilt, dass die Durchbruchspannung der PN-Diode BV_pn niedriger ist als die Durchbruchspannung der Schottky-Diode BV_schottky. Daher kann die Halbleiteranordnung mit hohen Strömen im Durchbruch betrieben werden.

Semiconductor device with 3-D resurf junctions

Semiconductor device

Manufacture of semiconductor devices with schottky barriers

SEMICONDUCTOR DEVICE

... 1368283 Semi-conductor devices SONY CORP 30 July 1971 [31 July 1970] 35996/71 Heading H1K In a semi-conductor device breakdown voltage of the surface adjacent part of a PN junction is increased by disposing on it an oxide layer overlain by a layer of non-monocrystalline silicon at least 1 Á thick which may in turn be covered with oxide. The layers may additionally serve to interrupt the surface channels associated with oxide passivation. The non-monocrystalline silicon, which may be P or N doped or intrinsic, is preferably deposited by thermal decomposition of silane. In a planar PN diode the silicon forms an annulus over the junction while in a PN mesa diode it extends over the entire mesa apart from the contact area. In both cases the highest breakdown voltage is achieved with the semi-conductor surface lying in a 110 crystallographic plane. In a planar diode with concentric guard rings the silicon extends over the areas of the substrate between the rings and the diode junction and over ...

Semiconductor device

... 1,078,273. Semi-conductor devices. SONY CORPORATION. Oct. 19, 1964, No. 42492/64. Heading H1K. To raise the breakdown voltage of a surfaceemergent junction in a planar diode or transistor the surface perimeter of the region forming the junction is surrounded by a zone of the same conductivity type and which is spaced from the region by an amount less than the width of the depletion region of the main junction when, in the absence of the zone, surface breakdown would be imminent. The zone is not connected to an electrode and is thus at a floating potential. By this means the breakdown voltage of the surface part of the main junction may be raised to approach or equal that of the internal part of the main junction. The embodiment described is a silicon diode provided with oxide protection over the intersections of the main and subsidiary junctions with the surface. Sizes of typical diffusion masks are given.

Semiconductor device

Semiconductor device with high surge endurance

Semiconductor device and method of fabricating same

There is disclosed a semiconductor device comprising a plurality of P well regions (4) and a P well region (41) insulated from each other by a plurality of trench isolating layers (10) formed regularly in predetermined spaced relation with each other and having the same depth. At least part of the outermost P well region (41) isolatedly formed externally of an outermost trench isolating layer (10A) is made deeper than the inner P well regions (4). This provides for the alleviation of the electric field concentration generated in the bottom edge of the outermost isolating layer of trench structure, thereby achieving the semiconductor device having an improved device breakdown voltage. The semiconductor device is a MOSFET or an IGBT. ...

CONDUCTIVITY MODULATED MOSFET

Manufacture of trench-gate semiconductor devices

PROCESS FOR MANUFACTURE OF HIGH POWER MOSFET WITH LATERALLY DISTRIBUTED HIGH CARRIER DENSITY BENEATH THE GATE OXIDE

VDMOS DEVICE

An asymmetric thyristor

In a thyristor having an n<+>pn<->n<+>p<+> structure, the junction 30 between the n-base 26 and the p<+>-type anode-emitter 31 terminates at the lower surface of the thyristor. The interface 32 between the n<-> and n<+> regions 27,28 of the n-base 26 also terminates at the lower surface. This arrangement provides a high blocking voltage and a low forward voltage drop. A p<+> field- dividing ring 37 is formed in the lower surface of the thyristor n<-> between the interface 32 and the edge. The edge is negatively bevelled such that the angle between the top surface and the edge is acute. The n<+> type cathode emitter 20 is annular and surrounds the gate electrode 44. ...

Reverse blocking IGBT

A semiconductor device

Semiconductor device monolithically integrated with a leakage current sense region

FIELD EFFECT TRANSISTORS

HIGH VOLTAGE SEMICONDUCTOR ARRANGEMENT CONCLUSION

SEMICONDUCTOR DEVICE AND MANUFACTURING PROCESS FOR IT

SIC FIELD-EFFECT TRANSISTOR AND USE OF THE SAME AS GAS SENSOR

SELFALIGNED GATE GUARD RINGSTRUKTUR FOR SIT

MONOLITHISCHER VERTIKAL- SPERRSCHICHTFELDEFFEKTTRANSISTOR UND AUS SILIZIUMCARBID HERGESTELLTE SCHOTTKY- BARRIERENDIODE UND HERSTELLUNGSVERFAHREN DAFÜR

POWER SEMICONDUCTOR ELEMENT

PROCEDURE FOR THE PRODUCTION OF A VERTICAL ONE, METAL OXIDE SEMICONDUCTOR

Schottky diode having increased active surface area with improved reverse bias characteristics and method of fabrication

Monolithic vertical junction field effect transistor and Schottky barrier diode fabricated from silicon carbide and method for fabricating the same

LATERAL SHORT-CHANNEL DMOS, METHOD FOR MANUFACTURING SAME AND SEMICONDUCTOR DEVICE

Semiconductor device and method of forming a semiconductor device

MESA TYPE SEMICONDUCTOR DEVICE WITH GUARD RING

AVALANCHE PHOTODIODE WITH DOUBLE GUARD RING

... 6446-320 An avalanche photodiode has a light absorbing semiconductor layer and an avalanche gain semiconductor layer having a bandgap greater than that of the light absorbing semiconductor layer. A first p-n junction having a substantially p+-n junction is selectively provided in the avalanche gain semiconductor layer. A second p-n junction having a substantially graded p-n junction surrounds the periphery of the first p-n junction. A third p-n junction having a substantially graded p-n junction surrounds the periphery of the second p-n junction. A specific feature of the invention is that the second p-n junction is positioned deeper from the upper surface than the first p-n junction and the third p-n junction is positioned closer to the upper surface than the second p-n junction. The photodiode of the invention is capable of achieving sufficient and uniform avalanche gain in a stepwise p-n junction region corresponding to its light receiving region before a voltage breakdown occurs in ...

MESA TYPE SEMICONDUCTOR DEVICE WITH GUARD RING

... 9 49,281 The present invention is directed to a mesa type semiconductor device, formed in a body of semiconductor material, containing at least one guard ring region. The at least one guard ring region is formed to a relatively shallow depth within the body thereby reducing the height of the mesa above the main portion of the body of semiconductor material. The resultant device is physically stronger than prior art devices.

PROCESS FOR MANUFACTURE OF HIGH POWER MOSFET WITH LATERALLY DISTRIBUTED HIGH CARRIER DENSITY BENEATH THE GATE OXIDE

PROCESS FOR MANUFACTURE OF HIGH POWER MOSFET WITH LATERALLY DISTRIBUTED HIGH CARRIER DENSITY BENEATH THE GATE OXIDE A high power MOSFET structure consists of a plurality of source cells distributed over the upper surface of a semiconductor chip, with a drain electrode on the bottom of the chip. Each of the source cells is hexagonal in configuration and is surrounded by a narrow, hexagonal conduction region disposed beneath a gate oxide. The semiconductor material beneath the gate oxide has a relatively high conductivity, with the carriers being laterally equally distributed in density beneath the gate oxide. The high conductivity hexagonal channel is formed in a low conductivity epitaxially formed region and consists of carriers deposited on the epitaxial region prior to the formation of the source region. Symmetrically arranged gate fingers extend over the upper surface of the device and extend through and along slits in the upper source metallizing and are connected to a polysilicon gate ...

SEMICONDUCTOR DEVICE AND METHOD OF FORMING A SEMICONDUCTOR DEVICE

A power semiconductor device (10) has an active region that includes a drift region (20). At least a portion of the drift region (20) is provided in a membrane )16) which has opposed top and bottom surfaces (15, 17). In one embodiment, the top surface (15) of the membrane (16) has electrical terminals connected directly or indirectly thereto to allow a voltage to be applied laterally across the drift region (20). In another embodiment, at least one electrical terminal is connected directly or indirectly to the top surface (15) and at least one electrical terminal is connected directly or indirectly to the bottom surface (17) to allow a voltage to be applied vertically across the drift region (20). In each of these embodiments, the bottom surface (17) of the membrane (16) does not have a semiconductor substrate positioned adjacent thereto.

PROCESS FOR MANUFACTURE OF HIGH POWER MOSFET WITH LATERALLY DISTRIBUTED HIGH CARRIER DENSITY BENEATH THE GATE OXIDE

LATERAL JUNCTION FIELD EFFECT TRANSISTOR DEVICE

JUNCTION BARRIER SCHOTTKY RECTIFIERS AND METHODS OF MAKING THEREOF

A junction barrier Schottky (JBS) rectifier device and a method of making th e device are described. The device comprises an epitaxially grown first n-type drift layer and p-type regions forming p+-n junctions and self-plana.pi.zing epitaxially over-grown second n-type drift regions between and, optionally, on top of the p-type regions. The device may include an edge termination structure such as an exposed or buried p+-n guard ring, a regrown or implant ed junction termination extension (JTE) region, or a "deep" mesa etched down to the substrate. The Schottky contact to the second n-type drift region and th e ohmic contact to the p-type region together serve as an anode. The cathode c an be formed by ohmic contact to the n-type region on the backside of the wafer . The devices can be used in monolithic digital, analog, and microwave integrated circuits.

Hochspannungs-Halbleitergleichrichter

Stabilisiertes Halbleiterbauelement

Halbleiterdiode

Halbleiteranordnung mit mindestens einem planaren pn-Uebergang

POWER SEMICONDUCTOR ELEMENT WITH ZONE GUARD RINGS.

SEMICONDUCTOR ARRANGEMENT WITH AT LEAST ONE FIELD-EFFECT TRANSISTOR.

SEMICONDUCTOR ARRANGEMENT.

HIGH CURRENT MOS FIELD-EFFECT TRANSISTOR.

Semiconductor device.

SEMICONDUCTOR COMPONENT.

Semiconductor power element, e.g. for thyristor or IGBT, has substrate with vertical and recessed lateral surfaces, and primary and secondary electrode regions

The power element, applicable e.g. to an NPNP thyristor or IGBT (insulated gate bi-polar transistor), consists of a semiconductor substrate (1) with a first type of conductivity and having lateral surfaces with vertical (1a) and recessed (1b) sections. It has a control electrode region (2) with a second type of conductibility, formed in a first main surface (1c) of the substrate and having primary electrode regions (3). A second main surface (1d) of the substrate opposite the first has a second electrode region (4) and a guard ring (5) surrounding it.

Semiconductor device

Insulated gate semiconductor device and method for manufacturing same

An insulated gate semiconductor device which comprises, in a surface layer of a substrate between trenches (10) that are filled with gate electrodes (6) with gate insulating films (5a) being interposed therebetween, a region that includes a p-type base region (3) and an n<+>-type emitter region (4) and is in conductive contact with an emitter electrode (8), and a floating p-type region (20) that is potentially insulated by an insulating film (7) that is interposed between the floating p-type region (20) and the emitter electrode (8). This insulated gate semiconductor device is configured such that the depth of the floating p-type region (20) is deeper than the trenches (10) and the impurity concentration of the floating p-type region (20) is lower than that of the p-type base region (3).

Semiconductor Devices and Methods for Forming a Semiconductor Device

Semiconductor device

Semiconductor device and method for manufacturing same

Semiconductor device

A power semiconductor component and method of manufacturing the same

Transistor device

Method and system fabricating floating guard rings in GaN materials

Semiconductor device

A semiconductor device using one or more guard rings includes a p-type guard ring region (7) surrounding a pn junction region (8), an insulating film (9) covering the p-type guard ring region (7), one or more conductive films (11) electrically connected with the p-type guard ring region (7) through one or more contact holes (10) made in the insulating film (9), and a semi-insulating film (12) covering the insulating film (9) and the conductive films (11). Thus, a desired breakdown voltage characteristic can be ensured even if a foreign matter or the like adheres to a surface of the conductivefilms (11).

Semiconductor device and manufacturing method of semiconductor device

Semiconductor device and method for forming semiconductor device

Power diode preparation method

Semiconductor structure

Bipolar transistor

Integrated schottky diode in high voltage semiconductor device

Approach to intergrate schottky in MOSFET and structure

Semiconductor device and method for manufacturing semiconductor device

Semiconductor device including a diode and method of manufacturing a semiconductor device

A semiconductor device includes a transistor cell array in the semiconductor body of a first conductivity type. The semiconductor device further includes a first trench in the transistor cell array between transistor cells. The first trench extends into the semiconductor body from a first side and includes a pn junction diode electrically coupled to the semiconductor body at a sidewall.

Withstand voltage layer with special shaped doped island for semiconductor device

Composant à semi-conducteurs, à au moins une jonction planaire p-n et à anneaux de protection.

COMPOSANT A SEMI-CONDUCTEURS DONT LA TENSION INVERSE DES JONCTIONS PLANAIRES P-N 4 PEUT ATTEINDRE DES VALEURS SUPERIEURES A 2 KV PAR UTILISATION D'ANNEAUX 5 DITS DE PROTECTION. UNE REGION 6, QUI DU MEME TYPE DE CONDUCTIVITE QUE CELUI DE LA REGION SEMI-CONDUCTRICE 1 QUI ENTOURE LES ANNEAUX DE PROTECTION 5, MAIS DONT LA CONCENTRATION EN DOPANT EST SUPERIEURE A CELLE DE CETTE REGION, PRECEDE LE BORD DE CES ANNEAUX 5 QUI EST SITUE DU COTE DE LA JONCTION P-N CORRESPONDANTE. APPLICATION AUX STRUCTURES A ANNEAUX DE PROTECTION AFIN DE REDUIRE LA SURFACE NECESSAIRE A CES ANNEAUX.

DIODE SCHOTTKY ON SILICON CARBIDE SUBSTRATE

SEMICONDUCTOR DEVICE HAS TRANSISTOR REMOVING THE PRODUCTION OF STRAY CURRENT

ENHANCEMENT MODE HIGH ELECTRON MOBILITY TRANSISTOR

SEMICONDUCTOR DEVICE HAS HIGH VOLTAGE OF BREAKDOWN

MANUFACTORING PROCESS Of a FIELD-EFFECT TRANSISTOR OF TYPE DMOS HAS VERTICAL OPERATION AND TRANSISTOR OBTAINED BY THIS PROCESS

Semiconductor device

The present teachings provides a semiconductor device which has a semiconductor substrate, and a lower electrode including a first layer in contact with a lower surface of the semiconductor substrate, a second layer in contact with a lower surface of the first layer, and a third layer stacked at a position farther from the semiconductor substrate than the second layer, wherein the first layer is an aluminum layer containing silicon, the second layer is a layer including silicon as a primary component, and the third layer is a solder joint layer.

High Voltage Semiconductor Devices

In one embodiment, the semiconductor device includes a first source of a first doping type disposed in a substrate. A first drain of the first doping type is disposed in the substrate. A first gate region is disposed between the first source and the first drain. A first channel region of a second doping type is disposed under the first gate region. The second doping type is opposite to the first doping type. A first extension region of the first doping type is disposed between the first gate and the first drain. The first extension region is part of a first fin disposed in or over the substrate. A first isolation region is disposed between the first extension region and the first drain. A first well region of the first doping type is disposed under the first isolation region. The first well region electrically couples the first extension region with the first drain.

Semiconductor device and method of manufacturing the same

A semiconductor device includes a drift layer, a base layer on the drift layer, and trench gate structures. Each trench gate structure includes a trench reaching the drift layer by penetrating the base layer, a gate insulation layer on a wall surface of the trench, and a gate electrode on the gate insulation layer. A bottom portion of the trench gate structure is located in the drift layer and expands in a predetermined direction so that a distance between the bottom portions of adjacent trench gate structures is less than a distance between opening portions of adjacent trench gate structures in the direction. A thickness of the gate insulation layer is greater in the bottom portion than in the opening portion.

Semiconductor device and manufacturing method for the same

A semiconductor device includes a first conductive type first semiconductor region, a second semiconductor region, and a second conductive type lateral RESURF region. The first semiconductor region is arranged on a first electrode side. The second semiconductor region includes first conductive type first pillar regions and a terminal part. The second pillar regions are alternately arranged on an element part. The terminal part is formed around the element part along a surface of the first semiconductor region on a second electrode side opposite to the first electrode side of the first semiconductor region. Furthermore, the second conductive type lateral RESURF region is formed in the second semiconductor region on the terminal part.

Power Semiconductor Device Having Gate Electrode Coupling Portions for Etchant Control

A general insulated gate power semiconductor active element with many gate electrodes arranged in parallel has a laminated structure including a barrier metal film and a thick aluminum electrode film formed over the gate electrodes via an interlayer insulating film. When the aluminum electrode film is embedded in between the gate electrodes in parallel, voids may be generated with the electrodes. Such voids allow the etchant to penetrate in wet etching, which may promote the etching up to a part of the electrode film in an active cell region which is to be left. Thus, an insulated gate power semiconductor device is provided to include gate electrodes protruding outward from the inside of the active cell region, and a gate electrode coupling portion for coupling the gate electrodes outside the active cell region. The gate electrode coupling portion is covered with a metal electrode covering the active cell region.

Semiconductor device

A semiconductor device is disclosed wherein a peripheral region with a high breakdown voltage and high robustness against induced surface charge is manufactured using a process with high mass productivity. The device has n-type drift region and p-type partition region of layer-shape deposited in a vertical direction to one main surface of n-type semiconductor substrate with high impurity concentration form as drift layer, alternately adjacent parallel pn layers in a direction along one main surface. Active region through which current flows and peripheral region enclosing the active region include parallel pn layers. P-type partition region has impurity concentration distribution where concentration decreases from surface toward substrate side, n-type surface region disposed on parallel pn layers in peripheral region, p-type guard rings disposed separately from each other on n-type surface region, and field plate disposed on inner and outer circumferential sides of p-type guard rings, and electrically connected.

Schottky rectifier

A semiconductor rectifier includes a semiconductor substrate having a first type of conductivity. A first layer, which is formed on the substrate, has the first type of conductivity and is more lightly doped than the substrate. A second layer having a second type of conductivity is formed on the substrate and a metal layer is disposed over the second layer. The second layer is lightly doped so that a Schottky contact is formed between the metal layer and the second layer. A first electrode is formed over the metal layer and a second electrode is formed on a backside of the substrate.

Bipolar junction transistor guard ring structures and method of fabricating thereof

Semiconductor devices with multiple floating guard ring edge termination structures and methods of fabricating same are disclosed. A method for fabricating guard rings in a semiconductor device that includes forming a mesa structure on a semiconductor layer stack, the semiconductor stack including two or more layers of semiconductor materials including a first layer and a second layer, said second layer being on top of said first layer, forming trenches for guard rings in the first layer outside a periphery of said mesa, and forming guard rings in the trenches. The top surfaces of said guard rings have a lower elevation than a top surface of said first layer.

Bipolar transistor with guard region

A bipolar transistor comprising an emitter region, a base region and a collector region, and a guard region spaced from and surrounding the base. The guard region can be formed in the same steps that form the base, and can serve to spread out the depletion layer in operation.

Semiconductor device

A semiconductor device includes an epitaxial layer having a first conductive type, and at least one first semiconductor layer and a second semiconductor layer having a second conductive type. The first semiconductor layer is disposed in the epitaxial layer of a peripheral region, and has an arc portion, and a first strip portion and a second strip portion extended from two ends of the arc portion. The first strip portion points to an active device region, and the second strip portion is perpendicular to the first strip portion The second semiconductor layer is disposed in the epitaxial layer of the peripheral region between the active device region and the second strip portion, and the second semiconductor has a sidewall facing and parallel to the first semiconductor layer.

Diode

A diode has a semiconductor layer and cathode and anode electrodes on a surface of the semiconductor layer. The semiconductor layer has cathode and anode regions respectively contacting the cathode and anode electrodes. The anode region has a first diffusion region having high surface concentration, a second diffusion region having intermediate surface concentration, and a third diffusion region having low surface concentration. The first diffusion region is covered with the second and third diffusion regions. The second diffusion region has a first side surface facing the cathode region, a second side surface opposite to the cathode region, and a bottom surface extending between the first and second side surfaces. The third diffusion region covers at least one of the first corner part connecting the first side surface with the bottom surface and the second corner part connecting the second side surface with the bottom surface.

Semiconductor Device

A semiconductor device includes a semiconductor layer of a first conductivity type and a semiconductor layer of a second conductivity type formed thereon. The semiconductor layer of the second conductivity type is characterized by a first thickness. The semiconductor device includes a set of trenches having a predetermined depth and extending into the semiconductor layer of the second conductivity type, thereby defining interfacial regions disposed between the semiconductor layer of the second conductivity type and each of the trenches. The trenches comprises a distal portion consisting essentially of a dielectric material disposed therein and a proximal portion comprising the dielectric material and a gate material disposed interior to the dielectric material in the proximal portion of the trench. The semiconductor device further includes a source region coupled to the semiconductor layer of the second conductivity type.

Semiconductor device

In a semiconductor power device such as a power MOSFET having a super-junction structure in each of an active cell region and a chip peripheral region, an outer end of a surface region of a second conductivity type coupled to a main junction of the second conductivity type in a surface of a drift region of a first conductivity type and having a concentration lower than that of the main junction is located in a middle region between an outer end of the main junction and an outer end of the super-junction structure in the chip peripheral region.

Semiconductor device and manufacturing method thereof

A thin semiconductor wafer, on which a top surface structure and a bottom surface structure that form a semiconductor chip are formed, is affixed to a supporting substrate. Then, on the wafer, a trench to become a scribing line is formed with a crystal face exposed so as to form a side wall of the trench. On that side wall, an isolation layer for holding a reverse breakdown voltage is formed by ion implantation and low temperature annealing or laser annealing so as to be extended to the top surface side while being in contact with a p collector region as a bottom surface diffused layer. Then, laser dicing is carried out to dice a collector electrode, formed on the p collector region, together with the p collector region.

Method of forming a semiconductor device termination and structure therefor

At least one embodiment is directed to a semiconductor edge termination structure, where the edge termination structure comprises several doped layers and a buffer layer.

Semiconductor rectifier device

A semiconductor rectifier device according to an embodiment includes a semiconductor substrate of a first conductive type of a wide gap semiconductor, a semiconductor layer of the first conductive type of the wide gap semiconductor formed on an upper surface of the semiconductor substrate, wherein an impurity concentration of the semiconductor layer is between 1E+14 atoms/cm 3 and 5E+16 atoms/cm 3 inclusive, and a thickness thereof is 8 μm or more, a first semiconductor region of the first conductive type of the wide gap semiconductor formed on the semiconductor layer surface, a second semiconductor region of the second conductive type of the wide gap semiconductor formed as sandwiched by the first semiconductor regions, wherein a width of the second semiconductor region is 15 μm or more, a first electrode formed on the first and second semiconductor regions, and a second electrode formed on a lower surface of the semiconductor substrate.

Semiconductor device

According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductive type, and a periodic array structure having a second semiconductor layer of a first conductive type and a third semiconductor layer of a second conductive type periodically arrayed on the first semiconductor layer in a direction parallel with a major surface of the first semiconductor layer. The second semiconductor layer and the third semiconductor layer are disposed in dots on the first semiconductor layer. A periodic structure in the outermost peripheral portion of the periodic array structure is different from a periodic structure of the periodic array structure in a portion other than the outermost peripheral portion.

Semiconductor device

A semiconductor layer has a second impurity concentration. First trenches are formed in the semiconductor layer to extend downward from an upper surface of the semiconductor layer. Each of insulation layers is formed along each of the inner walls of the first trenches. Each of conductive layers is formed to bury each of the first trenches via each of the insulation layers, and extends downward from the upper surface of the semiconductor layer to a first position. A first semiconductor diffusion layer reaches a second position from the upper surface of the semiconductor layer, is positioned between the first trenches, and has a third impurity concentration lower than the second impurity concentration. A length from the upper surface of the semiconductor layer to the second position is equal to or less than half a length from the upper surface of the semiconductor layer to the first position.

Semiconductor system including a schottky diode

A semiconductor system is described, which includes a trench junction barrier Schottky diode having an integrated p-n type diode as a clamping element, which is suitable for use in motor vehicle generator system, in particular as a Zener diode having a breakdown voltage of approximately 20V. In this case, the TJBS is a combination of a Schottky diode and a p-n type diode. Where the breakdown voltages are concerned, the breakdown voltage of the p-n type diode is lower than the breakdown voltage of Schottky diode. The semiconductor system may therefore be operated using high currents at breakdown.

Superjunction Structures for Power Devices and Methods of Manufacture

A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type.

Semiconductor device and method for forming the same

A semiconductor device and a method for forming the same are disclosed. In a method for forming the semiconductor substrate including a cell region and a peripheral region, a guard pattern defined by an epitaxial growth layer located at the edge part between the cell region and the peripheral region is formed. As the guard pattern is not damaged by an oxidation process, a bias leakage path between an N-well bias and a P-well bias of the peripheral region is prevented from occurring Reliability of a gate oxide film may be increased, resulting in an increased production yield of the semiconductor device and implementation of stable voltage and current characteristics.

Semiconductor device having groove-shaped via-hole

The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66 a having a pattern bent at a right angle; and buried conductors 70, 72 a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66 a. A groove-shaped via-hole 66 a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.

Method of manufacturing semiconductor device and semiconductor device

Techniques capable of improving the yield of IGBTs capable of reducing steady loss, turn-off time, and turn-off loss are provided. Upon formation of openings in an interlayer insulting film formed on a main surface of a substrate, etching of a laminated insulating film of a PSG film and an SOG film and a silicon oxide film is once stopped at a silicon nitride film. Then, the silicon nitride film and the silicon oxide film are sequentially etched to form the openings. As a result, the openings are prevented from penetrating through an n-type source layer and a p + -type emitter layer having a thickness of 20 to 100 nm and reaching the substrate.

Semiconductor device with increased channel mobility and dry chemistry processes for fabrication thereof

Embodiments of a semiconductor device having increased channel mobility and methods of manufacturing thereof are disclosed. In one embodiment, the semiconductor device includes a substrate including a channel region and a gate stack on the substrate over the channel region. The gate stack includes an alkaline earth metal. In one embodiment, the alkaline earth metal is Barium (Ba). In another embodiment, the alkaline earth metal is Strontium (Sr). The alkaline earth metal results in a substantial improvement of the channel mobility of the semiconductor device.

Mosfet-schottky rectifier-diode integrated circuits with trench contact structures

A trench MOSFET device with embedded Schottky rectifier, Gate-Drain and Gate-Source clamp diodes on single chip is formed to achieve device shrinkage and performance improvement. The present semiconductor devices achieve low Vf and reverse leakage current for embedded Schottky rectifier, have overvoltage protection for Gate-Source clamp diode and avalanche protection for Gate-Drain clamp diode.

Power semiconductor device

A power semiconductor device includes a high resistance epitaxial layer having a first pillar region and a second pillar region as a drift layer. The first pillar region includes a plurality of first pillars of the first conductivity type and a plurality of second pillars of the second conductivity type disposed alternately along a first direction. The second pillar region is adjacent to the first pillar region along the first direction. The second pillar region includes a third pillar and a fourth pillar of a conductivity type opposite to a conductivity type of the third pillar. A net quantity of impurities in the third pillar is less than a net quantity of impurities in each of the plurality of first pillars. A net quantity of impurities in the fourth pillar is less than the net quantity of impurities in the third pillar.

Semiconductor device and manufacturing method of the same

A semiconductor device includes first, second, and third semiconductor layers each having multiple diffusion layers. The first direction widths of the first diffusion layers are the same. The amount of impurity within the first diffusion layers gradually increases from the bottom end towards the top end of the first semiconductor layer. The first direction widths of the second diffusion layers are the same. The amounts of impurity within the second diffusion layers are the same. The first direction widths of the third diffusion layers are narrower than the first direction widths of the first diffusion layers and the first direction widths of the second diffusion layers at the same level, and gradually become narrower from the bottom end towards the top end of the third semiconductor layer. The amount of impurity within the third. diffusion layers are the same.

Manufacturing process of a power electronic device integrated in a semiconductor substrate with wide band gap and electronic device thus obtained

An embodiment of a process for manufacturing an electronic device on a semiconductor body of a material with wide forbidden bandgap having a first conductivity type. The process comprises the steps of: forming, on the semiconductor body, a first mask having a first window and a second window above a first surface portion and a second surface portion of the semiconductor body; forming, within the first and second surface portions of the semiconductor body underneath the first and second windows, at least one first conductive region and one second conductive region having a second conductivity type, the first conductive region and the second conductive region facing one another; forming a second mask on the semiconductor body, the second mask having a plurality of windows above surface portions of the first conductive region and the second conductive region; forming, within the first conductive region and the second conductive region and underneath the plurality of windows, a plurality of third conductive regions having the first conductivity type; removing completely the first and second masks; performing an activation thermal process of the first, second, and third conductive regions at a high temperature; and forming body and source regions.

Aluminum gallium nitride etch stop layer for gallium nitride bases devices

A semiconductor structure includes a III-nitride substrate with a first side and a second side opposing the first side. The III-nitride substrate is characterized by a first conductivity type and a first dopant concentration. The semiconductor structure also includes a III-nitride epitaxial layer of the first conductivity type coupled to the first surface of the III-nitride substrate, and a first metallic structure electrically coupled to the second surface of the III-nitride substrate. The semiconductor structure further includes an AlGaN epitaxial layer coupled to the III-nitride epitaxial layer of the first conductivity type, and a III-nitride epitaxial structure of a second conductivity type coupled to the AlGaN epitaxial layer. The III-nitride epitaxial structure comprises at least one edge termination structure.

Edge Termination by Ion Implantation in GaN

An edge terminated semiconductor device is described including a GaN substrate; a doped GaN epitaxial layer grown on the GaN substrate including an ion-implanted insulation region, wherein the ion-implanted region has a resistivity that is at least 90% of maximum resistivity and a conductive layer, such as a Schottky metal layer, disposed over the GaN epitaxial layer, wherein the conductive layer overlaps a portion of the ion-implanted region. A Schottky diode is prepared using the Schottky contact structure.

Method and system for fabricating edge termination structures in gan materials

A method for fabricating an edge termination, which can be used in conjunction with GaN-based materials, includes providing a substrate of a first conductivity type. The substrate has a first surface and a second surface. The method also includes forming a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the substrate and forming a second GaN epitaxial layer of a second conductivity type opposite to the first conductivity type. The second GaN epitaxial layer is coupled to the first GaN epitaxial layer. The substrate, the first GaN epitaxial layer and the second GaN epitaxial layer can be referred to as an epitaxial structure.

Semiconductor Diode and Method for Forming a Semiconductor Diode

A semiconductor diode is provided. The semiconductor diode includes a monocrystalline silicon semiconductor body including a first semiconductor region of a first conductivity type extending to a first surface of the semiconductor body and having a first maximum doping concentration, and a second semiconductor region of a second conductivity type forming a pn-junction with the first semiconductor region. The semiconductor diode further includes a polycrystalline silicon semiconductor region of the first conductivity type having a second maximum doping concentration which is higher than the first maximum doping concentration and adjoining the first semiconductor region on the first surface, a first metallization arranged on the polycrystalline silicon semiconductor region and in electric contact with the polycrystalline semiconductor region, and an edge-termination structure arranged next to the first semiconductor region. Further, a method for producing a semiconductor diode is provided.

Semiconductor device

A semiconductor device is disclosed that has enhanced its electric charge resistance. A first parallel p-n layer is disposed in an element activating part, and a second parallel p-n layer is disposed in an element peripheral edge part. An n − surface area is disposed between the second parallel p-n layer and a first principal face. Two or more p-type guard ring areas are disposed so as to be separate from each other on the first principal face side of the n − surface area. First field plate electrodes and second field plate electrodes are electrically connected to p-type guard ring areas. Second field plate electrodes cover the first field plate electrodes adjacent to each other so as to cover the first principal face between the first field plate electrodes through a second insulating film.

Monolithic high voltage multiplier

High voltage diode-connected gallium nitride high electron mobility transistor structures or Schottky diodes are employed in a network including high-k dielectric capacitors in a solid state, monolithic voltage multiplier. A superjunction formed by vertical p/n junctions in gallium nitride facilitates operation of the high electron mobility transistor structures and Schottky diodes. A design structure for designing, testing or manufacturing an integrated circuit is tangibly embodied in a machine-readable medium and includes elements of a solid state voltage multiplier.

NITRIDE SEMICONDUCTOR DEVICE

According to one embodiment, a nitride semiconductor device including a device region and a guard ring formation region surrounding the device region, the nitride semiconductor device includes a first nitride semiconductor layer provided in the device region and the guard ring formation region; a second nitride semiconductor layer provided on the first nitride semiconductor layer and forming a hetero-junction with the first nitride semiconductor layer; and a shielding layer provided on the second nitride semiconductor layer in the guard ring formation region and electrically protecting the device region. A two-dimensional electron gas is present near an interface between the first nitride semiconductor layer and the second nitride semiconductor layer within the first nitride semiconductor layer below the shielding layer, and the shielding layer is in ohmic contact with the two-dimensional electron gas. 1. A nitride semiconductor device including a device region and a guard ring formation region surrounding the device region , the nitride semiconductor device comprising:a first nitride semiconductor layer provided in the device region and the guard ring formation region;a second nitride semiconductor layer provided on the first nitride semiconductor layer and forming a hetero-junction with the first nitride semiconductor layer; anda shielding layer provided on the second nitride semiconductor layer in the guard ring formation region and electrically protecting the device region,wherein a two-dimensional electron gas is present near an interface between the first nitride semiconductor layer and the second nitride semiconductor layer within the first nitride semiconductor layer below the shielding layer, andthe shielding layer is in ohmic contact with the two-dimensional electron gas.2. The device according to claim 1 , wherein the device region is surrounded by the shielding layer and the two-dimensional electron gas.3. The device according to claim 1 , further ...

Power semiconductor device and fabrication method thereof

A fabrication method of a power semiconductor device is provided. Firstly, a plurality of trenched gate structures is formed in the base. Then, a body mask is used for forming a pattern layer on the base. The pattern layer has at least a first open and a second open for forming at least a body region and a heavily doped region in the base respectively. Then, a shielding structure is formed on the base to fill the second open and line at least a sidewall of the first open. Next, a plurality of source doped regions is formed in the body region by using the pattern layer and the shielding structure as the mask. Then, an interlayer dielectric layer is formed on the base and a plurality of source contact windows is formed therein to expose the source doped regions.

Semiconductor device and manufacturing method thereof

A semiconductor device of the present invention includes a semiconductor layer composed of SiC, a metal layer directly bonded to one face of the semiconductor layer, and a high carbon concentration layer formed on a surface layer portion at one side of the semiconductor layer and containing more highly concentrated carbon than a surface layer portion of the other side. Further, a manufacturing method of a semiconductor device of the present invention includes the steps of forming, on a surface layer portion at one face side of a semiconductor layer composed of SiC, a high carbon concentration layer containing more highly concentrated carbon than a surface layer portion at the other face side by heat treatment and directly bonding metal to the high carbon concentration layer.

Trench mosfet with trenched floating gates having thick trench bottom oxide as termination

A semiconductor power device with trenched floating gates having thick bottom oxide as termination is disclosed. The gate charge is reduced by forming a HDP oxide layer padded by a thermal oxide layer on trench bottom and a top surface of mesa areas between adjacent trenched gates. Therefore, only three masks are needed to achieve the device structure.

Semiconductor device and method for producing the same

In a MOSFET using a SiC substrate, a source region having low resistance and high injection efficiency is formed without performing a high-temperature heat treatment. A vertical Schottky barrier transistor in which a source region SR on a SiC epitaxial substrate is constituted by a metal material is formed. The source region SR composed of a metal material can be brought into a low resistance state without performing a high-temperature activation treatment. Further, by segregating a conductive impurity DP at an interface between the source region SR composed of a metal material and the SiC epitaxial substrate, the Schottky barrier height can be reduced, and the carrier injection efficiency from the source region SR can be improved.

Narrow active cell ie type trench gate igbt and a method for manufacturing a narrow active cell ie type trench gate igbt

In an equal width active cell IE type IGBT, a wide active cell IE type IGBT, and the like, an active cell region is equal in trench width to an inactive cell region, or the trench width of the inactive cell region is narrower. Accordingly, it is relatively easy to ensure the breakdown voltage. However, with such a structure, an attempt to enhance the IE effect entails problems such as further complication of the structure. The present invention provides a narrow active cell IE type IGBT having an active cell two-dimensional thinned-out structure, and not having a substrate trench for contact.

Rectifier circuit

A rectifier circuit has a rectifier element and a unipolar field-effect transistor connected in series between a first terminal and a second terminal. The rectifier element comprises a first electrode and a second electrode disposed in a direction of a forward current flowing from the first terminal to the second terminal. The field-effect transistor has a gate electrode having a potential identical to a potential at the first electrode, and a source electrode and a drain electrode connected in series to the rectifier element and passing a current depending on the potential at the gate electrode. A breakdown voltage between the gate electrode and drain electrode of the field-effect transistor in a reverse bias mode, where a potential at the second terminal is higher than a potential at the first terminal, being set higher than a breakdown voltage of the rectifier element.

Schottky-barrier device with locally planarized surface and related semiconductor product

The present disclosure is related to alleviation of at least some of the above drawbacks of the prior art and to provide an improved alternative to the prior art. Generally, at least some of the embodiments are related to a high voltage power conversion semiconductor device, in particular a SiC Schottky-barrier power rectifier device, having a surface (of the drift layer) with improved smoothness. Further, at least some of the embodiments are related to a method of manufacturing a power rectifier device with reduced leakage currents.

Sinker with a Reduced Width

The width of a heavily-doped sinker is substantially reduced by forming the heavily-doped sinker to lie in between a number of closely-spaced trench isolation structures, which have been formed in a semiconductor material. During drive-in, the closely-spaced trench isolation structures significantly limit the lateral diffusion.

Semiconductor device and method for manufacturing semiconductor device

According to one embodiment, a semiconductor device includes a SiC layer of a first conductivity type, a SiC region of a second conductivity type, and a conductive layer of the second conductivity type. The SiC layer of the first conductivity type has a hexagonal crystal structure. The SiC region of the second conductivity type is formed in a surface of the SiC layer. The conductive layer of the second conductivity type is provided on the SiC region and is in contact with a portion of the SiC region including SiC of a cubic crystal structure.

Semiconductor device and method for manufacturing same

A semiconductor device having a high withstand voltage in which a stable withstand voltage can be obtained and a method for manufacturing the same. A JTE region having a second conductivity type is formed in a portion on an outer peripheral end side of an SiC substrate from a second conductivity type SiC region in a vicinal portion of a surface on one of sides in a thickness direction of a first conductivity type SiC epitaxial layer. A first conductivity type SiC region having a higher concentration of an impurity having the first conductivity type than that of the SiC epitaxial layer is formed in at least a vicinal portion of a surface on one of sides in a thickness direction of a portion in which the JTE regions are bonded to each other.

Active edge structures providing uniform current flow in insulated gate turn-off thyristors

An insulated gate turn-off thyristor, formed as a die, has a layered structure including a p+ layer (e.g., a substrate), an n− layer, a p-well, vertical insulated gate regions formed in the p-well, and n+ regions between the gate regions, so that vertical NPN and PNP transistors are formed. The thyristor is formed of a matrix of cells. Due to the discontinuity along the edge cells, a relatively large number of holes are injected into the n− epi layer and drift into the edge p-well, normally creating a higher current along the edge and lowering the breakover voltage of the thyristor. To counter this effect, the dopant concentration of the n+ region(s) near the edge is reduced to reduce the NPN transistor beta and current along the edge, thus increasing the breakover voltage. Alternatively, a deep trench may circumscribe the edge cells to provide isolation from the injected holes.

RADIO FREQUENCY ISOLATION FOR SOI TRANSISTORS

According to one example embodiment, a structure includes at least one SOI (semiconductor-on-insulator) transistor situated over a buried oxide layer, where the buried oxide layer overlies a bulk substrate. The structure further includes an electrically charged field control ring situated over the buried oxide layer and surrounding the at least one SOI transistor. A width of the electrically charged field control ring is greater than a thickness of the buried oxide layer. The electrically charged field control ring reduces a conductivity of a surface portion of the bulk substrate underlying the field control ring, thereby reducing RF coupling of the at least one SOI transistor through the bulk substrate. The structure further includes an isolation region situated between the electrically charged field control ring and the at least one SOI transistor. A method to achieve and implement the disclosed structure is also provided. 1. A method for reducing RF coupling of at least one SOI (semiconductor-on-insulator) transistor through a bulk substrate of an SOI substrate , said method comprising:forming or providing a field control ring in a silicon layer, above said SOI substrate, said field control ring surrounding said at least one SOI transistor;providing a bias voltage; andcoupling the field control ring to the bias voltage to provide an electrical charge to said field control ring to generate an electrical field that forms a resistive surface portion on said bulk substrate underlying said field control ring to reduce RF coupling of said at least one SOI transistor through said bulk substrate.2. The method of wherein said field control ring includes a conductive material selected from the group consisting of silicon claim 1 , polysilicon claim 1 , and a metal.3. The method of wherein a width of said field control ring is greater than a thickness of a buried oxide layer situated over said bulk substrate.4. The method of further comprising doping the field control ring ...

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

A semiconductor device includes a substrate including a first region and a second region, a trench-gate transistor in the first region, the trench-gate transistor including a first trench in the substrate, a gate filling at least part of the first trench, and a source in the substrate and on each sidewall of the first trench, a first field diffusion junction in the second region, an interlayer insulating film on the substrate, the interlayer insulating film covering the trench-gate transistor and the first field diffusion junction, a first contact in the first region, the first contact passing through the interlayer insulating film and contacting the source, and a second contact in the second region, the second contact passing through the interlayer insulating film and contacting the first field diffusion junction, the first contact and the second contact having an equal height and including a same material. 1. A semiconductor device , comprising:a substrate including a first region and a second region; a first trench in the substrate,', 'a gate filling at least part of the first trench, and', 'a source in the substrate and on each sidewall of the first trench;, 'a trench-gate transistor in the first region, the trench-gate transistor includinga first field diffusion junction in the second region;an interlayer insulating film on the substrate, the interlayer insulating film covering the trench-gate transistor and the first field diffusion junction;a first contact in the first region, the first contact passing through the interlayer insulating film and contacting the source; anda second contact in the second region, the second contact passing through the interlayer insulating film and contacting the first field diffusion junction, the first contact and the second contact having an equal height and including a same material.2. The semiconductor device as claimed in claim 1 , wherein the first contact and the second contact are fabricated simultaneously.3. The ...

Trench-based power semiconductor devices with increased breakdown voltage characteristics

Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.

Device-Manufacturing Scheme for Increasing the Density of Metal Patterns in Inter-Layer Dielectrics

A method includes forming a transistor at a surface of a semiconductor substrate, wherein the step of forming the transistor comprises forming a gate electrode, and forming a source/drain region adjacent the gate electrode. First metal features are formed to include at least portions at a same level as the gate electrode. Second metal features are formed simultaneously, and are over and contacting the first metal features. A first one of the second metal features is removed and replaced with a third metal feature, wherein a second one of the second metal features is not removed. A fourth metal feature is formed directly over and contacting the gate electrode, wherein the third and the fourth metal features are formed using a same metal-filling process.

Method and system for in-situ and regrowth in gallium nitride based devices

A method of regrowing material includes providing a III-nitride structure including a masking layer and patterning the masking layer to form an etch mask. The method also includes removing, using an in-situ etch, a portion of the III-nitride structure to expose a regrowth region and regrowing a III-nitride material in the regrowth region.

Lateral diffusion metal oxide semiconductor transistor structure

A lateral diffusion metal-oxide-semiconductor (LDMOS) transistor structure comprises a barrier layer, a semiconductor layer, a source, a first drain and a guard ring. The barrier layer with a first polarity is disposed in a substrate. The semiconductor layer with a second polarity is disposed on the barrier layer. The source has a first polarity region and a second polarity region both formed in the semiconductor layer. The first drain is disposed in the semiconductor layer and has a drift region with the second polarity. The guard ring with the first polarity extends downward from a surface of the semiconductor layer in a manner of getting in touch with the barrier layer and to surround the source and the drain, and is electrically connected to the source.

Method and system for edge termination in gan materials by selective area implantation doping

A method for fabricating edge termination structures in gallium nitride (GaN) materials includes providing an n-type GaN substrate having a first surface and a second surface, forming an n-type GaN epitaxial layer coupled to the first surface of the n-type GaN substrate, and forming one or more p-type regions in the n-type GaN epitaxial layer by using a first ion implantation. At least one of the one or more p-type regions includes an edge termination structure.

Insulated gate bipolar transistor

There is provided an insulated gate bipolar transistor, including: an active region including a gate electrode, a first emitter metal layer, a first well region, and one portion of a third well region; a termination region including a second well region supporting diffusion of a depletion layer; and a connection region located between the active region and the termination region and including a second emitter metal layer, a gate metal layer, and the other portion of the third well region, wherein the third well region is formed over the active region and the connection region, and the first emitter metal layer and the second emitter metal layer are formed on the third well region.

Tunable Schottky Diode

A device includes a semiconductor substrate, first and second electrodes supported by the semiconductor substrate, laterally spaced from one another, and disposed at a surface of the semiconductor substrate to form an Ohmic contact and a Schottky junction, respectively. The device further includes a conduction path region in the semiconductor substrate, having a first conductivity type, and disposed along a conduction path between the first and second electrodes, a buried region in the semiconductor substrate having a second conductivity type and disposed below the conduction path region, and a device isolating region electrically coupled to the buried region, having the second conductivity type, and defining a lateral boundary of the device. The device isolating region is electrically coupled to the second electrode such that a voltage at the second electrode during operation is applied to the buried region to deplete the conduction path region.

Semiconductor device and semiconductor device manufacturing method

In some aspects of the invention, an n-type field-stop layer can have a total impurity of such an extent that a depletion layer spreading in response to an application of a rated voltage stops inside the n-type field-stop layer together with the total impurity of an n − type drift layer. Also, the n-type field-stop layer can have a concentration gradient such that the impurity concentration of the n-type field-stop layer decreases from a p + type collector layer toward a p-type base layer, and the diffusion depth is 20 μm or more. Furthermore, an n + type buffer layer of which the peak impurity concentration can be higher than that of the n-type field-stop layer at 6×10 15 cm −3 or more, and one-tenth or less of the peak impurity concentration of the p + type collector layer, can be included between the n-type field-stop layer and p + type collector layer.

Semiconductor device

In one surface of a semiconductor substrate, an active region in which main current flows and an IGBT is disposed is formed. A termination structure portion serving as an electric-field reduction region is formed laterally with respect to the active region. In the termination structure portion, a porous-oxide-film region, a p-type guard ring region, and an n+-type channel stopper region are formed. A plurality of floating electrodes are formed to contact the surface of the porous-oxide-film region. Another plurality of floating electrodes are formed to contact a first insulating film.

Semiconductor device and method of manufacturing semiconductor device

A breakdown voltage structure portion includes a field plate with an annular polysilicon field plate and a metal field plate. In the breakdown voltage structure portion, a plurality of annular guard rings are provided in a surface layer of the semiconductor substrate. The polysilicon field plates are separately arranged on the inner circumferential side and the outer circumferential side of the guard ring. Polysilicon bridges that connect the polysilicon field plates on the inner and outer circumferential sides are provided on at least one guard ring among the plurality of guard rings at a predetermined interval so as to be arranged over the entire circumference of the guard ring. The metal field plate is provided on the guard ring in a corner portion of the breakdown voltage structure portion and at least one guard ring in a straight portion of the breakdown voltage structure portion.

Semiconductor device and method for fabricating the same

According to example embodiments of inventive concepts: a semiconductor device includes: first and second trench gates extending long in one direction in a substrate; third and fourth trench gates in the substrate, the third and fourth trench gates connecting the first and second trench gates with each other; a first region defined in the substrate by the first to fourth trench gates and surrounded by the first to fourth trench gates; and a second region and a third region defined in the substrate. The second region is in surface contact with the first region. The third region is in point contact with the first region. The first region includes a first high-voltage semiconductor device including a body of a first conduction type and an emitter of a second conduction type in the body. Floating wells of the first conduction type are in the second region and the third region.

Semiconductor device

A semiconductor device includes a semiconductor substrate having one main surface in which an anode of a diode is formed. At a distance from the outer periphery of the anode, a guard ring is formed to surround the anode. The anode includes a p + -type diffusion region, a p − -type region, and an anode electrode. The p − -type region is formed as a region of relatively high electrical resistance sandwiched between the p + -type diffusion regions.

Power Semiconductor Device Edge Structure

A semiconductor device having a first load terminal, a second load terminal and a semiconductor body is presented. The semiconductor body comprises an active region configured to conduct a load current between the first load terminal and the second load terminal and a junction termination region surrounding the active region. The semiconductor body includes a drift layer arranged within both the active region and the junction termination region and having dopants of a first conductivity type at a drift layer dopant concentration of equal to or less than 10cm; a body zone arranged in the active region and having dopants of a second conductivity type complementary to the first conductivity type and isolating the drift layer from the first load terminal; a guard zone arranged in the junction termination region and having dopants of the second conductivity type and being configured to extend a depletion region formed by a transition between the drift layer and the body zone; a field stop zone arranged adjacent to the guard zone, the field stop zone having dopants of the first conductivity type at a field stop zone dopant concentration that is higher than the drift layer dopant concentration by a factor of at least 2; a low doped zone arranged adjacent to the field stop zone, the low doped zone having dopants of the first conductivity type at a dopant concentration that is lower than the drift layer dopant concentration by a factor of at least 1.5, wherein the body zone, the guard zone, the field stop zone and the low doped zone are arranged in the semiconductor body such that they exhibit a common depth range (DR) of at least μm along a vertical extension direction (Z). 1. A semiconductor device having a first load terminal , a second load terminal and a semiconductor body , the semiconductor body comprising an active region configured to conduct a load current between the first load terminal and the second load terminal and a junction termination region surrounding the ...

TRENCHED AND IMPLANTED BIPOLAR JUNCTION TRANSISTOR

The present invention concerns a monolithically merged trenched-and-implanted Bipolar Junction Transistor (TI-BJT) with antiparallel diode and a method of manufacturing the same. Trenches are made in a collector, base, emitter stack downto the collector. The base electrode is formed on an implanted base contact region at the bottom surface of the trench. The present invention also provides for products produced by the methods of the present invention and for apparatuses used to perform the methods of the present invention. 1. A trenched-and-implanted bipolar junction transistor (TI-BJT) comprising:a drift layer of a second conductivity type;a channel layer of the second conductivity type formed on top of the drift layer;a base layer of a first conductivity type formed on top of the channel layer, wherein the base layer has a thickness which extends along a first direction, wherein the thickness is in the range of 0.02 to 2 microns;an emitter layer of the second conductivity type formed on top of the base layer, the emitter layer having a bottom surface located adjacent to the base layer and a top surface opposite the first bottom surface along the first direction; a first side surface, a second side surface, and a bottom surface, the first side surface, second side surface, and the bottom surface being substantially planar;', 'the first and the second side surfaces spaced apart along a second direction, the second direction being perpendicular to the first direction, the first and second side surfaces extending (1) along the first direction, (2) from the top surface of the emitter layer to the bottom surface of the at least one U-shaped trench, and (3) through the emitter layer, through the base layer, and at least partially into the channel layer; and', 'the bottom surface of the at least one U-shaped trench extending (1) along the second direction and (2) between the first and the second wall of the at least one U-shaped trench;, 'at least one U-shaped trench ...

CARRIER INJECTION CONTROL FAST RECOVERY DIODE STRUCTURES AND METHODS OF FABRICATION

Semiconductor devices and methods of fabrication are provided. The semiconductor device includes a Charge Injection Controlled (CIC) Fast Recovery Diode (FRD) to control charge injection by lowering carrier storage. The device can have a first conductivity type semiconductor substrate, and a drift region that includes a doped buffer region, a doped middle region and a doped field stop region or carrier storage region. The device can also include a second conductivity type shield region including a deep junction encircling (or substantially laterally beneath) the buffer region and a second conductivity type shallow junction anode region in electrical contact with a second conductivity type anode electrode. The deep junction can have a range of doping concentrations surrounding the buffer regions to deplete buffer charge laterally as well as vertically to prevent premature device breakdown. The first conductivity type may be N type and the second conductivity type may be P type. 1. A method of fabricating a Charge Injection Controlled (CIC) Fast Recovery Diode (FRD) , the method comprising:forming a drift region of a first conductivity type on top of a heavily doped semiconductor substrate by epitaxial growth, the drift region supporting blocking of high voltage and comprising a buffer region on the top region of the drift region, a lightly doped middle region, and a medium level doped charge storage region;forming trenches, in the drift region, having depth ranging from 2-6 microns;ion implanting dopants of a second conductivity type into the trenches for forming a shield region of the second conductivity type, the shield region comprising a deep junction substantially spreading laterally beneath the buffer region of the first conductivity type;filling the trenches with poly silicon having lightly doped second conductivity type impurities encircling the buffer region of the first conductivity type;after planarizing the poly silicon in the trenches, ion implanting ...

CONFIGURATION AND METHOD TO GENERATE SADDLE JUNCTION ELECTRIC FIELD IN EDGE TERMINATION

This invention discloses a semiconductor power device disposed in a semiconductor substrate and having an active cell area and an edge termination area the edge termination area wherein the edge termination area comprises a superjunction structure having doped semiconductor columns of alternating conductivity types with a charge imbalance between the doped semiconductor columns to generate a saddle junction electric field in the edge termination. 1. A semiconductor power device disposed in a semiconductor substrate and having an active cell area and an edge termination area wherein:the edge termination area comprises a superjunction structure having doped semiconductor columns of alternating conductivity types wherein the doped semiconductor columns extends along a slanted direction in the edge termination area.2. The semiconductor power device of wherein:the doped semiconductor columns having electric charge imbalance to create a net P type doping in the edge termination area.3. The semiconductor power device of wherein:the edge termination area having a saddle junction electric field.4. The semiconductor power device of wherein:the doped semiconductor columns comprise P-columns and N-columns and the P-columns having greater electric charges than the N-columns.5. The semiconductor power device of wherein:the doped semiconductor columns comprise P-columns and N-columns and the P-columns have greater width than the N-columns.6. The semiconductor power device of wherein:the doped semiconductor columns comprise P-columns and N-columns and the P-columns have a higher dopant concentration than the N-columns.7. The semiconductor power device of wherein the doped semiconductor columns comprise P-columns and N-columns and wherein:the P-columns have a higher dopant concentration on a top portion than a bottom portion.8. The semiconductor power device of wherein:the doped semiconductor columns comprise P-columns and N-columns and the super-junction structure is formed in a P- ...

SEMICONDUCTOR DEVICE

A highly reliable semiconductor device with high withstand voltage is provided. As means therefor, an impurity concentration in a first JTE region is set to 4.4×10cmor higher and 6×10cmor lower and an impurity concentration in a second JTE region is set to 2×10cmor lower in a case of a Schottky diode, and an impurity concentration in the first JTE region is set to 6×10cmor higher and 8×10cmor lower and an impurity concentration in the second JTE region is set to 2×10cmor lower in a case of a junction barrier Schottky diode. 1. A semiconductor device comprising: a main junction region on a drift region having an n-type conductivity; and a p-type JTE region formed adjacently around the main junction region ,wherein the JTE region includes a first JTE region and a second JTE region having an impurity concentration lower than that of the first JTE region,the first JTE region is disposed so as to be sandwiched between the second JTE regions,{'sup': 17', '−3', '17', '−3', '17', '−3, 'an impurity concentration in the first JTE region is set to 4.4×10cmor higher and 8×10cmor lower and an impurity concentration in the second JTE region is set to 2×10cmor lower in a case of a Schottky diode, and'}{'sup': 17', '−3', '17', '−3', '17', '−3, 'an impurity concentration in the first JTE region is set to 6×10cmor higher and 8×10cmor lower and an impurity concentration in the second JTE region is set to 2×10cmor lower in a case of a junction barrier Schottky diode.'}2. The semiconductor device according to claim 1 ,wherein a difference in impurity concentration between the first JTE region and the second JTE region at a p-n junction depth is made small.3. The semiconductor device according to claim 1 ,wherein a ratio between width and space of the second JTE regions decreases in accordance with a distance from the main junction region. The present invention relates to a semiconductor device.Non-Patent Document 1 discloses a vertical p-n diode in which a JTE (Junction Termination ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

By using an SOI substrate in which a front surface-side semiconductor layer, an insulating layer, and a back surface-side semiconductor layer are laminated in this order, vertical semiconductor devices are mass-produced. A process to be executed on a front surface of the SOI substrate is executed on the front surface. A back surface of the SOI substrate is etched so that the back surface-side semiconductor layer and the insulating layer are removed and a back surface of the front surface-side semiconductor layer is exposed. A process to be executed on the exposed back surface of the front surface-side semiconductor layer is executed on the back surface. A thickness of the front surface-side semiconductor layer of the SOI substrate can be accurately controlled, and the semiconductor devices having a semiconductor layer with the same thickness as the thickness of the front surface-side semiconductor layer are mass-produced. 1. A manufacturing method of a vertical semiconductor device , the method comprising:executing a first process, which is to be performed on a front surface, to the front surface of a front surface-side semiconductor layer of an SOI substrate, the SOI substrate including the front surface-side semiconductor layer, an insulating layer, and a back surface-side semiconductor layer that are laminated in this order;an etching a back surface of the SOI substrate after the first process, and removing the back surface-side semiconductor layer and the insulating layer in at least a part of an active region in which a semiconductor structure functioning as a semiconductor device is formed, so as to expose a back surface of the front surface-side semiconductor layer; andexecuting a second process, which is to be performed on the back surface, on the back surface of the front surface-side semiconductor layer after the etching step.2. The manufacturing method according to claim 1 , further comprising:thinning the back surface-side semiconductor layer by ...

MANUFACTURING METHOD OF SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR APPARATUS

A screen oxide film is formed on an n-drift layer () that is disposed on an anterior side of an n-type low-resistance layer (), and a nitride film is formed on the screen oxide film. The nitride film is photo-etched using a first mask and thereby, a nitride shielding film () is formed. N-type impurity ions at a concentration higher than that of the n-drift layer are implanted through the nitride shielding film () from an anterior side of a semiconductor substrate and are thermally diffused and thereby, an n counter layer () is formed. The screen oxide film is removed. A gate oxide film () is formed. A gate electrode () is formed on the gate oxide film (). P-type impurity ions are implanted from the anterior side of the semiconductor substrate using the gate electrode () and the nitride shielding film () as a mask and thereby, p- well regions () are formed. N-type impurity ions are implanted from the anterior side of the semiconductor substrate using the gate electrode () and the nitride shielding film () as a mask and thereby, n source regions () are formed. 1. A semiconductor apparatus provided with an active portion and a voltage-resistant structure portion that surrounds the active portion on a same semiconductor substrate , comprising:a first semiconductor region of a first conductivity;a second semiconductor region of a second conductivity selectively provided in a surface layer on an anterior side of the first semiconductor region;a third semiconductor region of the first conductivity selectively provided in a surface layer of the second semiconductor region;a control electrode that is provided, through a first insulating film, on a surface of the second semiconductor region sandwiched by the first and the third semiconductor regions;a second insulating film that covers the control electrode;a first electrode that contacts the third semiconductor region and is insulated by the second insulating film from the control electrode;a second electrode that is ...

SEMICONDUCTOR DEVICE INCLUDING CRYSTAL DEFECT REGION AND METHOD FOR MANUFACTURING THE SAME

A semiconductor device includes: an n type semiconductor layer including an active region and an inactive region; an element structure formed in the active region and including at least an active side p type layer to form pn junction with n type portion of the n type semiconductor layer; an inactive side p type layer formed in the inactive region and forming pn junction with the n type portion of the n type semiconductor layer; a first electrode electrically connected to the active side p type layer in a front surface of the n type semiconductor layer; a second electrode electrically connected to the n type portion of the n type semiconductor layer in a rear surface of the n type semiconductor layer; and a crystal defect region formed in both the active region and the inactive region and having different depths in the active region and the inactive region. 1. A semiconductor device comprising:a first conductivity type semiconductor layer including an active region and an inactive region;an element structure which is formed in the active region and includes at least an active side second conductivity type layer to form a pn junction with a first conductivity type portion of the first conductivity type semiconductor layer;an inactive side second conductivity type layer which is formed in the inactive region and forms a pn junction with the first conductivity type portion of the first conductivity type semiconductor layer;a first electrode which is electrically connected to the active side second conductivity type layer in a front surface of the first conductivity type semiconductor layer;a second electrode which is electrically connected to the first conductivity type portion of the first conductivity type semiconductor layer in a rear surface of the first conductivity type semiconductor layer; anda crystal defect region which is formed in both of the active region and the inactive region, the crystal defect region in the active region being at a first depth within ...

VERTICAL POWER TRANSISTOR HAVING HETEROJUNCTIONS

A vertical power transistor, including a semiconductor substrate, on which at least one first layer and one second layer are situated, the second layer being situated on the first layer, and the first layer including a first semiconductor material; and a plurality of trenches, which extend from an upper side of the second layer into the first layer. The first layer has a first doping, and each trench has a first region, which extends from the respective trench bottom to a first level. Each first region is filled with a second semiconductor material, which has a second doping. The first semiconductor material and the second semiconductor material are different. Each first region is connected electrically to the second layer. The second doping is higher than the first doping. Heterojunctions, which behave as unipolar, rectifying junctions, form between the first layer and each first region. 18-. (canceled)9. A vertical power transistor , comprising:a semiconductor substrate, on which at least one first layer and one second layer are situated, the second layer being situated on the first layer, and the first layer including a first semiconductor material; anda plurality of trenches which extend from an upper side of the second layer into the first layer, so that a respective trench bottom of each of the trenches is surrounded by the first layer; the first layer has a first doping, and each of the trenches has a first region which extends from the respective trench bottom to a first level, each of the first regions being filled with a second semiconductor material, which has a second doping;', 'the first semiconductor material and the second semiconductor material are different from one another;', 'each of the first regions is connected electrically to the second layer; and', 'the second doping being higher than the first doping, so that heterojunctions, which behave as unipolar, rectifying junctions, form between the first layer and each of the first regions., ' ...

HETEROJUNCTION DEVICES AND METHODS FOR FABRICATING THE SAME

Current conducting devices and methods for their formation are disclosed. Described are vertical current devices that include a substrate, an n-type material layer, a plurality of p-type gates, and a source. The n-type material layer disposed on the substrate and includes a current channel. A plurality of p-type gates are disposed on opposite sides of the current channel. A source is disposed on a distal side of the current channel with respect to the substrate. The n-type material layer comprises beta-gallium oxide. 1a substrate;an n-type material layer disposed on the substrate, wherein the n-type material layer includes a current channel;a plurality of p-type gates disposed on opposite sides of the current channel; anda source disposed on a distal side of the current channel with respect to the substrate,wherein the n-type material layer comprises beta-gallium oxide.. A vertical current conducting device, comprising: The present application relates generally to heterojunction devices and methods for fabricating the same.In the world of semiconductors, Silicon (Si) is the most widely used. It properties lends itself to use in digital logic, memory, RF, power switching and optoelectronics. However, Si has fundamental limitations. For instance, in power switching applications, the operating voltage is limited by the electric field strength at which breakdowns occurs (E). Eis directly related to the bandgap of the material. Si has an Eof approximate 0.3 MV/cm, which limits its use in power switching applications. β-GaO, however, has a larger bandgap of approximately 4.9 eV, and an Eof 8 MV/cm. This corresponds to a power figure of merit (using the Baliga figure of merit) of approximately 3,444 as compared to 1 for Si. While SiC and GaN offer higher bandgaps than Si, their respective power figures of merit are 160 and 870, far less than β-GaO. However, β-GaOis not without limitations. As is typical of oxide semiconductors, it is unlikely that p-type doping can be ...

Nitride semiconductor device

A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer of a first conductivity type; a second nitride semiconductor layer of a second conductivity type; an electron transport layer and an electron supply layer provided, in that order from a side on which the substrate is located, above the second nitride semiconductor layer and on an inner surface of a first opening; a gate electrode provided above the electron supply layer and covering the first opening; a source electrode provided in a second opening and connected to the second nitride semiconductor layer; a drain electrode; a third opening at an outermost edge part in a plan view of the substrate; and a potential fixing electrode provided in the third opening, the potential fixing electrode being connected to the second nitride semiconductor layer and in contact with neither the electron transport layer nor the electron supply layer.

Method of manufacturing a semiconductor device

A method for manufacturing a semiconductor device having an SiC-IGBT and an SiC-MOSFET in a single semiconductor chip, including forming a second conductive-type SiC base layer on a substrate, and selectively implanting first and second conductive-type impurities into surfaces of the substrate and base layer to form a collector region, a channel region in a surficial portion of the SiC base layer, and an emitter region in a surficial portion of the channel region, the emitter region serving also as a source region of the SiC-MOSFET.

LATCH-UP IMMUNIZATION TECHNIQUES FOR INTEGRATED CIRCUITS

In an integrated circuit supporting complementary metal oxide semiconductor (CMOS) integrated circuits, latch-up immunity is supported by surrounding a hot n-well with an n-well strap spaced from the hot n-well by a specified distance in accordance with design rules. The n-well strap is positioned between the hot n-well and other n-well or n-type diffusion structures. 1. An integrated circuit , comprising:a semiconductor substrate doped with a first conductivity type; a first region heavily doped with the second conductivity type, wherein the first region is connected to a supply node; and', 'a second region heavily doped with the first conductivity type, wherein the second region is connected to an integrated circuit pad;, 'a first semiconductor well doped with a second conductivity type within the semiconductor substrate and includinga second semiconductor well doped with the second conductivity type within the semiconductor substrate;a third region heavily doped with the second conductivity type within the second semiconductor well, wherein the third region is connected to a ground node;a third semiconductor well doped with the second conductivity type within the semiconductor substrate; anda fourth region heavily doped with the second conductivity type within the third semiconductor well, wherein the fourth region is connected to the integrated circuit pad through a resistor;wherein the third semiconductor well is positioned within the semiconductor substrate between the first semiconductor well and the second semiconductor well.2. The integrated circuit of claim 1 , wherein the third semiconductor well is laterally spaced from the first semiconductor well by a design specific distance between adjacent wells having a same conductivity type as specified by design rules for the integrated circuit.3. The integrated circuit of claim 1 , wherein the third semiconductor well is laterally spaced from the second semiconductor well by a design specific distance between ...

ELECTROSTATIC DISCHARGE PROTECTION SEMICONDUCTOR DEVICE

An ESD protection semiconductor device is disclosed. The ESD protection semiconductor device includes a substrate and a gate set disposed on the substrate. A plurality of source fins and a plurality of drain fins are formed in the substrate respectively at two sides of the gate set. At least a first doped fin is formed in the substrate at one side of the gate set the same as the source fins. A plurality of isolation structures are formed in one of the drain fins to define at least a second doped fin in the one of the drain fins. The source fins and the drain fins are of a first conductivity type. The first doped fin is of a second conductivity type that is complementary to the first conductivity type. The first doped fin and the second doped fin are electrically connected to each other. 1. An ESD protection semiconductor device , comprising:a substrate;a gate set disposed on the substrate;a plurality of source fins and a plurality of drain fins disposed in the substrate respectively at two sides of the gate set, wherein the source fins and the drain fins comprise a first conductivity type;at least a first doped fin disposed in the substrate at one side of the gate set the same as the source fins and being spaced apart from the source fins, wherein the first doped fin comprises a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other; anda plurality of isolation structures disposed in one of the drain fins to define at least a second doped fin in the one of the drain fins, wherein the second doped fin is electrically connected to the first doped fin.2. The ESD protection semiconductor device according to claim 1 , wherein the source fins are electrically connected to a ground pad claim 1 , and the drain fins are electrically connected to an IO pad.3. The ESD protection semiconductor device according to claim 1 , wherein the source fins and the drain fins extend along a first direction and are ...

IGBT Having a Barrier Region

An IGBT having a barrier region is presented. A power unit cell of the IGBT has at least two trenches that may both extend into the barrier region. The barrier region may be p-doped and vertically confined, i.e., in and against the extension direction, by means of the drift region. The barrier region can be electrically floating. 1. An IGBT , comprising:a semiconductor body coupled to a first load terminal and a second load terminal of the IGBT and comprising a drift region configured to conduct a load current between the first and the second load terminals, the drift region comprising dopants of a first conductivity type; a control trench having a control trench electrode and a further trench having a further trench electrode electrically coupled to the control trench electrode;', 'an active mesa comprising a source region with dopants of the first conductivity type and electrically connected to the first load terminal and a channel region with dopants of a second conductivity type, the channel region separating the source region and the drift region, wherein in the active mesa, at least a respective section of each of the source region, the channel region and the drift region are arranged adjacent to a sidewall of the control trench, and wherein the control trench electrode is configured to receive a control signal from a control terminal of the IGBT and to control the load current in the active mesa, the further trench electrode not being configured to control the load current; and', 'an electrically floating semiconductor barrier region in the semiconductor body and comprising dopants of the second conductivity type, the barrier region laterally overlapping with both the active mesa and a bottom of the further trench., 'a power unit cell comprising2. The IGBT of claim 1 , wherein at least one of:the power unit cell further comprises an inactive mesa arranged adjacent to the further trench, a transition between the first load terminal and the inactive mesa ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

A semiconductor device includes: a semiconductor base body where a second semiconductor layer is stacked on a first semiconductor layer, a trench is formed on a surface of the second semiconductor layer, and a third semiconductor layer which is formed of an epitaxial layer is formed in the inside of the trench; a first electrode; an interlayer insulation film which has a predetermined opening; and a second electrode, wherein metal is filled in the opening, the opening is disposed at a position avoiding a center portion of the third semiconductor layer, the second electrode is connected to the third semiconductor layer through the metal, and a surface of the center portion of the third semiconductor layer is covered by the interlayer insulation film. 1. A semiconductor device comprising:a semiconductor base body where a second semiconductor layer of a first conductive type is stacked on a first semiconductor layer of the first conductive type or a second conductive type, a trench having a predetermined depth is formed on a surface of the second semiconductor layer, and a third semiconductor layer of the second conductive type which is formed of a monocrystal epitaxial layer is formed in the inside of the trench;a first electrode which is positioned on a surface of the first semiconductor layer;an interlayer insulation film which is positioned on a surface of the second semiconductor layer and on a surface of the third semiconductor layer and has a predetermined opening formed within a region where at least the third semiconductor layer is formed as viewed in a plan view, the opening being filled with metal; anda second electrode which is positioned over the interlayer insulation film, whereinthe opening is disposed at a position avoiding a center portion of the third semiconductor layer as viewed in a plan view,the second electrode is connected to at least the third semiconductor layer through the metal filled in the opening, anda surface of the center portion of the ...

Edge termination designs for silicon carbide super-junction power devices

The subject matter disclosed herein relates to silicon carbide (SiC) power devices and, more specifically, to SiC super-junction (SJ) power devices. A SiC-SJ device includes a plurality of SiC semiconductor layers of a first conductivity-type, wherein a first and a second SiC semiconductor layer of the plurality of SiC semiconductor layers comprise a termination region disposed adjacent to an active region with an interface formed therebetween, an act wherein the termination region of the first and the second SiC semiconductor layers comprises a plurality of implanted regions of a second conductivity-type, and wherein an effective doping profile of the termination region of the first SiC semiconductor layer is different from an effective doping profile of the termination region of the second SiC semiconductor layer.

INSULATED GATE TYPE SEMICONDUCTOR DEVICE

An insulating gate type semiconductor device being capable of easily depleting an outer periphery region is provided. The insulating gate type semiconductor device includes: first to fourth outer periphery trenches formed in a front surface of a semiconductor substrate; insulating layers located in the outer periphery trenches; fifth semiconductor regions being of a second conductive type and formed in ranges exposed to bottom surfaces of the outer periphery trenches; and a connection region connecting the fifth semiconductor region exposed to the bottom surface of the second outer periphery trench to the fifth semiconductor region exposed to the bottom surface of the third outer periphery trench. A clearance between the second and third outer periphery trenches is wider than each of a clearance between the first and second outer periphery trenches and a clearance between the third and fourth outer periphery trenches. 1. An insulated gate type semiconductor device , comprising:a semiconductor substrate;a front surface electrode formed on a front surface of the semiconductor substrate; anda rear surface electrode formed on a rear surface of the semiconductor substrate;whereinthe insulated gate type semiconductor device is configured to switch current between the front surface electrode and the rear surface electrode,the insulated gate type semiconductor device further comprises:a first semiconductor region being of a first conductive type and connected to the front surface electrode;a second semiconductor region being of a second conductive type and in contact with the first semiconductor region;a third semiconductor region being of the first conductive type and separated from the first semiconductor region by the second semiconductor region;a plurality of gate trenches formed in the front surface of the semiconductor substrate and penetrating the second semiconductor region to reach the third semiconductor region;gate insulating films and gate electrodes located in ...

Integrated device having multiple transistors

An integrated device includes a semiconductor well formed in an epitaxial layer, and a guard ring formed in the epitaxial layer and surrounding the semiconductor well. The semiconductor well and the guard ring include a type of semiconductor different from that of the epitaxial layer. The integrated device also includes an insulating layer formed atop the guard ring, and multiple gate electrodes formed on a top surface of the insulating layer, overlapping the guard ring and surrounding the semiconductor well. The gate electrodes include a first gate electrode and a second gate electrode separated by a gap. An intersecting line between the top surface of the insulating layer and a side wall of the first gate electrode partially overlaps an area that is defined based on an intersecting line between the top surface of the insulating layer and a side wall of the second gate electrode above the guard ring.

Semiconductor device and method of manufacturing semiconductor device

A semiconductor device includes a termination trench surrounding a region in which a plurality of gate trenches is provided; a p-type lower end region being in contact with a lower end of the termination trench; a p-type outer circumference region being in contact with the termination trench from an outer circumferential side and exposed on a surface of the semiconductor device; a plurality of guard ring regions of a p-type provided on an outer circumferential side of the p-type outer circumference region and exposed on the surface; and an n-type outer circumference region separating the p-type outer circumference region from the guard ring regions and separating the guard ring regions from each another.

POWER SEMICONDUCTOR DEVICE WITH THICK TOP-METAL-DESIGN AND METHOD FOR MANUFACTURING SUCH POWER SEMICONDUCTOR DEVICE

The present application contemplates a method for manufacturing a power semiconductor device. The method comprises: providing a wafer of a first conductivity type, the wafer having a first main side and a second main side opposite to the first main side, and the wafer including an active cell area, which extends from the first main side to the second main side, in a central part of the wafer and a termination area surrounding the active cell area in an orthogonal projection onto a plane parallel to the first main side; forming a metallization layer on the first main side to electrically contact the wafer in the active cell area, wherein the surface of the metallization layer, which faces away from the wafer, defines a first plane parallel to the first main side; forming an isolation layer on the first main side in the termination area, wherein the surface of the isolation layer facing away from the wafer defines a second plane parallel to the first main side; after the step of forming the metallization layer and after the step of forming the isolation layer, mounting the wafer with its first main side to a flat surface of a chuck; and thereafter thinning the wafer from its second main side by grinding while pressing the second main side of the wafer onto a grinding wheel by applying a pressure between the chuck and the grinding wheel, wherein the first plane is further away from the wafer than a third plane, which is parallel to the second plane and arranged at a distance of 1 μm from the second plane in a direction towards the wafer. 1. A method for manufacturing a power semiconductor device , the method comprising the following steps:providing a wafer of a first conductivity type, the wafer having a first main side and a second main side opposite to the first main side, and the wafer including an active cell area, which extends from the first main side to the second main side, in a central part of the wafer and a termination area surrounding the active cell area ...

SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS INCLUDING THE SAME

A semiconductor device includes a plurality of transistor components disposed on a semiconductor substrate, and a guard ring disposed on the semiconductor substrate surrounding the transistor components. The guard ring includes a plurality of fin structures disposed in parallel on the semiconductor substrate, a plurality of first conductive connection members disposed on the fin structures and connecting at least two fin structures, and a plurality of second conductive connection members connecting at least two first conductive connection members. The first conductive connection members and the second conductive connection members are formed as one structure. 1. A semiconductor device comprising:a plurality of transistor components disposed on a semiconductor substrate; a plurality of fin structures disposed in parallel on the semiconductor substrate;', 'a plurality of first conductive connection members disposed on the fin structures and connecting at least two fin structures; and', 'a plurality of second conductive connection members connecting at least two first conductive connection members,', 'wherein the first conductive connection members and the second conductive connection members are formed as one structure., 'a guard ring disposed on the semiconductor substrate surrounding the transistor components, wherein the guard ring comprises2. The semiconductor device according to claim 1 , wherein the first conductive connection members and the second conductive connection members are formed in a mesh configuration.3. The semiconductor device according to claim 1 , wherein the second conductive connection member is perpendicular to the first conductive connection member.4. The semiconductor device according to claim 1 , wherein the second conductive connection members have a same width claim 1 , and wherein adjacent second conductive connection members are spaced apart by a same distance.5. The semiconductor device according to claim 1 , wherein the first ...

SEMICONDUCTOR DEVICE

A semiconductor device includes a semiconductor substrate in which an active region and an edge termination region are defined, a semiconductor element formed in the active region, and first to fourth P layers formed in a region spanning from an edge portion of the active region to the edge termination region in the surface of the semiconductor substrate. The first to fourth P layers respectively have surface concentrations P(1) to P(4) that decrease in this order, bottom-end distances D(1) to D(4) that increase in this order, and distances B(1) to B(4) to the edge of the semiconductor substrate that increase in this order. The surface concentration P(4) is 10 to 1000 times the impurity concentration of the semiconductor substrate, and the bottom-end distance D(4) is in the range of 15 to 30 μm. 1. A semiconductor device comprising:a semiconductor substrate of a first conductivity type in which an active region and an edge termination region that is spaced from and encloses said active region are defined;a semiconductor element formed in said active region; anda plurality of impurity layers of a second conductivity type that are formed at least partly overlapping one another in a region spanning from an edge portion of said active region to said edge termination region in a surface of said semiconductor substrate,wherein, for an arbitrary pair of adjacent ith and an i+1th impurity layers among said plurality of impurity layers, P(i)>P(i+1), D(i) Подробнее

Semiconductor device and production method for semiconductor device

Depth of a termination p base region provided in a termination portion of an active region close to an edge termination structure portion is more than depth of a p-type base region provided inside the termination p base region. An n-type high-concentration region is provided from one main surface of the semiconductor substrate in the entire surface layer of one surface of a semiconductor substrate within a depth of 20 μm or less below the bottom of the termination p base region. Ratio of the impurity concentration n 1 of the n-type high-concentration region ( 1 c) to the impurity concentration n 2 of an n − drift region satisfies 1.0<n 1 /n 2 ≦5.0. Reverse leakage current when operation temperature of an element is high can be reduced and trade-off between on-state voltage and switching loss can be improved. Rising peak voltage of collector voltage when a semiconductor device is off is reduced.

SEMICONDUCTOR DEVICE WITH FIELD THRESHOLD MOSFET FOR HIGH VOLTAGE TERMINATION

This invention discloses a semiconductor power device disposed in a semiconductor substrate comprising a lightly doped layer formed on a heavily doped layer and having an active cell area and an edge termination area. The edge termination area comprises a plurality P-channel MOSFETs. By connecting the gate to the drain electrode, the P-channel MOSFET transistors formed on the edge termination are sequentially turned on when the applied voltage is equal to or greater than the threshold voltage Vt of the P-channel MOSFET transistors, thereby optimizing the voltage blocked by each region. 1. A semiconductor power device disposed in a semiconductor substrate comprising a lightly doped layer formed on top of a heavily doped layer and having an active cell area and an edge termination area wherein:said edge termination area comprises a plurality of termination trenches formed in said lightly doped layer and lined with a dielectric layer and filled with a conductive material therein; anda plurality of series connected MOSFET transistors, each of which comprises a trench gate region, a drain and source regions disposed on two opposite sides of each of said termination trenches, with said conductive material in each of said termination trenches functions as a trench gate for each of said MOSFET transistors, wherein each trench gate is electrically connected to said drain region.2. The semiconductor power device of wherein:said plurality of MOSFET transistors comprising a plurality of P-channel MOSFET transistors.3. The semiconductor power device of wherein:one of the plurality of MOSFET transistors is turned on when the applied voltage is greater than or equal to a threshold voltage of said MOSFET transistor, wherein said threshold voltage ranging from 0.5 to 80 volts.4. The semiconductor power device of wherein:said edge termination has a width ranging from 5 microns to 250 microns to form between 1 to 25 termination trenches in said edge termination.5. The semiconductor ...

VERTICAL SEMICONDUCTOR DEVICE

In a structure which secures a breakdown voltage of a semiconductor device by providing a channel stop region to a boundary part between an outer circumferential side surface and a front surface of the semiconductor substrate, the channel stop region is formed by a plurality of regions having different impurity concentrations. Upon this occasion, the channel stop region satisfies following relations: the impurity concentrations of the plurality of the regions are higher for regions closer to the outer circumferential side surface of the semiconductor substrate; and a depth of a high-impurity-concentration region is equal to or deeper than a depth of a low-impurity-concentration region. Electric field concentration is alleviated around the channel stop region and a breakdown voltage of the semiconductor substrate increases. 1. A semiconductor device comprising:a semiconductor substrate;a front-surface electrode disposed on a front surface of the semiconductor substrate; anda back-surface electrode disposed on a back surface of the semiconductor substrate;whereina semiconductor structure for current control is provided in a center region of the semiconductor substrate, andan extending structure, and a channel stop region, and a stop electrode are provided in a peripheral region of the semiconductor substrate,the semiconductor structure for current control controls a current flowing between the front-surface electrode and the back-surface electrode,the extending structure allows a depletion layer to extend toward an outer circumferential side surface of the semiconductor substrate when the current is not flowing between the front-surface electrode and the back-surface electrode,the channel stop region prevents the depletion layer from extending toward the outer circumferential side surface to reach the outer circumferential side surface when the current is not flowing between the front-surface electrode and the back-surface electrode,the channel stop region satisfies ...

Schottky barrier diode formed with nitride semiconductor substrate

An SBD is obtained by forming, on a front surface of a substrate in which a first nitride semiconductor layer and a second nitride semiconductor layer are laminated, an anode electrode configured to make Schottky contact and a cathode electrode configured to make Ohmic contact. The anode electrode is made to have a mixture of a portion that is in direct contact with the second nitride semiconductor layer and a portion that is in contact with the second nitride semiconductor layer via a fourth nitride semiconductor layer and a third nitride semiconductor layer. Using a p-type nitride semiconductor as the fourth layer makes it possible to suppress the leakage current. Using, as the third layer, a nitride semiconductor that is wider in band gap than the second nitride semiconductor layer makes it possible to keep down the lowest value of forward voltage at which a forward current flows.

SEMICONDUCTOR DEVICE HAVING INDUCTOR

A semiconductor device includes first and second winding portions disposed in a first level of an insulating layer and surrounding a center region thereof. Each of the winding portions includes conductive lines arranged from the inside to the outside. First and second extending conductive lines are disposed in the first level of the insulating layer. A third extending conductive line is disposed in a second level of the insulating layer. The first extending conductive line is coupled between the innermost conductive line of the second winding and the third extending conductive line. The second extending conductive line is coupled between the innermost conductive line of the first winding portion and the third extending conductive line. The first extending conductive line and the third extending conductive line coupled thereto are arranged in a helix or a spiral spatial configuration. 1. A semiconductor device , comprising:an insulating layer disposed over a substrate, wherein the insulating layer has a center region;a first winding portion and a second winding portion electrically connected to the first winding portion, disposed in a first level of the insulating layer and surrounding the center region, wherein each of the first winding portion and the second winding portion comprises a plurality of conductive lines arranged from the inside to the outside;a first extending conductive line and a second extending conductive line partially surrounding the first extending conductive line, disposed in the first level of the insulating layer, wherein the first winding portion and the second winding portion surround the first extending conductive line and the second extending conductive line; anda third extending conductive line disposed in a second level of the insulating layer and surrounding the center region,wherein the extending conductive lines and the conductive lines have a first end and a second end, wherein the first end and the second end of the first extending ...

SILICON CARBIDE SEMICONDUCTOR DEVICE

A silicon carbide semiconductor device has a silicon carbide substrate and an insulating film. The silicon carbide substrate includes a termination region having a peripheral edge, and an element region surrounded by the termination region. The insulating film is provided on the termination region. The termination region includes a first impurity region having a first conductivity type, and a field stop region having the first conductivity type, being in contact with the first impurity region and having a higher impurity concentration than the first impurity region. The field stop region is at least partially exposed at the peripheral edge. 1. A silicon carbide semiconductor device comprising:a silicon carbide substrate including a termination region having a peripheral edge, and an element region surrounded by the termination region; andan insulating film provided on the termination region, a first impurity region having a first conductivity type, and', 'a field stop region having the first conductivity type, being in contact with the first impurity region and having a higher impurity concentration than the first impurity region,, 'the termination region including'}the field stop region being at least partially exposed at the peripheral edge.2. The silicon carbide semiconductor device according to claim 1 , wherein{'sup': 16', '−3', '21', '−3, 'the impurity concentration in the field stop region is not less than 1×10cmand not more than 1×10cm.'}3. The silicon carbide semiconductor device according to claim 1 , whereinthe termination region includes a guard ring region surrounded by the field stop region and having a second conductivity type different from the first conductivity type.4. The silicon carbide semiconductor device according to claim 1 , whereinthe insulating film is a thermal oxide film.5. The silicon carbide semiconductor device according to claim 1 , whereinthe first conductivity type is n type.6. The silicon carbide semiconductor device according to ...

TRENCH-BASED POWER SEMICONDUCTOR DEVICES WITH INCREASED BREAKDOWN VOLTAGE CHARACTERISTICS

Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed. 1. A semiconductor device comprising:a plurality of primary trenches extending into the semiconductor region, each of the plurality of trenches having a first end, a second end, and opposing sidewalls lined with a dielectric layer, each trench further having a shield electrode;an end trench extending into the semiconductor region and disposed adjacent to and spaced from the first ends of the primary trenches, the end trench having opposing sidewalls lined with a dielectric layer and an electrode disposed in the end trench; anda gap region disposed between the end trench and the first ends of the primary trenches, the gap region being at a floating potential.2. The semiconductor device of claim 1 , wherein the electrode disposed in the end trench is electrically coupled to a conductive layer to receive a potential.3. The semiconductor device of claim 2 , a well region of a first conductivity type disposed in the semiconductor region and in the gap region claim 2 , the well being at a floating potential.4. The semiconductor device of claim 1 , wherein the electrode disposed in the end trench is at a floating potential.5. The semiconductor device of claim 4 , a well region of a first conductivity type disposed in the semiconductor region and in the gap region claim 4 , the well being at a floating potential.6. The semiconductor device of claim 1 , wherein the end trench fully encircle the plurality of primary trenches.7. The semiconductor device of claim 1 , wherein each primary trench further has a gate electrode vertically stacked on the shield electrode claim 1 , the gate and shield electrodes being insulated from each other. This application is a continuation of U.S. patent application Ser. No. 14/670,139, filed Mar. 26, 2015, which is a continuation of U.S. patent application Ser. No. 13/667,319, filed Nov. 2, 2012 (now U.S. Pat. No. 9,293, ...

SURFACE DEVICES WITHIN A VERTICAL POWER DEVICE

A semiconductor device comprises a vertical power device, such as a superjunction MOSFET, an IGBT, a diode, and the like, and a surface device that comprises one or more lateral devices that are electrically active along a top surface of the semiconductor device. 1. A semiconductor device comprising:a surface device; and,a vertical power device that is controlled by the surface device.2. The semiconductor device of further comprising:an insulator; and,the surface device and the vertical power device separated by the insulator.3. The semiconductor device of further comprising:epitaxial silicon;the surface device formed on the epitaxial silicon; and,the vertical power device formed on the epitaxial silicon as a superjunction metal oxide semiconductor field effect transistor.4. The semiconductor device of further comprising:the vertical power device including one or more power devices in which subsets of the one or more power devices are connected in parallel.5. The semiconductor device of further comprising:a wafer on which the semiconductor device is formed and which includes a front-side and a back-side;a first metal layer on the front-side of the wafer;a second metal layer on the back-side of the wafer; and,the vertical power device configured so that power flows between the first metal layer and the second metal layer.6. The semiconductor device of wherein the surface device further comprises:a set of analog circuits and a set of digital circuits formed by a set of metal oxide semiconductor regions.7. The semiconductor device of wherein the set of metal oxide semiconductor regions further comprises:a medium voltage N-type metal oxide semiconductor region;a medium voltage P-type metal oxide semiconductor region;a low voltage N-type metal oxide semiconductor region; and,a low voltage P-type metal oxide semiconductor region.8. The semiconductor device of further comprising:each region of the set of metal oxide semiconductor regions including a set of transistors ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device includes a first trench gate electrode and a second trench gate electrode which are electrically connected to a gate electrode, and a third trench gate electrode and a fourth trench gate electrode which are electrically connected to an emitter electrode. A plurality of p type semiconductor regions are formed in a part of a semiconductor layer between the first trench gate electrode and the second trench gate electrode. The plurality of p type semiconductor regions are arranged to be spaced apart from each other along an extending direction of the first trench gate electrode when seen in a plan view. 110-. (canceled)11. A semiconductor device comprising:a semiconductor substrate having a first main surface and a second main surface on an opposite side of the first main surface;a first semiconductor layer of a first conductivity type formed in the semiconductor substrate;a second semiconductor layer of a second conductivity type different from the first conductivity type formed in the semiconductor substrate positioned on a side close to the second main surface relative to the first semiconductor layer;a first trench portion which is formed in the first semiconductor layer from the first main surface and extends in a first direction when seen in a plan view;a second trench portion which is formed in the first semiconductor layer from the first main surface, is arranged to be spaced apart from the first trench portion, and extends in the first direction;a third trench portion which is formed in the first semiconductor layer from the first main surface, is arranged on an opposite side of the first trench portion with the second trench portion interposed therebetween, and extends in the first direction;a fourth trench portion which is formed in the first semiconductor layer from the first main surface, is arranged on an opposite side of the second trench portion with the third trench portion interposed therebetween, and extends in the first ...

SEMICONDUCTOR DEVICE WITH VERTICALLY INTEGRATED PHEMTS

The present disclosure relates to a semiconductor device with vertically integrated pseudomorphic high electron mobility transistors (pHEMTs). The disclosed semiconductor device includes a substrate, a lower pHEMT structure with a lower pHEMT, an isolation layer, and an upper pHEMT structure with an upper pHEMT. The lower pHEMT structure is formed over the substrate and has a first region and a second region that is laterally disposed with the first region. The lower pHEMT is formed in or on the second region. The isolation layer resides over the first region. The upper pHEMT structure is formed over the isolation layer and does not extend over the second region. Herein, the isolation layer separates the lower pHEMT structure from the upper pHEMT structure such that the lower pHEMT and the upper pHEMT operate independently from each other. 1. An apparatus comprising:a substrate; the lower pHEMT structure comprises a lower doping layer doped with at least one n-type dopant; and', 'a lower pHEMT is formed in or on the second region;, 'a lower pseudomorphic high electron mobility transistor (pHEMT) structure formed over the substrate and having a first region and a second region that is laterally disposed with the first region, whereinan isolation layer residing over the first region; and the upper pHEMT structure comprises an upper doping layer doped with at least one n-type dopant;', 'an upper pHEMT is formed in or on the upper pHEMT structure; and', 'the isolation layer separates the lower pHEMT structure from the upper pHEMT structure such that the lower pHEMT and the upper pHEMT operate independently from each other., 'an upper pHEMT structure formed over the isolation layer and not extending over the second region, wherein2. The apparatus of wherein the isolation layer does not extend over the second region.3. The apparatus of wherein the isolation layer is formed of aluminum gallium arsenide (AlGaAs) claim 1 , wherein x has a value between 0 and 1 representing ...

SEMICONDUCTOR DEVICES AND METHOD OF MAKING THE SAME

In one embodiment, the semiconductor devices relate to using one or more super-junction trenches for termination. 1. A semiconducting device comprising:a semiconductor substrate of a first conductivity type;a first layer of the first conductivity type overlying the semiconductor substrate;an active region; and [ a first semiconducting region having a second conductivity type;', 'a second semiconducting region adjacent to the first semiconducting region, wherein the second semiconducting region has a third conductivity type that is different than the second conductivity type;', 'a first buffer region adjacent to the second semiconducting region;', 'a third semiconducting region adjacent to the first buffer region, wherein the third semiconducting region has the third conductivity type; and', 'a fourth semiconducting region adjacent to the third semiconducting region, wherein the fourth semiconducting region has the second conductivity type; and, 'two or more first segments each comprising a first super-junction trench, wherein the first super-junction trench comprises, 'two or more second segments each comprising a fifth semiconducting region having the first conductivity type,', 'wherein the first segments and the second segments are alternatively arranged to form the ring structure., 'one or more ring structures surrounding the active region, the ring structures each comprising2. The semiconductor device of claim 1 , wherein the first conductivity type is a n-type conductivity and the second conductivity type is a n-type conductivity.3. The semiconductor device of claim 1 , wherein the third conductivity type is a p-type conductivity.4. The semiconductor device of claim 1 , wherein the first buffer region comprises a dielectric material and at least one void.5. The semiconducting device of claim 1 , wherein the second segments each further comprise a sixth semiconducting region having the third conductivity type claim 1 , wherein the sixth semiconducting region is ...

MOSFET DEVICE OF SILICON CARBIDE HAVING AN INTEGRATED DIODE AND MANUFACTURING PROCESS THEREOF

An integrated MOSFET device is formed in a body of silicon carbide and with a first type of conductivity. The body accommodates a first body region, with a second type of conductivity; a JFET region adjacent to the first body region; a first source region, with the first type of conductivity, extending into the interior of the first body region; an implanted structure, with the second type of conductivity, extending into the interior of the JFET region. An isolated gate structure lies partially over the first body region, the first source region and the JFET region. A first metallization layer extends over the first surface and forms, in direct contact with the implanted structure and with the JFET region, a JBS diode. 1. An integrated metal-oxide semiconductor field effect transistor (MOSFET) device comprising:a body, of silicon carbide and with a first type of conductivity, having a first surface and a second surface;a first body region with a second type of conductivity, extending from the first surface into the body;a junction field effect transistor (JFET) region adjacent to the first body region and facing the first surface;a first source region, with the first type of conductivity, extending from the first surface into the first body region;an isolated gate structure extending over the first surface and lying partially over the first body region, the first source region and the JFET region;an implanted structure, with the second type of conductivity, extending into the JFET region from the first surface; anda first metallization layer extending over the first surface, the first metallization layer being in direct contact with the implanted structure and with the JFET region and forming a Junction-Barrier Schottky (JBS) diode that includes the implanted structure and the JFET region.2. The device according to claim 1 , furthermore comprising a second metallization layer extending on the second surface of the body.3. The device according to claim 1 , ...

POWER SCHOTTKY DIODES HAVING CLOSELY-SPACED DEEP BLOCKING JUNCTIONS IN A HEAVILY-DOPED DRIFT REGION

A Schottky diode includes a drift region, a channel in an upper portion of the drift region, and first and second adjacent blocking junctions in the upper portion of the drift region that define the channel therebetween. The drift region and channel are doped with dopants having a first conductivity type, and the first and second blocking junctions doped with dopants having a second conductivity type that is opposite the first conductivity type. The blocking junctions extend at least one micron into the upper portion of the drift region and are spaced apart from each other by less than 3.0 microns. 1. A Schottky diode , comprising:a drift region having an upper portion and a lower portion, the drift region doped with dopants having a first conductivity type;a channel in the upper portion of the drift region, the channel having the first conductivity type;a first blocking junction and a second blocking junction adjacent the first blocking junction in the upper portion of the drift region, the first and second blocking junctions defining the channel therebetween, the first and second blocking junctions doped with dopants having a second conductivity type that is opposite the first conductivity type, the first and second blocking junctions extending at least one micron into the upper portion of the drift region and being spaced apart from each other by less than 3.0 microns;a first contact on the upper portion of the drift region; anda second contact on the lower portion of the drift region and vertically spaced apart from the first contact.2. The Schottky diode of claim 1 , wherein a doping concentration of the drift region is greater than 1.5×10/cm.3. The Schottky diode of claim 2 , wherein a doping concentration of the drift region is less than 5×10/cm.4. The Schottky diode of claim 3 , wherein the first and second blocking junctions each have a depth from the upper surface of the drift region of between 1.0 microns and 1.5 microns.5. The Schottky diode of claim 4 , ...

CHIP PARTS AND METHOD FOR MANUFACTURING THE SAME, CIRCUIT ASSEMBLY HAVING THE CHIP PARTS AND ELECTRONIC DEVICE

A chip part according to the present invention includes a substrate having a penetrating hole, a pair of electrodes formed on a front surface of the substrate and including one electrode overlapping the penetrating hole in a plan view and another electrode facing the one electrode, and an element formed on the front surface side of the substrate and electrically connected to the pair of electrodes. 1. A bidirectional Zener diode chip , comprising:a semiconductor substrate of a first conductivity type;an insulating film which covers a front surface of the semiconductor substrate;a first diffusion region of a second conductivity type formed in the semiconductor substrate and exposed at the front surface of the semiconductor substrate;a second diffusion region of the second conductivity type formed in the semiconductor substrate across an interval from the first diffusion region and exposed at the front surface of the semiconductor substrate;contact holes in the insulating film for selectively exposing the first diffusion region and the second diffusion region through the insulating film;a first electrode formed on the front surface of the semiconductor substrate and connected to the first diffusion region; anda second electrode formed on the front surface of the semiconductor substrate and connected to the second diffusion region,wherein the first electrode includes a plurality of first extraction electrodes which are defined to cover the first diffusion region,wherein the second electrode includes a plurality of second extraction electrodes which are defined to cover the second diffusion region along the second extraction electrodes extending parallel to the first extraction electrodes in a lengthwise direction as viewed from a plan view,wherein the plurality of first extraction electrodes and the plurality of second extraction electrodes are defined in a comb-toothed shape engaging with each other,wherein a shape of the contact holes is an elongated shape in the ...

SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME

The semiconductor device includes a substrate, a fin structure, a source/drain region, and a gate structure. The fin structure includes a first-stage fin region, a second-stage fin region, and a third-stage fin region. The second-stage fin region is under the first-stage fin region. The third-stage fin region is under the second-stage fin region. The source/drain region is on a top surface of the second-stage fin region. The gate structure is over the first-stage fin region and wraps around a top surface and sidewalls of the first-stage fin region. The top surface of the second-stage fin region is lower than the top surface of the first-stage fin region. A width of the third-stage fin region is greater than a width of the second-stage fin region, and the width of the second-stage fin region is substantially the same as a width of the first-stage fin region. 1. A semiconductor device , comprising:a substrate; a first-stage fin region;', 'a second-stage fin region under the first-stage fin region; and', 'a third-stage fin region under the second-stage fin region;, 'a fin structure on the substrate, comprisinga source/drain region on a top surface of the second-stage fin region; anda gate structure over the first-stage fin region, configured to wrap around a top surface and sidewalls of the first-stage fin region, wherein the top surface of the second-stage fin region is lower than the top surface of the first-stage fin region; andwherein a width of the third-stage fin region is greater than a width of the second-stage fin region, and the width of the second-stage fin region is substantially the same as a width of the first-stage fin region.2. The semiconductor device of claim 1 , wherein a width of the first-stage fin region is between about 3 nm and about 10 nm claim 1 , a width of the second-stage fin region is between about 5 nm and about 10 nm claim 1 , and a width of the third-stage fin region is between about 30 nm and about 80 nm.3. The semiconductor device of ...

Schottky Diode and Method of Manufacturing the Same

A Schottky diode includes a drift region of a first conductive type formed at a surface portion of a substrate, an insulating layer disposed on the substrate and having an opening exposing a portion of the drift region, and a titanium silicide layer disposed on the portion of the drift region exposed by the opening. 1. A Schottky diode comprising:a drift region of a first conductive type formed at a surface portion of a substrate;an insulating layer disposed on the substrate, the insulating layer having an opening exposing a portion of the drift region; anda titanium silicide layer disposed on the portion of the drift region exposed by the opening.2. The Schottky diode of claim 1 , further comprising a guard ring of a second conductive type disposed under an edge portion of the titanium silicide layer.3. The Schottky diode of claim 1 , further comprising:a landing pad disposed on the titanium silicide layer and the insulating layer;a second insulating layer disposed on the landing pad;a metal wiring disposed on the second insulating layer; andat least one via contact connecting the landing pad with the metal wiring.4. The Schottky diode of claim 3 , further comprising a contact pad disposed between the titanium silicide layer and the landing pad.5. The Schottky diode of claim 4 , wherein the contact pad extends along an upper surface of the titanium silicide layer and an inner side surface of the opening.6. The Schottky diode of claim 1 , further comprising:a titanium layer disposed on an inner side surface of the opening; anda titanium nitride layer disposed on the titanium silicide layer and the titanium layer.7. A method of manufacturing a Schottky diode claim 1 , the method comprising:forming a drift region of a first conductive type at a surface portion of a substrate;forming an insulating layer on the substrate, the insulating layer having an opening exposing a portion of the drift region; andforming a titanium silicide layer on the portion of the drift region ...

TRANSISTOR

A transistor includes: a semiconductor substrate; a plurality of gate electrodes, a plurality of source electrodes, and a plurality of drain electrodes on the semiconductor substrate; a drain pad on the semiconductor substrate and connected to the plurality of drain electrodes; a metal wiring on the semiconductor substrate and arranged spaced apart from, adjacent to and parallel to the drain pad; and a ground pad on the semiconductor substrate and connected to both ends of the metal wiring. 1. A transistor comprising:a semiconductor substrate;a plurality of gate electrodes, a plurality of source electrodes, and a plurality of drain electrodes on the semiconductor substrate;a drain pad on the semiconductor substrate and connected to the plurality of drain electrodes;a metal wiring on the semiconductor substrate and arranged spaced apart from, adjacent to and parallel to the drain pad; anda ground pad on the semiconductor substrate and connected to both ends of the metal wiring.2. The transistor of claim 1 , wherein the entire drain pad faces the metal wiring to constitute a capacitor.3. The transistor of claim 1 , wherein a ground potential is applied to the ground pad.4. The transistor of claim 3 , further comprising a wire or a via hole inside the semiconductor substrate claim 3 , wherein the ground potential is applied to the ground pad using the wire or the via hole.5. The transistor of claim 1 , wherein a distance between the drain pad and the metal wiring is 100 microns or less.6. The transistor of claim 1 , further comprising a resistor connected between the metal wiring and the ground pad.7. The transistor of claim 6 , wherein the resistor is an ion implantation resistor claim 6 , a film resistor or a wire resistor.8. The transistor of claim 1 , further comprising a guard ring on the semiconductor substrate and surrounding the plurality of gate electrodes claim 1 , the plurality of source electrodes and the plurality of drain electrodes claim 1 ,wherein the ...