FET DEVICE INCLUDING AN INGAAS CHANNEL AND METHOD OF MANUFACTURING SAME

Semiconductor devices and method of manufacturing them

Current aperture vertical electron transistors

NITRIDE-BASED TRANSISTOR HAVING NITRIDE-BASED GATE DIELECTRIC LAYER

An embodiment of the present disclosure provides a nitride-based transistor which is capable of improving device reliability due to a gate dielectric layer. According to an embodiment of the present invention, a nitride-based transistor comprises: an n-type doped nitride-based first semiconductor pattern layer; a p-type doped nitride-based second semiconductor pattern layer which is disposed under the first semiconductor pattern layer so as to overlap a portion of the first semiconductor pattern layer; and a nitride-based gate dielectric layer and a gate electrode layer which are sequentially disposed on the first semiconductor pattern layer so as to cover the first semiconductor pattern layer which overlaps at least the second semiconductor pattern layer. When a voltage which is equal to or greater than a threshold voltage is applied to the gate electrode layer, a channel layer is formed by overcoming a depletion layer which is formed inside the first semiconductor pattern layer. COPYRIGHT ...

SEMICONDUCTOR STACKED BODY, METHOD FOR MANUFACTURING SAME, AND SEMICONDUCTOR ELEMENT

... [Problem] To provide a semiconductor stacked body having a low electric resistance in the thickness direction, a method for manufacturing the semiconductor stacked body, and a semiconductor element including the semiconductor stacked body. [Solution] A semiconductor stacked body (1) is provided, including a Ga2O3 substrate (2) having, as a principal plane, a plane on which oxygen atoms are arranged in a hexagonal lattice, an AIN buffer layer (3) formed on the Ga2O3 substrate (2), and a nitride semiconductor layer (4) formed on the AIN buffer layer (3).

Semiconductor structures and methods for multi-level work function

Semiconductor devices and methods for forming semiconductor devices are provided. A vertical channel structure extends from a substrate and is formed as a channel between a source region and a drain region. A first metal gate surrounds a portion of the vertical channel structure and has a gate length. The first metal gate has a first gate section with a first workfunction and a first thickness. The first metal gate also has a second gate section with a second workfunction and a second thickness. The first thickness is different from the second thickness, and the sum of the first thickness and the second thickness is equal to the gate length. A ratio of the first thickness to the second thickness is chosen to achieve a desired threshold voltage level for the semiconductor device.

Semiconductor Device and Method of Manufacturing the Same

A semiconductor device comprises a semiconductor body of a first semiconductor material, wherein at least a part of the semiconductor body constitutes a drift zone of a first conductivity type. The semiconductor device further comprises a channel layer structure comprising a semiconductor heterojunction between first and second semiconductor layers electrically coupled to the drift zone. The first and second semiconductor layers include semiconductor materials that are different to the first semiconductor material.

III-nitride semiconductor device with trench structure

A III-nitride trench device has a vertical conduction region with an interrupted conduction channel when the device is not on, providing an enhancement mode device. The trench structure may be used in a vertical conduction or horizontal conduction device. A gate dielectric provides improved performance for the device by being capable of withstanding higher electric field or manipulating the charge in the conduction channel. A passivation of the III-nitride material decouples the dielectric from the device to permit lower dielectric constant materials to be used in high power applications.

VeSFET Chemical Sensor And Methods Of Use Thereof

Aspects of the invention are directed to chemical and biological molecule sensing devices, methods of fabricating the chemical sensor devices, and methods of using those devices to detect chemical and biological molecules. The chemical sensor device may comprise a chemically-sensitive vertical slit field effect transistor (VeSFET) with a chemical recognition element attached to a gate structure and/or a channel of the VeSFET. The recognition element may be capable of binding to a chemical of interest such that the binding of the chemical to the recognition element results in a modification of current flow of the VeSFET, resulting in a detectable signal. The chemical sensor device may further comprise an amplifier configured to receive the detectable signal and produce an amplified signal, and an analog-to-digital converter (ADC) configured to receive the amplified signal and to produce a digital signal that represents the amplified signal.

THREE DIMENSIONAL VERTICALLY STRUCTURED ELECTRONIC DEVICES

An apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate including a first semiconductor material, an array of three dimensional (3D) structures above the substrate, a sidewall heterojunction layer positioned on at least one vertical sidewall of each 3D structure, and an isolation region positioned between the 3D structures. Each 3D structure includes the first semiconductor material. The sidewall heterojunction layer includes a second semiconductor material, where the first and second semiconductor material have different bandgaps.

Nanowire and larger GaN based HEMTS

Nanowire and larger, post-based HEMTs, arrays of such HEMTs, and methods for their manufacture are provided. In one embodiment, a HEMT can include a III-N based core-shell structure including a core member (e.g., GaN), a shell member (e.g., AlGaN) surrounding a length of the core member and a two-dimensional electron gas (2-DEG) at the interface therebetween. The core member including a nanowire and/or a post can be disposed over a doped buffer layer and a gate material can be disposed around a portion of the shell member. Exemplary methods for making the nanowire HEMTs and arrays of nanowire HEMTs can include epitaxially forming nanowire(s) and epitaxially forming a shell member from each formed nanowire. Exemplary methods for making the post HEMTs and arrays of post HEMTs can include etching a III-N layer to form III-N post(s) followed by formation of the shell member(s).

SEMICONDUCTOR DEVICE

A semiconductor device includes a first nitride semiconductor layer, a source electrode on the first nitride semiconductor layer, a drain electrode on the first nitride semiconductor layer, a gate electrode on the first nitride semiconductor layer and between the source electrode and the drain electrode, a gate field plate electrode that is separated from the first nitride semiconductor layer, and includes one end in direct contact with the gate electrode, and the other end positioned between the gate electrode and the drain electrode, a first interlayer insulating film that is separated from the gate electrode and is between the gate field plate electrode and the first nitride semiconductor layer, and a second interlayer insulating film that is between the gate electrode and the first interlayer insulating film and has a dielectric constant higher than a dielectric constant of the first interlayer insulating film. 1. A semiconductor device comprising:a first nitride semiconductor layer;a source electrode on the first nitride semiconductor layer;a drain electrode on the first nitride semiconductor layer;a gate electrode on the first nitride semiconductor layer and between the source electrode and the drain electrode;a gate field plate electrode that is separated from the first nitride semiconductor layer, and includes one end in direct contact with the gate electrode, and the other end positioned between the gate electrode and the drain electrode;a first interlayer insulating film that is separated from the gate electrode and is between the gate field plate electrode and the first nitride semiconductor layer; anda second interlayer insulating film that is between the gate electrode and the first interlayer insulating film and has a dielectric constant higher than a dielectric constant of the first interlayer insulating film.2. The device according to claim 1 , wherein the first interlayer insulating film is in direct contact with the gate field plate electrode and ...

Vertical Semiconductor Device Structure and Method of Forming

Vertical gate all-around (VGAA) structures are described. In an embodiment, a structure including a first doped region in a substrate, a first vertical channel extending from the first doped region, a first metal-semiconductor compound region in a top surface of the first doped region, the first metal-semiconductor compound region extending along at least two sides of the first vertical channel, and a first gate electrode around the first vertical channel.

HALF-BRIDGE CIRCUIT INCLUDING A LOW-SIDE TRANSISTOR AND A LEVEL SHIFTER TRANSISTOR INTEGRATED IN A COMMON SEMICONDUCTOR BODY

A half-bridge circuit includes a low-side transistor and a high-side transistor each having a load path and a control terminal, and a high-side drive circuit having a level shifter with a level shifter transistor. The low-side transistor and the level shifter transistor are integrated in a common semiconductor body.

Halbleitervorrichtung und Verfahren zur Herstellung derselben

Es werden eine Halbleitervorrichtung, bei der dauerhaft ein niedriger Durchlasswiderstand und gleichzeitig eine hohe vertikale Überschlagsspannung erreicht werden kann, und ein Verfahren zur Herstellung der Halbleitervorrichtung bereitgestellt. Die Halbleitervorrichtung ist in Form einer gestapelten Schicht auf GaN-Basis ausgebildet, die eine n-Typ Driftschicht 4, eine p-Typ Schicht 6 und eine n-Typ Deckschicht 8 umfasst. Die Halbleitervorrichtung umfasst eine nachgewachsene Schicht 27, die so ausgebildet ist, um ein Gebiet der gestapelten Schicht auf GaN-Basis, das durch eine Öffnung 28 gezeigt ist, abzudecken, wobei die nachgewachsene Schicht 27 einen Kanal umfasst. Der Kanal weist zweidimensionales Elektronengas auf, das an der Grenzfläche zwischen der Elektronendriftschicht und der Elektronenversorgungsschicht gebildet ist. Unter der Annahme, dass die Elektronendriftschicht 22 eine Dicke d aufweist, weist die p-Typ Schicht 6 eine Dicke im Bereich von d bis 10 d auf, und eine gradierte ...

Semiconductor device and method for producing same

The objective of the present invention is to increase the voltage resistance performance of a vertical semiconductor device equipped with an aperture and provided with a channel formed by a two-dimensional electron gas at the aperture. The vertical semiconductor device is provided with a GaN-based laminate (15) to which an aperture (28) is provided, is provided with an n-type GaN drift layer (4), a p-type GaN barrier layer (6), and an n-type GaN contact layer (7), and is provided with: a re-grown layer (27) containing an electron donor layer (26) and an electron transit layer (22) in a manner so as to coat the aperture; a source electrode (S); and a gate electrode (G) positioned over the re-grown layer. The gate electrode (G) covers a portion corresponding to the thickness range of the p-type GaN barrier layer, and terminates at a position in the wall surface away from the bottom of the aperture.

Compound semiconductor device and manufacturing method for same

MICROELECTRONIC COMPONENT VERTICAL AND ITS MANUFACTURING METHOD

METHODS OF FORMING GRAPHENE-CONTAINING SWITCHES

NITRIDE-BASED TRANSISTOR HAVING VRTICAL CHANNEL AND METHOD FOR MANUFACUTRING SAME

A nitride-based transistor, according to one embodiment, comprises: a first-nitride-based first semiconductor layer doped as a first type; a first-nitride-based second semiconductor layer doped as a second type and disposed on the first semiconductor layer; a first-nitride-based third semiconductor layer doped as the first type and disposed on the second semiconductor layer; a second-nitride-based fourth semiconductor layer disposed along the inner wall of a trench formed so as to pass through at least the second and third semiconductor layers and disposed on the third semiconductor layer outside the trench; and a gate electrode formed on the fourth semiconductor layer. Compared with the first-nitride-based first to third semiconductor layers, the second-nitride-based fourth semiconductor layer includes a nitride having a different energy band gap.

GaN FIELD-EFFECT TRANSISTOR

A novel GaN field-effect transistor of normally-off type having a very small on-resistance when operating and capable of operating on large current. The transistor comprises source and drain electrodes, a channel region made of a first GaN semiconductor material being an i- or p-GaN semiconductor material and electrically connected to the source and drain electrodes, first and second electron supply region made of a second GaN semiconductor material having a band gap energy greater than that of the first GaN semiconductor material, joined to the channel region, and spaced from each other, an insulating layer formed on the channel region between the first and second electron supply regions, and a gate electrode formed on the insulating layer.

FET including an InGaAs channel and method of enhancing performance of the FET

According to an embodiment of the present invention, a method of manufacturing a FET device having a set BTBT leakage and a maximum VDD includes: determining an x value in InxGa1-xAs according to the BTBT leakage and the maximum VDD, and forming a channel utilizing InxGa1-xA, wherein x is not 0.53.

RADIATION RESISTANT CMOS DEVICE AND METHOD FOR FABRICATING THE SAME

A radiation resistant CMOS device and a method for fabricating the same. The CMOS device includes a substrate, a source region, a drain region and a vertical channel on the substrate. A first dielectric protection region is inserted into the vertical channel at the center of the vertical channel to divide the vertical channel into two parts and has a height equal to the length of the vertical channel. The edge of the first dielectric protection region is 20-100 nm from an outer side of the channel, with a central axis of an silicon platform for an active region as the center. A second dielectric protection region is disposed under the source or drain region, with a length equal to the length of the source or drain region and a height of 10-50 nm. The dielectric protection regions effectively block paths for the source and drain regions collecting charges.

IC unit and method of manufacturing the same, and electronic device including the same

There are provided an Integrated Circuit (IC) unit, a method of manufacturing the same, and an electronic device including the IC unit. According to an embodiment, the IC unit includes a first source/drain layer, a channel layer and a second source/drain layer for a first device and a first source/drain layer, a channel layer and a second source/drain layer for a second device stacked in sequence on a substrate. In the first device, the channel layer includes a first portion and a second portion separated from each other. The first source/rain layer and the second source/drain layer each extend integrally to overlap both the first portion and the second portion of the channel layer. The IC unit further includes a first gate stack surrounding a periphery of the first portion and also a periphery of the second portion of the channel layer of the first device, and a second gate stack surrounding a periphery of the channel layer of the second device.

Power semiconductor package with integrated heat spreader and partially etched conductive carrier

In one implementation, a power semiconductor package includes a power transistor having a first power electrode and a gate electrode on its bottom surface, and a second power electrode on its top surface. The first power electrode is configured for attachment to a first partially etched conductive carrier segment and the gate electrode is configured for attachment to a second partially etched conductive carrier segment. The power semiconductor package also includes a power electrode heat spreader situated over the second power electrode and configured for attachment to a power electrode conductive carrier segment.

Trenched vertical power field-effect transistors with improved on-resistance and breakdown voltage

Trenched vertical power field-effect transistors with improved on-resistance and/or breakdown voltage are fabricated. In one or more embodiments, the modulation of the current flow of the transistor occurs in the lateral channel, whereas the voltage is predominantly held in the vertical direction in the off-state. When the device is in the on-state, the current is channeled through an aperture in a current-blocking region after it flows under a gate region into the drift region. In another embodiment, a novel vertical power low-loss semiconductor multi-junction device in III-nitride and non-III-nitride material system is provided. One or more multi-junction device embodiments aim at providing enhancement mode (normally-off) operation alongside ultra-low on resistance and high breakdown voltage.

Semiconductor device and method for producing the same

The semiconductor device includes a GaN-based layered body having an opening and including an n-type drift layer and a p-type layer located on the n-type drift layer, a regrown layer including a channel and located so as to cover the opening, and a gate electrode located on the regrown layer and formed along the regrown layer, wherein the opening reaches the n-type drift layer, and an edge of the gate electrode is not located outside a region of the p-type layer when viewed in plan.

HIGH-ELECTRON-MOBILITY TRANSISTOR DEVICES

A device includes a first high electronic mobility transistor (HEMT) and a second HEMT. The first HEMT includes a first gate, a source coupled to the first gate, and a drain coupled to the first gate. The second HEMT includes a second gate coupled to the source and to the drain. The second HEMT has a lower threshold voltage than the first HEMT.

NITRIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Provided are a vertical nitride semiconductor device in which occurrence of leak currents can be suppressed, and a method for manufacturing such nitride semiconductor device. A nitride semiconductor device, which is a vertical HEMT, is provided with an n type GaN first nitride semiconductor layer, p+ type GaN second nitride semiconductor layers, an n type GaN third nitride semiconductor layer, and an n type AlGaN fourth nitride semiconductor layer that is in hetero junction with a front surface of the third nitride semiconductor layer. Openings that penetrate the third nitride semiconductor layer and reach front surfaces of the second nitride semiconductor layers are provided at positions isolated from the peripheral edge of the third nitride semiconductor layer. Source electrodes are provided in the openings. Etching damage that is in contact with the source electrodes is surrounded by a region where no etching damage is formed.

Compound semiconductor device and manufacturing method of the same

An i-GaN layer (5) (electron transit layer), an n-GaN layer (7) (compound semiconductor layer) formed over the i-GaN layer, and a source electrode (21s), a drain electrode (21d) and a gate electrode (21g) formed over the n-GaN layer are provided. A recess portion (7a) is formed inside an area between the source electrode and the drain electrode of the n-GaN layer and at a portion separated from the gate electrode.

INTEGRATED CIRCUITRY COMPONENTS, SWITCHES, AND MEMORY CELLS

A switch comprising: a graphene structure (24) extending longitudinally between a pair of electrodes (16, 18) and being conductively connected to both electrodes of said pair; first and second electrically conductive structures (26, 28) laterally outward of the graphene structure and on opposing sides of the graphene structure from one another; and ferroelectric material (31) laterally between the graphene structure and at least one of the first and second electrically conductive structures, the first and second electrically conductive structures being configured to provide the switch into "on" and "off' states by application of an electric field (EF) across the graphene structure and the ferroelectric material.

A VERTICAL HEMT, AN ELECTRICAL CIRCUIT, AND A METHOD FOR PRODUCING A VERTICAL HEMT

A vertical high-electron-mobility transistor, HEMT (100), comprising: a substrate (310); a drain contact (410), the drain contact being a metal contact via through said substrate; a pillar layer (500) arranged above the drain contact (410) and comprising at least one vertical pillar (510) and a supporting material (520) laterally enclosing the at least one vertical pillar (510); a heterostructure mesa (600) arranged on the pillar layer (500), the heterostructure mesa (600) comprising an AIGaN-layer (610) and a GaN-layer (620), together forming a heterojunction (630); at least one source contact (420a, 420b) electrically connected to the heterostructure mesa (600); a gate contact (430) arranged on said heterostructure mesa (600), and above the at least one vertical pillar (510); wherein the at least one vertical pillar (510) is forming an electron transport channel between the drain contact (410) and the heterojunction (630).

HEMT mit integrierter Diode mit niedriger Durchlassspannung

High-Electron-Mobility-Transistor (100), umfassend:Source (S), Gate (G) und Drain (D);ein erstes III-V-Halbleitergebiet (116) mit einem ersten zweidimensionalen Elektronengas (120), das einen ersten leitenden Kanal, der vom Gate (G) zwischen Source (S) und Drain (D) gesteuert werden kann, bereitstellt;ein zweites III-V-Halbleitergebiet (108) unter dem ersten III-V-Halbleitergebiet und mit einem zweiten zweidimensionalen Elektronengas (114) als zweiten leitenden Kanal, der entweder mit Source (S) oder mit Drain (D) verbunden ist und nicht vom Gate (G) gesteuert werden kann; undwobei das erste und zweite III-V-Halbleitergebiet (116, 108) voneinander durch ein Gebiet (110) des High-Electron-Mobility-Transistors (100) mit einem anderen Bandabstand als das erste und zweite III-V-Halbleitergebiet beabstandet sind.

Nitridhalbleitereinrichtung

Nitridhalbleitereinrichtung mit:einer ersten Nitridhalbleiterschicht (16);einer zweiten Nitridhalbleiterschicht (18), die auf der ersten Nitridhalbleiterschicht (16) lokalisiert ist und eine Bandlücke hat, die größer als eine Bandlücke der ersten Nitridhalbleiterschicht (16) ist;eine Halbleiterschicht (34) des p-Typs, die auf der zweiten Nitridhalbleiterschicht (18) lokalisiert ist; undeine Gate-Elektrode (36), die auf der Halbleiterschicht (34) des p-Typs lokalisiert ist, wobeieine erste Grenzfläche (38a) und eine zweite Grenzfläche (37a, 35a) parallel zwischen der Gate-Elektrode (36) und der Halbleiterschicht (34) des p-Typs lokalisiert sind,die erste Grenzfläche (38a) eine erste Barriere mit Bezug auf Löcher hat, die sich in einer Richtung von der Halbleiterschicht (34) des p-Typs zu der Gate-Elektrode (36) bewegen,die zweite Grenzfläche (37a, 35a) eine zweite Barriere mit Bezug auf die Löcher, die sich in einer Richtung von der Halbleiterschicht (34) des p-Typs zu der Gate-Elektrode ...

Transistoren mit Halbleiterverbindungsschichten und Halbleiterkanalschichten unterschiedlichen Halbleitermaterials

Transistor, umfassend:eine Halbleiterdriftschicht (101) eines ersten Halbleitermaterials;eine Halbleiterkanalschicht (103) auf der Halbleiterdriftschicht, wobei die Halbleiterkanalschicht (103) ein zweites Halbleitermaterial verschieden von dem ersten Halbleitermaterial umfasst;eine Verbindungsschicht (105), die elektrisch zwischen die Halbleiterdriftschicht (101) und die Halbleiterkanalschicht (103) gekoppelt ist, wobei die Verbindungsschicht (105) ein drittes Material verschieden von dem ersten und dem zweiten Halbleitermaterial umfasst; undeine Steuerelektrode (109) auf der Halbleiterkanalschicht (103), dadurch gekennzeichnet, dassdas dritte Material ein polykristallines Halbleitermaterial umfasst.

Semiconductor device and manufacturing method of the same

Method for manufacturing nitride electronic devices

Provided is a method for manufacturing nitride electronic devices that is capable of reducing gate leakage currents. After placing a substrate product in a growth furnace at time t0, the substrate temperature is increased to 950 DEG C. At time t3 when the substrate temperature is sufficiently stabilized, trimethyl gallium and ammonia are supplied to the growth furnace to grow an i-GaN film. At time t5, the substrate temperature reaches 1080 DEG C. At time t6 when the substrate temperature is sufficiently stabilized, trimethyl gallium, trimethyl aluminum and ammonia are supplied to the growth furnace to grow an i-AlGaN film. After film-formation is stopped by stopping the supply of trimethyl gallium and trimethyl aluminum at time t7, the ammonia and hydrogen atmosphere in the growth furnace chamber is promptly changed to a nitrogen atmosphere by stopping the supply of ammonia and hydrogen to the growth furnace and starting the supply of nitrogen. After the nitrogen atmosphere is formed, ...

HETEROJUNCTION TRANSISTOR NORMALLY OPEN TYPE HAS REDUCED TRANSFER RESISTANCE

TOP METAL PAD AS LOCAL INTERCONNECTOR OF VERTICAL TRANSISTOR

An integrated circuit structure includes a first vertical transistor and a second vertical transistor. The first vertical transistor includes a first semiconductor channel, a first top source/drain region over the first semiconductor channel, and a first top source/drain pad overlapping the first top source/drain region. The second vertical transistor includes a second semiconductor channel, a second top source/drain region over the second semiconductor channel, and a second top source/drain pad overlapping the second top source/drain region. A local interconnector interconnects the first top source/drain pad and the second top source/drain pad. The first top source/drain pad, the second top source/drain pad, and the local interconnector are portions of a continuous region with no distinguishable interfaces between the first top source/drain pad, the second top source/drain pad, and the local interconnector. COPYRIGHT KIPO 2016 (702) Form first and second VGAA transistor (704) Form upper ...

VERTICAL MICROELECTRONIC ELEMENT AND METHOD FOR MANUFACTURING THE SAME

SEMICONDUCTOR COMPONENT AND METHOD FOR MANUFACTURING OF THE SAME

Method for producing a semiconductor device with surrounding gate transistor

A method for producing a semiconductor device includes a first step of forming a fin-shaped silicon layer on a silicon substrate using a first resist and forming a first insulating film therearound; and a second step of forming a second insulating film around the fin-shaped silicon layer and etching the second insulating film so as to be left on a side wall of the fin-shaped silicon layer, depositing a third insulating film on the first and second insulating films and the fin-shaped silicon layer, depositing a polysilicon thereon, planarizing a surface thereof, and etching back the polysilicon to expose the third insulating film, forming a second resist, etching the second and third insulating films and then etching the fin-shaped silicon layer and the polysilicon, and removing the second insulating film to form a pillar-shaped silicon layer and a dummy gate formed of the polysilicon.

VERTICAL MICROELECTRONIC COMPONENT AND CORRESPONDING PRODUCTION METHOD

A vertical microelectronic component includes a semiconductor substrate having a front side and a back side, and a multiplicity of fins formed on the front side. Each fin has a side wall and an upper side and is separated from other fins by trenches. Each fin includes a GaN/AlGaN heterolayer region formed on the side wall and including a channel region extending essentially parallel to the side wall. Each fin includes a gate terminal region arranged above the GaN/AlGaN heterolayer region and electrically insulated from the channel region in the associated trench on the side wall. A common source terminal region arranged above the fins is connected to a first end of the channel region in a vicinity of the upper sides. A common drain terminal region arranged above the back side is connected to a second end of the channel region in a vicinity of the front side. 1. A vertical microelectronic component , comprising:a semiconductor substrate including a front side and a back side; at least one GaN/AlGaN heterolayer region formed on the side wall and including an embedded channel region extending essentially parallel to the side wall; and', 'at least one gate terminal region arranged above the GaN/AlGaN heterolayer region and electrically insulated from the channel region in an associated trench on the side wall;, 'an arrangement of a multiplicity of fins formed on the front side of the semiconductor substrate, each fin having a side wall and an upper side and separated from other fins by trenches, each fin includinga common source terminal region arranged above the fins and connected to a respective first end of the channel region in a vicinity of the upper sides of the fins; anda common drain terminal region arranged above the back side and connected to a respective second end of the channel region in a vicinity of the front side of the semiconductor substrate.2. The vertical microelectronic component according to claim 1 , wherein:each fin includes two GaN/AlGaN ...

Semiconductor devices having a hybrid channel layer, current aperture transistors and methods of fabricating same

Transistors and/or methods of fabricating transistors that include a source contact, drain contact and gate contact are provided. In some embodiments, a channel region is provided between the source and drain contacts and at least a portion of the channel regions includes a hybrid layer comprising semiconductor material. In particular embodiments of the present invention, the transistor is a current aperture transistor. The channel region may include pendeo-epitaxial layers or epitaxial laterally overgrown layers. Transistors and methods of fabricating current aperture transistors that include a trench that extends through the channel and barrier layers and includes semiconductor material therein are also provided.

Circuit structure

A circuit structure including a first gate structure, a first multi-connected channel layer and a second transistor is provided. The first gate structure has a first extension direction, and the first gate structure has a first end and a second end opposite to each other. The first gate structure is fully surrounded by the first multi-connected channel layer, and a plane direction of the multi-connected channel layer is perpendicular to the first extension direction. The first gate structure and the first multi-connected channel layer form a first transistor. The second transistor is disposed in the first multi-connected channel layer. A second gate structure or a channel of the second transistor is electrical connected to the first multi-connected channel layer.

Semiconductor device and method for producing the same

There is provided a vertical GaN-based semiconductor device in which the on-resistance can be decreased while the breakdown voltage characteristics are improved using a p-type GaN barrier layer. The semiconductor device includes a regrown layer 27 including a channel located on a wall surface of an opening 28, a p-type barrier layer 6 whose end face is covered, a source layer 7 that is in contact with the p-type barrier layer, a gate electrode G located on the regrown layer, and a source electrode S located around the opening. In the semiconductor device, the source layer has a superlattice structure that is constituted by a stacked layer including a first layer (a layer) having a lattice constant smaller than that of the p-type barrier layer and a second layer (b layer) having a lattice constant larger than that of the first layer.

Field effect transistor including a group III-V compound semiconductor layer

A field effect transistor (FET) includes a first semiconductor layer and a second semiconductor layer, the second semiconductor layer being formed on the first semiconductor layer and having a band gap energy greater than that of the first semiconductor layer. The first and second semiconductor layers are made of a Group III-V compound semiconductor layer, formed on the first semiconductor layer are a gate electrode 36 and a source electrode 35 , formed on the second semiconductor layer is a drain electrode 37 , and the drain electrode and the gate electrode are formed respectively on opposing planes of a semiconductor structure which contains the first and second semiconductor layers. This arrangement enables a drain's breakdown voltage to be increased in the FET, because the gate electrode 36 and the drain electrode 37 are respectively disposed, in a spatial separation of each other, on different planes instead of the same plane of the semiconductor structure.

CURRENT APERTURE VERTICAL ELECTRON TRANSISTORS WITH AMMONIA MOLECULAR BEAM EPITAXY GROWN P-TYPE GALLIUM NITRIDE AS A CURRENT BLOCKING LAYER

A current aperture vertical electron transistor (CAVET) with ammonia (NH 3 ) based molecular beam epitaxy (MBE) grown p-type Gallium Nitride (p-GaN) as a current blocking layer (CBL). Specifically, the CAVET features an active buried Magnesium (Mg) doped GaN layer for current blocking purposes. This structure is very advantageous for high power switching applications and for any device that requires a buried active p-GaN layer for its functionality.

MOSFET WITH SATURATION CONTACT AND METHOD FOR FORMING A MOSFET WITH SATURATION CONTACT

A MOSFET with saturation contact. The MOSFET with saturation contact includes an n-doped source region, a source contact, a contact structure, which extends from the source contact to the n-doped source region, and forms with the source contact a first conductive connection and forms with the n-doped source region a second conductive connection, a barrier layer and an insulating layer. The contact structure includes a section between the first conductive connection and the second conductive connection, which is embedded between the barrier layer and the dielectric layer and is configured in such a way that a two-dimensional electron gas is formed therein.

MOS-Gatterverknüpfte Vorrichtung vom Grabentyp mit einer verspannten Schicht an der Grabenseitenwand

MOS-Halbleitervorrichtung vom Grabentyp mit einem Siliziumwafer (10), der eine obere und eine untere Oberfläche aufweist; eher Source-Elektrode (S) auf der oberen Oberfläche; einer Drain-Elektrode (0) auf der unteren Oberfläche; mindestens einem Graben (20), der in der oberen Oberfläche ausgebildet ist und sich zu einer vorgegebenen liefe erstreckt; einer SiGe-Schicht (21), die zumindest die Seitenwände des Grabens (20) bedeckt und die im Bereich der Seltenwände den Gitterabstand des Siliziums annimmt und dabei verspannt wird; einer MOS-Gatestruktur, die eine dielektrische Gateschicht (30) aufweist, die auf mindestens einem Abschnitt der SiGe Schicht (21) ausgebildet ist, und eine leitende Gatestruktur (31) auf der dielektrischen Gateschicht aufweist.

Tri-valence nitride transistor with enhanced doping in base layer

STATIC RANDOM ACCESS MEMORY CELL WITH VERTICAL GATE-ALL-AROUND METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR

The present invention relates to a static random access memory (SRAM) cell with a vertical gate-all-around metal-oxide-semiconductor field-effect transistor (MOSFET). The SRAM cell includes a first boundary and a second boundary which is opposite to and parallel to the first boundary; a first and a second pull-up transistor; a first and a second pull-down transistor forming inverters which are cross-latched with the first and the second pull-up transistors; and a first and a second pass-gate transistor. Each of the first and the second pull-up transistors, the first and the second pull-down transistors, and the first and the second pass-gate transistors includes a bottom plate as a first source/drain region, a channel on the bottom plate, and a top plate on the channel as a second source/drain region. The SRAM cell further includes a first, a second, a third, and a fourth active region, each extending from the first boundary to the second boundary. According to the present invention, it ...

Double heterojunction group III-nitride structures

A semiconductor structure having: a Group III-N channel layer, a Group III-N top-barrier polarization-generating layer forming a heterojunction with an upper surface of the channel layer; and a Group III-N back-barrier polarization-generating layer forming a heterojunction with a lower surface of the channel layer. The channel layer has disposed therein a predetermined n-type conductive dopant.

Semiconductor device, power supply circuit, and computer

A semiconductor device includes a nitride semiconductor layer, a first electrode and second electrode on the nitride semiconductor layer, a gate electrode, and a gate insulating layer between the nitride semiconductor layer and the gate electrode. The gate insulating layer has a first oxide region containing at least any one element of aluminum and boron, gallium, and silicon. When a distance between the first end portion and the second end portion of the first oxide region is defined as d1, and a position separated by d1/10 from the first end portion toward the second end portion is defined as a first position, an atomic concentration of gallium at the first position is 80% or more and 120% or less of that of the at least any one element.

Vertical heterostructure field effect transistor and associated method

A vertical heterostructure field effect transistor including a first layer having a first material, and the first material having a hexagonal crystal lattice structure defining a first bandgap and one or more non-polar planes is provided. The transistor further includes a second layer that is adjacent to the first layer having a second material. Further, the second layer has a first surface and a second surface, and a portion of the second layer first surface is coupled to the surface of the first layer to form a two dimensional charge gas and to define a first region. The second material may have a second bandgap that is different than the first bandgap. Furthermore, the transistor may include a conductive layer that is disposed in the trench and is interposed between the first region and a second region that is not in electrical communication with the first region if no electrical potential is applied to the conductive layer, and an electrical potential applied to the conductive layer ...

NANOWIRE AND LARGER GaN BASED HEMTS

Nanowire and larger, post-based HEMTs, arrays of such HEMTs, and methods for their manufacture are provided. In one embodiment, a HEMT can include a III-N based core-shell structure including a core member (e.g., GaN), a shell member (e.g., AlGaN) surrounding a length of the core member and a two-dimensional electron gas (2-DEG) at the interface therebetween. The core member including a nanowire and/or a post can be disposed over a doped buffer layer and a gate material can be disposed around a portion of the shell member. Exemplary methods for making the nanowire HEMTs and arrays of nanowire HEMTs can include epitaxially forming nanowire(s) and epitaxially forming a shell member from each formed nanowire. Exemplary methods for making the post HEMTs and arrays of post HEMTs can include etching a III-N layer to form II-N post(s) followed by formation of the shell member(s).

Nitride semiconductor device

A nitride semiconductor device is provided that includes: a substrate; an n-type drift layer above the front surface of the substrate; a p-type base layer above the n-type drift layer; a gate opening in the base layer that reaches the drift layer; an n-type channel forming layer that covers the gate opening and has a channel region; a gate electrode above a section of the channel forming layer in the gate opening; an opening that is separated from the gate electrode and reaches the base layer; an opening formed in a bottom surface of said opening and reaching the drift layer; a source electrode covering the openings; and a drain electrode on the rear surface of the substrate.

METHOD OF MAKING A THREE-DIMENSIONAL MEMORY DEVICE HAVING A HETEROSTRUCTURE QUANTUM WELL CHANNEL

A cylindrical confinement electron gas confined within a two-dimensional cylindrical region can be formed in a vertical semiconductor channel extending through a plurality of electrically conductive layers comprising control gate electrodes. A memory film in a memory opening is interposed between the vertical semiconductor channel and the electrically conductive layers. The vertical semiconductor channel includes a wider band gap semiconductor material and a narrow band gap semiconductor material. The cylindrical confinement electron gas is formed at an interface between the wider band gap semiconductor material and the narrow band gap semiconductor material. As a two-dimensional electron gas, the cylindrical confinement electron gas can provide high charge carrier mobility for the vertical semiconductor channel, which can be advantageously employed to provide higher performance for a three-dimensional memory device.

Semiconductor device and method of making a semiconductor device

A semiconductor device and a method of making the same. The device includes a substrate having an AlGaN layer located on one or more GaN layers, for forming a two dimensional electron gas at an interface between the AlGaN layer and the GaN layer. The device also includes a source contact. The device further includes a drain contact. The device also includes a gate contact located between the source contact and the drain contact. The gate contact includes a gate electrode. The gate contact also includes an electrically insulating layer located between the gate electrode and the AlGaN layer. The insulating layer includes at least one aperture for allowing holes generated during an off-state of the device to exit the device through the gate electrode.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

PROBLEM TO BE SOLVED: To provide a vertical semiconductor device capable of stably obtaining improved pinch-off characteristics and improved breakdown voltage performance by surely fixing a potential of a p-type GaN barrier layer. SOLUTION: A semiconductor device comprises: a GaN-based stack 15 having an opening 28; a regrowth layer 27 including a channel located so as to cover the wall surfaces of the opening; an n+-type source layer 8 ohmic-contacting source electrodes S; a p-type GaN barrier layer 6; and a p+-GaN auxiliary layer 7 located between the n+-type source layer 8 and the p-type GaN barrier layer 6. In order for a potential of the p-type GaN barrier layer 6 to fix a source potential, the p+-GaN auxiliary layer 7 forms a tunnel junction with the n+-type source layer 8. COPYRIGHT: (C)2012,JPO&INPIT ...

Halbleiteranordnung mit einem Superjunction-Transistor und einem weiteren, in einen gemeinsamen Halbleiterkörper intergrierten Bauelement

Eine Halbleiteranordnung umfasst einen Halbleiterkörper, sowie einen Leistungstransistor, der in einer Bauelementzone des Halbleiterkörpers angeordnet ist. Der Leistungstransistor weist wenigstens eine Source-Zone, eine Drain-Zone und wenigstens eine Body-Zone auf, sowie wenigstens eine Drift-Zone von einem ersten Dotierungstyp und wenigstens eine Kompensationszone von einem zum ersten Dotierungstyp komplementären zweiten Dotierungstyp, und eine Gate-Elektrode, die benachbart zu der wenigstens einen Body-Zone angeordnet und durch ein Gate-Dielektrikum gegenüber der Body-Zone dielektrisch isoliert ist. Die Halbleiteranordnung umfasst außerdem ein weiteres Halbleiterbauelement, das in einer zweiten Bauelementzone des Halbleiterkörpers angeordnet ist. Die zweite Bauelementzone umfasst eine wannenförmige Struktur vom zweiten Dotierungstyp, die eine erste Halbleiterzone vom ersten Dotierungstyp umgibt. Das weitere Halbleiterbauelement umfasst Bauelementzonen, die in der ersten Halbleiterzone ...

Compound semiconductor device and method for manufacturing the same

Disclosed is a compound semiconductor device comprising an n-type GaN layer (3), a GaN layer (7) formed above the n-type GaN layer (3), an n-type AlGaN layer (9) formed above the GaN layer (7), a gate electrode (15) and a source electrode (13) formed above the n-type AlGaN layer (9), a drain electrode (14) formed below the n-type GaN layer (3), and a p-type GaN layer (4) formed between the GaN layer (7) and the drain electrode (14). A method for manufacturing the compound semiconductor device is also disclosed.

Avalanche-proof quasi-vertical HEMT

VERTICAL STRUCTURE HETEROJUNCTION TRANSISTOR

L'invention concerne un transistor (1) à effet de champ à hétérojonction, comprenant : -un empilement de première et deuxième couches semi conductrices de type III-N (14,13) formant une couche de gaz d'électrons ou de trous (15) ; -une première électrode de conduction (21) en contact électrique avec la couche de gaz et une deuxième électrode de conduction (22); -une couche de séparation (12) positionnée à l'aplomb de la première électrode et sous la deuxième couche semi conductrice (13) ; -une troisième couche semi conductrice (11) disposée sous la couche de séparation (12) et en contact électrique avec la deuxième électrode; -un élément conducteur (24) en contact électrique avec ladite couche de gaz (15) et connectant électriquement la troisième couche semi conductrice (11) et ladite couche de gaz (15) ; -une grille de commande (23) étant positionnée entre ledit élément conducteur (24) et la première électrode de conduction (21).

VERTICAL TYPE TRANSISTOR WITH HETERO-JUNCTION STRUCTURE AND METHOD FOR MANUFACTURING SAME

수직 구조물을 갖는 갈륨 질화물 전력 반도체 디바이스

... 반도체 디바이스가 제1 면 및 제2 면을 갖는 기판, 및 기판의 제1 면 위에 배치되는 제1 활성 층을 포함한다. 제2 활성 층이 제1 활성 층 상에 배치된다. 제2 활성 층은 제1 활성 층과 제2 활성 층 사이에 2차원 전자 기체 층이 생기도록 제1 활성 층보다 더 높은 밴드갭을 갖는다. 적어도 하나의 트렌치가 제1 활성 층 및 제2 활성 층과 2차원 전자 기체 층을 통과해서 기판 내로 연장된다. 전도성 재료가 트렌치를 라이닝한다. 제1 전극이 제2 활성 층 상에 배치되고 제2 전극이 기판의 제2 면 상에 배치된다.

Vertical power transistor device, semiconductor die and method of manufacturing a vertical power transistor device

INTEGRATED CIRCUITRY COMPONENTS, SWITCHES, AND MEMORY CELLS

A switch includes a graphene structure extending longitudinally between a pair of electrodes and being conductively connected to both electrodes of said pair. First and second electrically conductive structures are laterally outward of the graphene structure and on opposing sides of the graphene structure from one another. Ferroelectric material is laterally between the graphene structure and at least one of the first and second electrically conductive structures. The first and second electrically conductive structures are configured to provide the switch into "on" and "off states by application of an electric field across the graphene structure and the ferroelectric material. Other embodiments are disclosed, including components of integrated circuitry which may not be switches.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME

A semiconductor device includes a first compound semiconductor layer, a second compound semiconductor layer having a larger band gap than that of the first compound semiconductor layer, p-type third compound semiconductor layer disposed above a portion of the second compound semiconductor layer, a p-type fourth compound semiconductor layer disposed above the third compound semiconductor layer and having a higher resistance than that of the third compound semiconductor layer, and a gate electrode disposed above the fourth compound semiconductor layer.

Method of making a three-dimensional memory device having a heterostructure quantum well channel

A cylindrical confinement electron gas confined within a two-dimensional cylindrical region can be formed in a vertical semiconductor channel extending through a plurality of electrically conductive layers comprising control gate electrodes. A memory film in a memory opening is interposed between the vertical semiconductor channel and the electrically conductive layers. The vertical semiconductor channel includes a wider band gap semiconductor material and a narrow band gap semiconductor material. The cylindrical confinement electron gas is formed at an interface between the wider band gap semiconductor material and the narrow band gap semiconductor material. As a two-dimensional electron gas, the cylindrical confinement electron gas can provide high charge carrier mobility for the vertical semiconductor channel, which can be advantageously employed to provide higher performance for a three-dimensional memory device.

Gallium nitride semiconductor device and method for producing the same

An insulating layer, an undoped first GaN layer and an AlGaN layer are laminated in this order on a surface of a semiconductor substrate. A surface barrier layer formed by a two-dimensional electron gas is provided in an interface between the first GaN layer and the AlGaN layer. A recess (first recess) which reaches the first GaN layer but does not pierce the first GaN layer is formed in a surface layer of the AlGaN layer. A first high withstand voltage transistor and a control circuit are formed integrally on the aforementioned semiconductor substrate. The first high withstand voltage transistor is formed in the first recess and on a surface of the AlGaN layer. The control circuit includes an n-channel MOSFET formed in part of the first recess, and a depression type n-channel MOSFET formed on a surface of the AlGaN layer. In this manner, there are provided a gallium nitride semiconductor device which can be used under a high temperature environment while reduction in total circuit size ...

VERTICAL FIELD EFFECT TRANSISTOR HAVING TWO-DIMENSIONAL CHANNEL STRUCTURE

A vertical field effect transistor (VFET) including a first source/drain region, a channel structure upwardly protruding from the first source/drain region and configured to serve as a channel, the channel structure having a two-dimensional structure in a plan view, the channel structure having an opening at at least one side thereof, the channel structure including one or two first portions and one or more second portions, the one or two first portion extending in a first direction, and the one or more second portions connected to corresponding one or more of the one or more first portions and extending in a second direction, the second direction being different from the first direction, a gate structure horizontally surrounding the channel structure, and a second source/drain region upwardly on the channel structure may be provided.

NITRIDE SEMICONDUCTOR DEVICE

A nitride semiconductor device includes a substrate; a first nitride semiconductor layer above the substrate; a block layer above the first nitride semiconductor layer; a first opening penetrating through the block layer; an electron transit layer and an electron supply layer provided sequentially above the block layer and along an inner surface of the first opening; a gate electrode provided above the electron supply layer to cover the first opening; a second opening penetrating through the electron supply layer and the electron transit layer; a source electrode provided in the second opening; and a drain electrode. When the first main surface is seen in a plan view, (i) the first opening and the source electrode each are elongated in a predetermined direction, and (ii) at least part of an outline of a first end of the first opening in a longitudinal direction follows an arc or an elliptical arc.

LARGE AREA GROUP III NITRIDE CRYSTALS AND SUBSTRATES, METHODS OF MAKING, AND METHODS OF USE

HEMT device and method

Compound semiconductor device and manufacturing method thereof

Compound semiconductor, method for manufacturing same, and nitride semiconductor

This compound semiconductor constitutes a high-performance semiconductor device by having a high electron concentration of 5*1019 cm-3 or more, and exhibiting an electron mobility of 46 cm2/V.s or more, and low electrical resistance. The present invention provides an n conductivity-type group 13 nitride semiconductor that can be film-formed at a temperature within a range from a room temperature to 700 DEG C on a substrate having a large area.

TRENCH HIGH ELECTRON MOBILITY TRANSISTOR

A method for producing a solid state device, including forming a first dielectric layer over an epitaxial layer at least partially covering the a Silicon substrate and depositing a photoresist material thereover, removing a predetermined portion first dielectric layer to define an exposed portion, implanting dopants into the exposed portion to define a doped portion, preferentially removing Silicon from the exposed portion to generate trenches having V-shaped cosss-sections and having first and second angled sidewalls defining the V-shaped cross-section, wherein each angled sidewall defining the V- shaped cross-section is a Silicon face having a 111 orientation, and forming a 2DEG on at least one sidewall.

FIELD EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME

Disclosed is a field effect transistor which comprises a nitride semiconductor multilayer structure on a substrate through an appropriate buffer layer. The nitride semiconductor multilayer structure is obtained by epitaxially growing at least a drift layer composed of n-type or i-type AlXGa1-XN (wherein 0 ≤ X ≤ 0.3), a barrier layer composed of i-type AlYGa1-YN (wherein Y > X), an electron supply layer composed of n-type AlYGa1-YN, and a channel layer composed of i-type GaN or InGaN, sequentially from the substrate side. The field effect transistor also comprises a gate electrode formed on a part of the surface of the channel layer through an insulating film, an n+-type connection region which is formed at a position planarly adjacent to the region wherein the gate electrode is formed by doping a region ranging at least from a part of the channel layer to a part of the drift layer with an n-type impurity at a concentration of not less than 1 × 1018 cm-3, a source electrode formed in the ...

III-NITRIDE HIGH ELECTRON MOBILITY TRANSISTOR STRUCTURES AND METHODS FOR FABRICATION OF SAME

Structures for III-nitride GaN high electron mobility transistors (HEMT), method for fabricating for GaN devices and integrated chip-level power systems using the GaN devices are provided. The GaN HEMT structure includes a substrate, an AlGaN/GaN heterostructure grown on the substrate, and a normally-off GaN device fabricated on the AlGaN/GaN heterostructure. The AlGaN/GaN heterostructure includes a GaN buffer layer and an AlGaN barrier layer. The integrated chip-level power system includes a substrate, an AlGaN/GaN heterostructure layer grown on the substrate and a plurality of GaN devices. The AlGaN/GaN heterostructure layer includes a GaN buffer layer and an AlGaN barrier layer and is formed into mesa areas and valley areas. Each of the plurality of GaN devices are fabricated on a separate one of the mesa areas.

Device comprising 2D material

A device includes a substrate, a first electrode on the substrate, an insulating pattern on the substrate, a second electrode on an upper end of the insulating pattern, a two-dimensional (2D) material layer on a side surface of the insulating pattern, a gate insulating layer covering the 2D material layer, and a gate electrode contacting the gate insulting layer. The insulating pattern extends from the first electrode in a direction substantially vertical to the substrate. The 2D material layer includes at least one atomic layer of a 2D material that is substantially parallel to the side surface of the insulating pattern.

Ambipolar synaptic devices

Device architectures based on trapping and de-trapping holes or electrons and/or recombination of both types of carriers are obtained by carrier trapping either in near-interface deep ambipolar states or in quantum wells/dots, either serving as ambipolar traps in semiconductor layers or in gate dielectric/barrier layers. In either case, the potential barrier for trapping is small and retention is provided by carrier confinement in the deep trap states and/or quantum wells/dots. The device architectures are usable as three terminal or two terminal devices.

III-N transistors with enhanced breakdown voltage

Techniques related to III-N transistors having enhanced breakdown voltage, systems incorporating such transistors, and methods for forming them are discussed. Such transistors include a hardmask having an opening over a substrate, a source, a drain, and a channel between the source and drain, and a portion of the source or the drain disposed over the opening of the hardmask.

SEMICONDUCTOR DEVICE

According to one embodiment, a semiconductor device includes first to third electrodes, a semiconductor member, a first insulating member, and a compound member. The third electrode includes a first electrode portion. The first electrode portion is between the first and second electrodes. The semiconductor member includes a first semiconductor region and a second semiconductor region. The first semiconductor region includes first to fifth partial regions. The fourth partial region is between the first and third partial regions. The fifth partial region is between the third and second partial regions. The second semiconductor region includes first and second semiconductor portions. The first insulating member includes a first insulating region. The first insulating region is between the third partial region and the first electrode portion. The compound member includes a first compound region. At least a part of the first semiconductor portion dose not overlap the compound member in the second ...

METHOD AND SYSTEM FOR FABRICATION OF A VERTICAL FIN-BASED FIELD EFFECT TRANSISTOR

A method of fabricating a vertical fin-based field effect transistor (FET) includes providing a semiconductor substrate having a first surface and a second surface, the semiconductor substrate having a first conductivity type, epitaxially growing a first semiconductor layer on the first surface of the semiconductor substrate, the first semiconductor layer having the first conductivity type and including a drift layer and a graded doping layer on the drift layer, and epitaxially growing a second semiconductor layer having the first conductivity type on the graded doping layer. The method also includes forming a metal compound layer on the second semiconductor layer, forming a patterned hard mask layer on the metal compound layer, and etching the metal compound layer and the second semiconductor layer using the patterned hard mask layer as a mask exposing a surface of the graded doping layer to form a plurality of fins surrounded by a trench. 1. A method of fabricating a vertical fin-based field effect transistor (FET) , the method comprising:providing a semiconductor substrate having a first surface and a second surface, the semiconductor substrate having a first conductivity type;epitaxially growing a first semiconductor layer on the first surface of the semiconductor substrate, the first semiconductor layer having the first conductivity type and including a drift layer and a graded doping layer on the drift layer;epitaxially growing a second semiconductor layer having the first conductivity type on the graded doping layer;forming a metal compound layer on the second semiconductor layer;forming a patterned hard mask layer on the metal compound layer; andetching the metal compound layer and the second semiconductor layer using the patterned hard mask layer as a mask exposing a surface of the graded doping layer to form a plurality of fins surrounded by a trench.2. The method of claim 1 , further comprising:epitaxially growing a third semiconductor layer having a ...

HETEROJUNCTION TYPE GROUP III-V COMPOUND SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD

PROBLEM TO BE SOLVED: To suppress a leak current of a heterojunction type group III-V compound semiconductor device when the semiconductor device is turned off, and to reduce resistance when the device is turned on. SOLUTION: The group III-V compound semiconductor has a lower layer 46 of GaN, an upper layer 48 of AlGaN which has a heterojunction with the lower layer 46 and also has a band gap larger than a band gap of the lower layer 46, a source electrode 54 formed at a portion of the surface of the upper layer 48, and a gate electrode 52 formed at the other portion of the surface of the upper layer 48; and the lower layer 64 has a crystal defect high-density region 72 and a crystal defect low-density region distributed in a surface parallel to a heterojunction surface, the source electrode 54 is formed in a region opposed to the crystal defect low-density region, and the gate electrode 52 is formed in a region opposed to the crystal defect high-density region 72. COPYRIGHT: (C)2006,JPO ...

Halbleitervorrichtung und Verfahren zur Herstellung derselben

Bereitgestellt wird eine vertikale GaN-basierte Halbleitervorrichtung, in der der Ein-Widerstand gesenkt werden kann, während die Durchschlagspannungseigenschaften unter Verwendung einer p-Typ-GaN-Barriereschicht verbessert werden. Die Halbleitervorrichtung beinhaltet eine Regrown-Schicht 27, die einen Kanal beinhaltet, der an einer Wandoberfläche einer Öffnung 28 angeordnet ist, eine p-Typ-Barriereschicht 6, deren Endfläche bedeckt ist, eine Source-Schicht 7, die in Kontakt mit der p-Typ-Barriereschicht ist, eine Gate-Elektrode G, die an der Regrown-Schicht angeordnet ist, und eine Source-Elektrode S, die um die Öffnung herum angeordnet ist. In der Halbleitervorrichtung weist die Source-Schicht eine Supergitterstruktur auf, die von einer gestapelten Schicht gebildet wird, die eine erste Schicht (a-Schicht) mit einer Gitterkonstante von weniger als derjenigen der p-Typ-Barriereschicht und eine zweite Schicht (b-Schicht) mit einer Gitterkonstante von mehr als derjenigen der ersten Schicht ...

A gallium nitride transistor

Trenches are formed in a GaN layer 315 and a two dimensional carrier gas is formed along the horizontal and vertical interface portions defined by the mesa and trench sidewall structures and an overlying conformal AlGaN layer 325. The corrugated configuration of the 2DEG channel increases the current density of the device compared to a conventional planar HEMT channel structure.

Layered vertical field effect transistor and methods of fabrication

A III-nitride vertical field effect transistor (FET) comprises a base plate 1, a mask layer 6 on the base plate having openings for exposure of the base plate; a drain 2 grown epitaxially onto regions of the base plate exposed by the openings of the mask layer; an insulation layer 3 grown epitaxially onto the drain; a source 4 grown epitaxially onto the insulation layer; a vertical nitride stack 5 grown epitaxially onto the side faces of the drain, the insulation layer and the source, and overlaying the mask layer; the stack provides a vertical conducting channel to connect the source to the drain. A current flowing from the source to the drain through the conducting channel can be modulated by an electrical voltage that is applied to the side face of the vertical nitride stack. There are preferably also electrodes 7, 8, 10 and edge terms 9. The drain may grow partly over the mask layer i.e. there may be epitaxial lateral overgrowth (ELOG). A double width mask may be used. A method for ...

HEMT device with polarize junction longitudinal leakage current barrier lay structure and preparation method thereof

집적 회로 구성요소들, 스위치들, 및 메모리 셀들

... 스위치는 한 쌍의 전극들 사이에서 세로 방향으로 연장되며 상기 쌍의 양쪽 전극들에 도전성으로 연결되는 그래핀 구조를 포함한다. 제 1 및 제 2 전기적 도전성 구조들은 그래핀 구조의 측면 바깥쪽으로 및 서로로부터 그래핀 구조의 대향 측면들 상에 있다. 강유전성 재료는 측면으로 그래핀 구조 및 제 1 및 제 2 전기적 도전성 구조들 중 적어도 하나 사이에 있다. 제 1 및 제 2 전기적 도전성 구조들은 그래핀 구조 및 강유전성 재료를 가로지르는 전기장의 인가에 의해 “온” 및 “오프” 상태들로 스위치를 제공하도록 구성된다. 스위치들이 아닐 수 있는 집적 회로의 구성요소들을 포함한, 다른 실시예들이 개시된다.

Semiconductor device

A semiconductor device (1) according to the present invention comprises: a semiconductor layer (40) which has main surfaces (40a, 40b); a metal layer (31) which has main surfaces (31a, 31b) and is thicker than the semiconductor layer (40), while being formed from a first metal material and having the main surface (31a) in contact with the main surface (40b); a metal layer (30) which has main surface (30a, 30b) and is thicker than the semiconductor layer (40), while being formed from a metal material that has a higher Young's modulus than the first metal material and having the main surface (30a) in contact with the main surface (31b); and transistors (10, 20). With respect to this semiconductor device (1), the transistor (10) has a source electrode (11) and a gate electrode (19) on the main surface (40a) side of the semiconductor layer (40); the transistor (20) has a source electrode (21) and a gate electrode (29) on the main surface (40a) side of the semiconductor layer (40); and a bidirectional ...

VERTICAL POWER TRANSISTOR DEVICE, SEMICONDUCTOR DIE AND METHOD OF MANUFACTURING A VERTICAL POWER TRANSISTOR DEVICE

A vertical power transistor device comprises: a substrate (100) formed from a IM-V semiconductor material and a multi-layer stack (1 16) at least partially accommodated in the substrate (100). The multi-layer stack comprises: a semi-insulating layer (108) disposed adjacent the substrate (100) and a first layer (1 10) formed from a first III-V semiconductor material and disposed adjacent the semi-insulating layer (108). The multi-layer stack (116) also comprises a second layer (112) formed from a second III-V semiconductor material disposed adjacent the first layer (110) and a heterojunction is formed at an interface of the first and second layers.

POLARIZATION-DOPED ENHANCEMENT MODE HEMT

The present invention belongs to the field of semiconductor technology and relates to a polarization-doped enhancement mode HEMT device. The technical solution of the present invention grows the first barrier layer and the second barrier layer that contain gradient Al composition sequentially on the buffer layer. The gradient trends of the two layers are opposite. The three-dimensional electron gas (3DEG) and the three-dimensional hole gas (3DHG) are induced and generated in the barrier layers due to the inner polarization difference respectively. A trench insulated gate structure is at one side of the source which is away from the metal drain and is in contact with the source. First, since the highly concentrated electrons exist in the entire first barrier layer, the on-state current is improved greatly. Second, the vertical conductive channel between the source and the 3DEG are pinched off by the 3DHG, so as to realize the enhancement mode.

Lateral/Vertical Semiconductor Device with Embedded Isolator

A lateral/vertical device is provided. The device includes a device structure including a device channel having a lateral portion and a vertical portion. The lateral portion of the device channel can be located adjacent to a first surface of the device structure, and one or more contacts and/or a gate can be formed on the first surface. The device structure also includes a set of insulating layers located in the device structure between the lateral portion of the device channel and a second surface of the device structure opposite the first surface. An opening in the set of insulating layers defines a transition region between the lateral portion of the device channel and a vertical portion of the device channel. A contact to the vertical portion of the device channel can be located on the second surface.

TRENCHED VERTICAL POWER FIELD-EFFECT TRANSISTORS WITH IMPROVED ON-RESISTANCE AND BREAKDOWN VOLTAGE

Trenched vertical power field-effect transistors with improved on-resistance and/or breakdown voltage are fabricated. In one or more embodiments, the modulation of the current flow of the transistor occurs in the lateral channel, whereas the voltage is predominantly held in the vertical direction in the off-state. When the device is in the on-state, the current is channeled through an aperture in a current-blocking region after it flows under a gate region into the drift region. In another embodiment, a novel vertical power low-loss semiconductor multi-junction device in III-nitride and non-III-nitride material system is provided. One or more multi-junction device embodiments aim at providing enhancement mode (normally-off) operation alongside ultra-low on resistance and high breakdown voltage.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME

A semiconductor device includes a semiconductor substrate including a semiconductor element, a first surface-side electrode disposed on a first surface of the semiconductor substrate, and a second surface-side electrode disposed on a second surface of the semiconductor substrate. The semiconductor substrate includes a gallium nitride substrate and first column regions and second column regions disposed on a first principal surface of the gallium nitride substrate and alternately arranged along a c-axis direction in the first principal surface. The first column regions are formed of a first nitride semiconductor layer and the second column regions are formed of a second nitride semiconductor layer that is higher in band gap than the first nitride semiconductor layer. The semiconductor element is configured to enable a current to flow between the first surface and the second surface of the semiconductor substrate.

SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD THEREOF

PROBLEM TO BE SOLVED: To provide a semiconductor device and a manufacturing method of the same, capable of growing a GaN-based semiconductor region with excellent reproducibility for filling a trench, in a semiconductor device and a manufacturing method of the semiconductor device utilizing the GaN-based semiconductor material having a trench structure. SOLUTION: A base layer 8 of GaN containing n-type impurities, an embedding layer 10 of AlGaN containing p-type impurities, a coating layer 9 of undoped AlGaN and a surface layer 25 of a material same as that of the base layer 8 are laminated sequentially on the surface of the substrate 6 of GaN containing n-type impurities. The trench 10a, reaching the base layer 8, is formed in the embedding layer 10, the coating layer 9 and the surface layer 25. The base layer 8 is exposed on the bottom surface of the trench 10a. When heat treatment is carried out under this condition, the surface layer 25 of GaN, which is laminated on the surface of the ...

Hemt with integrated low forward bias diode

A high electron mobility transistor includes a source, gate and drain, a first III-V semiconductor region having a two-dimensional electron gas (2DEG) which provides a first conductive channel controllable by the gate between the source and drain, and a second III-V semiconductor region below the first III-V semiconductor region and having a second conductive channel connected to the source or drain and not controllable by the gate. The first and second III-V semiconductor regions are spaced apart from one another by a region of the high electron mobility transistor having a different band gap than the first and second III-V semiconductor regions.

SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME

There are provided a semiconductor device in which a drain leak current can be reduced in the transistor operation while high vertical breakdown voltage is achieved and a method for producing the semiconductor device. In the semiconductor device, an opening that extends from an n-type contact layer and reaches an n-type drift layer through a p-type barrier layer is formed. The semiconductor device includes a regrown layer located so as to cover portions of the p-type barrier layer and the like that are exposed to the opening, the regrown layer including an undoped GaN channel layer and a carrier supply layer ; an insulating layer located so as to cover the regrown layer and a gate electrode G located on the insulating layer In the p-type barrier layer, the Mg concentration A (cm)and the hydrogen concentration B (cm) satisfy 0.1 Подробнее