СПОСОБ ИЗГОТОВЛЕНИЯ ДИОДА С ВИСКЕРОМ ТЕРАГЕРЦОВОГО ДИАПАЗОНА

Изобретение относится к полупроводниковой электронике. Способ изготовления диода с вискером "Меза-подложка" терагерцового диапазона включает нанесение на поверхность гетероэпитаксиальной структуры диэлектрической пленки, в которой по маске фоторезиста травлением до высоколегированного катодного слоя создается окно катодного контакта U-, или О-образной формы, формирование в нем металлизации низкоомного омического катодного контакта с последующим удалением резиста, отжигом и гальваническим утолщением, формирование с использованием тонких резистивных масок на поверхности активных слоев окна анодного контакта микронного или субмикронного диаметра между U-выступами катода, или в центре О-образного катода, удаление в окне анодного контакта слоя диэлектрика, проведение финишных обработок, формирование металлизации анодного контакта, удаление резиста, формирование резистивной маски или маски диэлектрика для травления мезы вокруг площадки с расположенными на ней анодом и катодом, травление мезы ...

СПОСОБ ИЗГОТОВЛЕНИЯ ДИОДОВ ШОТТКИ НА ОСНОВЕ КАРБИДА КРЕМНИЯ

Использование: для изготовления карбид кремниевых приборов, а именно высоковольтных диодов Шоттки. Сущность изобретения заключается в том, что способ содержит окисление поверхности эпитаксиальной структуры, формирование в оксиде кремния контактных окон методом фотолитографии, формирование контакта Шоттки методом напыления металла и взрывной фотолитографии, термообработки контакта Шоттки, формирование контактной металлизации, проверки электрических параметров, дополнительно определяют высоту барьера и коэффициент неидеальности ВАХ диода Шоттки после взрывной фотолитографии, причем высота барьера должна быть не менее чем 75%, а коэффициент неидеальности не более 130% от значений годного диода Шоттки. Технический результат: обеспечение возможности повышения выхода годных диодов Шоттки. 1 з.п. ф-лы, 1 ил.

ИНТЕГРИРОВАННЫЙ ШОТТКИ p-n ДИОД

Интегрированный Шоттки p-n диод, состоящий из эпитаксиальной структуры, рабочая сторона которого покрыта слоем диэлектрика, охранного кольца, выполненного методом диффузии, типа проводимости противоположного типу проводимости эпитаксиальной структуры, контактного окна анода в слое диэлектрика, распределенных рядов полос локальных p-n-переходов, выполненных одновременно с охранным кольцом, и переходов Шоттки, выполненных в углублениях в контактном окне анода, отличающийся тем, что локальные p-n-переходы выполнены на выступах, сформированных в контактном окне анода высотой h, выбираемой из соотношения 0,15x≤h≤0,5x, где x- глубина диффузии охранного кольца.

АЛМАЗНЫЙ ДИОД С БАРЬЕРОМ ШОТТКИ

Полезная модель относится к области электронной техники, в частности к конструированию и технологии изготовления полупроводниковых диодов с барьером Шоттки, и может быть использована в сильнотоковой высоковольтной и твердотельной высокочастотной электронике. Алмазный диод с барьером Шоттки содержит сильнолегированную бором монокристаллическую алмазную подложку типа p+, контактирующую со слаболегированным бором гомоэпитаксиальным монокристаллическим алмазным слоем типа p-, защитный диэлектрический слой, расположений на поверхности слаболегированного слоя, катод в виде электрода с металлическим контактом, формирующим барьер Шоттки, расположенным частично на поверхности слаболегированного слоя и частично на поверхности защитного диэлектрического слоя, и анод в виде омического контакта, размещенного на сильнолегированной алмазной подложке. Между слаболегированным монокристаллическим слоем и контактом Шоттки выполнены функциональные зоны из алмаза n-типа проводимости, характеризующегося объемной ...

ДИОД С НИЗКИМ ПАДЕНИЕМ НАПРЯЖЕНИЯ

Полезная модель относится к области электроники, а именно к микроэлектронному конструированию кристаллов, и может быть использована в разработке и изготовлении мощных диодов с низким падением напряжения (диодов Шоттки) для различного применения в силовой электронике. Техническим результатом полезной модели является снижение обратного тока и, как следствие, повышение надежности диода при превышении пробивного напряжения. Технический результат достигается тем, что диод с низким падением напряжения содержит кремниевую сильнолегированную подложку n-типа проводимости, на лицевой стороне которой расположен слаболегированный эпитаксиальный слой n-типа проводимости; слой оксида кремния; охранное кольцо р-типа проводимости; контакт Шоттки, слой алюминиевой металлизации анода, отличающийся тем, что дополнительно содержит делительное кольцо р-типа проводимости, расположенное рядом с охранным кольцом р-типа проводимости с его внешней стороны на таком расстоянии от охранного кольца р-типа проводимости ...

Способ изготовления двухспектрального фоточувствительного элемента на основе барьера Шоттки

Способ используется для изготовления двухспектральных фоточувствительных устройств, предназначенных для независимой регистрации излучений в ближнем ультрафиолетовом (УФ) и среднем инфракрасном (ИК) диапазонах спектра. Сущность: способ изготовления двухспектрального фоточувствительного элемента на основе барьера Шоттки включает нанесение AuGe на обратную сторону подложки, быстрый термический отжиг, напыление Ti-Au на обратную сторону подложки, напыление барьерного Аu на эпитаксиальный слой, травление барьерного Au с использованием меза-технологии, формирование маски фоторезиста под «взрыв», «взрыв» Аu с фоторезистом, при этом после операции напыления Ti-Au проводятся следующие операции: формирование маски фоторезиста на обратной стороне подложки под травление Au-Ti-AuGe до подложки, напыление барьерного Аu на обратную сторону подложки, травление барьерного Au с использованием меза-технологии. 1 ил.

Диод Шоттки

Полезная модель относится к области электроники, а именно к микроэлектронному конструированию кристаллов, и может быть использована в разработке и изготовлении мощных диодов с низким падением напряжения (диодов Шоттки) для различного применения в силовой электронике. Диод Шоттки содержит кремниевую сильнолегированную подложку n-типа проводимости, на лицевой стороне которой расположен слаболегированный эпитаксиальный слой n-типа проводимости; слой оксида кремния; охранное кольцо p-типа проводимости, выполненное в слаболегированном эпитаксиальном слое n-типа проводимости под границей контактного окна; контакт Шоттки, сформированный в пределах охранного кольца p-типа проводимости; слой алюминиевой металлизации анода, расположенный на контакте Шоттки; делительное кольцо р-типа проводимости, расположенное рядом с охранным кольцом p-типа проводимости с его внешней стороны; многослойную металлизацию катода из последовательно нанесенных на обратную сторону кремниевой сильнолегированной подложки ...

Halbleitervorrichtung und Halbleiterstruktur mit Kontaktierung

The invention relates to a semiconductor device (100) consisting of a first semiconductor area (2) of a defined conductivity type within which a contact area (5), which is adjacent to a surface (20) and of the same conductivity type as the first semiconductor area (2), as well as a buried island area (3), whose conductivity type is opposite to that of the first semiconductor area (2), are arranged. Within the contact area (5) a via hole (70) is provided for which reaches as far as the buried island area (3) and serves to contact same. By means of said semiconductor device (100) it is possible to influence a current (I) flowing to or from the contact area (5) inside a channel area (22) via depletion zones (23, 24).

High temperature change-fixed insertion diode e.g. trench junction barrier schottky diode, for use in motor vehicle-generator system, has isolating plastic layer overlapping radial inner-lying end area of another isolating plastic layer

The diode (1) has a semiconductor chip (3) fixed between a socket and a head wire (6) by an interconnection layer i.e. solder layer (5), and made from semiconductor material e.g. silicon carbide or gallium nitride. The layer is arranged on a chip front side relative to a chip outer edge, and a circulating, isolating plastic layer (10) is arranged above an interconnection layer-free area of the chip. Another completely circulating, isolating plastic layer (11) overlaps a radial inner-lying end area of the former plastic layer, where the latter plastic layer is made from polyimide.

Schottky-Übergang Anordnung

Halbleitervorrichtung und Leistungsumsetzungsvorrichtung, die diese verwendet

Halbleitervorrichtung, die umfasst:ein Halbleiterelement; undeine Schichtstruktur, die eine erste Harzschicht, eine zweite Harzschicht und eine dritte Harzschicht enthält, die in dieser Reihenfolge geschichtet sind, um eine auf einer Seite des Halbleiterelements angeordnete Hauptelektrode zu bedecken,wobei die Schichtstruktur einen ersten Bereich (201) mit der ersten Harzschicht in Kontakt mit der zweiten Harzschicht und einen zweiten Bereich (202) mit der ersten Harzschicht in Kontakt mit der dritten Harzschicht enthält, wobei die beiden Bereiche um die Mitte des Halbleiterelements angeordnet sind,wobei zumindest ein Teil des zweiten Bereichs (202) näher zu der Mitte des Halbleiterelements als der erste Bereich (201) angeordnet ist,die erste Harzschicht durch Photolithographie gemustert ist undeine Begrenzung von zumindest einem Teil des zweiten Bereichs (202) als Muster für die Bilderkennung im Konfektionierungsprozess verwendet wird.

Halbleiterbauteil und Verfahren zu dessen Herstellung

Eine elektrische Feld-Pufferschicht (13) wird eine aktive Zone (12) umgebend ausgebildet. Die elektrische Feld-Pufferschicht (13) umfasst mehrere Fremdstoffschichten des P-Typs (21 bis 25). Jede der Fremdstoffschichten des P-Typs (21 bis 25) umfasst Implantationsschichten des P-Typs (21a bis 25a) und Diffusionsschichten des P-Typs (21b bis 25b), die so ausgebildet werden, dass sie jeweils die Implantationsschichten des P-Typs (21a bis 25a) umgeben und Fremdstoffe des P-Typs in einer Konzentration enthalten, die geringer ist als diejenige der Implantationsschichten des P-Typs (21a bis 25a). Eine erste Implantationsschicht des P-Typs (21a) wird in Kontakt mit der oder die aktive Zone (12) teilweise überlagernd ausgebildet. Jede der Diffusionsschichten des P-Typs (21b bis 25b) wird mit einer Ausdehnung in einem Ausmaß ausgebildet, in dem die erste Diffusionsschicht des P-Typs (21b) mit der zweiten Diffusionsschicht des P-Typs (22b) in Kontakt steht oder diese überlagert. Abstände (s2 bis s5 ...

Halbleitervorrichtung und Verfahren zu deren Herstellung

Eine Gateelektrode (6) ist auf der Halbleiterschicht (2) vorgesehen und umfasst zumindest eine unterste Schicht (6a) in Kontakt mit der Halbleiterschicht (2) und eine auf der untersten Schicht (6a) vorgesehene obere Schicht (6b). Die obere Schicht (6b) wendet eine Spannung auf die unterste Schicht (6a) an, um zu veranlassen, dass sich beide Ränder der untersten Schicht (6a) von der Halbleiterschicht (2) abheben.

SiC-Epitaxiewafer, Verfahren zum Herstellen eines SiC-Epitaxiewafers, SiC-Vorrichtung und Leistungsumwandlungsgerät

Graben Schottky-Sperrschichtdiode mit unterschiedlicher Oxiddicke und Verfahren zu ihrer Herstellung

Schottky-Gleichrichter, der umfasst: ein Halbleitersubstrat eines ersten Leitfähigkeitstyps; mehrere Gräben längs einer ersten Stirnseite des Halbleitersubstrats, die durch mehrere Mesas beabstandet sind, wobei jeder der Gräben eine Oxidschicht mit einer unterschiedlichen Dicke besitzt, die die Boden- bzw. Seitenwandflächen des Grabens überzieht und wobei ein Verhältnis einer Bodenoxidschichtdicke eines Grabens zu einer Seitenwandoxidschichtdicke eines Grabens für besagte Oxidschicht unterschiedlicher Dicken mehr als 2:1 beträgt; und eine Schottky-Metallschicht über der ersten Stirnseite des Halbleitersubstrats, die einen Schottky-Gleichrichterkontakt mit den mehreren Mesas bildet.

Trenched-Gate-Feldeffekttransistoren und Verfahren zum Bilden derselben

Struktur mit einem Trench-Feldeffekttransistor (FET) und einer Schottky-Diode, die monolithisch integriert sind, wobei die Struktur ferner umfasst:einen Gate-Graben (1106, 1206, 1306, 1406, 1506, 1606), der sich in einen Halbleiterbereich erstreckt;eine Gate-Elektrode (1110, 1210, 1310, 1410, 1510), die in dem Gate-Graben (1106, 1206, 1306, 1406, 1506, 1606) angeordnet ist;ein Dielektrikummaterial (1108, 1208, 1308, 1408, 1508, 1608), das über der Gate-Elektrode (1110, 1210, 1310, 1410, 1510) angeordnet ist;einen Halbleiter-Source-Spacer (1114, 1214, 1314, 1415, 1517, 1615), der derart an einer Seite des Gate-Grabens (1106, 1206, 1306, 1406, 1506, 1606) angeordnet ist, dass der Halbleiter-Source-Spacer (1114, 1214, 1314, 1415, 1517, 1615) zumindest einen Abschnitt einer Kontaktöffnung definiert, wobei der Halbleiter-Source-Spacer (1114, 1214, 1314, 1415, 1517, 1615) Polysilizium enthält; undeine Leiterschicht (1120, 1220, 1320, 1421, 1621), die in der Kontaktöffnung angeordnet ist und den ...

Siliciumcarbid-Halbleiteranordnung und Verfahren zur Herstellung derselben

In Anbetracht des oben genannten Problems ist es eine Aufgabe der vorliegenden Erfindung, einen Rückfluss zu ermöglichen, ohne eine Körperelektrode in einem SiC-MOSFET zu betreiben. Eine Siliciumcarbid-Halbleiteranordnung der vorliegenden Erfindung umfasst eine Drain-Elektrode 27; eine ohmsche Elektrode 25 und eine Schottky-Elektrode 26, die an der Drain-Elektrode 27 jeweils in Kontakt mit der Drain-Elektrode 27 sind und nebeneinander sind; einen ersten Stehspannungshaltebereich 13 eines ersten Leitfähigkeitstyps, der an der ohmschen Elektrode in Kontakt mit der ohmschen Elektrode 25 ist; einen zweiten Stehspannungshaltebereich 14 eines zweiten Leitfähigkeitstyps, der an der Schottky-Elektrode in Kontakt mit der Schottky-Elektrode 26 ist und neben dem ersten Stehspannungshaltebereich ist; einen Quellbereich 15 des zweiten Leitfähigkeitstyps in Kontakt auf dem ersten Stehspannungshaltebereich 13 und dem zweiten Stehspannungshaltebereich 14; einen Source-Bereich 16 des ersten Leitfähigkeitstyps ...

Integrierte Halbleiterschaltung

Integrierte Halbleiterschaltung (B2), die auf einem gemeinsamen Halbleiterkörper (U2 bis U4) einen IGBT (Z1), eine mit dessen isolierter Gateelektrode verbundene Steuerschaltung (B1) mit einem n-Kanal-MOSFET (M1) und eine mit der Steuerschaltung (B1) und dem Emitteranschluss des IGBT (Z1) verbundene Schutzschaltung mit einer Zener-Diode (D1) aufweist, dadurch gekennzeichnet, – dass die Steuerschaltung (B1) zusätzlich einen p-Kanal-MOSFET (M2) und die Schutzschaltung zusätzlich zwei Schottky-Dioden (D2 und D3) enthält, – dass der Eingang (P1) der integrierten Halbleiterschaltung (B2) mit der Kathode der Zener-Diode (D1) und mit der Anode der einen Schottky-Diode (D2) verbunden ist, wobei die Kathode dieser Schottky-Diode (D2) an den Eingang der Steuerschaltung (B1) und an die Kathode der anderen Schottky-Diode (D3) angeschlossen ist und die Anode der Zener-Diode (D1) und die Anode der anderen Schottky-Diode (D3) mit dem Emitter des IGBT (Z1) verbunden sind, – wobei der Halbleiterkörper ( ...

Siliziumkarbid-Halbleitervorrichtung

Es wird eine Siliziumkarbid-Halbleitervorrichtung offenbart. Die Siliziumkarbid-Halbleitervorrichtung weist ein Substrat, eine Driftschicht, die einen ersten Leitfähigkeitstyp aufweist und sich auf einer ersten Oberfläche des Substrats befindet, und ein Halbleiterelement eines vertikalen Typs auf. Das Halbleiterelement des vertikalen Typs weist eine Störstellenschicht, die einen zweiten Leitfähigkeitstyp aufweist und sich in einem Oberflächenabschnitt der Driftschicht befindet, und einen Bereich eines ersten Leitfähigkeitstyps auf, der sich in der Driftschicht befindet, von der Störstellenschicht entfernt ist, näher als die Störstellenschicht an dem Substrat angeordnet ist und eine Störstellenkonzentration aufweist, die höher als die der Driftschicht ist.

Semiconductor component used in high voltage applications comprises a silicon carbide layer, an anode having a Schottky contact, a cathode having an ohmic contact and control having a Schottky contact

Semiconductor component comprises: silicon carbide layer (101) having predetermined conductivity type with a surface (101S1) having a third region (R3) arranged between first region (R1) and second region (R2); an anode (102) having Schottky contact with the first region; a cathode (103) having an ohmic contact with second region; and control (104) having a Schottky contact with the third region. An Independent claim is also included for a module unit comprising a conducting plate, the above semiconductor component and an encapsulating housing. Preferred Features: At least one Schottky electrode from the anode and the control electrode has a thickness of not less than 5 mu m. The silicon carbide layer further comprises a rear side surface (101S2) lying opposite the surface (101S1).

ZÜNDVERBINDER FÜR AIRBAG-SYSTEM

HALBLEITERANORDNUNG MIT EINEM GLEICHRICHTENDEN METALL-HALBLEITER- UEBERGANG

Kondensatoranordnung

Kondensatoranordnung (700), aufweisend:ein Substrat (702);eine Mehrzahl von Wannen (704), wobei die Wannen (704) in Form von Säulen im Substrat (702) angeordnet sind, wobei benachbarte Wannen (704) einander entgegengesetzte Dotierungstypen haben;eine dielektrische Schicht (706), wobei die dielektrische Schicht (706) über der Mehrzahl von Wannen (704) angeordnet ist;eine Mehrzahl von Elektroden (708), wobei die Elektroden (708) in Form von Reihen auf mindestens einem Bereich der dielektrischen Schicht (706) angeordnet sind, die über der Mehrzahl von Wannen (704) angeordnet ist, und wobei benachbarte Elektroden (708) einander entgegengesetzte Dotierungstypen haben; undeinen ersten Anschlusspunkt, wobei der erste Anschlusspunkt elektrisch mit jeder Wanne (704) der Mehrzahl von Wannen (704) verbunden ist; undeinen zweiten Anschlusspunkt, wobei der zweite Anschlusspunkt elektrisch mit jeder Elektrode (708) der Mehrzahl von Elektroden (708) verbunden ist wobei die Säulen und Reihen orthogonal ...

Optimierter Randabschluss von Halbleiter-Bauelementen

III-V-Halbleiterdiode

Stapelförmige III-V-Halbleiterdiode (10), aufweisend eine n-Schicht (12) mit einer Dotierstoffkonzentration von mindestens 10N/cm3 und einer Schichtdicke (D1) von 50-675 µm, eine n-Schicht (14) mit einer Dotierstoffkonzentration von 10-10N/cm, einer Schichtdicke (D2) von 10-300 µm, eine p-Schicht (18) mit einer Dotierstoffkonzentration von 5•10-5•10cm, mit einer Schichtdicke (D3) größer 2 µm, wobei die Schichten in der genannten Reihenfolge aufeinander folgen, jeweils eine GaAs-Verbindung umfassen oder aus einer GaAs Verbindung bestehen und monolithisch ausgebildet sind, die n-Schicht (12) oder die p-Schicht (18) als Substrat ausgebildet ist und eine Unterseite der n-Schicht (14) stoffschlüssig mit einer Oberseite der n-Schicht (12) verbunden ist, die stapelförmige III-V-Halbleiterdiode (10) eine erste Defektschicht (16) mit einer Schichtdicke (D4) größer 0,5 µm umfasst, die Defektschicht (16) innerhalb der n-Schicht angeordnet ist und die Defektschicht (16) eine Defektkonzentration im ...

RC-IGBT

Ein Leistungshalbleiterbauelement (1) umfasst einen Halbleiterkörper (10), eine auf einer Vorderseite (10-1) des Halbleiterkörpers (10) angeordnete erste Lastanschlussstruktur (11) und eine auf einer Rückseite (10-2) des Halbleiterkörpers (10) angeordnete zweite Lastanschlussstruktur (12) und ist dahingehend konfiguriert, einen Laststrom zwischen der ersten Lastanschlussstruktur (11) und der zweiten Lastanschlussstruktur (12) mittels mindestens einer Transistorzelle (130) zu steuern. Die Transistorzelle (130) ist zumindest teilweise in dem Halbleiterkörper (10) enthalten und ist auf einer Seite mit der ersten Lastanschlussstruktur (11) und auf der anderen Seite mit einem Driftgebiet (100) des Halbleiterkörpers (10) elektrisch verbunden, wobei das Driftgebiet (100) von einem ersten Leitfähigkeitstyp ist. Der Halbleiterkörper (10) umfasst ferner Folgendes: ein Transistorshortgebiet (107), das vom ersten Leitfähigkeitstyp ist, wobei ein Übergang zwischen dem Transistorshortgebiet (107) und ...

DIODE MIT METALL-HALBLEITERKONTAKT UND VERFAHREN ZU IHRER HERSTELLUNG

Halbleiter-Bauelement mit wenigstens einer Zenerdiode und wenigstens einer dazu parallel geschalteten Schottky-Diode sowie Verfahren zum Herstellen der Halbleiter-Bauelemente

Schottky-Diode

Schottky-Diode mit: einem semiisolierenden GaAs-Substrat (1), einer epitaktischen Struktur auf dem semiisolierenden GaAs-Substrat (1), die der Reihe nach gestapelt eine Pufferschicht (2), eine GaAs-Schicht (3) hoher Ladungsträgerkonzentration und eine GaAs-Schicht (4) geringer Ladungsträgerkonzentration enthält, wobei die GaAs-Schicht (4) geringer Ladungsträgerkonzentration einen ersten und einen zweiten Graben aufweist, die sich durch die GaAs-Schicht (4) geringer Ladungsträgerkonzentration erstrecken und Teile der GaAs-Schicht (4) geringer Ladungsträgerkonzentration und Teile der GaAs-Schicht (3) hoher Ladungsträgerkonzentration freilegen, einer ersten und einer zweiten Kathodenelektrode (6), die jeweils in dem ersten und dem zweiten Graben in direktem ohmschen Kontakt mit der GaAs-Schicht (3) hoher Ladungsträgerkonzentration angeordnet sind, und einer Anodenelektrode (5) im Schottky-Kontakt mit der GaAs-Schicht (4) geringer Ladungsträgerkonzentration, wobei ein aktiver Bereich (31), ...

SiC-Halbleiteranordnung und Verfahren zum Herstellen derselben

Eine SiC-Halbleiteranordnung weist auf: Ein SiC-Substrat (1) mit einer Drainschicht (11), einer Driftschicht (12) und einer Sourceschicht (13), die in dieser Reihenfolge gestapelt sind; mehrere Gräben (14), welche die Sourceschicht (13) durchdringen und die Driftschicht (12) erreichen; eine Gateschicht (15) auf einer Seitenwand jedes Grabens (14); einen Isolationsfilm (17) auf der Seitenwand jedes Grabens (14), welcher die Gateschicht (15) bedeckt; eine Sourceelektrode (19) auf der Sourceschicht (13); und einen Diodenabschnitt (18) in oder unterhalb des Grabens (14), welcher die Driftschicht (12) kontaktiert, um eine Diode bereitzustellen. Die Driftschicht (12) zwischen der Gateschicht (15) auf den Seitenwänden zweier benachbarter Gräben (14) stellt ein Kanalgebiet bereit. Der Diodenabschnitt (18) ist mit der Sourceelektrode (19) gekoppelt und durch den Isolationsfilm (17) von der Gateschicht (15) isoliert.

Halbleiteranordnung

Es wird eine Halbleiteranordnung mit einer Trench-erter PN-Diode als Klammerelement, die sich insbesondere als Z-Diode mit einer Druchbruchspannung von ca. 20V zum Einsatz in Kfz-Generatorsystem eignet, beschrieben. Dabei besteht die TJBS aus einer Kombination von Schottky-Diode und PN-Diode. Für die Durchbruchspannungen gilt, dass die Durchbruchspannung der PN-Diode BV_pn niedriger ist als die Durchbruchspannung der Schottky-Diode BV_schottky. Daher kann die Halbleiteranordnung mit hohen Strömen im Durchbruch betrieben werden.

Manufacture of semiconductor devices with schottky barriers

Apparatus for storing electrical energy

IMPROVEMENTS IN OR RELATING TO BARRIER LAYER DEVICES

... 1291449 Semi-conductor devices WESTERN ELECTRIC CO Inc 21 Nov 1969 [22 Nov 1968] 56972/69 Heading H1K The disclosure of this Specification is identical to that of Specification 1,291,448 but the claims relate to a Si device including an insulating guard ring provided around and defining the periphery of a planar metal-Si or metal silicide-Si rectifying barrier, and extending into the semi-conductor substrate of the device beyond the depth of the rectifying barrier, the guard ring having been formed by chemical conversion of Si to its compound with oxygen, nitrogen or carbon or a combination thereof.

Semiconductor signal translating devices

... 1,100,708. Semi - conductor devices. WESTERN ELECTRIC CO. Inc. 17 June, 1965 [23 June, 1964], No. 25617/65. Heading HlK. In a device having a metal-to-semi -conductor rectifying junction, the metal layer consists of two different metals in contact with each other, both contacting a surface of the semi-conductor. The metal having the lower barrier potential defines the effective junction and the other metal provides a contact area for an electrode lead. In Fig. 1, an N-type silicon wafer 11 has been provided-eg. by vapour phase deposition through a surface oxide mask-with an annular deposit 12 of platinum which may, but need not, be alloyed to the silicon. The platinum serves as a mask for deposition of a circular layer 13 of tungsten inside the platinum annulus. An electrode lead 14 is attached, e.g. by thermocompression bonding, to the platinum and an ohmic contact 15 is made to the opposite face of the wafer, thus completing a diode in which the metal electrode connection is to the platinum ...

Method for modification of built in potential of diodes

A Method of manufacturing a semiconductor device, and a semiconductor device

Semi conductor devices

Methods, systems, and devices for active charge control diodes

Electronic circuit comprising transistor and resistor

An electronic circuit or circuit module 100 for flexible integrated circuits comprises a transistor 1 and a resistor 2, the transistor comprising a first body 10 of material providing a controllable semiconductive channel between source and drain terminals 11, 12, and the resistor comprising a second body 20 of material providing a resistive current path between first resistor terminal 21 and second resistor terminal 22. Both the first body 10 and the second body 20 comprise a metal oxide material, which may be indium gallium zinc oxide (IGZO). In alternate embodiments the first body 10 and second body 20 may comprise a polymer material, a compound semiconductor or a 2D material such as graphene or perovskite. The first body 10 and the second body 20 may be formed by deposition, either sequentially under different deposition conditions, or at the same time in a single deposition step, with the difference in electrical properties achieved by different doping or subsequent processing. The ...

HYBRID JUNCTION SEMICONDUCTOR DEVICE AND METHOD OF MAKING THE SAME

... 1,215,539. Semi-conductor devices. HEWLETT-PACKARD CO. 5 April, 1968 [17 April, 1967], No. 16472/68. Heading H1K. A hybrid semi-conductor device comprises both a Schottky-barrier diode and a PN junction diode in the same wafer 9. An annular P-type region 11 is formed in the N-type wafer 9 to define the PN junction by diffusion, alloying, epitaxy or ion implantation, and a metallic electrode 15 of silver or gold is provided by vapour deposition to extend over the surface area 13 to form the Schottky-barrier portion of the device, and to contact regions 11 to act as ohmic electrode for the PN junction device. A passivating insulation layer 17 of oxide is formed over the remaining surface.

Schottky diode

SEMICONDUCTOR ELECTRIC RECTIFIER

SEMICONDUCTOR DEVICE AND MANUFACTURING PROCESS FOR IT

TRANSITION CONCLUSION FOR SIC SCHOTTKYDIODE

MONOLITHISCHER VERTIKAL- SPERRSCHICHTFELDEFFEKTTRANSISTOR UND AUS SILIZIUMCARBID HERGESTELLTE SCHOTTKY- BARRIERENDIODE UND HERSTELLUNGSVERFAHREN DAFÜR

AUFBAU UND VERFAHREN ZUM AUSBILDEN EINES PLANAREN SCHOTTKY-KONTAKTS

A monolithically integrated trench FET and Schottky diode includes a plurality of trenches extending into a FET region and a Schottky region of a semiconductor layer. A trench in the Schottky region includes a dielectric layer lining the trench sidewalls, and a conductive electrode having a top surface that is substantially coplanar with a top surface of the semiconductor layer adjacent the trench. An interconnect layer electrically contacts the semiconductor layer in the Schottky region so as to form a Schottky contact with the semiconductor layer.

HALBLEITERGLEICHRICHTER

Disclosed are semiconductor devices and methods of making semiconductor devices. An exemplary embodiment comprises a semiconductor layer of a first conductivity type having a first surface, a second surface, and a graded net doping concentration of the first conductivity type within a portion of the semiconductor layer. The graded portion is located adjacent to the top surface of the semiconductor layer, and the graded net doping concentration therein decreasing in value with distance from the top surface of the semiconductor layer. The exemplary device also comprises an electrode disposed at the first surface of the semiconductor layer and adjacent to the graded portion.

TRENCH FET WITH HIGH DENSITY AND INTEGRATED SCHOTTKY DIODE AND MANUFACTURING PROCESS

SCHOTTKY DIODE.

IGNITION LINK FOR AIRBAG SYSTEM

Schottky diode having increased active surface area with improved reverse bias characteristics and method of fabrication

SCHOTTKY DIODES

A semiconductor device

Monolithic vertical junction field effect transistor and Schottky barrier diode fabricated from silicon carbide and method for fabricating the same

Field effect transistor (FET) structure with integrated gate connected diodes

A structure having: a plurality of field effect transistors (FETs) connected between a common input and a common output, each one of the field effect transistors comprises: a source region, a drain region, and a gate electrode for controlling carriers through a channel region of a transistor region of the structure between the source region and the drain region; a plurality of diodes, each one of the diodes being associated with a corresponding one of the plurality of FETs, each one of the diodes having an electrode in Schottky contact with a diode region of the corresponding one of the FETs. The gate electrode and the diode electrode extend along parallel lines. The source region, the drain region, the channel region, and a diode region having therein the diode are disposed along a common line.

Mesa schottky diode with guard ring

LOGIC STRUCTURE UTILIZING POLYCRYSTALLINE SILICON SCHOTTKY DIODE

SEMICONDUCTOR DEVICE

Provided is a semiconductor device which avoids an adverse effect of high temperatures due to a switching element and in which a circuit to prevent false firing is arranged on the same substrate as the switching element. An N-channel type MOSFET 10 and a JFET 30 of an N-channel type containing a semiconductor material of silicon carbide are individually arranged in proximity on conductive patterns 51, 52 on a substrate 5, and a gate electrode 13 of the MOSFET 10 and a drain electrode 31 of the JFET 30 are connected by a lead 61. When an external drive signal for on/off control of MOSFET 10 propagates between source electrode 32 and drain electrode 31 of JFET 30, the channel resistance of JFET 30 is changed to a large/small value according to a low/high level of gate voltage between source electrode 32 and gate electrode 33, whereby a leading edge of a switching waveform between drain electrode 11 and source electrode 12 of MOSFET 10 comes to have a gentler slope than a trailing edge thereof ...

SEMICONDUCTOR DEVICE HAVING ARRAY OF CONDUCTIVE RODS

... 83-3-045 CN SEMICONDUCTOR DEVICE A semiconductor device, specifically an FET, having a body which includes a matrix of semiconductor material, specifically silicon, having an array of individual rods of conductive material, specifically TaSi2, disposed therein. The rods form Schottky barriers with the semiconductor material. A gate contact is made to several of the rods at one end, and source and drain contacts are made to the matrix of semiconductor material. Current flow in the semiconductor material of the matrix between the source and the drain is controlled by applying biasing potential to the gate contact to enlarge the depletion zones around the rods.

HIGH CUT-OFF FREQUENCY PLANAR SCHOTTKY DIODE IN A TRANSMISSION LINE

A planar Schottky diode is disclosed which is inserted into a transmission line without disruption of surge impedance. The diode comprises a plurality of parallel finger-like projections forming Schottky contacts distributed over a width of the transmission line and also of ohmic contacts surrounding these projections but with a longer contact edge.

LOW-LOSS AND HIGH-SPEED DIODES

A diode has a Schottky barrier which permits bidirectional passage of minority carriers as well as majority carriers as an electrode that substitutes for the conventional Schottky electrode in Schottky diodes and low high electrode in Pn junction diodes.

EPITAXIAL EDGE TERMINATION FOR SILICON CARBIDE SCHOTTKY DEVICES AND METHODS OF FABRICATING SILICON CARBIDE DEVICES INCORPORATING SAME

Edge termination for a silicon carbide Schottky rectifier is provided by including a silicon carbide epitaxial region (16) on a voltage blocking layer (14) of the Schottky rectifier and adjacent a Schottky contact (18) of the silicon carbide Schottky rectifier. The silicon carbide epitaxial layer (16) may have a thickness and a doping level so as to provide a charge in the silicon carbide epitaxial region based on the surface doping of the blocking layer (14). The silicon carbide epitaxial region (16) may form a non-ohmic contact with the Schottky contact (18). The silicon carbide epitaxial region (16) may have a width of from about 1.5 to about 5 times the thickness of the blocking layer (14). Schottky rectifiers with such edge termination and methods of fabricating such edge termination and such rectifiers are also provided.

JUNCTION BARRIER SCHOTTKY RECTIFIERS AND METHODS OF MAKING THEREOF

A junction barrier Schottky (JBS) rectifier device and a method of making th e device are described. The device comprises an epitaxially grown first n-type drift layer and p-type regions forming p+-n junctions and self-plana.pi.zing epitaxially over-grown second n-type drift regions between and, optionally, on top of the p-type regions. The device may include an edge termination structure such as an exposed or buried p+-n guard ring, a regrown or implant ed junction termination extension (JTE) region, or a "deep" mesa etched down to the substrate. The Schottky contact to the second n-type drift region and th e ohmic contact to the p-type region together serve as an anode. The cathode c an be formed by ohmic contact to the n-type region on the backside of the wafer . The devices can be used in monolithic digital, analog, and microwave integrated circuits.

IMPROVEMENTS TO PARTICLE DETECTORS

A beam detector (10) including a light source (32), a receiver (34), and a target (36), acting in cooperation to detect particles in a monitored area (38). The target (36), reflects incident light (40), resulting in reflected light (32) being returned to receiver (34). The receiver (34) is a receiver is capable of recording and reporting light intensity at a plurality of points across its field of view. In the preferred form the detector (10) emits a first light beam (3614) in a first wavelength band; a second light beam (3618) in a second wavelength band; and a third light beam (3616) in a third wavelength band, wherein the first and second wavelengths bands are substantially equal and are different to the third wavelength band.

SUBSTRATE, SUBSTRATE WITH THIN FILM, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Provided are a substrate which suppresses deterioration of processing accuracy of a semiconductor device due to the warping of the substrate, a substrate provided with a thin film, a semiconductor device formed using the abovementioned substrate, and a method for manufacturing said semiconductor device. In the substrate (1), the diameter of the main surface (1a) is 2 inches or more, the bow value of the main surface (1a) is -40 µm to -5 µm, and the warp value of the main surface (1a) is 5 µm to 40 µm. The value of the surface roughness (Ra) of the main surface (1a) of the substrate (1) is preferably 1 nm or less and the value of the surface roughness (Ra) of the main surface (1b) is preferably 100 nm or less.

Halbleiterschalt- oder Speichervorrichtung

Sperrschicht-Halbleitervorrichtung

Schottkydiode mit Schutzring

Solid state pinch diode - has three zone structure with channel form and schottky electrode regions

The solid state pinch diode has three impregnated zones. A high impregnated zone (3) is located between an electrode (4) and a substrate (11) that is of a low impregnated zone (5) of the same conductive type as the first zone (3). The third zone is in the form of channels (6.1 - 6.3) of a second type and PN transfer regions are available (7.1 - 7.3). The ends have electrodes (9) of a schottky contact form and these are also located in the channels (11.1 - 11.3). The surfaces (8) provide boundaries for the elements. ADVANTAGE - Main surface structure provides zone boundaries.

METHOD FOR MAKING A BEAM JUNCTION, AND ELECTROMAGNETIC-RADIATION BEAM CONVERTER

Semiconductor device

Current aperture diode and method of fabricating same

A diode and a method of making same has a cathode, an anode and one or more semiconductor layers disposed between the cathode and the anode. A dielectric layer is disposed between at least one of the one or more semiconductor layers and at least one of the cathode or anode, the dielectric layer having one or more openings or trenches formed therein through which the at least one of said cathode or anode projects into the at least one of the one or more semiconductor layers, wherein a ratio of a total surface area of the one or more openings or trenches formed in the dielectric layer at the at least one of the one or more semiconductor layers to a total surface area of the dielectric layer at the at least one of the one or more semiconductor layers is no greater than 0.25.

Semiconductor device and semiconductor device manufacturing method

Provided is a high-performance semiconductor device which hardly causes electric field concentration and can suppress a leak current and minimize an ineffective region in the PN junction region while assuring a sufficient area of the shot-key junction region. The semiconductor device can be manufactured effectively and easily. The semiconductor device includes a PN junction region (7a) and a shot-key junction region (7b) on one side of a first conductive type semiconductor substrate (1) made from SiC. In the PN junction region (7a) are formed a convex portion (2a) having a cross section of a trapezoid shape including a second conductive layer (2) arranged on the semiconductor substrate (1) and a contact layer (3) formed on the second conductive layer (2) of the convex portion (2a) so as to be in the ohmic contact with the second conductive layer (2). A shot-key electrode (4) is formed to cover the side surface of the convex portion (2a) and the contact layer (3) and to be continuous with ...

Semiconductor device

Semiconductor device and method for manufacturing same

A power semiconductor component and method of manufacturing the same

Method of filling large deep trench with high quality oxide for semiconductor devices

A method is disclosed for creating a semiconductor device structure with an oxide-filled large deep trench (OFLDT) portion having trench size TCS and trench depth TCD. A bulk semiconductor layer (BSL) is provided with a thickness BSLT>TCD. A large trench top area (LTTA) is mapped out atop BSL with its geometry equal to OFLDT. The LTTA is partitioned into interspersed, complementary interim areas ITA-A and ITA-B. Numerous interim vertical trenches of depth TCD are created into the top BSL surface by removing bulk semiconductor materials corresponding to ITA-B. The remaining bulk semiconductor materials corresponding to ITA-A are converted into oxide. If any residual space is still left between the so-converted ITA-A, the residual space is filled up with oxide deposition. Importantly, the geometry of all ITA-A and ITA-B should be configured simple and small enough to facilitate fast and efficient processes of oxide conversion and oxide filling.

Method and system fabricating floating guard rings in GaN materials

Silicon carbide junction barrier Schottky diode

Having a different of the switching threshold can be the intrinsic diode of switch junction

Semiconductor device

A semiconductor device using one or more guard rings includes a p-type guard ring region (7) surrounding a pn junction region (8), an insulating film (9) covering the p-type guard ring region (7), one or more conductive films (11) electrically connected with the p-type guard ring region (7) through one or more contact holes (10) made in the insulating film (9), and a semi-insulating film (12) covering the insulating film (9) and the conductive films (11). Thus, a desired breakdown voltage characteristic can be ensured even if a foreign matter or the like adheres to a surface of the conductivefilms (11).

Semiconductor device and method for manufacturing the same

Disclosed is a semiconductor device comprising a silicon carbide substrate (11) having a major surface and a back surface, a semiconductor layer (12) formed on the major surface of the silicon carbide substrate, and a back ohmic electrode layer (1d) formed on the back surface of the silicon carbide substrate. The back ohmic electrode layer (1d) has a reaction layer (1da) containing titanium, silicon and carbon and situated on the back surface side of the silicon carbide substrate, and a titanium nitride layer (1db) situated on the opposite side relative to the back surface of the silicon carbide substrate.

For power devices of super junction structure and its manufacturing method

Semiconductor device and method for manufacturing semiconductor device

Integrated schottky diode in high voltage semiconductor device

Approach to intergrate schottky in MOSFET and structure

The Schottky diode structure

Enhancing schottky breakdown voltage (BV) without affecting an integrated MOSFET-schottky device layout

DIODE SCHOTTKY ON SILICON CARBIDE SUBSTRATE

Schottky diode with low noise - obtd. by surrounding metal layer on semiconductor with semi-insulating passivating layer

DISPOSITIF A SEMI-CONDUCTEUR COMPORTANT UNE STRUCTURE DE GRILLE ASSOCIEE A UNE JONCTION DE FAIBLE PROFONDEUR

L'INVENTION CONCERNE LA TECHNOLOGIE DES SEMI-CONDUCTEURS. UN DISPOSITIF A SEMI-CONDUCTEUR COMPORTE UNE COUCHE DE GA0,47IN0,53AS MINCE ET FORTEMENT DOPEE 37 QUI EST DISPOSEE SUR UNE COUCHE DE GA0,47IN0,53AS 35 DE FACON A AUGMENTER LA HAUTEUR DE BARRIERE DE SCHOTTKY ET A DONNER DES CARACTERISTIQUES INTERESSANTES POUR LE DISPOSITIF. ON PEUT PAR EXEMPLE UTILISER CETTE STRUCTURE EN TANT QU'ELECTRODE DE GRILLE DANS UN TRANSISTOR A EFFET DE CHAMP FABRIQUE EN INGAAS. APPLICATION AUX TRANSISTORS A EFFET DE CHAMP ULTRA-RAPIDES.

MANUFACTORING PROCESS OF UNIPOLAR COMPONENTS

PROCEDE DE FORMATION D'UNE DIODE DE SCHOTTKY MUNIE D'UN ANNEAU DE GARDE AUTO-ALIGNE

Procédé de formation d'une diode de Schottky munie d'un anneau de garde auto-aligné. Un substrat semi conducteur typiquement du silicium 10 comportant des poches 12 de matériau seilicium isolées par des régions d'oxyde 12 est recouvert par une couche isolante 16 qui est délimitée selon une configuration désirée et présente en particulier une ouverture à l'emplacement de la diode. On forme la barrière de Schottky en frittant un métal approprié qui combiné avec le silicium donne le siliciure désiré 22. On choisit un métal tel le platine qui présente un effet de retrait ce qui laisse un anneau de silicium exposé. On implante un dopant de type P, ce qui forme les régions d'anneau de garde 28 auto-alignées avec la diode. Il ne reste plus qu'à déposer le métal d'interconnexion pour achever le disposif. Application à la fabrication de dispositifs à semi-conducteurs et notamment de diodes à barrière de Schottky perfectionnées.

PROCESS OF FORMATION Of a DIODE OF SCHOTTKY PROVIDED With a GUARD RING AUTO-ALIGNE

Gallium nitride vertical Schottky diode, has heavily doped p-type and n-type gallium nitride guard rings respectively provided at peripheries of electrode and lightly doped layer, where electrode is arranged on lightly doped layer

L'invention concerne une diode Schottky verticale comprenant successivement, sur un substrat conducteur (20), une couche (14) de GaN fortement dopée de type N ; une couche (13) de GaN faiblement dopée de type N ; un contact Schottky (22) sur la couche de GaN faiblement dopée de type N.

Моп-транзистор на основе карбида кремния

Полезная модель относится к области мощных высоковольтных приборов, конкретно к конструкции мощного полевого МОП-транзистора на основе карбида кремния, и может быть использована для создания элементной базы преобразовательных устройств. Полезная модель обеспечивает уменьшение размера кристалла и повышение надежности транзистора. Это достигается тем, что МОП-транзистор на основе карбида кремния состоит из ячеек МОП-транзистора, ячеек диода Шоттки и делительных колец, сформированных на подложке n+-типа с эпитаксиальным слоем n-типа с легированными р- и n-типа областями, при этом диоды Шоттки сформированы в области первого делительного кольца МОП-транзистора. 2 ил. РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) (13) 186 986 U1 (51) МПК H01L 29/78 (2006.01) H01L 29/872 (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ОПИСАНИЕ ПОЛЕЗНОЙ МОДЕЛИ К ПАТЕНТУ (52) СПК H01L 29/78 (2018.08); H01L 29/872 (2018.08) (21)(22) Заявка: 2018142565, 03.12.2018 (24) Дата начала отсчета срока действия патента: Дата регистрации: 12.02.2019 (45) Опубликовано: 12.02.2019 Бюл. № 5 (54) МОП-ТРАНЗИСТОР НА ОСНОВЕ КАРБИДА КРЕМНИЯ (57) Реферат: Полезная модель относится к области мощных достигается тем, что МОП-транзистор на основе высоковольтных приборов, конкретно к карбида кремния состоит из ячеек МОПконструкции мощного полевого МОПтранзистора, ячеек диода Шоттки и делительных транзистора на основе карбида кремния, и может колец, сформированных на подложке n+-типа с быть использована для создания элементной базы эпитаксиальным слоем n-типа с легированными преобразовательных устройств. Полезная модель р- и n-типа областями, при этом диоды Шоттки обеспечивает уменьшение размера кристалла и сформированы в области первого делительного повышение надежности транзистора. Это кольца МОП-транзистора. 2 ил. R U 1 8 6 9 8 6 (73) Патентообладатель(и): федеральное государственное автономное образовательное учреждение высшего образования "Национальный исследовательский университет "Московский институт ...

ИНТЕГРИРОВАННЫЙ ШОТТКИ-pn ДИОД

Интегрированный Шоттки-pn диод содержит сильнолегированную подложку (1) n-типа проводимости, на одной стороне которой выращен эпитаксиальный слой (2) n o -типа проводимости, структура из планарных p-n переходов (3) в слое (2) n o -типа проводимости, интегрированных с контактом (4) Шоттки, расположенном на слое (2) n o -типа проводимости, и омический контакт (6) на другой стороне подложки (1). Диод выполнен из карбида кремния политипа 4H, а вне контура контакта (4) Шоттки сформирована полуизолирущая область (5) на глубину слоя (2) n o -типа проводимости. Интегрированный Шоттки-pn диод работает в лавинном режиме при большей величине электрического напряжения. 1 ил. РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) (13) 188 360 U1 (51) МПК H01L 29/872 (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ОПИСАНИЕ ПОЛЕЗНОЙ МОДЕЛИ К ПАТЕНТУ (52) СПК H01L 29/872 (2018.08) (21) (22) Заявка: 2018146707, 25.12.2018 (24) Дата начала отсчета срока действия патента: 25.12.2018 09.04.2019 (56) Список документов, цитированных в отчете о поиске: RU 2390880 C1, 27.05.2010. RU (45) Опубликовано: 09.04.2019 Бюл. № 10 (54) ИНТЕГРИРОВАННЫЙ ШОТТКИ-pn ДИОД (57) Реферат: Интегрированный Шоттки-pn диод содержит сильнолегированную подложку (1) n-типа проводимости, на одной стороне которой выращен эпитаксиальный слой (2) no-типа проводимости, структура из планарных p-n переходов (3) в слое (2) no-типа проводимости, R U интегрированных с контактом (4) Шоттки, расположенном на слое (2) no-типа проводимости, Стр.: 1 140005 U1, 27.04.2014. RU 160937 U1, 10.04.2016. RU 157852 U1, 20.12.2015. US 9865749 B1, 09.01.2018. U 1 U 1 Адрес для переписки: 194021, Санкт-Петербург, ул. Политехническая, 26, ФТИ им. А.Ф. Иоффе, пат.-лицензионная служба, Белову В.И. 1 8 8 3 6 0 Приоритет(ы): (22) Дата подачи заявки: 25.12.2018 R U (73) Патентообладатель(и): Федеральное государственное бюджетное учреждение науки Физико-технический институт им. А.Ф. Иоффе Российской академии наук (RU) Дата регистрации: 1 8 8 3 6 0 ...

Nitride-based semiconductor device and method for manufacturing the same

The present invention provides a nitride-based semiconductor device. The nitride-based semiconductor device includes: a base substrate having a diode structure; an epi-growth film disposed on the base substrate; and an electrode part disposed on the epi-growth film, wherein the diode structure includes: first-type semiconductor layers; and a second-type semiconductor layer which is disposed within the first-type semiconductor layers and has both sides covered by the first-type semiconductor layers.

Structures and methods for forming schottky diodes on a p-substrate or a bottom anode schottky diode

This invention discloses bottom-anode Schottky (BAS) device supported on a semiconductor substrate having a bottom surface functioning as an anode electrode with an epitaxial layer has a same doped conductivity as said anode electrode overlying the anode electrode. The BAS device further includes an Schottky contact metal disposed in a plurality of trenches and covering a top surface of the semiconductor substrate between the trenches. The BAS device further includes a plurality of doped JBS regions disposed on sidewalls and below a bottom surface of the trenches doped with an opposite conductivity type from the anode electrode constituting a junction barrier Schottky (JBS) with the epitaxial layer disposed between the plurality of doped JBS regions. The BAS device further includes an ultra-shallow Shannon implant layer disposed immediate below the Schottky contact metal in the epitaxial layer between the plurality of doped JBS regions.

Reduced process sensitivity of electrode-semiconductor rectifiers

Disclosed are semiconductor devices and methods of making semiconductor devices. An exemplary embodiment comprises a semiconductor layer of a first conductivity type having a first surface, a second surface, and a graded net doping concentration of the first conductivity type within a portion of the semiconductor layer. The graded portion is located adjacent to the top surface of the semiconductor layer, and the graded net doping concentration therein decreasing in value with distance from the top surface of the semiconductor layer. The exemplary device also comprises an electrode disposed at the first surface of the semiconductor layer and adjacent to the graded portion.

Power semiconductor device and method of manufacturing the same

A power semiconductor device includes a first semiconductor layer of a first conductivity type, a first drift layer, and a second drift layer. The first drift layer includes a first epitaxial layer of the first conductivity type, a plurality of first first-conductivity-type pillar layers, and a plurality of first second-conductivity-type pillar layers. The second drift layer is formed on the first drift layer and includes a second epitaxial layer of the first conductivity type, a plurality of second second-conductivity-type pillar layers, a plurality of second first-conductivity-type pillar layers, a plurality of third second-conductivity-type pillar layers, and a plurality of third first-conductivity-type pillar layers. The plurality of second second-conductivity-type pillar layers are connected to the first second-conductivity-type pillar layers. The plurality of second first-conductivity-type pillar layers are connected to the first first-conductivity-type pillar layers. The plurality of third second-conductivity-type pillar layers are arranged on the first epitaxial layer.

Semiconductor module including a switch and non-central diode

A semiconductor module having one or more silicon carbide diode elements mounted on a switching element is provided in which the temperature rise is reduced by properly disposing each of the diode elements on the switching element, to thereby provide a thermal dissipation path for the respective diode elements. The respective diode elements are arranged on a non-central portion of the switching element, to facilitate dissipation of the heat produced by each of the diode elements, whereby the temperature rise in the semiconductor module is reduced.

Semiconductor device with junction field-effect transistor and manufacturing method of the same

A semiconductor device with a JFET is disclosed. The semiconductor device includes a trench and a contact embedded layer formed in the trench. A gate wire is connected to the contact embedded layer, so that the gate wire is connected to an embedded gate layer via the contact embedded layer. In this configuration, it is possible to downsize a contact structure between the embedded gate layer and the gate wire.

Schottky rectifier

A semiconductor rectifier includes a semiconductor substrate having a first type of conductivity. A first layer, which is formed on the substrate, has the first type of conductivity and is more lightly doped than the substrate. A second layer having a second type of conductivity is formed on the substrate and a metal layer is disposed over the second layer. The second layer is lightly doped so that a Schottky contact is formed between the metal layer and the second layer. A first electrode is formed over the metal layer and a second electrode is formed on a backside of the substrate.

Trench-Gate Field Effect Transistors and Methods of Forming the Same

A field effect transistor includes a body region of a first conductivity type over a semiconductor region of a second conductivity type. A gate trench extends through the body region and terminates within the semiconductor region. At least one conductive shield electrode is disposed in the gate trench. A gate electrode is disposed in the gate trench over but insulated from the at least one conductive shield electrode. A shield dielectric layer insulates the at lease one conductive shield electrode from the semiconductor region. A gate dielectric layer insulates the gate electrode from the body region. The shield dielectric layer is formed such that it flares out and extends directly under the body region.

Method of manufacturing semiconductor devices

A method of manufacturing a semiconductor device is disclosed. The method includes forming a first trench and a second trench in an n-type substrate surface, the first trenches being spaced apart from each other, the second trench surrounding the first trenches, the second trench being wider than the first trench. The method also includes forming a gate oxide film on the inner surfaces of the first and second trenches, and depositing an electrically conductive material to the thickness a half or more as large as the first trench width. The method further includes removing the electrically conductive material using the gate oxide film as a stopper layer, forming an insulator film thicker than the gate oxide film, and polishing the insulator film by CMP for exposing the n-type substrate and the electrically conductive material in the first trench.

Semiconductor component with high breakthrough tension and low forward resistance

A semiconductor component having a semiconductor body is disclosed. In one embodiment, the semiconductor component includes a drift zone of a first conductivity type, a drift control zone composed of a semiconductor material which is arranged adjacent to the drift zone at least in places, a dielectric which is arranged between the drift zone and the drift control zone at least in places. A quotient of the net dopant charge of the drift control zone, in an area adjacent to the accumulation dielectric and the drift zone, divided by the area of the dielectric arranged between the drift control zone and the drift zone is less than the breakdown charge of the semiconductor material in the drift control zone.

particle detectors

A beam detector ( 10 ) including a light source ( 32 ), a receiver ( 34 ), and a target ( 36 ), acting in co-operation to detect particles in a monitored area ( 38 ). The target ( 36 ), reflects incident light ( 40 ), resulting in reflected light ( 32 ) being returned to receiver ( 34 ). The receiver ( 34 ) is a receiver is capable of recording and reporting light intensity at a plurality of points across its field of view. In the preferred form the detector ( 10 ) emits a first light beam ( 3614 ) in a first wavelength band; a second light beam ( 3618 ) in a second wavelength band; and a third light beam ( 3616 ) in a third wavelength band, wherein the first and second wavelengths bands are substantially equal and are different to the third wavelength band.

Nitride based semiconductor device

Disclosed herein is a nitride based semiconductor device. There is provided a nitride based semiconductor device including: a base substrate; a semiconductor layer disposed on the base substrate; and an electrode structure disposed on the semiconductor layer, wherein the electrode structure includes: a cathode structure ohmic-contacting the semiconductor layer; and an anode structure having a schottky electrode schottky-contacting the semiconductor layer and an ohmic electrode ohmic-contacting the nitride layer.

Schottky diode switch and memory units containing the same

A switching element that includes a first semiconductor layer, the first semiconductor layer having a first portion and a second portion; a second semiconductor layer, the second semiconductor layer having a first portion and a second portion; an insulating layer disposed between the first semiconductor layer and the second semiconductor layer; a first metal contact in contact with the first portion of the first semiconductor layer forming a first junction and in contact with the first portion of the second semiconductor layer forming a second junction; a second metal contact in contact with the second portion of the first semiconductor layer forming a third junction and in contact with the second portion of the second semiconductor layer forming a fourth junction, wherein the first junction and the fourth junction are Schottky contacts, and the second junction and the third junction are ohmic contacts.

Methods for manufacturing superjunction semiconductor device having a dielectric termination

A superjunction semiconductor device is provided having at least one column of a first conductivity type and at least one column of a second conductivity type extending from a first main surface of a semiconductor substrate toward a second main surface of the semiconductor substrate opposed to the first main surface. The at least one column of the second conductivity type has a first sidewall surface proximate the at least one column of the first conductivity type and a second sidewall surface opposed to the first sidewall surface. A termination structure is proximate the second sidewall surface of the at least one column of the second conductivity type. The termination structure includes a layer of dielectric of an effective thickness and consumes about 0% of the surface area of the first main surface. Methods for manufacturing superjunction semiconductor devices and for preventing surface breakdown are also provided.

Method of forming a semiconductor device termination and structure therefor

At least one embodiment is directed to a semiconductor edge termination structure, where the edge termination structure comprises several doped layers and a buffer layer.

Schottky diode with lowered forward voltage drop

A Schottky diode with a lowered forward voltage drop has an N− type doped drift layer formed on an N+ type doped layer. The N− type doped drift layer has a surface formed with a protection ring inside which is a P-type doped layer. The surface of the N− type doped drift layer is further formed with an oxide layer and a metal layer. The contact region between the metal layer and the N− type doped drift layer within the P-type doped layer forms a Schottky barrier. An upward extending N type doped layer is formed on the N+ type doped layer and under the Schottky barrier to reduce the thickness of the N− type doped drift layer under the Schottky barrier. This lowers the forward voltage drop of the Schottky diode.

Semiconductor diodes with low reverse bias currents

A diode is described with a III-N material structure, an electrically conductive channel in the III-N material structure, two terminals, wherein a first terminal is an anode adjacent to the III-N material structure and a second terminal is a cathode in ohmic contact with the electrically conductive channel, and a dielectric layer over at least a portion of the anode. The anode comprises a first metal layer adjacent to the III-N material structure, a second metal layer, and an intermediary electrically conductive structure between the first metal layer and the second metal layer. The intermediary electrically conductive structure reduces a shift in an on-voltage or reduces a shift in reverse bias current of the diode resulting from the inclusion of the dielectric layer. The diode can be a high voltage device and can have low reverse bias currents.

Semiconductor rectifier device

A semiconductor rectifier device according to an embodiment includes a semiconductor substrate of a first conductive type of a wide gap semiconductor, a semiconductor layer of the first conductive type of the wide gap semiconductor formed on an upper surface of the semiconductor substrate, wherein an impurity concentration of the semiconductor layer is between 1E+14 atoms/cm 3 and 5E+16 atoms/cm 3 inclusive, and a thickness thereof is 8 μm or more, a first semiconductor region of the first conductive type of the wide gap semiconductor formed on the semiconductor layer surface, a second semiconductor region of the second conductive type of the wide gap semiconductor formed as sandwiched by the first semiconductor regions, wherein a width of the second semiconductor region is 15 μm or more, a first electrode formed on the first and second semiconductor regions, and a second electrode formed on a lower surface of the semiconductor substrate.

Semiconductor device

A semiconductor layer has a second impurity concentration. First trenches are formed in the semiconductor layer to extend downward from an upper surface of the semiconductor layer. Each of insulation layers is formed along each of the inner walls of the first trenches. Each of conductive layers is formed to bury each of the first trenches via each of the insulation layers, and extends downward from the upper surface of the semiconductor layer to a first position. A first semiconductor diffusion layer reaches a second position from the upper surface of the semiconductor layer, is positioned between the first trenches, and has a third impurity concentration lower than the second impurity concentration. A length from the upper surface of the semiconductor layer to the second position is equal to or less than half a length from the upper surface of the semiconductor layer to the first position.

Semiconductor system including a schottky diode

A semiconductor system is described, which includes a trench junction barrier Schottky diode having an integrated p-n type diode as a clamping element, which is suitable for use in motor vehicle generator system, in particular as a Zener diode having a breakdown voltage of approximately 20V. In this case, the TJBS is a combination of a Schottky diode and a p-n type diode. Where the breakdown voltages are concerned, the breakdown voltage of the p-n type diode is lower than the breakdown voltage of Schottky diode. The semiconductor system may therefore be operated using high currents at breakdown.

Junction barrier schottky diodes with current surge capability

An electronic device includes a silicon carbide drift region having a first conductivity type, a Schottky contact on the drift region, and a plurality of junction barrier Schottky (JBS) regions at a surface of the drift region adjacent the Schottky contact. The JBS regions have a second conductivity type opposite the first conductivity type and have a first spacing between adjacent ones of the JBS regions. The device further includes a plurality of surge protection subregions having the second conductivity type. Each of the surge protection subregions has a second spacing between adjacent ones of the surge protection subregions that is less than the first spacing.

Superjunction Structures for Power Devices and Methods of Manufacture

A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type.

Integrating schottky diode into power mosfet

A semiconductor device includes a plurality of trenches including active gate trenches in an active area and gate runner/termination trenches and shield electrode pickup trenches in a termination area outside the active area. The gate runner/termination trenches include one or more trenches that define a mesa located outside an active area. A first conductive region is formed in the plurality of trenches. An intermediate dielectric region and termination protection region are formed in the trenches that define the mesa. A second conductive region is formed in the portion of the trenches that define the mesa. The second conductive region is electrically isolated from the first conductive region by the intermediate dielectric region. A first electrical contact is made to the second conductive regions and a second electrical contact to the first conductive region in the shield electrode pickup trenches. One or more Schottky diodes are formed within the mesa.

Vertical junction field effect transistor with mesa termination and method of making the same

A vertical junction field effect transistor (VJFET) having a mesa termination and a method of making the device are described. The device includes: an n-type mesa on an n-type substrate; a plurality of raised n-type regions on the mesa comprising an upper n-type layer on a lower n-type layer; p-type regions between and adjacent the raised n-type regions and along a lower sidewall portion of the raised regions; dielectric material on the sidewalls of the raised regions, on the p-type regions and on the sidewalls of the mesa; and electrical contacts to the substrate (drain), p-type regions (gate) and the upper n-type layer (source). The device can be made in a wide-bandgap semiconductor material such as SiC. The method includes selectively etching through an n-type layer using a mask to form the raised regions and implanting p-type dopants into exposed surfaces of an underlying n-type layer using the mask.

Power semiconductor device

A power semiconductor device and a manufacturing method thereof are provided. The power semiconductor device includes an anode electrode including an anode electrode pad, electrode bus lines connected to a first side and a second side on the anode electrode pad, the electrode bus lines each having a decreasing width in a direction away from the anode electrode pad, and pluralities of first anode electrode fingers and second anode electrode fingers connected with a third side and a fourth side on the anode electrode pad and with both sides of the electrode bus line, a cathode electrode including a first cathode electrode pad and a second cathode electrode pad, a plurality of cathode electrode fingers connected with the first cathode electrode pad, and a plurality of second cathode electrode fingers connected with the second cathode electrode pad, and an insulation layer disposed at an external portion of the anode.

Method for manufacturing diode, and diode

A semiconductor substrate having a first side and a second side made of single crystal silicon carbide is prepared. A mask layer having a plurality of openings and made of silicon oxide is formed on the second side. The plurality of openings expose a plurality of regions included in the second side, respectively. A plurality of diamond portions are formed by epitaxial growth on the plurality of regions, respectively. The epitaxial growth is stopped before the plurality of diamond portions come into contact with each other. A Schottky electrode is formed on each of the plurality of diamond portions. An ohmic electrode is formed on the first side.

Mosfet-schottky rectifier-diode integrated circuits with trench contact structures

A trench MOSFET device with embedded Schottky rectifier, Gate-Drain and Gate-Source clamp diodes on single chip is formed to achieve device shrinkage and performance improvement. The present semiconductor devices achieve low Vf and reverse leakage current for embedded Schottky rectifier, have overvoltage protection for Gate-Source clamp diode and avalanche protection for Gate-Drain clamp diode.

System and Method for Packaging of High-Voltage Semiconductor Devices

A method and an electronic device structure comprising at least one access lead to adapted to be connected to an electrical circuit; at least one substrate region; at least one semiconductor die positioned on the substrate; the at least one semiconductor die being operatively connected to the at least one access lead; a dielectric region extending below the at least one semiconductor die; the dielectric region being formed by creating a cavity in the at least one substrate region; whereby the dielectric region operates to reduce electric field stresses produced by the at least one semiconductor die to thereby reduce the possibility of material failure and voltage breakdown. The method of making an electronic device structure comprises providing at least one substrate region; providing at least one semiconductor die located on the at least one substrate region; removing a portion of the at least one substrate region to provide a dielectric region within the substrate extending below the at least one semiconductor die; whereby the dielectric region within the at least one substrate region operates to reduce electric field stresses produced by the at least one semiconductor die to thereby reduce the possibility of material failure and voltage breakdown.

Method and system for doping control in gallium nitride based devices

A method of growing a III-nitride-based epitaxial structure includes providing a substrate in an epitaxial growth reactor and heating the substrate to a predetermined temperature. The method also includes flowing a gallium-containing gas into the epitaxial growth reactor and flowing a nitrogen-containing gas into the epitaxial growth reactor. The method further includes flowing a gettering gas into the epitaxial growth reactor. The predetermined temperature is greater than 1000° C.

Silicon carbide semiconductor device

A first layer has a first conductivity type. A second layer is provided on the first layer such that a part of the first layer is exposed, and it has a second conductivity type. First to third impurity regions penetrate the second layer and reach the first layer. Each of the first and second impurity regions has the first conductivity type. The third impurity region is arranged between the first and second impurity regions and it has the second conductivity type. First to third electrodes are provided on the first to third impurity regions, respectively. A Schottky electrode is provided on the part of the first layer and electrically connected to the first electrode.

Semiconductor device and solid state relay using same

A semiconductor device includes one or more unipolar compound semiconductor element; and bypass semiconductor elements externally connected to the respective compound semiconductor elements in parallel. A turn-on voltage of the bypass semiconductor elements is smaller than a turn-on voltage of the compound semiconductor elements in the direction from the source to the drain.

SCHOTTKY BARRIER DIODE AND METHOD OF FORMING A SCHOTTKY BARRIER DIODE

Disclosed is a silicon-on-insulator-based Schottky barrier diode with a low forward voltage that can be manufactured according to standard SOI process flow. An active silicon island is formed using an SOI wafer. One area of the island is heavily-doped with an n-type or p-type dopant, one area is lightly-doped with the same dopant, and an isolation structure is formed on the top surface above a junction between the two areas. A metal silicide region contacts the lightly-doped side of the island forming a Schottky barrier. Another discrete metal silicide region contacts the heavily-doped area of the island forming an electrode to the Schottky barrier (i.e., a Schottky barrier contact). The two metal silicide regions are isolated from each other by the isolation structure. Contacts to each of the discrete metal silicide regions allow a forward and/or a reverse bias to be applied to the Schottky barrier. 1. A method of forming a Schottky barrier diode comprising:forming a silicon island in an insulator, said silicon island having an exposed top surface, a first area, and a second area;forming an isolation structure on said exposed top surface between said first area and said second area;doping said first area with one of a p-type dopant and an n-type dopant; andperforming a metal silicide formation process such that a first metal silicide region contacts said first area and extends above said top surface and such that a second metal silicide region contacts said second area and extends above said top region,said isolation structure separating said first metal silicide region from said second metal silicide region, andsaid second metal silicide region forming a Schottky barrier contact to said second area.2. The method of claim 1 , further comprising before said forming of said isolation structure claim 1 , doping said silicon island with said one of said p-type dopant and said n-type dopant in a lower concentration as compared to said first area.3. The method of claim 1 ...

High power semiconductor electronic components with increased reliability

An electronic component includes a depletion-mode transistor, an enhancement-mode transistor, and a resistor. The depletion-mode transistor has a higher breakdown voltage than the enhancement-mode transistor. A first terminal of the resistor is electrically connected to a source of the enhancement-mode transistor, and a second terminal of the resistor and a source of the depletion-mode transistor are each electrically connected to a drain of the enhancement-mode transistor. A gate of the depletion-mode transistor can be electrically connected to a source of the enhancement-mode transistor.

Trench type schottky junction semiconductor device and manufacturing method thereof

A Schottky junction type semiconductor device in which the opening width of a trench can be decreased without deteriorating the withstanding voltage. The cross sectional shape of a trench has a shape of a sub-trench in which the central portion is higher and the periphery is lower at the bottom of the trench, and a p type impurity is introduced vertically to the surface of the drift layer thereby forming a p + SiC region, which is formed in contact to the inner wall of the trench having the sub-trench disposed therein, such that the junction position is formed more deeply in the periphery of the bottom of the trench than the junction position in the central portion of the bottom of the trench.

Termination Structure for Gallium Nitride Schottky Diode

A termination structure for a nitride-based Schottky diode includes a guard ring formed by an epitaxially grown P-type nitride-based compound semiconductor layer and dielectric field plates formed on the guard ring. The termination structure is formed at the edge of the anode electrode of the Schottky diode and has the effect of reducing electric field crowding at the anode electrode edge, especially when the Schottky diode is reverse biased. In one embodiment, the P-type epitaxial layer includes a step recess to further enhance the field spreading effect of the termination structure.

Aluminum gallium nitride etch stop layer for gallium nitride bases devices

A semiconductor structure includes a III-nitride substrate with a first side and a second side opposing the first side. The III-nitride substrate is characterized by a first conductivity type and a first dopant concentration. The semiconductor structure also includes a III-nitride epitaxial layer of the first conductivity type coupled to the first surface of the III-nitride substrate, and a first metallic structure electrically coupled to the second surface of the III-nitride substrate. The semiconductor structure further includes an AlGaN epitaxial layer coupled to the III-nitride epitaxial layer of the first conductivity type, and a III-nitride epitaxial structure of a second conductivity type coupled to the AlGaN epitaxial layer. The III-nitride epitaxial structure comprises at least one edge termination structure.

Edge Termination by Ion Implantation in GaN

An edge terminated semiconductor device is described including a GaN substrate; a doped GaN epitaxial layer grown on the GaN substrate including an ion-implanted insulation region, wherein the ion-implanted region has a resistivity that is at least 90% of maximum resistivity and a conductive layer, such as a Schottky metal layer, disposed over the GaN epitaxial layer, wherein the conductive layer overlaps a portion of the ion-implanted region. A Schottky diode is prepared using the Schottky contact structure.

Low voltage diode with reduced parasitic resistance and method for fabricating

A method of making a diode begins by depositing an Al x Ga 1-x N nucleation layer on a SiC substrate, then depositing an n+ GaN buffer layer, an n− GaN layer, an Al x Ga 1-x N barrier layer, and an SiO 2 dielectric layer. A portion of the dielectric layer is removed and a Schottky metal deposited in the void. The dielectric layer is affixed to the support layer with a metal bonding layer using an Au—Sn utectic wafer bonding process, the substrate is removed using reactive ion etching to expose the n+ layer, selected portions of the n+, n−, and barrier layers are removed to form a mesa diode structure on the dielectric layer over the Schottky metal; and an ohmic contact is deposited on the n+ layer.

Semiconductor Device with Multiple Space-Charge Control Electrodes

A circuit including a semiconductor device having a set of space-charge control electrodes is provided. The set of space-charge control electrodes is located between a first terminal, such as a gate or a cathode, and a second terminal, such as a drain or an anode, of the device. The circuit includes a biasing network, which supplies an individual bias voltage to each of the set of space-charge control electrodes. The bias voltage for each space-charge control electrode can be: selected based on the bias voltages of each of the terminals and a location of the space-charge control electrode relative to the terminals and/or configured to deplete a region of the channel under the corresponding space-charge control electrode at an operating voltage applied to the second terminal.

Method for forming gallium nitride devices with conductive regions

Semiconductor structures comprising a III-nitride (e.g., gallium nitride) material region and methods associated with such structures are provided. In some embodiments, the structures include an electrically conductive material (e.g., gold) separated from certain other region(s) of the structure (e.g., a silicon substrate) by a barrier material in order to limit, or prevent, undesirable reactions between the electrically conductive material and the other component(s) which can impair device performance. In certain embodiments, the electrically conductive material may be formed in a via. For example, the via can extend from a topside of the device to a backside so that the electrically conductive material connects a topside contact to a backside contact. The structures described herein may form the basis of a number of semiconductor devices including transistors (e.g., FET), Schottky diodes, light-emitting diodes and laser diodes, amongst others.

JUNCTION BARRIER SCHOTTKY RECTIFIERS HAVING EPITAXIALLY GROWN P+-N JUNCTIONS AND METHODS OF MAKING

A junction barrier Schottky (JBS) rectifier device and a method of making the device are described. The device comprises an epitaxially grown first n-type drift layer and p-type regions forming p-n junctions and self-planarizing epitaxially over-grown second n-type drift regions between and, optionally, on top of the p-type regions. The device may include an edge termination structure such as an exposed or buried P guard ring, a regrown or implanted junction termination extension (JTE) region, or a “deep” mesa etched down to the substrate. The Schottky contact to the second n-type drift region and the ohmic contact to the p-type region together serve as an anode. The cathode can be formed by ohmic contact to the n-type region on the backside of the wafer. The devices can be used in monolithic digital, analog, and microwave integrated circuits. 150-. (canceled)51. A semiconductor device comprising:a semiconductor substrate of a first conductivity type;a semiconductor drift layer above the substrate;a plurality of highly doped epitaxial layer regions of semiconductor material of a second conductivity type different than the first conductivity type, each of the highly doped epitaxial layer regions separated from one another on the drift layer to form a plurality of junction barriers therewith, the highly doped epitaxial layer regions each having an upper surface and sidewalls; anda plurality of epitaxial drift layer regions of semiconductor material of the first conductivity type, at least some of the epitaxial drift layer regions being disposed between sidewalls of adjacent of the highly doped epitaxial layer regions to electrically couple with the drift layer;at least one ohmic contact with at least some of the plurality of highly doped epitaxial layer regions; andat least one Schottky contact with at least some of the drift layer regions of semiconductor material.52. The semiconductor device of claim 51 , wherein each of the highly doped epitaxial layer regions is ...

Phase-change memory device having multiple diodes

A phase-change memory device with an improved current characteristic is provided. The phase-change memory device includes a metal word line, a semiconductor layer of a first conductivity type being in contact with the metal word line, and an auxiliary diode layer being in contact with metal word line and the semiconductor layer,

Method and system for fabricating edge termination structures in gan materials

A method for fabricating an edge termination, which can be used in conjunction with GaN-based materials, includes providing a substrate of a first conductivity type. The substrate has a first surface and a second surface. The method also includes forming a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the substrate and forming a second GaN epitaxial layer of a second conductivity type opposite to the first conductivity type. The second GaN epitaxial layer is coupled to the first GaN epitaxial layer. The substrate, the first GaN epitaxial layer and the second GaN epitaxial layer can be referred to as an epitaxial structure.

SUPER TRENCH SCHOTTKY BARRIER SCHOTTKY DIODE

A Schottky diode includes an n-substrate, an n-epilayer, trenches introduced into the n-epilayer, floating Schottky contacts being located on their side walls and on the entire trench bottom, mesa regions between the adjacent trenches, a metal layer on its back face, this metal layer being used as a cathode electrode, and an anode electrode on the front face of the Schottky diode having two metal layers, the first metal layer of which forms a Schottky contact and the second metal layer of which is situated below the first metal layer and also forms a Schottky contact. Preferably, these two Schottky contacts have different barrier heights. 1. A Schottky diode , comprising:{'sup': '+', 'an n-substrate;'}an n-epilayer;trenches introduced into the n-epilayer;mesa regions between adjacent trenches;a metal layer on a back face of the diode, the metal layer being used as a cathode electrode;an anode electrode provided on a front face of the diode, the anode electrode having two metal layers, a first metal layer forming a Schottky contact, and a second metal layer being situated below the first metal layer and also forming a Schottky contact; andadditional, floating Schottky contacts situated on walls of the trenches between the second metal layer and bottoms of the trenches.2. The Schottky diode according to claim 1 , wherein the first metal layer and the second metal layer claim 1 , each of which forms a Schottky contact claim 1 , have different barrier heights.3. The Schottky diode according to claim 2 , wherein the second metal layer has a greater barrier height than the first metal layer.4. The Schottky diode according to claim 1 , wherein a distance (D gap) is provided between the second metal layer and the additional Schottky contact adjacent to the second metal layer claim 1 , and between the additional Schottky contacts.5. The Schottky diode according to claim 1 , wherein each of the additional Schottky contacts has a same barrier height as the second metal layer ...

Semiconductor device

A semiconductor device is disclosed that has enhanced its electric charge resistance. A first parallel p-n layer is disposed in an element activating part, and a second parallel p-n layer is disposed in an element peripheral edge part. An n − surface area is disposed between the second parallel p-n layer and a first principal face. Two or more p-type guard ring areas are disposed so as to be separate from each other on the first principal face side of the n − surface area. First field plate electrodes and second field plate electrodes are electrically connected to p-type guard ring areas. Second field plate electrodes cover the first field plate electrodes adjacent to each other so as to cover the first principal face between the first field plate electrodes through a second insulating film.

PRODUCTION OF AN INTEGRATED CIRCUIT INCLUDING ELECTRICAL CONTACT ON SiC

Production of an integrated circuit including an electrical contact on SiC is disclosed. One embodiment provides for production of an electrical contact on an SiC substrate, in which a conductive contact is produced on a boundary surface of the SiC substrate by irradiation and absorption of a laser pulse on an SiC substrate.

METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE

A target made of a metal material is sputtered to form a metal film on a silicon carbide wafer. At this time, the metal film is formed under a condition that an incident energy of incidence, on the silicon carbide wafer, of the metal material sputtered from the target and a sputtering gas flowed in through a gas inlet port is lower than a binding energy of silicon carbide, and more specifically lower than 4.8 eV. For example, the metal film is formed while a high-frequency voltage applied between a cathode and an anode is set to be equal to or higher than 20V and equal to or lower than 300V. 1. A method of manufacturing a silicon carbide semiconductor device , said method comprising a metal film formation step of forming a metal film by: in a chamber suctioned by a vacuum pump , causing a high-frequency voltage to be applied between a pair of electrodes including an anode and a cathode that are arranged opposed to each other , to thereby cause a plasma of a sputtering gas to be generated between said pair of electrodes; sputtering a metal material placed on said cathode with an ion in said generated plasma; and causing said sputtered metal material to be deposited on a silicon carbide wafer that is placed on said anode so as to be opposed to said metal material ,wherein, in said metal film formation step, said metal film is formed under a condition that an incident energy of incidence of said metal material and said sputtering gas on said silicon carbide wafer is lower than a binding energy of silicon carbide.2. The method of manufacturing a silicon carbide semiconductor device according to claim 1 , whereinin said metal film formation step, the condition that said incident energy is lower than said binding energy of silicon carbide, under which said metal film is formed, is satisfied by setting said high-frequency voltage applied between said pair of electrodes to be equal to or higher than 20V and equal to or lower than 300V.3. The method of manufacturing a ...

FABRICATION OF MOSFET DEVICE WITH REDUCED BREAKDOWN VOLTAGE

Fabricating a semiconductor device includes: forming a gate trench in an epitaxial layer overlaying a semiconductor substrate; depositing gate material in the gate trench; forming a body in the epitaxial layer; forming a source embedded in the body; forming a contact trench that extends through the source and at least part of the body; forming a body contact implant on a sidewall of the contact trench; forming a diode enhancement layer along bottom of the contact trench, the diode enhancement layer having opposite carrier type as the epitaxial layer; disposing an epitaxial enhancement portion below the diode enhancement layer, the epitaxial enhancement portion having the same carrier type as the epitaxial layer; and disposing a contact electrode in the contact trench; wherein: a distance between top surface of the substrate and bottom of the epitaxial enhancement layer is shorter than a distance between the top surface of the substrate and bottom of the body. 1. A method for fabricating a semiconductor device , comprising:forming a gate trench in an epitaxial layer overlaying a semiconductor substrate;depositing gate material in the gate trench;forming a body in the epitaxial layer;forming a source embedded in the body;forming a contact trench that extends through the source and at least part of the body;forming a body contact implant on a sidewall of the contact trench;forming a diode enhancement layer along bottom of the contact trench, the diode enhancement layer having opposite carrier type as the epitaxial layer;disposing an epitaxial enhancement portion below the diode enhancement layer, the epitaxial enhancement portion having the same carrier type as the epitaxial layer; anddisposing a contact electrode in the contact trench; wherein:a distance between top surface of the substrate and bottom of the epitaxial enhancement layer is shorter than a distance between the top surface of the substrate and bottom of the body.2. The method of claim 1 , wherein the ...

FABRICATION OF MOS DEVICE WITH SCHOTTKY BARRIER CONTROLLING LAYER

Fabricating a semiconductor device includes: forming a gate trench in an epitaxial layer overlaying a semiconductor substrate; depositing gate material in the gate trench; forming a body; forming a source; forming an active region contact trench that extends through the source and the body into the drain; forming a Schottky barrier controlling layer in the epitaxial layer in bottom region of the active region contact trench; and disposing a contact electrode within the active region contact trench. 1. A method of fabricating a semiconductor device , comprising:forming a gate trench in an epitaxial layer overlaying a semiconductor substrate;depositing gate material in the gate trench;forming a body;forming a source;forming an active region contact trench that extends through the source and the body into the drain;forming a Schottky barrier controlling layer in the epitaxial layer in bottom region of the active region contact trench; anddisposing a contact electrode within the active region contact trench.2. The method of claim 1 , wherein forming the Schottky barrier controlling layer includes depositing a layer of material doped with opposite polarity dopant as the epitaxial layer in the epitaxial layer in the bottom region of the active region contact trench.3. The method of claim 1 , wherein the gate trench is a first gate trench; and forming a second gate trench extending into the epitaxial layer;', 'forming a second gate disposed in the gate trench; and', 'forming a gate contact trench formed within the second gate., 'the method further comprising forming a gate region, including by4. The method of claim 3 , wherein the gate contact trench and the active region contact trench have approximately the same depth.5. The method of claim 3 , wherein the active region contact trench has a different depth than the gate contact trench.6. The method of claim 1 , wherein the active region contact trench has a non-uniform depth.7. The method of claim 1 , wherein:the active ...

SUPER-JUNCTION SCHOTTKY OXIDE PIN DIODE HAVING THIN P-TYPE LAYERS UNDER THE SCHOTTKY CONTACT

A semiconductor chip, which includes an n-type substrate, over which an n-type epitaxial layer having trenches introduced into the epitaxial layer and filled with p-type semiconductor is situated, the trenches each having a heavily doped p-type region on their upper side, the n-type substrate being situated in such a manner, that an alternating sequence of n-type regions having a first width and p-type regions having a second width is present; a first metallic layer, which is provided on the front side of the semiconductor chip, forms an ohmic contact with the heavily doped p-type regions and is used as an anode electrode; a second metallic layer, which is provided on the back side of the semiconductor chip, constitutes an ohmic contact and is used as a cathode electrode; a dielectric layer provided, in each instance, between an n-type region and an adjacent p-type region, as well as p-type layers provided between the n-type regions and the first metallic layer. 1. A semiconductor chip , comprising:{'sup': +', '+, 'an n-type substrate, over which an n-type epitaxial layer having trenches that are introduced into the epitaxial layer and filled with p-type semiconductor material, is situated, the trenches each having a highly doped p-type region on an upper side, and the n-type substrate being situated in such a manner that an alternating sequence of n-type regions having a first width and p-type regions having a second width is present;'}a first metallic layer provided on a front side of the semiconductor chip, which forms an ohmic contact with heavily doped p-type regions and is used as an anode electrode; anda second metallic layer provided on a back side of the semiconductor chip, the second metallic layer constituting an ohmic contact and is used as a cathode electrode, and in each instance, a dielectric layer is provided between an n-type region and an adjacent p-type region;wherein in each instance, a p-type layer is provided between each n-type region and the ...

Power semiconductor apparatus

A power semiconductor apparatus which is provided with a first power semiconductor device using Si as a base substance and a second power semiconductor device using a semiconductor having an energy bandgap wider than the energy bandgap of Si as a base substance, and includes a first insulated metal substrate on which the first power semiconductor device is mounted, a first heat dissipation metal base on which the first insulated metal substrate is mounted, a second insulated metal substrate on which the second power semiconductor device is mounted, and a second heat dissipation metal base on which the second insulated metal substrate is mounted.

SEMICONDUCTOR DEVICE INCLUDING A MOSFET AND SCHOTTKY JUNCTION

A semiconductor device for use in a power supply circuit has first and second MOSFETS. The source-drain path of one of the MOSFETS are coupled to the source-drain path of the other, and a load element is coupled to a connection node of the source-drain paths. The second MOSFET is formed on a semiconductor substrate with a Schottky barrier diode. First gate electrodes of the second MOSFET are formed in trenches in a first region of the semiconductor substrate, while second gate electrodes of the second MOSFET are formed in trenches in a second region of the semiconductor substrate. The first and second gate electrodes are electrically connected together. Portions of the Schottky barrier diode are formed between adjacent ones of the second gate electrodes. A center-to-center spacing between adjacent first gate electrodes is smaller than a center-to-center spacing between adjacent second gate electrodes. 126-. (canceled)27. A semiconductor device including a MOSFET , comprising:a semiconductor substrate having a main surface and a back surface opposite to the main surface; a plurality of trenches disposed in the semiconductor substrate;', 'a well region, in which a channel of the MOSFET is formed, disposed between the plurality of trenches;', 'a gate insulating film of the MOSFET disposed in each of the plurality of trenches;', 'a gate electrode of the MOSFET disposed over the gate insulating film in each of the plurality of trenches; and', 'a source region of the MOSFET disposed in the well region;, 'the semiconductor substrate having a plurality of transistor cell regions, each of the plurality of transistor cell regions includinga source electrode of the MOSFET disposed over the main surface of the semiconductor substrate and being in contact with a top surface of the source region in each of the plurality of transistor cell regions;a drain electrode of the MOSFET disposed over the back surface of the semiconductor substrate and electrically connected to the ...

Light emitting component and light emitting device using same

A light emitting device including a light emitting component is provided, wherein said light emitting comprising an integrated light emitting diode and a semiconductor field effect transistor. The semiconductor field effect transistor may prevent situations such as overheating and voltage instability by controlling a current passing through the light emitting diode as well as enhancing the ability to withstand electrostatic discharge and reducing cost of the light emitting device in multiple aspects.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device provided with a silicon carbide semiconductor substrate, and an ohmic metal layer joined to one surface of the silicon carbide semiconductor substrate in an ohmic contact and composed of a metal material whose silicide formation free energy and carbide formation free energy respectively take negative values. The ohmic metal layer is composed of, for example, a metal material such as molybdenum, titanium, chromium, manganese, zirconium, tantalum, or tungsten. 112-. (canceled)13. A semiconductor device , comprising:a silicon carbide semiconductor substrate having a front surface and a back surface;a front surface side electrode arranged on a front surface side of the silicon carbide semiconductor substrate;a back surface side electrode arranged on a back surface side of the silicon carbide semiconductor substrate;a first intermediate metal layer interposed between the silicon carbide semiconductor substrate and the front surface side electrode, the first intermediate metal layer being in contact with the front surface of the silicon carbide semiconductor substrate at least within a contact area defined on the front surface of the silicon carbide semiconductor substrate; anda peripheral area provided in the silicon carbide substrate in contact with a peripheral edge of the first intermediate metal layer on a surface thereof contacting the first surface, the peripheral area defining the contact area.141. The semiconductor device according to claim , further comprising a second intermediate metal layer interposed between the silicon carbide semiconductor substrate and the back surface side electrode.15. The semiconductor device according to claim 13 , wherein the first intermediate metal layer is in a Schottky contact with the front surface of the silicon carbide semiconductor substrate within the contact area.16. The semiconductor device according to claim 14 , wherein the second intermediate metal layer is in an ohmic contact with the back ...

DEVICES AND METHODS RELATED TO ELECTROSTATIC DISCHARGE PROTECTION BENIGN TO RADIO-FREQUENCY OPERATION

Disclosed are systems, devices and methods for providing electrostatic discharge (ESD) protection for integrated circuits. In some implementations, first and second conductors with ohmic contacts on an intrinsic semiconductor region can function similar to an x-i-y type diode, where each of x and y can be n-type or p-type. Such a diode can be configured to turn on under selected conditions such as an ESD event. Such a structure can be configured so as to provide an effective ESD protection while providing little or substantially nil effect on radio-frequency (RF) operating properties of a device. 1. A device , comprising:a semiconductor substrate having an intrinsic region;a circuit disposed on the semiconductor substrate;a first conductor disposed relative to the intrinsic region and electrically connected to the circuit; anda second conductor disposed relative to the intrinsic region and the first conductor, the second conductor configured so that a potential difference greater than a selected value between the first and second conductors results in a conduction path through the intrinsic region between the first and second conductors.2. The device of wherein the substrate further includes an insulating region disposed between the first and second conductors and above the intrinsic region so that the conduction path through the intrinsic region is away from a surface of the substrate.3. The device of wherein each of the first and second conductors is formed from metal such that the conduction path includes a metal-semiconductor-metal junction.4. The device of wherein the metal-semiconductor-metal junction includes a first turn-on voltage for conduction along a first direction between the first and second conductors claim 5 , and a second turn-on voltage for conduction along a second direction between the first and second conductors.5. The device of wherein the magnitude of the first turn-on voltage is lower than the magnitude of the second turn-on voltage.6. The ...

SEMICONDUCTOR DEVICE

A semiconductor device that can achieve a high-speed operation at a time of switching, and the like. The semiconductor device includes: a p-type buried layer buried within an n-type semiconductor layer; and a p-type surface layer formed in a central portion of each of cells. In a contact cell, the p-type buried layer is in contact with the p-type surface layer. The semiconductor device further includes: a p-type contact layer formed on the p-type surface layer of the contact cell; and an anode electrode provided on the n-type semiconductor layer. The anode electrode forms a Schottky junction with the n-type semiconductor layer and forms an ohmic junction with the p-type contact layer. 1. A semiconductor device including a cell array in which first cells are arranged and second cells are interspersed around the arrangement of the first cells , said semiconductor device comprising:a semiconductor layer having a first conductive type, said semiconductor layer being epitaxially formed on a semiconductor substrate having the first conductive type;a buried layer made of a semiconductor having a second conductive type, said buried layer being buried within said semiconductor layer, said buried layer being provided in a peripheral portion of said first cell and provided throughout an entire region of said second cell;at least one of a first surface layer made of a semiconductor having the second conductive type and a contact layer made of a semiconductor having the second conductive type, said first surface layer being formed in a central portion of said second cell on a surface of said semiconductor layer, said contact layer being formed in a central portion of said second cell on the surface of said semiconductor layer; anda second surface layer made of a semiconductor having the second conductive type, said second surface layer being formed in a central portion of said first cell on the surface of said semiconductor layer,whereinin said second cell, said buried layer is ...

Method of Producing a Vertically Inhomogeneous Platinum or Gold Distribution in a Semiconductor Substrate and in a Semiconductor Device

Method of producing a vertically inhomogeneous platinum or gold distribution in a semiconductor substrate with a first and a second surface opposite the first surface, with diffusing platinum or gold into the semiconductor substrate from one of the first and second surfaces of the semiconductor substrate, removing platinum- or gold-comprising residues remaining on the one of the first and second surfaces after diffusing the platinum or gold, forming a phosphorus- or boron-doped surface barrier layer on the first or second surface, and heating the semiconductor substrate for local gettering of the platinum or gold by the phosphorus- or boron-doped surface barrier layer.

Schottky contact

The present disclosure relates to a Schottky contact for a semiconductor device. The semiconductor device has a body formed from one or more epitaxial layers, which reside over a substrate. The Schottky contact may include a Schottky layer, a first diffusion barrier layer, and a third layer. The Schottky layer is formed of a first metal and is provided over at least a portion of a first surface of the body. The first diffusion barrier layer is formed of a silicide of the first metal and is provided over the Schottky layer. The third layer is formed of a second metal and is provided over the first diffusion barrier layer. In one embodiment, the first metal is nickel, and as such, the silicide is nickel silicide. Various other layers may be provided between or above the Schottky layer, the first diffusion barrier layer, and the third layer.

FUEL-FREE NANOWIRE MOTORS

Techniques and systems are disclosed for locomoting fuel-free nanomotors in a fluid. In one aspect of the disclosed technology, a system for locomoting fuel-free nanomotors can include an electrically-driven nanowire diode formed of two or more segments of different electrically conducting materials, a fluid container, and a mechanism that produces an electric field to drive the nanowire diode to locomote in the fluid. In another aspect, a system for locomoting fuel-free nanomotors can include a magnetically-propelled multi-segment nanowire motor formed of a magnetic segment and a flexible joint segment, a fluid container, and a mechanism that generates and controls a magnetic field to drive the multi-segment nanowire motor to locomote in the fluid. The disclosed fuel-free nanomotors can obviate fuel requirements and can be implemented for practical in vitro and in vivo biomedical applications. 1. A system for locomoting a nanostructure , comprising:a nanostructure configured as a nanowire diode formed of two or more segments of different electrically conducting materials;a container that contains a fluid surrounding the nanostructure; anda mechanism that produces an electric field in the fluid that drives the nanostructure to locomote in the fluid.2. The system of claim 1 , wherein the nanostructure locomotes in the fluid substantially free of a chemical reaction with the two or more segments of the nanostructure.3. The system of claim 1 , wherein the nanowire diode comprises at least one semiconductor segment and a conductor segment.4. The system of claim 3 , wherein the at least one semiconductor segment comprises a polypyrrole (PPy) segment and the conductor segment comprises a cadmium (Cd) segment.5. The system of claim 3 , wherein the at least one semiconductor segment comprises a cadmium selenide (CdSe) segment and the conductor segment comprises a gold (Au) segment.6. The system of claim 1 , wherein the mechanism for producing an electric field includes ...

Monolithic high voltage multiplier

High voltage diode-connected gallium nitride high electron mobility transistor structures or Schottky diodes are employed in a network including high-k dielectric capacitors in a solid state, monolithic voltage multiplier. A superjunction formed by vertical p/n junctions in gallium nitride facilitates operation of the high electron mobility transistor structures and Schottky diodes. A design structure for designing, testing or manufacturing an integrated circuit is tangibly embodied in a machine-readable medium and includes elements of a solid state voltage multiplier.

NITRIDE SEMICONDUCTOR SCHOTTKY DIODE AND METHOD FOR MANUFACTURING SAME

According to an embodiment, a nitride semiconductor Schottky diode includes a first layer including a first nitride semiconductor and a second layer provided on the first layer and including a second nitride semiconductor having a wider band gap than the first nitride semiconductor. The diode also includes an ohmic electrode provided on the second layer and a Schottky electrode provided on the second layer. The second layer includes a region containing an acceptor in the vicinity of the Schottky electrode between the Schottky electrode and the ohmic electrode. 1. A nitride semiconductor Schottky diode comprising:a first layer including a first nitride semiconductor;a second layer provided on the first layer and including a second nitride semiconductor having a wider band gap than the first nitride semiconductor;an ohmic electrode provided on the second layer; anda Schottky electrode provided on the second layer,the second layer including a region containing an acceptor in the vicinity of the Schottky electrode between the Schottky electrode and the ohmic electrode.2. The diode according to claim 1 , wherein the acceptor is fluorine.3. The diode according to claim 1 , wherein the first layer and the second layer are grown in a vertical direction with respect to a (0001) plane.4. The diode according to claim 1 , wherein a thickness of the region containing the acceptor is ½ or less of a thickness of the second layer.5. The diode according to claim 1 , wherein the region containing the acceptor is provided in the vicinity of a surface of the second layer.6. The diode according to claim 1 , wherein a width of the region containing the acceptor is ½ or less of an interval between the Schottky electrode and the ohmic electrode.7. The diode according to claim 1 , wherein the region containing the acceptor is provided in contact with the Schottky electrode.8. The diode according to claim 1 , wherein the first layer is GaN claim 1 , and the second layer is AlGaN.9. The diode ...

TRENCHED SEMICONDUCTOR STRUCTURE

A trenched semiconductor structure comprises a semiconductor substrate, an epitaxial layer, an ion implantation layer, a termination region dielectric layer, an active region dielectric layer, and a first polysilicon layer. The epitaxial layer doped with impurities of a first conductive type is formed on the semiconductor substrate. A plurality of active region trenches and a termination region trench are formed in the epitaxial layer. The ion implantation layer is formed in the active region trenches by doping impurities of a second conductive type. The termination region dielectric layer covers the termination region trench. The active region dielectric layer covers the ion implantation region. The first polysilicon layer covers the active region dielectric layer and fills the active region trenches. The depth of the termination region trench is greater than that of the active region trenches and close to that of the depletion region under reverse breakdown. 1. A trenched semiconductor structure , comprising:a semiconductor substrate doped with impurities of a first conductive type having a first impurity concentration;an epitaxial layer doped with impurities of the first conductive type of a second impurity concentration, formed on the semiconductor substrate;a plurality of active region trenches, formed in the epitaxial layer;at least a termination region trench, formed in the epitaxial layer and away from the active region trenches;an ion implantation layer, formed in a bottom of the active region trenches by doping impurities of a second conductive type ;a termination region dielectric layer, covering the termination region trench;an active region dielectric layer, covering the ion implantation region in the active region trenches; anda first polysilicon layer, covering the active region dielectric layer and filling the active region trenches;wherein, the first impurity concentration is greater than the second impurity concentration, and a depth of the ...

Semiconductor device and manufacturing method thereof

A semiconductor device of the present invention includes a semiconductor layer composed of SiC, a metal layer directly bonded to one face of the semiconductor layer, and a high carbon concentration layer formed on a surface layer portion at one side of the semiconductor layer and containing more highly concentrated carbon than a surface layer portion of the other side. Further, a manufacturing method of a semiconductor device of the present invention includes the steps of forming, on a surface layer portion at one face side of a semiconductor layer composed of SiC, a high carbon concentration layer containing more highly concentrated carbon than a surface layer portion at the other face side by heat treatment and directly bonding metal to the high carbon concentration layer.

SEMICONDUCTOR DIODE AND METHOD OF MANUFACTURE

A diode () is disclosed having improved efficiency, smaller form factor, and reduced reverse biased leakage current. Schottky diodes () are formed on the sidewalls () of a mesa region (). The mesa region () is a cathode of the Schottky diode (). The current path through the mesa region () has a lateral and a vertical current path. The diode () further comprises a MOS structure (), p-type regions (), MOS structures (), and p-type regions (). MOS structure () with the p-type regions () pinch-off the lateral current path under reverse bias conditions. P-type regions (), MOS structures (), and p-type regions () each pinch-off the vertical current path under reverse bias conditions. MOS structure () and MOS structures () reduce resistance of the lateral and vertical current path under forward bias conditions. The mesa region () can have a uniform or non-uniform doping concentration. 114-. (canceled)15. A method of forming a semiconductor device comprising the steps of:forming more than one trench to a first depth in a semiconductor substrate to form at least one mesa region of a first conductivity type;placing dopant of a second conductivity type into a sidewall of the at least one mesa region to form a first region of the second conductivity type, where the dopant is located a first predetermined distance below a major surface of the at least one mesa region;forming a barrier metal overlying a portion of the sidewall of the at least one mesa region to form a Schottky diode; andforming a MOS structure overlying the major surface of the at least one mesa region, where the gate of the MOS structure is coupled to the barrier metal.16. The method of further including the steps of:forming an insulating layer overlying the major surface of the at least one mesa region;forming an insulating layer overlying sidewalls of the at least one mesa region to a first depth;exposing major surfaces of the more than one trench;forming the more than one trench to a second depth;forming an ...

Schottky barrier diode and method for manufacturing schottky barrier diode

A method for manufacturing a Schottky barrier diode includes the following steps. First, a GaN substrate is prepared. A GaN layer is formed on the GaN substrate. A Schottky electrode including a first layer made of Ni or Ni alloy and in contact with the GaN layer is formed. The step of forming the Schottky electrode includes a step of forming a metal layer to serve as the Schottky electrode and a step of heat treating the metal layer. A region of the GaN layer in contact with the Schottky electrode has a dislocation density of 1×10 8 cm −2 or less.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device includes a semiconductor layer and a Schottky electrode, a Schottky junction being formed between the semiconductor layer and the Schottky electrode. The Schottky electrode includes a metal part containing a metal, a Schottky junction being formed between the semiconductor layer and the metal part; and a nitride part around the metal part, the nitride part containing a nitride of the metal, and a Schottky junction being formed between the semiconductor layer and the nitride part.

Semiconductor Devices Including Superjunction Structure and Method of Manufacturing

A semiconductor device includes a semiconductor body having a first surface and a second surface opposite to the first surface. A superjunction structure in the semiconductor body includes drift regions of a first conductivity type and compensation structures alternately disposed in a first direction parallel to the first surface. Each of the charge compensation structures includes a first semiconductor region of a second conductivity type complementary to the first conductivity type and a first trench including a second semiconductor region of the second conductivity type adjoining the first semiconductor region. The first semiconductor region and the first trench are disposed one after another in a second direction perpendicular to the first surface.

SCHOTTKY BARRIER DIODE HAVING A TRENCH STRUCTURE

A TMBS diode is disclosed. In an active portion and voltage withstanding structure portion of the diode, an end portion trench surrounds active portion trenches. An active end portion which is an outer circumferential side end portion of an anode electrode is in contact with conductive polysilicon inside the end portion trench. A guard trench is separated from the end portion trench and surrounds it. A field plate provided on an outer circumferential portion of the anode electrode is separated from the anode electrode, and contacts both part of a surface of n-type drift layer in a mesa region between the end portion trench and the guard trench and the conductive polysilicon formed inside the guard trench. The semiconductor device has high withstand voltage without injection of minority carriers, and relaxed electric field intensity of the trench formed in an end portion of an active portion. 1. A semiconductor device comprising:a cathode layer made of a first conductivity type semiconductor substrate;a drift layer provided on one principal surface of the cathode layer and made of a first conductivity type semiconductor substrate lower in concentration than the cathode layer;at least one first trench and an end portion trench provided in an upper surface of the drift layer so that the first trench is surrounded by the end portion trench;a first conductor embedded in each of the first trench and the end portion trench through an insulating film;an anode electrode provided on the upper surface of the drift layer so that the anode electrode is in contact with the first conductor, and that a Schottky barrier junction is formed between the anode electrode and the drift layer; anda cathode electrode provided on the other principal surface of the cathode layer, wherein:an outer circumferential side end portion of the anode electrode is in contact with the first conductor of the end portion trench;a field plate is provided separately from the anode electrode;a second trench ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

There are provided a semiconductor device that includes a bypass protection unit against surge voltage or the like, achieves good withstand voltage characteristics and low on-resistance (low On-state voltage), has a simple structure, and is used for large-current purpose and a method for producing the semiconductor device. 16.-. (canceled)7. A method for producing a semiconductor device comprising:a step of preparing a GaN substrate having a GaN layer that is in ohmic contact with a supporting substrate;a step of forming an epitaxial layered body of first conductivity type GaN-based drift layer/second conductivity type GaN-based layer/first conductivity type GaN-based cap layer on the GaN substrate;a step of etching the epitaxial layered body on the GaN substrate in a first region to form a FET opening that reaches the first conductivity type GaN-based drift layer;a step of forming a channel-forming layer on an inside surface of the opening; anda step of etching the channel-forming layer and the epitaxial layered body in a second region by masking the first region with a resist film to form an SBD opening that reaches the first conductivity type GaN-based drift layer,wherein an electrode is formed so as to be in Schottky contact with the first conductivity type GaN-based drift layer in the SBD opening and contact the second conductivity type GaN-based layer in the opening.8. (canceled)91. The semiconductor device according to claim , wherein the electrode that is in Schottky contact is located so as to fill the opening in the first conductivity type drift layer and the second conductivity type layer and extend onto the second conductivity type layer in the periphery of the opening.10. The method for producing the semiconductor device according to claim 7 , in the step of forming the SBD opening and the step of forming the electrode claim 7 , a bigger opening than the opening formed in the first conductivity type GaN-based drift layer is formed in the second ...

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES

A method of manufacturing a semiconductor device is disclosed. The method includes forming a first trench and a second trench in an n-type substrate surface, the first trenches being spaced apart from each other, the second trench surrounding the first trenches, the second trench being wider than the first trench. The method also includes forming a gate oxide film on the inner surfaces of the first and second trenches, and depositing an electrically conductive material to the thickness a half or more as large as the first trench width. The method further includes removing the electrically conductive material using the gate oxide film as a stopper layer, forming an insulator film thicker than the gate oxide film, and polishing the insulator film by CMP for exposing the n-type substrate and the electrically conductive material in the first trench. 1. A semiconductor device , comprising:a semiconductor substrate of a first conductivity type;at least one active section trench; anda ring-shaped edge termination trench spaced apart from a nearest one of the at least one active section trench for a predetermined spacing by a mesa region;wherein a height of an upper surface of an insulating film buried in the ring-shaped edge termination trench is substantially the same as the height of an exposed surface of the mesa region.2. The semiconductor device of claim 1 , wherein the ring-shaped edge termination trench is deeper than the at least one active section trench.3. The semiconductor device of claim 1 , wherein the at least one active section trench includes a plurality of active section trenches claim 1 , and a distance between an end portion of one of the plurality of active section trenches and the ring-shaped edge termination trench is narrower than a distance between the plurality of active section trenches. This application is a divisional of application Ser. No. 13/294,169, filed on Nov. 10, 2011. Furthermore, this application claims the benefit of priority of ...

Heterojunction semiconductor device and manufacturing method

Disclosed is a semiconductor device comprising a group 13 nitride heterojunction comprising a first layer having a first bandgap and a second layer having a second bandgap, wherein the first layer is located between a substrate and the second layer; and a Schottky electrode and a first further electrode each conductively coupled to a different area of the heterojunction, said Schottky electrode comprising a central region and an edge region, wherein the element comprises a conductive barrier portion located underneath said edge region only of the Schottky electrode for locally increasing the Schottky barrier of the Schottky electrode. A method of manufacturing such a semiconductor device is also disclosed.

Semiconductor device and method for producing the same

In a MOSFET using a SiC substrate, a source region having low resistance and high injection efficiency is formed without performing a high-temperature heat treatment. A vertical Schottky barrier transistor in which a source region SR on a SiC epitaxial substrate is constituted by a metal material is formed. The source region SR composed of a metal material can be brought into a low resistance state without performing a high-temperature activation treatment. Further, by segregating a conductive impurity DP at an interface between the source region SR composed of a metal material and the SiC epitaxial substrate, the Schottky barrier height can be reduced, and the carrier injection efficiency from the source region SR can be improved.

Rectifier circuit

A rectifier circuit has a rectifier element and a unipolar field-effect transistor connected in series between a first terminal and a second terminal. The rectifier element comprises a first electrode and a second electrode disposed in a direction of a forward current flowing from the first terminal to the second terminal. The field-effect transistor has a gate electrode having a potential identical to a potential at the first electrode, and a source electrode and a drain electrode connected in series to the rectifier element and passing a current depending on the potential at the gate electrode. A breakdown voltage between the gate electrode and drain electrode of the field-effect transistor in a reverse bias mode, where a potential at the second terminal is higher than a potential at the first terminal, being set higher than a breakdown voltage of the rectifier element.

SCHOTTKY BARRIER DIODE AND APPARATUS USING THE SAME

A Schottky barrier diode includes a first semiconductor layer, a LOCOS layer arranged in contact with the first semiconductor layer, a Schottky junction region provided on a contact surface between the first semiconductor layer and a first electrode, a second semiconductor layer connected to the first semiconductor layer and having a higher carrier concentration than that of the first semiconductor layer, and a second electrode forming an ohmic contact with the second semiconductor layer. In this case, the Schottky junction region and the LOCOS layer are in contact. 1. A Schottky barrier diode comprising:a first semiconductor layer;a LOCOS layer arranged in contact with the first semiconductor layer;a Schottky junction region provided on a contact surface between the first semiconductor layer and a first electrode;a second semiconductor layer connected to the first semiconductor layer and having a higher carrier concentration than that of the first semiconductor layer; anda second electrode forming an ohmic contact with the second semiconductor layer, whereinthe Schottky junction region and the LOCOS layer are in contact.2. The Schottky barrier diode according to claim 1 , wherein the second semiconductor layer and the first semiconductor layer are integrally formed on a substrate.3. The Schottky barrier diode according to claim 1 , wherein the first electrode or the second electrode is also formed on at least a part of the LOCOS layer.4. The Schottky barrier diode according to claim 1 , wherein the Schottky junction region is surrounded by the LOCOS layer.5. The Schottky barrier diode according to claim 1 , wherein the LOCOS layer is formed to insulate the first electrode from the second electrode.6. The Schottky barrier diode according to claim 1 , wherein the first semiconductor layer includes an epitaxially grown semiconductor layer.7. The Schottky barrier diode according to claim 1 , wherein the Schottky barrier diode has an island shape on the semiconductor ...

DOUBLE-RECESSED TRENCH SCHOTTKY BARRIER DEVICE

A Schottky barrier device includes a semiconductor substrate, a first contact metal layer, a second contact metal layer and an insulating layer. The semiconductor substrate has a first surface, and plural trenches are formed on the first surface. Each trench includes a first recess having a first depth and a second recess having a second depth. The second recess extends down from the first surface while the first recess extends down from the second recess. The first contact metal layer is formed on the second recess. The second contact metal layer is formed on the first surface between two adjacent trenches. The insulating layer is formed on the first recess. A first Schottky barrier formed between the first contact metal layer and the semiconductor substrate is larger than a second Schottky barrier formed between the second contact metal layer and the semiconductor substrate. 1. A Schottky barrier device , comprising:a semiconductor substrate, having a first surface and a second surface positioned oppositely, and a plurality of trenches formed on the first surface, each trench comprising a first recess having a first depth and a second recess having a second depth, the second recess extending down from the first surface, the first recess extending down from the second recess, and the first depth larger than the second depth;a first contact metal layer at least formed on a surface of the second recess;a second contact metal layer formed on the first surface and between two adjacent trenches; andan insulating layer formed on a surface of the first recess,wherein a first Schottky barrier is formed between the first contact metal layer and the semiconductor substrate, a second Schottky barrier is formed between the second contact metal layer and the semiconductor substrate, and the first Schottky barrier is larger than the second Schottky barrier.2. The Schottky barrier device according to claim 1 , wherein a material of the semiconductor substrate comprises silicon ...

Schottky-barrier device with locally planarized surface and related semiconductor product

The present disclosure is related to alleviation of at least some of the above drawbacks of the prior art and to provide an improved alternative to the prior art. Generally, at least some of the embodiments are related to a high voltage power conversion semiconductor device, in particular a SiC Schottky-barrier power rectifier device, having a surface (of the drift layer) with improved smoothness. Further, at least some of the embodiments are related to a method of manufacturing a power rectifier device with reduced leakage currents.

Semiconductor Arrangement Having a Schottky Diode

A semiconductor assemblage of a super-trench Schottky barrier diode (STSBD) made up of an n substrate, an n-epilayer, trenches etched into the n-epilayer that have a width and a distance from the n substrate, mesa regions between the adjacent trenches having a width, a metal layer on the front side of the chip that is a Schottky contact and serves as an anode electrode, and a metal layer on the back side of the chip that is an ohmic contact and serves as a cathode electrode, wherein multiple Schottky contacts having a width or distance and a distance between the Schottky contacts, and between the Schottky contact as anode electrode and the first Schottky contact, are located on the trench wall. 119-. (canceled)20. A semiconductor assemblage , comprising:{'sup': +', '+, 'a super-trench Schottky barrier diode (STSBD) having an n substrate, an n-epilayer, trenches etched into the n-epilayer that have a width and a distance from the n substrate, mesa regions between the adjacent trenches having a width, a metal layer on a front side of the chip that is a Schottky contact and serves as an anode electrode, a metal layer on a back side of the chip that is an ohmic contact and serves as a cathode electrode, multiple Schottky contacts having a width or distance and a distance between the Schottky contacts, and between the Schottky contact as anode electrode and the first Schottky contact, being located on the trench wall.'}21. The semiconductor assemblage of claim 20 , wherein the Schottky contacts are floated on the trench wall.22. The semiconductor assemblage of claim 20 , wherein the metal layer on the front side of the chip claim 20 , which is a Schottky contact and serves as an anode electrode claim 20 , covers the trench wall up to a depth.23. The semiconductor assemblage of claim 20 , wherein the metal layer on the front side of the chip fills up the trenches up to a depth.24. The semiconductor assemblage of claim 20 , wherein the last floated Schottky contact covers ...

Rectifierarrangement having schottky diodes

A rectifier system having press-in diodes that contain a Schottky diode as semiconductor element. The Schottky diodes are operated in an operating range in which the diode losses increase as the temperature increases.

Semiconductor device

A semiconductor device includes a substrate, a channel layer that is formed above the substrate, where the channel layer is made of a first nitride series compound semiconductor, a barrier layer that is formed on the channel layer, a first electrode that is formed on the barrier layer, and a second electrode that is formed above the channel layer. Here, the barrier layer includes a block layers and a quantum level layer. The block layer is formed on the channel layer and made of a second nitride series compound semiconductor having a larger band gap energy than the first nitride series compound semiconductor, and the quantum level layer is made of a third nitride series compound semiconductor having a smaller band gap energy than the second nitride series compound semiconductor, and has a quantum level formed therein.

Semiconductor device and method for manufacturing same

A semiconductor device having a high withstand voltage in which a stable withstand voltage can be obtained and a method for manufacturing the same. A JTE region having a second conductivity type is formed in a portion on an outer peripheral end side of an SiC substrate from a second conductivity type SiC region in a vicinal portion of a surface on one of sides in a thickness direction of a first conductivity type SiC epitaxial layer. A first conductivity type SiC region having a higher concentration of an impurity having the first conductivity type than that of the SiC epitaxial layer is formed in at least a vicinal portion of a surface on one of sides in a thickness direction of a portion in which the JTE regions are bonded to each other.

METHODS OF MANUFACTURING THE GALLIUM NITRIDE BASED SEMICONDUCTOR DEVICES

Gallium nitride (GaN) based semiconductor devices and methods of manufacturing the same. The GaN-based semiconductor device may include a heterostructure field effect transistor (HFET) or a Schottky diode, arranged on a heat dissipation substrate. The HFET device may include a GaN-based multi-layer having a recess region; a gate arranged in the recess region; and a source and a drain that are arranged on portions of the GaN-based multi-layer at two opposite sides of the gate (or the recess region). The gate, the source, and the drain may be attached to the heat dissipation substrate. The recess region may have a double recess structure. While such a GaN-based semiconductor device is being manufactured, a wafer bonding process and a laser lift-off process may be used. 1. A gallium nitride (GaN) based semiconductor device comprising:a heat dissipation substrate; anda heterostructure field effect transistor (HFET) device arranged on the heat dissipation substrate, a GaN-based multi-layer having a recess region close to the heat dissipation layer;', 'a gate arranged in the recess region; and', 'a source and a drain that are arranged on portions of the GaN-based multi-layer at two opposite sides of the gate, and, 'wherein the HFET device comprisesthe gate, the source, and the drain are attached to the heat dissipation substrate.2. The GaN-based semiconductor device of claim 1 , wherein the recess region has a double recess structure.3. The GaN-based semiconductor device of claim 1 , wherein the GaN-based multi-layer comprises a 2-dimensional electron gas (2DEG) layer.4. The GaN-based semiconductor device of claim 1 , wherein the GaN multi-layer comprises an AlGN layer and an AlGaN layer which are sequentially disposed from the heat dissipation substrate claim 1 , and{'sub': y', '1-y, 'in the AlGN layer, 0.1≦y≦0.6, and'}{'sub': x', '1-, 'in the AlGaN layer, 0≦x<0.01.'}5. The GaN-based semiconductor device of claim 4 , wherein the GaN-based multi-layer further comprises a ...

Multifunctional zinc oxide nano-structure-based circuit building blocks for re-configurable electronics and optoelectronics

A vertically integrated reconfigurable and programmable diode/memory resistor (1D1R) and thin film transistor/memory resistor (1T1R) structures built on substrates are disclosed.

Semiconductor laminate and process for production thereof, and semiconductor element

A semiconductor laminate having small electric resistivity in the thickness direction; a process for producing the semiconductor laminate; and a semiconductor element equipped with the semiconductor laminate. include a semiconductor laminate including a Ga 2 0 3 substrate; an AlGalnN buffer layer which is formed on the Ga 2 0 3 substrate; a nitride semiconductor layer which is formed on the AlGalnN buffer layer and contains Si; and an Si-rich region which is formed in an area located on the AlGalnN buffer layer side in the nitride semiconductor layer and has an Si concentration of 5×10 18 /cm 3 or more.

SEMICONDUCTOR STRUCTURE FOR ANTENNA SWITCHING CIRCUIT AND MANUFACTURING METHOD THEREOF

A manufacturing method for antenna switching circuit includes the following steps of: providing a GaAs wafer, which includes a capping layer; disposing an isolation layer to the GaAs wafer for forming a device area; and disposing a gate metal on the capping layer within the device area, wherein an interface between the gate metal and the capping layer forms a Schottky contact, and the Schottky contact is parallel connected with an impedance. The present invention also discloses a semiconductor structure for antenna switching circuit. 1. A manufacturing method of a semiconductor structure for antenna switching circuit , comprising steps of:providing a GaAs wafer having a capping layer;disposing an isolation layer to the GaAs wafer to form a device area; anddisposing a gate metal to the capping layer within the device area, wherein an interface between the gate metal and the capping layer forms a Schottky contact that is parallel connected to an impedance.2. The manufacturing method as recited in claim 1 , wherein the GaAs wafer includes a buffer layer claim 1 , a channel layer claim 1 , a space layer claim 1 , a donor layer and the capping layer.3. The manufacturing method as recited in claim 1 , wherein the isolation layer is made by insulating material and disposed to the GaAs wafer by an ion implantation.4. The manufacturing method as recited in claim 1 , wherein the gate metal is disposed on the capping layer by a vapor deposition.5. The manufacturing method as recited in claim 1 , further comprising steps of:disposing a first ohmic layer and a second ohmic layer on the capping layer; anddisposing a first metal layer on the first ohmic layer and the gate metal, and disposing a second metal on the second ohmic layer.6. A semiconductor structure for an antenna switching circuit claim 1 , comprising:a buffer layer;a channel layer disposed on the channel layer;a space layer disposed on the channel layer;a donor layer disposed on the space layer;a capping layer ...

TRENCH SCHOTTKY DIODE

A trench Schottky diode is described, which has a highly doped substrate of a first conductivity type and an epitaxial layer of the same conductivity type that is applied to the substrate. At least two trenches are introduced into the epitaxial layer. The epitaxial layer is a stepped epitaxial layer that has two partial layers of different doping concentrations. 1. A trench Schottky diode comprising a highly doped substrate of a first conductivity type (n) and an epitaxial layer of the same conductivity type (n) applied to the substrate , at least two trenches being introduced into the epitaxial layer ,{'b': 2', '2, 'i': a,', 'b, 'wherein the epitaxial layer is a stepped epitaxial layer that has two partial layers () of different doping concentrations.'}22121ba. The trench Schottky diode as recited in claim 1 , wherein the first partial layer () is contacted by the substrate () and has a higher doping concentration than the second partial layer () claim 1 , which is not contacted by the substrate ().3. The trench Schottky diode as recited in claim 1 , whereinit is a trench MOS barrier Schottky diode;{'b': '5', 'at the rear side thereof, a first metal layer () used as a cathode electrode is provided;'}{'b': 4', '2', '4, 'i': 'a', 'at the front side thereof, a second metal layer () is provided that is used as an anode electrode and forms a Schottky contact with the second partial layer (); and, between the second metal layer (); and'}{'b': '7', 'the side walls of the trenches, a layer () of dielectric material is provided.'}4. The trench Schottky diode as recited in claim 3 , whereinit is realized as a chip that has a chip surface region and a lower MOS region;{'b': 2', '7', '4, 'i': 'b', 'the first partial layer (), together with the layer () of dielectric material, and the second metal layer () form the lower MOS region;'}{'b': 2', '4, 'i': 'a', 'the second partial layer () and the second metal layer () form the chip surface region; and'}the breakdown voltage of the ...

SCHOTTKY DIODE

A Schottky diode has: a semiconductor layer stack including a GaN layer formed over a substrate and an AlGaN layer formed on the GaN layer and having a wider bandgap than the GaN layer; an anode electrode and a cathode electrode which are formed at an interval therebetween on the semiconductor layer stack; and a block layer formed in a region between the anode electrode and the cathode electrode so as to contact the AlGaN layer. A part of the anode electrode is formed on the block layer so as not to contact the surface of the AlGaN layer. The barrier height between the anode electrode and the block layer is greater than that between the anode electrode and the AlGaN layer. 1. A Schottky diode , comprising:a substrate;a semiconductor layer stack including a first nitride semiconductor layer formed over the substrate and a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a wider bandgap than the first nitride semiconductor layer;an anode electrode and a cathode electrode which are formed at an interval therebetween on the semiconductor layer stack; anda block layer formed in a region between the anode electrode and the cathode electrode so as to contact the second nitride semiconductor layer, whereina part of the anode electrode is formed on the block layer so as not to contact a surface of the second nitride semiconductor layer, anda barrier height between the anode electrode and the block layer is greater than that between the anode electrode and the second nitride semiconductor layer.2. The Schottky diode of claim 1 , whereinthe semiconductor layer stack includes multiple ones of the first nitride semiconductor layer and multiple ones of the second nitride semiconductor layer, andthe first nitride semiconductor layers and the second nitride semiconductor layers are alternately stacked.3. The Schottky diode of claim 1 , whereinthe semiconductor layer stack has a stepped portion formed by removing a part of the second ...

SILICON CARBIDE SCHOTTKY DIODE

A SiC Schottky diode which includes a Schottky barrier formed on a silicon face 4H-SiC body. 1a SiC substrate of one conductivity;a silicon face SiC epitaxial body of said one conductivity formed on a first surface of a said SiC substrate;a Schottky metal barrier formed on said silicon face of said SiC epitaxial body;a back power electrode on a second surface of said SiC substrate opposite said first surface of said SiC substrate.. A semiconductor device, comprising: This application is a continuation of and claims the benefit of co-pending, commonly-owned U.S. patent application Ser. No. 11/581,536, with Attorney Docket No. VISH-IR257, filed on Oct. 16, 2006, by Giovanni Richieri, and titled “Silicon carbide schottky diode,” which claims the benefit of and priority to the provisional patent application, Ser. No. 60/728,728, with Attorney Docket No. VISH-IR257.Pro, filed on Oct. 20, 2005, by Giovanni Richieri, and titled “Silicon carbide schottky diode,” each of which are hereby incorporated by reference in their entirety.The present invention relates to Schottky diodes and in particular to SiC Schottky diodes.Although the main intrinsic parameters in Silicon Carbide material have not been exhaustively studied, several experimental and theoretical studies have been performed in recent years in order to better describe the current transport in ohmic and rectifying contact on SiC.It has been known that in Schottky diodes the metal semiconductor interface (MST) between the Schottky barrier metal and the semiconductor plays a crucial role in the electrical performance of electronic devices. Many factors can worsen the performance of the MSI in a Schottky diode. For example, the quality of the semiconductor surface prior to the deposition of the Schottky barrier metal can cause the device to exhibit characteristics that are different from the ideal characteristics.Current-voltage (I-V) and capacitance-voltage (C-V) characterizations are useful methods for determining the ...

Trench-based power semiconductor devices with increased breakdown voltage characteristics

Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.

Method and system for in-situ and regrowth in gallium nitride based devices

A method of regrowing material includes providing a III-nitride structure including a masking layer and patterning the masking layer to form an etch mask. The method also includes removing, using an in-situ etch, a portion of the III-nitride structure to expose a regrowth region and regrowing a III-nitride material in the regrowth region.

DIODE, SEMICONDUCTOR DEVICE, AND MOSFET

Disclosed is a technique capable of reducing loss at the time of switching in a diode. A diode disclosed in the present specification includes a cathode electrode, a cathode region made of a first conductivity type semiconductor, a drift region made of a low concentration first conductivity type semiconductor, an anode region made of a second conductivity type semiconductor, an anode electrode made of metal, a barrier region formed between the drift region and the anode region and made of a first conductivity type semiconductor having a concentration higher than that of the drift region, and a pillar region formed so as to connect the barrier region to the anode electrode and made of a first conductivity type semiconductor having a concentration higher than that of the barrier region. The pillar region and the anode are connected through a Schottky junction. 1. A diode comprising:a cathode electrode;a cathode region made of a first conductivity type semiconductor;a drift region made of a low concentration first conductivity type semiconductor;an anode region made of a second conductivity type semiconductor;an anode electrode made of metal;a barrier region formed between the drift region and the anode region and made of a first conductivity type semiconductor having a concentration higher than that of the drift region; anda pillar region formed so as to connect the barrier region to the anode electrode and made of a first conductivity type semiconductor having a concentration higher than that of the barrier region,wherein the pillar region and the anode electrode are connected through a Schottky junction.2. The diode according to claim 1 , further comprising an electric field progress preventing region formed between the barrier region and the drift region and made of the second conductivity type semiconductor.3. The diode according to claim 1 , wherein a trench extending from the anode region to the drift region is formed claim 1 , anda trench electrode which is ...

RECTIFIER OF ALTERNATING-CURRENT GENERATOR FOR VEHICLE

In a rectifier device () for full-wave rectifying an output of a vehicle alternating-current generator (), a schottky barrier diode having a characteristic whose forward voltage drop with respect to a forward current is small and whose reverse leakage current is small, is used as a rectifier semiconductor element (),() constituting the rectifier device (). 1. A rectifier device of a vehicle alternating-current generator that performs full-wave rectification of an output of the vehicle alternating-current generator , wherein , as a rectifier semiconductor element constituting the rectifier device , a diode is used which has a characteristic whose forward voltage drop with respect to a forward current is smaller than that of a PN junction diode , and whose reverse leakage current is as small as the same level as that of the PN junction diode.2. The rectifier device of a vehicle alternating-current generator of claim 1 , wherein claim 1 , as the diode claim 1 , a schottky barrier diode having a junction barrier schottky structure is used so as to suppress the reverse leakage current.3. The rectifier device of a vehicle alternating-current generator of claim 2 , wherein the junction barrier schottky structure includes a plurality of P-type semiconductor regions formed under a schottky electrode claim 2 , so that PN junction portions are formed inside the schottky barrier diode. This invention relates to rectifier devices of alternating-current generators for on-vehicle use, and in particular, to rectifier devices of vehicle alternating-current generators in which schottky barrier diodes are used as semiconductor devices constituting the rectifier devices.is a circuit configuration diagram for showing an example of conventional rectifier device of a vehicle alternating-current generator.The conventional rectifier device with a vehicle alternating-current generator is configured with: an alternating-current generator comprising a field coil that is activated by a not ...

Method and system for edge termination in gan materials by selective area implantation doping

A method for fabricating edge termination structures in gallium nitride (GaN) materials includes providing an n-type GaN substrate having a first surface and a second surface, forming an n-type GaN epitaxial layer coupled to the first surface of the n-type GaN substrate, and forming one or more p-type regions in the n-type GaN epitaxial layer by using a first ion implantation. At least one of the one or more p-type regions includes an edge termination structure.

Method for manufacturing silicon carbide semiconductor device

A surface of a silicon carbide substrate on which a graphite layer is formed is covered with a metal layer which can form carbide. Then, the silicon carbide substrate is annealed to cause reaction between a metal in the metal layer which can form carbide and carbon in the graphite layer so as to change the graphite layer between the metal layer which can form carbide and the silicon carbide substrate to a metal carbide layer. Thus, the graphite layer is removed. The adhesion between the metal layer which can form carbide and the silicon carbide substrate can be improved so that separation of the metal layer which can form carbide can be suppressed. Graphite deposits can be suppressed due to the removal of the graphite layer so that separation of a wiring metal film formed on a surface of the metal layer which can form carbide can be suppressed.

Semiconductor Heterostructure Diodes

Planar Schottky diodes for which the semiconductor material includes a heterojunction which induces a 2DEG in at least one of the semiconductor layers. A metal anode contact is on top of the upper semiconductor layer and forms a Schottky contact with that layer. A metal cathode contact is connected to the 2DEG, forming an ohmic contact with the layer containing the 2DEG. 1. A diode , comprising:a semiconductor material comprising a first III-N material layer and a second III-N material layer, wherein a 2DEG channel is in the first III-N material layer because of a compositional difference between the first III-N material layer and the second III-N material layer;a first insulator layer on the semiconductor material; anda first terminal and a second terminal, wherein the first terminal comprises an anode that forms a Schottky contact with the semiconductor material and includes an extending portion that extends over the first insulator layer, and a second terminal is a single cathode in ohmic contact with the 2DEG channel.2. The diode of claim 1 , wherein when the diode is forward biased claim 1 , current flows from the anode to the cathode predominantly through a Schottky barrier and through the 2DEG channel.3. The diode of claim 1 , wherein the first III-N material layer includes GaN and the second III-N material layer includes AlGaN.4. The diode of claim 1 , wherein the extending portion comprises a field plate.5. The diode of claim 1 , wherein the extending portion comprises multiple field plates formed as a plurality of steps.6. The diode of claim 5 , wherein the first insulator layer surrounds the anode and is between the field plate and the second III-N material layer.7. An assembly claim 5 , comprising:{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'the diode of ; and'}a III-N transistor, wherein a terminal of the two terminals of the diode is electrically connected to a terminal of the III-N transistor.8. The assembly of claim 7 , wherein the terminal of ...

METHOD OF FORMING GROUP III NITRIDE SEMICONDUCTOR, METHOD OF FABRICATING SEMICONDUCTOR DEVICE, GROUP III NITRIDE SEMICONDUCTOR DEVICE, METHOD OF PERFORMING THERMAL TREATMENT

A method of forming a group III nitride semiconductor comprises: preparing a group III nitride semiconductor which contains a p-type dopant or an n-type dopant; and performing a treatment of the group III nitride semiconductor by using a reducing gas and a nitrogen source gas to form a conductive group III nitride semiconductor. The treatment includes performing a first treatment of the group III nitride semiconductor by using a first treatment gas including the reducing gas and the nitrogen source gas, which are supplied to a treatment apparatus at a first flow rate and a second flow rate, respectively, and after the first treatment is performed, performing a second treatment of the group III nitride semiconductor by using a second treatment gas including the reducing gas and the nitrogen source gas, which are supplied to the treatment apparatus at a third flow rate and a fourth flow rate, respectively. 1. A method of forming a group III nitride semiconductor , comprising the steps of:preparing a group III nitride semiconductor, the group III nitride semiconductor containing at least one of a p-type dopant and an n-type dopant; andperforming a treatment of the group III nitride semiconductor by using a reducing gas and a nitrogen source gas to form a conductive group III nitride semiconductor, performing a first thermal treatment of the group III nitride semiconductor by using a first treatment gas including the reducing gas and the nitrogen source gas, the reducing gas and the nitrogen source gas of the first treatment being supplied to a treatment apparatus at a first flow rate and a second flow rate, respectively, and', 'performing a second thermal treatment of the group III nitride semiconductor by using a second treatment gas including the reducing gas and the nitrogen source gas after the first thermal treatment is performed, the reducing gas and the nitrogen source gas of the second treatment gas being supplied to the treatment apparatus at a third flow rate ...

WIDE GAP SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

A wide gap semiconductor device has a substrate and a Schottky electrode. The substrate is made of a wide gap semiconductor material and has a first conductivity type. The Schottky electrode is arranged on the substrate to be in contact therewith and is made of a single material. The Schottky electrode includes a first region having a first barrier height and a second region having a second barrier height higher than the first barrier height. The second region includes an outer peripheral portion of the Schottky electrode. Thus, a wide gap semiconductor device capable of achieving less leakage current and a method for manufacturing the same can be provided. 1. A wide gap semiconductor device , comprising:a substrate made of a wide gap semiconductor material and having a first conductivity type; anda Schottky electrode arranged on said substrate to be in contact therewith and made of a single material,said Schottky electrode including a first region having a first barrier height and a second region having a second barrier height higher than said first barrier height, andsaid second region including an outer peripheral portion of said Schottky electrode.2. The wide gap semiconductor device according to claim 1 , whereinsaid wide gap semiconductor material is silicon carbide.3. The wide gap semiconductor device according to claim 1 , whereina width of said second region in a direction in parallel to a main surface of said substrate and from said outer peripheral portion of said Schottky electrode toward a center is not smaller than 2 μm and not greater than 100 μm.4. The wide gap semiconductor device according to claim 1 , whereinsaid substrate includes a second conductivity type region in contact with said outer peripheral portion of said Schottky electrode.5. A method for manufacturing a wide gap semiconductor device claim 1 , comprising the steps of:preparing a substrate made of a wide gap semiconductor material and having a first conductivity type; andforming a ...

WIDE GAP SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

A wide gap semiconductor device includes a substrate and a Schottky electrode. The substrate formed of a wide gap semiconductor material has a main face, and includes a first-conductivity-type region and a second-conductivity-type region. The Schottky electrode is arranged adjoining the main face of the substrate. At the substrate, there is foamed a trench having a side face continuous with the main face and a bottom continuous with the side face. The Schottky electrode adjoins the first-conductivity-type region at the side face of the trench and the main face, and adjoins the second-conductivity-type region at the bottom of the trench. The side face of the trench is inclined relative to the main face of the substrate. 1. A wide gap semiconductor device comprising:a substrate formed of a wide gap semiconductor material, having a main face, and including a first-conductivity-type region and a second-conductivity-type region, anda Schottky electrode arranged adjoining said main face of said substrate,said substrate having a trench formed, said trench including a side face continuous with said main face, and a bottom continuous with said side face,said Schottky electrode adjoining said first-conductivity-type region at said side face of said trench and said main face, and adjoining said second-conductivity-type region at said bottom of said trench,said side face of said trench inclined relative to said main face of said substrate.2. The wide gap semiconductor device according to claim 1 , wherein said wide gap semiconductor material includes silicon carbide.3. The wide gap semiconductor device according to claim 1 , wherein an angle of said main face relative to said side face is greater than or equal to 50° and less than or equal to 85°.4. The wide gap semiconductor device according to claim 1 , whereinsaid trench includes a first trench and a second trench adjacent to each other,said second-conductivity-type region includes a first second-conductivity-type region ...

Tunable Schottky Diode

A device includes a semiconductor substrate, first and second electrodes supported by the semiconductor substrate, laterally spaced from one another, and disposed at a surface of the semiconductor substrate to form an Ohmic contact and a Schottky junction, respectively. The device further includes a conduction path region in the semiconductor substrate, having a first conductivity type, and disposed along a conduction path between the first and second electrodes, a buried region in the semiconductor substrate having a second conductivity type and disposed below the conduction path region, and a device isolating region electrically coupled to the buried region, having the second conductivity type, and defining a lateral boundary of the device. The device isolating region is electrically coupled to the second electrode such that a voltage at the second electrode during operation is applied to the buried region to deplete the conduction path region.