Verfahren zum Herstellen einer Halbleiteranordnung.

METHOD AND DEVICE FOR FIXING CHIPS BY ENERGY BEAMS

Semi-conductor device

... 943,860. Semi-conductor devices. SIEMENS-SCHUCKERTWERKE A.G. June 21, 1961 [June 21, 1960], No. 22537/61. Drawings to Specification. Heading H1K. A semi-conductor device 3 is mounted on a carrier plate 2 by a sintered plate 1 whose composition varies from the semi-conductor to the carrier so as to match the coefficients of expansion both of the semi-conductor device and of the carrier plate. When the semi-conductor device is a silicon rectifier the plate may vary from molybdenum/nickel in the ratio 99: 1, through molybdenum/copper 50: 50 to all copper. In other arrangements tungsten nickel and copper may be used or tungsten nickel and silver.

Coil isolators

SEALING ELECTRICAL FEEDTHROUGH

Copper wire for bonding a semiconductor device

The present invention eliminates the problems associated with the use of oxygen-free copper and other high-purity copper materials as bonding wires. At least one rare earth element, or at least one element selected from the group consisting of Mg, Ca, Ti, Zr, Hf, Li, Na, K, Rb and Cs, or the combination of at least one rare earth element and at least one elemented selected from the above-specified group is incorporated in high-purity copper as a refining component in an amount of 0.1-100 ppm on a weight basis, and the high-purity copper is subsequently refined by zone melting. The very fine wire drawn from the so refined high-purity copper has the advantage that it can be employed in high-speed ball bonding of a semiconductor chip with a minimum chance of damaging the bonding pad on the chip by the ball forming at the tip of the wire.

SEMICONDUCTOR DEVICES

VERFAHREN UND VORRICHTUNG ZUM HERSTELLEN VON VERBINDUNGEN ZWISCHEN DEN ANSCHLUSSSTELLEN EINES BAUELEMENTES UND AEUSSEREN KONTAKTSTELLEN

COMPOSITIONS; PROCEDURE AND DEVICES FOR LEAD FREE HIGH TEMPERATURE SOLDER

Circuit structure having a flip-mounted matrix of devices

Solar cell and magnetically self-assembled solar cell assembly

Hybridization of polynucleotides conjugated with chromophores and fluorophores to generate donor-to-donor energy transfer system

Electrical contact structures from flexible wire

METHOD FOR LOW TEMPERATURE BONDING AND BONDED STRUCTURE

A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO2. The surfaces to be bonded are polished to a high degree of smoothness and planarity (2). VSE may use reactive ion etching or wet etching to slighthly etch the surfaces being bonded (3). The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces (4).

GLASS MATERIAL FOR USE AT HIGH FREQUENCIES

The aim of the invention is to improve the high-frequency characteristics of high-frequency substrates or high-frequency conductor assemblies. To achieve this, the invention provides a glass material for producing insulation layers for high-frequency conductor assemblies. Said material is applied as a layer, in particular with a layer thickness ranging between 0.05 .mu.m and 5 mm, with a tangent of loss angle tan.delta. in at least one frequency range above 1 GHz of less than or equal to 70*10-4.

HYBRIDIZATION OF POLYNUCLEOTIDES CONJUGATED WITH CHROMOPHORES AND FLUOROPHORES TO GENERATE DONOR-TO-DONOR ENERGY TRANSFER SYSTEM

... 2123133 9309128 PCTABS00022 The present invention contemplates chromophore-containing polynucleotides having at least two donor chromophores operatively linked to the polynucleotide by linker arms, such that the chromophores are positioned by linkage along the length of the polynucleotide at a donor-donor transfer distance, and at least one fluorescing acceptor chromophore operatively linked to the polynucleotide by a linker arm, such that the fluorescing acceptor chromophore is positioned by linkage at a donor-acceptor transfer distance from at least one of the donor chromophores, to form a photonic structure for collecting photonic energy and transferring the energy to an acceptor chromophore, and methods using the photonic structures.

Halbleitergerät

Raddrizzatore in miniatura

Method and device for producing electrical connections between a component and external connecting elements

SEMICONDUCTOR COMPONENT, PROCEDURE FOR ITS PRODUCTION AND USE OF THE SEMICONDUCTOR COMPONENT.

PROCEDURE FOR THE PRODUCTION OF ELECTRICAL CONTACTS AT SEMICONDUCTOR COMPONENTS.

Purifying wire from a Gold-Legierung, procedure for its production and its use.

Purifying wire from a Gold-Legierung, procedure for its production and its use.

For bare chip IC of warping reducing the assembly of the compensating TCE of the package substrate,

Composant semiconducteur possédant une jonction formée dans une partie de l'étendue d'une surface de semiconducteur, et son procédé de fabrication.

COMPOSANT SEMI-CONDUCTEUR COMPORTANT UNE COUCHE DE CONTACT QUI EST PLACEE AVEC TOUTE SA SURFACE DIRECTEMENT CONTRE SON SUBSTRAT SEMI-CONDUCTEUR, MAIS NE PRESENTE QUE DANS UNE PARTIE DE L'ETENDUE DE SA SURFACE UNE JONCTION CONDUCTRICE AVEC LE SUBSTRAT SEMI-CONDUCTEUR. LA COUCHE DE CONTACT4 N'EST ALLIEE QUE DANS LA PARTIE6 DE SON ETENDUE AVEC LE SUBSTRAT SEMI-CONDUCTEUR1. L'INVENTION EST APPLICABLE A DES DIODES LASERS, MAIS AUSSI A DES COMPOSANTS SEMI-CONDUCTEURS QUELCONQUES, COMME PAR EXEMPLE DES CIRCUITS INTEGRES.

PROCESS AND APPARATUS TO CONNECT CONDUCTING FILAMENTS HAVE SURFACES OF TERMINAL FOR THE REALIZATION OF ELECTRONICS COMPONENTS OF THE JUST TYPE AND SIMILAR

PACKAGE AND METHOD FOR CONNECTING A SET OF CONDUCTORS TO A FLIP CHIP SEMICONDUCTOR WAFER

ALLOY WIRE Of FINE GOLD TO CONNECT a TRANSISTOR

MACHINE FOR ATTACHING THE CONNECTING WIRES TO THE CONNECTION POINTS OF A SEMICONDUCTOR COMPONENT AND OF THE HOUSING ACCOMMODATING THE SEMICONDUCTOR COMPONENT

BALANCED CIRCUITRY FOR REDUCING INDUCTIVE NOISE OF EXTERNAL CHIP INTERCONNECTIONS

EPOXY RESIN COMPOSITION AND DIE BONDING MATERIAL COMPRISING THE COMPOSITION

Method For Low Temperature Bonding And Bonded Structure

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES

BONDING WIRE FOR SEMICONDUCTOR DEVICE

A bonding wire for semiconductor device that attains improvement to ball part formability and junction easiness, excelling in loop controllability, and that enhances bonding strength at wedge junction, ensuring industrial production applicability, and that is composed mainly of copper cheaper than gold wire. There is provided a bonding wire for semiconductor device, comprising a core material composed mainly of copper and, superimposed thereon, a skin layer of conductive metal whose composition is different from that of the core material, characterized in that the skin layer is composed mainly of at least two members selected from among gold, palladium, platinum, rhodium, silver and nickel, and that in the skin layer, there is a region with a gradient of concentration of one or both of major component metal and copper in the direction of wire diameter. © KIPO & WIPO 2007 ...

METHOD FOR FABRICATING SUBSTRATE JOINT BODY, SUBSTRATE JOINT BODY AND ELECTRO-OPTICAL APPARATUS TO SECURE CONDUCTION OF DEVICE AND INTERCONNECTION SUBSTRATE WITHOUT DAMAGING DEVICE AND INTERCONNECTION SUBSTRATE

PURPOSE: A method for fabricating a substrate joint body is provided to secure conduction of a device and an interconnection substrate without damaging the device and the interconnection substrate by increasing the pressurizing quantity of heat. CONSTITUTION: An electrode pad(17) of an interconnection substrate(3) is separated from an electrode pad(13a) of an electrical device(13) by a predetermined interval so that the interconnection substrate is mechanically connected to the electrical device. A bump(52) is grown from the electrode pad of the interconnection substrate and/or the electrode pad of the electrical device to electrically interconnect the interconnection substrate and the electrical device. © KIPO 2006 ...

CURE CATALYST, COMPOSITION, ELECTRONIC DEVICE AND ASSOCIATED METHOD

A cure catalyst is provided. The cure catalyst may include a Lewis acid and one or both of a nitrogen-containing molecule or a non-tertiary phosphine. The nitrogen-containing molecule may include a mono amine or a heterocyclic aromatic organic compound. A curable composition may include the cure catalyst. An electronic device may include the curable composition. Methods associated with the foregoing are provided also. © KIPO & WIPO 2008 ...

Electric circuit board

The present invention provides an electric circuit board capable of connecting an IC or a semiconductor chip with high reliability. An electrode part 20 to which the metal electrode (bump) of an IC circuit will be connected from an upper part is formed on the glass substrate 11 of a liquid crystal display device. The electrode part 20 is constituted by opening an inter-layer insulating film 23 in a part corresponding to metal wiring 22 and forming a land-like electrode pad 25 in this opened part. In the present invention, the plane shape of the electrode pad 25 is made smaller than the opened part of the inter-layer insulating film 23. Thus the flatness of the peripheral surface of the electrode 20 is improved.

Methods of fabricating nanostructures and nanowires and devices fabricated therefrom

One-dimensional nanostructures having uniform diameters of less than approximately 200 nm. These inventive nanostructures, which we refer to as ""nanowires"", include single-crystalline homostructures as well as heterostructures of at least two single-crystalline materials having different chemical compositions. Because single-crystalline materials are used to form the heterostructure, the resultant heterostructure will be single-crystalline as well. The nanowire heterostructures are generally based on a semiconducting wire wherein the doping and composition are controlled in either the longitudinal or radial directions, or in both directions, to yield a wire that comprises different materials. Examples of resulting nanowire heterostructures include a longitudinal heterostructure nanowire (LOHN) and a coaxial heterostructure nanowire (COHN).

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

A substrate (1) and a semiconductor chip (5) are flip-chip bonded. The periphery of a connecting pad (3) of the substrate (1) and an input/output terminal (10) of the semiconductor chip (5) is filled with an underfill material (7), i.e., a complex of a filler, which has a maximum grain diameter of 5μm or less and is contained by 40-60 mass%, and a resin. One main surface of the substrate (1) and a side surface of the semiconductor chip (5) not covered with the underfill material (7) are sealed with a molding material (8), i.e., a complex of a filler contained by 75 mass% and a resin having a glass transition temperature of 180°C or higher. The substrate (1) covered with the molding material (8) and the semiconductor chip (5) are integrally thinned from the top and the bottom.

WIRE BOND INTERCONNECTION

A wire bond interconnection between a die pad and a bond finger includes a support pedestal at a bond site of the lead finger, a ball bond on the die pad, and a stitch bond on the support pedestal, in which a width of the lead finger at the bond site is less than a diameter of the support pedestal. Also, a semiconductor package including a die mounted onto and electrically connected by a plurality of wire bonds to a substrate, in which each of the wire bonds includes a wire ball bonded to a pad on the die and stitch bonded to a support pedestal on a bond site on a lead finger, and in which the width of the lead finger at the bond site is less than the diameter of the support pedestal. Also, such a package in which the package substrate includes a two-tier substrate, each tier including a plurality of lead fingers having a lead finger bond pitch about twice the die pad pitch, the lead fingers of the first tier and the second tier having a staggered arrangement. In some embodiments the support ...

MICROELECTRONIC DEVICES, STACKED MICROELECTRONIC DEVICES, AND METHODS FOR MANUFACTURING MICROELECTRONIC DEVICES

Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices are described herein. In one embodiment, a set of stacked microelectronic devices includes (a) a first microelectronic die having a first side and a second side opposite the first side, (b) a first substrate attached to the first side of the first microelectronic die and electrically coupled to the first microelectronic die, (c) a second substrate attached to the second side of the first microelectronic die, (d) a plurality of electrical couplers attached to the second substrate, (e) a third substrate coupled to the electrical couplers, and (f) a second microelectronic die attached to the third substrate. The electrical couplers are positioned such that at least some of the electrical couplers are inboard the first microelectronic die.

SIMULTANEOUS LASER SOLDERING METHOD

To produce soldered joints between the contacts (K) of components (BE) and the corresponding connections of a support (T1), a deflectable laser beam (LS) is directed onto all solder points of a component (BE) in rapid succession and in several passes (D1), until the solder is simultaneously fused at all solder points. Energy is supplied in a timesharing operation, enabling greater energy to be supplied and the processing time to be reduced, without the risk of thermal damage.

PACKAGE OF SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE THEREOF

On forme des bosses (4, 4A) sur les électrodes d'un dispositif (3) à semi-conducteur puis on revêt le dispositif d'une feuille thermoplastique (7a) qu'on fait fondre par pression à chaud pour que la résine thermoplastique (7) recouvre la totalité du dispositif (3) à semi-conducteur à l'exception des sommets (9) des bosses. Après le pressage à chaud, on découpe la résine thermoplastique.

SEMICONDUCTOR DEVICE, THREE-DIMENSIONAL MOUNTING SEMICONDUCTOR APPARATUS, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Stacked semiconductor devices constitute a three-dimensional mounting semiconductor apparatus. Such a semiconductor device comprise a silicon semiconductor substrate on a major surface of which an integrated circuit part and an electrode pad are provided. A hole is made in the silicon semiconductor substrate by etching using the electrode pad as an etching stopper layer. A buried electrode is provided in this hole and used for electrical connection of the electrode pad to the back major surface of the silicon semiconductor substrate.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

It is an object of the present invention to provide a method of separating a thin film transistor, and circuit or a semiconductor device including the thin film transistor from a substrate by a method different from that disclosed in the patent document 1 and transposing the thin film transistor, and the circuit or the semiconductor device to a substrate having flexibility. According to the present invention, a large opening or a plurality of openings is formed at an insulating film, a conductive film connected to a thin film transistor is formed at the opening, and a peeling layer is removed, then, a layer having the thin film transistor is transposed to a substrate provided with a conductive film or the like. A thin film transistor according to the present invention has a semiconductor film which is crystallized by laser irradiation and prevents a peeling layer from exposing at laser irradiation not to be irradiated with laser light.

Bond head having dual axes of motion

A bond head is provided for a wire bonding machine having a linear axis frame, a rotary axis frame, a bond tool and a wire clamp. The linear axis frame is vertically linearly displacable along a linear axis, while the rotary axis frame is rotationally displacable along a rotary axis. A pivotal connector is provided which pivotally connects the rotary axis frame to the linear axis frame, enabling the rotary axis frame to rotate independent of linear displacement of the linear axis frame. The bond tool is connected to the rotary axis frame and is vertically linearly displacable in response to vertical linear displacement of the linear axis frame and rotationally displacable in response to rotational displacement of the rotary axis frame. The wire clamp is connected to the linear axis frame and is vertically linearly displacable in response to vertical linear displacement of the linear axis frame, while the wire clamp is maintained rotationally stationary during rotational displacement of ...

Power semiconductor device and method therefor

A power transistor includes a plurality of transistor cells. Each transistor cell has a first electrode coupled to a first electrode interconnection region overlying a first major surface, a control electrode coupled to a control electrode interconnection region overlying the first major surface, and a second electrode coupled to a second electrode interconnection region overlying a second major surface. Each transistor cell has an approximately constant doping concentration in the channel region. A dielectric platform is used as an edge termination of an epitaxial layer to maintain substantially planar equipotential lines therein. The power transistor finds particular utility in radio frequency applications operating at a frequency greater than 500 megahertz and dissipating more than 5 watts of power. The semiconductor die and package are designed so that the power transistor can efficiently operate under such severe conditions.

Methods of fabricating nanostructures and nanowires and devices fabricated therefrom

One-dimensional nanostructures having uniform diameters of less than approximately 200 nm. These inventive nanostructures, which we refer to as "nanowires", include single-crystalline homostructures as well as heterostructures of at least two single-crystalline materials having different chemical compositions. Because single-crystalline materials are used to form the heterostructure, the resultant heterostructure will be single-crystalline as well. The nanowire heterostructures are generally based on a semiconducting wire wherein the doping and composition are controlled in either the longitudinal or radial directions, or in both directions, to yield a wire that comprises different materials. Examples of resulting nanowire heterostructures include a longitudinal heterostructure nanowire (LOHN) and a coaxial heterostructure nanowire (COHN).

Semiconductor devices at least partially covered by a composite coating including particles dispersed through photopolymer material

Devices include at least one semiconductor die including at least one surface that is at least partially covered by a photopolymer material. The photopolymer material includes a plurality of discrete particles dispersed through a polymerized matrix. In some embodiments, the photopolymer material may cover at least a portion of each of a plurality of semiconductor dice attached to a substrate. Furthermore, the photopolymer material may cover only a portion of each of the plurality of semiconductor dice, and another photopolymer material may cover another portion of each of the plurality of semiconductor dice.

Light emitting diode, optical semiconductor element and epoxy resin composition suitable for optical semiconductor element and production methods therefor

A light emitting diode comprising an LED chip (5) having a light emitting layer made of a nitride compound semiconductor and a light transmitting resin (8) that includes a fluorescent material which absorbs at least a part of light emitted by the LED chip and emits light of a different wavelength, wherein the fluorescent material includes a fluorescent particles of small particle size (82) and a fluorescent particles of large particle size (81), the fluorescent particles of large particle size being distributed in the vicinity of the LED chip in the light transmitting resin to form a wavelength converting layer, the fluorescent particles of small particle size being distributed on the outside of the wavelength converting layer in the light transmitting resin.

Method of manufacturing semiconductor devices

In the disclosed method of manufacturing semiconductor devices with a single-sided resin-sealed package structure, when resin is filled into between the chip and the substrate, the occurrence of variations in the finishing dimensions of the package or defects in the outward appearance of the package is prevented. The present invention comprises the step of using a guide plate (11) for pouring resin and bringing one end of the guide plate into contact with one face end of a substrate or with a portion of one major surface near at least one side face of a chip in filling sealing resin (5a) between the chip and the substrate after the semiconductor chip (2) has been mounted, with the face down, on one major surface of a wiring substrate (1) having the wiring (1a) containing a connection section (1b), the step of inclining the guide plate so that the guide plate may meet one major surface of the substrate at a specified angle, when or after one end of the guide plate is brought into contact ...

Lead-less semiconductor device with improved electrode pattern structure

A semiconductor device comprises : an insulating substrate have a first main face which is sealed with a sealing material ; at least a set of input and output electrode patterns provided on the first main face, and the input and output electrode patterns being separated from each other ; at least a ground electrode pattern having a ground potential, and the ground electrode pattern being separated from the input and output electrode patterns ; and at least an electrically conductive pattern extending over an inter-region between the input and output electrode patterns, and the electrically conductive pattern being separated from the input and output electrode patterns, and the electrically conductive pattern being electrically connected to the ground electrode pattern, so that the electrically conductive pattern has a ground potential.

Surface acoustic wave device and its manufacturing method

Insecticidally active nitro compounds

КАТАЛИЗАТОР ОТВЕРЖДЕНИЯ, КОМПОЗИЦИЯ, ЭЛЕКТРОННОЕ УСТРОЙСТВО И СОПУТСТВУЮЩИЙ СПОСОБ

... 1. Катализатор отверждения, включающий ! кислоту Льюиса и ! один или оба компонента из числа азотсодержащей молекулы и нетретичного фосфина, в котором азотсодержащая молекула включает моноамин или гетероциклическое ароматическое органическое соединение. ! 2. Катализатор по п.1, в котором кислота Льюиса представляет собой комплекс или аддукт одного или обоих компонентов из числа азотсодержащей молекулы или нетретичного фосфина. ! 3. Катализатор по п.1, в котором азотсодержащая молекула включает одно или оба вещества из 1,8-диазабицикло[5.4.0]ундец-7-ена и метилимидазола. ! 4. Катализатор по п.1, в котором кислота Льюиса включает тризамещенный боран. ! 5. Катализатор по п.4, в котором кислота Льюиса включает три(арил)боран. ! 6. Катализатор по п.4, в котором три(арил)боран включает один или несколько радикалов из числа следующих: фенил, пентафторфенил; 2,3,5,6-тетрафторфенил; 2,3,4,5-тетрафторфенил; 3,4,5-трифтор-1-фенил или 4-(пентафторфенил)-2,3,5,6-тетрафторфенил. ! 7. Катализатор по п ...

Verfahren zur Herstellung eines Halbleiterbauteils mit in Kunststoffgehäusemasse eingebetteten Halbleiterbauteilkomponenten

Verfahren zur Herstellung eines Halbleiterbauteils mit in Kunststoffgehäusemasse (2) eingebetteten Halbleiterbauteilkomponenten (3) mit folgenden Schritten: Bereitstellen der Halbleiterbauteilkomponenten (3), Aufbringen einer Haftvermittlerschicht (5) nasschemisch unmittelbar auf die Oberfläche (4) der Halbleiterbauteilkomponenten (3), wobei das nasschemische Aufbringen so ausgebildet ist, dass als Halbleiterbauteilkomponenten (3) – ein Verdrahtungssubstrat (7) mit strukturierter Metallbeschichtung (8), – ein Keramiksubstrat mit strukturierten Metalllagen, – eine Leiterplatte (9) mit strukturierter Metallbeschichtung (8), – innere Flachleiter (10), die außerhalb der Kunststoffgehäusemasse (2) in Außenflachleiter (11) als Außenkontakte übergehen, – ein Halbleiterchip und – innere Flipchip-Kontakte und/oder Bondverbindungsdrähte (14) als Verbindungselemente (13) beschichtet werden können, ohne dass das Beschichtungsverfahren jeweils geändert werden muss, wobei eine Haftvermittlerschicht ( ...

VERBINDUNGSELEMENTE FÜR MIKROELEKTRONISCHE KOMPONENTEN

Verfahren zur Herstellung von Klebeverbindungen für Elektronik- und Mikroelektronikanwendungen

Semiconductor lead wire handling

... 1,040,668. Welding by pressure. GENERAL ELECTRIC CO. Aug. 4, 1964 [July 22, 19 No. 30756/64. Heading B3R. [Also in Division H1] Electrode wires are attached to a semiconductor device by an apparatus wherein the wires are cut to predetermined lengths, transported by a pair of holders to the semi-conductor and aligned therewith by the holders prior to joining thereto. In a specific embodiment, jaws 2 on carriage 1 draws a predetermined length of wire from a store, the wire then being grasped by holders 75 and 78 which are opened and closed by the movement of rods 69 and 70 actuated by rod 67 which moves parallel to bar 57 pivoted on mounting 59. Jaws 2 are released, carriage 1 moves back (into the plane of the paper) and jaws 2 come together again thus cutting off two predetermined lengths of wire which are removed by holders 75 and 78. The transport mechanism 3 moves through a rightangle about pivot 59 to the semi-conductor device. The movement of plate 86 makes the tubes 71 and 72 rotate ...

GOLD WIRE FOR THE BONDING OF A SEMICONDUCTOR DEVICE

Bonding method for electric element

GOLD WIRE FOR THE BONDING OF A SEMICONDUCTOR DEVICE

Improvements relating to semiconductor packages

COATED POLYMER FILM PROCESS FOR USE IN THE PRODUCTION OF SEMI CONDUCTOR DEVICES

... 1318811 Semi-conductor devices TEXAS INSTRUMENTS Inc 31 March 1971 8285/71 Headings H1K and H1R A semi-conductor assembly comprises utilizing a polymer film with a plurality of grouped individual contacts adhered thereto as a contact means for a semi-conductor device, and from making connection from the device to conductive parts of a header. The film is prepared from a polyimide film by forming a layer of copper thereon, patterning the sheet to form contact areas therefrom and plating these areas with a protective layer of nickel, chromium or molybdenum followed by a plated layer of a noble metal, e.g. gold, silver or platinum. The unplated areas of the copper layer are then removed, and holes, used as indexing means, punched into the film between groups of contacts. The edges of the film and adherent contacts are then turned in to give portions of each contact on both sides of the film. The film is then made into a roll, 27, and passed sequentially through a number of operation stations ...

Bonding material and bonding method for electric element

SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF

HYBRIDIZING OF WITH CHROMOPHOREN AND FLUOROPHOREN CONJUGATED POLYNUKLEOTIDEN FOR THE PRODUCTION OF A DONOR DONOR OF ENERGY TRANSFER SYSTEM

PROCEDURE FOR THE LASER SOLDERING AND FOR THE TEMPERATURE MONITORING OF SEMICONDUCTOR CHIPS AS WELL AS AFTER THIS PROCEDURE MANUFACTURED SMART CARD

CIRCUIT SORT SYSTEM AND PROCEDURE

Localized reflow for wire bonding and flip chip connections

LOCALIZED REFLOW FOR WIRE BONDING AND FLIP CHIP CONNECTIONS

A circuit singulation system and method

SEMICONDUCTOR LIGHT-EMITTING DEVICE, METHOD FOR MANUFACTURING SAME AND LIGHT-EMITTING APPARATUS USING SAME

COATED AND MAGNETIC PARTICLES AND APPLICATIONS THEREOF

COUPLING CONTINUOUS CONDUCTIVE FILAMENTS TO AN ELEMENT

Method for making a circuit structure having a flip-mounted matrix of devices

GLASS MATERIAL FOR USE AT HIGH FREQUENCIES

ROOM TEMPERATURE METAL DIRECT BONDING

... ²²²A bonded device structure including a first substrate having a first set of ²metallic bonding pads, preferably connected to a device or circuit, and having ²a first non-metallic region adjacent to the metallic bonding pads on the first ²substrate, a second substrate having a second set of metallic bonding pads ²aligned with the first set of metallic bonding pads, preferably connected to a ²device or circuit, and having a second non-metallic region adjacent to the ²metallic bonding pads on the second substrate, and a contact-bonded interface ²between the first and second set of metallic bonding pads formed by contact ²bonding of the first non-metallic region to the second non-metallic region. At ²least one of the first and second substrates may be elastically deformed.² ...

PLUG-IN TYPE ELECTRONIC CONTROL UNIT, STRUCTURE OF CONNECTION OF WIRING BOARD WITH PLUG MEMBER, UNIT OF CONNECTION OF ELECTRONIC PART WITH WIRING BOARD, AND PROCESS FOR MOUNTING ELECTRONIC PART

A plug-in type electronic control unit is constituted of a wiring board, a plurality of electronic parts mounted on one surface of the wiring board through the process by wireless bonding, and a plug member mounted on the other surface of the wiring board through the process by wireless bonding. The planar extent of the unit can be suppressed by using such a laminated structure and, at the same time, the extent of the unit in the laminating direction can also be suppressed by adopting the wireless bonding. Therefore, the size of the plug-in type electronic control unit can be reduced.

Electric circuit substrate

Integrated circuit chip made secure against the action of electromagnetic radiation

SIMULTANEOUS MULTIPLE LEAD BONDING

Device semiconductor

Integrated circuit device for digital camera, facsimile, has bumps to interconnect integrated circuit having image sensors and integrated circuit having signal processing circuit

Architecture d'interconnexion pour interconnecter une pluralité d'éléments électriques rapprochés, placés sur une structure fabriquée sur un premier circuit intégré, avec des circuits de travail placés sur une structure fabriquée sur un deuxième circuit intégré. Dans un mode de réalisation, la structure fabriquée sur le premier circuit intégré comprend une pluralité de capteurs photoélectriques. Des éléments d'interconnexion conducteurs placés sur la structure fabriquée sur le premier circuit intégré fournissent une connexion électrique entre les capteurs photoélectriques individuels et les circuits de travail placés sur la structure fabriquée sur le deuxième circuit intégré.

Treatment of a platelet of bites including the application of an anisotropic carrier adhesive

Pour le traitement d'une plaquette (15) de puces (4), ultérieur à sa production, avec des étape de : . découpe ou "dicing "; . application d'un adhésif (13) anisotropique de report; et . report sur ce substrat de la puce (4); on prévoit que l'adhésif (13) est appliqué, directement ou indirectement, sur la plaquette (15); le rapport d'aires entre celles d'une part d'une surface utile de la plaquette (15) ou puce (4), sur d'autre part celle d'une surface de dépôt d'adhésif (13) appliqué, étant de l'ordre de 80-85 % à 90-95 %.

SEMICONDUCTOR DEVICES

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

BONDING WIRE FOR SEMICONDUCTOR DEVICE

A bonding wire for semiconductor device that attains improvement to ball part formability and junction easiness, excelling in loop controllability, and that enhances bonding strength at wedge junction, ensuring industrial production applicability, and that is composed mainly of copper cheaper than gold wire. There is provided a bonding wire for semiconductor device, comprising a core material composed mainly of copper and, superimposed thereon, a skin layer of conductive metal whose composition is different from that of the core material, characterized in that the skin layer is composed mainly of at least two members selected from among gold, palladium, platinum, rhodium, silver and nickel, and that in the skin layer, there is a region with a gradient of concentration of one or both of major component metal and copper in the direction of wire diameter. COPYRIGHT KIPO & WIPO 2010 ...

EPOXY RESIN COMPOSITION AND DIE BONDING MATERIAL COMPRISING THE COMPOSITION

A composition characterized by comprising the following: (A) an epoxy resin; (B) an epoxy resin hardener, the amount of the hardener being such that the amount of the reactive groups of the epoxy resin hardener (B) is 0.8-1.25 equivalents to the epoxy groups of the epoxy resin (A); (C) thermoplastic resin particles which are solid at 25°C, the amount of the particles being 3-60 parts by mass per 100 parts by mass of the sum of the epoxy resin (A) and the epoxy resin hardener (B); and (D) an epoxy resin hardening accelerator, the amount of the accelerator being 0.1-10 parts by mass per 100 parts by mass of the sum of the epoxy resin (A) and the epoxy resin hardener (B). The composition comes into a stable B-stage state and gives a void-free cured object. © KIPO & WIPO 2008 ...

METHOD FOR PRODUCING CHIP STACKS, AND A CARRIER FOR CARRYING OUT THE METHOD

Semiconductor package including a semiconductor die having redistributed pads

A semiconductor package that includes a semiconductor die, an insulation around the die, and a conforming conductive pad coupled to an electrode of the die.

IMPROVEMENTS RELATING TO SEMICONDUCTOR PACKAGES

A semiconductor package comprising a first semiconductor sub-package (40) having a connection face (44) with un-supported connectors (21) depending therefrom arranged to electrically connect a first semiconductor device contained therein to an external circuit, and at least one second semiconductor sub-package (42) also having a connection face (46) with un-supported connectors (25) depending therefrom arranged to electrically connect a second semiconductor device contained therein to an external circuit, the second semiconductor sub-package (42) also having an attachment face (48), on an opposite side thereof from the connection face (46); wherein the second semiconductor sub-package (42) is mounted on the first semiconductor sub-package (40) such that its attachment face (48) is coupled to the connection face (44) of the first semiconductor sub-package (40).

CIRCUIT CONNECTING MATERIAL, CONNECTION STRUCTURE FOR CIRCUIT MEMBER USING THE SAME, AND METHOD FOR PRODUCING SUCH CONNECTION STRUCTURE

Disclosed is a circuit connecting material for connecting a first circuit member wherein a plurality of first circuit electrodes are formed on a major surface of a first circuit board, and a second circuit member wherein a plurality of second circuit electrodes are formed on a major surface of a second circuit board in such a manner that the first and second circuit electrodes are opposite to each other. This circuit connecting material contains an adhesive composition, coated particles obtained by coating a part of conductive particles with insulating fine particles, and uncoated particles which are composed of conductive particles whose entire surfaces are in contact with the adhesive composition.

DIE BONDER FOR LASER CRYSTAL

A die bonder for laser crystal in which bonding is performed extremely uniformly in the laser crystal face with high thermal conduction without causing any damage to a reflection control film attached to a laser crystal or the surface thereof. In the die bonder for bonding a laser crystal to a heat sink, a spring (9) located between a pin holding part (8) engaging with a pin seating base (10) and a pin flange part (7A) can slide a pin (7) vertically from the pin holding part (8). Under a state where the laser crystal (6) is pressed against the heat sink (4) with a predetermined pressure by touching the forward end face of the pin (7) onto the laser crystal (6), the laser crystal (6) is heated and secured to the heat sink (4).

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

A manufacturing method of a semiconductor device is provided, which includes a process in which a transistor is formed over a first substrate; a process in which a first insulating layer is formed over the transistor; a process in which a first conductive layer connected to a source or a drain of the transistor is formed; a process in which a second substrate provided with an second insulating layer is arranged so that the first insulating layer is attached to the second insulating layer; a process in which the second insulating layer is separated from the second substrate; and a process in which a third substrate provided with a second conductive layer which functions as an antenna is arranged so that the first conductive layer is electrically connected to the second conductive layer.

WAFER LEVEL SUPER STRETCH SOLDER

Disclosed is a technique to generate stretched solder columns (bumps) at the wafer level, suitable for wafer level packaging. This is accomplished through use of using two wafers - the standard (functional) wafer (21) that contains the integrated circuits and a master (dummy) wafer (22) on whose surface is provided an array of solder bumps (35) that is the mirror image of that on the functional wafer. After suitable alignment, both sets of solder bumps are melted and then slowly brought together till they merge. Then, as they cool, they are slowly pulled apart thereby stretching the merged solder columns. Once the latter have fully solidified, they are separated from the master wafer (22) only.

POWER SEMICONDUCTOR DEVICE AND METHOD THEREFOR CROSS REFERENCE TO RELATED APPLICATIONS

A power transistor includes a plurality of transistor cells. Each transistor cell has a first electrode coupled to a first electrode interconnection region overlying a first major surface, a control electrode coupled to a control electrode interconnection region overlying the first major surface, and a second electrode coupled to a second electrode interconnection region overlying a second major surface. Each transistor cell has an approximately constant doping concentration in the channel region. A dielectric platform is used as an edge termination of an epitaxial layer to maintain substantially planar equipotential lines therein. The power transistor finds particular utility in radio frequency applications operating at a frequency greater than 500 megahertz and dissipating more than 5 watts of power. The semiconductor die and package are designed so that the power transistor can efficiently operate under such severe conditions.

METHOD FOR PRODUCING A SEMICONDUCTOR ELEMENT

The invention relates to a method for producing a semiconductor element, especially a thin-layered element. According to the invention, a semi-conductive layer is separated from a substrate by radiation from a laser beam having a plateau-shaped spatial beam profile. Additionally, the semiconductor layer is applied to a support having an adapted thermal dilatation coefficient before being separated. The invention is particularly suitable for semiconductor layers which contain a nitride-compound semiconductor.

Semiconductor device

In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.

Methods of forming semiconductor elements using micro-abrasive particle stream

A method of fabricating a microelectronic unit includes providing a semiconductor element having a front surface and a rear surface remote from the front surface, forming at least one first opening extending from the rear surface partially through the semiconductor element towards the front surface by directing a jet of fine abrasive particles towards the semiconductor element, and forming at least one conductive contact and at least one conductive interconnect coupled thereto. The semiconductor element can include a plurality of active semiconductor devices therein. The semiconductor element can include a plurality of conductive pads exposed at the front surface. Each conductive interconnect can extend within one or more of the first openings and can be coupled directly or indirectly to at least one of the conductive pads. Each of the conductive contacts can be exposed at the rear surface of the semiconductor element for electrical connection to an external device.

Method and electrostatic transfer stamp for transferring semiconductor dice using electrostatic transfer printing techniques

A transfer stamp that can be charged with a spatial pattern of electrostatic charge for picking up selected semiconductor dice from a host substrate and transferring them to a target substrate. The stamp may be bulk charged and then selectively discharged using irradiation through a patterned mask. The technique may also be used to electrostatically transfer selected semiconductor dice from a host substrate to a target substrate.

Gas delivery system for reducing oxidation in wire bonding operations

A wire bonding machine is provided. The wire bonding machine includes a bonding tool and an electrode for forming a free air ball on an end of a wire extending through the bonding tool where the free air ball is formed at a free air ball formation area of the wire bonding machine. The wire bonding machine also includes a bond site area for holding a semiconductor device during a wire bonding operation. The wire bonding machine also includes a gas delivery mechanism configured to provide a cover gas to: (1) the bond site area whereby the cover gas is ejected through at least one aperture of the gas delivery mechanism to the bond site area, and (2) the free air ball formation area.

Structure for Multi-Row Leadframe and Semiconductor Package Thereof and Manufacture Method Thereof

The present invention relates to a multi-row leadframe for semiconductor packaging, characterized by: forming a plating pattern on a leadframe material (first step); forming a protective pattern on the plating pattern (second step); and forming a nano pattern by using the protective pattern as a mask (third step), whereby a protective pattern is formed on an upper surface of a plating pattern to increase reliability of a product by preventing damage to a plating layer caused by etching solution during pattern formation of leadframe and to thereby solve the problem of using the plating layer as an etching mask.

Packaging Integrated Circuits

An integrated circuit 15 is placed onto a lead frame 101 having lead fingers 109 of substantially constant thickness along their length. Wires are formed from the lead fingers 109 to corresponding electrical contacts the integrated circuit. Following the wire bonding process, the thickness of the tips of the lead fingers 109 is reduced by a laser process, to form tips of reduced thickness desirable for a subsequent moulding operation. Thus, at the time of the wire bonding the tips of the fingers 109 need not have a gap beneath them, so that more secure wire bonds to the lead fingers 109 can be formed.

Power Semiconductor Chip Package

A device includes a vertical power semiconductor chip having an epitaxial layer and a bulk semiconductor layer. A first contact pad is arranged on a first main face of the power semiconductor chip and a second contact pad is arranged on a second main face of the power semiconductor chip opposite to the first main face. The device further comprises an electrically conducting carrier attached to the second contact pad.

Semiconductor module including a switch and non-central diode

A semiconductor module having one or more silicon carbide diode elements mounted on a switching element is provided in which the temperature rise is reduced by properly disposing each of the diode elements on the switching element, to thereby provide a thermal dissipation path for the respective diode elements. The respective diode elements are arranged on a non-central portion of the switching element, to facilitate dissipation of the heat produced by each of the diode elements, whereby the temperature rise in the semiconductor module is reduced.

Integrated circuit tampering protection and reverse engineering prevention coatings and methods

A method of protecting an electronics package is discussed along with devices formed by the method. The method involves providing at least one electronic component that requires protecting from tampering and/or reverse engineering. Further, the method includes mixing into a liquid glass material at least one of high durability micro-particles or high-durability nano-particles, to form a coating material. Further still, the method includes depositing the coating material onto the electronic component and curing the coating material deposited.

Semiconductor module having a semiconductor chip stack and method

A semiconductor module having a semiconductor chip stack and a method for producing the same is disclosed. In one embodiment, a thermally conductive layer with anisotropically thermally conductive particles is arranged between the semiconductor chips. The anisotropically thermally conductive particles have a lower thermal conductivity in a direction vertically with respect to the layer or the film than in a direction of the layer or the film.

Copper conductor film and manufacturing method thereof, conductive substrate and manufacturing method thereof, copper conductor wiring and manufacturing method thereof, and treatment solution

Provided are a copper conductor film and manufacturing method thereof, and patterned copper conductor wiring, which have superior conductivity and wiring pattern formation, and with which there is no decrease in insulation between circuits, even at narrow wiring widths and narrow inter-wiring spacing. Disclosed are a copper conductor film and manufacturing method thereof in which a copper-based particle-containing layer, which contains both a metal having catalytic activity toward a reducing agent and copper oxide, is treated using a treatment solution that contains a reagent that ionizes or complexes copper oxide and a reducing agent that reduces copper ions or copper complex to form metallic copper in a single solution, and patterned copper conductor wiring that is obtained by patterning a copper-based particle-containing layer using printing and by said patterned particle-containing layer being treated by a treatment method using a solution that contains both a reagent that ionizes or complexes copper oxide and a reducing agent that reduces copper ions or copper complexes to form metallic copper in a single solution.

System comprising a semiconductor device and structure

A method of manufacturing a semiconductor device, the method including, providing a first monocrystalline layer including semiconductor regions, overlaying the first monocrystalline layer with an isolation layer, transferring a second monocrystalline layer comprising semiconductor regions to overlay the isolation layer, wherein the first monocrystalline layer and the second monocrystalline layer are formed from substantially different crystal materials; and subsequently etching the second monocrystalline layer as part of forming at least one transistor in the second monocrystalline layer.

Chip Pad Resistant to Antenna Effect and Method

A chip pad structure of an integrated circuit (IC) and the method of forming are disclosed. The chip pad comprises a main pad portion and a ring pad portion. During a charging process involved in forming the chip pad structure, electrical connections from the gate electrodes of MOS transistors in the IC substrate generally are made only to the ring pad portion that has an antenna-to-gate area ratio substantially below a predetermined antenna design rule ratio, and thus is resistant or immune to antenna effect. The main pad portion and the ring pad portion are coupled together through metal bridges formed in an upper interconnect metal layer or in the top conductive pad layer. The chip pad may be used as probe pads on a parametric testline or bonding pads on an IC.

Wiring substrate and method of manufacturing the same

A wiring substrate includes a structure in which a plurality of wiring layers are stacked through insulating layers intervening therebetween, and which has a first surface side and a second surface side, the first surface side where a semiconductor element is to be mounted, the second surface side being located at an opposite side to the first surface side, an interposer buried in an outermost one of the insulating layers located at the first surface side, and electrically connected to the semiconductor element to be mounted, and a sheet-shaped member buried in an outermost one of the insulating layers located at the second surface side, wherein, the interposer and the sheet-shaped member are disposed at symmetrical positions symmetrical each other.

Protection of reactive metal surfaces of semiconductor devices during shipping by providing an additional protection layer

When forming complex metallization systems on the basis of copper, the very last metallization layer may receive contact regions on the basis of copper, the surface of which may be passivated on the basis of a dedicated protection layer, which may thus allow the patterning of the passivation layer stack prior to shipping the device to a remote manufacturing site. Hence, the protected contact surface may be efficiently re-exposed in the remote manufacturing site on the basis of an efficient non-masked wet chemical etch process.

Electronic device and method for producing a device

An electronic device or devices and method for producing a device is disclosed. One embodiment provides an integrated component, a first package body and a contact device. The contact device penetrates the package body.

Die attach film

Provided are a die attach film, a semiconductor wafer, and a semiconductor packaging method. The die attach film can prevent generation of burrs or scattering of chips in a dicing process, and exhibits excellent expandability and pick-up characteristics in a die pressure-sensitive adhesive process. Further, the die attach film can prevent release, shifting, or deflection of a chip in a wire pressure-sensitive adhesive or molding process. Thus, it is possible to improve embeddability, inhibit warpage of a wafer or wiring substrate, and enhance productivity in a semiconductor packaging process.

Method for Making Solder-top Enhanced Semiconductor Device of Low Parasitic Packaging Impedance

A solder-top enhanced semiconductor device is proposed for packaging. The solder-top device includes a device die with a top metal layer patterned into contact zones and contact enhancement zones. At least one contact zone is electrically connected to at least one contact enhancement zone. Atop each contact enhancement zone is a solder layer for an increased composite thickness thus lowered parasitic impedance. Where the top metal material can not form a uniform good electrical bond with the solder material, the device die further includes an intermediary layer sandwiched between and forming a uniform electrical bond with the top metal layer and the solder layer. A method for making the solder-top device includes lithographically patterning the top metal layer into the contact zones and the contact enhancement zones; then forming a solder layer atop each of the contact enhancement zones using a stencil process for an increased composite thickness.

Electronic device and manufacturing thereof

An electronic device and manufacturing thereof. One embodiment provides a semiconductor chip having a control electrode and a first load electrode on a first surface and a second load electrode on a second surface. A first lead is electrically coupled to the control electrode. A second lead is electrically coupled to the first load electrode. A third lead is electrically coupled to the first load electrode, the third lead being separate from the second lead. A fourth lead is electrically coupled to the second load electrode, the second and third leads being arranged between the first and fourth leads.

Through wafer vias and method of making same

A method of forming and structure for through wafer vias and signal transmission lines formed of through wafer vias. The method of forming through wafer vias includes forming an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via through a semiconductor substrate having a top surface and an opposite bottom surface, each through wafer via of the array of through wafer vias extending from the top surface of the substrate to the bottom surface of the substrate.

TCE Compensation for Package Substrates for Reduced Die Warpage Assembly

A method for assembling die packages includes attaching contacts on a first side of a plurality of first die to substrate pads on a top surface of a composite carrier. The composite carrier includes a package substrate including at least one embedded metal layer having its bottom surface secured to a semiconductor wafer. The composite carrier minimizes effects of the CTE mismatch between the die and the package substrate during assembly reduces warpage of the die. After the attaching, the semiconductor wafer is removed from the package substrate. Electrically conductive connectors are attached to the bottom surface of the package substrate, and the package substrate is sawed to form a plurality of singulated die packages.

Semiconductor device including cladded base plate

A semiconductor device includes a semiconductor chip coupled to a substrate and a base plate coupled to the substrate. The base plate includes a first metal layer clad to a second metal layer. The second metal layer is deformed to provide a pin-fin or fin cooling structure.

Method to form solder deposits and non-melting bump structures on substrates

Described is a method of forming a metal or metal alloy layer onto a substrate comprising the following steps i) provide a substrate including a permanent resin layer on top of at least one contact area and a temporary resin layer on top of the permanent resin layer, ii) contact the entire substrate area including the at least one contact area with a solution suitable to provide a conductive layer on the substrate surface and i) electroplate a metal or metal alloy layer onto the conductive layer.

Resin Sealed Semiconductor Device And Manufacturing Method Therefor

A semiconductor device includes a thermoplastic resin case, a semiconductor chip mounted within the thermoplastic resin case, a metal terminal having a wire bonding surface and an opposing contact surface, and a wire connected between the wire bonding surface and the semiconductor chip. The contact surface of the metal terminal is thermoplastically bonded at an area to the inside of the thermoplastic resin case.

Semiconductor device and method of manufacturing the same

A semiconductor device includes a first bump that is located over a surface of a semiconductor element, and is formed on a first bump formation face distanced from a back surface of the semiconductor element at a first distance, and a second bump that is located over the surface of the semiconductor element, and is formed on a second bump formation face distanced from the back surface of the semiconductor element at a second distance being longer than the first distance, the second bump having a diameter larger than a diameter of the first bump.

Starting material for a sintered bond and process for producing the sintered bond

The invention relates to a starter material for a sintering compound, said starter material comprising first particles of at least one metal having a first coating which is applied to the first particles and consists of an organic material, and second particles which contain an organic metal compound and/or a precious metal oxide, the organic metal compound and/or the precious metal oxide being converted during heat treatment of the starter material into the fundamental elemental metal and/or precious metal. The invention is characterized in that the second particles have a core of at least one metal and a second coating which is applied to the core and contains the organic metal compound and/or precious metal oxide. Furthermore, the first coating contains a reducing agent by means of which the organic metal compound and/or the precious metal oxide is/are reduced to the elemental metal and/or precious metal at a temperature below the sintering temperature of the elemental metal and/or precious metal.

Package including an underfill material in a portion of an area between the package and a substrate or another package

Embodiments include but are not limited to apparatuses and systems including semiconductor packages, e.g. memory packages, having a substrate or a first package, and a second package coupled to the substrate or the first package, wherein the second package includes at least one die and an underfill material disposed in a portion, but not an entirety, of an area between the package and the substrate or the first package. Other embodiments may be described and claimed.

Power recovery circuit based on partial standing waves

A power recovery system includes a transmission line that is coupled to transfer an RF signal received via an antenna. The RF signal generates a partial standing wave in the transmission line and the transmission line has at least one standing wave anti-node. A power recovery circuit converts an anti-node signal from the at least one standing wave anti-node to a power signal.

Semiconductor integrated circuit device

In semiconductor integrated circuit devices for vehicle use, an aluminum pad on a semiconductor chip and an external device are coupled to each other by wire bonding using a gold wire for the convenience of mounting. Such a semiconductor integrated circuit device, however, causes a connection failure due to the interaction between aluminum and gold in use for a long time at a relatively high temperature (about 150 degrees C.). A semiconductor integrated circuit device can include a semiconductor chip as a part of the device, an electrolytic gold plated surface film (gold-based metal plated film) provided over an aluminum-based bonding pad on a semiconductor chip via a barrier metal film, and a gold bonding wire (gold-based bonding wire) for interconnection between the plated surface film and an external lead provided over a wiring board (wiring substrate).

Electrical module for being received by automatic placement machines by means of generating a vacuum

The invention relates to an electrical module ( 100 ) for being received by automatic placement machines by means of generating a vacuum, comprising a carrier substrate ( 10 ), at least one component ( 20, 21 ) disposed on the carrier substrate ( 10 ), and a cover element ( 30 ) disposed above the at least one component ( 20, 21 ). A fixing component ( 40 ) by which the cover element ( 30 ) is attached to the at least one component ( 21 ) is disposed between the cover element ( 30 ) and the at least one component ( 21 ). The cover element can be implemented as a dimensionally stable, flat film by means of which it is possible to suction the module by means of vacuum for a placement method, and to place said module at a position on a circuit board.

Method of Packaging a Die

A method of attaching a die to a substrate is disclosed. A major surface of the die has an array of electrical contacts, and is covered with a tape segment having an array of apertures in register with the contacts. Solder balls are inserted into the apertures. The die is positioned against a substrate with the solder balls in register with the die pads on the surface of the substrate, and a heat treatment process is performed to bond the conductive elements to the corresponding bond pads.

SEMICONDUCTOR DEVICE

A semiconductor device according to the present invention includes a semiconductor chip, an electrode pad made of a metal material containing aluminum and formed on a top surface of the semiconductor chip, an electrode lead disposed at a periphery of the semiconductor chip, a bonding wire having a linearly-extending main body portion and having a pad bond portion and a lead bond portion formed at respective ends of the main body portion and respectively bonded to the electrode pad and the electrode lead, and a resin package sealing the semiconductor chip, the electrode lead, and the bonding wire, the bonding wire is made of copper, and the entire electrode pad and the entire pad bond portion are integrally covered by a water-impermeable film. 1. A semiconductor device comprising:an interlayer insulating film formed on a semiconductor substrate;an uppermost layer wiring made of copper and formed on the interlayer insulating film;a passivation film formed on the uppermost layer wiring and selectively exposing a top surface of the uppermost layer wiring as an electrode pad; anda bonding wire made of copper and bonded directly to the electrode pad.2. The semiconductor device according to claim 1 , wherein the bonding wire is stitch bonded directly to the electrode pad.3. The semiconductor device according to claim 1 , wherein the bonding wire is bonded to the electrode pad by a stud bump.4. The semiconductor device according to claim 1 , wherein a thickness of the electrode pad is no less than 10 μm.5. The semiconductor device according to claim 1 , wherein a thickness of the electrode pad is 10 μm to 15 μm.6. The semiconductor device according to claim 1 , further comprising a lower layer wiring covered with the interlayer insulating film claim 1 , whereinthe uppermost layer wiring includes a protrusion extending inside the interlayer insulating film,the lower layer wiring is electrically connected to the electrode pad via a pathway including the protrusion.7. The ...

3D SEMICONDUCTOR DEVICE AND STRUCTURE

A 3D semiconductor device, including: a first level including a single crystal layer, a plurality of first transistors, and a first metal layer, forming memory control circuits; a second level overlaying the single crystal layer, and including a plurality of second transistors and a plurality of first memory cells; a third level overlaying the second level, and including a plurality of third transistors and a plurality of second memory cells; where the second transistors are aligned to the first transistors with less than 40 nm alignment error, where the memory cells include a NAND non-volatile memory type, where some of the memory control circuits can control at least one of the memory cells, and where some of the memory control circuits are designed to perform a verify read after a write pulse so to detect if the at least one of the memory cells has been successfully written. 1. A 3D semiconductor device , the device comprising: 'wherein connections between said first transistors and first metal layer comprise said first contact plugs;', 'a first level comprising a single crystal layer, a plurality of first transistors, a plurality of first contact plugs and a first metal layer,'}memory control circuits comprising a portion of said connections and said plurality of first transistors;a second level overlaying said single crystal layer, said second level comprising a plurality of second transistors;a third level overlaying said second level, said third level comprising a plurality of third transistors;a second metal layer overlaying said third level; and wherein said second transistors are aligned to said first transistors with less than 40 nm alignment error,', 'wherein said third metal layer comprises bit lines,', 'wherein said second level comprises a plurality of first memory cells,', 'wherein said third level comprises a plurality of second memory cells,', 'wherein one of said second transistors is at least partially self-aligned to at least one of said third ...

3D SEMICONDUCTOR DEVICE AND SYSTEM

A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors; at least one first metal layer interconnecting the plurality of first transistors, where the interconnecting includes forming memory peripheral circuits; a plurality of second transistors underlying the first single crystal layer; a second metal layer overlaying the plurality of second transistors; a first memory cell underlying the memory peripheral circuits; a second memory cell underlying the first memory cell, and a non-volatile NAND memory, where the first memory cell includes at least one of the second transistors, where at least one of the second transistors includes a source, channel and drain, where the source, the channel and the drain have the same dopant type, here the non-volatile NAND memory includes the first memory cell, and where at least one of the second transistors includes a polysilicon channel. 1. A 3D semiconductor device , the device comprising:a first single crystal layer comprising a plurality of first transistors; 'wherein said interconnecting comprises forming memory peripheral circuits;', 'at least one first metal layer interconnecting said plurality of first transistors,'}a plurality of second transistors underlying said first single crystal layer;a second metal layer overlaying said plurality of second transistors;a first memory cell underlying said memory peripheral circuits;a second memory cell underlying said first memory cell;a staircase structure underlying said first single crystal layer; and wherein said first memory cell comprises at least one of said second transistors,', 'wherein said memory peripheral circuits control at least said first memory cell,', 'wherein at least one of said second transistors comprises a source, channel and drain,', 'wherein said source, said channel and said drain have the same dopant type,', 'wherein said non-volatile NAND memory comprises said first memory cell,', 'wherein at ...

RARE EARTH INTERLAYS FOR MECHANICALLY LAYERING DISSIMILAR SEMICONDUCTOR WAFERS

Structures described herein may include mechanically bonded interlayers for formation between a first Group III-V semiconductor layer and a second semiconductor layer. The mechanically bonded interlayers provide reduced lattice strain by strain balancing between the Group III-V semiconductor layer and the second semiconductor layer, which may be silicon. 1. A structure comprising:a first layer comprising a Group IV semiconductor;a second layer comprising at least one rare earth element, wherein a first portion of the second layer is either lattice matched or strain balanced to the first layer;a third layer comprising a III-V semiconductor, and wherein the structure contains at least one bonded interface.2. The structure of claim 1 , wherein the third layer includes at least one shared element with a second portion of the second layer.3. The structure of claim 1 , wherein the at least one bonded interface is between the second and third layer.4. The structure of claim 1 , wherein the second layer offsets at least a fraction of a lattice mismatch between the first layer and the third layer.5. The structure of claim 1 , wherein the first layer is silicon.6. The structure of claim 1 , wherein the second layer is conductive.7. The structure of claim 1 , wherein the second layer is comprises of at least one rare earth pnictide.8. The structure of claim 1 , wherein:a first region of the second layer comprises a first rare earth pnictide alloy with rare earth elements in first proportions; anda second region of the second layer comprises the first rare earth pnictide alloy with rare earth elements in second proportions.9. The structure of claim 1 , wherein:a first region of the second layer comprises a first rare earth pnictide alloy with Group V elements in first proportions; anda second region of the second layer comprises the first rare earth pnictide alloy with Group V elements in second proportions.10. The structure of claim 1 , wherein the second layer is comprised of ...

Stretchable Form of Single Crystal Silicon for High Performance Electronics on Rubber Substrates

The present invention provides stretchable, and optionally printable, semiconductors and electronic circuits capable of providing good performance when stretched, compressed, flexed or otherwise deformed. Stretchable semiconductors and electronic circuits of the present invention preferred for some applications are flexible, in addition to being stretchable, and thus are capable of significant elongation, flexing, bending or other deformation along one or more axes. Further, stretchable semiconductors and electronic circuits of the present invention may be adapted to a wide range of device configurations to provide fully flexible electronic and optoelectronic devices. 1. A stretchable semiconductor element comprising:a flexible substrate having a supporting surface; anda semiconductor structure having a curved internal surface, wherein at least a portion of said curved internal surface is bonded to said supporting surface of said flexible substrate.2. The stretchable semiconductor element of wherein said semiconductor structure is a bent semiconductor structure.3. The stretchable semiconductor element of wherein said bent semiconductor structure has a wave-shaped claim 2 , wrinkled claim 2 , coiled or buckled conformation.4. The stretchable semiconductor element of wherein said bent semiconductor structure is under strain.5. The stretchable semiconductor element of wherein said bent semiconductor structure is under strain selected over the range of about 1% to about 30%.6. The stretchable semiconductor element of wherein said curved internal surface has at least one convex region claim 1 , at least one concave region or a combination of at least one convex region and at least one concave region.7. The stretchable semiconductor element of wherein said curved internal surface has a contour profile comprising a periodic wave or an aperiodic wave.8. The stretchable semiconductor element of wherein said bent semiconductor structure has a conformation comprising a ...

METHOD FOR FABRICATING A SEMICONDUCTOR AND SEMICONDUCTOR PACKAGE

A method for fabricating a semiconductor chip module and a semiconductor chip package is disclosed. One embodiment provides a first layer, a second layer, and a base layer. The first layer is disposed on the base layer, and the second layer is disposed on the first layer. A plurality of semiconductor chips is applied above the second layer, and the second layer with the applied semiconductor chips is separated from the first layer. 1. (canceled)2. A semiconductor chip package , comprising:a semiconductor chip having a front surface and a back surface opposite the front surface, and the semiconductor chip having side surfaces between the front surface and the back surface;a contact pad on the front surface of the semiconductor chip;a mold material layer on the back surface and side surfaces of the semiconductor chip, the mold material layer having a front surface and a back surface opposite the front surface, and the mold material layer having side surfaces between the front surface and the back surface, wherein the front surface of the mold material layer is co-planar with the front surface of the semiconductor chip;a dielectric layer on the front surface of the mold material and on the front surface of the semiconductor chip, the dielectric layer having side surfaces in vertical alignment with the side surfaces of the mold material layer;an electrical conductor in the dielectric layer, the electrical conductor in contact with the contact pad, and the electrical conductor having a width; anda conductive contact area in the dielectric layer, the conductive contact area in contact with the electrical conductor, the electrical contact area having a width greater than a width of the electrical conductor, and the conductive contact area having a surface co-planar with the dielectric layer.3. The semiconductor chip package of claim 2 , wherein the dielectric layer comprises an additive.4. The semiconductor chip package of claim 2 , wherein the mold material layer ...

NICKEL LANTHANIDE ALLOYS FOR MEMS PACKAGING APPLICATIONS

A semiconductor package including a semiconductor die and at least one bondline positioned on the semiconductor die, the at least one bondline comprising a nickel lanthanide alloy diffusion barrier layer abutting a gold layer. 1. A semiconductor package comprising:a semiconductor die; andat least one bondline positioned on the semiconductor die, the at least one bondline comprising a nickel lanthanide alloy layer abutting a gold layer.2. The semiconductor package of claim 1 , wherein the at least one bondline further comprises at least one other bondline layer claim 1 , wherein the nickel lanthanide alloy layer does not alloy with the at least one other bondline layer.3. The semiconductor package of claim 2 , wherein the at least one other bondline layer comprises indium claim 2 , a seed metal claim 2 , a base metal claim 2 , or a combination thereof.4. The semiconductor package of claim 3 , wherein the base metal comprises copper claim 3 , and wherein the seed metal comprises titanium claim 3 , or both.5. The semiconductor package of claim 1 , wherein the semiconductor die comprises a complementary metal-oxide semiconductor (CMOS).6. A Micro-Electro-Mechanical System (MEMS) package claim 1 , comprising:a semiconductor wafer;a substrate spaced apart from the semiconductor wafer; anda bondline positioned between and in contact with the semiconductor wafer and the substrate, the bondline comprising a nickel lanthanide alloy layer and a gold layer.7. The MEMS package of claim 6 , wherein the substrate comprises a semiconductor wafer.8. The MEMS package of further comprising indium incorporated into the bondline as an interlayer element for transient liquid phase bonding between the gold and the indium.9. The MEMS package of claim 6 , wherein the lanthanide comprises cerium claim 6 , lanthanum claim 6 , erbium claim 6 , or a combination thereof.10. The MEMS package of claim 6 , wherein the gold layer has a thickness in a range of from about 0.1 μm to about 20 μm.11. The ...

A 3d semiconductor device and system

A 3D semiconductor device, the device including: a first crystalline silicon layer including a plurality of first transistors; a first metal layer interconnecting the first transistors, a portion of the first transistors forming a plurality of first logic gates; a first array of memory cells including second transistors; a second metal layer overlying the first and second transistors; a second crystalline silicon layer overlaying the second metal layer and the second crystalline silicon layer including a plurality of third transistors; a third metal layer interconnecting the third transistors, a portion of the third transistors forming a plurality of second logic gates; a second array of memory cells including fourth transistors and overlaying the second crystalline silicon layer; a fourth metal layer overlying the third and fourth transistors, where at least one of the fourth transistors is overlaying at least another one of the fourth transistors such that they are self-aligned, having been processed following the same lithography step, where the second array of memory cells include NAND flash type memory cells.

SEMICONDUCTOR DEVICE

In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package. 1. A semiconductor device comprising:a semiconductor chip having a first side, a second side opposite the first side, a first upper surface on which a plurality of electrodes is formed and a first back surface opposite the first upper surface;a tab having a first side, a second upper surface to which the semiconductor chip is fixed;a plurality of leads arranged along the first side of the tab in a plan view;a plurality of first wires connecting a plurality of first electrodes of the plurality of electrodes with the plurality of leads, respectively;a plurality of second wires connecting a plurality of second electrodes of the plurality of electrodes with the tab, respectively; anda seal member sealing the semiconductor chip, the tab, a part of each of the plurality of leads, the plurality of first wires and the plurality of second wires,wherein, in the plan view, the plurality of electrodes of the semiconductor chip is arranged along the first side of the semiconductor chip,wherein, in the plan view, the first side of the semiconductor chip extends in a first direction and is disposed between the second side of the semiconductor chip and the first side of the tab, ...

Method for fabricating a semiconductor and semiconductor package

A method for fabricating a semiconductor chip module and a semiconductor chip package is disclosed. One embodiment provides a first layer, a second layer, and a base layer. The first layer is disposed on the base layer, and the second layer is disposed on the first layer. A plurality of semiconductor chips is applied above the second layer, and the second layer with the applied semiconductor chips is separated from the first layer.

3D SEMICONDUCTOR DEVICE AND SYSTEM

A 3D semiconductor device, the device including: a first layer including a first single crystal transistor; a second layer including second transistors; a third layer including third transistors; a fourth layer including fourth transistors, where the first layer is overlaid by the second layer, where the second layer is overlaid by the third layer, and where the third layer is overlaid by the fourth layer; where a plurality of the fourth transistors are aligned to the plurality of the first single crystal transistor with less than 40 nm alignment error, where the third transistors are junction-less transistors (JLT), where each of the fourth transistors include a transistor channel, a drain and a source, and where the transistor channel is significantly narrower than the drain or the source. 1. A 3D semiconductor device , the device comprising:a first level comprising a first single crystal transistor;a second level comprising second transistors;a third level comprising third transistors; wherein said first level is underneath said second level,', 'wherein said second level is underneath said third level, and', 'wherein said third level is underneath said fourth level;, 'a fourth level comprising fourth transistors,'} 'wherein said at least first metal layer and second metal layer comprise connections between a plurality of said first single crystal transistor; and', 'at least a first metal layer and a second metal layer,'} wherein said NAND type memory cells comprise a plurality of said third transistors,', 'wherein a plurality of said fourth transistors are aligned to said plurality of said first single crystal transistor with less than 140 nm alignment error,', 'wherein said second metal layer is above said first metal layer,', 'wherein said first metal layer comprises a first current carrying capacity,', 'wherein said second metal layer comprises a second current carrying capacity,', 'wherein said first current carrying capacity is significantly greater than ...

Semiconductor device and production method therefor

An object of the invention is to provide a method for producing a conductive member having low electrical resistance, and the conductive member is obtained using a low-cost stable conductive material composition that does not contain an adhesive. A method for producing a semiconductor device in which silver or silver oxide provided on a surface of a base and silver or silver oxide provided on a surface of a semiconductor element are bonded, includes the steps of arranging a semiconductor element on a base such that silver or silver oxide provided on a surface of the semiconductor element is in contact with silver or silver oxide provided on a surface of the base, and bonding the semiconductor element and the base by applying heat having a temperature of 200 to 900° C. to the semiconductor device and the base.

RADIATION HARDENED MICROELECTRONIC CHIP PACKAGING TECHNOLOGY

A novel radiation hardened chip package technology protects microelectronic chips and systems in aviation/space or terrestrial devices against high energy radiation. The proposed technology of a radiation hardened chip package using rare earth elements and mulitlayered structure provides protection against radiation bombardment from alpha and beta particles to neutrons and high energy electromagnetic radiation. 1. A method for forming a hardened chip package for a circuit chip , comprising:providing a circuit chip;coating the circuit chip with an alpha particle shielding material;coating the alpha particle shielding material with a high energy particle shielding composite material;coating the high energy particle shielding composite material with a high energy electromagnetic (EM) wave shielding composite material wherein a coated circuit chip is formed; andencapsulating the coated circuit chip, the alpha particle shielding material, the high energy particle shielding composite material and the high energy EM wave shielding composite material with a molding compound.2. The method of following the coating with an alpha particle shielding material step claim 1 , further comprising:etching holes in the alpha particle shielding material coating for the attachment of wiring.3. The method of following the coating with a high energy EM wave shielding composite material step claim 1 , further comprising:etching holes in the alpha particle shielding material coating, the high energy particle shielding composite material and the high energy EM wave shielding composite material for the attachment of wiring;slicing the coated circuit chip into a plurality of dies;attaching each of the plurality of dies to a pad; andattaching at least one wire to the circuit chip.4. The method of wherein the alpha particle shielding material is a pristine polyimide.5. The method of wherein the alpha particle shielding material is a siloxane containing polyimide.6. The method of wherein the high ...

Multiple access over proximity communication

A multiple access Proximity Communication system in which electrical elements on an integrated circuit chip provide the multiplexing of multiple signals to a single electrical receiving element on another chip. Multiple pads formed on one chip and receiving separate signals may be capacitively coupled to one large pad on the other chip. Multiple inductive coils on one chip may be magnetically coupled to one large coil on another chip or inductive coils on three or more chips may be used for either transmitting or receiving. The multiplexing may be based on time, frequency, or code.

Semiconductor element comprising a supporting structure and production method

One or more embodiments are related to a semiconductor component comprising a supporting structure arranged in a first layer sequence, a second layer arranged above the first layer sequence, and a bonding pad. The layer sequence may comprise a plurality of layers of a dielectric and the bonding pad is arranged above the second layer. The supporting structure may comprise a plurality of supporting substructures and is formed under partial regions of the bonding pad.

3D SEMICONDUCTOR DEVICE AND SYSTEM

A 3D semiconductor device, the device including: a first level including a plurality of first single crystal transistors; contact plugs; a first metal layer, where a portion of the contact plugs provide connections from the plurality of first single crystal transistors to the first metal layer, and where connections include forming memory control circuits; a second level including a plurality of second transistors; a third level including a plurality of third transistors, where the second level overlays the first level, the third level overlays the second level; a second metal layer overlaying the third level; and a third metal layer overlaying the second metal layer, where second transistors are aligned to first transistors with less than 40 nm alignment error, where the second level includes first memory cells, where the third level includes second memory cells, and where the memory control circuits are designed to adjust a memory write voltage according to the device specific process parameters. 1. A 3D semiconductor device , the device comprising:a first level comprising a plurality of first single crystal transistors; 'wherein said first single crystal transistors comprise forming memory control circuits;', 'a first metal layer,'}a second level comprising a plurality of second transistors; wherein said second level overlays said first level, and', 'wherein said third level overlays said second level;, 'a third level comprising a plurality of third transistors,'}a second metal layer overlaying said third level; and wherein said plurality of second transistors are aligned to said plurality of first single crystal transistors with less than 140 nm alignment error,', 'wherein said third metal comprises bit lines,', 'wherein said second level comprises a plurality of first memory cells,', 'wherein said third level comprises a plurality of second memory cells,', 'wherein one of said plurality of second transistors is at least partially self-aligned to at least one of ...

3D SEMICONDUCTOR DEVICE AND SYSTEM

A 3D semiconductor device including: a first level including first single crystal transistors and a first metal layer; a second level including a plurality of second transistors; where the second level includes memory cells including the plurality of second transistors; a third level including a plurality of third transistors, where the second level overlays the first level, and where the third level overlays the second level; a second metal layer overlaying the third level; and vertically oriented conductive plugs, the vertically oriented conductive plugs connect from the second transistors to the first metal layer, where the second transistors are aligned to the first transistors with less than 100 nm alignment error, where the second transistors are junction-less transistors, and where one end of at least one of the vertically oriented conductive plugs functions also as a contact to a portion of each of the plurality of second transistors. 1. A 3D semiconductor device , the device comprising: 'wherein said logic circuits comprise a plurality of first single crystal transistors and a first metal layer;', 'a first level comprising logic circuits,'} 'wherein said second level comprises memory cells comprising said plurality of second transistors;', 'a second level comprising a plurality of second transistors,'} wherein said second level is atop said first level, and', 'wherein said third level is atop said second level;, 'a third level comprising a plurality of third transistors,'}a second metal layer atop said third level; and wherein said vertically oriented conductive plugs connect from said second transistors to said first metal layer,', 'wherein said plurality of second transistors are aligned to said plurality of first single crystal transistors with less than 150 nm alignment error,', 'wherein said plurality of second transistors are junction-less transistors,', 'wherein one end of at least one of said vertically oriented conductive plugs functions also as a ...

Light emitting device including light emitting element with phosphor

A light emitting device includes a light emitting element, a molded member, and a sealing member. The light emitting element is arranged on or above the molded member. The sealing member covers the light emitting element. The sealing member contains a phosphor, and a filler material. The phosphor can be excited by light of the light emitting element, and emit luminescent radiation. The filler material contains neodymium hydroxide, neodymium aluminate or neodymium silicate. The filler material absorbs a part of the spectrum of the mixed light of the light emitting element and the phosphor so that the other parts of the spectrum of this mixed light are extracted from the light emitting device.

Semiconductor die package and method for making the same

Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.

3D SEMICONDUCTOR DEVICE AND SYSTEM

A 3D semiconductor device including: a first level comprising first single crystal transistors, a first metal layer, and a plurality of latches; a second level comprising a plurality of second transistors, wherein said second level comprises first memory cells, and wherein said first memory cells each comprise at least one of said plurality of second transistors; a third level comprising a plurality of third transistors, wherein said third level comprises second memory cells, wherein said second memory cells each comprise at least one of said plurality of third transistors, wherein said second level overlays said first level, and wherein said third level overlays said second level; a second metal layer overlaying said third level, said second metal layer comprising a plurality of bit-lines, wherein said plurality of second transistors are aligned to said first single crystal transistors with less than 100 nm alignment error, wherein said plurality of second transistors are junction-less transistors, and wherein each of said plurality of bit lines is connected to at least one of said plurality of latches. 1. A 3D semiconductor device , the device comprising:a first level comprising first single crystal transistors, a first metal layer, and a plurality of latches; wherein said second level comprises first memory cells, and', 'wherein said first memory cells each comprise at least one of said plurality of second transistors;, 'a second level comprising a plurality of second transistors,'} wherein said third level comprises second memory cells,', 'wherein said second memory cells each comprise at least one of said plurality of third transistors,', 'wherein said second level is above said first level, and', 'wherein said third level is above said second level;, 'a third level comprising a plurality of third transistors,'} wherein said plurality of second transistors are aligned to said first single crystal transistors with less than 150 nm alignment error,', 'wherein ...

Method of forming high voltage device

A method of forming a device includes forming a buried well region of a first dopant type in a substrate. A well region of the first dopant type is formed over the buried well region. A first well region of a second dopant type is formed between the well region of the first dopant type and the buried well region of the first dopant type. A second well region of the second dopant type is formed in the well region of the first dopant type. An isolation structure is formed at least partially in the well region of the first dopant type. A first gate electrode is formed over the isolation structure and the second well region of the second dopant type.

ROOM TEMPERATURE METAL DIRECT BONDING

A bonded device structure including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads formed by contact bonding of the first non-metallic region to the second non-metallic region. At least one of the first and second substrates may be elastically deformed. 1. A bonded structure comprising:a first plurality of metallic pads disposed on a first substrate;a first non-metallic region located on a first surface of said first substrate proximate to the first plurality of metallic pads;a second plurality of metallic pads disposed on a second substrate; anda second non-metallic region located on a second surface of the second substrate proximate to the second plurality of metallic pads,wherein a portion of each metallic pad of the first plurality of metallic pads directly contacts a corresponding metallic pad of the second plurality of metallic pads to form a metallic contact, andwherein the first non-metallic region contacts and is directly bonded to the second non-metallic region along an interface, the interface between the first non-metallic region and the second non-metallic region extending substantially to the metallic contact.2. The bonded structure of claim 1 , wherein each metallic pad comprises a reflowable material.3. The bonded structure of claim 1 , wherein the first non-metallic region comprises silicon oxide. This application is a continuation of application Ser. No. 14/959,204 filed Dec. 4, 2015, which is a continuation of application Ser. No. 14/474,476 ...

Semiconductor Device and Method of Providing Z-Interconnect Conductive Pillars with Inner Polymer Core

A semiconductor device is made by providing a sacrificial substrate and depositing an adhesive layer over the sacrificial substrate. A first conductive layer is formed over the adhesive layer. A polymer pillar is formed over the first conductive layer. A second conductive layer is formed over the polymer pillar to create a conductive pillar with inner polymer core. A semiconductor die or component is mounted over the substrate. An encapsulant is deposited over the semiconductor die or component and around the conductive pillar. A first interconnect structure is formed over a first side of the encapsulant. The first interconnect structure is electrically connected to the conductive pillar. The sacrificial substrate and adhesive layers are removed. A second interconnect structure is formed over a second side of the encapsulant opposite the first interconnect structure. The second interconnect structure is electrically connected to the conductive pillar.

LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING LIGHT EMITTING DEVICE

A light emitting device () includes a base member (), electrically conductive members () disposed on the base member (), a light emitting element () mounted on the electrically conductive members (), an insulating filler () covering at least a portion of surfaces of the electrically conductive members () where the light emitting element () is not mounted, and a light transmissive member () covering the light emitting element (). 1. A light emitting device comprising:a light emitting element having a semiconductor layer and a transparent substrate;a reflective member exposing at least apart of side surfaces and a top surface of the transparent substrate and covering side surfaces of the semiconductor layer; anda light transmissive member covering a portion of the transparent substrate exposed from the reflective member.2. The light emitting device according to further comprising a base member and electrically conductive members disposed on the base member claim 1 , wherein the light emitting element is mounted on the electrically conductive members claim 1 , at a surface of the electrically conductive members claim 1 , at least a portion of which does not have the light emitting element mounted thereon is covered with an insulating filler which is the reflective member claim 1 , and the light transmissive member covers the light emitting element.3. The light emitting device according to claim 2 , wherein the base member has a recess and the electrically conductive members are disposed on a bottom surface and side surfaces of the recess claim 2 , and the light emitting element is mounted on the bottom surface of the recess.4. The light emitting device according to claim 3 , wherein the side surfaces of the recess has claim 3 , at a portion abutting on a top edge surface of the recess have a region where an electrically conductive member is not formed.5. The light emitting device according to claim 3 , wherein the side surfaces of the recess at a portion abutting on ...

3d semiconductor device and structure

A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where the first transistors each include a single crystal channel; first metal layers interconnecting at least the first transistors; and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where the second transistors are horizontally oriented and each include a High-k metal gate, where the second level is bonded to the first level, and where the bonded includes oxide to oxide bonds.

White light devices using non-polar or semipolar gallium containing materials and phosphors

A packaged optical device includes a substrate having a surface region with light emitting diode devices fabricated on a semipolar or nonpolar GaN substrate. The light emitting diodes emit polarized light and are characterized by an overlapped electron wave function and a hole wave function. Phosphors within the package are excited by the polarized light and, in response, emit electromagnetic radiation of a second wavelength.

Sensor package and method for producing a sensor package

Some embodiments herein relate to a sensor package. The sensor package includes a printed circuit board with a laminar current conductor arranged on a first main surface of the printed circuit board. The sensor package also includes a sensor chip adapted to measure a current flowing through the laminar current conductor, wherein the sensor chip comprises a magnetic field sensor. The sensor chip is electrically insulated from the current conductor by the printed circuit board, and is arranged on a second main surface of the printed circuit board opposite to the first main surface. The sensor chip is hermetically sealed between the mold material and the printed circuit board, or is arranged in the printed circuit board and hermetically sealed by the printed circuit board.

Light emitting device and method for manufacturing the same

By using a light emitting device including an insulating substrate and a light emitting unit formed on the insulating substrate, the light emitting unit including: a plurality of linear wiring patterns disposed on the insulating substrate in parallel with one another, a plurality of light emitting elements that are mounted between the wiring patterns while being electrically connected to the wiring patterns, and a sealing member for sealing the light emitting elements, as well as a method for manufacturing thereof, it becomes possible to provide a light emitting device that achieves sufficient electrical insulation and has simple manufacturing processes so that it can be manufactured at a low cost, and a method for manufacturing the same.

3D SEMICONDUCTOR DEVICE AND SYSTEM

A 3D semiconductor device, the device including: a first level including a plurality of first single crystal transistors; contact plugs; a first metal layer, where the contact plugs are connected to the plurality of first single crystal transistors and the first metal layer, where the first metal layer interconnect the first single crystal transistors forming memory control circuits; a second level overlaying the first level, the second level including a plurality of second transistors; a third level overlaying the second level, the third level including a plurality of third transistors; a second metal layer; a third metal layer, where the second metal layer overlays the third level, where the third metal layer overlays the second metal layer, where the second level includes a plurality of first memory cells, where the third level includes a plurality of second memory cells, where the memory control circuits include control sub-circuits to remap a degraded memory block to an alternative memory space within the device. 1. A 3D semiconductor device , the device comprising:a first level comprising a plurality of first single crystal transistors;contact plugs; wherein said contact plugs are connected to said plurality of first single crystal transistors and said first metal layer, and', 'wherein said first metal layer interconnect said first single crystal transistors forming memory control circuits;, 'a first metal layer,'}a second level above said first level, said second level comprising a plurality of second transistors;a third level above said second level, said third level comprising a plurality of third transistors;a second metal layer; wherein said second metal layer is above said third level,', 'wherein said third metal layer is above said second metal layer,', 'wherein said second transistors are aligned to said first transistors with less than 140 nm alignment error,', 'wherein said third metal comprise bit lines,', 'wherein said second level comprises a ...

METHOD FOR PRODUCING A 3D MEMORY DEVICE

A method for producing a 3D memory device including: providing a first level including a single crystal layer; forming at least one second level above the first level; performing a first etch step including etching holes within the second level; forming at least one third level above the at least one second level; performing a second etch step including etching holes within the third level; performing additional processing steps to form memory cells within the second level and within the third level, each of the first memory cells include one first transistor, each of the second memory cells include one second transistor, where at least one of the first or second transistors has a channel, a source and a drain having the same doping type, the memory is NAND, the first level includes memory peripheral circuits, at least one of the first memory cells is at least partially atop a portion of the peripheral circuits. 1. A method for producing a 3D memory device , the method comprising:providing a first level comprising a single crystal layer;forming at least one second level above said first level;performing a first etch step comprising etching holes within said second level;forming at least one third level above said at least one second level;performing a second etch step comprising etching holes within said third level; wherein each of said first memory cells comprise one first transistor,', 'wherein each of said second memory cells comprise one second transistor,', 'wherein at least one of said first or second transistors has a channel, a source and a drain having the same doping type,', 'wherein said memory is a NAND nonvolatile type memory,', 'wherein said first etch step is directly followed by a deposition of tunneling dielectric and then a deposition comprising polysilicon,', 'wherein said first level comprises memory peripheral circuits, and', 'wherein at least one of said first memory cells is at least partially atop a portion of said memory peripheral circuits ...

Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same

A stacked-chip apparatus includes a package substrate and an interposer with a chip stack disposed with a standoff that matches the interposer. A package-on-package stacked-chip apparatus includes a top package disposed on the interposer.

Current sensors and methods

Embodiments relate to current sensors and methods. In an embodiment, a current sensor comprises a leadframe; a semiconductor die coupled to the leadframe; a conductor comprising a metal layer on the semiconductor die, the conductor comprising at least one bridge portion and at least two slots, a first slot having a first tip and a second slot having a second tip, a distance between the first and second tips defining a width of one of the at least one bridge portion, wherein the conductor is separated from the leadframe by at least a thickness of the semiconductor die, and the thickness is about 0.2 millimeters (mm) to about 0.7 mm; and at least one magnetic sensor element arranged on the die relative to and spaced apart from the one of the at least one bridge portion and more proximate the conductor than the leadframe.

Resin molding, surface mounted light emitting apparatus and methods for manufacturing the same

The present invention provides a surface mounted light emitting apparatus which has long service life and favorable property for mass production, and a molding used in the surface mounted light emitting apparatus. The surface mounted light emitting apparatus comprises the light emitting device 10 based on GaN which emits blue light, the first resin molding 40 which integrally molds the first lead 20 whereon the light emitting device 10 is mounted and the second lead 30 which is electrically connected to the light emitting device 10 , and the second resin molding 50 which contains YAG fluorescent material and covers the light emitting device 10 . The first resin molding 40 has the recess 40 c comprising the bottom surface 40 a and the side surface 40 b formed therein, and the second resin molding 50 is placed in the recess 40 c . The first resin molding 40 is formed from a thermosetting resin such as epoxy resin by the transfer molding process, and the second resin molding 50 is formed from a thermosetting resin such as silicone resin.

Light emitting device and method for manufacturing the same

By using a light emitting device including an insulating substrate and a light emitting unit formed on the insulating substrate, the light emitting unit including: a plurality of linear wiring patterns disposed on the insulating substrate in parallel with one another, a plurality of light emitting elements that are mounted between the wiring patterns while being electrically connected to the wiring patterns, and a sealing member for sealing the light emitting elements, as well as a method for manufacturing thereof, it becomes possible to provide a light emitting device that achieves sufficient electrical insulation and has simple manufacturing processes so that it can be manufactured at a low cost, and a method for manufacturing the same.

Integrated circuit device

An integrally packaged optronic integrated circuit device including an integrated circuit die containing at least one of a radiation emitter and radiation receiver and having a transparent packaging layer overlying a surface of the die, the transparent packaging layer having an opaque coating adjacent to edges of the layer.

METHODS TO PRODUCE A 3D SEMICONDUCTOR MEMORY DEVICE AND SYSTEM

A method for producing a 3D memory device, the method including: providing a first level including a single crystal layer; forming at least one second level above the first level; performing a first etch step including etching holes within the second level; forming at least one third level above the at least one second level; performing a second etch step including etching holes within the third level; and performing additional processing steps to form a plurality of first memory cells within the second level and a plurality of second memory cells within the third level, where each of the first memory cells includes one first transistor, where each of the second memory cells includes one second transistor, where at least one of the first or second transistors has a channel, a source and a drain having the same doping type, and where the forming at least one third level includes forming a window within the third level so to allow a lithography alignment through the third level to an alignment mark disposed underneath the third level. 1. A method for producing a 3D memory device , the method comprising:providing a first level comprising a single crystal layer;forming at least one second level above said first level;performing a first etch step comprising etching holes within said second level;forming at least one third level above said at least one second level;performing a second etch step comprising etching holes within said third level; and wherein each of said first memory cells comprises one first transistor,', 'wherein each of said second memory cells comprises one second transistor,', 'wherein at least one of said first or second transistors has a channel, a source and a drain having the same doping type,', 'wherein said memory is a NAND nonvolatile type memory,', 'wherein said first etch step is directly followed by a deposition of tunneling dielectric and then a deposition comprising polysilicon,', 'wherein said forming at least one third level comprises ...

Nickel lanthanide alloys for mems packaging applications

A semiconductor package including a semiconductor die and at least one bondline positioned on the semiconductor die, the at least one bondline comprising a nickel lanthanide alloy diffusion barrier layer abutting a gold layer.

Resin molding, surface mounted light emitting apparatus and methods for manufacturing the same

The present invention provides a surface mounted light emitting apparatus which has long service life and favorable property for mass production, and a molding used in the surface mounted light emitting apparatus. The surface mounted light emitting apparatus comprises the light emitting device 10 based on GaN which emits blue light, the first resin molding 40 which integrally molds the first lead 20 whereon the light emitting device 10 is mounted and the second lead 30 which is electrically connected to the light emitting device 10 , and the second resin molding 50 which contains YAG fluorescent material and covers the light emitting device 10 . The first resin molding 40 has the recess 40 c comprising the bottom surface 40 a and the side surface 40 b formed therein, and the second resin molding 50 is placed in the recess 40 c . The first resin molding 40 is formed from a thermosetting resin such as epoxy resin by the transfer molding process, and the second resin molding 50 is formed from a thermosetting resin such as silicone resin.

Semiconductor packages and methods of fabricating the same

Provided are a semiconductor package and a method of fabricating the same. In one embodiment, to fabricate a semiconductor package, a wafer having semiconductor chips fabricated therein is provided. A heat sink layer is formed over the wafer. The heat sink layer contacts top surfaces of the semiconductor chips. Thereafter, the plurality of semiconductor chips are singulated from the wafer.

Power semiconductor device and method therefor

A power transistor includes a plurality of transistor cells. Each transistor cell has a first electrode coupled to a first electrode interconnection region overlying a first major surface, a control electrode coupled to a control electrode interconnection region overlying the first major surface, and a second electrode coupled to a second electrode interconnection region overlying a second major surface. Each transistor cell has an approximately constant doping concentration in the channel region. A dielectric platform is used as an edge termination of an epitaxial layer to maintain substantially planar equipotential lines therein. The power transistor finds particular utility in radio frequency applications operating at a frequency greater than 500 megahertz and dissipating more than 5 watts of power. The semiconductor die and package are designed so that the power transistor can efficiently operate under such severe conditions.

3D SEMICONDUCTOR DEVICE, FABRICATION METHOD AND SYSTEM

A 3D memory device, the device including: a first single crystal layer including memory peripheral circuits; a first memory layer including a first junction-less transistor; a second memory layer including a second junction-less transistor; and a third memory layer including a third junction-less transistor, where the first memory layer overlays the first single crystal layer, where the second memory layer overlays the first memory layer, where the third memory layer overlays the second memory layer, where the first junction-less transistor, the second junction-less transistor and the third junction-less transistor are formed by a single lithography and etch process, and where the first memory layer includes a nonvolatile NAND type memory. 120-. (canceled)21. A method for fabrication of a 3D semiconductor device , the method comprising:providing a substrate comprising a single crystal layer;forming a plurality of first transistors in and on said single crystal layer; then 'wherein a portion of said at least one metal layer comprising connections between said first transistors form memory peripheral circuits, said peripheral circuits comprise decoder circuits; then', 'forming at least one metal layer, said at least one metal layer comprising connections between said first transistors,'} wherein said stack of at least sixteen layers comprises odd numbered layers and even numbered layers,', 'wherein said odd numbered layers comprise a first material and said even numbered layers comprise a second material,', 'wherein said first material is of a different composition than said second material, and', 'wherein said forming a stack is performed as part of forming a multilevel memory structure; and then, 'forming a stack of at least sixteen layers,'} wherein said at least eight layers of memory cells are controlled by said periphery circuits,', 'wherein at least said forming a stack of at least sixteen layers and said processing said stack of at least sixteen layers ...

SEMICONDUCTOR DEVICE AND INSPECTION DEVICE

A semiconductor device includes a pair of electrodes and a conductive connection member electrically bonded to the pair of electrodes At least a portion of a perimeter of a bonding surface of at least one of the pair of electrodes and the conductive connection member includes an electromigration reducing area 1. A semiconductor device comprising:a pair of electrodes; anda conductive connection member electrically bonded to the pair of electrodes, whereinat least a portion of a perimeter of a bonding surface of at least one of the pair of electrodes and the conductive connection member comprises an electromigration reducing area.2. The semiconductor device according to claim 1 , wherein the electromigration reducing area is an area of the perimeter of the bonding surface.3. The semiconductor device according to claim 1 , wherein the electromigration reducing area is an end area on an upstream side in a current direction of the perimeter of the bonding surface of the conductive connection member.4. The semiconductor device according to claim 1 , wherein the electromigration reducing area is an area of at least a portion of the perimeter of the bonding surface of at least either of the pair of electrodes and the conductive connection member.5. The semiconductor device according to claim 1 , wherein the electromigration reducing area is an additive containing area containing an additive for reducing diffusion of the electromigration or reducing electrical conductivity of a base material of the bonding surface.6. The semiconductor device according to claim 5 , wherein a content of the additive contained in the electromigration reducing area is 0.1% or greater by mass and 20.0% or lower by mass.7. The semiconductor device according to claim 5 , wherein the additive is at least one type selected from a group comprising Al claim 5 , Cu claim 5 , Si claim 5 , Ni claim 5 , Cr claim 5 , Mg claim 5 , Au claim 5 , Ag claim 5 , Ta claim 5 , Fe claim 5 , a molybdenum-tungsten ...

Microelectronic elements with post-assembly planarization

A microelectronic unit can include a carrier structure having a front surface, a rear surface remote from the front surface, and a recess having an opening at the front surface and an inner surface located below the front surface of the carrier structure. The microelectronic unit can also include a microelectronic element having a top surface adjacent the inner surface, a bottom surface remote from the top surface, and a plurality of contacts at the top surface. The microelectronic unit can also include terminals electrically connected with the contacts of the microelectronic element. The terminals can be electrically insulated from the carrier structure. The microelectronic unit can also include a dielectric region contacting at least the bottom surface of the microelectronic element. The dielectric region can define a planar surface located coplanar with or above the front surface of the carrier structure.

Microelectronic elements with post-assembly planarization

A microelectronic unit can include a carrier structure having a front surface, a rear surface remote from the front surface, and a recess having an opening at the front surface and an inner surface located below the front surface of the carrier structure. The microelectronic unit can also include a microelectronic element having a top surface adjacent the inner surface, a bottom surface remote from the top surface, and a plurality of contacts at the top surface. The microelectronic unit can also include terminals electrically connected with the contacts of the microelectronic element. The terminals can be electrically insulated from the carrier structure. The microelectronic unit can also include a dielectric region contacting at least the bottom surface of the microelectronic element. The dielectric region can define a planar surface located coplanar with or above the front surface of the carrier structure.

METHOD FOR PRODUCING A 3D SEMICONDUCTOR MEMORY DEVICE AND STRUCTURE

A method for producing a 3D memory device, the method comprising: providing a first level comprising a first single crystal layer; forming first alignment marks and control circuits comprising first single crystal transistors, wherein said control circuits comprise at least two metal layers; forming at least one second level above said control circuits; performing a first etch step within said second level; forming at least one third level above said at least one second level; performing a second etch step within said third level; and performing additional processing steps to form a plurality of first memory cells within said second level and a plurality of second memory cells within said third level, wherein said first etch step comprises performing a lithography step aligned to said first alignment marks. 1. A method for producing a 3D memory device , the method comprising:providing a first level comprising a first single crystal layer; wherein said control circuits comprise first single crystal transistors, and', 'wherein said control circuits comprise at least two interconnection metal layers;, 'forming first alignment marks and control circuits in and on said first level,'}forming at least one second level disposed on top of said control circuits;performing a first etch step comprising a first etching of first holes within said second level;forming at least one third level disposed on top of said at least one second level;performing a second etch step comprising a second etching of second holes within said third level; and wherein said forming at least one second level comprises forming lithography holes atop of said first alignment marks to enable performing lithography steps aligned to said first alignment marks,', 'wherein said first etch step comprises performing at least one of said lithography steps aligned to said first alignment marks, and', 'wherein said second etch step comprises performing at least one of said lithography steps aligned to said first ...

COMPUTING SYSTEM WITH A THERMAL INTERFACE COMPRISING MAGNETIC PARTICLES

Embodiments of the present disclosure provide techniques and configurations for a computing system with a thermal interface having magnetic particles. In some embodiments, the computing system may include a first part, a second part, and a thermal interface to couple the first and second parts. The thermal interface may comprise a thermal interface material having magnetic particles that are aligned in a defined direction relative to a surface of the first or second part, to provide desired thermal conductivity between the first and second parts. The defined direction of alignment of magnetic particles may comprise an alignment of the particles substantially perpendicularly to the surface of the first or second part. Other embodiments may be described and/or claimed. 1. A package assembly , comprising:a die; anda thermal interface disposed on the die, wherein the thermal interface comprises:a preform that includes a thermal interface material having magnetic particles that are self-aligned substantially perpendicularly to a surface of the die, and a polymer compound disposed on a first surface of the thermal interface material that faces the die, and one a second surface of the thermal interface material that faces a layer of the package assembly coupled with the die via the thermal interface,wherein the thermal interface is to provide desired thermal conductivity between the die and the layer of the package assembly coupled with the die via the thermal interface.2. The package assembly of claim 1 , wherein the layer of the package assembly comprises an integrated heat spreader (IHS).3. The package assembly of claim 2 , wherein the polymer compound disposed on the first surface of the thermal interface material is to provide a desired thermal contact between the thermal interface and the die.4. The package assembly of claim 3 , wherein the polymer compound disposed on a-the second surface of the thermal interface material is to provide a desired thermal contact ...

SEMICONDUCTOR DEVICE

A semiconductor device including a semiconductor chip having a first conduction element; a substrate having second and third conduction elements; and external connection elements configured to form an electrical path between the second and third conduction elements via the first conduction element. 1. (canceled)2. A semiconductor device , comprising:a semiconductor chip having a face comprising a plurality of contact elements, and the semiconductor chip having a backside opposite the face;a mold mass on the backside of the semiconductor chip and along sides of the semiconductor chip;a first dielectric layer having a first side opposite a second side, the first side of the first dielectric layer on the face of the chip and on the mold mass;a plurality of contacts within the first dielectric layer;a metallization layer on the second side of the first dielectric layer, the metallization layer comprising a plurality of conducting elements, the plurality of conducting elements coupled directly to the plurality of contact elements of the face of the semiconductor chip by the plurality of contacts, wherein a first one and a second one of the plurality of conducting elements of the metallization layer are electrically coupled to one another by one of the plurality of contact elements of the face of the semiconductor chip, and wherein a third one of the of the plurality of conducting elements of the metallization layer is between the first one and the second one of the plurality of conducting elements of the metallization layer;a second dielectric layer on the metallization layer; anda plurality of vias in the second dielectric layer, the plurality of vias directly coupled to the plurality of conducting elements of the metallization layer, wherein the plurality of vias is both within and outside of the footprint of the chip.3. The semiconductor device of claim 2 , further comprising:a plurality of solder balls, wherein individual ones of the plurality of solder balls are ...

Module Comprising a Semiconductor Chip

A module includes a semiconductor chip having at least a first terminal contact surface and a second terminal contact surface. A first bond element made of a material on the basis of Cu is attached to the first terminal contact surface, and a second bond element is attached to the second terminal contact surface. The second bond element is made of a material different from the material of the first bond element or is made of a type of bond element different from the type of the first bond element.

MICROELECTRONIC DEVICES, STACKED MICROELECTRONIC DEVICES, AND METHODS FOR MANUFACTURING MICROELECTRONIC DEVICES

Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices are described herein. In one embodiment, a set of stacked microelectronic devices includes (a) a first microelectronic die having a first side and a second side opposite the first side, (b) a first substrate attached to the first side of the first microelectronic die and electrically coupled to the first microelectronic die, (c) a second substrate attached to the second side of the first microelectronic die, (d) a plurality of electrical couplers attached to the second substrate, (e) a third substrate coupled to the electrical couplers, and (f) a second microelectronic die attached to the third substrate. The electrical couplers are positioned such that at least some of the electrical couplers are inboard the first microelectronic die. 120-. (canceled)21. A stacked microelectronic device , comprising: a first lower substrate,', 'a first microelectronic die carried on the first lower substrate and electrically coupled to the first lower substrate, and', 'a first upper substrate disposed over the first microelectronic die and electrically coupled to the first lower substrate; and, 'a first microelectronic device, including a second lower substrate,', 'a second microelectronic die carried on the second lower substrate and electrically coupled to the second lower substrate, and', 'a second upper substrate disposed over the second microelectronic die and electrically coupled to the second lower substrate;, 'a second microelectronic device disposed over the first microelectronic device, the second microelectronic device includingwherein the second lower substrate is electrically coupled to the first upper substrate.22. The stacked microelectronic device of wherein the first microelectronic device further includes a first casing at least partially encapsulating a sidewall of the first microelectronic die.23. The stacked microelectronic device of wherein the ...

3D SEMICONDUCTOR DEVICE AND SYSTEM

A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors; at least one first metal layer interconnecting the plurality of first transistors, where the interconnecting includes forming memory peripheral circuits; a plurality of second transistors overlaying the at least one first metal layer; a second metal layer overlaying the plurality of second transistors; a first memory cell overlaying the memory peripheral circuits; and a second memory cell overlaying the first memory cell, where the first memory cell includes at least one of the second transistors, where at least one of the second transistors includes a source, channel and drain, where the source, the channel and the drain have the same dopant type. 1. A 3D semiconductor device , the device comprising:a first single crystal layer comprising a plurality of first transistors; 'wherein said interconnecting comprises forming memory peripheral circuits;', 'at least one first metal layer interconnecting said plurality of first transistors,'}a plurality of second transistors overlaying said at least one first metal layer;a second metal layer overlaying said plurality of second transistors;a first memory cell overlaying said memory peripheral circuits;a second memory cell overlaying said first memory cell;a staircase structure overlaying said first single crystal layer; and wherein said first memory cell comprises at least one of said second transistors,', 'wherein said memory peripheral circuits control at least said first memory cell,', 'wherein at least one of said second transistors comprises a source, channel and drain,', 'wherein said source, said channel and said drain have the same dopant type,', 'wherein said non-volatile NAND memory comprises said first memory cell,', 'wherein at least one of said second transistors comprises a polysilicon channel,', 'wherein said non-volatile NAND memory comprises a memory array structure,', 'wherein said ...

METHOD FOR FABRICATING A SEMICONDUCTOR AND SEMICONDUCTOR PACKAGE

A method for fabricating a semiconductor chip module and a semiconductor chip package is disclosed. One embodiment provides a first layer, a second layer, and a base layer. The first layer is disposed on the base layer, and the second layer is disposed on the first layer. A plurality of semiconductor chips is applied above the second layer, and the second layer with the applied semiconductor chips is separated from the first layer. 1. (canceled)2. A semiconductor chip package , comprising:a semiconductor chip having a front surface and a back surface opposite the front surface, and the semiconductor chip having side surfaces between the front surface and the back surface;a contact pad on the front surface of the semiconductor chip;a mold material layer on the back surface and side surfaces of the semiconductor chip, the mold material layer having a front surface and a back surface opposite the front surface, and the mold material layer having side surfaces between the front surface and the back surface, wherein the front surface of the mold material layer is co-planar with the front surface of the semiconductor chip;a material layer on the front surface of the mold material and on the front surface of the semiconductor chip, the material layer having side surfaces in vertical alignment with the side surfaces of the mold material layer;an electrical conductor in the material layer and protruding from the material layer, the electrical conductor in contact with the contact pad; anda conductive contact area on the material layer, the conductive contact area in contact with sides of a portion of the electrical conductor protruding from the material layer.3. The semiconductor chip package of claim 2 , wherein the material layer comprises a preimpregnated foil.4. The semiconductor chip package of claim 2 , wherein the mold material layer comprises an aliphatic polymer.5. The semiconductor chip package of claim 2 , wherein the mold material layer comprises an aromatic ...

LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME

By using a light emitting device including an insulating substrate and a light emitting unit formed on the insulating substrate, the light emitting unit including: a plurality of linear wiring patterns disposed on the insulating substrate in parallel with one another, a plurality of light emitting elements that are mounted between the wiring patterns while being electrically connected to the wiring patterns, and a sealing member for sealing the light emitting elements, as well as a method for manufacturing thereof, it becomes possible to provide a light emitting device that achieves sufficient electrical insulation and has simple manufacturing processes so that it can be manufactured at a low cost, and a method for manufacturing the same. 1. (canceled)2. A light emitting device comprising:a substrate having a top surface and a bottom surface opposite from the top surface, the substrate including a lighting area and a peripheral area surrounding the lighting area in the top surface of said substrate;a positive electrode land for external connection on the top surface and a negative electrode land for external connection on the top surface, said positive and negative electrode lands being provided on the peripheral area of said substrate;a light emitting unit formed on the lighting area of said substrate, including a plurality of light emitting elements, and a sealing member for sealing and covering the plurality of light emitting elements, the sealing member being located within the lighting area,wherein the sealing member includes a first sealing member layer containing a first fluorescent material and a second sealing member layer that contains a second fluorescent material that is different from the first fluorescent material.3. The light emitting device of claim 1 , wherein the shape of the upper face of sealing member is hexagonal shape claim 1 , a round shape or a rectangular shape.4. The light emitting device of claim 1 , wherein the shape of the upper face of ...

Method for Forming Solder Deposits

A method for forming solder deposits on elevated contact metallizations of terminal faces of a substrate formed in particular as a semiconductor component includes bringing wetting surfaces of the contact metallizations into physical contact with a solder material layer. The solder material is arranged on a solder material carrier. At least for the duration of the physical contact, a heating of the substrate and a tempering of the solder material layer takes place. Subsequently a separation of the physical contact between the contact metallizations wetted with solder material and the solder material layer takes place. 1. Method for forming solder deposits on elevated contact metallizations of terminal faces of a substrate formed in particular as a semiconductor component , in which wetting surfaces of the contact metallizations are brought into physical contact with a solder material layer arranged on a solder material carrier ,at least for the duration of the physical contact a heating of the substrate and a tempering of the solder material layer takes place,and subsequently a separation of the physical contact between the contact metallizations wetted with solder material and the solder material layer takes place.2. Method according to claim 1 ,characterized in that{'b': '15', 'during the formation of the physical contact with the solder material layer () at least the contact metallizations are disposed in a protective medium atmosphere.'}3. Method according to claim 2 ,characterized in thatthe formation of the protective medium atmosphere is effected by the application of a flux layer onto the solder material layer.4. Method according to claim 1 ,characterized in thatthe contacting of the contact metallizations with the solder material layer and the separation of the contact metallizations from the solder material layer is effected by an approach or retreat motion of the substrate.5. Method according to claim 1 ,characterized in thatfor performing the approach or ...

Power semiconductor device and method therefor

A power transistor includes a plurality of transistor cells. Each transistor cell has a first electrode coupled to a first electrode interconnection region overlying a first major surface, a control electrode coupled to a control electrode interconnection region overlying the first major surface, and a second electrode coupled to a second electrode interconnection region overlying a second major surface. Each transistor cell has an approximately constant doping concentration in the channel region. A dielectric platform is used as an edge termination of an epitaxial layer to maintain substantially planar equipotential lines therein. The power transistor finds particular utility in radio frequency applications operating at a frequency greater than 500 megahertz and dissipating more than 5 watts of power. The semiconductor die and package are designed so that the power transistor can efficiently operate under such severe conditions.

LIGHT EMITTING DEVICE

A light emitting device including a transparent board elongated in a first direction and having a first surface and an opposite second surface. Light emitting elements are arranged in the first direction on the first surface side of the board. A transparent bulb houses the board and the elements. A base is connected to the bulb, and leads electrically connect the elements to the base. The leads have a first end portion connected to the base, and an opposite second end portion. Conductive members are respectively connected to the second end portions of the leads, and the conductive members are arranged at both side of the elements on the board in the first direction. A first wavelength converting member is provided on the first surface and seals the elements. The first wavelength converting member is elongated in the first direction. The second surface of the board faces the base. 1. A light emitting device comprising:a transparent board elongated in a first direction and having a first surface on a first surface side thereof and a second surface on a second surface side thereof that is opposite to the first surface side;a plurality of light emitting elements arranged in the first direction on the first surface side of the transparent board;a transparent bulb housing the transparent board and the plurality of light emitting elements;a base connected to the transparent bulb, the base having terminals and configured to be threadedly engaged with a conventional socket for a light bulb; a first end portion connected to the base; and', 'a second end portion opposite to the first end portion;, 'a plurality of leads electrically connecting the plurality of light emitting elements to the base, the plurality of leads respectively havingconductive members respectively connected to the second end portion of respective one of the plurality of leads, the conductive members arranged at both side of the plurality of light emitting elements on the transparent board in the first ...

STACKED SEMICONDUCTOR PACKAGES, METHODS OF FABRICATING THE SAME, AND/OR SYSTEMS EMPLOYING THE SAME

An apparatus includes a first substrate having a first land and a second substrate having a second land. A first molding compound is disposed between the first substrate and the second substrate. A first semiconductor chip is disposed on the first substrate and in contact with the first molding portion. A first connector contacts the first land and a second connector contacts the second land. The second connector is disposed on the first connector. A volume of the second connector is greater than a volume of the first connector. A surface of the first semiconductor chip is exposed. The first molding compound is in contact with the second connector, and at least a portion of the second connector is surrounded by the first molding compound. 1. (canceled)2. A method for fabricating a semiconductor package , comprising:mounting a first semiconductor chip on a first area of a first substrate;disposing a first connector on a second area of the first substrate;placing a first molding compound on the first substrate such that the first molding compound contacts side surfaces of the first semiconductor chip and covers the first connector and a top surface of the first semiconductor chip is not covered with the first molding compound;forming an opening through the first molding compound to expose a portion of the first connector;disposing a second connector and a second semiconductor chip on lower surface and upper surface of a second substrate, respectively; andplacing the second substrate on the first substrate such that the second connector contacts the first connector.3. The method of claim 2 , the opening through the first molding compound is formed by a laser drilling process.4. The method of claim 3 , wherein each of the first and second connectors is a solder ball.5. The method of claim 4 , the second connector has a larger volume than that of the first connector.6. The method of claim 4 , the second connector has a larger radius than that of the first connector.7. ...

Light emitting device

A light emitting device includes a board, light emitting element chips, a wavelength conversion member, a transparent bulb, support leads, and a support base. The board has a first surface and a second surface. The second surface is an opposite side to the first surface. The light emitting element chips are mounted on the first surface side. The wavelength conversion member is formed unitarily with a transparent member. The transparent bulb encloses the board and the light emitting element chips. The support leads secure the light emitting element chips inside the transparent bulb. The support base can be threadedly engaged with a conventional light bulb socket along a socket axis. The wavelength conversion member is provided on a first surface side and a second surface side, and is elongated in a longitudinal direction. The light emitting element chips is aligned along a line that extends in the longitudinal direction.

3d semiconductor device and system

A 3D semiconductor, the device including: a first level including a plurality of first transistors; a first metal layer including interconnects between the plurality of first transistors, where the interconnects between the plurality of first transistors includes forming a plurality of logic gates; a plurality of second transistors overlaying the first metal layer, where at least six of the plurality of first transistors are connected in series forming at least a portion of a NAND logic structure, where the plurality of second transistors are vertically oriented transistors, and where the plurality of second transistors are at least partially directly overlaying the NAND logic structure; a memory cell; and a second metal layer overlaying the plurality of second transistors, where the second metal layer is aligned to the first metal layer with less than 40 nm misalignment, where the second transistors include a p type source and a p type drain.

3D SEMICONDUCTOR DEVICE AND SYSTEM

A 3D semiconductor device, the device including: a substrate including a single crystal layer; a plurality of first transistors in and on the single crystal layer; at least one metal layer, where the at least one metal layer overlays the plurality of first transistors and the at least one metal layer includes connections between the first transistors, and where a portion of the connections between the first transistors form memory peripheral circuits; a stack of at least sixteen layers, where the stack of sixteen layers includes odd numbered layers and even numbered layers of a different composition and overlays the at least one metal layer, a multilevel memory structure, where the multilevel memory structure includes the stack of at least sixteen layers, where the stack of at least sixteen layers includes at least eight layers of memory cells controlled by the memory peripheral circuits. 1. A 3D semiconductor device , the device comprising:a substrate comprising a single crystal layer;a plurality of first transistors in and on said single crystal layer; wherein said at least one metal layer overlays said plurality of first transistors and said at least one metal layer comprises connections between said first transistors, and', 'wherein a portion of said connections between said first transistors form memory peripheral circuits;, 'at least one metal layer,'} wherein said stack of sixteen layers overlays said at least one metal layer,', 'wherein said stack of at least sixteen layers comprises odd numbered layers and even numbered layers,', 'wherein said odd numbered layers comprise a first material and said even numbered layers comprise a second material, and', 'wherein said first material is of a different composition than said second material, a multilevel memory structure,', 'wherein said multilevel memory structure comprises said stack of at least sixteen layers,', 'wherein said stack of at least sixteen layers comprises at least eight layers of memory cells, and ...

3D SEMICONDUCTOR DEVICE AND SYSTEM

A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors and at least one metal layer, where the at least one metal layer interconnecting the first transistors; a plurality of logic gates including the at least one metal layer interconnecting the first transistors; a plurality of second transistors overlaying the at least one metal layer; a plurality of third transistors overlaying the second transistors; a top metal layer overlaying the third transistors; and a memory array including wordlines, where the memory array includes at least four rows by four columns of memory mini arrays, where each of the mini arrays includes at least four rows by four columns of memory cells, and where each of the memory cells includes at least one of the second transistors or at least one of the third transistors. 1. A 3D semiconductor device , the device comprising: 'wherein said at least one metal layer interconnecting said first transistors;', 'a first single crystal layer comprising a plurality of first transistors and at least one metal layer,'}a plurality of logic gates comprising said at least one metal layer interconnecting said first transistors;a plurality of second transistors overlaying said at least one metal layer;a plurality of third transistors overlaying said second transistors;a top metal layer overlaying said third transistors; and wherein said memory array comprises at least four rows by four columns of memory mini arrays,', 'wherein each of said mini arrays comprises at least four rows by four columns of memory cells,', 'wherein each of said memory cells comprises at least one of said second transistors or at least one of said third transistors,', 'wherein each row of said memory cells is controlled by at least one of said wordlines,', 'wherein each of said wordlines is controlled by a logic gate comprising said first transistors,', 'wherein said first single crystal layer comprises row decoders and ...

3D SEMICONDUCTOR DEVICE AND SYSTEM

A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors; at least one metal layer interconnecting the first transistors and forming a plurality of logic gates; a first intermediate metal layer overlaying the at least one metal layer; a second intermediate metal layer overlaying the first intermediate metal layer; where the first intermediate metal layer has a first current carrying capacity, where the second intermediate metal layer has a second current carrying capacity, and where the first current carrying capacity is significantly greater than the second current carrying capacity; a plurality of second transistors overlaying the second intermediate metal layer; and a top metal layer overlaying the second transistors; and a memory cell, where at least one of the second transistors includes a polysilicon transistor channel, where the second transistors are precisely aligned to the first transistors. 1. A 3D semiconductor device , the device comprising:a first single crystal layer comprising a plurality of first transistors;at least one metal layer interconnecting said first transistors and forming a plurality of logic gates;a first intermediate metal layer overlaying said at least one metal layer; wherein said first intermediate metal layer has a first current carrying capacity,', 'wherein said second intermediate metal layer has a second current carrying capacity, and', 'wherein said first current carrying capacity is significantly greater than said second current carrying capacity;, 'a second intermediate metal layer overlaying said first intermediate metal layer;'}a plurality of second transistors overlaying said second intermediate metal layer;a top metal layer overlaying said second transistors; and wherein at least one of said second transistors comprises a polysilicon transistor channel,', 'wherein at least one of said second transistors has a cylinder shape,', 'wherein said second transistors ...

METHOD OF ROOM TEMPERATURE COVALENT BONDING

A method of bonding includes using a bonding layer having a fluorinated oxide. Fluorine may be introduced into the bonding layer by exposure to a fluorine-containing solution, vapor or gas or by implantation. The bonding layer may also be formed using a method where fluorine is introduced into the layer during its formation. The surface of the bonding layer is terminated with a desired species, preferably an NHspecies. This may be accomplished by exposing the bonding layer to an NHOH solution. High bonding strength is obtained at room temperature. The method may also include bonding two bonding layers together and creating a fluorine distribution having a peak in the vicinity of the interface between the bonding layers. One of the bonding layers may include two oxide layers formed on each other. The fluorine concentration may also have a second peak at the interface between the two oxide layers. 1. (canceled)2. A bonding method comprising: depositing a first film on the first element,', 'introducing fluorine into the first film,', 'polishing the first film,', 'depositing a second film directly on the first film to define an interface between the first film and the second film,', 'introducing fluorine into the second film, and', 'polishing the second film;, 'forming a first bonding layer on a first element, wherein forming the first bonding layer comprisesforming a second bonding layer on a second element;bringing into contact a surface of the second film with a surface of the second bonding layer at about room temperature; andforming a direct bond between the second film and the second bonding layer without an intervening adhesive.3. The method of claim 2 , wherein forming the first bonding layer comprises depositing the first film and subsequently introducing fluorine into the first film; and depositing the second film and subsequently introducing fluorine into the second film.4. The method of claim 3 , wherein introducing fluorine into the first film comprises ...

METHOD OF ROOM TEMPERATURE COVALENT BONDING

A method of bonding includes using a bonding layer having a fluorinated oxide. Fluorine may be introduced into the bonding layer by exposure to a fluorine-containing solution, vapor or gas or by implantation. The bonding layer may also be formed using a method where fluorine is introduced into the layer during its formation. The surface of the bonding layer is terminated with a desired species, preferably an NHspecies. This may be accomplished by exposing the bonding layer to an NHOH solution. High bonding strength is obtained at room temperature. The method may also include bonding two bonding layers together and creating a fluorine distribution having a peak in the vicinity of the interface between the bonding layers. One of the bonding layers may include two oxide layers formed on each other. The fluorine concentration may also have a second peak at the interface between the two oxide layers. 1. (canceled)2. A bonded structure comprising:a first element;a first bonding layer disposed on the first element, the first bonding layer comprising a first film and a second film formed directly on the first film, wherein each of the first and the second films is planarized and includes fluorine;a second element; anda second bonding layer disposed on the second element,wherein the second film and the second bonding layer are directly bonded to one another without an intervening adhesive.3. The bonded structure of claim 2 , further comprising a fluorine concentration within the first bonding layer having a first peak in the vicinity of a bonding interface between the first and second bonding layers and a second peak in the vicinity of an internal interface between the first and second films.4. The bonded structure of claim 2 , wherein the second bonding layer comprises a third film on the second element and a fourth film on the third film.5. The bonded structure of claim 2 , wherein the second film is disposed directly on the first film without intervening layers.6. The ...

SEMICONDUCTOR PACKAGE INCLUDING A SEMICONDUCTOR DIE HAVING REDISTRIBUTED PADS

A semiconductor package that includes a semiconductor die, an insulation around the die, and a conforming conductive pad coupled to an electrode of the die. 1. A semiconductor package , comprising:a semiconductor die including at least one electrode disposed on one major surface thereof, said electrode having a first area;an insulation body disposed around said semiconductor die;a conforming conductive pad being coupled to said at least one electrode and extending over and conforming to a portion of said insulation body; anda passivation body disposed over said conforming conductive pad, said passivation body including at least one opening over said conforming conductive pad such that an exposed portion of said conforming conductive pad is exposed by said opening, wherein said exposed portion has a second area that is larger than said first area of said electrode.2. The package of claim 1 , wherein said conforming conductive pad includes a solderable surface.3. (canceled)4. The package of claim 1 , wherein said passivation body includes solder resist characteristics.5. The package of claim 1 , further comprising a conductive clip having a web portion coupled to another major surface of said semiconductor die opposite said one major surface.6. The package of claim 5 , wherein said clip includes at least one lead extending from an edge of said web portion and including a connection surface generally coplanar with said conforming conductive pad.7. The package of claim 6 , wherein said web portion is coupled to said another major surface by a conductive adhesive body.8. The package of claim 7 , wherein said conductive adhesive body is comprised of solder or a conductive epoxy.9. The package of claim 1 , further comprising a conductive plate coupled to another major surface of said semiconductor die opposite said one major surface.10. The package of claim 9 , wherein said conductive plate is coupled to said another major surface with a conductive adhesive body.11. The ...

3d semiconductor memory device and structure

A 3D semiconductor memory, the memory including: a first level including first memory cells, first transistors, and a first control line, where the first memory cells each include one of the first transistors; a second level including second memory cells, second transistors, and a second control line, where the second memory cells each include one of the second transistors, where the second level overlays the first level, where the second control line and the first control line have been processed following the same lithography step and accordingly are self-aligned, where the first control line is directly connected to each source or drain of at least five of the first transistors, and where the second control line is directly connected to each source or drain of at least five of the second transistors; and an oxide layer disposed between the first control line and the second control line.

MICROELECTRONIC DEVICES, STACKED MICROELECTRONIC DEVICES, AND METHODS FOR MANUFACTURING MICROELECTRONIC DEVICES

Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices are described herein. In one embodiment, a set of stacked microelectronic devices includes (a) a first microelectronic die having a first side and a second side opposite the first side, (b) a first substrate attached to the first side of the first microelectronic die and electrically coupled to the first microelectronic die, (c) a second substrate attached to the second side of the first microelectronic die, (d) a plurality of electrical couplers attached to the second substrate, (e) a third substrate coupled to the electrical couplers, and (f) a second microelectronic die attached to the third substrate. The electrical couplers are positioned such that at least some of the electrical couplers are inboard the first microelectronic die. 1. A microelectronic device , comprising:a first interposer substrate;a microelectronic die carried on the first interposer substrate and electrically coupled to the first interposer substrate;a standoff disposed over the microelectronic die;a second interposer substrate disposed over the standoff and electrically coupled to the first interposer substrate; anda casing at least partially encapsulating the microelectronic die, the standoff, and the second interposer substrate.2. The microelectronic device of claim 1 , wherein the microelectronic die is electrically coupled to the first interposer substrate by a first plurality of wirebonds.3. The microelectronic device of claim 2 , wherein the second interposer substrate is electrically coupled to the first interposer substrate by a second plurality of wirebonds.4. The microelectronic device of claim 3 , wherein the casing further at least partially encapsulates the first and second pluralities of wirebonds.5. The microelectronic device of claim 1 , wherein the first interposer substrate includes a perimeter array of bond-pads on an upper side thereof claim 1 , and wherein the ...

Light emitting device

A light emitting device includes a first metal plate, a second metal plate, and light emitting elements between the metal plates. The device further includes a wavelength conversion member excited by a first light from the light emitting elements to emit a second light having a wavelength different from the first light, a bulb including a base, a first lead connected to the first metal plate, and a second lead connected to the second metal plate. The base of the bulb includes terminals connected to respective leads. The conversion member covers the light emitting elements entirely, opposite surfaces of the first metal plate partially, and opposite surfaces of the second metal plate partially. The first lead is connected to a portion of the first metal plate exposed from the conversion member, and the second lead is connected to a portion of the second metal plate exposed from the conversion member.

Method for connecting a flexible substrate to a chip

The invention concerns a process for thermally bonding contact elements (14, 15) of a flexible film substrate (10) to metallized contact areas (17) of an electronic component (12). The flexible substrate comprises a carrier layer (13) of transparent plastics. The rear of the contact elements is acted on by energy in the form of laser radiation (11). The transparency of the carrier layer (13), the absorption of the contact elements (14, 15) and the wavelength of the laser radiation (11) are adapted to one another such that the laser radiation is substantially guided through the carrier layer (13) and absorbed in the contact elements (14, 15). Pressure acts on the substrate (10) such that the contact elements (14, 15) of the substrate (10) and the metallized contact areas (17) of the component (12) abut one another in the region of the optical fibre orientation point during the action of the laser radiation (11).

Light-emitting apparatus

A light-emitting apparatus includes a light-emitting device, a metal package consisting of a concave portion for containing the light-emitting device and a base portion having at least one through hole, and a lead electrode inserted into the through hole via an insulation member. The lead electrode has a bottom protruding from a bottom of the base portion and substantially on the same plane as the bottom of the concave portion. Furthermore, the base portion has a film thickness larger than the bottom thickness of the concave portion. This enables the light-emitting apparatus to obtain a high heat radiation and a high mechanical strength.